ae1e042498
When WLAN is attached to PCIe switch, set and retrain DSP <-> EP link in BW scale callback function. It avoids touching RC <-> USP link which may impact other devices. With this change, it could support Hamilton PCIe Gen3 on PCIe switch platform. Change-Id: Id444ac847613971545bf66db9bb1a6e427028802 CRs-Fixed: 3848272
254 行
7.4 KiB
C
254 行
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
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#ifndef _CNSS_PCI_PLATFORM_H
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#define _CNSS_PCI_PLATFORM_H
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#include "pci.h"
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#if IS_ENABLED(CONFIG_PCI_MSM)
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/**
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* _cnss_pci_enumerate() - Enumerate PCIe endpoints
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* @plat_priv: driver platform context pointer
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* @rc_num: root complex index that an endpoint connects to
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to power on root complex and enumerate the endpoint connected to it.
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*
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* Return: 0 for success, negative value for error
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*/
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int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num);
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/**
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* cnss_pci_assert_perst() - Assert PCIe PERST GPIO
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to assert PCIe PERST GPIO.
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*
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* Return: 0 for success, negative value for error
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*/
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int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv);
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/**
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* cnss_pci_disable_pc() - Disable PCIe link power collapse from RC driver
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* @pci_priv: driver PCI bus context pointer
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* @vote: value to indicate disable (true) or enable (false)
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to disable PCIe power collapse. The purpose of this API is to avoid
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* root complex driver still controlling PCIe link from callbacks of
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* system suspend/resume. Device driver itself should take full control
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* of the link in such cases.
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*
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* Return: 0 for success, negative value for error
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*/
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int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote);
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/**
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* cnss_pci_set_link_bandwidth() - Update number of lanes and speed of
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* PCIe link
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* @pci_priv: driver PCI bus context pointer
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* @link_speed: PCIe link gen speed
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* @link_width: number of lanes for PCIe link
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to update number of lanes and speed of the link.
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*
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* Return: 0 for success, negative value for error
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*/
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int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
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u16 link_speed, u16 link_width);
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/**
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* cnss_pci_set_max_link_speed() - Set the maximum speed PCIe can link up with
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* @pci_priv: driver PCI bus context pointer
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* @rc_num: root complex index that an endpoint connects to
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* @link_speed: PCIe link gen speed
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to update the maximum speed that PCIe can link up with.
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*
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* Return: 0 for success, negative value for error
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*/
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int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
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u32 rc_num, u16 link_speed);
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/**
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* cnss_reg_pci_event() - Register for PCIe events
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to register for PCIe events like link down or WAKE GPIO toggling etc.
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* The events should be based on PCIe root complex driver's capability.
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*
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* Return: 0 for success, negative value for error
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*/
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int cnss_reg_pci_event(struct cnss_pci_data *pci_priv);
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void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv);
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/**
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* cnss_wlan_adsp_pc_enable: Control ADSP power collapse setup
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* @dev: Platform driver pci private data structure
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* @control: Power collapse enable / disable
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*
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* This function controls ADSP power collapse (PC). It must be called
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* based on wlan state. ADSP power collapse during wlan RTPM suspend state
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* results in delay during periodic QMI stats PCI link up/down. This delay
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* causes additional power consumption.
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*
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* Result: 0 Success. negative error codes.
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*/
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int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
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bool control);
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int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up);
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int cnss_pci_prevent_l1(struct device *dev);
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void cnss_pci_allow_l1(struct device *dev);
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int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv);
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int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv);
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bool cnss_pci_fallback_one_msi(struct cnss_pci_data *pci_priv,
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int *num_vectors);
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bool cnss_pci_is_one_msi(struct cnss_pci_data *pci_priv);
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int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv);
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bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv);
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int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv);
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void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv);
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int cnss_pci_dsp_link_control(struct cnss_pci_data *pci_priv,
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bool link_enable);
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/**
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* _cnss_pci_get_reg_dump() - Dump PCIe RC registers for debug
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* @pci_priv: driver PCI bus context pointer
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* @buf: destination buffer pointer
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* @len: length of the buffer
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*
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* This function shall call corresponding PCIe root complex driver API
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* to dump PCIe RC registers for debug purpose.
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*
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* Return: 0 for success, negative value for error
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*/
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int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
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u8 *buf, u32 len);
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int cnss_pci_set_dsp_link_status(struct cnss_pci_data *pci_priv,
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bool link_enable);
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int cnss_pci_get_dsp_link_status(struct cnss_pci_data *pci_priv);
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int cnss_pci_dsp_link_enable(struct cnss_pci_data *pci_priv);
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int cnss_pci_dsp_link_retrain(struct cnss_pci_data *pci_priv,
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u16 target_link_speed);
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#else
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int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote)
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{
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return 0;
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}
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int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
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u16 link_speed, u16 link_width)
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{
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return 0;
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}
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int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
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u32 rc_num, u16 link_speed)
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{
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return 0;
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}
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int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv) {}
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int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv, bool control)
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{
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return 0;
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}
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int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up)
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{
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return 0;
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}
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int cnss_pci_prevent_l1(struct device *dev)
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{
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return 0;
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}
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EXPORT_SYMBOL(cnss_pci_prevent_l1);
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void cnss_pci_allow_l1(struct device *dev)
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{
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}
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EXPORT_SYMBOL(cnss_pci_allow_l1);
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int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
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u8 *buf, u32 len)
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{
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return 0;
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}
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void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv)
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{
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pci_priv->drv_supported = false;
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}
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int cnss_pci_dsp_link_control(struct cnss_pci_data *pci_priv,
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bool link_enable)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_set_dsp_link_status(struct cnss_pci_data *pci_priv,
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bool link_enable)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_get_dsp_link_status(struct cnss_pci_data *pci_priv)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_dsp_link_enable(struct cnss_pci_data *pci_priv)
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{
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return -EOPNOTSUPP;
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}
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int cnss_pci_dsp_link_retrain(struct cnss_pci_data *pci_priv,
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u16 target_link_speed)
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{
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return -EOPNOTSUPP;
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}
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#endif /* CONFIG_PCI_MSM */
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static inline bool cnss_pci_get_drv_supported(struct cnss_pci_data *pci_priv)
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{
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return pci_priv->drv_supported;
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}
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#if IS_ENABLED(CONFIG_ARCH_QCOM)
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int cnss_pci_of_reserved_mem_device_init(struct cnss_pci_data *pci_priv);
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int cnss_pci_wake_gpio_init(struct cnss_pci_data *pci_priv);
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void cnss_pci_wake_gpio_deinit(struct cnss_pci_data *pci_priv);
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#endif /* CONFIG_ARCH_QCOM */
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#endif /* _CNSS_PCI_PLATFORM_H*/
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