dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include "qdf_module.h"
  30. #include <wlan_cfg.h>
  31. #include "dp_ipa.h"
  32. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "enet.h"
  36. #include "dp_internal.h"
  37. #ifdef ATH_SUPPORT_IQUE
  38. #include "dp_txrx_me.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  42. #include <dp_swlm.h>
  43. #endif
  44. #ifdef WIFI_MONITOR_SUPPORT
  45. #include <dp_mon.h>
  46. #endif
  47. #ifdef FEATURE_WDS
  48. #include "dp_txrx_wds.h"
  49. #endif
  50. /* Flag to skip CCE classify when mesh or tid override enabled */
  51. #define DP_TX_SKIP_CCE_CLASSIFY \
  52. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  53. /* TODO Add support in TSO */
  54. #define DP_DESC_NUM_FRAG(x) 0
  55. /* disable TQM_BYPASS */
  56. #define TQM_BYPASS_WAR 0
  57. /* invalid peer id for reinject*/
  58. #define DP_INVALID_PEER 0XFFFE
  59. /*mapping between hal encrypt type and cdp_sec_type*/
  60. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  61. HAL_TX_ENCRYPT_TYPE_WEP_128,
  62. HAL_TX_ENCRYPT_TYPE_WEP_104,
  63. HAL_TX_ENCRYPT_TYPE_WEP_40,
  64. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  65. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  67. HAL_TX_ENCRYPT_TYPE_WAPI,
  68. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  70. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  71. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  72. qdf_export_symbol(sec_type_map);
  73. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  74. /**
  75. * dp_update_tx_desc_stats - Update the increase or decrease in
  76. * outstanding tx desc count
  77. * values on pdev and soc
  78. * @vdev: DP pdev handle
  79. *
  80. * Return: void
  81. */
  82. static inline void
  83. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  84. {
  85. int32_t tx_descs_cnt =
  86. qdf_atomic_read(&pdev->num_tx_outstanding);
  87. if (pdev->tx_descs_max < tx_descs_cnt)
  88. pdev->tx_descs_max = tx_descs_cnt;
  89. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  90. pdev->tx_descs_max);
  91. }
  92. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  93. static inline void
  94. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  95. {
  96. }
  97. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  98. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  99. static inline
  100. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  101. {
  102. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  103. QDF_DMA_TO_DEVICE,
  104. desc->nbuf->len);
  105. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  106. }
  107. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  108. {
  109. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  110. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  111. QDF_DMA_TO_DEVICE,
  112. desc->nbuf->len);
  113. }
  114. #else
  115. static inline
  116. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  117. {
  118. }
  119. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  120. {
  121. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  122. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  123. }
  124. #endif
  125. #ifdef QCA_TX_LIMIT_CHECK
  126. /**
  127. * dp_tx_limit_check - Check if allocated tx descriptors reached
  128. * soc max limit and pdev max limit
  129. * @vdev: DP vdev handle
  130. *
  131. * Return: true if allocated tx descriptors reached max configured value, else
  132. * false
  133. */
  134. static inline bool
  135. dp_tx_limit_check(struct dp_vdev *vdev)
  136. {
  137. struct dp_pdev *pdev = vdev->pdev;
  138. struct dp_soc *soc = pdev->soc;
  139. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  140. soc->num_tx_allowed) {
  141. dp_tx_info("queued packets are more than max tx, drop the frame");
  142. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  143. return true;
  144. }
  145. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  146. pdev->num_tx_allowed) {
  147. dp_tx_info("queued packets are more than max tx, drop the frame");
  148. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  149. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  150. return true;
  151. }
  152. return false;
  153. }
  154. /**
  155. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  156. * reached soc max limit
  157. * @vdev: DP vdev handle
  158. *
  159. * Return: true if allocated tx descriptors reached max configured value, else
  160. * false
  161. */
  162. static inline bool
  163. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  164. {
  165. struct dp_pdev *pdev = vdev->pdev;
  166. struct dp_soc *soc = pdev->soc;
  167. if (qdf_atomic_read(&soc->num_tx_exception) >=
  168. soc->num_msdu_exception_desc) {
  169. dp_info("exc packets are more than max drop the exc pkt");
  170. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  171. return true;
  172. }
  173. return false;
  174. }
  175. /**
  176. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  177. * @vdev: DP pdev handle
  178. *
  179. * Return: void
  180. */
  181. static inline void
  182. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  183. {
  184. struct dp_soc *soc = pdev->soc;
  185. qdf_atomic_inc(&pdev->num_tx_outstanding);
  186. qdf_atomic_inc(&soc->num_tx_outstanding);
  187. dp_update_tx_desc_stats(pdev);
  188. }
  189. /**
  190. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. qdf_atomic_dec(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. #else //QCA_TX_LIMIT_CHECK
  204. static inline bool
  205. dp_tx_limit_check(struct dp_vdev *vdev)
  206. {
  207. return false;
  208. }
  209. static inline bool
  210. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  211. {
  212. return false;
  213. }
  214. static inline void
  215. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  216. {
  217. qdf_atomic_inc(&pdev->num_tx_outstanding);
  218. dp_update_tx_desc_stats(pdev);
  219. }
  220. static inline void
  221. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  222. {
  223. qdf_atomic_dec(&pdev->num_tx_outstanding);
  224. dp_update_tx_desc_stats(pdev);
  225. }
  226. #endif //QCA_TX_LIMIT_CHECK
  227. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  228. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  229. {
  230. enum dp_tx_event_type type;
  231. if (flags & DP_TX_DESC_FLAG_FLUSH)
  232. type = DP_TX_DESC_FLUSH;
  233. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  234. type = DP_TX_COMP_UNMAP_ERR;
  235. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  236. type = DP_TX_COMP_UNMAP;
  237. else
  238. type = DP_TX_DESC_UNMAP;
  239. return type;
  240. }
  241. static inline void
  242. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  243. qdf_nbuf_t skb, uint32_t sw_cookie,
  244. enum dp_tx_event_type type)
  245. {
  246. struct dp_tx_desc_event *entry;
  247. uint32_t idx;
  248. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  249. return;
  250. switch (type) {
  251. case DP_TX_COMP_UNMAP:
  252. case DP_TX_COMP_UNMAP_ERR:
  253. case DP_TX_COMP_MSDU_EXT:
  254. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  255. DP_TX_COMP_HISTORY_SIZE);
  256. entry = &soc->tx_comp_history->entry[idx];
  257. break;
  258. case DP_TX_DESC_MAP:
  259. case DP_TX_DESC_UNMAP:
  260. case DP_TX_DESC_COOKIE:
  261. case DP_TX_DESC_FLUSH:
  262. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  263. DP_TX_TCL_HISTORY_SIZE);
  264. entry = &soc->tx_tcl_history->entry[idx];
  265. break;
  266. default:
  267. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  268. return;
  269. }
  270. entry->skb = skb;
  271. entry->paddr = paddr;
  272. entry->sw_cookie = sw_cookie;
  273. entry->type = type;
  274. entry->ts = qdf_get_log_timestamp();
  275. }
  276. static inline void
  277. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  278. struct qdf_tso_seg_elem_t *tso_seg,
  279. qdf_nbuf_t skb, uint32_t sw_cookie,
  280. enum dp_tx_event_type type)
  281. {
  282. int i;
  283. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  284. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  285. skb, sw_cookie, type);
  286. }
  287. if (!tso_seg->next)
  288. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  289. skb, 0xFFFFFFFF, type);
  290. }
  291. static inline void
  292. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  297. uint32_t num_segs = tso_info.num_segs;
  298. while (num_segs) {
  299. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  300. curr_seg = curr_seg->next;
  301. num_segs--;
  302. }
  303. }
  304. #else
  305. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  306. {
  307. return DP_TX_DESC_INVAL_EVT;
  308. }
  309. static inline void
  310. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  311. qdf_nbuf_t skb, uint32_t sw_cookie,
  312. enum dp_tx_event_type type)
  313. {
  314. }
  315. static inline void
  316. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *tso_seg,
  318. qdf_nbuf_t skb, uint32_t sw_cookie,
  319. enum dp_tx_event_type type)
  320. {
  321. }
  322. static inline void
  323. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  324. qdf_nbuf_t skb, uint32_t sw_cookie,
  325. enum dp_tx_event_type type)
  326. {
  327. }
  328. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  329. #if defined(FEATURE_TSO)
  330. /**
  331. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  332. *
  333. * @soc - core txrx main context
  334. * @seg_desc - tso segment descriptor
  335. * @num_seg_desc - tso number segment descriptor
  336. */
  337. static void dp_tx_tso_unmap_segment(
  338. struct dp_soc *soc,
  339. struct qdf_tso_seg_elem_t *seg_desc,
  340. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  341. {
  342. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  343. if (qdf_unlikely(!seg_desc)) {
  344. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  345. __func__, __LINE__);
  346. qdf_assert(0);
  347. } else if (qdf_unlikely(!num_seg_desc)) {
  348. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  349. __func__, __LINE__);
  350. qdf_assert(0);
  351. } else {
  352. bool is_last_seg;
  353. /* no tso segment left to do dma unmap */
  354. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  355. return;
  356. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  357. true : false;
  358. qdf_nbuf_unmap_tso_segment(soc->osdev,
  359. seg_desc, is_last_seg);
  360. num_seg_desc->num_seg.tso_cmn_num_seg--;
  361. }
  362. }
  363. /**
  364. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  365. * back to the freelist
  366. *
  367. * @soc - soc device handle
  368. * @tx_desc - Tx software descriptor
  369. */
  370. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  371. struct dp_tx_desc_s *tx_desc)
  372. {
  373. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  374. if (qdf_unlikely(!tx_desc->tso_desc)) {
  375. dp_tx_err("SO desc is NULL!");
  376. qdf_assert(0);
  377. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  378. dp_tx_err("TSO num desc is NULL!");
  379. qdf_assert(0);
  380. } else {
  381. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  382. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  383. /* Add the tso num segment into the free list */
  384. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  385. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  386. tx_desc->tso_num_desc);
  387. tx_desc->tso_num_desc = NULL;
  388. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  389. }
  390. /* Add the tso segment into the free list*/
  391. dp_tx_tso_desc_free(soc,
  392. tx_desc->pool_id, tx_desc->tso_desc);
  393. tx_desc->tso_desc = NULL;
  394. }
  395. }
  396. #else
  397. static void dp_tx_tso_unmap_segment(
  398. struct dp_soc *soc,
  399. struct qdf_tso_seg_elem_t *seg_desc,
  400. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  401. {
  402. }
  403. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  404. struct dp_tx_desc_s *tx_desc)
  405. {
  406. }
  407. #endif
  408. /**
  409. * dp_tx_desc_release() - Release Tx Descriptor
  410. * @tx_desc : Tx Descriptor
  411. * @desc_pool_id: Descriptor Pool ID
  412. *
  413. * Deallocate all resources attached to Tx descriptor and free the Tx
  414. * descriptor.
  415. *
  416. * Return:
  417. */
  418. static void
  419. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  420. {
  421. struct dp_pdev *pdev = tx_desc->pdev;
  422. struct dp_soc *soc;
  423. uint8_t comp_status = 0;
  424. qdf_assert(pdev);
  425. soc = pdev->soc;
  426. dp_tx_outstanding_dec(pdev);
  427. if (tx_desc->frm_type == dp_tx_frm_tso)
  428. dp_tx_tso_desc_release(soc, tx_desc);
  429. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  430. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  431. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  432. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  433. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  434. qdf_atomic_dec(&soc->num_tx_exception);
  435. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  436. tx_desc->buffer_src)
  437. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  438. soc->hal_soc);
  439. else
  440. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  441. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  442. tx_desc->id, comp_status,
  443. qdf_atomic_read(&pdev->num_tx_outstanding));
  444. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  445. return;
  446. }
  447. /**
  448. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  449. * @vdev: DP vdev Handle
  450. * @nbuf: skb
  451. * @msdu_info: msdu_info required to create HTT metadata
  452. *
  453. * Prepares and fills HTT metadata in the frame pre-header for special frames
  454. * that should be transmitted using varying transmit parameters.
  455. * There are 2 VDEV modes that currently needs this special metadata -
  456. * 1) Mesh Mode
  457. * 2) DSRC Mode
  458. *
  459. * Return: HTT metadata size
  460. *
  461. */
  462. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  463. struct dp_tx_msdu_info_s *msdu_info)
  464. {
  465. uint32_t *meta_data = msdu_info->meta_data;
  466. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  467. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  468. uint8_t htt_desc_size;
  469. /* Size rounded of multiple of 8 bytes */
  470. uint8_t htt_desc_size_aligned;
  471. uint8_t *hdr = NULL;
  472. /*
  473. * Metadata - HTT MSDU Extension header
  474. */
  475. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  476. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  477. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  478. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  479. meta_data[0])) {
  480. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  481. htt_desc_size_aligned)) {
  482. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  483. htt_desc_size_aligned);
  484. if (!nbuf) {
  485. /*
  486. * qdf_nbuf_realloc_headroom won't do skb_clone
  487. * as skb_realloc_headroom does. so, no free is
  488. * needed here.
  489. */
  490. DP_STATS_INC(vdev,
  491. tx_i.dropped.headroom_insufficient,
  492. 1);
  493. qdf_print(" %s[%d] skb_realloc_headroom failed",
  494. __func__, __LINE__);
  495. return 0;
  496. }
  497. }
  498. /* Fill and add HTT metaheader */
  499. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  500. if (!hdr) {
  501. dp_tx_err("Error in filling HTT metadata");
  502. return 0;
  503. }
  504. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  505. } else if (vdev->opmode == wlan_op_mode_ocb) {
  506. /* Todo - Add support for DSRC */
  507. }
  508. return htt_desc_size_aligned;
  509. }
  510. /**
  511. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  512. * @tso_seg: TSO segment to process
  513. * @ext_desc: Pointer to MSDU extension descriptor
  514. *
  515. * Return: void
  516. */
  517. #if defined(FEATURE_TSO)
  518. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  519. void *ext_desc)
  520. {
  521. uint8_t num_frag;
  522. uint32_t tso_flags;
  523. /*
  524. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  525. * tcp_flag_mask
  526. *
  527. * Checksum enable flags are set in TCL descriptor and not in Extension
  528. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  529. */
  530. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  531. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  532. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  533. tso_seg->tso_flags.ip_len);
  534. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  535. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  536. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  537. uint32_t lo = 0;
  538. uint32_t hi = 0;
  539. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  540. (tso_seg->tso_frags[num_frag].length));
  541. qdf_dmaaddr_to_32s(
  542. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  543. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  544. tso_seg->tso_frags[num_frag].length);
  545. }
  546. return;
  547. }
  548. #else
  549. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  550. void *ext_desc)
  551. {
  552. return;
  553. }
  554. #endif
  555. #if defined(FEATURE_TSO)
  556. /**
  557. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  558. * allocated and free them
  559. *
  560. * @soc: soc handle
  561. * @free_seg: list of tso segments
  562. * @msdu_info: msdu descriptor
  563. *
  564. * Return - void
  565. */
  566. static void dp_tx_free_tso_seg_list(
  567. struct dp_soc *soc,
  568. struct qdf_tso_seg_elem_t *free_seg,
  569. struct dp_tx_msdu_info_s *msdu_info)
  570. {
  571. struct qdf_tso_seg_elem_t *next_seg;
  572. while (free_seg) {
  573. next_seg = free_seg->next;
  574. dp_tx_tso_desc_free(soc,
  575. msdu_info->tx_queue.desc_pool_id,
  576. free_seg);
  577. free_seg = next_seg;
  578. }
  579. }
  580. /**
  581. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  582. * allocated and free them
  583. *
  584. * @soc: soc handle
  585. * @free_num_seg: list of tso number segments
  586. * @msdu_info: msdu descriptor
  587. * Return - void
  588. */
  589. static void dp_tx_free_tso_num_seg_list(
  590. struct dp_soc *soc,
  591. struct qdf_tso_num_seg_elem_t *free_num_seg,
  592. struct dp_tx_msdu_info_s *msdu_info)
  593. {
  594. struct qdf_tso_num_seg_elem_t *next_num_seg;
  595. while (free_num_seg) {
  596. next_num_seg = free_num_seg->next;
  597. dp_tso_num_seg_free(soc,
  598. msdu_info->tx_queue.desc_pool_id,
  599. free_num_seg);
  600. free_num_seg = next_num_seg;
  601. }
  602. }
  603. /**
  604. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  605. * do dma unmap for each segment
  606. *
  607. * @soc: soc handle
  608. * @free_seg: list of tso segments
  609. * @num_seg_desc: tso number segment descriptor
  610. *
  611. * Return - void
  612. */
  613. static void dp_tx_unmap_tso_seg_list(
  614. struct dp_soc *soc,
  615. struct qdf_tso_seg_elem_t *free_seg,
  616. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  617. {
  618. struct qdf_tso_seg_elem_t *next_seg;
  619. if (qdf_unlikely(!num_seg_desc)) {
  620. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  621. return;
  622. }
  623. while (free_seg) {
  624. next_seg = free_seg->next;
  625. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  626. free_seg = next_seg;
  627. }
  628. }
  629. #ifdef FEATURE_TSO_STATS
  630. /**
  631. * dp_tso_get_stats_idx: Retrieve the tso packet id
  632. * @pdev - pdev handle
  633. *
  634. * Return: id
  635. */
  636. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  637. {
  638. uint32_t stats_idx;
  639. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  640. % CDP_MAX_TSO_PACKETS);
  641. return stats_idx;
  642. }
  643. #else
  644. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  645. {
  646. return 0;
  647. }
  648. #endif /* FEATURE_TSO_STATS */
  649. /**
  650. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  651. * free the tso segments descriptor and
  652. * tso num segments descriptor
  653. *
  654. * @soc: soc handle
  655. * @msdu_info: msdu descriptor
  656. * @tso_seg_unmap: flag to show if dma unmap is necessary
  657. *
  658. * Return - void
  659. */
  660. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  661. struct dp_tx_msdu_info_s *msdu_info,
  662. bool tso_seg_unmap)
  663. {
  664. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  665. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  666. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  667. tso_info->tso_num_seg_list;
  668. /* do dma unmap for each segment */
  669. if (tso_seg_unmap)
  670. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  671. /* free all tso number segment descriptor though looks only have 1 */
  672. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  673. /* free all tso segment descriptor */
  674. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  675. }
  676. /**
  677. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  678. * @vdev: virtual device handle
  679. * @msdu: network buffer
  680. * @msdu_info: meta data associated with the msdu
  681. *
  682. * Return: QDF_STATUS_SUCCESS success
  683. */
  684. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  685. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  686. {
  687. struct qdf_tso_seg_elem_t *tso_seg;
  688. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  689. struct dp_soc *soc = vdev->pdev->soc;
  690. struct dp_pdev *pdev = vdev->pdev;
  691. struct qdf_tso_info_t *tso_info;
  692. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  693. tso_info = &msdu_info->u.tso_info;
  694. tso_info->curr_seg = NULL;
  695. tso_info->tso_seg_list = NULL;
  696. tso_info->num_segs = num_seg;
  697. msdu_info->frm_type = dp_tx_frm_tso;
  698. tso_info->tso_num_seg_list = NULL;
  699. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  700. while (num_seg) {
  701. tso_seg = dp_tx_tso_desc_alloc(
  702. soc, msdu_info->tx_queue.desc_pool_id);
  703. if (tso_seg) {
  704. tso_seg->next = tso_info->tso_seg_list;
  705. tso_info->tso_seg_list = tso_seg;
  706. num_seg--;
  707. } else {
  708. dp_err_rl("Failed to alloc tso seg desc");
  709. DP_STATS_INC_PKT(vdev->pdev,
  710. tso_stats.tso_no_mem_dropped, 1,
  711. qdf_nbuf_len(msdu));
  712. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  713. return QDF_STATUS_E_NOMEM;
  714. }
  715. }
  716. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  717. tso_num_seg = dp_tso_num_seg_alloc(soc,
  718. msdu_info->tx_queue.desc_pool_id);
  719. if (tso_num_seg) {
  720. tso_num_seg->next = tso_info->tso_num_seg_list;
  721. tso_info->tso_num_seg_list = tso_num_seg;
  722. } else {
  723. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  724. __func__);
  725. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  726. return QDF_STATUS_E_NOMEM;
  727. }
  728. msdu_info->num_seg =
  729. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  730. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  731. msdu_info->num_seg);
  732. if (!(msdu_info->num_seg)) {
  733. /*
  734. * Free allocated TSO seg desc and number seg desc,
  735. * do unmap for segments if dma map has done.
  736. */
  737. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  738. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  739. return QDF_STATUS_E_INVAL;
  740. }
  741. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  742. msdu, 0, DP_TX_DESC_MAP);
  743. tso_info->curr_seg = tso_info->tso_seg_list;
  744. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  745. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  746. msdu, msdu_info->num_seg);
  747. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  748. tso_info->msdu_stats_idx);
  749. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  750. return QDF_STATUS_SUCCESS;
  751. }
  752. #else
  753. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  754. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  755. {
  756. return QDF_STATUS_E_NOMEM;
  757. }
  758. #endif
  759. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  760. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  761. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  762. /**
  763. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  764. * @vdev: DP Vdev handle
  765. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  766. * @desc_pool_id: Descriptor Pool ID
  767. *
  768. * Return:
  769. */
  770. static
  771. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  772. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  773. {
  774. uint8_t i;
  775. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  776. struct dp_tx_seg_info_s *seg_info;
  777. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  778. struct dp_soc *soc = vdev->pdev->soc;
  779. /* Allocate an extension descriptor */
  780. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  781. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  782. if (!msdu_ext_desc) {
  783. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  784. return NULL;
  785. }
  786. if (msdu_info->exception_fw &&
  787. qdf_unlikely(vdev->mesh_vdev)) {
  788. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  789. &msdu_info->meta_data[0],
  790. sizeof(struct htt_tx_msdu_desc_ext2_t));
  791. qdf_atomic_inc(&soc->num_tx_exception);
  792. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  793. }
  794. switch (msdu_info->frm_type) {
  795. case dp_tx_frm_sg:
  796. case dp_tx_frm_me:
  797. case dp_tx_frm_raw:
  798. seg_info = msdu_info->u.sg_info.curr_seg;
  799. /* Update the buffer pointers in MSDU Extension Descriptor */
  800. for (i = 0; i < seg_info->frag_cnt; i++) {
  801. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  802. seg_info->frags[i].paddr_lo,
  803. seg_info->frags[i].paddr_hi,
  804. seg_info->frags[i].len);
  805. }
  806. break;
  807. case dp_tx_frm_tso:
  808. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  809. &cached_ext_desc[0]);
  810. break;
  811. default:
  812. break;
  813. }
  814. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  815. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  816. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  817. msdu_ext_desc->vaddr);
  818. return msdu_ext_desc;
  819. }
  820. /**
  821. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  822. *
  823. * @skb: skb to be traced
  824. * @msdu_id: msdu_id of the packet
  825. * @vdev_id: vdev_id of the packet
  826. *
  827. * Return: None
  828. */
  829. #ifdef DP_DISABLE_TX_PKT_TRACE
  830. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  831. uint8_t vdev_id)
  832. {
  833. }
  834. #else
  835. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  836. uint8_t vdev_id)
  837. {
  838. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  839. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  840. DPTRACE(qdf_dp_trace_ptr(skb,
  841. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  842. QDF_TRACE_DEFAULT_PDEV_ID,
  843. qdf_nbuf_data_addr(skb),
  844. sizeof(qdf_nbuf_data(skb)),
  845. msdu_id, vdev_id, 0));
  846. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  847. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  848. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  849. msdu_id, QDF_TX));
  850. }
  851. #endif
  852. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  853. /**
  854. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  855. * exception by the upper layer (OS_IF)
  856. * @soc: DP soc handle
  857. * @nbuf: packet to be transmitted
  858. *
  859. * Returns: 1 if the packet is marked as exception,
  860. * 0, if the packet is not marked as exception.
  861. */
  862. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  863. qdf_nbuf_t nbuf)
  864. {
  865. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  866. }
  867. #else
  868. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  869. qdf_nbuf_t nbuf)
  870. {
  871. return 0;
  872. }
  873. #endif
  874. /**
  875. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  876. * @vdev: DP vdev handle
  877. * @nbuf: skb
  878. * @desc_pool_id: Descriptor pool ID
  879. * @meta_data: Metadata to the fw
  880. * @tx_exc_metadata: Handle that holds exception path metadata
  881. * Allocate and prepare Tx descriptor with msdu information.
  882. *
  883. * Return: Pointer to Tx Descriptor on success,
  884. * NULL on failure
  885. */
  886. static
  887. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  888. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  889. struct dp_tx_msdu_info_s *msdu_info,
  890. struct cdp_tx_exception_metadata *tx_exc_metadata)
  891. {
  892. uint8_t align_pad;
  893. uint8_t is_exception = 0;
  894. uint8_t htt_hdr_size;
  895. struct dp_tx_desc_s *tx_desc;
  896. struct dp_pdev *pdev = vdev->pdev;
  897. struct dp_soc *soc = pdev->soc;
  898. if (dp_tx_limit_check(vdev))
  899. return NULL;
  900. /* Allocate software Tx descriptor */
  901. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  902. if (qdf_unlikely(!tx_desc)) {
  903. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  904. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  905. return NULL;
  906. }
  907. dp_tx_outstanding_inc(pdev);
  908. /* Initialize the SW tx descriptor */
  909. tx_desc->nbuf = nbuf;
  910. tx_desc->frm_type = dp_tx_frm_std;
  911. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  912. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  913. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  914. tx_desc->vdev_id = vdev->vdev_id;
  915. tx_desc->pdev = pdev;
  916. tx_desc->msdu_ext_desc = NULL;
  917. tx_desc->pkt_offset = 0;
  918. tx_desc->length = qdf_nbuf_headlen(nbuf);
  919. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  920. if (qdf_unlikely(vdev->multipass_en)) {
  921. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  922. goto failure;
  923. }
  924. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  925. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  926. is_exception = 1;
  927. /*
  928. * For special modes (vdev_type == ocb or mesh), data frames should be
  929. * transmitted using varying transmit parameters (tx spec) which include
  930. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  931. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  932. * These frames are sent as exception packets to firmware.
  933. *
  934. * HW requirement is that metadata should always point to a
  935. * 8-byte aligned address. So we add alignment pad to start of buffer.
  936. * HTT Metadata should be ensured to be multiple of 8-bytes,
  937. * to get 8-byte aligned start address along with align_pad added
  938. *
  939. * |-----------------------------|
  940. * | |
  941. * |-----------------------------| <-----Buffer Pointer Address given
  942. * | | ^ in HW descriptor (aligned)
  943. * | HTT Metadata | |
  944. * | | |
  945. * | | | Packet Offset given in descriptor
  946. * | | |
  947. * |-----------------------------| |
  948. * | Alignment Pad | v
  949. * |-----------------------------| <----- Actual buffer start address
  950. * | SKB Data | (Unaligned)
  951. * | |
  952. * | |
  953. * | |
  954. * | |
  955. * | |
  956. * |-----------------------------|
  957. */
  958. if (qdf_unlikely((msdu_info->exception_fw)) ||
  959. (vdev->opmode == wlan_op_mode_ocb) ||
  960. (tx_exc_metadata &&
  961. tx_exc_metadata->is_tx_sniffer)) {
  962. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  963. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  964. DP_STATS_INC(vdev,
  965. tx_i.dropped.headroom_insufficient, 1);
  966. goto failure;
  967. }
  968. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  969. dp_tx_err("qdf_nbuf_push_head failed");
  970. goto failure;
  971. }
  972. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  973. msdu_info);
  974. if (htt_hdr_size == 0)
  975. goto failure;
  976. tx_desc->length = qdf_nbuf_headlen(nbuf);
  977. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  978. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  979. is_exception = 1;
  980. tx_desc->length -= tx_desc->pkt_offset;
  981. }
  982. #if !TQM_BYPASS_WAR
  983. if (is_exception || tx_exc_metadata)
  984. #endif
  985. {
  986. /* Temporary WAR due to TQM VP issues */
  987. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  988. qdf_atomic_inc(&soc->num_tx_exception);
  989. }
  990. return tx_desc;
  991. failure:
  992. dp_tx_desc_release(tx_desc, desc_pool_id);
  993. return NULL;
  994. }
  995. /**
  996. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  997. * @vdev: DP vdev handle
  998. * @nbuf: skb
  999. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1000. * @desc_pool_id : Descriptor Pool ID
  1001. *
  1002. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1003. * information. For frames wth fragments, allocate and prepare
  1004. * an MSDU extension descriptor
  1005. *
  1006. * Return: Pointer to Tx Descriptor on success,
  1007. * NULL on failure
  1008. */
  1009. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1010. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1011. uint8_t desc_pool_id)
  1012. {
  1013. struct dp_tx_desc_s *tx_desc;
  1014. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1015. struct dp_pdev *pdev = vdev->pdev;
  1016. struct dp_soc *soc = pdev->soc;
  1017. if (dp_tx_limit_check(vdev))
  1018. return NULL;
  1019. /* Allocate software Tx descriptor */
  1020. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1021. if (!tx_desc) {
  1022. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1023. return NULL;
  1024. }
  1025. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1026. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1027. dp_tx_outstanding_inc(pdev);
  1028. /* Initialize the SW tx descriptor */
  1029. tx_desc->nbuf = nbuf;
  1030. tx_desc->frm_type = msdu_info->frm_type;
  1031. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1032. tx_desc->vdev_id = vdev->vdev_id;
  1033. tx_desc->pdev = pdev;
  1034. tx_desc->pkt_offset = 0;
  1035. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1036. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1037. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  1038. /* Handle scattered frames - TSO/SG/ME */
  1039. /* Allocate and prepare an extension descriptor for scattered frames */
  1040. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1041. if (!msdu_ext_desc) {
  1042. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1043. goto failure;
  1044. }
  1045. #if TQM_BYPASS_WAR
  1046. /* Temporary WAR due to TQM VP issues */
  1047. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1048. qdf_atomic_inc(&soc->num_tx_exception);
  1049. #endif
  1050. if (qdf_unlikely(msdu_info->exception_fw))
  1051. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1052. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1053. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1054. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1055. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1056. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1057. else
  1058. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1059. return tx_desc;
  1060. failure:
  1061. dp_tx_desc_release(tx_desc, desc_pool_id);
  1062. return NULL;
  1063. }
  1064. /**
  1065. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1066. * @vdev: DP vdev handle
  1067. * @nbuf: buffer pointer
  1068. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1069. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1070. * descriptor
  1071. *
  1072. * Return:
  1073. */
  1074. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1075. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1076. {
  1077. qdf_nbuf_t curr_nbuf = NULL;
  1078. uint16_t total_len = 0;
  1079. qdf_dma_addr_t paddr;
  1080. int32_t i;
  1081. int32_t mapped_buf_num = 0;
  1082. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1083. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1084. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1085. /* Continue only if frames are of DATA type */
  1086. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1087. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1088. dp_tx_debug("Pkt. recd is of not data type");
  1089. goto error;
  1090. }
  1091. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1092. if (vdev->raw_mode_war &&
  1093. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1094. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1095. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1096. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1097. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1098. /*
  1099. * Number of nbuf's must not exceed the size of the frags
  1100. * array in seg_info.
  1101. */
  1102. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1103. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1104. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1105. goto error;
  1106. }
  1107. if (QDF_STATUS_SUCCESS !=
  1108. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1109. curr_nbuf,
  1110. QDF_DMA_TO_DEVICE,
  1111. curr_nbuf->len)) {
  1112. dp_tx_err("%s dma map error ", __func__);
  1113. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1114. goto error;
  1115. }
  1116. /* Update the count of mapped nbuf's */
  1117. mapped_buf_num++;
  1118. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1119. seg_info->frags[i].paddr_lo = paddr;
  1120. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1121. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1122. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1123. total_len += qdf_nbuf_len(curr_nbuf);
  1124. }
  1125. seg_info->frag_cnt = i;
  1126. seg_info->total_len = total_len;
  1127. seg_info->next = NULL;
  1128. sg_info->curr_seg = seg_info;
  1129. msdu_info->frm_type = dp_tx_frm_raw;
  1130. msdu_info->num_seg = 1;
  1131. return nbuf;
  1132. error:
  1133. i = 0;
  1134. while (nbuf) {
  1135. curr_nbuf = nbuf;
  1136. if (i < mapped_buf_num) {
  1137. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1138. QDF_DMA_TO_DEVICE,
  1139. curr_nbuf->len);
  1140. i++;
  1141. }
  1142. nbuf = qdf_nbuf_next(nbuf);
  1143. qdf_nbuf_free(curr_nbuf);
  1144. }
  1145. return NULL;
  1146. }
  1147. /**
  1148. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1149. * @soc: DP soc handle
  1150. * @nbuf: Buffer pointer
  1151. *
  1152. * unmap the chain of nbufs that belong to this RAW frame.
  1153. *
  1154. * Return: None
  1155. */
  1156. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1157. qdf_nbuf_t nbuf)
  1158. {
  1159. qdf_nbuf_t cur_nbuf = nbuf;
  1160. do {
  1161. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1162. QDF_DMA_TO_DEVICE,
  1163. cur_nbuf->len);
  1164. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1165. } while (cur_nbuf);
  1166. }
  1167. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1168. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1169. qdf_nbuf_t nbuf)
  1170. {
  1171. qdf_nbuf_t nbuf_local;
  1172. struct dp_vdev *vdev_local = vdev_hdl;
  1173. do {
  1174. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1175. break;
  1176. nbuf_local = nbuf;
  1177. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1178. htt_cmn_pkt_type_raw))
  1179. break;
  1180. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1181. break;
  1182. else if (qdf_nbuf_is_tso((nbuf_local)))
  1183. break;
  1184. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1185. (nbuf_local),
  1186. NULL, 1, 0);
  1187. } while (0);
  1188. }
  1189. #endif
  1190. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1191. /**
  1192. * dp_tx_update_stats() - Update soc level tx stats
  1193. * @soc: DP soc handle
  1194. * @nbuf: packet being transmitted
  1195. *
  1196. * Returns: none
  1197. */
  1198. void dp_tx_update_stats(struct dp_soc *soc,
  1199. qdf_nbuf_t nbuf)
  1200. {
  1201. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1202. }
  1203. int
  1204. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1205. struct dp_tx_desc_s *tx_desc,
  1206. uint8_t tid)
  1207. {
  1208. struct dp_swlm *swlm = &soc->swlm;
  1209. union swlm_data swlm_query_data;
  1210. struct dp_swlm_tcl_data tcl_data;
  1211. QDF_STATUS status;
  1212. int ret;
  1213. if (qdf_unlikely(!swlm->is_enabled))
  1214. return 0;
  1215. tcl_data.nbuf = tx_desc->nbuf;
  1216. tcl_data.tid = tid;
  1217. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1218. swlm_query_data.tcl_data = &tcl_data;
  1219. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1220. if (QDF_IS_STATUS_ERROR(status)) {
  1221. dp_swlm_tcl_reset_session_data(soc);
  1222. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1223. return 0;
  1224. }
  1225. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1226. if (ret) {
  1227. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1228. } else {
  1229. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1230. }
  1231. return ret;
  1232. }
  1233. void
  1234. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1235. int coalesce)
  1236. {
  1237. if (coalesce)
  1238. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1239. else
  1240. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1241. }
  1242. #endif
  1243. #ifdef FEATURE_RUNTIME_PM
  1244. /**
  1245. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1246. * @soc: Datapath soc handle
  1247. * @hal_ring_hdl: HAL ring handle
  1248. * @coalesce: Coalesce the current write or not
  1249. *
  1250. * Wrapper for HAL ring access end for data transmission for
  1251. * FEATURE_RUNTIME_PM
  1252. *
  1253. * Returns: none
  1254. */
  1255. void
  1256. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1257. hal_ring_handle_t hal_ring_hdl,
  1258. int coalesce)
  1259. {
  1260. int ret;
  1261. ret = hif_pm_runtime_get(soc->hif_handle,
  1262. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1263. switch (ret) {
  1264. case 0:
  1265. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1266. hif_pm_runtime_put(soc->hif_handle,
  1267. RTPM_ID_DW_TX_HW_ENQUEUE);
  1268. break;
  1269. /*
  1270. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1271. * take the dp runtime refcount using dp_runtime_get,
  1272. * check link state,if up, write TX ring HP, else just set flush event.
  1273. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1274. * zero or time out, then flush pending tx.
  1275. */
  1276. case -EBUSY:
  1277. case -EINPROGRESS:
  1278. dp_runtime_get(soc);
  1279. if (hif_pm_get_link_state(soc->hif_handle) ==
  1280. HIF_PM_LINK_STATE_UP) {
  1281. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1282. } else {
  1283. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1284. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1285. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1286. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1287. }
  1288. dp_runtime_put(soc);
  1289. break;
  1290. default:
  1291. dp_runtime_get(soc);
  1292. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1293. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1294. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1295. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1296. dp_runtime_put(soc);
  1297. }
  1298. }
  1299. #endif
  1300. /**
  1301. * dp_cce_classify() - Classify the frame based on CCE rules
  1302. * @vdev: DP vdev handle
  1303. * @nbuf: skb
  1304. *
  1305. * Classify frames based on CCE rules
  1306. * Return: bool( true if classified,
  1307. * else false)
  1308. */
  1309. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1310. {
  1311. qdf_ether_header_t *eh = NULL;
  1312. uint16_t ether_type;
  1313. qdf_llc_t *llcHdr;
  1314. qdf_nbuf_t nbuf_clone = NULL;
  1315. qdf_dot3_qosframe_t *qos_wh = NULL;
  1316. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1317. /*
  1318. * In case of mesh packets or hlos tid override enabled,
  1319. * don't do any classification
  1320. */
  1321. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1322. & DP_TX_SKIP_CCE_CLASSIFY))
  1323. return false;
  1324. }
  1325. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1326. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1327. ether_type = eh->ether_type;
  1328. llcHdr = (qdf_llc_t *)(nbuf->data +
  1329. sizeof(qdf_ether_header_t));
  1330. } else {
  1331. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1332. /* For encrypted packets don't do any classification */
  1333. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1334. return false;
  1335. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1336. if (qdf_unlikely(
  1337. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1338. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1339. ether_type = *(uint16_t *)(nbuf->data
  1340. + QDF_IEEE80211_4ADDR_HDR_LEN
  1341. + sizeof(qdf_llc_t)
  1342. - sizeof(ether_type));
  1343. llcHdr = (qdf_llc_t *)(nbuf->data +
  1344. QDF_IEEE80211_4ADDR_HDR_LEN);
  1345. } else {
  1346. ether_type = *(uint16_t *)(nbuf->data
  1347. + QDF_IEEE80211_3ADDR_HDR_LEN
  1348. + sizeof(qdf_llc_t)
  1349. - sizeof(ether_type));
  1350. llcHdr = (qdf_llc_t *)(nbuf->data +
  1351. QDF_IEEE80211_3ADDR_HDR_LEN);
  1352. }
  1353. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1354. && (ether_type ==
  1355. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1356. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1357. return true;
  1358. }
  1359. }
  1360. return false;
  1361. }
  1362. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1363. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1364. sizeof(*llcHdr));
  1365. nbuf_clone = qdf_nbuf_clone(nbuf);
  1366. if (qdf_unlikely(nbuf_clone)) {
  1367. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1368. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1369. qdf_nbuf_pull_head(nbuf_clone,
  1370. sizeof(qdf_net_vlanhdr_t));
  1371. }
  1372. }
  1373. } else {
  1374. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1375. nbuf_clone = qdf_nbuf_clone(nbuf);
  1376. if (qdf_unlikely(nbuf_clone)) {
  1377. qdf_nbuf_pull_head(nbuf_clone,
  1378. sizeof(qdf_net_vlanhdr_t));
  1379. }
  1380. }
  1381. }
  1382. if (qdf_unlikely(nbuf_clone))
  1383. nbuf = nbuf_clone;
  1384. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1385. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1386. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1387. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1388. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1389. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1390. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1391. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1392. if (qdf_unlikely(nbuf_clone))
  1393. qdf_nbuf_free(nbuf_clone);
  1394. return true;
  1395. }
  1396. if (qdf_unlikely(nbuf_clone))
  1397. qdf_nbuf_free(nbuf_clone);
  1398. return false;
  1399. }
  1400. /**
  1401. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1402. * @vdev: DP vdev handle
  1403. * @nbuf: skb
  1404. *
  1405. * Extract the DSCP or PCP information from frame and map into TID value.
  1406. *
  1407. * Return: void
  1408. */
  1409. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. uint8_t tos = 0, dscp_tid_override = 0;
  1413. uint8_t *hdr_ptr, *L3datap;
  1414. uint8_t is_mcast = 0;
  1415. qdf_ether_header_t *eh = NULL;
  1416. qdf_ethervlan_header_t *evh = NULL;
  1417. uint16_t ether_type;
  1418. qdf_llc_t *llcHdr;
  1419. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1420. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1421. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1422. eh = (qdf_ether_header_t *)nbuf->data;
  1423. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1424. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1425. } else {
  1426. qdf_dot3_qosframe_t *qos_wh =
  1427. (qdf_dot3_qosframe_t *) nbuf->data;
  1428. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1429. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1430. return;
  1431. }
  1432. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1433. ether_type = eh->ether_type;
  1434. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1435. /*
  1436. * Check if packet is dot3 or eth2 type.
  1437. */
  1438. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1439. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1440. sizeof(*llcHdr));
  1441. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1442. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1443. sizeof(*llcHdr);
  1444. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1445. + sizeof(*llcHdr) +
  1446. sizeof(qdf_net_vlanhdr_t));
  1447. } else {
  1448. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1449. sizeof(*llcHdr);
  1450. }
  1451. } else {
  1452. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1453. evh = (qdf_ethervlan_header_t *) eh;
  1454. ether_type = evh->ether_type;
  1455. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1456. }
  1457. }
  1458. /*
  1459. * Find priority from IP TOS DSCP field
  1460. */
  1461. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1462. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1463. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1464. /* Only for unicast frames */
  1465. if (!is_mcast) {
  1466. /* send it on VO queue */
  1467. msdu_info->tid = DP_VO_TID;
  1468. }
  1469. } else {
  1470. /*
  1471. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1472. * from TOS byte.
  1473. */
  1474. tos = ip->ip_tos;
  1475. dscp_tid_override = 1;
  1476. }
  1477. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1478. /* TODO
  1479. * use flowlabel
  1480. *igmpmld cases to be handled in phase 2
  1481. */
  1482. unsigned long ver_pri_flowlabel;
  1483. unsigned long pri;
  1484. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1485. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1486. DP_IPV6_PRIORITY_SHIFT;
  1487. tos = pri;
  1488. dscp_tid_override = 1;
  1489. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1490. msdu_info->tid = DP_VO_TID;
  1491. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1492. /* Only for unicast frames */
  1493. if (!is_mcast) {
  1494. /* send ucast arp on VO queue */
  1495. msdu_info->tid = DP_VO_TID;
  1496. }
  1497. }
  1498. /*
  1499. * Assign all MCAST packets to BE
  1500. */
  1501. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1502. if (is_mcast) {
  1503. tos = 0;
  1504. dscp_tid_override = 1;
  1505. }
  1506. }
  1507. if (dscp_tid_override == 1) {
  1508. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1509. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1510. }
  1511. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1512. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1513. return;
  1514. }
  1515. /**
  1516. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1517. * @vdev: DP vdev handle
  1518. * @nbuf: skb
  1519. *
  1520. * Software based TID classification is required when more than 2 DSCP-TID
  1521. * mapping tables are needed.
  1522. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1523. *
  1524. * Return: void
  1525. */
  1526. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1527. struct dp_tx_msdu_info_s *msdu_info)
  1528. {
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. /*
  1531. * skip_sw_tid_classification flag will set in below cases-
  1532. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1533. * 2. hlos_tid_override enabled for vdev
  1534. * 3. mesh mode enabled for vdev
  1535. */
  1536. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1537. /* Update tid in msdu_info from skb priority */
  1538. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1539. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1540. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1541. return;
  1542. }
  1543. return;
  1544. }
  1545. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1546. }
  1547. #ifdef FEATURE_WLAN_TDLS
  1548. /**
  1549. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1550. * @soc: datapath SOC
  1551. * @vdev: datapath vdev
  1552. * @tx_desc: TX descriptor
  1553. *
  1554. * Return: None
  1555. */
  1556. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1557. struct dp_vdev *vdev,
  1558. struct dp_tx_desc_s *tx_desc)
  1559. {
  1560. if (vdev) {
  1561. if (vdev->is_tdls_frame) {
  1562. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1563. vdev->is_tdls_frame = false;
  1564. }
  1565. }
  1566. }
  1567. /**
  1568. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1569. * @soc: dp_soc handle
  1570. * @tx_desc: TX descriptor
  1571. * @vdev: datapath vdev handle
  1572. *
  1573. * Return: None
  1574. */
  1575. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1576. struct dp_tx_desc_s *tx_desc)
  1577. {
  1578. struct hal_tx_completion_status ts = {0};
  1579. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1580. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1581. DP_MOD_ID_TDLS);
  1582. if (qdf_unlikely(!vdev)) {
  1583. dp_err_rl("vdev is null!");
  1584. goto error;
  1585. }
  1586. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1587. if (vdev->tx_non_std_data_callback.func) {
  1588. qdf_nbuf_set_next(nbuf, NULL);
  1589. vdev->tx_non_std_data_callback.func(
  1590. vdev->tx_non_std_data_callback.ctxt,
  1591. nbuf, ts.status);
  1592. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1593. return;
  1594. } else {
  1595. dp_err_rl("callback func is null");
  1596. }
  1597. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1598. error:
  1599. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1600. qdf_nbuf_free(nbuf);
  1601. }
  1602. /**
  1603. * dp_tx_msdu_single_map() - do nbuf map
  1604. * @vdev: DP vdev handle
  1605. * @tx_desc: DP TX descriptor pointer
  1606. * @nbuf: skb pointer
  1607. *
  1608. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1609. * operation done in other component.
  1610. *
  1611. * Return: QDF_STATUS
  1612. */
  1613. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1614. struct dp_tx_desc_s *tx_desc,
  1615. qdf_nbuf_t nbuf)
  1616. {
  1617. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1618. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1619. nbuf,
  1620. QDF_DMA_TO_DEVICE,
  1621. nbuf->len);
  1622. else
  1623. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1624. QDF_DMA_TO_DEVICE);
  1625. }
  1626. #else
  1627. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1628. struct dp_vdev *vdev,
  1629. struct dp_tx_desc_s *tx_desc)
  1630. {
  1631. }
  1632. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1633. struct dp_tx_desc_s *tx_desc)
  1634. {
  1635. }
  1636. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1637. struct dp_tx_desc_s *tx_desc,
  1638. qdf_nbuf_t nbuf)
  1639. {
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. }
  1645. #endif
  1646. #ifdef MESH_MODE_SUPPORT
  1647. /**
  1648. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1649. * @soc: datapath SOC
  1650. * @vdev: datapath vdev
  1651. * @tx_desc: TX descriptor
  1652. *
  1653. * Return: None
  1654. */
  1655. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1656. struct dp_vdev *vdev,
  1657. struct dp_tx_desc_s *tx_desc)
  1658. {
  1659. if (qdf_unlikely(vdev->mesh_vdev))
  1660. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1661. }
  1662. /**
  1663. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1664. * @soc: dp_soc handle
  1665. * @tx_desc: TX descriptor
  1666. * @vdev: datapath vdev handle
  1667. *
  1668. * Return: None
  1669. */
  1670. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1671. struct dp_tx_desc_s *tx_desc)
  1672. {
  1673. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1674. struct dp_vdev *vdev = NULL;
  1675. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1676. qdf_nbuf_free(nbuf);
  1677. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1678. } else {
  1679. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1680. DP_MOD_ID_MESH);
  1681. if (vdev && vdev->osif_tx_free_ext)
  1682. vdev->osif_tx_free_ext((nbuf));
  1683. else
  1684. qdf_nbuf_free(nbuf);
  1685. if (vdev)
  1686. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1687. }
  1688. }
  1689. #else
  1690. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1691. struct dp_vdev *vdev,
  1692. struct dp_tx_desc_s *tx_desc)
  1693. {
  1694. }
  1695. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1696. struct dp_tx_desc_s *tx_desc)
  1697. {
  1698. }
  1699. #endif
  1700. /**
  1701. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1702. * @vdev: DP vdev handle
  1703. * @nbuf: skb
  1704. *
  1705. * Return: 1 if frame needs to be dropped else 0
  1706. */
  1707. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1708. {
  1709. struct dp_pdev *pdev = NULL;
  1710. struct dp_ast_entry *src_ast_entry = NULL;
  1711. struct dp_ast_entry *dst_ast_entry = NULL;
  1712. struct dp_soc *soc = NULL;
  1713. qdf_assert(vdev);
  1714. pdev = vdev->pdev;
  1715. qdf_assert(pdev);
  1716. soc = pdev->soc;
  1717. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1718. (soc, dstmac, vdev->pdev->pdev_id);
  1719. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1720. (soc, srcmac, vdev->pdev->pdev_id);
  1721. if (dst_ast_entry && src_ast_entry) {
  1722. if (dst_ast_entry->peer_id ==
  1723. src_ast_entry->peer_id)
  1724. return 1;
  1725. }
  1726. return 0;
  1727. }
  1728. /**
  1729. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1730. * @vdev: DP vdev handle
  1731. * @nbuf: skb
  1732. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1733. * @meta_data: Metadata to the fw
  1734. * @tx_q: Tx queue to be used for this Tx frame
  1735. * @peer_id: peer_id of the peer in case of NAWDS frames
  1736. * @tx_exc_metadata: Handle that holds exception path metadata
  1737. *
  1738. * Return: NULL on success,
  1739. * nbuf when it fails to send
  1740. */
  1741. qdf_nbuf_t
  1742. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1743. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1744. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1745. {
  1746. struct dp_pdev *pdev = vdev->pdev;
  1747. struct dp_soc *soc = pdev->soc;
  1748. struct dp_tx_desc_s *tx_desc;
  1749. QDF_STATUS status;
  1750. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1751. uint16_t htt_tcl_metadata = 0;
  1752. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1753. uint8_t tid = msdu_info->tid;
  1754. struct cdp_tid_tx_stats *tid_stats = NULL;
  1755. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1756. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1757. msdu_info, tx_exc_metadata);
  1758. if (!tx_desc) {
  1759. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1760. vdev, tx_q->desc_pool_id);
  1761. drop_code = TX_DESC_ERR;
  1762. goto fail_return;
  1763. }
  1764. if (qdf_unlikely(soc->cce_disable)) {
  1765. if (dp_cce_classify(vdev, nbuf) == true) {
  1766. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1767. tid = DP_VO_TID;
  1768. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1769. }
  1770. }
  1771. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1772. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1773. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1774. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1775. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1776. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1777. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1778. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1779. peer_id);
  1780. } else
  1781. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1782. if (msdu_info->exception_fw)
  1783. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1784. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1785. !pdev->enhanced_stats_en);
  1786. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1787. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1788. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1789. /* Handle failure */
  1790. dp_err("qdf_nbuf_map failed");
  1791. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1792. drop_code = TX_DMA_MAP_ERR;
  1793. goto release_desc;
  1794. }
  1795. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1796. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1797. tx_desc->id, DP_TX_DESC_MAP);
  1798. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1799. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1800. htt_tcl_metadata,
  1801. tx_exc_metadata, msdu_info);
  1802. if (status != QDF_STATUS_SUCCESS) {
  1803. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1804. tx_desc, tx_q->ring_id);
  1805. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1806. tx_desc->id, DP_TX_DESC_UNMAP);
  1807. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1808. QDF_DMA_TO_DEVICE,
  1809. nbuf->len);
  1810. drop_code = TX_HW_ENQUEUE;
  1811. goto release_desc;
  1812. }
  1813. return NULL;
  1814. release_desc:
  1815. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1816. fail_return:
  1817. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1818. tid_stats = &pdev->stats.tid_stats.
  1819. tid_tx_stats[tx_q->ring_id][tid];
  1820. tid_stats->swdrop_cnt[drop_code]++;
  1821. return nbuf;
  1822. }
  1823. /**
  1824. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1825. * @soc: Soc handle
  1826. * @desc: software Tx descriptor to be processed
  1827. *
  1828. * Return: none
  1829. */
  1830. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1831. struct dp_tx_desc_s *desc)
  1832. {
  1833. qdf_nbuf_t nbuf = desc->nbuf;
  1834. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1835. /* nbuf already freed in vdev detach path */
  1836. if (!nbuf)
  1837. return;
  1838. /* If it is TDLS mgmt, don't unmap or free the frame */
  1839. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1840. return dp_non_std_tx_comp_free_buff(soc, desc);
  1841. /* 0 : MSDU buffer, 1 : MLE */
  1842. if (desc->msdu_ext_desc) {
  1843. /* TSO free */
  1844. if (hal_tx_ext_desc_get_tso_enable(
  1845. desc->msdu_ext_desc->vaddr)) {
  1846. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1847. desc->id, DP_TX_COMP_MSDU_EXT);
  1848. dp_tx_tso_seg_history_add(soc, desc->tso_desc,
  1849. desc->nbuf, desc->id, type);
  1850. /* unmap eash TSO seg before free the nbuf */
  1851. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1852. desc->tso_num_desc);
  1853. qdf_nbuf_free(nbuf);
  1854. return;
  1855. }
  1856. }
  1857. /* If it's ME frame, dont unmap the cloned nbuf's */
  1858. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1859. goto nbuf_free;
  1860. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1861. dp_tx_unmap(soc, desc);
  1862. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1863. return dp_mesh_tx_comp_free_buff(soc, desc);
  1864. nbuf_free:
  1865. qdf_nbuf_free(nbuf);
  1866. }
  1867. /**
  1868. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1869. * @vdev: DP vdev handle
  1870. * @nbuf: skb
  1871. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1872. *
  1873. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1874. *
  1875. * Return: NULL on success,
  1876. * nbuf when it fails to send
  1877. */
  1878. #if QDF_LOCK_STATS
  1879. noinline
  1880. #else
  1881. #endif
  1882. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1883. struct dp_tx_msdu_info_s *msdu_info)
  1884. {
  1885. uint32_t i;
  1886. struct dp_pdev *pdev = vdev->pdev;
  1887. struct dp_soc *soc = pdev->soc;
  1888. struct dp_tx_desc_s *tx_desc;
  1889. bool is_cce_classified = false;
  1890. QDF_STATUS status;
  1891. uint16_t htt_tcl_metadata = 0;
  1892. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1893. struct cdp_tid_tx_stats *tid_stats = NULL;
  1894. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1895. if (qdf_unlikely(soc->cce_disable)) {
  1896. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1897. if (is_cce_classified) {
  1898. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1899. msdu_info->tid = DP_VO_TID;
  1900. }
  1901. }
  1902. if (msdu_info->frm_type == dp_tx_frm_me)
  1903. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1904. i = 0;
  1905. /* Print statement to track i and num_seg */
  1906. /*
  1907. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1908. * descriptors using information in msdu_info
  1909. */
  1910. while (i < msdu_info->num_seg) {
  1911. /*
  1912. * Setup Tx descriptor for an MSDU, and MSDU extension
  1913. * descriptor
  1914. */
  1915. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1916. tx_q->desc_pool_id);
  1917. if (!tx_desc) {
  1918. if (msdu_info->frm_type == dp_tx_frm_me) {
  1919. prep_desc_fail++;
  1920. dp_tx_me_free_buf(pdev,
  1921. (void *)(msdu_info->u.sg_info
  1922. .curr_seg->frags[0].vaddr));
  1923. if (prep_desc_fail == msdu_info->num_seg) {
  1924. /*
  1925. * Unmap is needed only if descriptor
  1926. * preparation failed for all segments.
  1927. */
  1928. qdf_nbuf_unmap(soc->osdev,
  1929. msdu_info->u.sg_info.
  1930. curr_seg->nbuf,
  1931. QDF_DMA_TO_DEVICE);
  1932. }
  1933. /*
  1934. * Free the nbuf for the current segment
  1935. * and make it point to the next in the list.
  1936. * For me, there are as many segments as there
  1937. * are no of clients.
  1938. */
  1939. qdf_nbuf_free(msdu_info->u.sg_info
  1940. .curr_seg->nbuf);
  1941. if (msdu_info->u.sg_info.curr_seg->next) {
  1942. msdu_info->u.sg_info.curr_seg =
  1943. msdu_info->u.sg_info
  1944. .curr_seg->next;
  1945. nbuf = msdu_info->u.sg_info
  1946. .curr_seg->nbuf;
  1947. }
  1948. i++;
  1949. continue;
  1950. }
  1951. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1952. dp_tx_tso_seg_history_add(
  1953. soc,
  1954. msdu_info->u.tso_info.curr_seg,
  1955. nbuf, 0, DP_TX_DESC_UNMAP);
  1956. dp_tx_tso_unmap_segment(soc,
  1957. msdu_info->u.tso_info.
  1958. curr_seg,
  1959. msdu_info->u.tso_info.
  1960. tso_num_seg_list);
  1961. if (msdu_info->u.tso_info.curr_seg->next) {
  1962. msdu_info->u.tso_info.curr_seg =
  1963. msdu_info->u.tso_info.curr_seg->next;
  1964. i++;
  1965. continue;
  1966. }
  1967. }
  1968. goto done;
  1969. }
  1970. if (msdu_info->frm_type == dp_tx_frm_me) {
  1971. tx_desc->me_buffer =
  1972. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1973. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1974. }
  1975. if (is_cce_classified)
  1976. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1977. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1978. if (msdu_info->exception_fw) {
  1979. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1980. }
  1981. /*
  1982. * For frames with multiple segments (TSO, ME), jump to next
  1983. * segment.
  1984. */
  1985. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1986. if (msdu_info->u.tso_info.curr_seg->next) {
  1987. msdu_info->u.tso_info.curr_seg =
  1988. msdu_info->u.tso_info.curr_seg->next;
  1989. /*
  1990. * If this is a jumbo nbuf, then increment the
  1991. * number of nbuf users for each additional
  1992. * segment of the msdu. This will ensure that
  1993. * the skb is freed only after receiving tx
  1994. * completion for all segments of an nbuf
  1995. */
  1996. qdf_nbuf_inc_users(nbuf);
  1997. /* Check with MCL if this is needed */
  1998. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1999. */
  2000. }
  2001. }
  2002. /*
  2003. * Enqueue the Tx MSDU descriptor to HW for transmit
  2004. */
  2005. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2006. htt_tcl_metadata,
  2007. NULL, msdu_info);
  2008. if (status != QDF_STATUS_SUCCESS) {
  2009. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2010. tx_desc, tx_q->ring_id);
  2011. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2012. tid_stats = &pdev->stats.tid_stats.
  2013. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2014. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2015. if (msdu_info->frm_type == dp_tx_frm_me) {
  2016. hw_enq_fail++;
  2017. if (hw_enq_fail == msdu_info->num_seg) {
  2018. /*
  2019. * Unmap is needed only if enqueue
  2020. * failed for all segments.
  2021. */
  2022. qdf_nbuf_unmap(soc->osdev,
  2023. msdu_info->u.sg_info.
  2024. curr_seg->nbuf,
  2025. QDF_DMA_TO_DEVICE);
  2026. }
  2027. /*
  2028. * Free the nbuf for the current segment
  2029. * and make it point to the next in the list.
  2030. * For me, there are as many segments as there
  2031. * are no of clients.
  2032. */
  2033. qdf_nbuf_free(msdu_info->u.sg_info
  2034. .curr_seg->nbuf);
  2035. if (msdu_info->u.sg_info.curr_seg->next) {
  2036. msdu_info->u.sg_info.curr_seg =
  2037. msdu_info->u.sg_info
  2038. .curr_seg->next;
  2039. nbuf = msdu_info->u.sg_info
  2040. .curr_seg->nbuf;
  2041. } else
  2042. break;
  2043. i++;
  2044. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2045. continue;
  2046. }
  2047. /*
  2048. * For TSO frames, the nbuf users increment done for
  2049. * the current segment has to be reverted, since the
  2050. * hw enqueue for this segment failed
  2051. */
  2052. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2053. msdu_info->u.tso_info.curr_seg) {
  2054. /*
  2055. * unmap and free current,
  2056. * retransmit remaining segments
  2057. */
  2058. dp_tx_comp_free_buf(soc, tx_desc);
  2059. i++;
  2060. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2061. continue;
  2062. }
  2063. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2064. goto done;
  2065. }
  2066. /*
  2067. * TODO
  2068. * if tso_info structure can be modified to have curr_seg
  2069. * as first element, following 2 blocks of code (for TSO and SG)
  2070. * can be combined into 1
  2071. */
  2072. /*
  2073. * For Multicast-Unicast converted packets,
  2074. * each converted frame (for a client) is represented as
  2075. * 1 segment
  2076. */
  2077. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2078. (msdu_info->frm_type == dp_tx_frm_me)) {
  2079. if (msdu_info->u.sg_info.curr_seg->next) {
  2080. msdu_info->u.sg_info.curr_seg =
  2081. msdu_info->u.sg_info.curr_seg->next;
  2082. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2083. } else
  2084. break;
  2085. }
  2086. i++;
  2087. }
  2088. nbuf = NULL;
  2089. done:
  2090. return nbuf;
  2091. }
  2092. /**
  2093. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2094. * for SG frames
  2095. * @vdev: DP vdev handle
  2096. * @nbuf: skb
  2097. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2098. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2099. *
  2100. * Return: NULL on success,
  2101. * nbuf when it fails to send
  2102. */
  2103. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2104. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2105. {
  2106. uint32_t cur_frag, nr_frags, i;
  2107. qdf_dma_addr_t paddr;
  2108. struct dp_tx_sg_info_s *sg_info;
  2109. sg_info = &msdu_info->u.sg_info;
  2110. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2111. if (QDF_STATUS_SUCCESS !=
  2112. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2113. QDF_DMA_TO_DEVICE,
  2114. qdf_nbuf_headlen(nbuf))) {
  2115. dp_tx_err("dma map error");
  2116. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2117. qdf_nbuf_free(nbuf);
  2118. return NULL;
  2119. }
  2120. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2121. seg_info->frags[0].paddr_lo = paddr;
  2122. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2123. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2124. seg_info->frags[0].vaddr = (void *) nbuf;
  2125. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2126. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2127. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2128. dp_tx_err("frag dma map error");
  2129. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2130. goto map_err;
  2131. }
  2132. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2133. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2134. seg_info->frags[cur_frag + 1].paddr_hi =
  2135. ((uint64_t) paddr) >> 32;
  2136. seg_info->frags[cur_frag + 1].len =
  2137. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2138. }
  2139. seg_info->frag_cnt = (cur_frag + 1);
  2140. seg_info->total_len = qdf_nbuf_len(nbuf);
  2141. seg_info->next = NULL;
  2142. sg_info->curr_seg = seg_info;
  2143. msdu_info->frm_type = dp_tx_frm_sg;
  2144. msdu_info->num_seg = 1;
  2145. return nbuf;
  2146. map_err:
  2147. /* restore paddr into nbuf before calling unmap */
  2148. qdf_nbuf_mapped_paddr_set(nbuf,
  2149. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2150. ((uint64_t)
  2151. seg_info->frags[0].paddr_hi) << 32));
  2152. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2153. QDF_DMA_TO_DEVICE,
  2154. seg_info->frags[0].len);
  2155. for (i = 1; i <= cur_frag; i++) {
  2156. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2157. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2158. seg_info->frags[i].paddr_hi) << 32),
  2159. seg_info->frags[i].len,
  2160. QDF_DMA_TO_DEVICE);
  2161. }
  2162. qdf_nbuf_free(nbuf);
  2163. return NULL;
  2164. }
  2165. /**
  2166. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2167. * @vdev: DP vdev handle
  2168. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2169. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2170. *
  2171. * Return: NULL on failure,
  2172. * nbuf when extracted successfully
  2173. */
  2174. static
  2175. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2176. struct dp_tx_msdu_info_s *msdu_info,
  2177. uint16_t ppdu_cookie)
  2178. {
  2179. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2180. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2181. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2182. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2183. (msdu_info->meta_data[5], 1);
  2184. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2185. (msdu_info->meta_data[5], 1);
  2186. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2187. (msdu_info->meta_data[6], ppdu_cookie);
  2188. msdu_info->exception_fw = 1;
  2189. msdu_info->is_tx_sniffer = 1;
  2190. }
  2191. #ifdef MESH_MODE_SUPPORT
  2192. /**
  2193. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2194. and prepare msdu_info for mesh frames.
  2195. * @vdev: DP vdev handle
  2196. * @nbuf: skb
  2197. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2198. *
  2199. * Return: NULL on failure,
  2200. * nbuf when extracted successfully
  2201. */
  2202. static
  2203. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2204. struct dp_tx_msdu_info_s *msdu_info)
  2205. {
  2206. struct meta_hdr_s *mhdr;
  2207. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2208. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2209. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2210. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2211. msdu_info->exception_fw = 0;
  2212. goto remove_meta_hdr;
  2213. }
  2214. msdu_info->exception_fw = 1;
  2215. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2216. meta_data->host_tx_desc_pool = 1;
  2217. meta_data->update_peer_cache = 1;
  2218. meta_data->learning_frame = 1;
  2219. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2220. meta_data->power = mhdr->power;
  2221. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2222. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2223. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2224. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2225. meta_data->dyn_bw = 1;
  2226. meta_data->valid_pwr = 1;
  2227. meta_data->valid_mcs_mask = 1;
  2228. meta_data->valid_nss_mask = 1;
  2229. meta_data->valid_preamble_type = 1;
  2230. meta_data->valid_retries = 1;
  2231. meta_data->valid_bw_info = 1;
  2232. }
  2233. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2234. meta_data->encrypt_type = 0;
  2235. meta_data->valid_encrypt_type = 1;
  2236. meta_data->learning_frame = 0;
  2237. }
  2238. meta_data->valid_key_flags = 1;
  2239. meta_data->key_flags = (mhdr->keyix & 0x3);
  2240. remove_meta_hdr:
  2241. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2242. dp_tx_err("qdf_nbuf_pull_head failed");
  2243. qdf_nbuf_free(nbuf);
  2244. return NULL;
  2245. }
  2246. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2247. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2248. " tid %d to_fw %d",
  2249. msdu_info->meta_data[0],
  2250. msdu_info->meta_data[1],
  2251. msdu_info->meta_data[2],
  2252. msdu_info->meta_data[3],
  2253. msdu_info->meta_data[4],
  2254. msdu_info->meta_data[5],
  2255. msdu_info->tid, msdu_info->exception_fw);
  2256. return nbuf;
  2257. }
  2258. #else
  2259. static
  2260. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2261. struct dp_tx_msdu_info_s *msdu_info)
  2262. {
  2263. return nbuf;
  2264. }
  2265. #endif
  2266. /**
  2267. * dp_check_exc_metadata() - Checks if parameters are valid
  2268. * @tx_exc - holds all exception path parameters
  2269. *
  2270. * Returns true when all the parameters are valid else false
  2271. *
  2272. */
  2273. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2274. {
  2275. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2276. HTT_INVALID_TID);
  2277. bool invalid_encap_type =
  2278. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2279. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2280. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2281. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2282. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2283. tx_exc->ppdu_cookie == 0);
  2284. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2285. invalid_cookie) {
  2286. return false;
  2287. }
  2288. return true;
  2289. }
  2290. #ifdef ATH_SUPPORT_IQUE
  2291. /**
  2292. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2293. * @vdev: vdev handle
  2294. * @nbuf: skb
  2295. *
  2296. * Return: true on success,
  2297. * false on failure
  2298. */
  2299. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2300. {
  2301. qdf_ether_header_t *eh;
  2302. /* Mcast to Ucast Conversion*/
  2303. if (qdf_likely(!vdev->mcast_enhancement_en))
  2304. return true;
  2305. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2306. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2307. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2308. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2309. qdf_nbuf_set_next(nbuf, NULL);
  2310. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2311. qdf_nbuf_len(nbuf));
  2312. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2313. QDF_STATUS_SUCCESS) {
  2314. return false;
  2315. }
  2316. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2317. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2318. QDF_STATUS_SUCCESS) {
  2319. return false;
  2320. }
  2321. }
  2322. }
  2323. return true;
  2324. }
  2325. #else
  2326. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2327. {
  2328. return true;
  2329. }
  2330. #endif
  2331. /**
  2332. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2333. * @nbuf: qdf_nbuf_t
  2334. * @vdev: struct dp_vdev *
  2335. *
  2336. * Allow packet for processing only if it is for peer client which is
  2337. * connected with same vap. Drop packet if client is connected to
  2338. * different vap.
  2339. *
  2340. * Return: QDF_STATUS
  2341. */
  2342. static inline QDF_STATUS
  2343. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2344. {
  2345. struct dp_ast_entry *dst_ast_entry = NULL;
  2346. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2347. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2348. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2349. return QDF_STATUS_SUCCESS;
  2350. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2351. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2352. eh->ether_dhost,
  2353. vdev->vdev_id);
  2354. /* If there is no ast entry, return failure */
  2355. if (qdf_unlikely(!dst_ast_entry)) {
  2356. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2357. return QDF_STATUS_E_FAILURE;
  2358. }
  2359. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2360. return QDF_STATUS_SUCCESS;
  2361. }
  2362. /**
  2363. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2364. * @soc: DP soc handle
  2365. * @vdev_id: id of DP vdev handle
  2366. * @nbuf: skb
  2367. * @tx_exc_metadata: Handle that holds exception path meta data
  2368. *
  2369. * Entry point for Core Tx layer (DP_TX) invoked from
  2370. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2371. *
  2372. * Return: NULL on success,
  2373. * nbuf when it fails to send
  2374. */
  2375. qdf_nbuf_t
  2376. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2377. qdf_nbuf_t nbuf,
  2378. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2379. {
  2380. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2381. qdf_ether_header_t *eh = NULL;
  2382. struct dp_tx_msdu_info_s msdu_info;
  2383. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2384. DP_MOD_ID_TX_EXCEPTION);
  2385. if (qdf_unlikely(!vdev))
  2386. goto fail;
  2387. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2388. if (!tx_exc_metadata)
  2389. goto fail;
  2390. msdu_info.tid = tx_exc_metadata->tid;
  2391. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2392. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2393. QDF_MAC_ADDR_REF(nbuf->data));
  2394. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2395. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2396. dp_tx_err("Invalid parameters in exception path");
  2397. goto fail;
  2398. }
  2399. /* Basic sanity checks for unsupported packets */
  2400. /* MESH mode */
  2401. if (qdf_unlikely(vdev->mesh_vdev)) {
  2402. dp_tx_err("Mesh mode is not supported in exception path");
  2403. goto fail;
  2404. }
  2405. /*
  2406. * Classify the frame and call corresponding
  2407. * "prepare" function which extracts the segment (TSO)
  2408. * and fragmentation information (for TSO , SG, ME, or Raw)
  2409. * into MSDU_INFO structure which is later used to fill
  2410. * SW and HW descriptors.
  2411. */
  2412. if (qdf_nbuf_is_tso(nbuf)) {
  2413. dp_verbose_debug("TSO frame %pK", vdev);
  2414. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2415. qdf_nbuf_len(nbuf));
  2416. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2417. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2418. qdf_nbuf_len(nbuf));
  2419. goto fail;
  2420. }
  2421. goto send_multiple;
  2422. }
  2423. /* SG */
  2424. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2425. struct dp_tx_seg_info_s seg_info = {0};
  2426. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2427. if (!nbuf)
  2428. goto fail;
  2429. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2430. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2431. qdf_nbuf_len(nbuf));
  2432. goto send_multiple;
  2433. }
  2434. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2435. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2436. qdf_nbuf_len(nbuf));
  2437. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2438. tx_exc_metadata->ppdu_cookie);
  2439. }
  2440. /*
  2441. * Get HW Queue to use for this frame.
  2442. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2443. * dedicated for data and 1 for command.
  2444. * "queue_id" maps to one hardware ring.
  2445. * With each ring, we also associate a unique Tx descriptor pool
  2446. * to minimize lock contention for these resources.
  2447. */
  2448. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2449. /*
  2450. * Check exception descriptors
  2451. */
  2452. if (dp_tx_exception_limit_check(vdev))
  2453. goto fail;
  2454. /* Single linear frame */
  2455. /*
  2456. * If nbuf is a simple linear frame, use send_single function to
  2457. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2458. * SRNG. There is no need to setup a MSDU extension descriptor.
  2459. */
  2460. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2461. tx_exc_metadata->peer_id, tx_exc_metadata);
  2462. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2463. return nbuf;
  2464. send_multiple:
  2465. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2466. fail:
  2467. if (vdev)
  2468. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2469. dp_verbose_debug("pkt send failed");
  2470. return nbuf;
  2471. }
  2472. /**
  2473. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2474. * in exception path in special case to avoid regular exception path chk.
  2475. * @soc: DP soc handle
  2476. * @vdev_id: id of DP vdev handle
  2477. * @nbuf: skb
  2478. * @tx_exc_metadata: Handle that holds exception path meta data
  2479. *
  2480. * Entry point for Core Tx layer (DP_TX) invoked from
  2481. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2482. *
  2483. * Return: NULL on success,
  2484. * nbuf when it fails to send
  2485. */
  2486. qdf_nbuf_t
  2487. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2488. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2489. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2490. {
  2491. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2492. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2493. DP_MOD_ID_TX_EXCEPTION);
  2494. if (qdf_unlikely(!vdev))
  2495. goto fail;
  2496. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2497. == QDF_STATUS_E_FAILURE)) {
  2498. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2499. goto fail;
  2500. }
  2501. /* Unref count as it will agin be taken inside dp_tx_exception */
  2502. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2503. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2504. fail:
  2505. if (vdev)
  2506. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2507. dp_verbose_debug("pkt send failed");
  2508. return nbuf;
  2509. }
  2510. /**
  2511. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2512. * @soc: DP soc handle
  2513. * @vdev_id: DP vdev handle
  2514. * @nbuf: skb
  2515. *
  2516. * Entry point for Core Tx layer (DP_TX) invoked from
  2517. * hard_start_xmit in OSIF/HDD
  2518. *
  2519. * Return: NULL on success,
  2520. * nbuf when it fails to send
  2521. */
  2522. #ifdef MESH_MODE_SUPPORT
  2523. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2524. qdf_nbuf_t nbuf)
  2525. {
  2526. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2527. struct meta_hdr_s *mhdr;
  2528. qdf_nbuf_t nbuf_mesh = NULL;
  2529. qdf_nbuf_t nbuf_clone = NULL;
  2530. struct dp_vdev *vdev;
  2531. uint8_t no_enc_frame = 0;
  2532. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2533. if (!nbuf_mesh) {
  2534. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2535. "qdf_nbuf_unshare failed");
  2536. return nbuf;
  2537. }
  2538. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2539. if (!vdev) {
  2540. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2541. "vdev is NULL for vdev_id %d", vdev_id);
  2542. return nbuf;
  2543. }
  2544. nbuf = nbuf_mesh;
  2545. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2546. if ((vdev->sec_type != cdp_sec_type_none) &&
  2547. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2548. no_enc_frame = 1;
  2549. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2550. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2551. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2552. !no_enc_frame) {
  2553. nbuf_clone = qdf_nbuf_clone(nbuf);
  2554. if (!nbuf_clone) {
  2555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2556. "qdf_nbuf_clone failed");
  2557. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2558. return nbuf;
  2559. }
  2560. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2561. }
  2562. if (nbuf_clone) {
  2563. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2564. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2565. } else {
  2566. qdf_nbuf_free(nbuf_clone);
  2567. }
  2568. }
  2569. if (no_enc_frame)
  2570. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2571. else
  2572. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2573. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2574. if ((!nbuf) && no_enc_frame) {
  2575. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2576. }
  2577. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2578. return nbuf;
  2579. }
  2580. #else
  2581. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2582. qdf_nbuf_t nbuf)
  2583. {
  2584. return dp_tx_send(soc, vdev_id, nbuf);
  2585. }
  2586. #endif
  2587. /**
  2588. * dp_tx_nawds_handler() - NAWDS handler
  2589. *
  2590. * @soc: DP soc handle
  2591. * @vdev_id: id of DP vdev handle
  2592. * @msdu_info: msdu_info required to create HTT metadata
  2593. * @nbuf: skb
  2594. *
  2595. * This API transfers the multicast frames with the peer id
  2596. * on NAWDS enabled peer.
  2597. * Return: none
  2598. */
  2599. static inline
  2600. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2601. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2602. {
  2603. struct dp_peer *peer = NULL;
  2604. qdf_nbuf_t nbuf_clone = NULL;
  2605. uint16_t peer_id = DP_INVALID_PEER;
  2606. uint16_t sa_peer_id = DP_INVALID_PEER;
  2607. struct dp_ast_entry *ast_entry = NULL;
  2608. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2609. if (!soc->ast_offload_support) {
  2610. qdf_spin_lock_bh(&soc->ast_lock);
  2611. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2612. (soc,
  2613. (uint8_t *)(eh->ether_shost),
  2614. vdev->pdev->pdev_id);
  2615. if (ast_entry)
  2616. sa_peer_id = ast_entry->peer_id;
  2617. qdf_spin_unlock_bh(&soc->ast_lock);
  2618. }
  2619. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2620. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2621. if (!peer->bss_peer && peer->nawds_enabled) {
  2622. peer_id = peer->peer_id;
  2623. /* Multicast packets needs to be
  2624. * dropped in case of intra bss forwarding
  2625. */
  2626. if (!soc->ast_offload_support) {
  2627. if (sa_peer_id == peer->peer_id) {
  2628. dp_tx_debug("multicast packet");
  2629. DP_STATS_INC(peer, tx.nawds_mcast_drop,
  2630. 1);
  2631. continue;
  2632. }
  2633. }
  2634. nbuf_clone = qdf_nbuf_clone(nbuf);
  2635. if (!nbuf_clone) {
  2636. QDF_TRACE(QDF_MODULE_ID_DP,
  2637. QDF_TRACE_LEVEL_ERROR,
  2638. FL("nbuf clone failed"));
  2639. break;
  2640. }
  2641. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2642. msdu_info, peer_id,
  2643. NULL);
  2644. if (nbuf_clone) {
  2645. dp_tx_debug("pkt send failed");
  2646. qdf_nbuf_free(nbuf_clone);
  2647. } else {
  2648. if (peer_id != DP_INVALID_PEER)
  2649. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2650. 1, qdf_nbuf_len(nbuf));
  2651. }
  2652. }
  2653. }
  2654. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2655. }
  2656. /**
  2657. * dp_tx_send() - Transmit a frame on a given VAP
  2658. * @soc: DP soc handle
  2659. * @vdev_id: id of DP vdev handle
  2660. * @nbuf: skb
  2661. *
  2662. * Entry point for Core Tx layer (DP_TX) invoked from
  2663. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2664. * cases
  2665. *
  2666. * Return: NULL on success,
  2667. * nbuf when it fails to send
  2668. */
  2669. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2670. qdf_nbuf_t nbuf)
  2671. {
  2672. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2673. uint16_t peer_id = HTT_INVALID_PEER;
  2674. /*
  2675. * doing a memzero is causing additional function call overhead
  2676. * so doing static stack clearing
  2677. */
  2678. struct dp_tx_msdu_info_s msdu_info = {0};
  2679. struct dp_vdev *vdev = NULL;
  2680. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2681. return nbuf;
  2682. /*
  2683. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2684. * this in per packet path.
  2685. *
  2686. * As in this path vdev memory is already protected with netdev
  2687. * tx lock
  2688. */
  2689. vdev = soc->vdev_id_map[vdev_id];
  2690. if (qdf_unlikely(!vdev))
  2691. return nbuf;
  2692. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2693. QDF_MAC_ADDR_REF(nbuf->data));
  2694. /*
  2695. * Set Default Host TID value to invalid TID
  2696. * (TID override disabled)
  2697. */
  2698. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2699. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2700. if (qdf_unlikely(vdev->mesh_vdev)) {
  2701. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2702. &msdu_info);
  2703. if (!nbuf_mesh) {
  2704. dp_verbose_debug("Extracting mesh metadata failed");
  2705. return nbuf;
  2706. }
  2707. nbuf = nbuf_mesh;
  2708. }
  2709. /*
  2710. * Get HW Queue to use for this frame.
  2711. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2712. * dedicated for data and 1 for command.
  2713. * "queue_id" maps to one hardware ring.
  2714. * With each ring, we also associate a unique Tx descriptor pool
  2715. * to minimize lock contention for these resources.
  2716. */
  2717. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2718. /*
  2719. * TCL H/W supports 2 DSCP-TID mapping tables.
  2720. * Table 1 - Default DSCP-TID mapping table
  2721. * Table 2 - 1 DSCP-TID override table
  2722. *
  2723. * If we need a different DSCP-TID mapping for this vap,
  2724. * call tid_classify to extract DSCP/ToS from frame and
  2725. * map to a TID and store in msdu_info. This is later used
  2726. * to fill in TCL Input descriptor (per-packet TID override).
  2727. */
  2728. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2729. /*
  2730. * Classify the frame and call corresponding
  2731. * "prepare" function which extracts the segment (TSO)
  2732. * and fragmentation information (for TSO , SG, ME, or Raw)
  2733. * into MSDU_INFO structure which is later used to fill
  2734. * SW and HW descriptors.
  2735. */
  2736. if (qdf_nbuf_is_tso(nbuf)) {
  2737. dp_verbose_debug("TSO frame %pK", vdev);
  2738. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2739. qdf_nbuf_len(nbuf));
  2740. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2741. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2742. qdf_nbuf_len(nbuf));
  2743. return nbuf;
  2744. }
  2745. goto send_multiple;
  2746. }
  2747. /* SG */
  2748. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2749. struct dp_tx_seg_info_s seg_info = {0};
  2750. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2751. if (!nbuf)
  2752. return NULL;
  2753. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2754. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2755. qdf_nbuf_len(nbuf));
  2756. goto send_multiple;
  2757. }
  2758. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2759. return NULL;
  2760. /* RAW */
  2761. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2762. struct dp_tx_seg_info_s seg_info = {0};
  2763. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2764. if (!nbuf)
  2765. return NULL;
  2766. dp_verbose_debug("Raw frame %pK", vdev);
  2767. goto send_multiple;
  2768. }
  2769. if (qdf_unlikely(vdev->nawds_enabled)) {
  2770. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2771. qdf_nbuf_data(nbuf);
  2772. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2773. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2774. peer_id = DP_INVALID_PEER;
  2775. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2776. 1, qdf_nbuf_len(nbuf));
  2777. }
  2778. /* Single linear frame */
  2779. /*
  2780. * If nbuf is a simple linear frame, use send_single function to
  2781. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2782. * SRNG. There is no need to setup a MSDU extension descriptor.
  2783. */
  2784. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2785. return nbuf;
  2786. send_multiple:
  2787. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2788. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2789. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2790. return nbuf;
  2791. }
  2792. /**
  2793. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2794. * case to vaoid check in perpkt path.
  2795. * @soc: DP soc handle
  2796. * @vdev_id: id of DP vdev handle
  2797. * @nbuf: skb
  2798. *
  2799. * Entry point for Core Tx layer (DP_TX) invoked from
  2800. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2801. * with special condition to avoid per pkt check in dp_tx_send
  2802. *
  2803. * Return: NULL on success,
  2804. * nbuf when it fails to send
  2805. */
  2806. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2807. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2808. {
  2809. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2810. struct dp_vdev *vdev = NULL;
  2811. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2812. return nbuf;
  2813. /*
  2814. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2815. * this in per packet path.
  2816. *
  2817. * As in this path vdev memory is already protected with netdev
  2818. * tx lock
  2819. */
  2820. vdev = soc->vdev_id_map[vdev_id];
  2821. if (qdf_unlikely(!vdev))
  2822. return nbuf;
  2823. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2824. == QDF_STATUS_E_FAILURE)) {
  2825. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2826. return nbuf;
  2827. }
  2828. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2829. }
  2830. #ifdef UMAC_SUPPORT_PROXY_ARP
  2831. /**
  2832. * dp_tx_proxy_arp() - Tx proxy arp handler
  2833. * @vdev: datapath vdev handle
  2834. * @buf: sk buffer
  2835. *
  2836. * Return: status
  2837. */
  2838. static inline
  2839. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2840. {
  2841. if (vdev->osif_proxy_arp)
  2842. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2843. /*
  2844. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2845. * osif_proxy_arp has a valid function pointer assigned
  2846. * to it
  2847. */
  2848. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2849. return QDF_STATUS_NOT_INITIALIZED;
  2850. }
  2851. #else
  2852. /**
  2853. * dp_tx_proxy_arp() - Tx proxy arp handler
  2854. * @vdev: datapath vdev handle
  2855. * @buf: sk buffer
  2856. *
  2857. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2858. * is not defined.
  2859. *
  2860. * Return: status
  2861. */
  2862. static inline
  2863. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2864. {
  2865. return QDF_STATUS_SUCCESS;
  2866. }
  2867. #endif
  2868. /**
  2869. * dp_tx_reinject_handler() - Tx Reinject Handler
  2870. * @soc: datapath soc handle
  2871. * @vdev: datapath vdev handle
  2872. * @tx_desc: software descriptor head pointer
  2873. * @status : Tx completion status from HTT descriptor
  2874. *
  2875. * This function reinjects frames back to Target.
  2876. * Todo - Host queue needs to be added
  2877. *
  2878. * Return: none
  2879. */
  2880. static
  2881. void dp_tx_reinject_handler(struct dp_soc *soc,
  2882. struct dp_vdev *vdev,
  2883. struct dp_tx_desc_s *tx_desc,
  2884. uint8_t *status)
  2885. {
  2886. struct dp_peer *peer = NULL;
  2887. uint32_t peer_id = HTT_INVALID_PEER;
  2888. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2889. qdf_nbuf_t nbuf_copy = NULL;
  2890. struct dp_tx_msdu_info_s msdu_info;
  2891. #ifdef WDS_VENDOR_EXTENSION
  2892. int is_mcast = 0, is_ucast = 0;
  2893. int num_peers_3addr = 0;
  2894. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2895. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2896. #endif
  2897. qdf_assert(vdev);
  2898. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2899. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2900. dp_tx_debug("Tx reinject path");
  2901. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2902. qdf_nbuf_len(tx_desc->nbuf));
  2903. #ifdef WDS_VENDOR_EXTENSION
  2904. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2905. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2906. } else {
  2907. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2908. }
  2909. is_ucast = !is_mcast;
  2910. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2911. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2912. if (peer->bss_peer)
  2913. continue;
  2914. /* Detect wds peers that use 3-addr framing for mcast.
  2915. * if there are any, the bss_peer is used to send the
  2916. * the mcast frame using 3-addr format. all wds enabled
  2917. * peers that use 4-addr framing for mcast frames will
  2918. * be duplicated and sent as 4-addr frames below.
  2919. */
  2920. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2921. num_peers_3addr = 1;
  2922. break;
  2923. }
  2924. }
  2925. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2926. #endif
  2927. if (qdf_unlikely(vdev->mesh_vdev)) {
  2928. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2929. } else {
  2930. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2931. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2932. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2933. #ifdef WDS_VENDOR_EXTENSION
  2934. /*
  2935. * . if 3-addr STA, then send on BSS Peer
  2936. * . if Peer WDS enabled and accept 4-addr mcast,
  2937. * send mcast on that peer only
  2938. * . if Peer WDS enabled and accept 4-addr ucast,
  2939. * send ucast on that peer only
  2940. */
  2941. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2942. (peer->wds_enabled &&
  2943. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2944. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2945. #else
  2946. (peer->bss_peer &&
  2947. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2948. #endif
  2949. peer_id = DP_INVALID_PEER;
  2950. nbuf_copy = qdf_nbuf_copy(nbuf);
  2951. if (!nbuf_copy) {
  2952. dp_tx_debug("nbuf copy failed");
  2953. break;
  2954. }
  2955. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2956. nbuf_copy,
  2957. &msdu_info,
  2958. peer_id,
  2959. NULL);
  2960. if (nbuf_copy) {
  2961. dp_tx_debug("pkt send failed");
  2962. qdf_nbuf_free(nbuf_copy);
  2963. }
  2964. }
  2965. }
  2966. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2967. }
  2968. qdf_nbuf_free(nbuf);
  2969. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2970. }
  2971. /**
  2972. * dp_tx_inspect_handler() - Tx Inspect Handler
  2973. * @soc: datapath soc handle
  2974. * @vdev: datapath vdev handle
  2975. * @tx_desc: software descriptor head pointer
  2976. * @status : Tx completion status from HTT descriptor
  2977. *
  2978. * Handles Tx frames sent back to Host for inspection
  2979. * (ProxyARP)
  2980. *
  2981. * Return: none
  2982. */
  2983. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2984. struct dp_vdev *vdev,
  2985. struct dp_tx_desc_s *tx_desc,
  2986. uint8_t *status)
  2987. {
  2988. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2989. "%s Tx inspect path",
  2990. __func__);
  2991. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2992. qdf_nbuf_len(tx_desc->nbuf));
  2993. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2994. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2995. }
  2996. #ifdef MESH_MODE_SUPPORT
  2997. /**
  2998. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2999. * in mesh meta header
  3000. * @tx_desc: software descriptor head pointer
  3001. * @ts: pointer to tx completion stats
  3002. * Return: none
  3003. */
  3004. static
  3005. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3006. struct hal_tx_completion_status *ts)
  3007. {
  3008. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3009. if (!tx_desc->msdu_ext_desc) {
  3010. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3012. "netbuf %pK offset %d",
  3013. netbuf, tx_desc->pkt_offset);
  3014. return;
  3015. }
  3016. }
  3017. }
  3018. #else
  3019. static
  3020. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3021. struct hal_tx_completion_status *ts)
  3022. {
  3023. }
  3024. #endif
  3025. #ifdef QCA_PEER_EXT_STATS
  3026. /*
  3027. * dp_tx_compute_tid_delay() - Compute per TID delay
  3028. * @stats: Per TID delay stats
  3029. * @tx_desc: Software Tx descriptor
  3030. *
  3031. * Compute the software enqueue and hw enqueue delays and
  3032. * update the respective histograms
  3033. *
  3034. * Return: void
  3035. */
  3036. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3037. struct dp_tx_desc_s *tx_desc)
  3038. {
  3039. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3040. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3041. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3042. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3043. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3044. timestamp_hw_enqueue = tx_desc->timestamp;
  3045. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3046. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3047. timestamp_hw_enqueue);
  3048. /*
  3049. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3050. */
  3051. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3052. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3053. }
  3054. /*
  3055. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3056. * @peer: DP peer context
  3057. * @tx_desc: Tx software descriptor
  3058. * @tid: Transmission ID
  3059. * @ring_id: Rx CPU context ID/CPU_ID
  3060. *
  3061. * Update the peer extended stats. These are enhanced other
  3062. * delay stats per msdu level.
  3063. *
  3064. * Return: void
  3065. */
  3066. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3067. struct dp_tx_desc_s *tx_desc,
  3068. uint8_t tid, uint8_t ring_id)
  3069. {
  3070. struct dp_pdev *pdev = peer->vdev->pdev;
  3071. struct dp_soc *soc = NULL;
  3072. struct cdp_peer_ext_stats *pext_stats = NULL;
  3073. soc = pdev->soc;
  3074. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3075. return;
  3076. pext_stats = peer->pext_stats;
  3077. qdf_assert(pext_stats);
  3078. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3079. /*
  3080. * For non-TID packets use the TID 9
  3081. */
  3082. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3083. tid = CDP_MAX_DATA_TIDS - 1;
  3084. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3085. tx_desc);
  3086. }
  3087. #else
  3088. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3089. struct dp_tx_desc_s *tx_desc,
  3090. uint8_t tid, uint8_t ring_id)
  3091. {
  3092. }
  3093. #endif
  3094. /**
  3095. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3096. * to pass in correct fields
  3097. *
  3098. * @vdev: pdev handle
  3099. * @tx_desc: tx descriptor
  3100. * @tid: tid value
  3101. * @ring_id: TCL or WBM ring number for transmit path
  3102. * Return: none
  3103. */
  3104. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3105. struct dp_tx_desc_s *tx_desc,
  3106. uint8_t tid, uint8_t ring_id)
  3107. {
  3108. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3109. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3110. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3111. return;
  3112. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3113. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3114. timestamp_hw_enqueue = tx_desc->timestamp;
  3115. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3116. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3117. timestamp_hw_enqueue);
  3118. interframe_delay = (uint32_t)(timestamp_ingress -
  3119. vdev->prev_tx_enq_tstamp);
  3120. /*
  3121. * Delay in software enqueue
  3122. */
  3123. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3124. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3125. /*
  3126. * Delay between packet enqueued to HW and Tx completion
  3127. */
  3128. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3129. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3130. /*
  3131. * Update interframe delay stats calculated at hardstart receive point.
  3132. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3133. * interframe delay will not be calculate correctly for 1st frame.
  3134. * On the other side, this will help in avoiding extra per packet check
  3135. * of !vdev->prev_tx_enq_tstamp.
  3136. */
  3137. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3138. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3139. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3140. }
  3141. #ifdef DISABLE_DP_STATS
  3142. static
  3143. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3144. {
  3145. }
  3146. #else
  3147. static
  3148. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3149. {
  3150. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3151. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3152. if (subtype != QDF_PROTO_INVALID)
  3153. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3154. }
  3155. #endif
  3156. /**
  3157. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3158. * per wbm ring
  3159. *
  3160. * @tx_desc: software descriptor head pointer
  3161. * @ts: Tx completion status
  3162. * @peer: peer handle
  3163. * @ring_id: ring number
  3164. *
  3165. * Return: None
  3166. */
  3167. static inline void
  3168. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3169. struct hal_tx_completion_status *ts,
  3170. struct dp_peer *peer, uint8_t ring_id)
  3171. {
  3172. struct dp_pdev *pdev = peer->vdev->pdev;
  3173. struct dp_soc *soc = NULL;
  3174. uint8_t mcs, pkt_type;
  3175. uint8_t tid = ts->tid;
  3176. uint32_t length;
  3177. struct cdp_tid_tx_stats *tid_stats;
  3178. if (!pdev)
  3179. return;
  3180. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3181. tid = CDP_MAX_DATA_TIDS - 1;
  3182. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3183. soc = pdev->soc;
  3184. mcs = ts->mcs;
  3185. pkt_type = ts->pkt_type;
  3186. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3187. dp_err("Release source is not from TQM");
  3188. return;
  3189. }
  3190. length = qdf_nbuf_len(tx_desc->nbuf);
  3191. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3192. if (qdf_unlikely(pdev->delay_stats_flag))
  3193. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3194. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3195. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3196. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3197. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3198. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3199. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3200. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3201. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3202. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3203. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3204. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3205. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3206. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3207. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3208. /*
  3209. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3210. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3211. * are no completions for failed cases. Hence updating tx_failed from
  3212. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3213. * then this has to be removed
  3214. */
  3215. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3216. peer->stats.tx.dropped.fw_rem_notx +
  3217. peer->stats.tx.dropped.fw_rem_tx +
  3218. peer->stats.tx.dropped.age_out +
  3219. peer->stats.tx.dropped.fw_reason1 +
  3220. peer->stats.tx.dropped.fw_reason2 +
  3221. peer->stats.tx.dropped.fw_reason3;
  3222. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3223. tid_stats->tqm_status_cnt[ts->status]++;
  3224. }
  3225. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3226. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3227. return;
  3228. }
  3229. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3230. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3231. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3232. /*
  3233. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3234. * Return from here if HTT PPDU events are enabled.
  3235. */
  3236. if (!(soc->process_tx_status))
  3237. return;
  3238. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3239. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3240. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3241. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3242. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3243. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3244. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3245. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3246. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3247. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3248. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3249. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3250. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3251. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3252. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3253. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3254. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3255. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3256. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3257. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3258. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3259. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3260. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3261. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3262. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3263. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3264. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3265. }
  3266. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3267. /**
  3268. * dp_tx_flow_pool_lock() - take flow pool lock
  3269. * @soc: core txrx main context
  3270. * @tx_desc: tx desc
  3271. *
  3272. * Return: None
  3273. */
  3274. static inline
  3275. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3276. struct dp_tx_desc_s *tx_desc)
  3277. {
  3278. struct dp_tx_desc_pool_s *pool;
  3279. uint8_t desc_pool_id;
  3280. desc_pool_id = tx_desc->pool_id;
  3281. pool = &soc->tx_desc[desc_pool_id];
  3282. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3283. }
  3284. /**
  3285. * dp_tx_flow_pool_unlock() - release flow pool lock
  3286. * @soc: core txrx main context
  3287. * @tx_desc: tx desc
  3288. *
  3289. * Return: None
  3290. */
  3291. static inline
  3292. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3293. struct dp_tx_desc_s *tx_desc)
  3294. {
  3295. struct dp_tx_desc_pool_s *pool;
  3296. uint8_t desc_pool_id;
  3297. desc_pool_id = tx_desc->pool_id;
  3298. pool = &soc->tx_desc[desc_pool_id];
  3299. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3300. }
  3301. #else
  3302. static inline
  3303. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3304. {
  3305. }
  3306. static inline
  3307. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3308. {
  3309. }
  3310. #endif
  3311. /**
  3312. * dp_tx_notify_completion() - Notify tx completion for this desc
  3313. * @soc: core txrx main context
  3314. * @vdev: datapath vdev handle
  3315. * @tx_desc: tx desc
  3316. * @netbuf: buffer
  3317. * @status: tx status
  3318. *
  3319. * Return: none
  3320. */
  3321. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3322. struct dp_vdev *vdev,
  3323. struct dp_tx_desc_s *tx_desc,
  3324. qdf_nbuf_t netbuf,
  3325. uint8_t status)
  3326. {
  3327. void *osif_dev;
  3328. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3329. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3330. qdf_assert(tx_desc);
  3331. dp_tx_flow_pool_lock(soc, tx_desc);
  3332. if (!vdev ||
  3333. !vdev->osif_vdev) {
  3334. dp_tx_flow_pool_unlock(soc, tx_desc);
  3335. return;
  3336. }
  3337. osif_dev = vdev->osif_vdev;
  3338. tx_compl_cbk = vdev->tx_comp;
  3339. dp_tx_flow_pool_unlock(soc, tx_desc);
  3340. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3341. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3342. if (tx_compl_cbk)
  3343. tx_compl_cbk(netbuf, osif_dev, flag);
  3344. }
  3345. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3346. * @pdev: pdev handle
  3347. * @tid: tid value
  3348. * @txdesc_ts: timestamp from txdesc
  3349. * @ppdu_id: ppdu id
  3350. *
  3351. * Return: none
  3352. */
  3353. #ifdef FEATURE_PERPKT_INFO
  3354. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3355. struct dp_peer *peer,
  3356. uint8_t tid,
  3357. uint64_t txdesc_ts,
  3358. uint32_t ppdu_id)
  3359. {
  3360. uint64_t delta_ms;
  3361. struct cdp_tx_sojourn_stats *sojourn_stats;
  3362. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3363. return;
  3364. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3365. tid >= CDP_DATA_TID_MAX))
  3366. return;
  3367. if (qdf_unlikely(!pdev->sojourn_buf))
  3368. return;
  3369. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3370. qdf_nbuf_data(pdev->sojourn_buf);
  3371. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3372. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3373. txdesc_ts;
  3374. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3375. delta_ms);
  3376. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3377. sojourn_stats->num_msdus[tid] = 1;
  3378. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3379. peer->avg_sojourn_msdu[tid].internal;
  3380. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3381. pdev->sojourn_buf, HTT_INVALID_PEER,
  3382. WDI_NO_VAL, pdev->pdev_id);
  3383. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3384. sojourn_stats->num_msdus[tid] = 0;
  3385. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3386. }
  3387. #else
  3388. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3389. struct dp_peer *peer,
  3390. uint8_t tid,
  3391. uint64_t txdesc_ts,
  3392. uint32_t ppdu_id)
  3393. {
  3394. }
  3395. #endif
  3396. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3397. /**
  3398. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3399. * @soc: dp_soc handle
  3400. * @desc: Tx Descriptor
  3401. * @ts: HAL Tx completion descriptor contents
  3402. *
  3403. * This function is used to send tx completion to packet capture
  3404. */
  3405. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3406. struct dp_tx_desc_s *desc,
  3407. struct hal_tx_completion_status *ts)
  3408. {
  3409. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3410. desc, ts->peer_id,
  3411. WDI_NO_VAL, desc->pdev->pdev_id);
  3412. }
  3413. #endif
  3414. /**
  3415. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3416. * @soc: DP Soc handle
  3417. * @tx_desc: software Tx descriptor
  3418. * @ts : Tx completion status from HAL/HTT descriptor
  3419. *
  3420. * Return: none
  3421. */
  3422. static inline void
  3423. dp_tx_comp_process_desc(struct dp_soc *soc,
  3424. struct dp_tx_desc_s *desc,
  3425. struct hal_tx_completion_status *ts,
  3426. struct dp_peer *peer)
  3427. {
  3428. uint64_t time_latency = 0;
  3429. /*
  3430. * m_copy/tx_capture modes are not supported for
  3431. * scatter gather packets
  3432. */
  3433. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3434. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3435. desc->timestamp);
  3436. }
  3437. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3438. if (!(desc->msdu_ext_desc)) {
  3439. dp_tx_enh_unmap(soc, desc);
  3440. if (QDF_STATUS_SUCCESS ==
  3441. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3442. return;
  3443. }
  3444. if (QDF_STATUS_SUCCESS ==
  3445. dp_get_completion_indication_for_stack(soc,
  3446. desc->pdev,
  3447. peer, ts,
  3448. desc->nbuf,
  3449. time_latency)) {
  3450. dp_send_completion_to_stack(soc,
  3451. desc->pdev,
  3452. ts->peer_id,
  3453. ts->ppdu_id,
  3454. desc->nbuf);
  3455. return;
  3456. }
  3457. }
  3458. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3459. dp_tx_comp_free_buf(soc, desc);
  3460. }
  3461. #ifdef DISABLE_DP_STATS
  3462. /**
  3463. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3464. * @soc: core txrx main context
  3465. * @tx_desc: tx desc
  3466. * @status: tx status
  3467. *
  3468. * Return: none
  3469. */
  3470. static inline
  3471. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3472. struct dp_vdev *vdev,
  3473. struct dp_tx_desc_s *tx_desc,
  3474. uint8_t status)
  3475. {
  3476. }
  3477. #else
  3478. static inline
  3479. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3480. struct dp_vdev *vdev,
  3481. struct dp_tx_desc_s *tx_desc,
  3482. uint8_t status)
  3483. {
  3484. void *osif_dev;
  3485. ol_txrx_stats_rx_fp stats_cbk;
  3486. uint8_t pkt_type;
  3487. qdf_assert(tx_desc);
  3488. if (!vdev ||
  3489. !vdev->osif_vdev ||
  3490. !vdev->stats_cb)
  3491. return;
  3492. osif_dev = vdev->osif_vdev;
  3493. stats_cbk = vdev->stats_cb;
  3494. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3495. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3496. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3497. &pkt_type);
  3498. }
  3499. #endif
  3500. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3501. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3502. uint32_t delta_tsf)
  3503. {
  3504. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3505. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3506. DP_MOD_ID_CDP);
  3507. if (!vdev) {
  3508. dp_err_rl("vdev %d does not exist", vdev_id);
  3509. return;
  3510. }
  3511. vdev->delta_tsf = delta_tsf;
  3512. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3513. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3514. }
  3515. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3516. uint8_t vdev_id, bool enable)
  3517. {
  3518. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3519. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3520. DP_MOD_ID_CDP);
  3521. if (!vdev) {
  3522. dp_err_rl("vdev %d does not exist", vdev_id);
  3523. return QDF_STATUS_E_FAILURE;
  3524. }
  3525. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3526. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3527. return QDF_STATUS_SUCCESS;
  3528. }
  3529. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3530. uint32_t *val)
  3531. {
  3532. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3533. struct dp_vdev *vdev;
  3534. uint32_t delay_accum;
  3535. uint32_t pkts_accum;
  3536. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3537. if (!vdev) {
  3538. dp_err_rl("vdev %d does not exist", vdev_id);
  3539. return QDF_STATUS_E_FAILURE;
  3540. }
  3541. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3542. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3543. return QDF_STATUS_E_FAILURE;
  3544. }
  3545. /* Average uplink delay based on current accumulated values */
  3546. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3547. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3548. *val = delay_accum / pkts_accum;
  3549. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3550. delay_accum, pkts_accum);
  3551. /* Reset accumulated values to 0 */
  3552. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3553. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3554. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3555. return QDF_STATUS_SUCCESS;
  3556. }
  3557. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3558. struct hal_tx_completion_status *ts)
  3559. {
  3560. uint32_t buffer_ts;
  3561. uint32_t delta_tsf;
  3562. uint32_t ul_delay;
  3563. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3564. if (!ts->valid)
  3565. return;
  3566. if (qdf_unlikely(!vdev)) {
  3567. dp_info_rl("vdev is null or delete in progrss");
  3568. return;
  3569. }
  3570. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3571. return;
  3572. delta_tsf = vdev->delta_tsf;
  3573. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3574. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3575. * valid up to 29 bits.
  3576. */
  3577. buffer_ts = ts->buffer_timestamp << 10;
  3578. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3579. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3580. if (ul_delay > 0x1000000) {
  3581. dp_info_rl("----------------------\n"
  3582. "Tx completion status:\n"
  3583. "----------------------\n"
  3584. "release_src = %d\n"
  3585. "ppdu_id = 0x%x\n"
  3586. "release_reason = %d\n"
  3587. "tsf = %u (0x%x)\n"
  3588. "buffer_timestamp = %u (0x%x)\n"
  3589. "delta_tsf = %u (0x%x)\n",
  3590. ts->release_src, ts->ppdu_id, ts->status,
  3591. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3592. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3593. return;
  3594. }
  3595. ul_delay /= 1000; /* in unit of ms */
  3596. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3597. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3598. }
  3599. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3600. static inline
  3601. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3602. struct hal_tx_completion_status *ts)
  3603. {
  3604. }
  3605. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3606. /**
  3607. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3608. * @soc: DP soc handle
  3609. * @tx_desc: software descriptor head pointer
  3610. * @ts: Tx completion status
  3611. * @peer: peer handle
  3612. * @ring_id: ring number
  3613. *
  3614. * Return: none
  3615. */
  3616. static inline
  3617. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3618. struct dp_tx_desc_s *tx_desc,
  3619. struct hal_tx_completion_status *ts,
  3620. struct dp_peer *peer, uint8_t ring_id)
  3621. {
  3622. uint32_t length;
  3623. qdf_ether_header_t *eh;
  3624. struct dp_vdev *vdev = NULL;
  3625. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3626. enum qdf_dp_tx_rx_status dp_status;
  3627. if (!nbuf) {
  3628. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3629. goto out;
  3630. }
  3631. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3632. length = qdf_nbuf_len(nbuf);
  3633. dp_status = dp_tx_hw_to_qdf(ts->status);
  3634. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3635. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3636. QDF_TRACE_DEFAULT_PDEV_ID,
  3637. qdf_nbuf_data_addr(nbuf),
  3638. sizeof(qdf_nbuf_data(nbuf)),
  3639. tx_desc->id, ts->status, dp_status));
  3640. dp_tx_comp_debug("-------------------- \n"
  3641. "Tx Completion Stats: \n"
  3642. "-------------------- \n"
  3643. "ack_frame_rssi = %d \n"
  3644. "first_msdu = %d \n"
  3645. "last_msdu = %d \n"
  3646. "msdu_part_of_amsdu = %d \n"
  3647. "rate_stats valid = %d \n"
  3648. "bw = %d \n"
  3649. "pkt_type = %d \n"
  3650. "stbc = %d \n"
  3651. "ldpc = %d \n"
  3652. "sgi = %d \n"
  3653. "mcs = %d \n"
  3654. "ofdma = %d \n"
  3655. "tones_in_ru = %d \n"
  3656. "tsf = %d \n"
  3657. "ppdu_id = %d \n"
  3658. "transmit_cnt = %d \n"
  3659. "tid = %d \n"
  3660. "peer_id = %d\n",
  3661. ts->ack_frame_rssi, ts->first_msdu,
  3662. ts->last_msdu, ts->msdu_part_of_amsdu,
  3663. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3664. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3665. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3666. ts->transmit_cnt, ts->tid, ts->peer_id);
  3667. /* Update SoC level stats */
  3668. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3669. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3670. if (!peer) {
  3671. dp_info_rl("peer is null or deletion in progress");
  3672. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3673. goto out;
  3674. }
  3675. vdev = peer->vdev;
  3676. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3677. dp_tx_update_uplink_delay(soc, vdev, ts);
  3678. /* Update per-packet stats for mesh mode */
  3679. if (qdf_unlikely(vdev->mesh_vdev) &&
  3680. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3681. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3682. /* Update peer level stats */
  3683. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3684. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3685. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3686. if ((peer->vdev->tx_encap_type ==
  3687. htt_cmn_pkt_type_ethernet) &&
  3688. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3689. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3690. }
  3691. }
  3692. } else {
  3693. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3694. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3695. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3696. if (qdf_unlikely(peer->in_twt)) {
  3697. DP_STATS_INC_PKT(peer,
  3698. tx.tx_success_twt,
  3699. 1, length);
  3700. }
  3701. }
  3702. }
  3703. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3704. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3705. #ifdef QCA_SUPPORT_RDK_STATS
  3706. if (soc->rdkstats_enabled)
  3707. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3708. tx_desc->timestamp,
  3709. ts->ppdu_id);
  3710. #endif
  3711. out:
  3712. return;
  3713. }
  3714. /**
  3715. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3716. * @soc: core txrx main context
  3717. * @comp_head: software descriptor head pointer
  3718. * @ring_id: ring number
  3719. *
  3720. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3721. * and release the software descriptors after processing is complete
  3722. *
  3723. * Return: none
  3724. */
  3725. static void
  3726. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3727. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3728. {
  3729. struct dp_tx_desc_s *desc;
  3730. struct dp_tx_desc_s *next;
  3731. struct hal_tx_completion_status ts;
  3732. struct dp_peer *peer = NULL;
  3733. uint16_t peer_id = DP_INVALID_PEER;
  3734. qdf_nbuf_t netbuf;
  3735. desc = comp_head;
  3736. while (desc) {
  3737. if (peer_id != desc->peer_id) {
  3738. if (peer)
  3739. dp_peer_unref_delete(peer,
  3740. DP_MOD_ID_TX_COMP);
  3741. peer_id = desc->peer_id;
  3742. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3743. DP_MOD_ID_TX_COMP);
  3744. }
  3745. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3746. struct dp_pdev *pdev = desc->pdev;
  3747. if (qdf_likely(peer)) {
  3748. /*
  3749. * Increment peer statistics
  3750. * Minimal statistics update done here
  3751. */
  3752. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3753. desc->length);
  3754. if (desc->tx_status !=
  3755. HAL_TX_TQM_RR_FRAME_ACKED)
  3756. DP_STATS_INC(peer, tx.tx_failed, 1);
  3757. }
  3758. qdf_assert(pdev);
  3759. dp_tx_outstanding_dec(pdev);
  3760. /*
  3761. * Calling a QDF WRAPPER here is creating signifcant
  3762. * performance impact so avoided the wrapper call here
  3763. */
  3764. next = desc->next;
  3765. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3766. desc->id, DP_TX_COMP_UNMAP);
  3767. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3768. desc->nbuf,
  3769. desc->dma_addr,
  3770. QDF_DMA_TO_DEVICE,
  3771. desc->length);
  3772. qdf_nbuf_free(desc->nbuf);
  3773. dp_tx_desc_free(soc, desc, desc->pool_id);
  3774. desc = next;
  3775. continue;
  3776. }
  3777. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3778. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3779. netbuf = desc->nbuf;
  3780. /* check tx complete notification */
  3781. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3782. dp_tx_notify_completion(soc, peer->vdev, desc,
  3783. netbuf, ts.status);
  3784. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3785. next = desc->next;
  3786. dp_tx_desc_release(desc, desc->pool_id);
  3787. desc = next;
  3788. }
  3789. if (peer)
  3790. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3791. }
  3792. /**
  3793. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3794. * @soc: Handle to DP soc structure
  3795. * @tx_desc: software descriptor head pointer
  3796. * @status : Tx completion status from HTT descriptor
  3797. * @ring_id: ring number
  3798. *
  3799. * This function will process HTT Tx indication messages from Target
  3800. *
  3801. * Return: none
  3802. */
  3803. static
  3804. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3805. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3806. uint8_t ring_id)
  3807. {
  3808. uint8_t tx_status;
  3809. struct dp_pdev *pdev;
  3810. struct dp_vdev *vdev;
  3811. struct hal_tx_completion_status ts = {0};
  3812. uint32_t *htt_desc = (uint32_t *)status;
  3813. struct dp_peer *peer;
  3814. struct cdp_tid_tx_stats *tid_stats = NULL;
  3815. struct htt_soc *htt_handle;
  3816. uint8_t vdev_id;
  3817. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3818. htt_handle = (struct htt_soc *)soc->htt_handle;
  3819. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3820. /*
  3821. * There can be scenario where WBM consuming descriptor enqueued
  3822. * from TQM2WBM first and TQM completion can happen before MEC
  3823. * notification comes from FW2WBM. Avoid access any field of tx
  3824. * descriptor in case of MEC notify.
  3825. */
  3826. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3827. qdf_assert_always(!soc->mec_fw_offload);
  3828. /*
  3829. * Get vdev id from HTT status word in case of MEC
  3830. * notification
  3831. */
  3832. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3833. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3834. return;
  3835. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3836. DP_MOD_ID_HTT_COMP);
  3837. if (!vdev)
  3838. return;
  3839. dp_tx_mec_handler(vdev, status);
  3840. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3841. return;
  3842. }
  3843. /*
  3844. * If the descriptor is already freed in vdev_detach,
  3845. * continue to next descriptor
  3846. */
  3847. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3848. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3849. return;
  3850. }
  3851. pdev = tx_desc->pdev;
  3852. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3853. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3854. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3855. dp_tx_comp_free_buf(soc, tx_desc);
  3856. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3857. return;
  3858. }
  3859. qdf_assert(tx_desc->pdev);
  3860. vdev_id = tx_desc->vdev_id;
  3861. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3862. DP_MOD_ID_HTT_COMP);
  3863. if (!vdev)
  3864. return;
  3865. switch (tx_status) {
  3866. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3867. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3868. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3869. {
  3870. uint8_t tid;
  3871. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3872. ts.peer_id =
  3873. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3874. htt_desc[2]);
  3875. ts.tid =
  3876. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3877. htt_desc[2]);
  3878. } else {
  3879. ts.peer_id = HTT_INVALID_PEER;
  3880. ts.tid = HTT_INVALID_TID;
  3881. }
  3882. ts.ppdu_id =
  3883. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3884. htt_desc[1]);
  3885. ts.ack_frame_rssi =
  3886. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3887. htt_desc[1]);
  3888. ts.tsf = htt_desc[3];
  3889. ts.first_msdu = 1;
  3890. ts.last_msdu = 1;
  3891. tid = ts.tid;
  3892. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3893. tid = CDP_MAX_DATA_TIDS - 1;
  3894. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3895. if (qdf_unlikely(pdev->delay_stats_flag))
  3896. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3897. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3898. tid_stats->htt_status_cnt[tx_status]++;
  3899. }
  3900. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3901. DP_MOD_ID_HTT_COMP);
  3902. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3903. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3904. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3905. if (qdf_likely(peer))
  3906. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3907. break;
  3908. }
  3909. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3910. {
  3911. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3912. break;
  3913. }
  3914. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3915. {
  3916. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3917. break;
  3918. }
  3919. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  3920. {
  3921. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3922. goto release_tx_desc;
  3923. }
  3924. default:
  3925. dp_tx_comp_alert("Invalid HTT tx_status %d\n",
  3926. tx_status);
  3927. goto release_tx_desc;
  3928. }
  3929. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3930. return;
  3931. release_tx_desc:
  3932. dp_tx_comp_free_buf(soc, tx_desc);
  3933. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3934. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3935. }
  3936. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3937. static inline
  3938. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3939. int max_reap_limit)
  3940. {
  3941. bool limit_hit = false;
  3942. limit_hit =
  3943. (num_reaped >= max_reap_limit) ? true : false;
  3944. if (limit_hit)
  3945. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3946. return limit_hit;
  3947. }
  3948. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3949. {
  3950. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3951. }
  3952. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3953. {
  3954. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3955. return cfg->tx_comp_loop_pkt_limit;
  3956. }
  3957. #else
  3958. static inline
  3959. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3960. int max_reap_limit)
  3961. {
  3962. return false;
  3963. }
  3964. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3965. {
  3966. return false;
  3967. }
  3968. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3969. {
  3970. return 0;
  3971. }
  3972. #endif
  3973. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  3974. static inline int
  3975. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3976. int *max_reap_limit)
  3977. {
  3978. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  3979. max_reap_limit);
  3980. }
  3981. #else
  3982. static inline int
  3983. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3984. int *max_reap_limit)
  3985. {
  3986. return 0;
  3987. }
  3988. #endif
  3989. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3990. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3991. uint32_t quota)
  3992. {
  3993. void *tx_comp_hal_desc;
  3994. uint8_t buffer_src;
  3995. struct dp_tx_desc_s *tx_desc = NULL;
  3996. struct dp_tx_desc_s *head_desc = NULL;
  3997. struct dp_tx_desc_s *tail_desc = NULL;
  3998. uint32_t num_processed = 0;
  3999. uint32_t count;
  4000. uint32_t num_avail_for_reap = 0;
  4001. bool force_break = false;
  4002. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4003. int max_reap_limit, ring_near_full;
  4004. DP_HIST_INIT();
  4005. more_data:
  4006. /* Re-initialize local variables to be re-used */
  4007. head_desc = NULL;
  4008. tail_desc = NULL;
  4009. count = 0;
  4010. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4011. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4012. &max_reap_limit);
  4013. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4014. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4015. return 0;
  4016. }
  4017. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4018. if (num_avail_for_reap >= quota)
  4019. num_avail_for_reap = quota;
  4020. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4021. /* Find head descriptor from completion ring */
  4022. while (qdf_likely(num_avail_for_reap--)) {
  4023. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4024. if (qdf_unlikely(!tx_comp_hal_desc))
  4025. break;
  4026. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4027. tx_comp_hal_desc);
  4028. /* If this buffer was not released by TQM or FW, then it is not
  4029. * Tx completion indication, assert */
  4030. if (qdf_unlikely(buffer_src !=
  4031. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4032. (qdf_unlikely(buffer_src !=
  4033. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4034. uint8_t wbm_internal_error;
  4035. dp_err_rl(
  4036. "Tx comp release_src != TQM | FW but from %d",
  4037. buffer_src);
  4038. hal_dump_comp_desc(tx_comp_hal_desc);
  4039. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4040. /* When WBM sees NULL buffer_addr_info in any of
  4041. * ingress rings it sends an error indication,
  4042. * with wbm_internal_error=1, to a specific ring.
  4043. * The WBM2SW ring used to indicate these errors is
  4044. * fixed in HW, and that ring is being used as Tx
  4045. * completion ring. These errors are not related to
  4046. * Tx completions, and should just be ignored
  4047. */
  4048. wbm_internal_error = hal_get_wbm_internal_error(
  4049. soc->hal_soc,
  4050. tx_comp_hal_desc);
  4051. if (wbm_internal_error) {
  4052. dp_err_rl("Tx comp wbm_internal_error!!");
  4053. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4054. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4055. buffer_src)
  4056. dp_handle_wbm_internal_error(
  4057. soc,
  4058. tx_comp_hal_desc,
  4059. hal_tx_comp_get_buffer_type(
  4060. tx_comp_hal_desc));
  4061. } else {
  4062. dp_err_rl("Tx comp wbm_internal_error false");
  4063. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4064. }
  4065. continue;
  4066. }
  4067. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4068. tx_comp_hal_desc,
  4069. &tx_desc);
  4070. if (!tx_desc) {
  4071. dp_err("unable to retrieve tx_desc!");
  4072. QDF_BUG(0);
  4073. continue;
  4074. }
  4075. tx_desc->buffer_src = buffer_src;
  4076. /*
  4077. * If the release source is FW, process the HTT status
  4078. */
  4079. if (qdf_unlikely(buffer_src ==
  4080. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4081. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4082. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4083. htt_tx_status);
  4084. dp_tx_process_htt_completion(soc, tx_desc,
  4085. htt_tx_status, ring_id);
  4086. } else {
  4087. tx_desc->peer_id =
  4088. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  4089. tx_desc->tx_status =
  4090. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4091. tx_desc->buffer_src = buffer_src;
  4092. /*
  4093. * If the fast completion mode is enabled extended
  4094. * metadata from descriptor is not copied
  4095. */
  4096. if (qdf_likely(tx_desc->flags &
  4097. DP_TX_DESC_FLAG_SIMPLE))
  4098. goto add_to_pool;
  4099. /*
  4100. * If the descriptor is already freed in vdev_detach,
  4101. * continue to next descriptor
  4102. */
  4103. if (qdf_unlikely
  4104. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4105. !tx_desc->flags)) {
  4106. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4107. tx_desc->id);
  4108. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4109. continue;
  4110. }
  4111. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4112. dp_tx_comp_info_rl("pdev in down state %d",
  4113. tx_desc->id);
  4114. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4115. dp_tx_comp_free_buf(soc, tx_desc);
  4116. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4117. goto next_desc;
  4118. }
  4119. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4120. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4121. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4122. tx_desc->flags, tx_desc->id);
  4123. qdf_assert_always(0);
  4124. }
  4125. /* Collect hw completion contents */
  4126. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4127. &tx_desc->comp, 1);
  4128. add_to_pool:
  4129. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4130. /* First ring descriptor on the cycle */
  4131. if (!head_desc) {
  4132. head_desc = tx_desc;
  4133. tail_desc = tx_desc;
  4134. }
  4135. tail_desc->next = tx_desc;
  4136. tx_desc->next = NULL;
  4137. tail_desc = tx_desc;
  4138. }
  4139. next_desc:
  4140. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4141. /*
  4142. * Processed packet count is more than given quota
  4143. * stop to processing
  4144. */
  4145. count++;
  4146. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4147. break;
  4148. }
  4149. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4150. /* Process the reaped descriptors */
  4151. if (head_desc)
  4152. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4153. /*
  4154. * If we are processing in near-full condition, there are 3 scenario
  4155. * 1) Ring entries has reached critical state
  4156. * 2) Ring entries are still near high threshold
  4157. * 3) Ring entries are below the safe level
  4158. *
  4159. * One more loop will move te state to normal processing and yield
  4160. */
  4161. if (ring_near_full)
  4162. goto more_data;
  4163. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4164. if (num_processed >= quota)
  4165. force_break = true;
  4166. if (!force_break &&
  4167. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4168. hal_ring_hdl)) {
  4169. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4170. if (!hif_exec_should_yield(soc->hif_handle,
  4171. int_ctx->dp_intr_id))
  4172. goto more_data;
  4173. }
  4174. }
  4175. DP_TX_HIST_STATS_PER_PDEV();
  4176. return num_processed;
  4177. }
  4178. #ifdef FEATURE_WLAN_TDLS
  4179. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4180. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4181. {
  4182. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4183. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4184. DP_MOD_ID_TDLS);
  4185. if (!vdev) {
  4186. dp_err("vdev handle for id %d is NULL", vdev_id);
  4187. return NULL;
  4188. }
  4189. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4190. vdev->is_tdls_frame = true;
  4191. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4192. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4193. }
  4194. #endif
  4195. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4196. {
  4197. struct wlan_cfg_dp_soc_ctxt *cfg;
  4198. struct dp_soc *soc;
  4199. soc = vdev->pdev->soc;
  4200. if (!soc)
  4201. return;
  4202. cfg = soc->wlan_cfg_ctx;
  4203. if (!cfg)
  4204. return;
  4205. if (vdev->opmode == wlan_op_mode_ndi)
  4206. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4207. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4208. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4209. (vdev->subtype == wlan_op_subtype_p2p_go))
  4210. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4211. else
  4212. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4213. }
  4214. /**
  4215. * dp_tx_vdev_attach() - attach vdev to dp tx
  4216. * @vdev: virtual device instance
  4217. *
  4218. * Return: QDF_STATUS_SUCCESS: success
  4219. * QDF_STATUS_E_RESOURCES: Error return
  4220. */
  4221. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4222. {
  4223. int pdev_id;
  4224. /*
  4225. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4226. */
  4227. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4228. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4229. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4230. vdev->vdev_id);
  4231. pdev_id =
  4232. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4233. vdev->pdev->pdev_id);
  4234. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4235. /*
  4236. * Set HTT Extension Valid bit to 0 by default
  4237. */
  4238. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4239. dp_tx_vdev_update_search_flags(vdev);
  4240. dp_tx_vdev_update_feature_flags(vdev);
  4241. return QDF_STATUS_SUCCESS;
  4242. }
  4243. #ifndef FEATURE_WDS
  4244. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4245. {
  4246. return false;
  4247. }
  4248. #endif
  4249. /**
  4250. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4251. * @vdev: virtual device instance
  4252. *
  4253. * Return: void
  4254. *
  4255. */
  4256. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4257. {
  4258. struct dp_soc *soc = vdev->pdev->soc;
  4259. /*
  4260. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4261. * for TDLS link
  4262. *
  4263. * Enable AddrY (SA based search) only for non-WDS STA and
  4264. * ProxySTA VAP (in HKv1) modes.
  4265. *
  4266. * In all other VAP modes, only DA based search should be
  4267. * enabled
  4268. */
  4269. if (vdev->opmode == wlan_op_mode_sta &&
  4270. vdev->tdls_link_connected)
  4271. vdev->hal_desc_addr_search_flags =
  4272. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4273. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4274. !dp_tx_da_search_override(vdev))
  4275. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4276. else
  4277. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4278. if (vdev->opmode == wlan_op_mode_sta)
  4279. vdev->search_type = soc->sta_mode_search_policy;
  4280. else
  4281. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4282. }
  4283. static inline bool
  4284. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4285. struct dp_vdev *vdev,
  4286. struct dp_tx_desc_s *tx_desc)
  4287. {
  4288. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4289. return false;
  4290. /*
  4291. * if vdev is given, then only check whether desc
  4292. * vdev match. if vdev is NULL, then check whether
  4293. * desc pdev match.
  4294. */
  4295. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4296. (tx_desc->pdev == pdev);
  4297. }
  4298. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4299. /**
  4300. * dp_tx_desc_flush() - release resources associated
  4301. * to TX Desc
  4302. *
  4303. * @dp_pdev: Handle to DP pdev structure
  4304. * @vdev: virtual device instance
  4305. * NULL: no specific Vdev is required and check all allcated TX desc
  4306. * on this pdev.
  4307. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4308. *
  4309. * @force_free:
  4310. * true: flush the TX desc.
  4311. * false: only reset the Vdev in each allocated TX desc
  4312. * that associated to current Vdev.
  4313. *
  4314. * This function will go through the TX desc pool to flush
  4315. * the outstanding TX data or reset Vdev to NULL in associated TX
  4316. * Desc.
  4317. */
  4318. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4319. bool force_free)
  4320. {
  4321. uint8_t i;
  4322. uint32_t j;
  4323. uint32_t num_desc, page_id, offset;
  4324. uint16_t num_desc_per_page;
  4325. struct dp_soc *soc = pdev->soc;
  4326. struct dp_tx_desc_s *tx_desc = NULL;
  4327. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4328. if (!vdev && !force_free) {
  4329. dp_err("Reset TX desc vdev, Vdev param is required!");
  4330. return;
  4331. }
  4332. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4333. tx_desc_pool = &soc->tx_desc[i];
  4334. if (!(tx_desc_pool->pool_size) ||
  4335. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4336. !(tx_desc_pool->desc_pages.cacheable_pages))
  4337. continue;
  4338. /*
  4339. * Add flow pool lock protection in case pool is freed
  4340. * due to all tx_desc is recycled when handle TX completion.
  4341. * this is not necessary when do force flush as:
  4342. * a. double lock will happen if dp_tx_desc_release is
  4343. * also trying to acquire it.
  4344. * b. dp interrupt has been disabled before do force TX desc
  4345. * flush in dp_pdev_deinit().
  4346. */
  4347. if (!force_free)
  4348. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4349. num_desc = tx_desc_pool->pool_size;
  4350. num_desc_per_page =
  4351. tx_desc_pool->desc_pages.num_element_per_page;
  4352. for (j = 0; j < num_desc; j++) {
  4353. page_id = j / num_desc_per_page;
  4354. offset = j % num_desc_per_page;
  4355. if (qdf_unlikely(!(tx_desc_pool->
  4356. desc_pages.cacheable_pages)))
  4357. break;
  4358. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4359. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4360. /*
  4361. * Free TX desc if force free is
  4362. * required, otherwise only reset vdev
  4363. * in this TX desc.
  4364. */
  4365. if (force_free) {
  4366. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4367. dp_tx_comp_free_buf(soc, tx_desc);
  4368. dp_tx_desc_release(tx_desc, i);
  4369. } else {
  4370. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4371. }
  4372. }
  4373. }
  4374. if (!force_free)
  4375. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4376. }
  4377. }
  4378. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4379. /**
  4380. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4381. *
  4382. * @soc: Handle to DP soc structure
  4383. * @tx_desc: pointer of one TX desc
  4384. * @desc_pool_id: TX Desc pool id
  4385. */
  4386. static inline void
  4387. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4388. uint8_t desc_pool_id)
  4389. {
  4390. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4391. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4392. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4393. }
  4394. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4395. bool force_free)
  4396. {
  4397. uint8_t i, num_pool;
  4398. uint32_t j;
  4399. uint32_t num_desc, page_id, offset;
  4400. uint16_t num_desc_per_page;
  4401. struct dp_soc *soc = pdev->soc;
  4402. struct dp_tx_desc_s *tx_desc = NULL;
  4403. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4404. if (!vdev && !force_free) {
  4405. dp_err("Reset TX desc vdev, Vdev param is required!");
  4406. return;
  4407. }
  4408. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4409. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4410. for (i = 0; i < num_pool; i++) {
  4411. tx_desc_pool = &soc->tx_desc[i];
  4412. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4413. continue;
  4414. num_desc_per_page =
  4415. tx_desc_pool->desc_pages.num_element_per_page;
  4416. for (j = 0; j < num_desc; j++) {
  4417. page_id = j / num_desc_per_page;
  4418. offset = j % num_desc_per_page;
  4419. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4420. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4421. if (force_free) {
  4422. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4423. dp_tx_comp_free_buf(soc, tx_desc);
  4424. dp_tx_desc_release(tx_desc, i);
  4425. } else {
  4426. dp_tx_desc_reset_vdev(soc, tx_desc,
  4427. i);
  4428. }
  4429. }
  4430. }
  4431. }
  4432. }
  4433. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4434. /**
  4435. * dp_tx_vdev_detach() - detach vdev from dp tx
  4436. * @vdev: virtual device instance
  4437. *
  4438. * Return: QDF_STATUS_SUCCESS: success
  4439. * QDF_STATUS_E_RESOURCES: Error return
  4440. */
  4441. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4442. {
  4443. struct dp_pdev *pdev = vdev->pdev;
  4444. /* Reset TX desc associated to this Vdev as NULL */
  4445. dp_tx_desc_flush(pdev, vdev, false);
  4446. return QDF_STATUS_SUCCESS;
  4447. }
  4448. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4449. /* Pools will be allocated dynamically */
  4450. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4451. int num_desc)
  4452. {
  4453. uint8_t i;
  4454. for (i = 0; i < num_pool; i++) {
  4455. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4456. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4457. }
  4458. return QDF_STATUS_SUCCESS;
  4459. }
  4460. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4461. int num_desc)
  4462. {
  4463. return QDF_STATUS_SUCCESS;
  4464. }
  4465. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4466. {
  4467. }
  4468. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4469. {
  4470. uint8_t i;
  4471. for (i = 0; i < num_pool; i++)
  4472. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4473. }
  4474. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4475. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4476. int num_desc)
  4477. {
  4478. uint8_t i, count;
  4479. /* Allocate software Tx descriptor pools */
  4480. for (i = 0; i < num_pool; i++) {
  4481. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4483. FL("Tx Desc Pool alloc %d failed %pK"),
  4484. i, soc);
  4485. goto fail;
  4486. }
  4487. }
  4488. return QDF_STATUS_SUCCESS;
  4489. fail:
  4490. for (count = 0; count < i; count++)
  4491. dp_tx_desc_pool_free(soc, count);
  4492. return QDF_STATUS_E_NOMEM;
  4493. }
  4494. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4495. int num_desc)
  4496. {
  4497. uint8_t i;
  4498. for (i = 0; i < num_pool; i++) {
  4499. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4500. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4501. FL("Tx Desc Pool init %d failed %pK"),
  4502. i, soc);
  4503. return QDF_STATUS_E_NOMEM;
  4504. }
  4505. }
  4506. return QDF_STATUS_SUCCESS;
  4507. }
  4508. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4509. {
  4510. uint8_t i;
  4511. for (i = 0; i < num_pool; i++)
  4512. dp_tx_desc_pool_deinit(soc, i);
  4513. }
  4514. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4515. {
  4516. uint8_t i;
  4517. for (i = 0; i < num_pool; i++)
  4518. dp_tx_desc_pool_free(soc, i);
  4519. }
  4520. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4521. /**
  4522. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4523. * @soc: core txrx main context
  4524. * @num_pool: number of pools
  4525. *
  4526. */
  4527. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4528. {
  4529. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4530. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4531. }
  4532. /**
  4533. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4534. * @soc: core txrx main context
  4535. * @num_pool: number of pools
  4536. *
  4537. */
  4538. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4539. {
  4540. dp_tx_tso_desc_pool_free(soc, num_pool);
  4541. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4542. }
  4543. /**
  4544. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4545. * @soc: core txrx main context
  4546. *
  4547. * This function frees all tx related descriptors as below
  4548. * 1. Regular TX descriptors (static pools)
  4549. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4550. * 3. TSO descriptors
  4551. *
  4552. */
  4553. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4554. {
  4555. uint8_t num_pool;
  4556. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4557. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4558. dp_tx_ext_desc_pool_free(soc, num_pool);
  4559. dp_tx_delete_static_pools(soc, num_pool);
  4560. }
  4561. /**
  4562. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4563. * @soc: core txrx main context
  4564. *
  4565. * This function de-initializes all tx related descriptors as below
  4566. * 1. Regular TX descriptors (static pools)
  4567. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4568. * 3. TSO descriptors
  4569. *
  4570. */
  4571. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4572. {
  4573. uint8_t num_pool;
  4574. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4575. dp_tx_flow_control_deinit(soc);
  4576. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4577. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4578. dp_tx_deinit_static_pools(soc, num_pool);
  4579. }
  4580. /**
  4581. * dp_tso_attach() - TSO attach handler
  4582. * @txrx_soc: Opaque Dp handle
  4583. *
  4584. * Reserve TSO descriptor buffers
  4585. *
  4586. * Return: QDF_STATUS_E_FAILURE on failure or
  4587. * QDF_STATUS_SUCCESS on success
  4588. */
  4589. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4590. uint8_t num_pool,
  4591. uint16_t num_desc)
  4592. {
  4593. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4594. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4595. return QDF_STATUS_E_FAILURE;
  4596. }
  4597. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4598. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4599. num_pool, soc);
  4600. return QDF_STATUS_E_FAILURE;
  4601. }
  4602. return QDF_STATUS_SUCCESS;
  4603. }
  4604. /**
  4605. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4606. * @soc: DP soc handle
  4607. * @num_pool: Number of pools
  4608. * @num_desc: Number of descriptors
  4609. *
  4610. * Initialize TSO descriptor pools
  4611. *
  4612. * Return: QDF_STATUS_E_FAILURE on failure or
  4613. * QDF_STATUS_SUCCESS on success
  4614. */
  4615. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4616. uint8_t num_pool,
  4617. uint16_t num_desc)
  4618. {
  4619. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4620. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4621. return QDF_STATUS_E_FAILURE;
  4622. }
  4623. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4624. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4625. num_pool, soc);
  4626. return QDF_STATUS_E_FAILURE;
  4627. }
  4628. return QDF_STATUS_SUCCESS;
  4629. }
  4630. /**
  4631. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4632. * @soc: core txrx main context
  4633. *
  4634. * This function allocates memory for following descriptor pools
  4635. * 1. regular sw tx descriptor pools (static pools)
  4636. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4637. * 3. TSO descriptor pools
  4638. *
  4639. * Return: QDF_STATUS_SUCCESS: success
  4640. * QDF_STATUS_E_RESOURCES: Error return
  4641. */
  4642. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4643. {
  4644. uint8_t num_pool;
  4645. uint32_t num_desc;
  4646. uint32_t num_ext_desc;
  4647. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4648. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4649. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4651. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4652. __func__, num_pool, num_desc);
  4653. if ((num_pool > MAX_TXDESC_POOLS) ||
  4654. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4655. goto fail1;
  4656. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4657. goto fail1;
  4658. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4659. goto fail2;
  4660. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4661. return QDF_STATUS_SUCCESS;
  4662. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4663. goto fail3;
  4664. return QDF_STATUS_SUCCESS;
  4665. fail3:
  4666. dp_tx_ext_desc_pool_free(soc, num_pool);
  4667. fail2:
  4668. dp_tx_delete_static_pools(soc, num_pool);
  4669. fail1:
  4670. return QDF_STATUS_E_RESOURCES;
  4671. }
  4672. /**
  4673. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4674. * @soc: core txrx main context
  4675. *
  4676. * This function initializes the following TX descriptor pools
  4677. * 1. regular sw tx descriptor pools (static pools)
  4678. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4679. * 3. TSO descriptor pools
  4680. *
  4681. * Return: QDF_STATUS_SUCCESS: success
  4682. * QDF_STATUS_E_RESOURCES: Error return
  4683. */
  4684. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4685. {
  4686. uint8_t num_pool;
  4687. uint32_t num_desc;
  4688. uint32_t num_ext_desc;
  4689. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4690. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4691. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4692. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4693. goto fail1;
  4694. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4695. goto fail2;
  4696. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4697. return QDF_STATUS_SUCCESS;
  4698. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4699. goto fail3;
  4700. dp_tx_flow_control_init(soc);
  4701. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4702. return QDF_STATUS_SUCCESS;
  4703. fail3:
  4704. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4705. fail2:
  4706. dp_tx_deinit_static_pools(soc, num_pool);
  4707. fail1:
  4708. return QDF_STATUS_E_RESOURCES;
  4709. }
  4710. /**
  4711. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4712. * @txrx_soc: dp soc handle
  4713. *
  4714. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4715. * QDF_STATUS_E_FAILURE
  4716. */
  4717. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4718. {
  4719. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4720. uint8_t num_pool;
  4721. uint32_t num_desc;
  4722. uint32_t num_ext_desc;
  4723. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4724. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4725. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4726. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4727. return QDF_STATUS_E_FAILURE;
  4728. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4729. return QDF_STATUS_E_FAILURE;
  4730. return QDF_STATUS_SUCCESS;
  4731. }
  4732. /**
  4733. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4734. * @txrx_soc: dp soc handle
  4735. *
  4736. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4737. */
  4738. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4739. {
  4740. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4741. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4742. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4743. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4744. return QDF_STATUS_SUCCESS;
  4745. }