dp_be.c 28 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <wlan_utility.h>
  19. #include <dp_internal.h>
  20. #include <dp_htt.h>
  21. #include "dp_be.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_be_rx.h"
  24. #include <hal_be_api.h>
  25. /* Generic AST entry aging timer value */
  26. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  27. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  28. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  29. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  30. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  31. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  32. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  33. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  34. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  35. };
  36. #else
  37. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  38. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  39. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  40. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  41. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  42. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  43. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  44. };
  45. #endif
  46. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  47. {
  48. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  49. /* this is used only when dmac mode is enabled */
  50. soc->num_rx_refill_buf_rings = 1;
  51. }
  52. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  53. {
  54. switch (context_type) {
  55. case DP_CONTEXT_TYPE_SOC:
  56. return sizeof(struct dp_soc_be);
  57. case DP_CONTEXT_TYPE_PDEV:
  58. return sizeof(struct dp_pdev_be);
  59. case DP_CONTEXT_TYPE_VDEV:
  60. return sizeof(struct dp_vdev_be);
  61. case DP_CONTEXT_TYPE_PEER:
  62. return sizeof(struct dp_peer_be);
  63. default:
  64. return 0;
  65. }
  66. }
  67. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  68. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  69. /**
  70. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  71. per wbm2sw ring
  72. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  73. *
  74. * Return: None
  75. */
  76. static inline
  77. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  78. {
  79. cc_cfg->wbm2sw6_cc_en = 1;
  80. cc_cfg->wbm2sw5_cc_en = 1;
  81. cc_cfg->wbm2sw4_cc_en = 1;
  82. cc_cfg->wbm2sw3_cc_en = 1;
  83. cc_cfg->wbm2sw2_cc_en = 1;
  84. /* disable wbm2sw1 hw cc as it's for FW */
  85. cc_cfg->wbm2sw1_cc_en = 0;
  86. cc_cfg->wbm2sw0_cc_en = 1;
  87. cc_cfg->wbm2fw_cc_en = 0;
  88. }
  89. #else
  90. static inline
  91. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  92. {
  93. cc_cfg->wbm2sw6_cc_en = 1;
  94. cc_cfg->wbm2sw5_cc_en = 1;
  95. cc_cfg->wbm2sw4_cc_en = 1;
  96. cc_cfg->wbm2sw3_cc_en = 1;
  97. cc_cfg->wbm2sw2_cc_en = 1;
  98. cc_cfg->wbm2sw1_cc_en = 1;
  99. cc_cfg->wbm2sw0_cc_en = 1;
  100. cc_cfg->wbm2fw_cc_en = 0;
  101. }
  102. #endif
  103. /**
  104. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  105. conversion register
  106. * @soc: SOC handle
  107. * @cc_ctx: cookie conversion context pointer
  108. * @is_4k_align: page address 4k alignd
  109. *
  110. * Return: None
  111. */
  112. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  113. struct dp_hw_cookie_conversion_t *cc_ctx,
  114. bool is_4k_align)
  115. {
  116. struct hal_hw_cc_config cc_cfg = { 0 };
  117. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  118. dp_info("INI skip HW CC register setting");
  119. return;
  120. }
  121. cc_cfg.lut_base_addr_31_0 = cc_ctx->cmem_base;
  122. cc_cfg.cc_global_en = true;
  123. cc_cfg.page_4k_align = is_4k_align;
  124. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  125. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  126. /* 36th bit should be 1 then HW know this is CMEM address */
  127. cc_cfg.lut_base_addr_39_32 = 0x10;
  128. cc_cfg.error_path_cookie_conv_en = true;
  129. cc_cfg.release_path_cookie_conv_en = true;
  130. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  131. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  132. }
  133. /**
  134. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  135. * @hal_soc_hdl: HAL SOC handle
  136. * @offset: CMEM address
  137. * @value: value to write
  138. *
  139. * Return: None.
  140. */
  141. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  142. uint32_t offset,
  143. uint32_t value)
  144. {
  145. hal_cmem_write(hal_soc_hdl, offset, value);
  146. }
  147. /**
  148. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  149. HW cookie conversion
  150. * @soc: SOC handle
  151. * @cc_ctx: cookie conversion context pointer
  152. *
  153. * Return: 0 in case of success, else error value
  154. */
  155. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
  156. struct dp_soc *soc,
  157. struct dp_hw_cookie_conversion_t *cc_ctx)
  158. {
  159. dp_info("cmem base 0x%llx, size 0x%llx",
  160. soc->cmem_base, soc->cmem_size);
  161. /* get CMEM for cookie conversion */
  162. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  163. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  164. return QDF_STATUS_E_RESOURCES;
  165. }
  166. cc_ctx->cmem_base = (uint32_t)(soc->cmem_base +
  167. DP_CC_MEM_OFFSET_IN_CMEM);
  168. return QDF_STATUS_SUCCESS;
  169. }
  170. #else
  171. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  172. struct dp_hw_cookie_conversion_t *cc_ctx,
  173. bool is_4k_align) {}
  174. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  175. uint32_t offset,
  176. uint32_t value)
  177. { }
  178. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
  179. struct dp_soc *soc,
  180. struct dp_hw_cookie_conversion_t *cc_ctx)
  181. {
  182. return QDF_STATUS_SUCCESS;
  183. }
  184. #endif
  185. static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
  186. {
  187. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  188. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  189. uint32_t max_tx_rx_desc_num, num_spt_pages, i = 0;
  190. struct dp_spt_page_desc *spt_desc;
  191. struct qdf_mem_dma_page_t *dma_page;
  192. QDF_STATUS qdf_status;
  193. if (soc->cdp_soc.ol_ops->get_con_mode &&
  194. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  195. return QDF_STATUS_SUCCESS;
  196. qdf_status = dp_hw_cc_cmem_addr_init(soc, cc_ctx);
  197. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  198. return qdf_status;
  199. /* estimate how many SPT DDR pages needed */
  200. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  201. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  202. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  203. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  204. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  205. dp_info("num_spt_pages needed %d", num_spt_pages);
  206. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  207. &cc_ctx->page_pool, qdf_page_size,
  208. num_spt_pages, 0, false);
  209. if (!cc_ctx->page_pool.dma_pages) {
  210. dp_err("spt ddr pages allocation failed");
  211. return QDF_STATUS_E_RESOURCES;
  212. }
  213. cc_ctx->page_desc_base = qdf_mem_malloc(
  214. num_spt_pages * sizeof(struct dp_spt_page_desc));
  215. if (!cc_ctx->page_desc_base) {
  216. dp_err("spt page descs allocation failed");
  217. goto fail_0;
  218. }
  219. /* initial page desc */
  220. spt_desc = cc_ctx->page_desc_base;
  221. dma_page = cc_ctx->page_pool.dma_pages;
  222. while (i < num_spt_pages) {
  223. /* check if page address 4K aligned */
  224. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  225. dp_err("non-4k aligned pages addr %pK",
  226. (void *)dma_page[i].page_p_addr);
  227. goto fail_1;
  228. }
  229. spt_desc[i].page_v_addr =
  230. dma_page[i].page_v_addr_start;
  231. spt_desc[i].page_p_addr =
  232. dma_page[i].page_p_addr;
  233. i++;
  234. }
  235. cc_ctx->total_page_num = num_spt_pages;
  236. qdf_spinlock_create(&cc_ctx->cc_lock);
  237. return QDF_STATUS_SUCCESS;
  238. fail_1:
  239. qdf_mem_free(cc_ctx->page_desc_base);
  240. fail_0:
  241. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  242. &cc_ctx->page_pool, 0, false);
  243. return QDF_STATUS_E_FAILURE;
  244. }
  245. static QDF_STATUS dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc)
  246. {
  247. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  248. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  249. if (soc->cdp_soc.ol_ops->get_con_mode &&
  250. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  251. return QDF_STATUS_SUCCESS;
  252. qdf_mem_free(cc_ctx->page_desc_base);
  253. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  254. &cc_ctx->page_pool, 0, false);
  255. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  256. return QDF_STATUS_SUCCESS;
  257. }
  258. static QDF_STATUS dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc)
  259. {
  260. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  261. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  262. uint32_t i = 0;
  263. struct dp_spt_page_desc *spt_desc;
  264. if (soc->cdp_soc.ol_ops->get_con_mode &&
  265. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  266. return QDF_STATUS_SUCCESS;
  267. if (!cc_ctx->total_page_num) {
  268. dp_err("total page num is 0");
  269. return QDF_STATUS_E_INVAL;
  270. }
  271. spt_desc = cc_ctx->page_desc_base;
  272. while (i < cc_ctx->total_page_num) {
  273. /* write page PA to CMEM */
  274. dp_hw_cc_cmem_write(soc->hal_soc,
  275. (cc_ctx->cmem_base +
  276. i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED),
  277. (spt_desc[i].page_p_addr >>
  278. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  279. spt_desc[i].ppt_index = i;
  280. spt_desc[i].avail_entry_index = 0;
  281. /* link page desc */
  282. if ((i + 1) != cc_ctx->total_page_num)
  283. spt_desc[i].next = &spt_desc[i + 1];
  284. else
  285. spt_desc[i].next = NULL;
  286. i++;
  287. }
  288. cc_ctx->page_desc_freelist = cc_ctx->page_desc_base;
  289. cc_ctx->free_page_num = cc_ctx->total_page_num;
  290. /* write WBM/REO cookie conversion CFG register */
  291. dp_cc_reg_cfg_init(soc, cc_ctx, true);
  292. return QDF_STATUS_SUCCESS;
  293. }
  294. static QDF_STATUS dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc)
  295. {
  296. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  297. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  298. if (soc->cdp_soc.ol_ops->get_con_mode &&
  299. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  300. return QDF_STATUS_SUCCESS;
  301. cc_ctx->page_desc_freelist = NULL;
  302. cc_ctx->free_page_num = 0;
  303. return QDF_STATUS_SUCCESS;
  304. }
  305. uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
  306. struct dp_spt_page_desc **list_head,
  307. struct dp_spt_page_desc **list_tail,
  308. uint16_t num_desc)
  309. {
  310. uint16_t num_pages, count;
  311. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  312. num_pages = (num_desc / DP_CC_SPT_PAGE_MAX_ENTRIES) +
  313. (num_desc % DP_CC_SPT_PAGE_MAX_ENTRIES ? 1 : 0);
  314. if (num_pages > cc_ctx->free_page_num) {
  315. dp_err("fail: num_pages required %d > free_page_num %d",
  316. num_pages,
  317. cc_ctx->free_page_num);
  318. return 0;
  319. }
  320. qdf_spin_lock_bh(&cc_ctx->cc_lock);
  321. *list_head = *list_tail = cc_ctx->page_desc_freelist;
  322. for (count = 0; count < num_pages; count++) {
  323. if (qdf_unlikely(!cc_ctx->page_desc_freelist)) {
  324. cc_ctx->page_desc_freelist = *list_head;
  325. *list_head = *list_tail = NULL;
  326. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  327. return 0;
  328. }
  329. *list_tail = cc_ctx->page_desc_freelist;
  330. cc_ctx->page_desc_freelist = cc_ctx->page_desc_freelist->next;
  331. }
  332. (*list_tail)->next = NULL;
  333. cc_ctx->free_page_num -= count;
  334. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  335. return count;
  336. }
  337. void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
  338. struct dp_spt_page_desc **list_head,
  339. struct dp_spt_page_desc **list_tail,
  340. uint16_t page_nums)
  341. {
  342. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  343. struct dp_spt_page_desc *temp_list = NULL;
  344. qdf_spin_lock_bh(&cc_ctx->cc_lock);
  345. temp_list = cc_ctx->page_desc_freelist;
  346. cc_ctx->page_desc_freelist = *list_head;
  347. (*list_tail)->next = temp_list;
  348. cc_ctx->free_page_num += page_nums;
  349. *list_tail = NULL;
  350. *list_head = NULL;
  351. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  352. }
  353. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc)
  354. {
  355. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  356. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  357. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  358. qdf_status = dp_tx_init_bank_profiles(be_soc);
  359. /* cookie conversion */
  360. qdf_status = dp_hw_cookie_conversion_attach(be_soc);
  361. return qdf_status;
  362. }
  363. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  364. {
  365. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  366. dp_tx_deinit_bank_profiles(be_soc);
  367. dp_hw_cookie_conversion_detach(be_soc);
  368. return QDF_STATUS_SUCCESS;
  369. }
  370. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  371. {
  372. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  373. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  374. qdf_status = dp_hw_cookie_conversion_init(be_soc);
  375. /* route vdev_id mismatch notification via FW completion */
  376. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  377. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  378. return qdf_status;
  379. }
  380. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  381. {
  382. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  383. dp_hw_cookie_conversion_deinit(be_soc);
  384. return QDF_STATUS_SUCCESS;
  385. }
  386. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev)
  387. {
  388. return QDF_STATUS_SUCCESS;
  389. }
  390. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  391. {
  392. return QDF_STATUS_SUCCESS;
  393. }
  394. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  395. {
  396. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  397. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  398. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  399. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  400. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  401. QDF_BUG(0);
  402. return QDF_STATUS_E_FAULT;
  403. }
  404. if (vdev->opmode == wlan_op_mode_sta) {
  405. if (soc->cdp_soc.ol_ops->set_mec_timer)
  406. soc->cdp_soc.ol_ops->set_mec_timer(
  407. soc->ctrl_psoc,
  408. vdev->vdev_id,
  409. DP_AST_AGING_TIMER_DEFAULT_MS);
  410. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  411. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  412. }
  413. return QDF_STATUS_SUCCESS;
  414. }
  415. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  416. {
  417. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  418. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  419. dp_tx_put_bank_profile(be_soc, be_vdev);
  420. return QDF_STATUS_SUCCESS;
  421. }
  422. qdf_size_t dp_get_soc_context_size_be(void)
  423. {
  424. return sizeof(struct dp_soc_be);
  425. }
  426. /**
  427. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  428. * @soc: Common DP soc handle
  429. *
  430. * Return: QDF_STATUS
  431. */
  432. static QDF_STATUS
  433. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  434. {
  435. int i;
  436. int mac_id;
  437. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  438. struct dp_srng *rx_mac_srng;
  439. QDF_STATUS status = QDF_STATUS_SUCCESS;
  440. /*
  441. * In Beryllium chipset msdu_start, mpdu_end
  442. * and rx_attn are part of msdu_end/mpdu_start
  443. */
  444. htt_tlv_filter.msdu_start = 0;
  445. htt_tlv_filter.mpdu_end = 0;
  446. htt_tlv_filter.attention = 0;
  447. htt_tlv_filter.mpdu_start = 1;
  448. htt_tlv_filter.msdu_end = 1;
  449. htt_tlv_filter.packet = 1;
  450. htt_tlv_filter.packet_header = 1;
  451. htt_tlv_filter.ppdu_start = 0;
  452. htt_tlv_filter.ppdu_end = 0;
  453. htt_tlv_filter.ppdu_end_user_stats = 0;
  454. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  455. htt_tlv_filter.ppdu_end_status_done = 0;
  456. htt_tlv_filter.enable_fp = 1;
  457. htt_tlv_filter.enable_md = 0;
  458. htt_tlv_filter.enable_md = 0;
  459. htt_tlv_filter.enable_mo = 0;
  460. htt_tlv_filter.fp_mgmt_filter = 0;
  461. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  462. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  463. FILTER_DATA_MCAST |
  464. FILTER_DATA_DATA);
  465. htt_tlv_filter.mo_mgmt_filter = 0;
  466. htt_tlv_filter.mo_ctrl_filter = 0;
  467. htt_tlv_filter.mo_data_filter = 0;
  468. htt_tlv_filter.md_data_filter = 0;
  469. htt_tlv_filter.offset_valid = true;
  470. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  471. htt_tlv_filter.rx_mpdu_end_offset = 0;
  472. htt_tlv_filter.rx_msdu_start_offset = 0;
  473. htt_tlv_filter.rx_attn_offset = 0;
  474. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  475. htt_tlv_filter.rx_header_offset =
  476. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  477. htt_tlv_filter.rx_mpdu_start_offset =
  478. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  479. htt_tlv_filter.rx_msdu_end_offset =
  480. hal_rx_msdu_end_offset_get(soc->hal_soc);
  481. dp_info("TLV subscription\n"
  482. "msdu_start %d, mpdu_end %d, attention %d"
  483. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  484. "TLV offsets\n"
  485. "msdu_start %d, mpdu_end %d, attention %d"
  486. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  487. htt_tlv_filter.msdu_start,
  488. htt_tlv_filter.mpdu_end,
  489. htt_tlv_filter.attention,
  490. htt_tlv_filter.mpdu_start,
  491. htt_tlv_filter.msdu_end,
  492. htt_tlv_filter.packet_header,
  493. htt_tlv_filter.packet,
  494. htt_tlv_filter.rx_msdu_start_offset,
  495. htt_tlv_filter.rx_mpdu_end_offset,
  496. htt_tlv_filter.rx_attn_offset,
  497. htt_tlv_filter.rx_mpdu_start_offset,
  498. htt_tlv_filter.rx_msdu_end_offset,
  499. htt_tlv_filter.rx_header_offset,
  500. htt_tlv_filter.rx_packet_offset);
  501. for (i = 0; i < MAX_PDEV_CNT; i++) {
  502. struct dp_pdev *pdev = soc->pdev_list[i];
  503. if (!pdev)
  504. continue;
  505. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  506. int mac_for_pdev =
  507. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  508. /*
  509. * Obtain lmac id from pdev to access the LMAC ring
  510. * in soc context
  511. */
  512. int lmac_id =
  513. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  514. pdev->pdev_id);
  515. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  516. if (!rx_mac_srng->hal_srng)
  517. continue;
  518. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  519. rx_mac_srng->hal_srng,
  520. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  521. &htt_tlv_filter);
  522. }
  523. }
  524. return status;
  525. }
  526. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  527. /**
  528. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  529. * near-full IRQs.
  530. * @soc: Datapath SoC handle
  531. * @int_ctx: Interrupt context
  532. * @dp_budget: Budget of the work that can be done in the bottom half
  533. *
  534. * Return: work done in the handler
  535. */
  536. static uint32_t
  537. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  538. uint32_t dp_budget)
  539. {
  540. int ring = 0;
  541. int budget = dp_budget;
  542. uint32_t work_done = 0;
  543. uint32_t remaining_quota = dp_budget;
  544. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  545. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  546. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  547. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  548. int rx_near_full_mask = rx_near_full_grp_1_mask |
  549. rx_near_full_grp_2_mask;
  550. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  551. rx_near_full_mask,
  552. tx_ring_near_full_mask);
  553. if (rx_near_full_mask) {
  554. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  555. if (!(rx_near_full_mask & (1 << ring)))
  556. continue;
  557. work_done = dp_rx_nf_process(int_ctx,
  558. soc->reo_dest_ring[ring].hal_srng,
  559. ring, remaining_quota);
  560. if (work_done) {
  561. intr_stats->num_rx_ring_near_full_masks[ring]++;
  562. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  563. rx_near_full_mask, ring,
  564. work_done,
  565. budget);
  566. budget -= work_done;
  567. if (budget <= 0)
  568. goto budget_done;
  569. remaining_quota = budget;
  570. }
  571. }
  572. }
  573. if (tx_ring_near_full_mask) {
  574. for (ring = 0; ring < MAX_TCL_DATA_RINGS; ring++) {
  575. if (!(tx_ring_near_full_mask & (1 << ring)))
  576. continue;
  577. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  578. soc->tx_comp_ring[ring].hal_srng,
  579. ring, remaining_quota);
  580. if (work_done) {
  581. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  582. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  583. tx_ring_near_full_mask, ring,
  584. work_done, budget);
  585. budget -= work_done;
  586. if (budget <= 0)
  587. break;
  588. remaining_quota = budget;
  589. }
  590. }
  591. }
  592. intr_stats->num_near_full_masks++;
  593. budget_done:
  594. return dp_budget - budget;
  595. }
  596. /**
  597. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  598. * state and set the reap_limit appropriately
  599. * as per the near full state
  600. * @soc: Datapath soc handle
  601. * @dp_srng: Datapath handle for SRNG
  602. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  603. * the srng near-full state
  604. *
  605. * Return: 1, if the srng is in near-full state
  606. * 0, if the srng is not in near-full state
  607. */
  608. static int
  609. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  610. struct dp_srng *dp_srng,
  611. int *max_reap_limit)
  612. {
  613. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  614. }
  615. /**
  616. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  617. * near full IRQ handling operations.
  618. * @arch_ops: arch ops handle
  619. *
  620. * Return: none
  621. */
  622. static inline void
  623. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  624. {
  625. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  626. arch_ops->dp_srng_test_and_update_nf_params =
  627. dp_srng_test_and_update_nf_params_be;
  628. }
  629. #else
  630. static inline void
  631. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  632. {
  633. }
  634. #endif
  635. #ifdef WLAN_SUPPORT_PPEDS
  636. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  637. {
  638. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  639. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  640. soc_cfg_ctx = soc->wlan_cfg_ctx;
  641. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  642. return;
  643. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  644. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  645. be_soc->ppe_release_ring.alloc_size,
  646. soc->ctrl_psoc,
  647. WLAN_MD_DP_SRNG_PPE_RELEASE,
  648. "ppe_release_ring");
  649. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  650. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  651. be_soc->ppe2tcl_ring.alloc_size,
  652. soc->ctrl_psoc,
  653. WLAN_MD_DP_SRNG_PPE2TCL,
  654. "ppe2tcl_ring");
  655. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  656. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  657. be_soc->reo2ppe_ring.alloc_size,
  658. soc->ctrl_psoc,
  659. WLAN_MD_DP_SRNG_REO2PPE,
  660. "reo2ppe_ring");
  661. }
  662. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  663. {
  664. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  665. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  666. soc_cfg_ctx = soc->wlan_cfg_ctx;
  667. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  668. return;
  669. dp_srng_free(soc, &be_soc->ppe_release_ring);
  670. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  671. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  672. }
  673. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  674. {
  675. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  676. uint32_t entries;
  677. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  678. soc_cfg_ctx = soc->wlan_cfg_ctx;
  679. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  680. return QDF_STATUS_SUCCESS;
  681. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  682. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  683. entries, 0)) {
  684. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  685. goto fail;
  686. }
  687. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  688. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  689. entries, 0)) {
  690. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  691. goto fail;
  692. }
  693. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  694. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  695. entries, 0)) {
  696. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  697. goto fail;
  698. }
  699. return QDF_STATUS_SUCCESS;
  700. fail:
  701. dp_soc_ppe_srng_free(soc);
  702. return QDF_STATUS_E_NOMEM;
  703. }
  704. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  705. {
  706. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  707. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  708. soc_cfg_ctx = soc->wlan_cfg_ctx;
  709. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  710. return QDF_STATUS_SUCCESS;
  711. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  712. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  713. goto fail;
  714. }
  715. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  716. be_soc->reo2ppe_ring.alloc_size,
  717. soc->ctrl_psoc,
  718. WLAN_MD_DP_SRNG_REO2PPE,
  719. "reo2ppe_ring");
  720. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  721. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  722. goto fail;
  723. }
  724. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  725. be_soc->ppe2tcl_ring.alloc_size,
  726. soc->ctrl_psoc,
  727. WLAN_MD_DP_SRNG_PPE2TCL,
  728. "ppe2tcl_ring");
  729. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  730. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  731. goto fail;
  732. }
  733. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  734. be_soc->ppe_release_ring.alloc_size,
  735. soc->ctrl_psoc,
  736. WLAN_MD_DP_SRNG_PPE_RELEASE,
  737. "ppe_release_ring");
  738. return QDF_STATUS_SUCCESS;
  739. fail:
  740. dp_soc_ppe_srng_deinit(soc);
  741. return QDF_STATUS_E_NOMEM;
  742. }
  743. #else
  744. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  745. {
  746. }
  747. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  748. {
  749. }
  750. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  751. {
  752. return QDF_STATUS_SUCCESS;
  753. }
  754. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  755. {
  756. return QDF_STATUS_SUCCESS;
  757. }
  758. #endif
  759. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  760. {
  761. uint32_t i;
  762. dp_soc_ppe_srng_deinit(soc);
  763. if (hal_dmac_cmn_src_rxbuf_ring_get(soc->hal_soc)) {
  764. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  765. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  766. RXDMA_BUF, 0);
  767. }
  768. }
  769. }
  770. static void dp_soc_srng_free_be(struct dp_soc *soc)
  771. {
  772. uint32_t i;
  773. dp_soc_ppe_srng_free(soc);
  774. if (hal_dmac_cmn_src_rxbuf_ring_get(soc->hal_soc)) {
  775. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  776. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  777. }
  778. }
  779. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  780. {
  781. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  782. uint32_t ring_size;
  783. uint32_t i;
  784. soc_cfg_ctx = soc->wlan_cfg_ctx;
  785. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  786. if (hal_dmac_cmn_src_rxbuf_ring_get(soc->hal_soc)) {
  787. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  788. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  789. RXDMA_BUF, ring_size, 0)) {
  790. dp_err("%pK: dp_srng_alloc failed refill ring",
  791. soc);
  792. goto fail;
  793. }
  794. }
  795. }
  796. if (dp_soc_ppe_srng_alloc(soc)) {
  797. dp_err("%pK: ppe rings alloc failed",
  798. soc);
  799. goto fail;
  800. }
  801. return QDF_STATUS_SUCCESS;
  802. fail:
  803. dp_soc_srng_free_be(soc);
  804. return QDF_STATUS_E_NOMEM;
  805. }
  806. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  807. {
  808. int i = 0;
  809. if (hal_dmac_cmn_src_rxbuf_ring_get(soc->hal_soc)) {
  810. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  811. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  812. RXDMA_BUF, 0, 0)) {
  813. dp_err("%pK: dp_srng_init failed refill ring",
  814. soc);
  815. goto fail;
  816. }
  817. }
  818. }
  819. if (dp_soc_ppe_srng_init(soc)) {
  820. dp_err("%pK: ppe rings init failed",
  821. soc);
  822. goto fail;
  823. }
  824. return QDF_STATUS_SUCCESS;
  825. fail:
  826. dp_soc_srng_deinit_be(soc);
  827. return QDF_STATUS_E_NOMEM;
  828. }
  829. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  830. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  831. uint8_t tx_ring_id,
  832. uint8_t bm_id)
  833. {
  834. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  835. soc->tcl_data_ring[tx_ring_id].hal_srng,
  836. bm_id);
  837. }
  838. #else
  839. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  840. uint8_t tx_ring_id,
  841. uint8_t bm_id)
  842. {
  843. }
  844. #endif
  845. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  846. {
  847. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  848. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  849. arch_ops->dp_rx_process = dp_rx_process_be;
  850. arch_ops->tx_comp_get_params_from_hal_desc =
  851. dp_tx_comp_get_params_from_hal_desc_be;
  852. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  853. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  854. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  855. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  856. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  857. dp_wbm_get_rx_desc_from_hal_desc_be;
  858. #endif
  859. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  860. arch_ops->dp_rx_desc_cookie_2_va =
  861. dp_rx_desc_cookie_2_va_be;
  862. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  863. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  864. arch_ops->txrx_soc_init = dp_soc_init_be;
  865. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  866. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  867. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  868. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  869. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  870. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  871. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  872. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  873. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  874. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  875. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  876. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  877. dp_init_near_full_arch_ops_be(arch_ops);
  878. }