cam_mem_mgr.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #include "cam_compat.h"
  13. #include "cam_req_mgr_util.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_smmu_api.h"
  16. #include "cam_debug_util.h"
  17. #include "cam_trace.h"
  18. #include "cam_common_util.h"
  19. static struct cam_mem_table tbl;
  20. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  21. static void cam_mem_mgr_print_tbl(void)
  22. {
  23. int i;
  24. uint64_t ms, tmp, hrs, min, sec;
  25. struct timespec64 *ts = NULL;
  26. struct timespec64 current_ts;
  27. ktime_get_real_ts64(&(current_ts));
  28. tmp = current_ts.tv_sec;
  29. ms = (current_ts.tv_nsec) / 1000000;
  30. sec = do_div(tmp, 60);
  31. min = do_div(tmp, 60);
  32. hrs = do_div(tmp, 24);
  33. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  34. hrs, min, sec, ms);
  35. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  36. if (tbl.bufq[i].active) {
  37. ts = &tbl.bufq[i].timestamp;
  38. tmp = ts->tv_sec;
  39. ms = (ts->tv_nsec) / 1000000;
  40. sec = do_div(tmp, 60);
  41. min = do_div(tmp, 60);
  42. hrs = do_div(tmp, 24);
  43. CAM_INFO(CAM_MEM,
  44. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  45. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  46. tbl.bufq[i].len);
  47. }
  48. }
  49. }
  50. static int cam_mem_util_get_dma_dir(uint32_t flags)
  51. {
  52. int rc = -EINVAL;
  53. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  54. rc = DMA_TO_DEVICE;
  55. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  56. rc = DMA_FROM_DEVICE;
  57. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  58. rc = DMA_BIDIRECTIONAL;
  59. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  60. rc = DMA_BIDIRECTIONAL;
  61. return rc;
  62. }
  63. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  64. uintptr_t *vaddr,
  65. size_t *len)
  66. {
  67. int rc = 0;
  68. void *addr;
  69. /*
  70. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  71. * need to be called in pair to avoid stability issue.
  72. */
  73. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  74. if (rc) {
  75. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  76. return rc;
  77. }
  78. addr = dma_buf_vmap(dmabuf);
  79. if (!addr) {
  80. CAM_ERR(CAM_MEM, "kernel map fail");
  81. *vaddr = 0;
  82. *len = 0;
  83. rc = -ENOSPC;
  84. goto fail;
  85. }
  86. *vaddr = (uint64_t)addr;
  87. *len = dmabuf->size;
  88. return 0;
  89. fail:
  90. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  91. return rc;
  92. }
  93. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  94. uint64_t vaddr)
  95. {
  96. int rc = 0;
  97. if (!dmabuf || !vaddr) {
  98. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  99. return -EINVAL;
  100. }
  101. dma_buf_vunmap(dmabuf, (void *)vaddr);
  102. /*
  103. * dma_buf_begin_cpu_access() and
  104. * dma_buf_end_cpu_access() need to be called in pair
  105. * to avoid stability issue.
  106. */
  107. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  108. if (rc) {
  109. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  110. dmabuf);
  111. return rc;
  112. }
  113. return rc;
  114. }
  115. static int cam_mem_mgr_create_debug_fs(void)
  116. {
  117. int rc = 0;
  118. struct dentry *dbgfileptr = NULL;
  119. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  120. if (!dbgfileptr) {
  121. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  122. rc = -ENOENT;
  123. goto end;
  124. }
  125. /* Store parent inode for cleanup in caller */
  126. tbl.dentry = dbgfileptr;
  127. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  128. tbl.dentry, &tbl.alloc_profile_enable);
  129. if (IS_ERR(dbgfileptr)) {
  130. if (PTR_ERR(dbgfileptr) == -ENODEV)
  131. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  132. else
  133. rc = PTR_ERR(dbgfileptr);
  134. }
  135. end:
  136. return rc;
  137. }
  138. int cam_mem_mgr_init(void)
  139. {
  140. int i;
  141. int bitmap_size;
  142. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  143. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  144. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  145. return -EINVAL;
  146. }
  147. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  148. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  149. if (!tbl.bitmap)
  150. return -ENOMEM;
  151. tbl.bits = bitmap_size * BITS_PER_BYTE;
  152. bitmap_zero(tbl.bitmap, tbl.bits);
  153. /* We need to reserve slot 0 because 0 is invalid */
  154. set_bit(0, tbl.bitmap);
  155. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  156. tbl.bufq[i].fd = -1;
  157. tbl.bufq[i].buf_handle = -1;
  158. }
  159. mutex_init(&tbl.m_lock);
  160. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  161. cam_mem_mgr_create_debug_fs();
  162. return 0;
  163. }
  164. static int32_t cam_mem_get_slot(void)
  165. {
  166. int32_t idx;
  167. mutex_lock(&tbl.m_lock);
  168. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  169. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  170. mutex_unlock(&tbl.m_lock);
  171. return -ENOMEM;
  172. }
  173. set_bit(idx, tbl.bitmap);
  174. tbl.bufq[idx].active = true;
  175. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  176. mutex_init(&tbl.bufq[idx].q_lock);
  177. mutex_unlock(&tbl.m_lock);
  178. return idx;
  179. }
  180. static void cam_mem_put_slot(int32_t idx)
  181. {
  182. mutex_lock(&tbl.m_lock);
  183. mutex_lock(&tbl.bufq[idx].q_lock);
  184. tbl.bufq[idx].active = false;
  185. tbl.bufq[idx].is_internal = false;
  186. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  187. mutex_unlock(&tbl.bufq[idx].q_lock);
  188. mutex_destroy(&tbl.bufq[idx].q_lock);
  189. clear_bit(idx, tbl.bitmap);
  190. mutex_unlock(&tbl.m_lock);
  191. }
  192. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  193. dma_addr_t *iova_ptr, size_t *len_ptr)
  194. {
  195. int rc = 0, idx;
  196. *len_ptr = 0;
  197. if (!atomic_read(&cam_mem_mgr_state)) {
  198. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  199. return -EINVAL;
  200. }
  201. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  202. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  203. return -ENOENT;
  204. if (!tbl.bufq[idx].active) {
  205. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  206. idx);
  207. return -EAGAIN;
  208. }
  209. mutex_lock(&tbl.bufq[idx].q_lock);
  210. if (buf_handle != tbl.bufq[idx].buf_handle) {
  211. rc = -EINVAL;
  212. goto handle_mismatch;
  213. }
  214. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  215. rc = cam_smmu_get_stage2_iova(mmu_handle,
  216. tbl.bufq[idx].fd,
  217. iova_ptr,
  218. len_ptr);
  219. else
  220. rc = cam_smmu_get_iova(mmu_handle,
  221. tbl.bufq[idx].fd,
  222. iova_ptr,
  223. len_ptr);
  224. if (rc) {
  225. CAM_ERR(CAM_MEM,
  226. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  227. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  228. goto handle_mismatch;
  229. }
  230. CAM_DBG(CAM_MEM,
  231. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  232. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  233. handle_mismatch:
  234. mutex_unlock(&tbl.bufq[idx].q_lock);
  235. return rc;
  236. }
  237. EXPORT_SYMBOL(cam_mem_get_io_buf);
  238. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  239. {
  240. int idx;
  241. if (!atomic_read(&cam_mem_mgr_state)) {
  242. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  243. return -EINVAL;
  244. }
  245. if (!atomic_read(&cam_mem_mgr_state)) {
  246. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  247. return -EINVAL;
  248. }
  249. if (!buf_handle || !vaddr_ptr || !len)
  250. return -EINVAL;
  251. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  252. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  253. return -EINVAL;
  254. if (!tbl.bufq[idx].active) {
  255. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  256. idx);
  257. return -EPERM;
  258. }
  259. if (buf_handle != tbl.bufq[idx].buf_handle)
  260. return -EINVAL;
  261. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  262. return -EINVAL;
  263. if (tbl.bufq[idx].kmdvaddr) {
  264. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  265. *len = tbl.bufq[idx].len;
  266. } else {
  267. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  268. buf_handle);
  269. return -EINVAL;
  270. }
  271. return 0;
  272. }
  273. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  274. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  275. {
  276. int rc = 0, idx;
  277. uint32_t cache_dir;
  278. unsigned long dmabuf_flag = 0;
  279. if (!atomic_read(&cam_mem_mgr_state)) {
  280. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  281. return -EINVAL;
  282. }
  283. if (!cmd)
  284. return -EINVAL;
  285. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  286. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  287. return -EINVAL;
  288. mutex_lock(&tbl.bufq[idx].q_lock);
  289. if (!tbl.bufq[idx].active) {
  290. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  291. idx);
  292. rc = -EINVAL;
  293. goto end;
  294. }
  295. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  296. rc = -EINVAL;
  297. goto end;
  298. }
  299. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  300. if (rc) {
  301. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  302. goto end;
  303. }
  304. if (dmabuf_flag & ION_FLAG_CACHED) {
  305. switch (cmd->mem_cache_ops) {
  306. case CAM_MEM_CLEAN_CACHE:
  307. cache_dir = DMA_TO_DEVICE;
  308. break;
  309. case CAM_MEM_INV_CACHE:
  310. cache_dir = DMA_FROM_DEVICE;
  311. break;
  312. case CAM_MEM_CLEAN_INV_CACHE:
  313. cache_dir = DMA_BIDIRECTIONAL;
  314. break;
  315. default:
  316. CAM_ERR(CAM_MEM,
  317. "invalid cache ops :%d", cmd->mem_cache_ops);
  318. rc = -EINVAL;
  319. goto end;
  320. }
  321. } else {
  322. CAM_DBG(CAM_MEM, "BUF is not cached");
  323. goto end;
  324. }
  325. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  326. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  327. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  328. if (rc) {
  329. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  330. goto end;
  331. }
  332. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  333. cache_dir);
  334. if (rc) {
  335. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  336. goto end;
  337. }
  338. end:
  339. mutex_unlock(&tbl.bufq[idx].q_lock);
  340. return rc;
  341. }
  342. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  343. static int cam_mem_util_get_dma_buf(size_t len,
  344. unsigned int cam_flags,
  345. struct dma_buf **buf)
  346. {
  347. int rc = 0;
  348. unsigned int heap_id;
  349. int32_t ion_flag = 0;
  350. struct timespec64 ts1, ts2;
  351. long microsec = 0;
  352. if (!buf) {
  353. CAM_ERR(CAM_MEM, "Invalid params");
  354. return -EINVAL;
  355. }
  356. if (tbl.alloc_profile_enable)
  357. CAM_GET_TIMESTAMP(ts1);
  358. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  359. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  360. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  361. ion_flag |=
  362. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  363. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  364. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  365. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  366. } else {
  367. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  368. ION_HEAP(ION_CAMERA_HEAP_ID);
  369. }
  370. if (cam_flags & CAM_MEM_FLAG_CACHE)
  371. ion_flag |= ION_FLAG_CACHED;
  372. else
  373. ion_flag &= ~ION_FLAG_CACHED;
  374. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  375. ion_flag |= ION_FLAG_CACHED;
  376. *buf = ion_alloc(len, heap_id, ion_flag);
  377. if (IS_ERR_OR_NULL(*buf))
  378. return -ENOMEM;
  379. if (tbl.alloc_profile_enable) {
  380. CAM_GET_TIMESTAMP(ts2);
  381. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  382. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  383. len, microsec);
  384. }
  385. return rc;
  386. }
  387. static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  388. struct dma_buf **dmabuf,
  389. int *fd)
  390. {
  391. int rc;
  392. struct dma_buf *temp_dmabuf = NULL;
  393. rc = cam_mem_util_get_dma_buf(cmd->len,
  394. cmd->flags,
  395. dmabuf);
  396. if (rc) {
  397. CAM_ERR(CAM_MEM,
  398. "Error allocating dma buf : len=%llu, flags=0x%x",
  399. cmd->len, cmd->flags);
  400. return rc;
  401. }
  402. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  403. if (*fd < 0) {
  404. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  405. rc = -EINVAL;
  406. goto put_buf;
  407. }
  408. /*
  409. * increment the ref count so that ref count becomes 2 here
  410. * when we close fd, refcount becomes 1 and when we do
  411. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  412. */
  413. temp_dmabuf = dma_buf_get(*fd);
  414. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  415. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  416. rc = -EINVAL;
  417. goto put_buf;
  418. }
  419. return rc;
  420. put_buf:
  421. dma_buf_put(*dmabuf);
  422. return rc;
  423. }
  424. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  425. {
  426. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  427. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  428. CAM_MEM_MMU_MAX_HANDLE);
  429. return -EINVAL;
  430. }
  431. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  432. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  433. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  434. return -EINVAL;
  435. }
  436. return 0;
  437. }
  438. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  439. {
  440. if (!cmd->flags) {
  441. CAM_ERR(CAM_MEM, "Invalid flags");
  442. return -EINVAL;
  443. }
  444. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  445. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  446. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  447. return -EINVAL;
  448. }
  449. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  450. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  451. CAM_ERR(CAM_MEM,
  452. "Kernel mapping in secure mode not allowed, flags=0x%x",
  453. cmd->flags);
  454. return -EINVAL;
  455. }
  456. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  457. CAM_ERR(CAM_MEM,
  458. "Shared memory buffers are not allowed to be mapped");
  459. return -EINVAL;
  460. }
  461. return 0;
  462. }
  463. static int cam_mem_util_map_hw_va(uint32_t flags,
  464. int32_t *mmu_hdls,
  465. int32_t num_hdls,
  466. int fd,
  467. dma_addr_t *hw_vaddr,
  468. size_t *len,
  469. enum cam_smmu_region_id region,
  470. bool is_internal)
  471. {
  472. int i;
  473. int rc = -1;
  474. int dir = cam_mem_util_get_dma_dir(flags);
  475. bool dis_delayed_unmap = false;
  476. if (dir < 0) {
  477. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  478. return dir;
  479. }
  480. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  481. dis_delayed_unmap = true;
  482. CAM_DBG(CAM_MEM,
  483. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  484. fd, flags, dir, num_hdls);
  485. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  486. for (i = 0; i < num_hdls; i++) {
  487. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  488. fd,
  489. dir,
  490. hw_vaddr,
  491. len);
  492. if (rc < 0) {
  493. CAM_ERR(CAM_MEM,
  494. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  495. i, fd, dir, mmu_hdls[i], rc);
  496. goto multi_map_fail;
  497. }
  498. }
  499. } else {
  500. for (i = 0; i < num_hdls; i++) {
  501. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  502. fd,
  503. dis_delayed_unmap,
  504. dir,
  505. (dma_addr_t *)hw_vaddr,
  506. len,
  507. region,
  508. is_internal);
  509. if (rc < 0) {
  510. CAM_ERR(CAM_MEM,
  511. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  512. i, fd, dir, mmu_hdls[i], region, rc);
  513. goto multi_map_fail;
  514. }
  515. }
  516. }
  517. return rc;
  518. multi_map_fail:
  519. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  520. for (--i; i >= 0; i--)
  521. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  522. else
  523. for (--i; i >= 0; i--)
  524. cam_smmu_unmap_user_iova(mmu_hdls[i],
  525. fd,
  526. CAM_SMMU_REGION_IO);
  527. return rc;
  528. }
  529. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  530. {
  531. int rc;
  532. int32_t idx;
  533. struct dma_buf *dmabuf = NULL;
  534. int fd = -1;
  535. dma_addr_t hw_vaddr = 0;
  536. size_t len;
  537. uintptr_t kvaddr = 0;
  538. size_t klen;
  539. if (!atomic_read(&cam_mem_mgr_state)) {
  540. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  541. return -EINVAL;
  542. }
  543. if (!cmd) {
  544. CAM_ERR(CAM_MEM, " Invalid argument");
  545. return -EINVAL;
  546. }
  547. len = cmd->len;
  548. rc = cam_mem_util_check_alloc_flags(cmd);
  549. if (rc) {
  550. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  551. cmd->flags, rc);
  552. return rc;
  553. }
  554. rc = cam_mem_util_ion_alloc(cmd,
  555. &dmabuf,
  556. &fd);
  557. if (rc) {
  558. CAM_ERR(CAM_MEM,
  559. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  560. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  561. cam_mem_mgr_print_tbl();
  562. return rc;
  563. }
  564. idx = cam_mem_get_slot();
  565. if (idx < 0) {
  566. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  567. rc = -ENOMEM;
  568. goto slot_fail;
  569. }
  570. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  571. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  572. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  573. enum cam_smmu_region_id region;
  574. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  575. region = CAM_SMMU_REGION_IO;
  576. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  577. region = CAM_SMMU_REGION_SHARED;
  578. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  579. region = CAM_SMMU_REGION_SECHEAP;
  580. rc = cam_mem_util_map_hw_va(cmd->flags,
  581. cmd->mmu_hdls,
  582. cmd->num_hdl,
  583. fd,
  584. &hw_vaddr,
  585. &len,
  586. region,
  587. true);
  588. if (rc) {
  589. CAM_ERR(CAM_MEM,
  590. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  591. len, cmd->flags,
  592. fd, region, cmd->num_hdl, rc);
  593. if (rc == -EALREADY) {
  594. if ((size_t)dmabuf->size != len)
  595. rc = -EBADR;
  596. cam_mem_mgr_print_tbl();
  597. }
  598. goto map_hw_fail;
  599. }
  600. }
  601. mutex_lock(&tbl.bufq[idx].q_lock);
  602. tbl.bufq[idx].fd = fd;
  603. tbl.bufq[idx].dma_buf = NULL;
  604. tbl.bufq[idx].flags = cmd->flags;
  605. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  606. tbl.bufq[idx].is_internal = true;
  607. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  608. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  609. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  610. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  611. if (rc) {
  612. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  613. dmabuf, rc);
  614. goto map_kernel_fail;
  615. }
  616. }
  617. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  618. tbl.dbg_buf_idx = idx;
  619. tbl.bufq[idx].kmdvaddr = kvaddr;
  620. tbl.bufq[idx].vaddr = hw_vaddr;
  621. tbl.bufq[idx].dma_buf = dmabuf;
  622. tbl.bufq[idx].len = cmd->len;
  623. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  624. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  625. sizeof(int32_t) * cmd->num_hdl);
  626. tbl.bufq[idx].is_imported = false;
  627. mutex_unlock(&tbl.bufq[idx].q_lock);
  628. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  629. cmd->out.fd = tbl.bufq[idx].fd;
  630. cmd->out.vaddr = 0;
  631. CAM_DBG(CAM_MEM,
  632. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  633. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  634. tbl.bufq[idx].len);
  635. return rc;
  636. map_kernel_fail:
  637. mutex_unlock(&tbl.bufq[idx].q_lock);
  638. map_hw_fail:
  639. cam_mem_put_slot(idx);
  640. slot_fail:
  641. dma_buf_put(dmabuf);
  642. return rc;
  643. }
  644. static bool cam_mem_util_is_map_internal(int32_t fd)
  645. {
  646. uint32_t i;
  647. bool is_internal = false;
  648. mutex_lock(&tbl.m_lock);
  649. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  650. if (tbl.bufq[i].fd == fd) {
  651. is_internal = tbl.bufq[i].is_internal;
  652. break;
  653. }
  654. }
  655. mutex_unlock(&tbl.m_lock);
  656. return is_internal;
  657. }
  658. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  659. {
  660. int32_t idx;
  661. int rc;
  662. struct dma_buf *dmabuf;
  663. dma_addr_t hw_vaddr = 0;
  664. size_t len = 0;
  665. bool is_internal = false;
  666. if (!atomic_read(&cam_mem_mgr_state)) {
  667. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  668. return -EINVAL;
  669. }
  670. if (!cmd || (cmd->fd < 0)) {
  671. CAM_ERR(CAM_MEM, "Invalid argument");
  672. return -EINVAL;
  673. }
  674. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  675. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  676. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  677. return -EINVAL;
  678. }
  679. rc = cam_mem_util_check_map_flags(cmd);
  680. if (rc) {
  681. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  682. return rc;
  683. }
  684. dmabuf = dma_buf_get(cmd->fd);
  685. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  686. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  687. return -EINVAL;
  688. }
  689. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  690. idx = cam_mem_get_slot();
  691. if (idx < 0) {
  692. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  693. idx, cmd->fd);
  694. rc = -ENOMEM;
  695. goto slot_fail;
  696. }
  697. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  698. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  699. rc = cam_mem_util_map_hw_va(cmd->flags,
  700. cmd->mmu_hdls,
  701. cmd->num_hdl,
  702. cmd->fd,
  703. &hw_vaddr,
  704. &len,
  705. CAM_SMMU_REGION_IO,
  706. is_internal);
  707. if (rc) {
  708. CAM_ERR(CAM_MEM,
  709. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  710. cmd->flags, cmd->fd, len,
  711. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  712. if (rc == -EALREADY) {
  713. if ((size_t)dmabuf->size != len) {
  714. rc = -EBADR;
  715. cam_mem_mgr_print_tbl();
  716. }
  717. }
  718. goto map_fail;
  719. }
  720. }
  721. mutex_lock(&tbl.bufq[idx].q_lock);
  722. tbl.bufq[idx].fd = cmd->fd;
  723. tbl.bufq[idx].dma_buf = NULL;
  724. tbl.bufq[idx].flags = cmd->flags;
  725. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  726. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  727. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  728. tbl.bufq[idx].kmdvaddr = 0;
  729. if (cmd->num_hdl > 0)
  730. tbl.bufq[idx].vaddr = hw_vaddr;
  731. else
  732. tbl.bufq[idx].vaddr = 0;
  733. tbl.bufq[idx].dma_buf = dmabuf;
  734. tbl.bufq[idx].len = len;
  735. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  736. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  737. sizeof(int32_t) * cmd->num_hdl);
  738. tbl.bufq[idx].is_imported = true;
  739. tbl.bufq[idx].is_internal = is_internal;
  740. mutex_unlock(&tbl.bufq[idx].q_lock);
  741. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  742. cmd->out.vaddr = 0;
  743. cmd->out.size = (uint32_t)len;
  744. CAM_DBG(CAM_MEM,
  745. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  746. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  747. tbl.bufq[idx].len);
  748. return rc;
  749. map_fail:
  750. cam_mem_put_slot(idx);
  751. slot_fail:
  752. dma_buf_put(dmabuf);
  753. return rc;
  754. }
  755. static int cam_mem_util_unmap_hw_va(int32_t idx,
  756. enum cam_smmu_region_id region,
  757. enum cam_smmu_mapping_client client)
  758. {
  759. int i;
  760. uint32_t flags;
  761. int32_t *mmu_hdls;
  762. int num_hdls;
  763. int fd;
  764. int rc = 0;
  765. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  766. CAM_ERR(CAM_MEM, "Incorrect index");
  767. return -EINVAL;
  768. }
  769. flags = tbl.bufq[idx].flags;
  770. mmu_hdls = tbl.bufq[idx].hdls;
  771. num_hdls = tbl.bufq[idx].num_hdl;
  772. fd = tbl.bufq[idx].fd;
  773. CAM_DBG(CAM_MEM,
  774. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  775. idx, fd, flags, num_hdls, client);
  776. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  777. for (i = 0; i < num_hdls; i++) {
  778. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  779. if (rc < 0) {
  780. CAM_ERR(CAM_MEM,
  781. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  782. i, fd, mmu_hdls[i], rc);
  783. goto unmap_end;
  784. }
  785. }
  786. } else {
  787. for (i = 0; i < num_hdls; i++) {
  788. if (client == CAM_SMMU_MAPPING_USER) {
  789. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  790. fd, region);
  791. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  792. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  793. tbl.bufq[idx].dma_buf, region);
  794. } else {
  795. CAM_ERR(CAM_MEM,
  796. "invalid caller for unmapping : %d",
  797. client);
  798. rc = -EINVAL;
  799. }
  800. if (rc < 0) {
  801. CAM_ERR(CAM_MEM,
  802. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  803. i, fd, mmu_hdls[i], region, rc);
  804. goto unmap_end;
  805. }
  806. }
  807. }
  808. return rc;
  809. unmap_end:
  810. CAM_ERR(CAM_MEM, "unmapping failed");
  811. return rc;
  812. }
  813. static void cam_mem_mgr_unmap_active_buf(int idx)
  814. {
  815. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  816. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  817. region = CAM_SMMU_REGION_SHARED;
  818. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  819. region = CAM_SMMU_REGION_IO;
  820. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  821. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  822. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  823. tbl.bufq[idx].kmdvaddr);
  824. }
  825. static int cam_mem_mgr_cleanup_table(void)
  826. {
  827. int i;
  828. mutex_lock(&tbl.m_lock);
  829. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  830. if (!tbl.bufq[i].active) {
  831. CAM_DBG(CAM_MEM,
  832. "Buffer inactive at idx=%d, continuing", i);
  833. continue;
  834. } else {
  835. CAM_DBG(CAM_MEM,
  836. "Active buffer at idx=%d, possible leak needs unmapping",
  837. i);
  838. cam_mem_mgr_unmap_active_buf(i);
  839. }
  840. mutex_lock(&tbl.bufq[i].q_lock);
  841. if (tbl.bufq[i].dma_buf) {
  842. dma_buf_put(tbl.bufq[i].dma_buf);
  843. tbl.bufq[i].dma_buf = NULL;
  844. }
  845. tbl.bufq[i].fd = -1;
  846. tbl.bufq[i].flags = 0;
  847. tbl.bufq[i].buf_handle = -1;
  848. tbl.bufq[i].vaddr = 0;
  849. tbl.bufq[i].len = 0;
  850. memset(tbl.bufq[i].hdls, 0,
  851. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  852. tbl.bufq[i].num_hdl = 0;
  853. tbl.bufq[i].dma_buf = NULL;
  854. tbl.bufq[i].active = false;
  855. tbl.bufq[i].is_internal = false;
  856. mutex_unlock(&tbl.bufq[i].q_lock);
  857. mutex_destroy(&tbl.bufq[i].q_lock);
  858. }
  859. bitmap_zero(tbl.bitmap, tbl.bits);
  860. /* We need to reserve slot 0 because 0 is invalid */
  861. set_bit(0, tbl.bitmap);
  862. mutex_unlock(&tbl.m_lock);
  863. return 0;
  864. }
  865. void cam_mem_mgr_deinit(void)
  866. {
  867. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  868. cam_mem_mgr_cleanup_table();
  869. debugfs_remove_recursive(tbl.dentry);
  870. mutex_lock(&tbl.m_lock);
  871. bitmap_zero(tbl.bitmap, tbl.bits);
  872. kfree(tbl.bitmap);
  873. tbl.bitmap = NULL;
  874. tbl.dbg_buf_idx = -1;
  875. mutex_unlock(&tbl.m_lock);
  876. mutex_destroy(&tbl.m_lock);
  877. }
  878. static int cam_mem_util_unmap(int32_t idx,
  879. enum cam_smmu_mapping_client client)
  880. {
  881. int rc = 0;
  882. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  883. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  884. CAM_ERR(CAM_MEM, "Incorrect index");
  885. return -EINVAL;
  886. }
  887. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  888. mutex_lock(&tbl.m_lock);
  889. if ((!tbl.bufq[idx].active) &&
  890. (tbl.bufq[idx].vaddr) == 0) {
  891. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  892. idx);
  893. mutex_unlock(&tbl.m_lock);
  894. return 0;
  895. }
  896. /* Deactivate the buffer queue to prevent multiple unmap */
  897. mutex_lock(&tbl.bufq[idx].q_lock);
  898. tbl.bufq[idx].active = false;
  899. tbl.bufq[idx].vaddr = 0;
  900. mutex_unlock(&tbl.bufq[idx].q_lock);
  901. mutex_unlock(&tbl.m_lock);
  902. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  903. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  904. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  905. tbl.bufq[idx].kmdvaddr);
  906. if (rc)
  907. CAM_ERR(CAM_MEM,
  908. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  909. tbl.bufq[idx].dma_buf,
  910. (void *) tbl.bufq[idx].kmdvaddr);
  911. }
  912. }
  913. /* SHARED flag gets precedence, all other flags after it */
  914. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  915. region = CAM_SMMU_REGION_SHARED;
  916. } else {
  917. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  918. region = CAM_SMMU_REGION_IO;
  919. }
  920. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  921. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  922. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  923. if (cam_mem_util_unmap_hw_va(idx, region, client))
  924. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  925. tbl.bufq[idx].dma_buf);
  926. if (client == CAM_SMMU_MAPPING_KERNEL)
  927. tbl.bufq[idx].dma_buf = NULL;
  928. }
  929. mutex_lock(&tbl.m_lock);
  930. mutex_lock(&tbl.bufq[idx].q_lock);
  931. tbl.bufq[idx].flags = 0;
  932. tbl.bufq[idx].buf_handle = -1;
  933. memset(tbl.bufq[idx].hdls, 0,
  934. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  935. CAM_DBG(CAM_MEM,
  936. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  937. idx, tbl.bufq[idx].fd,
  938. tbl.bufq[idx].is_imported,
  939. tbl.bufq[idx].dma_buf);
  940. if (tbl.bufq[idx].dma_buf)
  941. dma_buf_put(tbl.bufq[idx].dma_buf);
  942. tbl.bufq[idx].fd = -1;
  943. tbl.bufq[idx].dma_buf = NULL;
  944. tbl.bufq[idx].is_imported = false;
  945. tbl.bufq[idx].is_internal = false;
  946. tbl.bufq[idx].len = 0;
  947. tbl.bufq[idx].num_hdl = 0;
  948. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  949. mutex_unlock(&tbl.bufq[idx].q_lock);
  950. mutex_destroy(&tbl.bufq[idx].q_lock);
  951. clear_bit(idx, tbl.bitmap);
  952. mutex_unlock(&tbl.m_lock);
  953. return rc;
  954. }
  955. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  956. {
  957. int idx;
  958. int rc;
  959. if (!atomic_read(&cam_mem_mgr_state)) {
  960. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  961. return -EINVAL;
  962. }
  963. if (!cmd) {
  964. CAM_ERR(CAM_MEM, "Invalid argument");
  965. return -EINVAL;
  966. }
  967. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  968. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  969. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  970. idx);
  971. return -EINVAL;
  972. }
  973. if (!tbl.bufq[idx].active) {
  974. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  975. return -EINVAL;
  976. }
  977. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  978. CAM_ERR(CAM_MEM,
  979. "Released buf handle %d not matching within table %d, idx=%d",
  980. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  981. return -EINVAL;
  982. }
  983. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  984. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  985. return rc;
  986. }
  987. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  988. struct cam_mem_mgr_memory_desc *out)
  989. {
  990. struct dma_buf *buf = NULL;
  991. int ion_fd = -1;
  992. int rc = 0;
  993. uintptr_t kvaddr;
  994. dma_addr_t iova = 0;
  995. size_t request_len = 0;
  996. uint32_t mem_handle;
  997. int32_t idx;
  998. int32_t smmu_hdl = 0;
  999. int32_t num_hdl = 0;
  1000. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1001. if (!atomic_read(&cam_mem_mgr_state)) {
  1002. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1003. return -EINVAL;
  1004. }
  1005. if (!inp || !out) {
  1006. CAM_ERR(CAM_MEM, "Invalid params");
  1007. return -EINVAL;
  1008. }
  1009. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1010. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1011. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1012. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1013. return -EINVAL;
  1014. }
  1015. rc = cam_mem_util_get_dma_buf(inp->size,
  1016. inp->flags,
  1017. &buf);
  1018. if (rc) {
  1019. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1020. goto ion_fail;
  1021. } else {
  1022. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1023. }
  1024. /*
  1025. * we are mapping kva always here,
  1026. * update flags so that we do unmap properly
  1027. */
  1028. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1029. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1030. if (rc) {
  1031. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1032. goto map_fail;
  1033. }
  1034. if (!inp->smmu_hdl) {
  1035. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1036. rc = -EINVAL;
  1037. goto smmu_fail;
  1038. }
  1039. /* SHARED flag gets precedence, all other flags after it */
  1040. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1041. region = CAM_SMMU_REGION_SHARED;
  1042. } else {
  1043. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1044. region = CAM_SMMU_REGION_IO;
  1045. }
  1046. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1047. buf,
  1048. CAM_SMMU_MAP_RW,
  1049. &iova,
  1050. &request_len,
  1051. region);
  1052. if (rc < 0) {
  1053. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1054. goto smmu_fail;
  1055. }
  1056. smmu_hdl = inp->smmu_hdl;
  1057. num_hdl = 1;
  1058. idx = cam_mem_get_slot();
  1059. if (idx < 0) {
  1060. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1061. rc = -ENOMEM;
  1062. goto slot_fail;
  1063. }
  1064. mutex_lock(&tbl.bufq[idx].q_lock);
  1065. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1066. tbl.bufq[idx].dma_buf = buf;
  1067. tbl.bufq[idx].fd = -1;
  1068. tbl.bufq[idx].flags = inp->flags;
  1069. tbl.bufq[idx].buf_handle = mem_handle;
  1070. tbl.bufq[idx].kmdvaddr = kvaddr;
  1071. tbl.bufq[idx].vaddr = iova;
  1072. tbl.bufq[idx].len = inp->size;
  1073. tbl.bufq[idx].num_hdl = num_hdl;
  1074. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1075. sizeof(int32_t));
  1076. tbl.bufq[idx].is_imported = false;
  1077. mutex_unlock(&tbl.bufq[idx].q_lock);
  1078. out->kva = kvaddr;
  1079. out->iova = (uint32_t)iova;
  1080. out->smmu_hdl = smmu_hdl;
  1081. out->mem_handle = mem_handle;
  1082. out->len = inp->size;
  1083. out->region = region;
  1084. return rc;
  1085. slot_fail:
  1086. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1087. buf, region);
  1088. smmu_fail:
  1089. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1090. map_fail:
  1091. dma_buf_put(buf);
  1092. ion_fail:
  1093. return rc;
  1094. }
  1095. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1096. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1097. {
  1098. int32_t idx;
  1099. int rc;
  1100. if (!atomic_read(&cam_mem_mgr_state)) {
  1101. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1102. return -EINVAL;
  1103. }
  1104. if (!inp) {
  1105. CAM_ERR(CAM_MEM, "Invalid argument");
  1106. return -EINVAL;
  1107. }
  1108. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1109. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1110. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1111. return -EINVAL;
  1112. }
  1113. if (!tbl.bufq[idx].active) {
  1114. if (tbl.bufq[idx].vaddr == 0) {
  1115. CAM_ERR(CAM_MEM, "buffer is released already");
  1116. return 0;
  1117. }
  1118. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1119. return -EINVAL;
  1120. }
  1121. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1122. CAM_ERR(CAM_MEM,
  1123. "Released buf handle not matching within table");
  1124. return -EINVAL;
  1125. }
  1126. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1127. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1128. return rc;
  1129. }
  1130. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1131. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1132. enum cam_smmu_region_id region,
  1133. struct cam_mem_mgr_memory_desc *out)
  1134. {
  1135. struct dma_buf *buf = NULL;
  1136. int rc = 0;
  1137. int ion_fd = -1;
  1138. dma_addr_t iova = 0;
  1139. size_t request_len = 0;
  1140. uint32_t mem_handle;
  1141. int32_t idx;
  1142. int32_t smmu_hdl = 0;
  1143. int32_t num_hdl = 0;
  1144. if (!atomic_read(&cam_mem_mgr_state)) {
  1145. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1146. return -EINVAL;
  1147. }
  1148. if (!inp || !out) {
  1149. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1150. return -EINVAL;
  1151. }
  1152. if (!inp->smmu_hdl) {
  1153. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1154. return -EINVAL;
  1155. }
  1156. if (region != CAM_SMMU_REGION_SECHEAP) {
  1157. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1158. return -EINVAL;
  1159. }
  1160. rc = cam_mem_util_get_dma_buf(inp->size,
  1161. 0,
  1162. &buf);
  1163. if (rc) {
  1164. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1165. goto ion_fail;
  1166. } else {
  1167. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1168. }
  1169. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1170. buf,
  1171. &iova,
  1172. &request_len);
  1173. if (rc) {
  1174. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1175. goto smmu_fail;
  1176. }
  1177. smmu_hdl = inp->smmu_hdl;
  1178. num_hdl = 1;
  1179. idx = cam_mem_get_slot();
  1180. if (idx < 0) {
  1181. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1182. rc = -ENOMEM;
  1183. goto slot_fail;
  1184. }
  1185. mutex_lock(&tbl.bufq[idx].q_lock);
  1186. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1187. tbl.bufq[idx].fd = -1;
  1188. tbl.bufq[idx].dma_buf = buf;
  1189. tbl.bufq[idx].flags = inp->flags;
  1190. tbl.bufq[idx].buf_handle = mem_handle;
  1191. tbl.bufq[idx].kmdvaddr = 0;
  1192. tbl.bufq[idx].vaddr = iova;
  1193. tbl.bufq[idx].len = request_len;
  1194. tbl.bufq[idx].num_hdl = num_hdl;
  1195. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1196. sizeof(int32_t));
  1197. tbl.bufq[idx].is_imported = false;
  1198. mutex_unlock(&tbl.bufq[idx].q_lock);
  1199. out->kva = 0;
  1200. out->iova = (uint32_t)iova;
  1201. out->smmu_hdl = smmu_hdl;
  1202. out->mem_handle = mem_handle;
  1203. out->len = request_len;
  1204. out->region = region;
  1205. return rc;
  1206. slot_fail:
  1207. cam_smmu_release_sec_heap(smmu_hdl);
  1208. smmu_fail:
  1209. dma_buf_put(buf);
  1210. ion_fail:
  1211. return rc;
  1212. }
  1213. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1214. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1215. {
  1216. int32_t idx;
  1217. int rc;
  1218. int32_t smmu_hdl;
  1219. if (!atomic_read(&cam_mem_mgr_state)) {
  1220. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1221. return -EINVAL;
  1222. }
  1223. if (!inp) {
  1224. CAM_ERR(CAM_MEM, "Invalid argument");
  1225. return -EINVAL;
  1226. }
  1227. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1228. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1229. return -EINVAL;
  1230. }
  1231. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1232. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1233. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1234. return -EINVAL;
  1235. }
  1236. if (!tbl.bufq[idx].active) {
  1237. if (tbl.bufq[idx].vaddr == 0) {
  1238. CAM_ERR(CAM_MEM, "buffer is released already");
  1239. return 0;
  1240. }
  1241. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1242. return -EINVAL;
  1243. }
  1244. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1245. CAM_ERR(CAM_MEM,
  1246. "Released buf handle not matching within table");
  1247. return -EINVAL;
  1248. }
  1249. if (tbl.bufq[idx].num_hdl != 1) {
  1250. CAM_ERR(CAM_MEM,
  1251. "Sec heap region should have only one smmu hdl");
  1252. return -ENODEV;
  1253. }
  1254. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1255. sizeof(int32_t));
  1256. if (inp->smmu_hdl != smmu_hdl) {
  1257. CAM_ERR(CAM_MEM,
  1258. "Passed SMMU handle doesn't match with internal hdl");
  1259. return -ENODEV;
  1260. }
  1261. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1262. if (rc) {
  1263. CAM_ERR(CAM_MEM,
  1264. "Sec heap region release failed");
  1265. return -ENODEV;
  1266. }
  1267. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1268. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1269. if (rc)
  1270. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1271. return rc;
  1272. }
  1273. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);