dp_li_rx.c 24 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "cdp_txrx_cmn_struct.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_types.h"
  21. #include "dp_rx.h"
  22. #include "dp_li_rx.h"
  23. #include "dp_peer.h"
  24. #include "hal_rx.h"
  25. #include "hal_li_rx.h"
  26. #include "hal_api.h"
  27. #include "hal_li_api.h"
  28. #include "qdf_nbuf.h"
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "dp_internal.h"
  33. #include "dp_ipa.h"
  34. #ifdef WIFI_MONITOR_SUPPORT
  35. #include <dp_mon.h>
  36. #endif
  37. #ifdef FEATURE_WDS
  38. #include "dp_txrx_wds.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #include "dp_rx_buffer_pool.h"
  42. static inline
  43. bool is_sa_da_idx_valid(struct dp_soc *soc, uint8_t *rx_tlv_hdr,
  44. qdf_nbuf_t nbuf, struct hal_rx_msdu_metadata msdu_info)
  45. {
  46. if ((qdf_nbuf_is_sa_valid(nbuf) &&
  47. (msdu_info.sa_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))) ||
  48. (!qdf_nbuf_is_da_mcbc(nbuf) && qdf_nbuf_is_da_valid(nbuf) &&
  49. (msdu_info.da_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))))
  50. return false;
  51. return true;
  52. }
  53. /**
  54. * dp_rx_process_li() - Brain of the Rx processing functionality
  55. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  56. * @int_ctx: per interrupt context
  57. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  58. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  59. * @quota: No. of units (packets) that can be serviced in one shot.
  60. *
  61. * This function implements the core of Rx functionality. This is
  62. * expected to handle only non-error frames.
  63. *
  64. * Return: uint32_t: No. of elements processed
  65. */
  66. uint32_t dp_rx_process_li(struct dp_intr *int_ctx,
  67. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  68. uint32_t quota)
  69. {
  70. hal_ring_desc_t ring_desc;
  71. hal_soc_handle_t hal_soc;
  72. struct dp_rx_desc *rx_desc = NULL;
  73. qdf_nbuf_t nbuf, next;
  74. bool near_full;
  75. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  76. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  77. uint32_t num_pending;
  78. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  79. uint16_t msdu_len = 0;
  80. uint16_t peer_id;
  81. uint8_t vdev_id;
  82. struct dp_peer *peer;
  83. struct dp_vdev *vdev;
  84. uint32_t pkt_len = 0;
  85. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  86. struct hal_rx_msdu_desc_info msdu_desc_info;
  87. enum hal_reo_error_status error;
  88. uint32_t peer_mdata;
  89. uint8_t *rx_tlv_hdr;
  90. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  91. uint8_t mac_id = 0;
  92. struct dp_pdev *rx_pdev;
  93. struct dp_srng *dp_rxdma_srng;
  94. struct rx_desc_pool *rx_desc_pool;
  95. struct dp_soc *soc = int_ctx->soc;
  96. uint8_t core_id = 0;
  97. struct cdp_tid_rx_stats *tid_stats;
  98. qdf_nbuf_t nbuf_head;
  99. qdf_nbuf_t nbuf_tail;
  100. qdf_nbuf_t deliver_list_head;
  101. qdf_nbuf_t deliver_list_tail;
  102. uint32_t num_rx_bufs_reaped = 0;
  103. uint32_t intr_id;
  104. struct hif_opaque_softc *scn;
  105. int32_t tid = 0;
  106. bool is_prev_msdu_last = true;
  107. uint32_t num_entries_avail = 0;
  108. uint32_t rx_ol_pkt_cnt = 0;
  109. uint32_t num_entries = 0;
  110. struct hal_rx_msdu_metadata msdu_metadata;
  111. QDF_STATUS status;
  112. qdf_nbuf_t ebuf_head;
  113. qdf_nbuf_t ebuf_tail;
  114. uint8_t pkt_capture_offload = 0;
  115. int max_reap_limit;
  116. DP_HIST_INIT();
  117. qdf_assert_always(soc && hal_ring_hdl);
  118. hal_soc = soc->hal_soc;
  119. qdf_assert_always(hal_soc);
  120. scn = soc->hif_handle;
  121. hif_pm_runtime_mark_dp_rx_busy(scn);
  122. intr_id = int_ctx->dp_intr_id;
  123. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  124. more_data:
  125. /* reset local variables here to be re-used in the function */
  126. nbuf_head = NULL;
  127. nbuf_tail = NULL;
  128. deliver_list_head = NULL;
  129. deliver_list_tail = NULL;
  130. peer = NULL;
  131. vdev = NULL;
  132. num_rx_bufs_reaped = 0;
  133. ebuf_head = NULL;
  134. ebuf_tail = NULL;
  135. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  136. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  137. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  138. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  139. qdf_mem_zero(head, sizeof(head));
  140. qdf_mem_zero(tail, sizeof(tail));
  141. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  142. /*
  143. * Need API to convert from hal_ring pointer to
  144. * Ring Type / Ring Id combo
  145. */
  146. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  147. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  148. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  149. goto done;
  150. }
  151. /*
  152. * start reaping the buffers from reo ring and queue
  153. * them in per vdev queue.
  154. * Process the received pkts in a different per vdev loop.
  155. */
  156. while (qdf_likely(quota &&
  157. (ring_desc = hal_srng_dst_peek(hal_soc,
  158. hal_ring_hdl)))) {
  159. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  160. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  161. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  162. soc, hal_ring_hdl, error);
  163. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  164. 1);
  165. /* Don't know how to deal with this -- assert */
  166. qdf_assert(0);
  167. }
  168. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  169. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  170. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  171. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  172. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  173. break;
  174. }
  175. rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie);
  176. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  177. ring_desc, rx_desc);
  178. if (QDF_IS_STATUS_ERROR(status)) {
  179. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  180. qdf_assert_always(!rx_desc->unmapped);
  181. dp_ipa_reo_ctx_buf_mapping_lock(soc,
  182. reo_ring_num);
  183. dp_ipa_handle_rx_buf_smmu_mapping(
  184. soc,
  185. rx_desc->nbuf,
  186. RX_DATA_BUFFER_SIZE,
  187. false);
  188. qdf_nbuf_unmap_nbytes_single(
  189. soc->osdev,
  190. rx_desc->nbuf,
  191. QDF_DMA_FROM_DEVICE,
  192. RX_DATA_BUFFER_SIZE);
  193. rx_desc->unmapped = 1;
  194. dp_ipa_reo_ctx_buf_mapping_unlock(soc,
  195. reo_ring_num);
  196. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  197. rx_desc->pool_id);
  198. dp_rx_add_to_free_desc_list(
  199. &head[rx_desc->pool_id],
  200. &tail[rx_desc->pool_id],
  201. rx_desc);
  202. }
  203. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  204. continue;
  205. }
  206. /*
  207. * this is a unlikely scenario where the host is reaping
  208. * a descriptor which it already reaped just a while ago
  209. * but is yet to replenish it back to HW.
  210. * In this case host will dump the last 128 descriptors
  211. * including the software descriptor rx_desc and assert.
  212. */
  213. if (qdf_unlikely(!rx_desc->in_use)) {
  214. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  215. dp_info_rl("Reaping rx_desc not in use!");
  216. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  217. ring_desc, rx_desc);
  218. /* ignore duplicate RX desc and continue to process */
  219. /* Pop out the descriptor */
  220. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  221. continue;
  222. }
  223. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  224. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  225. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  226. dp_info_rl("Nbuf sanity check failure!");
  227. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  228. ring_desc, rx_desc);
  229. rx_desc->in_err_state = 1;
  230. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  231. continue;
  232. }
  233. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  234. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  235. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  236. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  237. ring_desc, rx_desc);
  238. }
  239. /* Get MPDU DESC info */
  240. hal_rx_mpdu_desc_info_get_li(ring_desc, &mpdu_desc_info);
  241. /* Get MSDU DESC info */
  242. hal_rx_msdu_desc_info_get_li(ring_desc, &msdu_desc_info);
  243. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  244. HAL_MSDU_F_MSDU_CONTINUATION)) {
  245. /* previous msdu has end bit set, so current one is
  246. * the new MPDU
  247. */
  248. if (is_prev_msdu_last) {
  249. /* Get number of entries available in HW ring */
  250. num_entries_avail =
  251. hal_srng_dst_num_valid(hal_soc,
  252. hal_ring_hdl, 1);
  253. /* For new MPDU check if we can read complete
  254. * MPDU by comparing the number of buffers
  255. * available and number of buffers needed to
  256. * reap this MPDU
  257. */
  258. if ((msdu_desc_info.msdu_len /
  259. (RX_DATA_BUFFER_SIZE -
  260. soc->rx_pkt_tlv_size) + 1) >
  261. num_entries_avail) {
  262. DP_STATS_INC(soc,
  263. rx.msdu_scatter_wait_break,
  264. 1);
  265. dp_rx_cookie_reset_invalid_bit(
  266. ring_desc);
  267. break;
  268. }
  269. is_prev_msdu_last = false;
  270. }
  271. }
  272. core_id = smp_processor_id();
  273. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  274. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  275. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  276. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  277. HAL_MPDU_F_RAW_AMPDU))
  278. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  279. if (!is_prev_msdu_last &&
  280. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  281. is_prev_msdu_last = true;
  282. /* Pop out the descriptor*/
  283. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  284. rx_bufs_reaped[rx_desc->pool_id]++;
  285. peer_mdata = mpdu_desc_info.peer_meta_data;
  286. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  287. DP_PEER_METADATA_PEER_ID_GET(peer_mdata);
  288. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  289. DP_PEER_METADATA_VDEV_ID_GET(peer_mdata);
  290. /* to indicate whether this msdu is rx offload */
  291. pkt_capture_offload =
  292. DP_PEER_METADATA_OFFLOAD_GET(peer_mdata);
  293. /*
  294. * save msdu flags first, last and continuation msdu in
  295. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  296. * length to nbuf->cb. This ensures the info required for
  297. * per pkt processing is always in the same cache line.
  298. * This helps in improving throughput for smaller pkt
  299. * sizes.
  300. */
  301. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  302. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  303. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  304. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  305. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  306. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  307. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  308. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  309. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  310. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  311. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  312. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  313. qdf_nbuf_set_tid_val(rx_desc->nbuf,
  314. HAL_RX_REO_QUEUE_NUMBER_GET(ring_desc));
  315. qdf_nbuf_set_rx_reo_dest_ind(
  316. rx_desc->nbuf,
  317. HAL_RX_REO_MSDU_REO_DST_IND_GET(ring_desc));
  318. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  319. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  320. /*
  321. * move unmap after scattered msdu waiting break logic
  322. * in case double skb unmap happened.
  323. */
  324. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  325. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  326. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  327. rx_desc_pool->buf_size,
  328. false);
  329. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  330. QDF_DMA_FROM_DEVICE,
  331. rx_desc_pool->buf_size);
  332. rx_desc->unmapped = 1;
  333. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  334. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  335. ebuf_tail, rx_desc);
  336. /*
  337. * if continuation bit is set then we have MSDU spread
  338. * across multiple buffers, let us not decrement quota
  339. * till we reap all buffers of that MSDU.
  340. */
  341. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  342. quota -= 1;
  343. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  344. &tail[rx_desc->pool_id], rx_desc);
  345. num_rx_bufs_reaped++;
  346. /*
  347. * only if complete msdu is received for scatter case,
  348. * then allow break.
  349. */
  350. if (is_prev_msdu_last &&
  351. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  352. max_reap_limit))
  353. break;
  354. }
  355. done:
  356. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  357. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  358. /*
  359. * continue with next mac_id if no pkts were reaped
  360. * from that pool
  361. */
  362. if (!rx_bufs_reaped[mac_id])
  363. continue;
  364. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  365. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  366. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  367. rx_desc_pool, rx_bufs_reaped[mac_id],
  368. &head[mac_id], &tail[mac_id]);
  369. }
  370. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  371. /* Peer can be NULL is case of LFR */
  372. if (qdf_likely(peer))
  373. vdev = NULL;
  374. /*
  375. * BIG loop where each nbuf is dequeued from global queue,
  376. * processed and queued back on a per vdev basis. These nbufs
  377. * are sent to stack as and when we run out of nbufs
  378. * or a new nbuf dequeued from global queue has a different
  379. * vdev when compared to previous nbuf.
  380. */
  381. nbuf = nbuf_head;
  382. while (nbuf) {
  383. next = nbuf->next;
  384. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  385. nbuf = next;
  386. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  387. continue;
  388. }
  389. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  390. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  391. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  392. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  393. peer_id, vdev_id)) {
  394. dp_rx_deliver_to_stack(soc, vdev, peer,
  395. deliver_list_head,
  396. deliver_list_tail);
  397. deliver_list_head = NULL;
  398. deliver_list_tail = NULL;
  399. }
  400. /* Get TID from struct cb->tid_val, save to tid */
  401. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  402. tid = qdf_nbuf_get_tid_val(nbuf);
  403. if (qdf_unlikely(!peer)) {
  404. peer = dp_peer_get_ref_by_id(soc, peer_id,
  405. DP_MOD_ID_RX);
  406. } else if (peer && peer->peer_id != peer_id) {
  407. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  408. peer = dp_peer_get_ref_by_id(soc, peer_id,
  409. DP_MOD_ID_RX);
  410. }
  411. if (peer) {
  412. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  413. qdf_dp_trace_set_track(nbuf, QDF_RX);
  414. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  415. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  416. QDF_NBUF_RX_PKT_DATA_TRACK;
  417. }
  418. rx_bufs_used++;
  419. if (qdf_likely(peer)) {
  420. vdev = peer->vdev;
  421. } else {
  422. nbuf->next = NULL;
  423. dp_rx_deliver_to_pkt_capture_no_peer(
  424. soc, nbuf, pkt_capture_offload);
  425. if (!pkt_capture_offload)
  426. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  427. nbuf = next;
  428. continue;
  429. }
  430. if (qdf_unlikely(!vdev)) {
  431. qdf_nbuf_free(nbuf);
  432. nbuf = next;
  433. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  434. continue;
  435. }
  436. /* when hlos tid override is enabled, save tid in
  437. * skb->priority
  438. */
  439. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  440. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  441. qdf_nbuf_set_priority(nbuf, tid);
  442. rx_pdev = vdev->pdev;
  443. DP_RX_TID_SAVE(nbuf, tid);
  444. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  445. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  446. soc->wlan_cfg_ctx)))
  447. qdf_nbuf_set_timestamp(nbuf);
  448. tid_stats =
  449. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  450. /*
  451. * Check if DMA completed -- msdu_done is the last bit
  452. * to be written
  453. */
  454. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(nbuf))) {
  455. if (qdf_unlikely(!hal_rx_attn_msdu_done_get_li(
  456. rx_tlv_hdr))) {
  457. dp_err_rl("MSDU DONE failure");
  458. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  459. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  460. QDF_TRACE_LEVEL_INFO);
  461. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  462. qdf_assert(0);
  463. qdf_nbuf_free(nbuf);
  464. nbuf = next;
  465. continue;
  466. } else if (qdf_unlikely(hal_rx_attn_msdu_len_err_get_li(
  467. rx_tlv_hdr))) {
  468. DP_STATS_INC(soc, rx.err.msdu_len_err, 1);
  469. qdf_nbuf_free(nbuf);
  470. nbuf = next;
  471. continue;
  472. }
  473. }
  474. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  475. /*
  476. * First IF condition:
  477. * 802.11 Fragmented pkts are reinjected to REO
  478. * HW block as SG pkts and for these pkts we only
  479. * need to pull the RX TLVS header length.
  480. * Second IF condition:
  481. * The below condition happens when an MSDU is spread
  482. * across multiple buffers. This can happen in two cases
  483. * 1. The nbuf size is smaller then the received msdu.
  484. * ex: we have set the nbuf size to 2048 during
  485. * nbuf_alloc. but we received an msdu which is
  486. * 2304 bytes in size then this msdu is spread
  487. * across 2 nbufs.
  488. *
  489. * 2. AMSDUs when RAW mode is enabled.
  490. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  491. * across 1st nbuf and 2nd nbuf and last MSDU is
  492. * spread across 2nd nbuf and 3rd nbuf.
  493. *
  494. * for these scenarios let us create a skb frag_list and
  495. * append these buffers till the last MSDU of the AMSDU
  496. * Third condition:
  497. * This is the most likely case, we receive 802.3 pkts
  498. * decapsulated by HW, here we need to set the pkt length.
  499. */
  500. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  501. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  502. bool is_mcbc, is_sa_vld, is_da_vld;
  503. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  504. rx_tlv_hdr);
  505. is_sa_vld =
  506. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  507. rx_tlv_hdr);
  508. is_da_vld =
  509. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  510. rx_tlv_hdr);
  511. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  512. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  513. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  514. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  515. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  516. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  517. nbuf = dp_rx_sg_create(soc, nbuf);
  518. next = nbuf->next;
  519. if (qdf_nbuf_is_raw_frame(nbuf)) {
  520. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  521. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  522. } else {
  523. qdf_nbuf_free(nbuf);
  524. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  525. dp_info_rl("scatter msdu len %d, dropped",
  526. msdu_len);
  527. nbuf = next;
  528. continue;
  529. }
  530. } else {
  531. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  532. pkt_len = msdu_len +
  533. msdu_metadata.l3_hdr_pad +
  534. soc->rx_pkt_tlv_size;
  535. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  536. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  537. }
  538. /*
  539. * process frame for mulitpass phrase processing
  540. */
  541. if (qdf_unlikely(vdev->multipass_en)) {
  542. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  543. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  544. qdf_nbuf_free(nbuf);
  545. nbuf = next;
  546. continue;
  547. }
  548. }
  549. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  550. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  551. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  552. /* Drop & free packet */
  553. qdf_nbuf_free(nbuf);
  554. /* Statistics */
  555. nbuf = next;
  556. continue;
  557. }
  558. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  559. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  560. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  561. rx_tlv_hdr) ==
  562. false))) {
  563. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  564. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  565. qdf_nbuf_free(nbuf);
  566. nbuf = next;
  567. continue;
  568. }
  569. /*
  570. * Drop non-EAPOL frames from unauthorized peer.
  571. */
  572. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  573. !qdf_nbuf_is_raw_frame(nbuf)) {
  574. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  575. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  576. if (!is_eapol) {
  577. DP_STATS_INC(soc,
  578. rx.err.peer_unauth_rx_pkt_drop,
  579. 1);
  580. qdf_nbuf_free(nbuf);
  581. nbuf = next;
  582. continue;
  583. }
  584. }
  585. if (soc->process_rx_status)
  586. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  587. /* Update the protocol tag in SKB based on CCE metadata */
  588. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  589. reo_ring_num, false, true);
  590. /* Update the flow tag in SKB based on FSE metadata */
  591. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  592. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  593. reo_ring_num, tid_stats);
  594. if (qdf_unlikely(vdev->mesh_vdev)) {
  595. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  596. == QDF_STATUS_SUCCESS) {
  597. dp_rx_info("%pK: mesh pkt filtered", soc);
  598. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  599. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  600. 1);
  601. qdf_nbuf_free(nbuf);
  602. nbuf = next;
  603. continue;
  604. }
  605. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  606. }
  607. if (qdf_likely(vdev->rx_decap_type ==
  608. htt_cmn_pkt_type_ethernet) &&
  609. qdf_likely(!vdev->mesh_vdev)) {
  610. /* WDS Destination Address Learning */
  611. dp_rx_da_learn(soc, rx_tlv_hdr, peer, nbuf);
  612. /* Due to HW issue, sometimes we see that the sa_idx
  613. * and da_idx are invalid with sa_valid and da_valid
  614. * bits set
  615. *
  616. * in this case we also see that value of
  617. * sa_sw_peer_id is set as 0
  618. *
  619. * Drop the packet if sa_idx and da_idx OOB or
  620. * sa_sw_peerid is 0
  621. */
  622. if (!is_sa_da_idx_valid(soc, rx_tlv_hdr, nbuf,
  623. msdu_metadata)) {
  624. qdf_nbuf_free(nbuf);
  625. nbuf = next;
  626. DP_STATS_INC(soc, rx.err.invalid_sa_da_idx, 1);
  627. continue;
  628. }
  629. /* WDS Source Port Learning */
  630. if (qdf_likely(vdev->wds_enabled))
  631. dp_rx_wds_srcport_learn(soc,
  632. rx_tlv_hdr,
  633. peer,
  634. nbuf,
  635. msdu_metadata);
  636. /* Intrabss-fwd */
  637. if (dp_rx_check_ap_bridge(vdev))
  638. if (DP_RX_INTRABSS_FWD(soc, peer, rx_tlv_hdr,
  639. nbuf, msdu_metadata)) {
  640. nbuf = next;
  641. tid_stats->intrabss_cnt++;
  642. continue; /* Get next desc */
  643. }
  644. }
  645. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  646. dp_rx_update_stats(soc, nbuf);
  647. DP_RX_LIST_APPEND(deliver_list_head,
  648. deliver_list_tail,
  649. nbuf);
  650. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  651. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  652. if (qdf_unlikely(peer->in_twt))
  653. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  654. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  655. tid_stats->delivered_to_stack++;
  656. nbuf = next;
  657. }
  658. if (qdf_likely(deliver_list_head)) {
  659. if (qdf_likely(peer)) {
  660. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  661. pkt_capture_offload,
  662. deliver_list_head);
  663. if (!pkt_capture_offload)
  664. dp_rx_deliver_to_stack(soc, vdev, peer,
  665. deliver_list_head,
  666. deliver_list_tail);
  667. } else {
  668. nbuf = deliver_list_head;
  669. while (nbuf) {
  670. next = nbuf->next;
  671. nbuf->next = NULL;
  672. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  673. nbuf = next;
  674. }
  675. }
  676. }
  677. if (qdf_likely(peer))
  678. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  679. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  680. if (quota) {
  681. num_pending =
  682. dp_rx_srng_get_num_pending(hal_soc,
  683. hal_ring_hdl,
  684. num_entries,
  685. &near_full);
  686. if (num_pending) {
  687. DP_STATS_INC(soc, rx.hp_oos2, 1);
  688. if (!hif_exec_should_yield(scn, intr_id))
  689. goto more_data;
  690. if (qdf_unlikely(near_full)) {
  691. DP_STATS_INC(soc, rx.near_full, 1);
  692. goto more_data;
  693. }
  694. }
  695. }
  696. if (vdev && vdev->osif_fisa_flush)
  697. vdev->osif_fisa_flush(soc, reo_ring_num);
  698. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  699. vdev->osif_gro_flush(vdev->osif_vdev,
  700. reo_ring_num);
  701. }
  702. }
  703. /* Update histogram statistics by looping through pdev's */
  704. DP_RX_HIST_STATS_PER_PDEV();
  705. return rx_bufs_used; /* Assume no scale factor for now */
  706. }
  707. QDF_STATUS dp_rx_desc_pool_init_li(struct dp_soc *soc,
  708. struct rx_desc_pool *rx_desc_pool,
  709. uint32_t pool_id)
  710. {
  711. return dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  712. }
  713. void dp_rx_desc_pool_deinit_li(struct dp_soc *soc,
  714. struct rx_desc_pool *rx_desc_pool,
  715. uint32_t pool_id)
  716. {
  717. }
  718. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_li(
  719. struct dp_soc *soc,
  720. void *ring_desc,
  721. struct dp_rx_desc **r_rx_desc)
  722. {
  723. struct hal_buf_info buf_info = {0};
  724. hal_soc_handle_t hal_soc = soc->hal_soc;
  725. /* only cookie and rbm will be valid in buf_info */
  726. hal_rx_buf_cookie_rbm_get(hal_soc, (uint32_t *)ring_desc,
  727. &buf_info);
  728. if (qdf_unlikely(buf_info.rbm !=
  729. HAL_RX_BUF_RBM_SW3_BM(soc->wbm_sw0_bm_id))) {
  730. /* TODO */
  731. /* Call appropriate handler */
  732. DP_STATS_INC(soc, rx.err.invalid_rbm, 1);
  733. dp_rx_err("%pK: Invalid RBM %d", soc, buf_info.rbm);
  734. return QDF_STATUS_E_INVAL;
  735. }
  736. *r_rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, buf_info.sw_cookie);
  737. return QDF_STATUS_SUCCESS;
  738. }