wcd937x.c 82 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define NUM_SWRS_DT_PARAMS 5
  30. #define WCD937X_VERSION_1_0 1
  31. #define WCD937X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. enum {
  34. CODEC_TX = 0,
  35. CODEC_RX,
  36. };
  37. enum {
  38. ALLOW_BUCK_DISABLE,
  39. HPH_COMP_DELAY,
  40. HPH_PA_DELAY,
  41. };
  42. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  43. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  44. static int wcd937x_handle_post_irq(void *data);
  45. static int wcd937x_reset(struct device *dev);
  46. static int wcd937x_reset_low(struct device *dev);
  47. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  48. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  49. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  68. };
  69. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  70. .name = "wcd937x",
  71. .irqs = wcd937x_irqs,
  72. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  73. .num_regs = 3,
  74. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  75. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  76. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  77. .use_ack = 1,
  78. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  79. .runtime_pm = false,
  80. .handle_post_irq = wcd937x_handle_post_irq,
  81. .irq_drv_data = NULL,
  82. };
  83. static int wcd937x_handle_post_irq(void *data)
  84. {
  85. struct wcd937x_priv *wcd937x = data;
  86. u32 status1 = 0, status2 = 0, status3 = 0;
  87. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  88. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  90. wcd937x->tx_swr_dev->slave_irq_pending =
  91. ((status1 || status2 || status3) ? true : false);
  92. return IRQ_HANDLED;
  93. }
  94. static int wcd937x_init_reg(struct snd_soc_component *component)
  95. {
  96. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  97. 0x0E, 0x0E);
  98. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  99. 0x80, 0x80);
  100. usleep_range(1000, 1010);
  101. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  102. 0x40, 0x40);
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  105. 0x10, 0x00);
  106. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  107. 0xF0, 0x80);
  108. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  109. 0x80, 0x80);
  110. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  111. 0x40, 0x40);
  112. usleep_range(10000, 10010);
  113. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  114. 0x40, 0x00);
  115. snd_soc_component_update_bits(component, WCD937X_HPH_OCP_CTL,
  116. 0xFF, 0x3A);
  117. snd_soc_component_update_bits(component, WCD937X_RX_OCP_CTL,
  118. 0x0F, 0x02);
  119. snd_soc_component_update_bits(component,
  120. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  121. 0xFF, 0xD9);
  122. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  123. 0xFF, 0xFA);
  124. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  125. 0xFF, 0xFA);
  126. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  127. 0xFF, 0xFA);
  128. return 0;
  129. }
  130. static int wcd937x_set_port_params(struct snd_soc_component *component,
  131. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  132. u8 *ch_mask, u32 *ch_rate,
  133. u8 *port_type, u8 path)
  134. {
  135. int i, j;
  136. u8 num_ports = 0;
  137. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  138. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  139. switch (path) {
  140. case CODEC_RX:
  141. map = &wcd937x->rx_port_mapping;
  142. num_ports = wcd937x->num_rx_ports;
  143. break;
  144. case CODEC_TX:
  145. map = &wcd937x->tx_port_mapping;
  146. num_ports = wcd937x->num_tx_ports;
  147. break;
  148. }
  149. for (i = 0; i <= num_ports; i++) {
  150. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  151. if ((*map)[i][j].slave_port_type == slv_prt_type)
  152. goto found;
  153. }
  154. }
  155. found:
  156. if (i > num_ports || j == MAX_CH_PER_PORT) {
  157. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  158. __func__, slv_prt_type);
  159. return -EINVAL;
  160. }
  161. *port_id = i;
  162. *num_ch = (*map)[i][j].num_ch;
  163. *ch_mask = (*map)[i][j].ch_mask;
  164. *ch_rate = (*map)[i][j].ch_rate;
  165. *port_type = (*map)[i][j].master_port_type;
  166. return 0;
  167. }
  168. static int wcd937x_parse_port_mapping(struct device *dev,
  169. char *prop, u8 path)
  170. {
  171. u32 *dt_array, map_size, map_length;
  172. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  173. u32 slave_port_type, master_port_type;
  174. u32 i, ch_iter = 0;
  175. int ret = 0;
  176. u8 *num_ports = NULL;
  177. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  178. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  179. switch (path) {
  180. case CODEC_RX:
  181. map = &wcd937x->rx_port_mapping;
  182. num_ports = &wcd937x->num_rx_ports;
  183. break;
  184. case CODEC_TX:
  185. map = &wcd937x->tx_port_mapping;
  186. num_ports = &wcd937x->num_tx_ports;
  187. break;
  188. }
  189. if (!of_find_property(dev->of_node, prop,
  190. &map_size)) {
  191. dev_err(dev, "missing port mapping prop %s\n", prop);
  192. ret = -EINVAL;
  193. goto err;
  194. }
  195. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  196. dt_array = kzalloc(map_size, GFP_KERNEL);
  197. if (!dt_array) {
  198. ret = -ENOMEM;
  199. goto err;
  200. }
  201. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  202. NUM_SWRS_DT_PARAMS * map_length);
  203. if (ret) {
  204. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  205. __func__, prop);
  206. ret = -EINVAL;
  207. goto err_pdata_fail;
  208. }
  209. for (i = 0; i < map_length; i++) {
  210. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  211. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  212. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  213. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  214. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  215. if (port_num != old_port_num)
  216. ch_iter = 0;
  217. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  218. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  219. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  220. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  221. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  222. old_port_num = port_num;
  223. }
  224. *num_ports = port_num;
  225. kfree(dt_array);
  226. return 0;
  227. err_pdata_fail:
  228. kfree(dt_array);
  229. err:
  230. return ret;
  231. }
  232. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  233. u8 slv_port_type, u8 enable)
  234. {
  235. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  236. u8 port_id;
  237. u8 num_ch;
  238. u8 ch_mask;
  239. u32 ch_rate;
  240. u8 port_type;
  241. u8 num_port = 1;
  242. int ret = 0;
  243. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  244. &num_ch, &ch_mask, &ch_rate,
  245. &port_type, CODEC_TX);
  246. if (ret)
  247. return ret;
  248. if (enable)
  249. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  250. num_port, &ch_mask, &ch_rate,
  251. &num_ch, &port_type);
  252. else
  253. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  254. num_port, &ch_mask, &port_type);
  255. return ret;
  256. }
  257. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  258. u8 slv_port_type, u8 enable)
  259. {
  260. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  261. u8 port_id;
  262. u8 num_ch;
  263. u8 ch_mask;
  264. u32 ch_rate;
  265. u8 port_type;
  266. u8 num_port = 1;
  267. int ret = 0;
  268. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  269. &num_ch, &ch_mask, &ch_rate,
  270. &port_type, CODEC_RX);
  271. if (ret)
  272. return ret;
  273. if (enable)
  274. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  275. num_port, &ch_mask, &ch_rate,
  276. &num_ch, &port_type);
  277. else
  278. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  279. num_port, &ch_mask, &port_type);
  280. return ret;
  281. }
  282. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  283. {
  284. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  285. if (wcd937x->rx_clk_cnt == 0) {
  286. snd_soc_component_update_bits(component,
  287. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  288. snd_soc_component_update_bits(component,
  289. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  290. snd_soc_component_update_bits(component,
  291. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  292. snd_soc_component_update_bits(component,
  293. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  294. snd_soc_component_update_bits(component,
  295. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  296. snd_soc_component_update_bits(component,
  297. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  298. snd_soc_component_update_bits(component,
  299. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  300. }
  301. wcd937x->rx_clk_cnt++;
  302. return 0;
  303. }
  304. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  305. {
  306. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  307. if (wcd937x->rx_clk_cnt == 0) {
  308. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  309. return 0;
  310. }
  311. wcd937x->rx_clk_cnt--;
  312. if (wcd937x->rx_clk_cnt == 0) {
  313. snd_soc_component_update_bits(component,
  314. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  315. snd_soc_component_update_bits(component,
  316. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  317. 0x02, 0x00);
  318. snd_soc_component_update_bits(component,
  319. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  320. 0x01, 0x00);
  321. }
  322. return 0;
  323. }
  324. /*
  325. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  326. * @component: handle to snd_soc_component *
  327. *
  328. * return wcd937x_mbhc handle or error code in case of failure
  329. */
  330. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  331. {
  332. struct wcd937x_priv *wcd937x;
  333. if (!component) {
  334. pr_err("%s: Invalid params, NULL component\n", __func__);
  335. return NULL;
  336. }
  337. wcd937x = snd_soc_component_get_drvdata(component);
  338. if (!wcd937x) {
  339. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  340. return NULL;
  341. }
  342. return wcd937x->mbhc;
  343. }
  344. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  345. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  346. struct snd_kcontrol *kcontrol,
  347. int event)
  348. {
  349. struct snd_soc_component *component =
  350. snd_soc_dapm_to_component(w->dapm);
  351. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  352. int hph_mode = wcd937x->hph_mode;
  353. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  354. w->name, event);
  355. switch (event) {
  356. case SND_SOC_DAPM_PRE_PMU:
  357. wcd937x_rx_clk_enable(component);
  358. snd_soc_component_update_bits(component,
  359. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  360. 0x01, 0x01);
  361. snd_soc_component_update_bits(component,
  362. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  363. 0x04, 0x04);
  364. snd_soc_component_update_bits(component,
  365. WCD937X_HPH_RDAC_CLK_CTL1,
  366. 0x80, 0x00);
  367. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  368. break;
  369. case SND_SOC_DAPM_POST_PMU:
  370. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  371. snd_soc_component_update_bits(component,
  372. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  373. 0x0F, 0x02);
  374. else if (hph_mode == CLS_H_LOHIFI)
  375. snd_soc_component_update_bits(component,
  376. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  377. 0x0F, 0x06);
  378. if (wcd937x->comp1_enable) {
  379. snd_soc_component_update_bits(component,
  380. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  381. 0x02, 0x02);
  382. snd_soc_component_update_bits(component,
  383. WCD937X_HPH_L_EN, 0x20, 0x00);
  384. if (wcd937x->comp2_enable) {
  385. snd_soc_component_update_bits(component,
  386. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  387. 0x01, 0x01);
  388. snd_soc_component_update_bits(component,
  389. WCD937X_HPH_R_EN, 0x20, 0x00);
  390. }
  391. /*
  392. * 5ms sleep is required after COMP is enabled as per
  393. * HW requirement
  394. */
  395. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  396. usleep_range(5000, 5100);
  397. clear_bit(HPH_COMP_DELAY,
  398. &wcd937x->status_mask);
  399. }
  400. } else {
  401. snd_soc_component_update_bits(component,
  402. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  403. 0x02, 0x00);
  404. snd_soc_component_update_bits(component,
  405. WCD937X_HPH_L_EN, 0x20, 0x20);
  406. }
  407. snd_soc_component_update_bits(component,
  408. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  409. break;
  410. case SND_SOC_DAPM_POST_PMD:
  411. snd_soc_component_update_bits(component,
  412. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  413. 0x0F, 0x01);
  414. break;
  415. }
  416. return 0;
  417. }
  418. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  419. struct snd_kcontrol *kcontrol,
  420. int event)
  421. {
  422. struct snd_soc_component *component =
  423. snd_soc_dapm_to_component(w->dapm);
  424. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  425. int hph_mode = wcd937x->hph_mode;
  426. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  427. w->name, event);
  428. switch (event) {
  429. case SND_SOC_DAPM_PRE_PMU:
  430. wcd937x_rx_clk_enable(component);
  431. snd_soc_component_update_bits(component,
  432. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  433. snd_soc_component_update_bits(component,
  434. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  435. snd_soc_component_update_bits(component,
  436. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  437. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  438. break;
  439. case SND_SOC_DAPM_POST_PMU:
  440. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  441. snd_soc_component_update_bits(component,
  442. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  443. 0x0F, 0x02);
  444. else if (hph_mode == CLS_H_LOHIFI)
  445. snd_soc_component_update_bits(component,
  446. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  447. 0x0F, 0x06);
  448. if (wcd937x->comp2_enable) {
  449. snd_soc_component_update_bits(component,
  450. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  451. 0x01, 0x01);
  452. snd_soc_component_update_bits(component,
  453. WCD937X_HPH_R_EN, 0x20, 0x00);
  454. if (wcd937x->comp1_enable) {
  455. snd_soc_component_update_bits(component,
  456. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  457. 0x02, 0x02);
  458. snd_soc_component_update_bits(component,
  459. WCD937X_HPH_L_EN, 0x20, 0x00);
  460. }
  461. /*
  462. * 5ms sleep is required after COMP is enabled as per
  463. * HW requirement
  464. */
  465. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  466. usleep_range(5000, 5100);
  467. clear_bit(HPH_COMP_DELAY,
  468. &wcd937x->status_mask);
  469. }
  470. } else {
  471. snd_soc_component_update_bits(component,
  472. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  473. 0x01, 0x00);
  474. snd_soc_component_update_bits(component,
  475. WCD937X_HPH_R_EN, 0x20, 0x20);
  476. }
  477. snd_soc_component_update_bits(component,
  478. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  479. break;
  480. case SND_SOC_DAPM_POST_PMD:
  481. snd_soc_component_update_bits(component,
  482. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  483. 0x0F, 0x01);
  484. break;
  485. }
  486. return 0;
  487. }
  488. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  489. struct snd_kcontrol *kcontrol,
  490. int event)
  491. {
  492. struct snd_soc_component *component =
  493. snd_soc_dapm_to_component(w->dapm);
  494. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  495. int hph_mode = wcd937x->hph_mode;
  496. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  497. w->name, event);
  498. switch (event) {
  499. case SND_SOC_DAPM_PRE_PMU:
  500. wcd937x_rx_clk_enable(component);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  503. 0x04, 0x04);
  504. snd_soc_component_update_bits(component,
  505. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  506. 0x01, 0x01);
  507. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  508. snd_soc_component_update_bits(component,
  509. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  510. 0x0F, 0x02);
  511. else if (hph_mode == CLS_H_LOHIFI)
  512. snd_soc_component_update_bits(component,
  513. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  514. 0x0F, 0x06);
  515. snd_soc_component_update_bits(component,
  516. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  517. 0x02, 0x02);
  518. usleep_range(5000, 5010);
  519. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  520. 0x04, 0x00);
  521. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  522. WCD_CLSH_EVENT_PRE_DAC,
  523. WCD_CLSH_STATE_EAR,
  524. hph_mode);
  525. break;
  526. case SND_SOC_DAPM_POST_PMD:
  527. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  528. hph_mode == CLS_H_HIFI)
  529. snd_soc_component_update_bits(component,
  530. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  531. 0x0F, 0x01);
  532. break;
  533. };
  534. return 0;
  535. }
  536. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  537. struct snd_kcontrol *kcontrol,
  538. int event)
  539. {
  540. struct snd_soc_component *component =
  541. snd_soc_dapm_to_component(w->dapm);
  542. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  543. int hph_mode = wcd937x->hph_mode;
  544. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  545. w->name, event);
  546. switch (event) {
  547. case SND_SOC_DAPM_PRE_PMU:
  548. wcd937x_rx_clk_enable(component);
  549. snd_soc_component_update_bits(component,
  550. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  551. 0x04, 0x04);
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  554. 0x04, 0x04);
  555. snd_soc_component_update_bits(component,
  556. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  557. 0x01, 0x01);
  558. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  559. WCD_CLSH_EVENT_PRE_DAC,
  560. WCD_CLSH_STATE_AUX,
  561. hph_mode);
  562. break;
  563. case SND_SOC_DAPM_POST_PMD:
  564. wcd937x_rx_clk_disable(component);
  565. snd_soc_component_update_bits(component,
  566. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  567. 0x04, 0x00);
  568. break;
  569. };
  570. return 0;
  571. }
  572. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  573. struct snd_kcontrol *kcontrol,
  574. int event)
  575. {
  576. struct snd_soc_component *component =
  577. snd_soc_dapm_to_component(w->dapm);
  578. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  579. int ret = 0;
  580. int hph_mode = wcd937x->hph_mode;
  581. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  582. w->name, event);
  583. switch (event) {
  584. case SND_SOC_DAPM_PRE_PMU:
  585. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  586. wcd937x->rx_swr_dev->dev_num,
  587. true);
  588. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  589. WCD_CLSH_EVENT_PRE_DAC,
  590. WCD_CLSH_STATE_HPHR,
  591. hph_mode);
  592. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  593. 0x10, 0x10);
  594. usleep_range(100, 110);
  595. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  596. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  597. wcd937x->rx_swr_dev->dev_num,
  598. true);
  599. snd_soc_component_update_bits(component,
  600. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  601. break;
  602. case SND_SOC_DAPM_POST_PMU:
  603. /*
  604. * 7ms sleep is required after PA is enabled as per
  605. * HW requirement. If compander is disabled, then
  606. * 20ms delay is required.
  607. */
  608. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  609. if (!wcd937x->comp2_enable)
  610. usleep_range(20000, 20100);
  611. else
  612. usleep_range(7000, 7100);
  613. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  614. }
  615. snd_soc_component_update_bits(component,
  616. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  617. 0x02, 0x02);
  618. snd_soc_component_update_bits(component,
  619. WCD937X_HPH_R_TEST, 0x01, 0x01);
  620. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  621. snd_soc_component_update_bits(component,
  622. WCD937X_ANA_RX_SUPPLIES,
  623. 0x02, 0x02);
  624. if (wcd937x->update_wcd_event)
  625. wcd937x->update_wcd_event(wcd937x->handle,
  626. WCD_BOLERO_EVT_RX_MUTE,
  627. (WCD_RX2 << 0x10));
  628. break;
  629. case SND_SOC_DAPM_PRE_PMD:
  630. snd_soc_component_update_bits(component,
  631. WCD937X_HPH_R_TEST, 0x01, 0x00);
  632. if (wcd937x->update_wcd_event)
  633. wcd937x->update_wcd_event(wcd937x->handle,
  634. WCD_BOLERO_EVT_RX_MUTE,
  635. (WCD_RX2 << 0x10 | 0x1));
  636. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  637. WCD_EVENT_PRE_HPHR_PA_OFF,
  638. &wcd937x->mbhc->wcd_mbhc);
  639. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  640. break;
  641. case SND_SOC_DAPM_POST_PMD:
  642. /*
  643. * 7ms sleep is required after PA is disabled as per
  644. * HW requirement. If compander is disabled, then
  645. * 20ms delay is required.
  646. */
  647. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  648. if (!wcd937x->comp2_enable)
  649. usleep_range(20000, 20100);
  650. else
  651. usleep_range(7000, 7100);
  652. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  653. }
  654. snd_soc_component_update_bits(component,
  655. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  656. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  657. WCD_EVENT_POST_HPHR_PA_OFF,
  658. &wcd937x->mbhc->wcd_mbhc);
  659. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  660. 0x10, 0x00);
  661. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  662. WCD_CLSH_EVENT_POST_PA,
  663. WCD_CLSH_STATE_HPHR,
  664. hph_mode);
  665. break;
  666. };
  667. return ret;
  668. }
  669. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  670. struct snd_kcontrol *kcontrol,
  671. int event)
  672. {
  673. struct snd_soc_component *component =
  674. snd_soc_dapm_to_component(w->dapm);
  675. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  676. int ret = 0;
  677. int hph_mode = wcd937x->hph_mode;
  678. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  679. w->name, event);
  680. switch (event) {
  681. case SND_SOC_DAPM_PRE_PMU:
  682. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  683. wcd937x->rx_swr_dev->dev_num,
  684. true);
  685. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  686. WCD_CLSH_EVENT_PRE_DAC,
  687. WCD_CLSH_STATE_HPHL,
  688. hph_mode);
  689. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  690. 0x20, 0x20);
  691. usleep_range(100, 110);
  692. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  693. snd_soc_component_update_bits(component,
  694. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  695. break;
  696. case SND_SOC_DAPM_POST_PMU:
  697. /*
  698. * 7ms sleep is required after PA is enabled as per
  699. * HW requirement. If compander is disabled, then
  700. * 20ms delay is required.
  701. */
  702. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  703. if (!wcd937x->comp1_enable)
  704. usleep_range(20000, 20100);
  705. else
  706. usleep_range(7000, 7100);
  707. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  708. }
  709. snd_soc_component_update_bits(component,
  710. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  711. 0x02, 0x02);
  712. snd_soc_component_update_bits(component,
  713. WCD937X_HPH_L_TEST, 0x01, 0x01);
  714. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  715. snd_soc_component_update_bits(component,
  716. WCD937X_ANA_RX_SUPPLIES,
  717. 0x02, 0x02);
  718. if (wcd937x->update_wcd_event)
  719. wcd937x->update_wcd_event(wcd937x->handle,
  720. WCD_BOLERO_EVT_RX_MUTE,
  721. (WCD_RX1 << 0x10));
  722. break;
  723. case SND_SOC_DAPM_PRE_PMD:
  724. snd_soc_component_update_bits(component,
  725. WCD937X_HPH_L_TEST, 0x01, 0x00);
  726. if (wcd937x->update_wcd_event)
  727. wcd937x->update_wcd_event(wcd937x->handle,
  728. WCD_BOLERO_EVT_RX_MUTE,
  729. (WCD_RX1 << 0x10 | 0x1));
  730. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  731. WCD_EVENT_PRE_HPHL_PA_OFF,
  732. &wcd937x->mbhc->wcd_mbhc);
  733. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  734. break;
  735. case SND_SOC_DAPM_POST_PMD:
  736. /*
  737. * 7ms sleep is required after PA is disabled as per
  738. * HW requirement. If compander is disabled, then
  739. * 20ms delay is required.
  740. */
  741. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  742. if (!wcd937x->comp1_enable)
  743. usleep_range(20000, 20100);
  744. else
  745. usleep_range(7000, 7100);
  746. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  747. }
  748. snd_soc_component_update_bits(component,
  749. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  750. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  751. WCD_EVENT_POST_HPHL_PA_OFF,
  752. &wcd937x->mbhc->wcd_mbhc);
  753. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  754. 0x20, 0x00);
  755. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  756. WCD_CLSH_EVENT_POST_PA,
  757. WCD_CLSH_STATE_HPHL,
  758. hph_mode);
  759. break;
  760. };
  761. return ret;
  762. }
  763. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  764. struct snd_kcontrol *kcontrol,
  765. int event)
  766. {
  767. struct snd_soc_component *component =
  768. snd_soc_dapm_to_component(w->dapm);
  769. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  770. int hph_mode = wcd937x->hph_mode;
  771. int ret = 0;
  772. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  773. w->name, event);
  774. switch (event) {
  775. case SND_SOC_DAPM_PRE_PMU:
  776. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  777. wcd937x->rx_swr_dev->dev_num,
  778. true);
  779. snd_soc_component_update_bits(component,
  780. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  781. break;
  782. case SND_SOC_DAPM_POST_PMU:
  783. usleep_range(1000, 1010);
  784. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  785. snd_soc_component_update_bits(component,
  786. WCD937X_ANA_RX_SUPPLIES,
  787. 0x02, 0x02);
  788. if (wcd937x->update_wcd_event)
  789. wcd937x->update_wcd_event(wcd937x->handle,
  790. WCD_BOLERO_EVT_RX_MUTE,
  791. (WCD_RX3 << 0x10));
  792. break;
  793. case SND_SOC_DAPM_PRE_PMD:
  794. if (wcd937x->update_wcd_event)
  795. wcd937x->update_wcd_event(wcd937x->handle,
  796. WCD_BOLERO_EVT_RX_MUTE,
  797. (WCD_RX3 << 0x10 | 0x1));
  798. break;
  799. case SND_SOC_DAPM_POST_PMD:
  800. /* Add delay as per hw requirement */
  801. usleep_range(2000, 2010);
  802. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  803. WCD_CLSH_EVENT_POST_PA,
  804. WCD_CLSH_STATE_AUX,
  805. hph_mode);
  806. snd_soc_component_update_bits(component,
  807. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  808. break;
  809. };
  810. return ret;
  811. }
  812. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  813. struct snd_kcontrol *kcontrol,
  814. int event)
  815. {
  816. struct snd_soc_component *component =
  817. snd_soc_dapm_to_component(w->dapm);
  818. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  819. int hph_mode = wcd937x->hph_mode;
  820. int ret = 0;
  821. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  822. w->name, event);
  823. switch (event) {
  824. case SND_SOC_DAPM_PRE_PMU:
  825. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  826. wcd937x->rx_swr_dev->dev_num,
  827. true);
  828. /*
  829. * Enable watchdog interrupt for HPHL or AUX
  830. * depending on mux value
  831. */
  832. wcd937x->ear_rx_path =
  833. snd_soc_component_read32(
  834. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  835. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  836. snd_soc_component_update_bits(component,
  837. WCD937X_DIGITAL_PDM_WD_CTL2,
  838. 0x05, 0x05);
  839. else
  840. snd_soc_component_update_bits(component,
  841. WCD937X_DIGITAL_PDM_WD_CTL0,
  842. 0x17, 0x13);
  843. if (!wcd937x->comp1_enable)
  844. snd_soc_component_update_bits(component,
  845. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  846. break;
  847. case SND_SOC_DAPM_POST_PMU:
  848. usleep_range(6000, 6010);
  849. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  850. snd_soc_component_update_bits(component,
  851. WCD937X_ANA_RX_SUPPLIES,
  852. 0x02, 0x02);
  853. if (wcd937x->update_wcd_event)
  854. wcd937x->update_wcd_event(wcd937x->handle,
  855. WCD_BOLERO_EVT_RX_MUTE,
  856. (WCD_RX1 << 0x10));
  857. break;
  858. case SND_SOC_DAPM_PRE_PMD:
  859. if (wcd937x->update_wcd_event)
  860. wcd937x->update_wcd_event(wcd937x->handle,
  861. WCD_BOLERO_EVT_RX_MUTE,
  862. (WCD_RX1 << 0x10 | 0x1));
  863. break;
  864. case SND_SOC_DAPM_POST_PMD:
  865. if (!wcd937x->comp1_enable)
  866. snd_soc_component_update_bits(component,
  867. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  868. usleep_range(7000, 7010);
  869. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  870. WCD_CLSH_EVENT_POST_PA,
  871. WCD_CLSH_STATE_EAR,
  872. hph_mode);
  873. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  874. 0x04, 0x04);
  875. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  876. snd_soc_component_update_bits(component,
  877. WCD937X_DIGITAL_PDM_WD_CTL2,
  878. 0x05, 0x00);
  879. else
  880. snd_soc_component_update_bits(component,
  881. WCD937X_DIGITAL_PDM_WD_CTL0,
  882. 0x17, 0x00);
  883. break;
  884. };
  885. return ret;
  886. }
  887. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  888. struct snd_kcontrol *kcontrol,
  889. int event)
  890. {
  891. struct snd_soc_component *component =
  892. snd_soc_dapm_to_component(w->dapm);
  893. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  894. int mode = wcd937x->hph_mode;
  895. int ret = 0;
  896. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  897. w->name, event);
  898. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  899. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  900. wcd937x_rx_connect_port(component, CLSH,
  901. SND_SOC_DAPM_EVENT_ON(event));
  902. }
  903. if (SND_SOC_DAPM_EVENT_OFF(event))
  904. ret = swr_slvdev_datapath_control(
  905. wcd937x->rx_swr_dev,
  906. wcd937x->rx_swr_dev->dev_num,
  907. false);
  908. return ret;
  909. }
  910. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  911. struct snd_kcontrol *kcontrol,
  912. int event)
  913. {
  914. struct snd_soc_component *component =
  915. snd_soc_dapm_to_component(w->dapm);
  916. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  917. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  918. w->name, event);
  919. switch (event) {
  920. case SND_SOC_DAPM_PRE_PMU:
  921. wcd937x_rx_connect_port(component, HPH_L, true);
  922. if (wcd937x->comp1_enable)
  923. wcd937x_rx_connect_port(component, COMP_L, true);
  924. break;
  925. case SND_SOC_DAPM_POST_PMD:
  926. wcd937x_rx_connect_port(component, HPH_L, false);
  927. if (wcd937x->comp1_enable)
  928. wcd937x_rx_connect_port(component, COMP_L, false);
  929. wcd937x_rx_clk_disable(component);
  930. snd_soc_component_update_bits(component,
  931. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  932. 0x01, 0x00);
  933. break;
  934. };
  935. return 0;
  936. }
  937. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  938. struct snd_kcontrol *kcontrol, int event)
  939. {
  940. struct snd_soc_component *component =
  941. snd_soc_dapm_to_component(w->dapm);
  942. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  943. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  944. w->name, event);
  945. switch (event) {
  946. case SND_SOC_DAPM_PRE_PMU:
  947. wcd937x_rx_connect_port(component, HPH_R, true);
  948. if (wcd937x->comp2_enable)
  949. wcd937x_rx_connect_port(component, COMP_R, true);
  950. break;
  951. case SND_SOC_DAPM_POST_PMD:
  952. wcd937x_rx_connect_port(component, HPH_R, false);
  953. if (wcd937x->comp2_enable)
  954. wcd937x_rx_connect_port(component, COMP_R, false);
  955. wcd937x_rx_clk_disable(component);
  956. snd_soc_component_update_bits(component,
  957. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  958. 0x02, 0x00);
  959. break;
  960. };
  961. return 0;
  962. }
  963. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  964. struct snd_kcontrol *kcontrol,
  965. int event)
  966. {
  967. struct snd_soc_component *component =
  968. snd_soc_dapm_to_component(w->dapm);
  969. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  970. w->name, event);
  971. switch (event) {
  972. case SND_SOC_DAPM_PRE_PMU:
  973. wcd937x_rx_connect_port(component, LO, true);
  974. break;
  975. case SND_SOC_DAPM_POST_PMD:
  976. wcd937x_rx_connect_port(component, LO, false);
  977. usleep_range(6000, 6010);
  978. wcd937x_rx_clk_disable(component);
  979. snd_soc_component_update_bits(component,
  980. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  981. break;
  982. }
  983. return 0;
  984. }
  985. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  986. struct snd_kcontrol *kcontrol,
  987. int event)
  988. {
  989. struct snd_soc_component *component =
  990. snd_soc_dapm_to_component(w->dapm);
  991. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  992. u16 dmic_clk_reg;
  993. s32 *dmic_clk_cnt;
  994. unsigned int dmic;
  995. char *wname;
  996. int ret = 0;
  997. wname = strpbrk(w->name, "012345");
  998. if (!wname) {
  999. dev_err(component->dev, "%s: widget not found\n", __func__);
  1000. return -EINVAL;
  1001. }
  1002. ret = kstrtouint(wname, 10, &dmic);
  1003. if (ret < 0) {
  1004. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1005. __func__);
  1006. return -EINVAL;
  1007. }
  1008. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1009. w->name, event);
  1010. switch (dmic) {
  1011. case 0:
  1012. case 1:
  1013. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1014. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1015. break;
  1016. case 2:
  1017. case 3:
  1018. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1019. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1020. break;
  1021. case 4:
  1022. case 5:
  1023. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1024. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1025. break;
  1026. default:
  1027. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1028. __func__);
  1029. return -EINVAL;
  1030. };
  1031. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1032. __func__, event, dmic, *dmic_clk_cnt);
  1033. switch (event) {
  1034. case SND_SOC_DAPM_PRE_PMU:
  1035. snd_soc_component_update_bits(component,
  1036. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1037. snd_soc_component_update_bits(component,
  1038. dmic_clk_reg, 0x07, 0x02);
  1039. snd_soc_component_update_bits(component,
  1040. dmic_clk_reg, 0x08, 0x08);
  1041. snd_soc_component_update_bits(component,
  1042. dmic_clk_reg, 0x70, 0x20);
  1043. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1044. break;
  1045. case SND_SOC_DAPM_POST_PMD:
  1046. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1047. break;
  1048. };
  1049. return 0;
  1050. }
  1051. /*
  1052. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1053. * @micb_mv: micbias in mv
  1054. *
  1055. * return register value converted
  1056. */
  1057. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1058. {
  1059. /* min micbias voltage is 1V and maximum is 2.85V */
  1060. if (micb_mv < 1000 || micb_mv > 2850) {
  1061. pr_err("%s: unsupported micbias voltage\n", __func__);
  1062. return -EINVAL;
  1063. }
  1064. return (micb_mv - 1000) / 50;
  1065. }
  1066. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1067. /*
  1068. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1069. * @component: handle to snd_soc_component *
  1070. * @req_volt: micbias voltage to be set
  1071. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1072. *
  1073. * return 0 if adjustment is success or error code in case of failure
  1074. */
  1075. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1076. int req_volt, int micb_num)
  1077. {
  1078. struct wcd937x_priv *wcd937x =
  1079. snd_soc_component_get_drvdata(component);
  1080. int cur_vout_ctl, req_vout_ctl;
  1081. int micb_reg, micb_val, micb_en;
  1082. int ret = 0;
  1083. switch (micb_num) {
  1084. case MIC_BIAS_1:
  1085. micb_reg = WCD937X_ANA_MICB1;
  1086. break;
  1087. case MIC_BIAS_2:
  1088. micb_reg = WCD937X_ANA_MICB2;
  1089. break;
  1090. case MIC_BIAS_3:
  1091. micb_reg = WCD937X_ANA_MICB3;
  1092. break;
  1093. default:
  1094. return -EINVAL;
  1095. }
  1096. mutex_lock(&wcd937x->micb_lock);
  1097. /*
  1098. * If requested micbias voltage is same as current micbias
  1099. * voltage, then just return. Otherwise, adjust voltage as
  1100. * per requested value. If micbias is already enabled, then
  1101. * to avoid slow micbias ramp-up or down enable pull-up
  1102. * momentarily, change the micbias value and then re-enable
  1103. * micbias.
  1104. */
  1105. micb_val = snd_soc_component_read32(component, micb_reg);
  1106. micb_en = (micb_val & 0xC0) >> 6;
  1107. cur_vout_ctl = micb_val & 0x3F;
  1108. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1109. if (req_vout_ctl < 0) {
  1110. ret = -EINVAL;
  1111. goto exit;
  1112. }
  1113. if (cur_vout_ctl == req_vout_ctl) {
  1114. ret = 0;
  1115. goto exit;
  1116. }
  1117. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1118. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1119. req_volt, micb_en);
  1120. if (micb_en == 0x1)
  1121. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1122. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1123. if (micb_en == 0x1) {
  1124. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1125. /*
  1126. * Add 2ms delay as per HW requirement after enabling
  1127. * micbias
  1128. */
  1129. usleep_range(2000, 2100);
  1130. }
  1131. exit:
  1132. mutex_unlock(&wcd937x->micb_lock);
  1133. return ret;
  1134. }
  1135. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1136. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1137. struct snd_kcontrol *kcontrol,
  1138. int event)
  1139. {
  1140. struct snd_soc_component *component =
  1141. snd_soc_dapm_to_component(w->dapm);
  1142. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1143. int ret = 0;
  1144. switch (event) {
  1145. case SND_SOC_DAPM_PRE_PMU:
  1146. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1147. wcd937x->tx_swr_dev->dev_num,
  1148. true);
  1149. break;
  1150. case SND_SOC_DAPM_POST_PMD:
  1151. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1152. wcd937x->tx_swr_dev->dev_num,
  1153. false);
  1154. break;
  1155. };
  1156. return ret;
  1157. }
  1158. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1159. struct snd_kcontrol *kcontrol,
  1160. int event){
  1161. struct snd_soc_component *component =
  1162. snd_soc_dapm_to_component(w->dapm);
  1163. struct wcd937x_priv *wcd937x =
  1164. snd_soc_component_get_drvdata(component);
  1165. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1166. w->name, event);
  1167. switch (event) {
  1168. case SND_SOC_DAPM_PRE_PMU:
  1169. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1170. wcd937x->ana_clk_count++;
  1171. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1172. snd_soc_component_update_bits(component,
  1173. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1174. snd_soc_component_update_bits(component,
  1175. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1176. snd_soc_component_update_bits(component,
  1177. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1178. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1179. break;
  1180. case SND_SOC_DAPM_POST_PMD:
  1181. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1182. snd_soc_component_update_bits(component,
  1183. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1184. break;
  1185. };
  1186. return 0;
  1187. }
  1188. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1189. struct snd_kcontrol *kcontrol, int event)
  1190. {
  1191. struct snd_soc_component *component =
  1192. snd_soc_dapm_to_component(w->dapm);
  1193. struct wcd937x_priv *wcd937x =
  1194. snd_soc_component_get_drvdata(component);
  1195. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1196. w->name, event);
  1197. switch (event) {
  1198. case SND_SOC_DAPM_PRE_PMU:
  1199. snd_soc_component_update_bits(component,
  1200. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1201. snd_soc_component_update_bits(component,
  1202. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1203. snd_soc_component_update_bits(component,
  1204. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1205. snd_soc_component_update_bits(component,
  1206. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1207. snd_soc_component_update_bits(component,
  1208. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1209. snd_soc_component_update_bits(component,
  1210. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1211. snd_soc_component_update_bits(component,
  1212. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1213. break;
  1214. case SND_SOC_DAPM_POST_PMD:
  1215. snd_soc_component_update_bits(component,
  1216. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1217. snd_soc_component_update_bits(component,
  1218. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1219. snd_soc_component_update_bits(component,
  1220. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1221. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1222. wcd937x->ana_clk_count--;
  1223. if (wcd937x->ana_clk_count <= 0) {
  1224. snd_soc_component_update_bits(component,
  1225. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1226. wcd937x->ana_clk_count = 0;
  1227. }
  1228. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1229. snd_soc_component_update_bits(component,
  1230. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1231. break;
  1232. };
  1233. return 0;
  1234. }
  1235. int wcd937x_micbias_control(struct snd_soc_component *component,
  1236. int micb_num, int req, bool is_dapm)
  1237. {
  1238. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1239. int micb_index = micb_num - 1;
  1240. u16 micb_reg;
  1241. int pre_off_event = 0, post_off_event = 0;
  1242. int post_on_event = 0, post_dapm_off = 0;
  1243. int post_dapm_on = 0;
  1244. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1245. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1246. __func__, micb_index);
  1247. return -EINVAL;
  1248. }
  1249. switch (micb_num) {
  1250. case MIC_BIAS_1:
  1251. micb_reg = WCD937X_ANA_MICB1;
  1252. break;
  1253. case MIC_BIAS_2:
  1254. micb_reg = WCD937X_ANA_MICB2;
  1255. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1256. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1257. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1258. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1259. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1260. break;
  1261. case MIC_BIAS_3:
  1262. micb_reg = WCD937X_ANA_MICB3;
  1263. break;
  1264. default:
  1265. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1266. __func__, micb_num);
  1267. return -EINVAL;
  1268. };
  1269. mutex_lock(&wcd937x->micb_lock);
  1270. switch (req) {
  1271. case MICB_PULLUP_ENABLE:
  1272. wcd937x->pullup_ref[micb_index]++;
  1273. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1274. (wcd937x->micb_ref[micb_index] == 0))
  1275. snd_soc_component_update_bits(component, micb_reg,
  1276. 0xC0, 0x80);
  1277. break;
  1278. case MICB_PULLUP_DISABLE:
  1279. if (wcd937x->pullup_ref[micb_index] > 0)
  1280. wcd937x->pullup_ref[micb_index]--;
  1281. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1282. (wcd937x->micb_ref[micb_index] == 0))
  1283. snd_soc_component_update_bits(component, micb_reg,
  1284. 0xC0, 0x00);
  1285. break;
  1286. case MICB_ENABLE:
  1287. wcd937x->micb_ref[micb_index]++;
  1288. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1289. wcd937x->ana_clk_count++;
  1290. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1291. if (wcd937x->micb_ref[micb_index] == 1) {
  1292. snd_soc_component_update_bits(component,
  1293. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1294. snd_soc_component_update_bits(component,
  1295. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1296. snd_soc_component_update_bits(component,
  1297. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1298. snd_soc_component_update_bits(component,
  1299. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1300. snd_soc_component_update_bits(component,
  1301. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1302. snd_soc_component_update_bits(component,
  1303. micb_reg, 0xC0, 0x40);
  1304. if (post_on_event)
  1305. blocking_notifier_call_chain(
  1306. &wcd937x->mbhc->notifier, post_on_event,
  1307. &wcd937x->mbhc->wcd_mbhc);
  1308. }
  1309. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1310. blocking_notifier_call_chain(
  1311. &wcd937x->mbhc->notifier, post_dapm_on,
  1312. &wcd937x->mbhc->wcd_mbhc);
  1313. break;
  1314. case MICB_DISABLE:
  1315. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1316. wcd937x->ana_clk_count--;
  1317. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1318. if (wcd937x->micb_ref[micb_index] > 0)
  1319. wcd937x->micb_ref[micb_index]--;
  1320. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1321. (wcd937x->pullup_ref[micb_index] > 0))
  1322. snd_soc_component_update_bits(component, micb_reg,
  1323. 0xC0, 0x80);
  1324. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1325. (wcd937x->pullup_ref[micb_index] == 0)) {
  1326. if (pre_off_event && wcd937x->mbhc)
  1327. blocking_notifier_call_chain(
  1328. &wcd937x->mbhc->notifier, pre_off_event,
  1329. &wcd937x->mbhc->wcd_mbhc);
  1330. snd_soc_component_update_bits(component, micb_reg,
  1331. 0xC0, 0x00);
  1332. if (post_off_event && wcd937x->mbhc)
  1333. blocking_notifier_call_chain(
  1334. &wcd937x->mbhc->notifier,
  1335. post_off_event,
  1336. &wcd937x->mbhc->wcd_mbhc);
  1337. }
  1338. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1339. if (wcd937x->ana_clk_count <= 0) {
  1340. snd_soc_component_update_bits(component,
  1341. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1342. 0x10, 0x00);
  1343. wcd937x->ana_clk_count = 0;
  1344. }
  1345. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1346. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1347. blocking_notifier_call_chain(
  1348. &wcd937x->mbhc->notifier, post_dapm_off,
  1349. &wcd937x->mbhc->wcd_mbhc);
  1350. break;
  1351. };
  1352. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1353. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1354. wcd937x->pullup_ref[micb_index]);
  1355. mutex_unlock(&wcd937x->micb_lock);
  1356. return 0;
  1357. }
  1358. EXPORT_SYMBOL(wcd937x_micbias_control);
  1359. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1360. {
  1361. int ret = 0;
  1362. uint8_t devnum = 0;
  1363. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1364. if (ret) {
  1365. dev_err(&swr_dev->dev,
  1366. "%s get devnum %d for dev addr %lx failed\n",
  1367. __func__, devnum, swr_dev->addr);
  1368. return ret;
  1369. }
  1370. swr_dev->dev_num = devnum;
  1371. return 0;
  1372. }
  1373. static int wcd937x_event_notify(struct notifier_block *block,
  1374. unsigned long val,
  1375. void *data)
  1376. {
  1377. u16 event = (val & 0xffff);
  1378. u16 amic = (val >> 0x10);
  1379. u16 mask = 0x40, reg = 0x0;
  1380. int ret = 0;
  1381. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1382. struct snd_soc_component *component = wcd937x->component;
  1383. struct wcd_mbhc *mbhc;
  1384. switch (event) {
  1385. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1386. if (amic == 0x1 || amic == 0x2)
  1387. reg = WCD937X_ANA_TX_CH2;
  1388. else if (amic == 0x3)
  1389. reg = WCD937X_ANA_TX_CH3_HPF;
  1390. else
  1391. return 0;
  1392. if (amic == 0x2)
  1393. mask = 0x20;
  1394. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1395. break;
  1396. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1397. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1398. 0xC0, 0x00);
  1399. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1400. 0x80, 0x00);
  1401. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1402. 0x80, 0x00);
  1403. break;
  1404. case BOLERO_WCD_EVT_SSR_DOWN:
  1405. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1406. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1407. wcd937x_reset_low(wcd937x->dev);
  1408. break;
  1409. case BOLERO_WCD_EVT_SSR_UP:
  1410. wcd937x_reset(wcd937x->dev);
  1411. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1412. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1413. regcache_mark_dirty(wcd937x->regmap);
  1414. regcache_sync(wcd937x->regmap);
  1415. /* Enable surge protection */
  1416. snd_soc_component_update_bits(component,
  1417. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1418. 0xFF, 0xD9);
  1419. /* Initialize MBHC module */
  1420. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1421. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1422. if (ret) {
  1423. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1424. __func__);
  1425. } else {
  1426. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1427. }
  1428. break;
  1429. default:
  1430. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1431. event);
  1432. break;
  1433. }
  1434. return 0;
  1435. }
  1436. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1437. int event)
  1438. {
  1439. struct snd_soc_component *component =
  1440. snd_soc_dapm_to_component(w->dapm);
  1441. int micb_num;
  1442. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1443. __func__, w->name, event);
  1444. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1445. micb_num = MIC_BIAS_1;
  1446. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1447. micb_num = MIC_BIAS_2;
  1448. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1449. micb_num = MIC_BIAS_3;
  1450. else
  1451. return -EINVAL;
  1452. switch (event) {
  1453. case SND_SOC_DAPM_PRE_PMU:
  1454. wcd937x_micbias_control(component, micb_num,
  1455. MICB_ENABLE, true);
  1456. break;
  1457. case SND_SOC_DAPM_POST_PMU:
  1458. usleep_range(1000, 1100);
  1459. break;
  1460. case SND_SOC_DAPM_POST_PMD:
  1461. wcd937x_micbias_control(component, micb_num,
  1462. MICB_DISABLE, true);
  1463. break;
  1464. };
  1465. return 0;
  1466. }
  1467. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1468. struct snd_kcontrol *kcontrol,
  1469. int event)
  1470. {
  1471. return __wcd937x_codec_enable_micbias(w, event);
  1472. }
  1473. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1474. struct snd_ctl_elem_value *ucontrol)
  1475. {
  1476. struct snd_soc_component *component =
  1477. snd_soc_kcontrol_component(kcontrol);
  1478. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1479. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1480. return 0;
  1481. }
  1482. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1483. struct snd_ctl_elem_value *ucontrol)
  1484. {
  1485. struct snd_soc_component *component =
  1486. snd_soc_kcontrol_component(kcontrol);
  1487. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1488. u32 mode_val;
  1489. mode_val = ucontrol->value.enumerated.item[0];
  1490. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1491. if (mode_val == 0) {
  1492. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1493. __func__);
  1494. mode_val = 3; /* enum will be updated later */
  1495. }
  1496. wcd937x->hph_mode = mode_val;
  1497. return 0;
  1498. }
  1499. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1500. struct snd_ctl_elem_value *ucontrol)
  1501. {
  1502. u8 ear_pa_gain = 0;
  1503. struct snd_soc_component *component =
  1504. snd_soc_kcontrol_component(kcontrol);
  1505. ear_pa_gain = snd_soc_component_read32(component,
  1506. WCD937X_ANA_EAR_COMPANDER_CTL);
  1507. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1508. ucontrol->value.integer.value[0] = ear_pa_gain;
  1509. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1510. ear_pa_gain);
  1511. return 0;
  1512. }
  1513. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1514. struct snd_ctl_elem_value *ucontrol)
  1515. {
  1516. u8 ear_pa_gain = 0;
  1517. struct snd_soc_component *component =
  1518. snd_soc_kcontrol_component(kcontrol);
  1519. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1520. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1521. __func__, ucontrol->value.integer.value[0]);
  1522. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1523. if (!wcd937x->comp1_enable) {
  1524. snd_soc_component_update_bits(component,
  1525. WCD937X_ANA_EAR_COMPANDER_CTL,
  1526. 0x7C, ear_pa_gain);
  1527. }
  1528. return 0;
  1529. }
  1530. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. struct snd_soc_component *component =
  1534. snd_soc_kcontrol_component(kcontrol);
  1535. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1536. bool hphr;
  1537. struct soc_multi_mixer_control *mc;
  1538. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1539. hphr = mc->shift;
  1540. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1541. wcd937x->comp1_enable;
  1542. return 0;
  1543. }
  1544. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. struct snd_soc_component *component =
  1548. snd_soc_kcontrol_component(kcontrol);
  1549. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1550. int value = ucontrol->value.integer.value[0];
  1551. bool hphr;
  1552. struct soc_multi_mixer_control *mc;
  1553. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1554. hphr = mc->shift;
  1555. if (hphr)
  1556. wcd937x->comp2_enable = value;
  1557. else
  1558. wcd937x->comp1_enable = value;
  1559. return 0;
  1560. }
  1561. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1562. struct snd_kcontrol *kcontrol,
  1563. int event)
  1564. {
  1565. struct snd_soc_component *component =
  1566. snd_soc_dapm_to_component(w->dapm);
  1567. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1568. struct wcd937x_pdata *pdata = NULL;
  1569. int ret = 0;
  1570. pdata = dev_get_platdata(wcd937x->dev);
  1571. if (!pdata) {
  1572. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1573. return -EINVAL;
  1574. }
  1575. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1576. w->name, event);
  1577. switch (event) {
  1578. case SND_SOC_DAPM_PRE_PMU:
  1579. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1580. dev_dbg(component->dev,
  1581. "%s: buck already in enabled state\n",
  1582. __func__);
  1583. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1584. return 0;
  1585. }
  1586. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1587. wcd937x->supplies,
  1588. pdata->regulator,
  1589. pdata->num_supplies,
  1590. "cdc-vdd-buck");
  1591. if (ret == -EINVAL) {
  1592. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1593. __func__);
  1594. return ret;
  1595. }
  1596. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1597. /*
  1598. * 200us sleep is required after LDO15 is enabled as per
  1599. * HW requirement
  1600. */
  1601. usleep_range(200, 250);
  1602. break;
  1603. case SND_SOC_DAPM_POST_PMD:
  1604. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1605. break;
  1606. }
  1607. return 0;
  1608. }
  1609. static const char * const rx_hph_mode_mux_text[] = {
  1610. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1611. "CLS_H_ULP", "CLS_AB_HIFI",
  1612. };
  1613. static const char * const wcd937x_ear_pa_gain_text[] = {
  1614. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1615. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1616. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1617. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1618. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1619. };
  1620. static const struct soc_enum rx_hph_mode_mux_enum =
  1621. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1622. rx_hph_mode_mux_text);
  1623. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1624. wcd937x_ear_pa_gain_text);
  1625. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1626. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1627. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1628. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1629. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1630. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1631. wcd937x_get_compander, wcd937x_set_compander),
  1632. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1633. wcd937x_get_compander, wcd937x_set_compander),
  1634. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1635. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1636. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1637. analog_gain),
  1638. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1639. analog_gain),
  1640. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1641. analog_gain),
  1642. };
  1643. static const struct snd_kcontrol_new adc1_switch[] = {
  1644. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1645. };
  1646. static const struct snd_kcontrol_new adc2_switch[] = {
  1647. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1648. };
  1649. static const struct snd_kcontrol_new adc3_switch[] = {
  1650. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1651. };
  1652. static const struct snd_kcontrol_new dmic1_switch[] = {
  1653. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1654. };
  1655. static const struct snd_kcontrol_new dmic2_switch[] = {
  1656. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1657. };
  1658. static const struct snd_kcontrol_new dmic3_switch[] = {
  1659. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1660. };
  1661. static const struct snd_kcontrol_new dmic4_switch[] = {
  1662. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1663. };
  1664. static const struct snd_kcontrol_new dmic5_switch[] = {
  1665. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1666. };
  1667. static const struct snd_kcontrol_new dmic6_switch[] = {
  1668. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1669. };
  1670. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1671. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1672. };
  1673. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1674. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1675. };
  1676. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1677. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1678. };
  1679. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1680. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1681. };
  1682. static const char * const adc2_mux_text[] = {
  1683. "INP2", "INP3"
  1684. };
  1685. static const char * const rdac3_mux_text[] = {
  1686. "RX1", "RX3"
  1687. };
  1688. static const struct soc_enum adc2_enum =
  1689. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1690. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1691. static const struct soc_enum rdac3_enum =
  1692. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1693. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1694. static const struct snd_kcontrol_new tx_adc2_mux =
  1695. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1696. static const struct snd_kcontrol_new rx_rdac3_mux =
  1697. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1698. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1699. /*input widgets*/
  1700. SND_SOC_DAPM_INPUT("AMIC1"),
  1701. SND_SOC_DAPM_INPUT("AMIC2"),
  1702. SND_SOC_DAPM_INPUT("AMIC3"),
  1703. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1704. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1705. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1706. /*tx widgets*/
  1707. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1708. wcd937x_codec_enable_adc,
  1709. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1710. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1711. wcd937x_codec_enable_adc,
  1712. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1713. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1714. NULL, 0, wcd937x_enable_req,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1716. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1717. NULL, 0, wcd937x_enable_req,
  1718. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1719. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1720. &tx_adc2_mux),
  1721. /*tx mixers*/
  1722. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1723. adc1_switch, ARRAY_SIZE(adc1_switch),
  1724. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1725. SND_SOC_DAPM_POST_PMD),
  1726. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1727. adc2_switch, ARRAY_SIZE(adc2_switch),
  1728. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1729. SND_SOC_DAPM_POST_PMD),
  1730. /* micbias widgets*/
  1731. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1732. wcd937x_codec_enable_micbias,
  1733. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1734. SND_SOC_DAPM_POST_PMD),
  1735. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1736. wcd937x_codec_enable_micbias,
  1737. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1738. SND_SOC_DAPM_POST_PMD),
  1739. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1740. wcd937x_codec_enable_micbias,
  1741. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1742. SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1744. wcd937x_codec_enable_vdd_buck,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1747. wcd937x_enable_clsh,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1749. /*rx widgets*/
  1750. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1751. wcd937x_codec_enable_ear_pa,
  1752. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1753. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1754. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1755. wcd937x_codec_enable_aux_pa,
  1756. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1757. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1758. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1759. wcd937x_codec_enable_hphl_pa,
  1760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1761. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1762. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1763. wcd937x_codec_enable_hphr_pa,
  1764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1765. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1766. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1767. wcd937x_codec_hphl_dac_event,
  1768. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1769. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1770. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1771. wcd937x_codec_hphr_dac_event,
  1772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1773. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1774. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1775. wcd937x_codec_ear_dac_event,
  1776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1777. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1778. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1779. wcd937x_codec_aux_dac_event,
  1780. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1781. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1782. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1783. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1784. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1785. SND_SOC_DAPM_POST_PMD),
  1786. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1787. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1788. SND_SOC_DAPM_POST_PMD),
  1789. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1790. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1791. SND_SOC_DAPM_POST_PMD),
  1792. /* rx mixer widgets*/
  1793. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1794. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1795. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1796. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1797. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1798. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1799. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1800. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1801. /*output widgets tx*/
  1802. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1803. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1804. /*output widgets rx*/
  1805. SND_SOC_DAPM_OUTPUT("EAR"),
  1806. SND_SOC_DAPM_OUTPUT("AUX"),
  1807. SND_SOC_DAPM_OUTPUT("HPHL"),
  1808. SND_SOC_DAPM_OUTPUT("HPHR"),
  1809. };
  1810. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1811. /*input widgets*/
  1812. SND_SOC_DAPM_INPUT("AMIC4"),
  1813. /*tx widgets*/
  1814. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1815. wcd937x_codec_enable_adc,
  1816. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1817. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1818. NULL, 0, wcd937x_enable_req,
  1819. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1820. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1821. wcd937x_codec_enable_dmic,
  1822. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1823. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1824. wcd937x_codec_enable_dmic,
  1825. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1826. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1827. wcd937x_codec_enable_dmic,
  1828. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1829. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1830. wcd937x_codec_enable_dmic,
  1831. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1832. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1833. wcd937x_codec_enable_dmic,
  1834. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1835. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1836. wcd937x_codec_enable_dmic,
  1837. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1838. /*tx mixer widgets*/
  1839. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1840. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1841. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1842. SND_SOC_DAPM_POST_PMD),
  1843. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1844. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1845. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1846. SND_SOC_DAPM_POST_PMD),
  1847. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1848. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1849. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1850. SND_SOC_DAPM_POST_PMD),
  1851. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1852. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1853. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1854. SND_SOC_DAPM_POST_PMD),
  1855. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1856. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1857. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1858. SND_SOC_DAPM_POST_PMD),
  1859. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1860. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1861. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1862. SND_SOC_DAPM_POST_PMD),
  1863. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1864. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1865. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1866. /*output widgets*/
  1867. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1868. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1869. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1870. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1871. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1872. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1873. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1874. };
  1875. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1876. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1877. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1878. {"ADC1 REQ", NULL, "ADC1"},
  1879. {"ADC1", NULL, "AMIC1"},
  1880. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1881. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1882. {"ADC2 REQ", NULL, "ADC2"},
  1883. {"ADC2", NULL, "ADC2 MUX"},
  1884. {"ADC2 MUX", "INP3", "AMIC3"},
  1885. {"ADC2 MUX", "INP2", "AMIC2"},
  1886. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1887. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1888. {"RX1", NULL, "IN1_HPHL"},
  1889. {"RDAC1", NULL, "RX1"},
  1890. {"HPHL_RDAC", "Switch", "RDAC1"},
  1891. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1892. {"HPHL", NULL, "HPHL PGA"},
  1893. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1894. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1895. {"RX2", NULL, "IN2_HPHR"},
  1896. {"RDAC2", NULL, "RX2"},
  1897. {"HPHR_RDAC", "Switch", "RDAC2"},
  1898. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1899. {"HPHR", NULL, "HPHR PGA"},
  1900. {"IN3_AUX", NULL, "VDD_BUCK"},
  1901. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1902. {"RX3", NULL, "IN3_AUX"},
  1903. {"RDAC4", NULL, "RX3"},
  1904. {"AUX_RDAC", "Switch", "RDAC4"},
  1905. {"AUX PGA", NULL, "AUX_RDAC"},
  1906. {"AUX", NULL, "AUX PGA"},
  1907. {"RDAC3_MUX", "RX3", "RX3"},
  1908. {"RDAC3_MUX", "RX1", "RX1"},
  1909. {"RDAC3", NULL, "RDAC3_MUX"},
  1910. {"EAR_RDAC", "Switch", "RDAC3"},
  1911. {"EAR PGA", NULL, "EAR_RDAC"},
  1912. {"EAR", NULL, "EAR PGA"},
  1913. };
  1914. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1915. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1916. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1917. {"ADC3 REQ", NULL, "ADC3"},
  1918. {"ADC3", NULL, "AMIC4"},
  1919. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1920. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1921. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1922. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1923. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1924. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1925. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1926. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1927. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1928. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1929. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1930. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1931. };
  1932. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1933. void *file_private_data,
  1934. struct file *file,
  1935. char __user *buf, size_t count,
  1936. loff_t pos)
  1937. {
  1938. struct wcd937x_priv *priv;
  1939. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1940. int len = 0;
  1941. priv = (struct wcd937x_priv *) entry->private_data;
  1942. if (!priv) {
  1943. pr_err("%s: wcd937x priv is null\n", __func__);
  1944. return -EINVAL;
  1945. }
  1946. switch (priv->version) {
  1947. case WCD937X_VERSION_1_0:
  1948. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1949. break;
  1950. default:
  1951. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1952. }
  1953. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1954. }
  1955. static struct snd_info_entry_ops wcd937x_info_ops = {
  1956. .read = wcd937x_version_read,
  1957. };
  1958. /*
  1959. * wcd937x_info_create_codec_entry - creates wcd937x module
  1960. * @codec_root: The parent directory
  1961. * @component: component instance
  1962. *
  1963. * Creates wcd937x module and version entry under the given
  1964. * parent directory.
  1965. *
  1966. * Return: 0 on success or negative error code on failure.
  1967. */
  1968. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1969. struct snd_soc_component *component)
  1970. {
  1971. struct snd_info_entry *version_entry;
  1972. struct wcd937x_priv *priv;
  1973. struct snd_soc_card *card;
  1974. if (!codec_root || !component)
  1975. return -EINVAL;
  1976. priv = snd_soc_component_get_drvdata(component);
  1977. if (priv->entry) {
  1978. dev_dbg(priv->dev,
  1979. "%s:wcd937x module already created\n", __func__);
  1980. return 0;
  1981. }
  1982. card = component->card;
  1983. priv->entry = snd_info_create_subdir(codec_root->module,
  1984. "wcd937x", codec_root);
  1985. if (!priv->entry) {
  1986. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  1987. __func__);
  1988. return -ENOMEM;
  1989. }
  1990. version_entry = snd_info_create_card_entry(card->snd_card,
  1991. "version",
  1992. priv->entry);
  1993. if (!version_entry) {
  1994. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  1995. __func__);
  1996. return -ENOMEM;
  1997. }
  1998. version_entry->private_data = priv;
  1999. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2000. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2001. version_entry->c.ops = &wcd937x_info_ops;
  2002. if (snd_info_register(version_entry) < 0) {
  2003. snd_info_free_entry(version_entry);
  2004. return -ENOMEM;
  2005. }
  2006. priv->version_entry = version_entry;
  2007. return 0;
  2008. }
  2009. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2010. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2011. struct wcd937x_pdata *pdata)
  2012. {
  2013. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2014. int rc = 0;
  2015. if (!pdata) {
  2016. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2017. return -ENODEV;
  2018. }
  2019. /* set micbias voltage */
  2020. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2021. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2022. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2023. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2024. rc = -EINVAL;
  2025. goto done;
  2026. }
  2027. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2028. vout_ctl_1);
  2029. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2030. vout_ctl_2);
  2031. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2032. vout_ctl_3);
  2033. done:
  2034. return rc;
  2035. }
  2036. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2037. {
  2038. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2039. struct snd_soc_dapm_context *dapm =
  2040. snd_soc_component_get_dapm(component);
  2041. int variant;
  2042. int ret = -EINVAL;
  2043. dev_info(component->dev, "%s()\n", __func__);
  2044. wcd937x = snd_soc_component_get_drvdata(component);
  2045. if (!wcd937x)
  2046. return -EINVAL;
  2047. wcd937x->component = component;
  2048. variant = (snd_soc_component_read32(
  2049. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2050. wcd937x->variant = variant;
  2051. wcd937x->fw_data = devm_kzalloc(component->dev,
  2052. sizeof(*(wcd937x->fw_data)),
  2053. GFP_KERNEL);
  2054. if (!wcd937x->fw_data) {
  2055. dev_err(component->dev, "Failed to allocate fw_data\n");
  2056. ret = -ENOMEM;
  2057. goto err;
  2058. }
  2059. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2060. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2061. WCD9XXX_CODEC_HWDEP_NODE, component);
  2062. if (ret < 0) {
  2063. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2064. goto err_hwdep;
  2065. }
  2066. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2067. if (ret) {
  2068. pr_err("%s: mbhc initialization failed\n", __func__);
  2069. goto err_hwdep;
  2070. }
  2071. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2072. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2073. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2074. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2075. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2076. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2077. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2078. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2079. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2080. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2081. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2082. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2083. snd_soc_dapm_sync(dapm);
  2084. wcd_cls_h_init(&wcd937x->clsh_info);
  2085. wcd937x_init_reg(component);
  2086. if (wcd937x->variant == WCD9375_VARIANT) {
  2087. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2088. ARRAY_SIZE(wcd9375_dapm_widgets));
  2089. if (ret < 0) {
  2090. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2091. __func__);
  2092. goto err_hwdep;
  2093. }
  2094. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2095. ARRAY_SIZE(wcd9375_audio_map));
  2096. if (ret < 0) {
  2097. dev_err(component->dev, "%s: Failed to add routes\n",
  2098. __func__);
  2099. goto err_hwdep;
  2100. }
  2101. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2102. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2103. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2104. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2105. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2106. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2107. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2108. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2109. snd_soc_dapm_sync(dapm);
  2110. }
  2111. wcd937x->version = WCD937X_VERSION_1_0;
  2112. /* Register event notifier */
  2113. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2114. if (wcd937x->register_notifier) {
  2115. ret = wcd937x->register_notifier(wcd937x->handle,
  2116. &wcd937x->nblock,
  2117. true);
  2118. if (ret) {
  2119. dev_err(component->dev,
  2120. "%s: Failed to register notifier %d\n",
  2121. __func__, ret);
  2122. return ret;
  2123. }
  2124. }
  2125. return ret;
  2126. err_hwdep:
  2127. wcd937x->fw_data = NULL;
  2128. err:
  2129. return ret;
  2130. }
  2131. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2132. {
  2133. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2134. if (!wcd937x)
  2135. return;
  2136. if (wcd937x->register_notifier)
  2137. wcd937x->register_notifier(wcd937x->handle,
  2138. &wcd937x->nblock,
  2139. false);
  2140. return;
  2141. }
  2142. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2143. .name = DRV_NAME,
  2144. .probe = wcd937x_soc_codec_probe,
  2145. .remove = wcd937x_soc_codec_remove,
  2146. .controls = wcd937x_snd_controls,
  2147. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2148. .dapm_widgets = wcd937x_dapm_widgets,
  2149. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2150. .dapm_routes = wcd937x_audio_map,
  2151. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2152. };
  2153. #ifdef CONFIG_PM_SLEEP
  2154. static int wcd937x_suspend(struct device *dev)
  2155. {
  2156. struct wcd937x_priv *wcd937x = NULL;
  2157. int ret = 0;
  2158. struct wcd937x_pdata *pdata = NULL;
  2159. if (!dev)
  2160. return -ENODEV;
  2161. wcd937x = dev_get_drvdata(dev);
  2162. if (!wcd937x)
  2163. return -EINVAL;
  2164. pdata = dev_get_platdata(wcd937x->dev);
  2165. if (!pdata) {
  2166. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2167. return -EINVAL;
  2168. }
  2169. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2170. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2171. wcd937x->supplies,
  2172. pdata->regulator,
  2173. pdata->num_supplies,
  2174. "cdc-vdd-buck");
  2175. if (ret == -EINVAL) {
  2176. dev_err(dev, "%s: vdd buck is not disabled\n",
  2177. __func__);
  2178. return 0;
  2179. }
  2180. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2181. }
  2182. return 0;
  2183. }
  2184. static int wcd937x_resume(struct device *dev)
  2185. {
  2186. return 0;
  2187. }
  2188. #endif
  2189. static int wcd937x_reset(struct device *dev)
  2190. {
  2191. struct wcd937x_priv *wcd937x = NULL;
  2192. int rc = 0;
  2193. int value = 0;
  2194. if (!dev)
  2195. return -ENODEV;
  2196. wcd937x = dev_get_drvdata(dev);
  2197. if (!wcd937x)
  2198. return -EINVAL;
  2199. if (!wcd937x->rst_np) {
  2200. dev_err(dev, "%s: reset gpio device node not specified\n",
  2201. __func__);
  2202. return -EINVAL;
  2203. }
  2204. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2205. if (value > 0)
  2206. return 0;
  2207. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2208. if (rc) {
  2209. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2210. __func__);
  2211. return rc;
  2212. }
  2213. /* 20ms sleep required after pulling the reset gpio to LOW */
  2214. usleep_range(20, 30);
  2215. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2216. if (rc) {
  2217. dev_err(dev, "%s: wcd active state request fail!\n",
  2218. __func__);
  2219. return rc;
  2220. }
  2221. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2222. usleep_range(20, 30);
  2223. return rc;
  2224. }
  2225. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2226. u32 *val)
  2227. {
  2228. int rc = 0;
  2229. rc = of_property_read_u32(dev->of_node, name, val);
  2230. if (rc)
  2231. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2232. __func__, name, dev->of_node->full_name);
  2233. return rc;
  2234. }
  2235. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2236. struct wcd937x_micbias_setting *mb)
  2237. {
  2238. u32 prop_val = 0;
  2239. int rc = 0;
  2240. /* MB1 */
  2241. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2242. NULL)) {
  2243. rc = wcd937x_read_of_property_u32(dev,
  2244. "qcom,cdc-micbias1-mv",
  2245. &prop_val);
  2246. if (!rc)
  2247. mb->micb1_mv = prop_val;
  2248. } else {
  2249. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2250. __func__);
  2251. }
  2252. /* MB2 */
  2253. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2254. NULL)) {
  2255. rc = wcd937x_read_of_property_u32(dev,
  2256. "qcom,cdc-micbias2-mv",
  2257. &prop_val);
  2258. if (!rc)
  2259. mb->micb2_mv = prop_val;
  2260. } else {
  2261. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2262. __func__);
  2263. }
  2264. /* MB3 */
  2265. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2266. NULL)) {
  2267. rc = wcd937x_read_of_property_u32(dev,
  2268. "qcom,cdc-micbias3-mv",
  2269. &prop_val);
  2270. if (!rc)
  2271. mb->micb3_mv = prop_val;
  2272. } else {
  2273. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2274. __func__);
  2275. }
  2276. }
  2277. static int wcd937x_reset_low(struct device *dev)
  2278. {
  2279. struct wcd937x_priv *wcd937x = NULL;
  2280. int rc = 0;
  2281. if (!dev)
  2282. return -ENODEV;
  2283. wcd937x = dev_get_drvdata(dev);
  2284. if (!wcd937x)
  2285. return -EINVAL;
  2286. if (!wcd937x->rst_np) {
  2287. dev_err(dev, "%s: reset gpio device node not specified\n",
  2288. __func__);
  2289. return -EINVAL;
  2290. }
  2291. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2292. if (rc) {
  2293. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2294. __func__);
  2295. return rc;
  2296. }
  2297. /* 20ms sleep required after pulling the reset gpio to LOW */
  2298. usleep_range(20, 30);
  2299. return rc;
  2300. }
  2301. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2302. {
  2303. struct wcd937x_pdata *pdata = NULL;
  2304. pdata = devm_kzalloc(dev, sizeof(struct wcd937x_pdata),
  2305. GFP_KERNEL);
  2306. if (!pdata)
  2307. return NULL;
  2308. pdata->rst_np = of_parse_phandle(dev->of_node,
  2309. "qcom,wcd-rst-gpio-node", 0);
  2310. if (!pdata->rst_np) {
  2311. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2312. __func__, "qcom,wcd-rst-gpio-node",
  2313. dev->of_node->full_name);
  2314. return NULL;
  2315. }
  2316. /* Parse power supplies */
  2317. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2318. &pdata->num_supplies);
  2319. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2320. dev_err(dev, "%s: no power supplies defined for codec\n",
  2321. __func__);
  2322. return NULL;
  2323. }
  2324. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2325. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2326. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2327. return pdata;
  2328. }
  2329. static int wcd937x_wakeup(void *handle, bool enable)
  2330. {
  2331. struct wcd937x_priv *priv;
  2332. if (!handle) {
  2333. pr_err("%s: NULL handle\n", __func__);
  2334. return -EINVAL;
  2335. }
  2336. priv = (struct wcd937x_priv *)handle;
  2337. if (!priv->tx_swr_dev) {
  2338. pr_err("%s: tx swr dev is NULL\n", __func__);
  2339. return -EINVAL;
  2340. }
  2341. if (enable)
  2342. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2343. else
  2344. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2345. }
  2346. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2347. {
  2348. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2349. __func__, irq);
  2350. return IRQ_HANDLED;
  2351. }
  2352. static int wcd937x_bind(struct device *dev)
  2353. {
  2354. int ret = 0, i = 0;
  2355. struct wcd937x_priv *wcd937x = NULL;
  2356. struct wcd937x_pdata *pdata = NULL;
  2357. struct wcd_ctrl_platform_data *plat_data = NULL;
  2358. wcd937x = devm_kzalloc(dev, sizeof(struct wcd937x_priv), GFP_KERNEL);
  2359. if (!wcd937x)
  2360. return -ENOMEM;
  2361. dev_set_drvdata(dev, wcd937x);
  2362. pdata = wcd937x_populate_dt_data(dev);
  2363. if (!pdata) {
  2364. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2365. return -EINVAL;
  2366. }
  2367. wcd937x->dev = dev;
  2368. wcd937x->dev->platform_data = pdata;
  2369. wcd937x->rst_np = pdata->rst_np;
  2370. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2371. pdata->regulator, pdata->num_supplies);
  2372. if (!wcd937x->supplies) {
  2373. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2374. __func__);
  2375. return ret;
  2376. }
  2377. plat_data = dev_get_platdata(dev->parent);
  2378. if (!plat_data) {
  2379. dev_err(dev, "%s: platform data from parent is NULL\n",
  2380. __func__);
  2381. return -EINVAL;
  2382. }
  2383. wcd937x->handle = (void *)plat_data->handle;
  2384. if (!wcd937x->handle) {
  2385. dev_err(dev, "%s: handle is NULL\n", __func__);
  2386. return -EINVAL;
  2387. }
  2388. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2389. if (!wcd937x->update_wcd_event) {
  2390. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2391. __func__);
  2392. return -EINVAL;
  2393. }
  2394. wcd937x->register_notifier = plat_data->register_notifier;
  2395. if (!wcd937x->register_notifier) {
  2396. dev_err(dev, "%s: register_notifier api is null!\n",
  2397. __func__);
  2398. return -EINVAL;
  2399. }
  2400. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2401. pdata->regulator,
  2402. pdata->num_supplies);
  2403. if (ret) {
  2404. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2405. __func__);
  2406. return ret;
  2407. }
  2408. wcd937x_reset(dev);
  2409. /*
  2410. * Add 5msec delay to provide sufficient time for
  2411. * soundwire auto enumeration of slave devices as
  2412. * as per HW requirement.
  2413. */
  2414. usleep_range(5000, 5010);
  2415. wcd937x->wakeup = wcd937x_wakeup;
  2416. ret = component_bind_all(dev, wcd937x);
  2417. if (ret) {
  2418. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2419. __func__, ret);
  2420. return ret;
  2421. }
  2422. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2423. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2424. if (ret) {
  2425. dev_err(dev, "Failed to read port mapping\n");
  2426. goto err;
  2427. }
  2428. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2429. if (!wcd937x->rx_swr_dev) {
  2430. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2431. __func__);
  2432. ret = -ENODEV;
  2433. goto err;
  2434. }
  2435. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2436. if (!wcd937x->tx_swr_dev) {
  2437. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2438. __func__);
  2439. ret = -ENODEV;
  2440. goto err;
  2441. }
  2442. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2443. &wcd937x_regmap_config);
  2444. if (!wcd937x->regmap) {
  2445. dev_err(dev, "%s: Regmap init failed\n",
  2446. __func__);
  2447. goto err;
  2448. }
  2449. /* Set all interupts as edge triggered */
  2450. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2451. regmap_write(wcd937x->regmap,
  2452. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2453. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2454. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2455. wcd937x->irq_info.codec_name = "WCD937X";
  2456. wcd937x->irq_info.regmap = wcd937x->regmap;
  2457. wcd937x->irq_info.dev = dev;
  2458. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2459. if (ret) {
  2460. dev_err(dev, "%s: IRQ init failed: %d\n",
  2461. __func__, ret);
  2462. goto err;
  2463. }
  2464. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2465. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2466. if (ret < 0) {
  2467. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2468. goto err_irq;
  2469. }
  2470. mutex_init(&wcd937x->micb_lock);
  2471. mutex_init(&wcd937x->ana_tx_clk_lock);
  2472. /* Request for watchdog interrupt */
  2473. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2474. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2475. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2476. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2477. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2478. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2479. /* Enable watchdog interrupt for HPH and AUX */
  2480. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2481. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2482. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2483. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2484. NULL, 0);
  2485. if (ret) {
  2486. dev_err(dev, "%s: Codec registration failed\n",
  2487. __func__);
  2488. goto err_irq;
  2489. }
  2490. return ret;
  2491. err_irq:
  2492. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2493. err:
  2494. component_unbind_all(dev, wcd937x);
  2495. return ret;
  2496. }
  2497. static void wcd937x_unbind(struct device *dev)
  2498. {
  2499. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2500. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2501. snd_soc_unregister_component(dev);
  2502. component_unbind_all(dev, wcd937x);
  2503. mutex_destroy(&wcd937x->micb_lock);
  2504. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2505. }
  2506. static const struct of_device_id wcd937x_dt_match[] = {
  2507. { .compatible = "qcom,wcd937x-codec" },
  2508. {}
  2509. };
  2510. static const struct component_master_ops wcd937x_comp_ops = {
  2511. .bind = wcd937x_bind,
  2512. .unbind = wcd937x_unbind,
  2513. };
  2514. static int wcd937x_compare_of(struct device *dev, void *data)
  2515. {
  2516. return dev->of_node == data;
  2517. }
  2518. static void wcd937x_release_of(struct device *dev, void *data)
  2519. {
  2520. of_node_put(data);
  2521. }
  2522. static int wcd937x_add_slave_components(struct device *dev,
  2523. struct component_match **matchptr)
  2524. {
  2525. struct device_node *np, *rx_node, *tx_node;
  2526. np = dev->of_node;
  2527. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2528. if (!rx_node) {
  2529. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2530. return -ENODEV;
  2531. }
  2532. of_node_get(rx_node);
  2533. component_match_add_release(dev, matchptr,
  2534. wcd937x_release_of,
  2535. wcd937x_compare_of,
  2536. rx_node);
  2537. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2538. if (!tx_node) {
  2539. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2540. return -ENODEV;
  2541. }
  2542. of_node_get(tx_node);
  2543. component_match_add_release(dev, matchptr,
  2544. wcd937x_release_of,
  2545. wcd937x_compare_of,
  2546. tx_node);
  2547. return 0;
  2548. }
  2549. static int wcd937x_probe(struct platform_device *pdev)
  2550. {
  2551. struct component_match *match = NULL;
  2552. int ret;
  2553. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2554. if (ret)
  2555. return ret;
  2556. return component_master_add_with_match(&pdev->dev,
  2557. &wcd937x_comp_ops, match);
  2558. }
  2559. static int wcd937x_remove(struct platform_device *pdev)
  2560. {
  2561. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2562. return 0;
  2563. }
  2564. #ifdef CONFIG_PM_SLEEP
  2565. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2566. SET_SYSTEM_SLEEP_PM_OPS(
  2567. wcd937x_suspend,
  2568. wcd937x_resume
  2569. )
  2570. };
  2571. #endif
  2572. static struct platform_driver wcd937x_codec_driver = {
  2573. .probe = wcd937x_probe,
  2574. .remove = wcd937x_remove,
  2575. .driver = {
  2576. .name = "wcd937x_codec",
  2577. .owner = THIS_MODULE,
  2578. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2579. #ifdef CONFIG_PM_SLEEP
  2580. .pm = &wcd937x_dev_pm_ops,
  2581. #endif
  2582. .suppress_bind_attrs = true,
  2583. },
  2584. };
  2585. module_platform_driver(wcd937x_codec_driver);
  2586. MODULE_DESCRIPTION("WCD937X Codec driver");
  2587. MODULE_LICENSE("GPL v2");