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samsung-sm8650
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android_kernel_samsung_sm8650-modules
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android_kernel_...
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asoc
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codecs
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sdm660_cdc
/
msm-digital-cdc-regmap.c

msm-digital-cdc-regmap.c 18 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 and
    6. 

  6.  * only version 2 as published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful,
    9. 

  9.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    10. 

  10.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    11. 

  11.  * GNU General Public License for more details.
    12. 

  12.  */
    13. 

  13. 

  14. #include <linux/regmap.h>
    15. 

  15. #include "msm-cdc-common.h"
    16. 

  16. #include "sdm660-cdc-registers.h"
    17. 

  17. 

  18. /*
    19. 

  19.  * Default register reset values that are common across different versions
    20. 

  20.  * are defined here. If a register reset value is changed based on version
    21. 

  21.  * then remove it from this structure and add it in version specific
    22. 

  22.  * structures.
    23. 

  23.  */
    24. 

  24. struct reg_default
    25. 

  25. 	msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = {
    26. 

  26. 	{MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00},
    27. 

  27. 	{MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00},
    28. 

  28. 	{MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00},
    29. 

  29. 	{MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13},
    30. 

  30. 	{MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13},
    31. 

  31. 	{MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00},
    32. 

  32. 	{MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00},
    33. 

  33. 	{MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04},
    34. 

  34. 	{MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00},
    35. 

  35. 	{MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00},
    36. 

  36. 	{MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00},
    37. 

  37. 	{MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00},
    38. 

  38. 	{MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00},
    39. 

  39. 	{MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00},
    40. 

  40. 	{MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL, 0x13},
    41. 

  41. 	{MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00},
    42. 

  42. 	{MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00},
    43. 

  43. 	{MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00},
    44. 

  44. 	{MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00},
    45. 

  45. 	{MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00},
    46. 

  46. 	{MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00},
    47. 

  47. 	{MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00},
    48. 

  48. 	{MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00},
    49. 

  49. 	{MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00},
    50. 

  50. 	{MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00},
    51. 

  51. 	{MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00},
    52. 

  52. 	{MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00},
    53. 

  53. 	{MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68},
    54. 

  54. 	{MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68},
    55. 

  55. 	{MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68},
    56. 

  56. 	{MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00},
    57. 

  57. 	{MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00},
    58. 

  58. 	{MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00},
    59. 

  59. 	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00},
    60. 

  60. 	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00},
    61. 

  61. 	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00},
    62. 

  62. 	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00},
    63. 

  63. 	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00},
    64. 

  64. 	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00},
    65. 

  65. 	{MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00},
    66. 

  66. 	{MSM89XX_CDC_CORE_TOP_CTL, 0x01},
    67. 

  67. 	{MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30},
    68. 

  68. 	{MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5},
    69. 

  69. 	{MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28},
    70. 

  70. 	{MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37},
    71. 

  71. 	{MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F},
    72. 

  72. 	{MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00},
    73. 

  73. 	{MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03},
    74. 

  74. 	{MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03},
    75. 

  75. 	{MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02},
    76. 

  76. 	{MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00},
    77. 

  77. 	{MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00},
    78. 

  78. 	{MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00},
    79. 

  79. 	{MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00},
    80. 

  80. 	{MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00},
    81. 

  81. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00},
    82. 

  82. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00},
    83. 

  83. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00},
    84. 

  84. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00},
    85. 

  85. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00},
    86. 

  86. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00},
    87. 

  87. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00},
    88. 

  88. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00},
    89. 

  89. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00},
    90. 

  90. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00},
    91. 

  91. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00},
    92. 

  92. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00},
    93. 

  93. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00},
    94. 

  94. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00},
    95. 

  95. 	{MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00},
    96. 

  96. 	{MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00},
    97. 

  97. 	{MSM89XX_CDC_CORE_IIR1_CTL, 0x40},
    98. 

  98. 	{MSM89XX_CDC_CORE_IIR2_CTL, 0x40},
    99. 

  99. 	{MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00},
    100. 

  100. 	{MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00},
    101. 

  101. 	{MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00},
    102. 

  102. 	{MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00},
    103. 

  103. 	{MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00},
    104. 

  104. 	{MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00},
    105. 

  105. 	{MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00},
    106. 

  106. 	{MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00},
    107. 

  107. 	{MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00},
    108. 

  108. 	{MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00},
    109. 

  109. 	{MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00},
    110. 

  110. 	{MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00},
    111. 

  111. 	{MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00},
    112. 

  112. 	{MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00},
    113. 

  113. 	{MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00},
    114. 

  114. 	{MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00},
    115. 

  115. 	{MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00},
    116. 

  116. 	{MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00},
    117. 

  117. 	{MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00},
    118. 

  118. 	{MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00},
    119. 

  119. 	{MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00},
    120. 

  120. 	{MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00},
    121. 

  121. 	{MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00},
    122. 

  122. 	{MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00},
    123. 

  123. 	{MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00},
    124. 

  124. 	{MSM89XX_CDC_CORE_CONN_TX_B3_CTL, 0x00},
    125. 

  125. 	{MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER, 0x00},
    126. 

  126. 	{MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, 0x00},
    127. 

  127. 	{MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x00},
    128. 

  128. 	{MSM89XX_CDC_CORE_TX5_MUX_CTL, 0x00},
    129. 

  129. 	{MSM89XX_CDC_CORE_TX5_CLK_FS_CTL, 0x03},
    130. 

  130. 	{MSM89XX_CDC_CORE_TX5_DMIC_CTL, 0x00},
    131. 

  131. 	{MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00},
    132. 

  132. 	{MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00},
    133. 

  133. 	{MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00},
    134. 

  134. 	{MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00},
    135. 

  135. 	{MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00},
    136. 

  136. 	{MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00},
    137. 

  137. 	{MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00},
    138. 

  138. 	{MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00},
    139. 

  139. 	{MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00},
    140. 

  140. 	{MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00},
    141. 

  141. 	{MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00},
    142. 

  142. 	{MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00},
    143. 

  143. 	{MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00},
    144. 

  144. 	{MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00},
    145. 

  145. 	{MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00},
    146. 

  146. 	{MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00},
    147. 

  147. 	{MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03},
    148. 

  148. 	{MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03},
    149. 

  149. 	{MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03},
    150. 

  150. 	{MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03},
    151. 

  151. 	{MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00},
    152. 

  152. 	{MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00},
    153. 

  153. 	{MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00},
    154. 

  154. 	{MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00},
    155. 

  155. };
    156. 

  156. 

  157. static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
    158. 

  158. 		[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
    159. 

  159. 		[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
    160. 

  160. 		[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
    161. 

  161. 		[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
    162. 

  162. 		[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
    163. 

  163. 		[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
    164. 

  164. 		[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
    165. 

  165. 		[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
    166. 

  166. 		[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
    167. 

  167. 		[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
    168. 

  168. 		[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
    169. 

  169. 		[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
    170. 

  170. 		[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
    171. 

  171. 		[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
    172. 

  172. 		[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
    173. 

  173. 		[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
    174. 

  174. 		[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
    175. 

  175. 		[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
    176. 

  176. 		[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
    177. 

  177. 		[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
    178. 

  178. 		[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
    179. 

  179. 		[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
    180. 

  180. 		[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
    181. 

  181. 		[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
    182. 

  182. 		[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
    183. 

  183. 		[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
    184. 

  184. 		[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
    185. 

  185. 		[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
    186. 

  186. 		[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
    187. 

  187. 		[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
    188. 

  188. 		[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
    189. 

  189. 		[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
    190. 

  190. 		[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
    191. 

  191. 		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
    192. 

  192. 		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
    193. 

  193. 		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
    194. 

  194. 		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
    195. 

  195. 		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
    196. 

  196. 		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
    197. 

  197. 		[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
    198. 

  198. 		[MSM89XX_CDC_CORE_TOP_CTL] = 1,
    199. 

  199. 		[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
    200. 

  200. 		[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
    201. 

  201. 		[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
    202. 

  202. 		[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
    203. 

  203. 		[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
    204. 

  204. 		[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
    205. 

  205. 		[MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1,
    206. 

  206. 		[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
    207. 

  207. 		[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
    208. 

  208. 		[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
    209. 

  209. 		[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
    210. 

  210. 		[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
    211. 

  211. 		[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
    212. 

  212. 		[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
    213. 

  213. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
    214. 

  214. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
    215. 

  215. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
    216. 

  216. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
    217. 

  217. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
    218. 

  218. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
    219. 

  219. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
    220. 

  220. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
    221. 

  221. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
    222. 

  222. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
    223. 

  223. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
    224. 

  224. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
    225. 

  225. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
    226. 

  226. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
    227. 

  227. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
    228. 

  228. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
    229. 

  229. 		[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
    230. 

  230. 		[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
    231. 

  231. 		[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
    232. 

  232. 		[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
    233. 

  233. 		[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
    234. 

  234. 		[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
    235. 

  235. 		[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
    236. 

  236. 		[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
    237. 

  237. 		[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
    238. 

  238. 		[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
    239. 

  239. 		[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
    240. 

  240. 		[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
    241. 

  241. 		[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
    242. 

  242. 		[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
    243. 

  243. 		[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
    244. 

  244. 		[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
    245. 

  245. 		[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
    246. 

  246. 		[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
    247. 

  247. 		[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
    248. 

  248. 		[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
    249. 

  249. 		[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
    250. 

  250. 		[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
    251. 

  251. 		[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
    252. 

  252. 		[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
    253. 

  253. 		[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
    254. 

  254. 		[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
    255. 

  255. 		[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
    256. 

  256. 		[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
    257. 

  257. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
    258. 

  258. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
    259. 

  259. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
    260. 

  260. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
    261. 

  261. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
    262. 

  262. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
    263. 

  263. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
    264. 

  264. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
    265. 

  265. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
    266. 

  266. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
    267. 

  267. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
    268. 

  268. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
    269. 

  269. 		[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
    270. 

  270. 		[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
    271. 

  271. 		[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
    272. 

  272. 		[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
    273. 

  273. 		[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
    274. 

  274. 		[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
    275. 

  275. 		[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
    276. 

  276. 		[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
    277. 

  277. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
    278. 

  278. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
    279. 

  279. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
    280. 

  280. 		[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
    281. 

  281. 		[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
    282. 

  282. 		[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
    283. 

  283. 		[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
    284. 

  284. 		[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
    285. 

  285. 		[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
    286. 

  286. 		[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
    287. 

  287. };
    288. 

  288. 

  289. static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
    290. 

  290. 		[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
    291. 

  291. 		[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
    292. 

  292. 		[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
    293. 

  293. 		[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
    294. 

  294. 		[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
    295. 

  295. 		[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
    296. 

  296. 		[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
    297. 

  297. 		[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
    298. 

  298. 		[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
    299. 

  299. 		[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
    300. 

  300. 		[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
    301. 

  301. 		[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
    302. 

  302. 		[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
    303. 

  303. 		[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
    304. 

  304. 		[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
    305. 

  305. 		[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
    306. 

  306. 		[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
    307. 

  307. 		[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
    308. 

  308. 		[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
    309. 

  309. 		[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
    310. 

  310. 		[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
    311. 

  311. 		[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
    312. 

  312. 		[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
    313. 

  313. 		[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
    314. 

  314. 		[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
    315. 

  315. 		[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
    316. 

  316. 		[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
    317. 

  317. 		[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
    318. 

  318. 		[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
    319. 

  319. 		[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
    320. 

  320. 		[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
    321. 

  321. 		[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
    322. 

  322. 		[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
    323. 

  323. 		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
    324. 

  324. 		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
    325. 

  325. 		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
    326. 

  326. 		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
    327. 

  327. 		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
    328. 

  328. 		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
    329. 

  329. 		[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
    330. 

  330. 		[MSM89XX_CDC_CORE_TOP_CTL] = 1,
    331. 

  331. 		[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
    332. 

  332. 		[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
    333. 

  333. 		[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
    334. 

  334. 		[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
    335. 

  335. 		[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
    336. 

  336. 		[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
    337. 

  337. 		[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
    338. 

  338. 		[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
    339. 

  339. 		[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
    340. 

  340. 		[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
    341. 

  341. 		[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
    342. 

  342. 		[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
    343. 

  343. 		[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
    344. 

  344. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
    345. 

  345. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
    346. 

  346. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
    347. 

  347. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
    348. 

  348. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
    349. 

  349. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
    350. 

  350. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
    351. 

  351. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
    352. 

  352. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
    353. 

  353. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
    354. 

  354. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
    355. 

  355. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
    356. 

  356. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
    357. 

  357. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
    358. 

  358. 		[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
    359. 

  359. 		[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
    360. 

  360. 		[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
    361. 

  361. 		[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
    362. 

  362. 		[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
    363. 

  363. 		[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
    364. 

  364. 		[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
    365. 

  365. 		[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
    366. 

  366. 		[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
    367. 

  367. 		[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
    368. 

  368. 		[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
    369. 

  369. 		[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
    370. 

  370. 		[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
    371. 

  371. 		[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
    372. 

  372. 		[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
    373. 

  373. 		[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
    374. 

  374. 		[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
    375. 

  375. 		[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
    376. 

  376. 		[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
    377. 

  377. 		[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
    378. 

  378. 		[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
    379. 

  379. 		[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
    380. 

  380. 		[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
    381. 

  381. 		[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
    382. 

  382. 		[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
    383. 

  383. 		[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
    384. 

  384. 		[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
    385. 

  385. 		[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
    386. 

  386. 		[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
    387. 

  387. 		[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
    388. 

  388. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
    389. 

  389. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
    390. 

  390. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
    391. 

  391. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
    392. 

  392. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
    393. 

  393. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
    394. 

  394. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
    395. 

  395. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
    396. 

  396. 		[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
    397. 

  397. 		[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
    398. 

  398. 		[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
    399. 

  399. 		[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
    400. 

  400. 		[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
    401. 

  401. 		[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
    402. 

  402. 		[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
    403. 

  403. 		[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
    404. 

  404. 		[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
    405. 

  405. 		[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
    406. 

  406. 		[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
    407. 

  407. 		[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
    408. 

  408. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
    409. 

  409. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
    410. 

  410. 		[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
    411. 

  411. 		[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
    412. 

  412. 		[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
    413. 

  413. 		[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
    414. 

  414. 		[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
    415. 

  415. 		[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
    416. 

  416. 		[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
    417. 

  417. 		[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
    418. 

  418. };
    419. 

  419. 

  420. bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)
    421. 

  421. {
    422. 

  422. 	return msm89xx_cdc_core_reg_readable[reg];
    423. 

  423. }
    424. 

  424. 

  425. bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg)
    426. 

  426. {
    427. 

  427. 	return msm89xx_cdc_core_reg_writeable[reg];
    428. 

  428. }
    429. 

  429. 

  430. bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)
    431. 

  431. {
    432. 

  432. 	switch (reg) {
    433. 

  433. 	case MSM89XX_CDC_CORE_RX1_B1_CTL:
    434. 

  434. 	case MSM89XX_CDC_CORE_RX2_B1_CTL:
    435. 

  435. 	case MSM89XX_CDC_CORE_RX3_B1_CTL:
    436. 

  436. 	case MSM89XX_CDC_CORE_RX1_B6_CTL:
    437. 

  437. 	case MSM89XX_CDC_CORE_RX2_B6_CTL:
    438. 

  438. 	case MSM89XX_CDC_CORE_RX3_B6_CTL:
    439. 

  439. 	case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:
    440. 

  440. 	case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:
    441. 

  441. 	case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG:
    442. 

  442. 	case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG:
    443. 

  443. 	case MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG:
    444. 

  444. 	case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:
    445. 

  445. 	case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:
    446. 

  446. 	case MSM89XX_CDC_CORE_CLK_MCLK_CTL:
    447. 

  447. 	case MSM89XX_CDC_CORE_CLK_PDM_CTL:
    448. 

  448. 		return true;
    449. 

  449. 	default:
    450. 

  450. 		return false;
    451. 

  451. 	}
    452. 

  452. }
    453.