qcs405.c 239 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671767276737674767576767677767876797680768176827683768476857686768776887689769076917692769376947695769676977698769977007701770277037704770577067707770877097710771177127713771477157716771777187719772077217722772377247725772677277728772977307731773277337734773577367737773877397740774177427743774477457746774777487749775077517752775377547755775677577758775977607761776277637764776577667767776877697770777177727773777477757776777777787779778077817782778377847785778677877788778977907791779277937794779577967797779877997800780178027803780478057806780778087809781078117812781378147815781678177818781978207821782278237824782578267827782878297830783178327833783478357836783778387839784078417842784378447845784678477848784978507851785278537854785578567857785878597860786178627863786478657866786778687869787078717872787378747875787678777878787978807881788278837884788578867887788878897890789178927893789478957896789778987899790079017902790379047905790679077908790979107911791279137914791579167917791879197920792179227923792479257926792779287929793079317932793379347935793679377938793979407941794279437944794579467947794879497950795179527953795479557956795779587959796079617962796379647965796679677968796979707971797279737974797579767977797879797980798179827983798479857986798779887989799079917992799379947995799679977998799980008001800280038004800580068007800880098010801180128013801480158016801780188019802080218022802380248025802680278028802980308031803280338034803580368037803880398040804180428043804480458046804780488049805080518052805380548055805680578058805980608061806280638064806580668067806880698070807180728073807480758076807780788079808080818082808380848085808680878088808980908091809280938094809580968097809880998100810181028103810481058106810781088109811081118112811381148115811681178118811981208121812281238124812581268127812881298130813181328133813481358136813781388139814081418142814381448145814681478148814981508151815281538154815581568157815881598160816181628163816481658166816781688169817081718172817381748175817681778178817981808181818281838184818581868187818881898190819181928193819481958196819781988199820082018202820382048205820682078208820982108211821282138214821582168217821882198220822182228223822482258226822782288229823082318232823382348235823682378238823982408241824282438244824582468247824882498250825182528253825482558256825782588259826082618262826382648265826682678268826982708271827282738274827582768277827882798280828182828283828482858286828782888289829082918292829382948295829682978298829983008301830283038304830583068307830883098310831183128313831483158316831783188319832083218322832383248325832683278328832983308331833283338334833583368337833883398340834183428343834483458346834783488349835083518352835383548355835683578358835983608361836283638364836583668367836883698370837183728373837483758376837783788379838083818382838383848385838683878388838983908391839283938394839583968397839883998400840184028403840484058406840784088409841084118412841384148415841684178418841984208421842284238424842584268427842884298430843184328433843484358436843784388439844084418442844384448445844684478448844984508451845284538454845584568457845884598460846184628463846484658466846784688469847084718472847384748475847684778478847984808481848284838484848584868487848884898490849184928493849484958496849784988499850085018502850385048505850685078508850985108511851285138514851585168517851885198520852185228523852485258526852785288529853085318532853385348535853685378538853985408541854285438544854585468547854885498550855185528553855485558556855785588559856085618562856385648565856685678568856985708571857285738574857585768577857885798580858185828583858485858586858785888589859085918592859385948595859685978598859986008601860286038604860586068607860886098610861186128613861486158616861786188619862086218622862386248625862686278628862986308631863286338634863586368637
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "codecs/msm-cdc-pinctrl.h"
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  162. int dmic_01_gpio_cnt;
  163. int dmic_23_gpio_cnt;
  164. int dmic_45_gpio_cnt;
  165. int dmic_67_gpio_cnt;
  166. struct regulator *tdm_micb_supply;
  167. u32 tdm_micb_voltage;
  168. u32 tdm_micb_current;
  169. bool codec_is_csra;
  170. };
  171. struct msm_asoc_wcd93xx_codec {
  172. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  173. enum afe_config_type config_type);
  174. };
  175. static const char *const pin_states[] = {"sleep", "i2s-active",
  176. "tdm-active"};
  177. enum {
  178. TDM_0 = 0,
  179. TDM_1,
  180. TDM_2,
  181. TDM_3,
  182. TDM_4,
  183. TDM_5,
  184. TDM_6,
  185. TDM_7,
  186. TDM_PORT_MAX,
  187. };
  188. enum {
  189. TDM_PRI = 0,
  190. TDM_SEC,
  191. TDM_TERT,
  192. TDM_QUAT,
  193. TDM_QUIN,
  194. TDM_INTERFACE_MAX,
  195. };
  196. struct tdm_port {
  197. u32 mode;
  198. u32 channel;
  199. };
  200. /* TDM default config */
  201. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  202. { /* PRI TDM */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  211. },
  212. { /* SEC TDM */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  221. },
  222. { /* TERT TDM */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  231. },
  232. { /* QUAT TDM */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  241. },
  242. { /* QUIN TDM */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  251. }
  252. };
  253. /* TDM default config */
  254. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  255. { /* PRI TDM */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  264. },
  265. { /* SEC TDM */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  274. },
  275. { /* TERT TDM */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  284. },
  285. { /* QUAT TDM */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  294. },
  295. { /* QUIN TDM */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  304. }
  305. };
  306. /* Default configuration of slimbus channels */
  307. static struct dev_config slim_rx_cfg[] = {
  308. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. };
  317. static struct dev_config slim_tx_cfg[] = {
  318. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  327. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. };
  329. /* Default configuration of Codec DMA Interface Tx */
  330. static struct dev_config cdc_dma_rx_cfg[] = {
  331. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. };
  334. /* Default configuration of Codec DMA Interface Rx */
  335. static struct dev_config cdc_dma_tx_cfg[] = {
  336. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  337. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  340. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. };
  342. static struct dev_config usb_rx_cfg = {
  343. .sample_rate = SAMPLING_RATE_48KHZ,
  344. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  345. .channels = 2,
  346. };
  347. static struct dev_config usb_tx_cfg = {
  348. .sample_rate = SAMPLING_RATE_48KHZ,
  349. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  350. .channels = 1,
  351. };
  352. static struct dev_config proxy_rx_cfg = {
  353. .sample_rate = SAMPLING_RATE_48KHZ,
  354. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  355. .channels = 2,
  356. };
  357. /* Default configuration of MI2S channels */
  358. static struct dev_config mi2s_rx_cfg[] = {
  359. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  360. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. };
  366. /* Default configuration of SPDIF channels */
  367. static struct dev_config spdif_rx_cfg[] = {
  368. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. };
  371. static struct dev_config spdif_tx_cfg[] = {
  372. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. };
  375. static struct dev_config mi2s_tx_cfg[] = {
  376. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. };
  383. static struct dev_config aux_pcm_rx_cfg[] = {
  384. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. };
  391. static struct dev_config aux_pcm_tx_cfg[] = {
  392. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. };
  399. static int msm_vi_feed_tx_ch = 2;
  400. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  401. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  402. "Five", "Six", "Seven",
  403. "Eight"};
  404. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  405. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  406. "S32_LE"};
  407. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  408. "KHZ_32", "KHZ_44P1", "KHZ_48",
  409. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  410. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  411. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  412. "KHZ_44P1", "KHZ_48",
  413. "KHZ_88P2", "KHZ_96"};
  414. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  418. "Six", "Seven", "Eight"};
  419. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  420. "KHZ_16", "KHZ_22P05",
  421. "KHZ_32", "KHZ_44P1", "KHZ_48",
  422. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  423. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  424. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  425. "Five", "Six", "Seven", "Eight"};
  426. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  427. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  428. "KHZ_48", "KHZ_176P4",
  429. "KHZ_352P8"};
  430. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  431. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  432. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  433. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  434. static const char *const mi2s_ch_text[] = {
  435. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  436. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  437. "Fourteen", "Fifteen", "Sixteen"
  438. };
  439. static const char *const qos_text[] = {"Disable", "Enable"};
  440. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  441. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  442. "Five", "Six", "Seven",
  443. "Eight"};
  444. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  445. "KHZ_16", "KHZ_22P05",
  446. "KHZ_32", "KHZ_44P1", "KHZ_48",
  447. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  448. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  449. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  450. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  451. "KHZ_192"};
  452. static const char *spdif_ch_text[] = {"One", "Two"};
  453. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  454. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  539. cdc_dma_sample_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  541. cdc_dma_sample_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  543. cdc_dma_sample_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  545. cdc_dma_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  549. cdc_dma_sample_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  551. cdc_dma_sample_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  558. static struct platform_device *spdev;
  559. static bool is_initial_boot;
  560. static bool codec_reg_done;
  561. static struct snd_soc_aux_dev *msm_aux_dev;
  562. static struct snd_soc_codec_conf *msm_codec_conf;
  563. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  564. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  565. int enable, bool dapm);
  566. static int msm_wsa881x_init(struct snd_soc_component *component);
  567. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  568. struct snd_ctl_elem_value *ucontrol);
  569. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  570. {"MIC BIAS1", NULL, "MCLK TX"},
  571. {"MIC BIAS2", NULL, "MCLK TX"},
  572. {"MIC BIAS3", NULL, "MCLK TX"},
  573. {"MIC BIAS4", NULL, "MCLK TX"},
  574. };
  575. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  576. {
  577. AFE_API_VERSION_I2S_CONFIG,
  578. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  579. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  580. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  581. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  582. 0,
  583. },
  584. {
  585. AFE_API_VERSION_I2S_CONFIG,
  586. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  587. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  588. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  589. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  590. 0,
  591. },
  592. {
  593. AFE_API_VERSION_I2S_CONFIG,
  594. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  595. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  596. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  597. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  598. 0,
  599. },
  600. {
  601. AFE_API_VERSION_I2S_CONFIG,
  602. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  603. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  604. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  605. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  606. 0,
  607. },
  608. {
  609. AFE_API_VERSION_I2S_CONFIG,
  610. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  611. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  612. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  613. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  614. 0,
  615. },
  616. {
  617. AFE_API_VERSION_I2S_CONFIG,
  618. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  619. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  620. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  621. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  622. 0,
  623. }
  624. };
  625. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  626. static int slim_get_sample_rate_val(int sample_rate)
  627. {
  628. int sample_rate_val = 0;
  629. switch (sample_rate) {
  630. case SAMPLING_RATE_8KHZ:
  631. sample_rate_val = 0;
  632. break;
  633. case SAMPLING_RATE_16KHZ:
  634. sample_rate_val = 1;
  635. break;
  636. case SAMPLING_RATE_32KHZ:
  637. sample_rate_val = 2;
  638. break;
  639. case SAMPLING_RATE_44P1KHZ:
  640. sample_rate_val = 3;
  641. break;
  642. case SAMPLING_RATE_48KHZ:
  643. sample_rate_val = 4;
  644. break;
  645. case SAMPLING_RATE_88P2KHZ:
  646. sample_rate_val = 5;
  647. break;
  648. case SAMPLING_RATE_96KHZ:
  649. sample_rate_val = 6;
  650. break;
  651. case SAMPLING_RATE_176P4KHZ:
  652. sample_rate_val = 7;
  653. break;
  654. case SAMPLING_RATE_192KHZ:
  655. sample_rate_val = 8;
  656. break;
  657. case SAMPLING_RATE_352P8KHZ:
  658. sample_rate_val = 9;
  659. break;
  660. case SAMPLING_RATE_384KHZ:
  661. sample_rate_val = 10;
  662. break;
  663. default:
  664. sample_rate_val = 4;
  665. break;
  666. }
  667. return sample_rate_val;
  668. }
  669. static int slim_get_sample_rate(int value)
  670. {
  671. int sample_rate = 0;
  672. switch (value) {
  673. case 0:
  674. sample_rate = SAMPLING_RATE_8KHZ;
  675. break;
  676. case 1:
  677. sample_rate = SAMPLING_RATE_16KHZ;
  678. break;
  679. case 2:
  680. sample_rate = SAMPLING_RATE_32KHZ;
  681. break;
  682. case 3:
  683. sample_rate = SAMPLING_RATE_44P1KHZ;
  684. break;
  685. case 4:
  686. sample_rate = SAMPLING_RATE_48KHZ;
  687. break;
  688. case 5:
  689. sample_rate = SAMPLING_RATE_88P2KHZ;
  690. break;
  691. case 6:
  692. sample_rate = SAMPLING_RATE_96KHZ;
  693. break;
  694. case 7:
  695. sample_rate = SAMPLING_RATE_176P4KHZ;
  696. break;
  697. case 8:
  698. sample_rate = SAMPLING_RATE_192KHZ;
  699. break;
  700. case 9:
  701. sample_rate = SAMPLING_RATE_352P8KHZ;
  702. break;
  703. case 10:
  704. sample_rate = SAMPLING_RATE_384KHZ;
  705. break;
  706. default:
  707. sample_rate = SAMPLING_RATE_48KHZ;
  708. break;
  709. }
  710. return sample_rate;
  711. }
  712. static int slim_get_bit_format_val(int bit_format)
  713. {
  714. int val = 0;
  715. switch (bit_format) {
  716. case SNDRV_PCM_FORMAT_S32_LE:
  717. val = 3;
  718. break;
  719. case SNDRV_PCM_FORMAT_S24_3LE:
  720. val = 2;
  721. break;
  722. case SNDRV_PCM_FORMAT_S24_LE:
  723. val = 1;
  724. break;
  725. case SNDRV_PCM_FORMAT_S16_LE:
  726. default:
  727. val = 0;
  728. break;
  729. }
  730. return val;
  731. }
  732. static int slim_get_bit_format(int val)
  733. {
  734. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  735. switch (val) {
  736. case 0:
  737. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  738. break;
  739. case 1:
  740. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  741. break;
  742. case 2:
  743. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  744. break;
  745. case 3:
  746. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  747. break;
  748. default:
  749. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  750. break;
  751. }
  752. return bit_fmt;
  753. }
  754. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  755. {
  756. int port_id = 0;
  757. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  758. port_id = SLIM_RX_0;
  759. } else if (strnstr(kcontrol->id.name,
  760. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  761. port_id = SLIM_RX_2;
  762. } else if (strnstr(kcontrol->id.name,
  763. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  764. port_id = SLIM_RX_5;
  765. } else if (strnstr(kcontrol->id.name,
  766. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  767. port_id = SLIM_RX_6;
  768. } else if (strnstr(kcontrol->id.name,
  769. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  770. port_id = SLIM_TX_0;
  771. } else if (strnstr(kcontrol->id.name,
  772. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  773. port_id = SLIM_TX_1;
  774. } else {
  775. pr_err("%s: unsupported channel: %s",
  776. __func__, kcontrol->id.name);
  777. return -EINVAL;
  778. }
  779. return port_id;
  780. }
  781. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  782. struct snd_ctl_elem_value *ucontrol)
  783. {
  784. int ch_num = slim_get_port_idx(kcontrol);
  785. if (ch_num < 0)
  786. return ch_num;
  787. ucontrol->value.enumerated.item[0] =
  788. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  789. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  790. ch_num, slim_rx_cfg[ch_num].sample_rate,
  791. ucontrol->value.enumerated.item[0]);
  792. return 0;
  793. }
  794. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. int ch_num = slim_get_port_idx(kcontrol);
  798. if (ch_num < 0)
  799. return ch_num;
  800. slim_rx_cfg[ch_num].sample_rate =
  801. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  802. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  803. ch_num, slim_rx_cfg[ch_num].sample_rate,
  804. ucontrol->value.enumerated.item[0]);
  805. return 0;
  806. }
  807. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  808. struct snd_ctl_elem_value *ucontrol)
  809. {
  810. int ch_num = slim_get_port_idx(kcontrol);
  811. if (ch_num < 0)
  812. return ch_num;
  813. ucontrol->value.enumerated.item[0] =
  814. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  815. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  816. ch_num, slim_tx_cfg[ch_num].sample_rate,
  817. ucontrol->value.enumerated.item[0]);
  818. return 0;
  819. }
  820. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. int sample_rate = 0;
  824. int ch_num = slim_get_port_idx(kcontrol);
  825. if (ch_num < 0)
  826. return ch_num;
  827. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  828. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  829. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  830. __func__, sample_rate);
  831. return -EINVAL;
  832. }
  833. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  834. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  835. ch_num, slim_tx_cfg[ch_num].sample_rate,
  836. ucontrol->value.enumerated.item[0]);
  837. return 0;
  838. }
  839. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. int ch_num = slim_get_port_idx(kcontrol);
  843. if (ch_num < 0)
  844. return ch_num;
  845. ucontrol->value.enumerated.item[0] =
  846. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  847. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  848. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  849. ucontrol->value.enumerated.item[0]);
  850. return 0;
  851. }
  852. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. int ch_num = slim_get_port_idx(kcontrol);
  856. if (ch_num < 0)
  857. return ch_num;
  858. slim_rx_cfg[ch_num].bit_format =
  859. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  860. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  861. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  862. ucontrol->value.enumerated.item[0]);
  863. return 0;
  864. }
  865. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. ucontrol->value.enumerated.item[0] =
  872. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  873. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  874. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  875. ucontrol->value.enumerated.item[0]);
  876. return 0;
  877. }
  878. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. int ch_num = slim_get_port_idx(kcontrol);
  882. if (ch_num < 0)
  883. return ch_num;
  884. slim_tx_cfg[ch_num].bit_format =
  885. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  886. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  887. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  888. ucontrol->value.enumerated.item[0]);
  889. return 0;
  890. }
  891. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_value *ucontrol)
  893. {
  894. int ch_num = slim_get_port_idx(kcontrol);
  895. if (ch_num < 0)
  896. return ch_num;
  897. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  898. ch_num, slim_rx_cfg[ch_num].channels);
  899. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  900. return 0;
  901. }
  902. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. int ch_num = slim_get_port_idx(kcontrol);
  906. if (ch_num < 0)
  907. return ch_num;
  908. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  909. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  910. ch_num, slim_rx_cfg[ch_num].channels);
  911. return 1;
  912. }
  913. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. int ch_num = slim_get_port_idx(kcontrol);
  917. if (ch_num < 0)
  918. return ch_num;
  919. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  920. ch_num, slim_tx_cfg[ch_num].channels);
  921. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  922. return 0;
  923. }
  924. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. int ch_num = slim_get_port_idx(kcontrol);
  928. if (ch_num < 0)
  929. return ch_num;
  930. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  931. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  932. ch_num, slim_tx_cfg[ch_num].channels);
  933. return 1;
  934. }
  935. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  939. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  940. ucontrol->value.integer.value[0]);
  941. return 0;
  942. }
  943. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  944. struct snd_ctl_elem_value *ucontrol)
  945. {
  946. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  947. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  948. return 1;
  949. }
  950. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  951. struct snd_ctl_elem_value *ucontrol)
  952. {
  953. /*
  954. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  955. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  956. * value.
  957. */
  958. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  959. case SAMPLING_RATE_96KHZ:
  960. ucontrol->value.integer.value[0] = 5;
  961. break;
  962. case SAMPLING_RATE_88P2KHZ:
  963. ucontrol->value.integer.value[0] = 4;
  964. break;
  965. case SAMPLING_RATE_48KHZ:
  966. ucontrol->value.integer.value[0] = 3;
  967. break;
  968. case SAMPLING_RATE_44P1KHZ:
  969. ucontrol->value.integer.value[0] = 2;
  970. break;
  971. case SAMPLING_RATE_16KHZ:
  972. ucontrol->value.integer.value[0] = 1;
  973. break;
  974. case SAMPLING_RATE_8KHZ:
  975. default:
  976. ucontrol->value.integer.value[0] = 0;
  977. break;
  978. }
  979. pr_debug("%s: sample rate = %d", __func__,
  980. slim_rx_cfg[SLIM_RX_7].sample_rate);
  981. return 0;
  982. }
  983. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  984. struct snd_ctl_elem_value *ucontrol)
  985. {
  986. switch (ucontrol->value.integer.value[0]) {
  987. case 1:
  988. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  989. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  990. break;
  991. case 2:
  992. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  993. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  994. break;
  995. case 3:
  996. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  997. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  998. break;
  999. case 4:
  1000. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1001. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1002. break;
  1003. case 5:
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1006. break;
  1007. case 0:
  1008. default:
  1009. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1010. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1011. break;
  1012. }
  1013. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1014. __func__,
  1015. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1016. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1017. ucontrol->value.enumerated.item[0]);
  1018. return 0;
  1019. }
  1020. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1021. struct snd_ctl_elem_value *ucontrol)
  1022. {
  1023. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1024. case SAMPLING_RATE_96KHZ:
  1025. ucontrol->value.integer.value[0] = 5;
  1026. break;
  1027. case SAMPLING_RATE_88P2KHZ:
  1028. ucontrol->value.integer.value[0] = 4;
  1029. break;
  1030. case SAMPLING_RATE_48KHZ:
  1031. ucontrol->value.integer.value[0] = 3;
  1032. break;
  1033. case SAMPLING_RATE_44P1KHZ:
  1034. ucontrol->value.integer.value[0] = 2;
  1035. break;
  1036. case SAMPLING_RATE_16KHZ:
  1037. ucontrol->value.integer.value[0] = 1;
  1038. break;
  1039. case SAMPLING_RATE_8KHZ:
  1040. default:
  1041. ucontrol->value.integer.value[0] = 0;
  1042. break;
  1043. }
  1044. pr_debug("%s: sample rate = %d", __func__,
  1045. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1046. return 0;
  1047. }
  1048. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1049. struct snd_ctl_elem_value *ucontrol)
  1050. {
  1051. switch (ucontrol->value.integer.value[0]) {
  1052. case 1:
  1053. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1054. break;
  1055. case 2:
  1056. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1057. break;
  1058. case 3:
  1059. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1060. break;
  1061. case 4:
  1062. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1063. break;
  1064. case 5:
  1065. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1066. break;
  1067. case 0:
  1068. default:
  1069. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1070. break;
  1071. }
  1072. pr_debug("%s: sample rate = %d, value = %d\n",
  1073. __func__,
  1074. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1075. ucontrol->value.enumerated.item[0]);
  1076. return 0;
  1077. }
  1078. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1079. {
  1080. int idx = 0;
  1081. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1082. sizeof("WSA_CDC_DMA_RX_0")))
  1083. idx = WSA_CDC_DMA_RX_0;
  1084. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1085. sizeof("WSA_CDC_DMA_RX_0")))
  1086. idx = WSA_CDC_DMA_RX_1;
  1087. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1088. sizeof("WSA_CDC_DMA_TX_0")))
  1089. idx = WSA_CDC_DMA_TX_0;
  1090. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1091. sizeof("WSA_CDC_DMA_TX_1")))
  1092. idx = WSA_CDC_DMA_TX_1;
  1093. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1094. sizeof("WSA_CDC_DMA_TX_2")))
  1095. idx = WSA_CDC_DMA_TX_2;
  1096. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1097. sizeof("VA_CDC_DMA_TX_0")))
  1098. idx = VA_CDC_DMA_TX_0;
  1099. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1100. sizeof("VA_CDC_DMA_TX_1")))
  1101. idx = VA_CDC_DMA_TX_1;
  1102. else {
  1103. pr_err("%s: unsupported port: %s\n",
  1104. __func__, kcontrol->id.name);
  1105. return -EINVAL;
  1106. }
  1107. return idx;
  1108. }
  1109. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1110. struct snd_ctl_elem_value *ucontrol)
  1111. {
  1112. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1113. if (ch_num < 0)
  1114. return ch_num;
  1115. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1116. cdc_dma_rx_cfg[ch_num].channels - 1);
  1117. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1118. return 0;
  1119. }
  1120. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1121. struct snd_ctl_elem_value *ucontrol)
  1122. {
  1123. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1124. if (ch_num < 0)
  1125. return ch_num;
  1126. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1127. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1128. cdc_dma_rx_cfg[ch_num].channels);
  1129. return 1;
  1130. }
  1131. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1132. struct snd_ctl_elem_value *ucontrol)
  1133. {
  1134. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1135. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1136. case SNDRV_PCM_FORMAT_S32_LE:
  1137. ucontrol->value.integer.value[0] = 3;
  1138. break;
  1139. case SNDRV_PCM_FORMAT_S24_3LE:
  1140. ucontrol->value.integer.value[0] = 2;
  1141. break;
  1142. case SNDRV_PCM_FORMAT_S24_LE:
  1143. ucontrol->value.integer.value[0] = 1;
  1144. break;
  1145. case SNDRV_PCM_FORMAT_S16_LE:
  1146. default:
  1147. ucontrol->value.integer.value[0] = 0;
  1148. break;
  1149. }
  1150. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1151. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1152. ucontrol->value.integer.value[0]);
  1153. return 0;
  1154. }
  1155. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1156. struct snd_ctl_elem_value *ucontrol)
  1157. {
  1158. int rc = 0;
  1159. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1160. switch (ucontrol->value.integer.value[0]) {
  1161. case 3:
  1162. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1163. break;
  1164. case 2:
  1165. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1166. break;
  1167. case 1:
  1168. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1169. break;
  1170. case 0:
  1171. default:
  1172. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1173. break;
  1174. }
  1175. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1176. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1177. ucontrol->value.integer.value[0]);
  1178. return rc;
  1179. }
  1180. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1181. {
  1182. int sample_rate_val = 0;
  1183. switch (sample_rate) {
  1184. case SAMPLING_RATE_8KHZ:
  1185. sample_rate_val = 0;
  1186. break;
  1187. case SAMPLING_RATE_11P025KHZ:
  1188. sample_rate_val = 1;
  1189. break;
  1190. case SAMPLING_RATE_16KHZ:
  1191. sample_rate_val = 2;
  1192. break;
  1193. case SAMPLING_RATE_22P05KHZ:
  1194. sample_rate_val = 3;
  1195. break;
  1196. case SAMPLING_RATE_32KHZ:
  1197. sample_rate_val = 4;
  1198. break;
  1199. case SAMPLING_RATE_44P1KHZ:
  1200. sample_rate_val = 5;
  1201. break;
  1202. case SAMPLING_RATE_48KHZ:
  1203. sample_rate_val = 6;
  1204. break;
  1205. case SAMPLING_RATE_88P2KHZ:
  1206. sample_rate_val = 7;
  1207. break;
  1208. case SAMPLING_RATE_96KHZ:
  1209. sample_rate_val = 8;
  1210. break;
  1211. case SAMPLING_RATE_176P4KHZ:
  1212. sample_rate_val = 9;
  1213. break;
  1214. case SAMPLING_RATE_192KHZ:
  1215. sample_rate_val = 10;
  1216. break;
  1217. case SAMPLING_RATE_352P8KHZ:
  1218. sample_rate_val = 11;
  1219. break;
  1220. case SAMPLING_RATE_384KHZ:
  1221. sample_rate_val = 12;
  1222. break;
  1223. default:
  1224. sample_rate_val = 6;
  1225. break;
  1226. }
  1227. return sample_rate_val;
  1228. }
  1229. static int cdc_dma_get_sample_rate(int value)
  1230. {
  1231. int sample_rate = 0;
  1232. switch (value) {
  1233. case 0:
  1234. sample_rate = SAMPLING_RATE_8KHZ;
  1235. break;
  1236. case 1:
  1237. sample_rate = SAMPLING_RATE_11P025KHZ;
  1238. break;
  1239. case 2:
  1240. sample_rate = SAMPLING_RATE_16KHZ;
  1241. break;
  1242. case 3:
  1243. sample_rate = SAMPLING_RATE_22P05KHZ;
  1244. break;
  1245. case 4:
  1246. sample_rate = SAMPLING_RATE_32KHZ;
  1247. break;
  1248. case 5:
  1249. sample_rate = SAMPLING_RATE_44P1KHZ;
  1250. break;
  1251. case 6:
  1252. sample_rate = SAMPLING_RATE_48KHZ;
  1253. break;
  1254. case 7:
  1255. sample_rate = SAMPLING_RATE_88P2KHZ;
  1256. break;
  1257. case 8:
  1258. sample_rate = SAMPLING_RATE_96KHZ;
  1259. break;
  1260. case 9:
  1261. sample_rate = SAMPLING_RATE_176P4KHZ;
  1262. break;
  1263. case 10:
  1264. sample_rate = SAMPLING_RATE_192KHZ;
  1265. break;
  1266. case 11:
  1267. sample_rate = SAMPLING_RATE_352P8KHZ;
  1268. break;
  1269. case 12:
  1270. sample_rate = SAMPLING_RATE_384KHZ;
  1271. break;
  1272. default:
  1273. sample_rate = SAMPLING_RATE_48KHZ;
  1274. break;
  1275. }
  1276. return sample_rate;
  1277. }
  1278. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1279. struct snd_ctl_elem_value *ucontrol)
  1280. {
  1281. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1282. if (ch_num < 0)
  1283. return ch_num;
  1284. ucontrol->value.enumerated.item[0] =
  1285. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1286. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1287. cdc_dma_rx_cfg[ch_num].sample_rate);
  1288. return 0;
  1289. }
  1290. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1291. struct snd_ctl_elem_value *ucontrol)
  1292. {
  1293. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1294. if (ch_num < 0)
  1295. return ch_num;
  1296. cdc_dma_rx_cfg[ch_num].sample_rate =
  1297. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1298. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1299. __func__, ucontrol->value.enumerated.item[0],
  1300. cdc_dma_rx_cfg[ch_num].sample_rate);
  1301. return 0;
  1302. }
  1303. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1304. struct snd_ctl_elem_value *ucontrol)
  1305. {
  1306. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1307. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1308. cdc_dma_tx_cfg[ch_num].channels);
  1309. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1310. return 0;
  1311. }
  1312. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1313. struct snd_ctl_elem_value *ucontrol)
  1314. {
  1315. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1316. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1317. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1318. cdc_dma_tx_cfg[ch_num].channels);
  1319. return 1;
  1320. }
  1321. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. int sample_rate_val;
  1325. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1326. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1327. case SAMPLING_RATE_384KHZ:
  1328. sample_rate_val = 12;
  1329. break;
  1330. case SAMPLING_RATE_352P8KHZ:
  1331. sample_rate_val = 11;
  1332. break;
  1333. case SAMPLING_RATE_192KHZ:
  1334. sample_rate_val = 10;
  1335. break;
  1336. case SAMPLING_RATE_176P4KHZ:
  1337. sample_rate_val = 9;
  1338. break;
  1339. case SAMPLING_RATE_96KHZ:
  1340. sample_rate_val = 8;
  1341. break;
  1342. case SAMPLING_RATE_88P2KHZ:
  1343. sample_rate_val = 7;
  1344. break;
  1345. case SAMPLING_RATE_48KHZ:
  1346. sample_rate_val = 6;
  1347. break;
  1348. case SAMPLING_RATE_44P1KHZ:
  1349. sample_rate_val = 5;
  1350. break;
  1351. case SAMPLING_RATE_32KHZ:
  1352. sample_rate_val = 4;
  1353. break;
  1354. case SAMPLING_RATE_22P05KHZ:
  1355. sample_rate_val = 3;
  1356. break;
  1357. case SAMPLING_RATE_16KHZ:
  1358. sample_rate_val = 2;
  1359. break;
  1360. case SAMPLING_RATE_11P025KHZ:
  1361. sample_rate_val = 1;
  1362. break;
  1363. case SAMPLING_RATE_8KHZ:
  1364. sample_rate_val = 0;
  1365. break;
  1366. default:
  1367. sample_rate_val = 6;
  1368. break;
  1369. }
  1370. ucontrol->value.integer.value[0] = sample_rate_val;
  1371. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1372. cdc_dma_tx_cfg[ch_num].sample_rate);
  1373. return 0;
  1374. }
  1375. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1376. struct snd_ctl_elem_value *ucontrol)
  1377. {
  1378. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1379. switch (ucontrol->value.integer.value[0]) {
  1380. case 12:
  1381. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1382. break;
  1383. case 11:
  1384. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1385. break;
  1386. case 10:
  1387. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1388. break;
  1389. case 9:
  1390. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1391. break;
  1392. case 8:
  1393. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1394. break;
  1395. case 7:
  1396. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1397. break;
  1398. case 6:
  1399. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1400. break;
  1401. case 5:
  1402. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1403. break;
  1404. case 4:
  1405. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1406. break;
  1407. case 3:
  1408. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1409. break;
  1410. case 2:
  1411. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1412. break;
  1413. case 1:
  1414. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1415. break;
  1416. case 0:
  1417. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1418. break;
  1419. default:
  1420. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1421. break;
  1422. }
  1423. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1424. __func__, ucontrol->value.integer.value[0],
  1425. cdc_dma_tx_cfg[ch_num].sample_rate);
  1426. return 0;
  1427. }
  1428. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1429. struct snd_ctl_elem_value *ucontrol)
  1430. {
  1431. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1432. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1433. case SNDRV_PCM_FORMAT_S32_LE:
  1434. ucontrol->value.integer.value[0] = 3;
  1435. break;
  1436. case SNDRV_PCM_FORMAT_S24_3LE:
  1437. ucontrol->value.integer.value[0] = 2;
  1438. break;
  1439. case SNDRV_PCM_FORMAT_S24_LE:
  1440. ucontrol->value.integer.value[0] = 1;
  1441. break;
  1442. case SNDRV_PCM_FORMAT_S16_LE:
  1443. default:
  1444. ucontrol->value.integer.value[0] = 0;
  1445. break;
  1446. }
  1447. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1448. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1449. ucontrol->value.integer.value[0]);
  1450. return 0;
  1451. }
  1452. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1453. struct snd_ctl_elem_value *ucontrol)
  1454. {
  1455. int rc = 0;
  1456. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1457. switch (ucontrol->value.integer.value[0]) {
  1458. case 3:
  1459. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1460. break;
  1461. case 2:
  1462. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1463. break;
  1464. case 1:
  1465. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1466. break;
  1467. case 0:
  1468. default:
  1469. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1470. break;
  1471. }
  1472. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1473. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1474. ucontrol->value.integer.value[0]);
  1475. return rc;
  1476. }
  1477. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1481. usb_rx_cfg.channels);
  1482. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1483. return 0;
  1484. }
  1485. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1486. struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1489. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1490. return 1;
  1491. }
  1492. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. int sample_rate_val;
  1496. switch (usb_rx_cfg.sample_rate) {
  1497. case SAMPLING_RATE_384KHZ:
  1498. sample_rate_val = 12;
  1499. break;
  1500. case SAMPLING_RATE_352P8KHZ:
  1501. sample_rate_val = 11;
  1502. break;
  1503. case SAMPLING_RATE_192KHZ:
  1504. sample_rate_val = 10;
  1505. break;
  1506. case SAMPLING_RATE_176P4KHZ:
  1507. sample_rate_val = 9;
  1508. break;
  1509. case SAMPLING_RATE_96KHZ:
  1510. sample_rate_val = 8;
  1511. break;
  1512. case SAMPLING_RATE_88P2KHZ:
  1513. sample_rate_val = 7;
  1514. break;
  1515. case SAMPLING_RATE_48KHZ:
  1516. sample_rate_val = 6;
  1517. break;
  1518. case SAMPLING_RATE_44P1KHZ:
  1519. sample_rate_val = 5;
  1520. break;
  1521. case SAMPLING_RATE_32KHZ:
  1522. sample_rate_val = 4;
  1523. break;
  1524. case SAMPLING_RATE_22P05KHZ:
  1525. sample_rate_val = 3;
  1526. break;
  1527. case SAMPLING_RATE_16KHZ:
  1528. sample_rate_val = 2;
  1529. break;
  1530. case SAMPLING_RATE_11P025KHZ:
  1531. sample_rate_val = 1;
  1532. break;
  1533. case SAMPLING_RATE_8KHZ:
  1534. default:
  1535. sample_rate_val = 0;
  1536. break;
  1537. }
  1538. ucontrol->value.integer.value[0] = sample_rate_val;
  1539. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1540. usb_rx_cfg.sample_rate);
  1541. return 0;
  1542. }
  1543. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. switch (ucontrol->value.integer.value[0]) {
  1547. case 12:
  1548. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1549. break;
  1550. case 11:
  1551. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1552. break;
  1553. case 10:
  1554. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1555. break;
  1556. case 9:
  1557. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1558. break;
  1559. case 8:
  1560. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1561. break;
  1562. case 7:
  1563. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1564. break;
  1565. case 6:
  1566. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1567. break;
  1568. case 5:
  1569. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1570. break;
  1571. case 4:
  1572. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1573. break;
  1574. case 3:
  1575. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1576. break;
  1577. case 2:
  1578. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1579. break;
  1580. case 1:
  1581. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1582. break;
  1583. case 0:
  1584. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1585. break;
  1586. default:
  1587. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1588. break;
  1589. }
  1590. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1591. __func__, ucontrol->value.integer.value[0],
  1592. usb_rx_cfg.sample_rate);
  1593. return 0;
  1594. }
  1595. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_value *ucontrol)
  1597. {
  1598. switch (usb_rx_cfg.bit_format) {
  1599. case SNDRV_PCM_FORMAT_S32_LE:
  1600. ucontrol->value.integer.value[0] = 3;
  1601. break;
  1602. case SNDRV_PCM_FORMAT_S24_3LE:
  1603. ucontrol->value.integer.value[0] = 2;
  1604. break;
  1605. case SNDRV_PCM_FORMAT_S24_LE:
  1606. ucontrol->value.integer.value[0] = 1;
  1607. break;
  1608. case SNDRV_PCM_FORMAT_S16_LE:
  1609. default:
  1610. ucontrol->value.integer.value[0] = 0;
  1611. break;
  1612. }
  1613. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1614. __func__, usb_rx_cfg.bit_format,
  1615. ucontrol->value.integer.value[0]);
  1616. return 0;
  1617. }
  1618. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1619. struct snd_ctl_elem_value *ucontrol)
  1620. {
  1621. int rc = 0;
  1622. switch (ucontrol->value.integer.value[0]) {
  1623. case 3:
  1624. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1625. break;
  1626. case 2:
  1627. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1628. break;
  1629. case 1:
  1630. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1631. break;
  1632. case 0:
  1633. default:
  1634. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1635. break;
  1636. }
  1637. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1638. __func__, usb_rx_cfg.bit_format,
  1639. ucontrol->value.integer.value[0]);
  1640. return rc;
  1641. }
  1642. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1643. struct snd_ctl_elem_value *ucontrol)
  1644. {
  1645. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1646. usb_tx_cfg.channels);
  1647. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1648. return 0;
  1649. }
  1650. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1651. struct snd_ctl_elem_value *ucontrol)
  1652. {
  1653. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1654. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1655. return 1;
  1656. }
  1657. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1658. struct snd_ctl_elem_value *ucontrol)
  1659. {
  1660. int sample_rate_val;
  1661. switch (usb_tx_cfg.sample_rate) {
  1662. case SAMPLING_RATE_384KHZ:
  1663. sample_rate_val = 12;
  1664. break;
  1665. case SAMPLING_RATE_352P8KHZ:
  1666. sample_rate_val = 11;
  1667. break;
  1668. case SAMPLING_RATE_192KHZ:
  1669. sample_rate_val = 10;
  1670. break;
  1671. case SAMPLING_RATE_176P4KHZ:
  1672. sample_rate_val = 9;
  1673. break;
  1674. case SAMPLING_RATE_96KHZ:
  1675. sample_rate_val = 8;
  1676. break;
  1677. case SAMPLING_RATE_88P2KHZ:
  1678. sample_rate_val = 7;
  1679. break;
  1680. case SAMPLING_RATE_48KHZ:
  1681. sample_rate_val = 6;
  1682. break;
  1683. case SAMPLING_RATE_44P1KHZ:
  1684. sample_rate_val = 5;
  1685. break;
  1686. case SAMPLING_RATE_32KHZ:
  1687. sample_rate_val = 4;
  1688. break;
  1689. case SAMPLING_RATE_22P05KHZ:
  1690. sample_rate_val = 3;
  1691. break;
  1692. case SAMPLING_RATE_16KHZ:
  1693. sample_rate_val = 2;
  1694. break;
  1695. case SAMPLING_RATE_11P025KHZ:
  1696. sample_rate_val = 1;
  1697. break;
  1698. case SAMPLING_RATE_8KHZ:
  1699. sample_rate_val = 0;
  1700. break;
  1701. default:
  1702. sample_rate_val = 6;
  1703. break;
  1704. }
  1705. ucontrol->value.integer.value[0] = sample_rate_val;
  1706. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1707. usb_tx_cfg.sample_rate);
  1708. return 0;
  1709. }
  1710. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1711. struct snd_ctl_elem_value *ucontrol)
  1712. {
  1713. switch (ucontrol->value.integer.value[0]) {
  1714. case 12:
  1715. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1716. break;
  1717. case 11:
  1718. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1719. break;
  1720. case 10:
  1721. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1722. break;
  1723. case 9:
  1724. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1725. break;
  1726. case 8:
  1727. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1728. break;
  1729. case 7:
  1730. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1731. break;
  1732. case 6:
  1733. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1734. break;
  1735. case 5:
  1736. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1737. break;
  1738. case 4:
  1739. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1740. break;
  1741. case 3:
  1742. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1743. break;
  1744. case 2:
  1745. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1746. break;
  1747. case 1:
  1748. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1749. break;
  1750. case 0:
  1751. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1752. break;
  1753. default:
  1754. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1755. break;
  1756. }
  1757. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1758. __func__, ucontrol->value.integer.value[0],
  1759. usb_tx_cfg.sample_rate);
  1760. return 0;
  1761. }
  1762. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1763. struct snd_ctl_elem_value *ucontrol)
  1764. {
  1765. switch (usb_tx_cfg.bit_format) {
  1766. case SNDRV_PCM_FORMAT_S32_LE:
  1767. ucontrol->value.integer.value[0] = 3;
  1768. break;
  1769. case SNDRV_PCM_FORMAT_S24_3LE:
  1770. ucontrol->value.integer.value[0] = 2;
  1771. break;
  1772. case SNDRV_PCM_FORMAT_S24_LE:
  1773. ucontrol->value.integer.value[0] = 1;
  1774. break;
  1775. case SNDRV_PCM_FORMAT_S16_LE:
  1776. default:
  1777. ucontrol->value.integer.value[0] = 0;
  1778. break;
  1779. }
  1780. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1781. __func__, usb_tx_cfg.bit_format,
  1782. ucontrol->value.integer.value[0]);
  1783. return 0;
  1784. }
  1785. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1786. struct snd_ctl_elem_value *ucontrol)
  1787. {
  1788. int rc = 0;
  1789. switch (ucontrol->value.integer.value[0]) {
  1790. case 3:
  1791. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1792. break;
  1793. case 2:
  1794. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1795. break;
  1796. case 1:
  1797. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1798. break;
  1799. case 0:
  1800. default:
  1801. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1802. break;
  1803. }
  1804. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1805. __func__, usb_tx_cfg.bit_format,
  1806. ucontrol->value.integer.value[0]);
  1807. return rc;
  1808. }
  1809. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1810. struct snd_ctl_elem_value *ucontrol)
  1811. {
  1812. pr_debug("%s: proxy_rx channels = %d\n",
  1813. __func__, proxy_rx_cfg.channels);
  1814. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1815. return 0;
  1816. }
  1817. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1818. struct snd_ctl_elem_value *ucontrol)
  1819. {
  1820. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1821. pr_debug("%s: proxy_rx channels = %d\n",
  1822. __func__, proxy_rx_cfg.channels);
  1823. return 1;
  1824. }
  1825. static int tdm_get_sample_rate(int value)
  1826. {
  1827. int sample_rate = 0;
  1828. switch (value) {
  1829. case 0:
  1830. sample_rate = SAMPLING_RATE_8KHZ;
  1831. break;
  1832. case 1:
  1833. sample_rate = SAMPLING_RATE_16KHZ;
  1834. break;
  1835. case 2:
  1836. sample_rate = SAMPLING_RATE_32KHZ;
  1837. break;
  1838. case 3:
  1839. sample_rate = SAMPLING_RATE_48KHZ;
  1840. break;
  1841. case 4:
  1842. sample_rate = SAMPLING_RATE_176P4KHZ;
  1843. break;
  1844. case 5:
  1845. sample_rate = SAMPLING_RATE_352P8KHZ;
  1846. break;
  1847. default:
  1848. sample_rate = SAMPLING_RATE_48KHZ;
  1849. break;
  1850. }
  1851. return sample_rate;
  1852. }
  1853. static int aux_pcm_get_sample_rate(int value)
  1854. {
  1855. int sample_rate;
  1856. switch (value) {
  1857. case 1:
  1858. sample_rate = SAMPLING_RATE_16KHZ;
  1859. break;
  1860. case 0:
  1861. default:
  1862. sample_rate = SAMPLING_RATE_8KHZ;
  1863. break;
  1864. }
  1865. return sample_rate;
  1866. }
  1867. static int tdm_get_sample_rate_val(int sample_rate)
  1868. {
  1869. int sample_rate_val = 0;
  1870. switch (sample_rate) {
  1871. case SAMPLING_RATE_8KHZ:
  1872. sample_rate_val = 0;
  1873. break;
  1874. case SAMPLING_RATE_16KHZ:
  1875. sample_rate_val = 1;
  1876. break;
  1877. case SAMPLING_RATE_32KHZ:
  1878. sample_rate_val = 2;
  1879. break;
  1880. case SAMPLING_RATE_48KHZ:
  1881. sample_rate_val = 3;
  1882. break;
  1883. case SAMPLING_RATE_176P4KHZ:
  1884. sample_rate_val = 4;
  1885. break;
  1886. case SAMPLING_RATE_352P8KHZ:
  1887. sample_rate_val = 5;
  1888. break;
  1889. default:
  1890. sample_rate_val = 3;
  1891. break;
  1892. }
  1893. return sample_rate_val;
  1894. }
  1895. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1896. {
  1897. int sample_rate_val;
  1898. switch (sample_rate) {
  1899. case SAMPLING_RATE_16KHZ:
  1900. sample_rate_val = 1;
  1901. break;
  1902. case SAMPLING_RATE_8KHZ:
  1903. default:
  1904. sample_rate_val = 0;
  1905. break;
  1906. }
  1907. return sample_rate_val;
  1908. }
  1909. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1910. struct tdm_port *port)
  1911. {
  1912. if (port) {
  1913. if (strnstr(kcontrol->id.name, "PRI",
  1914. sizeof(kcontrol->id.name))) {
  1915. port->mode = TDM_PRI;
  1916. } else if (strnstr(kcontrol->id.name, "SEC",
  1917. sizeof(kcontrol->id.name))) {
  1918. port->mode = TDM_SEC;
  1919. } else if (strnstr(kcontrol->id.name, "TERT",
  1920. sizeof(kcontrol->id.name))) {
  1921. port->mode = TDM_TERT;
  1922. } else if (strnstr(kcontrol->id.name, "QUAT",
  1923. sizeof(kcontrol->id.name))) {
  1924. port->mode = TDM_QUAT;
  1925. } else if (strnstr(kcontrol->id.name, "QUIN",
  1926. sizeof(kcontrol->id.name))) {
  1927. port->mode = TDM_QUIN;
  1928. } else {
  1929. pr_err("%s: unsupported mode in: %s",
  1930. __func__, kcontrol->id.name);
  1931. return -EINVAL;
  1932. }
  1933. if (strnstr(kcontrol->id.name, "RX_0",
  1934. sizeof(kcontrol->id.name)) ||
  1935. strnstr(kcontrol->id.name, "TX_0",
  1936. sizeof(kcontrol->id.name))) {
  1937. port->channel = TDM_0;
  1938. } else if (strnstr(kcontrol->id.name, "RX_1",
  1939. sizeof(kcontrol->id.name)) ||
  1940. strnstr(kcontrol->id.name, "TX_1",
  1941. sizeof(kcontrol->id.name))) {
  1942. port->channel = TDM_1;
  1943. } else if (strnstr(kcontrol->id.name, "RX_2",
  1944. sizeof(kcontrol->id.name)) ||
  1945. strnstr(kcontrol->id.name, "TX_2",
  1946. sizeof(kcontrol->id.name))) {
  1947. port->channel = TDM_2;
  1948. } else if (strnstr(kcontrol->id.name, "RX_3",
  1949. sizeof(kcontrol->id.name)) ||
  1950. strnstr(kcontrol->id.name, "TX_3",
  1951. sizeof(kcontrol->id.name))) {
  1952. port->channel = TDM_3;
  1953. } else if (strnstr(kcontrol->id.name, "RX_4",
  1954. sizeof(kcontrol->id.name)) ||
  1955. strnstr(kcontrol->id.name, "TX_4",
  1956. sizeof(kcontrol->id.name))) {
  1957. port->channel = TDM_4;
  1958. } else if (strnstr(kcontrol->id.name, "RX_5",
  1959. sizeof(kcontrol->id.name)) ||
  1960. strnstr(kcontrol->id.name, "TX_5",
  1961. sizeof(kcontrol->id.name))) {
  1962. port->channel = TDM_5;
  1963. } else if (strnstr(kcontrol->id.name, "RX_6",
  1964. sizeof(kcontrol->id.name)) ||
  1965. strnstr(kcontrol->id.name, "TX_6",
  1966. sizeof(kcontrol->id.name))) {
  1967. port->channel = TDM_6;
  1968. } else if (strnstr(kcontrol->id.name, "RX_7",
  1969. sizeof(kcontrol->id.name)) ||
  1970. strnstr(kcontrol->id.name, "TX_7",
  1971. sizeof(kcontrol->id.name))) {
  1972. port->channel = TDM_7;
  1973. } else {
  1974. pr_err("%s: unsupported channel in: %s",
  1975. __func__, kcontrol->id.name);
  1976. return -EINVAL;
  1977. }
  1978. } else
  1979. return -EINVAL;
  1980. return 0;
  1981. }
  1982. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1983. struct snd_ctl_elem_value *ucontrol)
  1984. {
  1985. struct tdm_port port;
  1986. int ret = tdm_get_port_idx(kcontrol, &port);
  1987. if (ret) {
  1988. pr_err("%s: unsupported control: %s",
  1989. __func__, kcontrol->id.name);
  1990. } else {
  1991. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1992. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1993. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1994. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1995. ucontrol->value.enumerated.item[0]);
  1996. }
  1997. return ret;
  1998. }
  1999. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2000. struct snd_ctl_elem_value *ucontrol)
  2001. {
  2002. struct tdm_port port;
  2003. int ret = tdm_get_port_idx(kcontrol, &port);
  2004. if (ret) {
  2005. pr_err("%s: unsupported control: %s",
  2006. __func__, kcontrol->id.name);
  2007. } else {
  2008. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2009. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2010. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2011. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2012. ucontrol->value.enumerated.item[0]);
  2013. }
  2014. return ret;
  2015. }
  2016. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2017. struct snd_ctl_elem_value *ucontrol)
  2018. {
  2019. struct tdm_port port;
  2020. int ret = tdm_get_port_idx(kcontrol, &port);
  2021. if (ret) {
  2022. pr_err("%s: unsupported control: %s",
  2023. __func__, kcontrol->id.name);
  2024. } else {
  2025. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2026. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2027. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2028. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2029. ucontrol->value.enumerated.item[0]);
  2030. }
  2031. return ret;
  2032. }
  2033. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2034. struct snd_ctl_elem_value *ucontrol)
  2035. {
  2036. struct tdm_port port;
  2037. int ret = tdm_get_port_idx(kcontrol, &port);
  2038. if (ret) {
  2039. pr_err("%s: unsupported control: %s",
  2040. __func__, kcontrol->id.name);
  2041. } else {
  2042. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2043. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2044. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2045. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2046. ucontrol->value.enumerated.item[0]);
  2047. }
  2048. return ret;
  2049. }
  2050. static int tdm_get_format(int value)
  2051. {
  2052. int format = 0;
  2053. switch (value) {
  2054. case 0:
  2055. format = SNDRV_PCM_FORMAT_S16_LE;
  2056. break;
  2057. case 1:
  2058. format = SNDRV_PCM_FORMAT_S24_LE;
  2059. break;
  2060. case 2:
  2061. format = SNDRV_PCM_FORMAT_S32_LE;
  2062. break;
  2063. default:
  2064. format = SNDRV_PCM_FORMAT_S16_LE;
  2065. break;
  2066. }
  2067. return format;
  2068. }
  2069. static int tdm_get_format_val(int format)
  2070. {
  2071. int value = 0;
  2072. switch (format) {
  2073. case SNDRV_PCM_FORMAT_S16_LE:
  2074. value = 0;
  2075. break;
  2076. case SNDRV_PCM_FORMAT_S24_LE:
  2077. value = 1;
  2078. break;
  2079. case SNDRV_PCM_FORMAT_S32_LE:
  2080. value = 2;
  2081. break;
  2082. default:
  2083. value = 0;
  2084. break;
  2085. }
  2086. return value;
  2087. }
  2088. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2089. struct snd_ctl_elem_value *ucontrol)
  2090. {
  2091. struct tdm_port port;
  2092. int ret = tdm_get_port_idx(kcontrol, &port);
  2093. if (ret) {
  2094. pr_err("%s: unsupported control: %s",
  2095. __func__, kcontrol->id.name);
  2096. } else {
  2097. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2098. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2099. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2100. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2101. ucontrol->value.enumerated.item[0]);
  2102. }
  2103. return ret;
  2104. }
  2105. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2106. struct snd_ctl_elem_value *ucontrol)
  2107. {
  2108. struct tdm_port port;
  2109. int ret = tdm_get_port_idx(kcontrol, &port);
  2110. if (ret) {
  2111. pr_err("%s: unsupported control: %s",
  2112. __func__, kcontrol->id.name);
  2113. } else {
  2114. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2115. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2116. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2117. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2118. ucontrol->value.enumerated.item[0]);
  2119. }
  2120. return ret;
  2121. }
  2122. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2123. struct snd_ctl_elem_value *ucontrol)
  2124. {
  2125. struct tdm_port port;
  2126. int ret = tdm_get_port_idx(kcontrol, &port);
  2127. if (ret) {
  2128. pr_err("%s: unsupported control: %s",
  2129. __func__, kcontrol->id.name);
  2130. } else {
  2131. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2132. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2133. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2134. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2135. ucontrol->value.enumerated.item[0]);
  2136. }
  2137. return ret;
  2138. }
  2139. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2140. struct snd_ctl_elem_value *ucontrol)
  2141. {
  2142. struct tdm_port port;
  2143. int ret = tdm_get_port_idx(kcontrol, &port);
  2144. if (ret) {
  2145. pr_err("%s: unsupported control: %s",
  2146. __func__, kcontrol->id.name);
  2147. } else {
  2148. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2149. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2150. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2151. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2152. ucontrol->value.enumerated.item[0]);
  2153. }
  2154. return ret;
  2155. }
  2156. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2157. struct snd_ctl_elem_value *ucontrol)
  2158. {
  2159. struct tdm_port port;
  2160. int ret = tdm_get_port_idx(kcontrol, &port);
  2161. if (ret) {
  2162. pr_err("%s: unsupported control: %s",
  2163. __func__, kcontrol->id.name);
  2164. } else {
  2165. ucontrol->value.enumerated.item[0] =
  2166. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2167. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2168. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2169. ucontrol->value.enumerated.item[0]);
  2170. }
  2171. return ret;
  2172. }
  2173. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2174. struct snd_ctl_elem_value *ucontrol)
  2175. {
  2176. struct tdm_port port;
  2177. int ret = tdm_get_port_idx(kcontrol, &port);
  2178. if (ret) {
  2179. pr_err("%s: unsupported control: %s",
  2180. __func__, kcontrol->id.name);
  2181. } else {
  2182. tdm_rx_cfg[port.mode][port.channel].channels =
  2183. ucontrol->value.enumerated.item[0] + 1;
  2184. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2185. tdm_rx_cfg[port.mode][port.channel].channels,
  2186. ucontrol->value.enumerated.item[0] + 1);
  2187. }
  2188. return ret;
  2189. }
  2190. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2191. struct snd_ctl_elem_value *ucontrol)
  2192. {
  2193. struct tdm_port port;
  2194. int ret = tdm_get_port_idx(kcontrol, &port);
  2195. if (ret) {
  2196. pr_err("%s: unsupported control: %s",
  2197. __func__, kcontrol->id.name);
  2198. } else {
  2199. ucontrol->value.enumerated.item[0] =
  2200. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2201. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2202. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2203. ucontrol->value.enumerated.item[0]);
  2204. }
  2205. return ret;
  2206. }
  2207. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2208. struct snd_ctl_elem_value *ucontrol)
  2209. {
  2210. struct tdm_port port;
  2211. int ret = tdm_get_port_idx(kcontrol, &port);
  2212. if (ret) {
  2213. pr_err("%s: unsupported control: %s",
  2214. __func__, kcontrol->id.name);
  2215. } else {
  2216. tdm_tx_cfg[port.mode][port.channel].channels =
  2217. ucontrol->value.enumerated.item[0] + 1;
  2218. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2219. tdm_tx_cfg[port.mode][port.channel].channels,
  2220. ucontrol->value.enumerated.item[0] + 1);
  2221. }
  2222. return ret;
  2223. }
  2224. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2225. {
  2226. int idx;
  2227. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2228. sizeof("PRIM_AUX_PCM")))
  2229. idx = PRIM_AUX_PCM;
  2230. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2231. sizeof("SEC_AUX_PCM")))
  2232. idx = SEC_AUX_PCM;
  2233. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2234. sizeof("TERT_AUX_PCM")))
  2235. idx = TERT_AUX_PCM;
  2236. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2237. sizeof("QUAT_AUX_PCM")))
  2238. idx = QUAT_AUX_PCM;
  2239. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2240. sizeof("QUIN_AUX_PCM")))
  2241. idx = QUIN_AUX_PCM;
  2242. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2243. sizeof("SENN_AUX_PCM")))
  2244. idx = SEN_AUX_PCM;
  2245. else {
  2246. pr_err("%s: unsupported port: %s",
  2247. __func__, kcontrol->id.name);
  2248. idx = -EINVAL;
  2249. }
  2250. return idx;
  2251. }
  2252. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2253. struct snd_ctl_elem_value *ucontrol)
  2254. {
  2255. int idx = aux_pcm_get_port_idx(kcontrol);
  2256. if (idx < 0)
  2257. return idx;
  2258. aux_pcm_rx_cfg[idx].sample_rate =
  2259. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2260. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2261. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2262. ucontrol->value.enumerated.item[0]);
  2263. return 0;
  2264. }
  2265. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2266. struct snd_ctl_elem_value *ucontrol)
  2267. {
  2268. int idx = aux_pcm_get_port_idx(kcontrol);
  2269. if (idx < 0)
  2270. return idx;
  2271. ucontrol->value.enumerated.item[0] =
  2272. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2273. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2274. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2275. ucontrol->value.enumerated.item[0]);
  2276. return 0;
  2277. }
  2278. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2279. struct snd_ctl_elem_value *ucontrol)
  2280. {
  2281. int idx = aux_pcm_get_port_idx(kcontrol);
  2282. if (idx < 0)
  2283. return idx;
  2284. aux_pcm_tx_cfg[idx].sample_rate =
  2285. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2286. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2287. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2288. ucontrol->value.enumerated.item[0]);
  2289. return 0;
  2290. }
  2291. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2292. struct snd_ctl_elem_value *ucontrol)
  2293. {
  2294. int idx = aux_pcm_get_port_idx(kcontrol);
  2295. if (idx < 0)
  2296. return idx;
  2297. ucontrol->value.enumerated.item[0] =
  2298. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2299. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2300. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2301. ucontrol->value.enumerated.item[0]);
  2302. return 0;
  2303. }
  2304. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2305. {
  2306. int idx;
  2307. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2308. sizeof("PRIM_MI2S_RX")))
  2309. idx = PRIM_MI2S;
  2310. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2311. sizeof("SEC_MI2S_RX")))
  2312. idx = SEC_MI2S;
  2313. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2314. sizeof("TERT_MI2S_RX")))
  2315. idx = TERT_MI2S;
  2316. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2317. sizeof("QUAT_MI2S_RX")))
  2318. idx = QUAT_MI2S;
  2319. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2320. sizeof("QUIN_MI2S_RX")))
  2321. idx = QUIN_MI2S;
  2322. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2323. sizeof("SEN_MI2S_RX")))
  2324. idx = SEN_MI2S;
  2325. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2326. sizeof("PRIM_MI2S_TX")))
  2327. idx = PRIM_MI2S;
  2328. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2329. sizeof("SEC_MI2S_TX")))
  2330. idx = SEC_MI2S;
  2331. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2332. sizeof("TERT_MI2S_TX")))
  2333. idx = TERT_MI2S;
  2334. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2335. sizeof("QUAT_MI2S_TX")))
  2336. idx = QUAT_MI2S;
  2337. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2338. sizeof("QUIN_MI2S_TX")))
  2339. idx = QUIN_MI2S;
  2340. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2341. sizeof("SEN_MI2S_TX")))
  2342. idx = SEN_MI2S;
  2343. else {
  2344. pr_err("%s: unsupported channel: %s",
  2345. __func__, kcontrol->id.name);
  2346. idx = -EINVAL;
  2347. }
  2348. return idx;
  2349. }
  2350. static int mi2s_get_sample_rate_val(int sample_rate)
  2351. {
  2352. int sample_rate_val;
  2353. switch (sample_rate) {
  2354. case SAMPLING_RATE_8KHZ:
  2355. sample_rate_val = 0;
  2356. break;
  2357. case SAMPLING_RATE_11P025KHZ:
  2358. sample_rate_val = 1;
  2359. break;
  2360. case SAMPLING_RATE_16KHZ:
  2361. sample_rate_val = 2;
  2362. break;
  2363. case SAMPLING_RATE_22P05KHZ:
  2364. sample_rate_val = 3;
  2365. break;
  2366. case SAMPLING_RATE_32KHZ:
  2367. sample_rate_val = 4;
  2368. break;
  2369. case SAMPLING_RATE_44P1KHZ:
  2370. sample_rate_val = 5;
  2371. break;
  2372. case SAMPLING_RATE_48KHZ:
  2373. sample_rate_val = 6;
  2374. break;
  2375. case SAMPLING_RATE_96KHZ:
  2376. sample_rate_val = 7;
  2377. break;
  2378. case SAMPLING_RATE_192KHZ:
  2379. sample_rate_val = 8;
  2380. break;
  2381. case SAMPLING_RATE_384KHZ:
  2382. sample_rate_val = 9;
  2383. break;
  2384. default:
  2385. sample_rate_val = 6;
  2386. break;
  2387. }
  2388. return sample_rate_val;
  2389. }
  2390. static int mi2s_get_sample_rate(int value)
  2391. {
  2392. int sample_rate;
  2393. switch (value) {
  2394. case 0:
  2395. sample_rate = SAMPLING_RATE_8KHZ;
  2396. break;
  2397. case 1:
  2398. sample_rate = SAMPLING_RATE_11P025KHZ;
  2399. break;
  2400. case 2:
  2401. sample_rate = SAMPLING_RATE_16KHZ;
  2402. break;
  2403. case 3:
  2404. sample_rate = SAMPLING_RATE_22P05KHZ;
  2405. break;
  2406. case 4:
  2407. sample_rate = SAMPLING_RATE_32KHZ;
  2408. break;
  2409. case 5:
  2410. sample_rate = SAMPLING_RATE_44P1KHZ;
  2411. break;
  2412. case 6:
  2413. sample_rate = SAMPLING_RATE_48KHZ;
  2414. break;
  2415. case 7:
  2416. sample_rate = SAMPLING_RATE_96KHZ;
  2417. break;
  2418. case 8:
  2419. sample_rate = SAMPLING_RATE_192KHZ;
  2420. break;
  2421. case 9:
  2422. sample_rate = SAMPLING_RATE_384KHZ;
  2423. break;
  2424. default:
  2425. sample_rate = SAMPLING_RATE_48KHZ;
  2426. break;
  2427. }
  2428. return sample_rate;
  2429. }
  2430. static int mi2s_auxpcm_get_format(int value)
  2431. {
  2432. int format;
  2433. switch (value) {
  2434. case 0:
  2435. format = SNDRV_PCM_FORMAT_S16_LE;
  2436. break;
  2437. case 1:
  2438. format = SNDRV_PCM_FORMAT_S24_LE;
  2439. break;
  2440. case 2:
  2441. format = SNDRV_PCM_FORMAT_S24_3LE;
  2442. break;
  2443. case 3:
  2444. format = SNDRV_PCM_FORMAT_S32_LE;
  2445. break;
  2446. default:
  2447. format = SNDRV_PCM_FORMAT_S16_LE;
  2448. break;
  2449. }
  2450. return format;
  2451. }
  2452. static int mi2s_auxpcm_get_format_value(int format)
  2453. {
  2454. int value;
  2455. switch (format) {
  2456. case SNDRV_PCM_FORMAT_S16_LE:
  2457. value = 0;
  2458. break;
  2459. case SNDRV_PCM_FORMAT_S24_LE:
  2460. value = 1;
  2461. break;
  2462. case SNDRV_PCM_FORMAT_S24_3LE:
  2463. value = 2;
  2464. break;
  2465. case SNDRV_PCM_FORMAT_S32_LE:
  2466. value = 3;
  2467. break;
  2468. default:
  2469. value = 0;
  2470. break;
  2471. }
  2472. return value;
  2473. }
  2474. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2475. struct snd_ctl_elem_value *ucontrol)
  2476. {
  2477. int idx = mi2s_get_port_idx(kcontrol);
  2478. if (idx < 0)
  2479. return idx;
  2480. mi2s_rx_cfg[idx].sample_rate =
  2481. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2482. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2483. idx, mi2s_rx_cfg[idx].sample_rate,
  2484. ucontrol->value.enumerated.item[0]);
  2485. return 0;
  2486. }
  2487. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2488. struct snd_ctl_elem_value *ucontrol)
  2489. {
  2490. int idx = mi2s_get_port_idx(kcontrol);
  2491. if (idx < 0)
  2492. return idx;
  2493. ucontrol->value.enumerated.item[0] =
  2494. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2495. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2496. idx, mi2s_rx_cfg[idx].sample_rate,
  2497. ucontrol->value.enumerated.item[0]);
  2498. return 0;
  2499. }
  2500. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2501. struct snd_ctl_elem_value *ucontrol)
  2502. {
  2503. int idx = mi2s_get_port_idx(kcontrol);
  2504. if (idx < 0)
  2505. return idx;
  2506. mi2s_tx_cfg[idx].sample_rate =
  2507. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2508. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2509. idx, mi2s_tx_cfg[idx].sample_rate,
  2510. ucontrol->value.enumerated.item[0]);
  2511. return 0;
  2512. }
  2513. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2514. struct snd_ctl_elem_value *ucontrol)
  2515. {
  2516. int idx = mi2s_get_port_idx(kcontrol);
  2517. if (idx < 0)
  2518. return idx;
  2519. ucontrol->value.enumerated.item[0] =
  2520. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2521. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2522. idx, mi2s_tx_cfg[idx].sample_rate,
  2523. ucontrol->value.enumerated.item[0]);
  2524. return 0;
  2525. }
  2526. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2527. struct snd_ctl_elem_value *ucontrol)
  2528. {
  2529. int idx = mi2s_get_port_idx(kcontrol);
  2530. if (idx < 0)
  2531. return idx;
  2532. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2533. idx, mi2s_rx_cfg[idx].channels);
  2534. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2535. return 0;
  2536. }
  2537. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2538. struct snd_ctl_elem_value *ucontrol)
  2539. {
  2540. int idx = mi2s_get_port_idx(kcontrol);
  2541. if (idx < 0)
  2542. return idx;
  2543. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2544. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2545. idx, mi2s_rx_cfg[idx].channels);
  2546. return 1;
  2547. }
  2548. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2549. struct snd_ctl_elem_value *ucontrol)
  2550. {
  2551. int idx = mi2s_get_port_idx(kcontrol);
  2552. if (idx < 0)
  2553. return idx;
  2554. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2555. idx, mi2s_tx_cfg[idx].channels);
  2556. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2557. return 0;
  2558. }
  2559. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2560. struct snd_ctl_elem_value *ucontrol)
  2561. {
  2562. int idx = mi2s_get_port_idx(kcontrol);
  2563. if (idx < 0)
  2564. return idx;
  2565. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2566. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2567. idx, mi2s_tx_cfg[idx].channels);
  2568. return 1;
  2569. }
  2570. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2571. struct snd_ctl_elem_value *ucontrol)
  2572. {
  2573. int idx = mi2s_get_port_idx(kcontrol);
  2574. if (idx < 0)
  2575. return idx;
  2576. ucontrol->value.enumerated.item[0] =
  2577. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2578. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2579. idx, mi2s_rx_cfg[idx].bit_format,
  2580. ucontrol->value.enumerated.item[0]);
  2581. return 0;
  2582. }
  2583. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2584. struct snd_ctl_elem_value *ucontrol)
  2585. {
  2586. struct msm_asoc_mach_data *pdata = NULL;
  2587. struct snd_soc_component *component = NULL;
  2588. struct snd_soc_card *card = NULL;
  2589. int idx = mi2s_get_port_idx(kcontrol);
  2590. component = snd_soc_kcontrol_component(kcontrol);
  2591. card = kcontrol->private_data;
  2592. pdata = snd_soc_card_get_drvdata(card);
  2593. if (idx < 0)
  2594. return idx;
  2595. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2596. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2597. {
  2598. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2599. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2600. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2601. ucontrol->value.enumerated.item[0]);
  2602. } else {
  2603. mi2s_rx_cfg[idx].bit_format =
  2604. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2605. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2606. idx, mi2s_rx_cfg[idx].bit_format,
  2607. ucontrol->value.enumerated.item[0]);
  2608. }
  2609. return 0;
  2610. }
  2611. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2612. struct snd_ctl_elem_value *ucontrol)
  2613. {
  2614. int idx = mi2s_get_port_idx(kcontrol);
  2615. if (idx < 0)
  2616. return idx;
  2617. ucontrol->value.enumerated.item[0] =
  2618. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2619. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2620. idx, mi2s_tx_cfg[idx].bit_format,
  2621. ucontrol->value.enumerated.item[0]);
  2622. return 0;
  2623. }
  2624. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2625. struct snd_ctl_elem_value *ucontrol)
  2626. {
  2627. int idx = mi2s_get_port_idx(kcontrol);
  2628. if (idx < 0)
  2629. return idx;
  2630. mi2s_tx_cfg[idx].bit_format =
  2631. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2632. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2633. idx, mi2s_tx_cfg[idx].bit_format,
  2634. ucontrol->value.enumerated.item[0]);
  2635. return 0;
  2636. }
  2637. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2638. struct snd_ctl_elem_value *ucontrol)
  2639. {
  2640. int idx = aux_pcm_get_port_idx(kcontrol);
  2641. if (idx < 0)
  2642. return idx;
  2643. ucontrol->value.enumerated.item[0] =
  2644. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2645. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2646. idx, aux_pcm_rx_cfg[idx].bit_format,
  2647. ucontrol->value.enumerated.item[0]);
  2648. return 0;
  2649. }
  2650. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2651. struct snd_ctl_elem_value *ucontrol)
  2652. {
  2653. int idx = aux_pcm_get_port_idx(kcontrol);
  2654. if (idx < 0)
  2655. return idx;
  2656. aux_pcm_rx_cfg[idx].bit_format =
  2657. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2658. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2659. idx, aux_pcm_rx_cfg[idx].bit_format,
  2660. ucontrol->value.enumerated.item[0]);
  2661. return 0;
  2662. }
  2663. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2664. struct snd_ctl_elem_value *ucontrol)
  2665. {
  2666. int idx = aux_pcm_get_port_idx(kcontrol);
  2667. if (idx < 0)
  2668. return idx;
  2669. ucontrol->value.enumerated.item[0] =
  2670. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2671. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2672. idx, aux_pcm_tx_cfg[idx].bit_format,
  2673. ucontrol->value.enumerated.item[0]);
  2674. return 0;
  2675. }
  2676. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2677. struct snd_ctl_elem_value *ucontrol)
  2678. {
  2679. int idx = aux_pcm_get_port_idx(kcontrol);
  2680. if (idx < 0)
  2681. return idx;
  2682. aux_pcm_tx_cfg[idx].bit_format =
  2683. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2684. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2685. idx, aux_pcm_tx_cfg[idx].bit_format,
  2686. ucontrol->value.enumerated.item[0]);
  2687. return 0;
  2688. }
  2689. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2690. {
  2691. int idx;
  2692. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2693. sizeof("PRIM_SPDIF_RX")))
  2694. idx = PRIM_SPDIF_RX;
  2695. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2696. sizeof("SEC_SPDIF_RX")))
  2697. idx = SEC_SPDIF_RX;
  2698. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2699. sizeof("PRIM_SPDIF_TX")))
  2700. idx = PRIM_SPDIF_TX;
  2701. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2702. sizeof("SEC_SPDIF_TX")))
  2703. idx = SEC_SPDIF_TX;
  2704. else {
  2705. pr_err("%s: unsupported channel: %s",
  2706. __func__, kcontrol->id.name);
  2707. idx = -EINVAL;
  2708. }
  2709. return idx;
  2710. }
  2711. static int spdif_get_sample_rate_val(int sample_rate)
  2712. {
  2713. int sample_rate_val;
  2714. switch (sample_rate) {
  2715. case SAMPLING_RATE_32KHZ:
  2716. sample_rate_val = 0;
  2717. break;
  2718. case SAMPLING_RATE_44P1KHZ:
  2719. sample_rate_val = 1;
  2720. break;
  2721. case SAMPLING_RATE_48KHZ:
  2722. sample_rate_val = 2;
  2723. break;
  2724. case SAMPLING_RATE_88P2KHZ:
  2725. sample_rate_val = 3;
  2726. break;
  2727. case SAMPLING_RATE_96KHZ:
  2728. sample_rate_val = 4;
  2729. break;
  2730. case SAMPLING_RATE_176P4KHZ:
  2731. sample_rate_val = 5;
  2732. break;
  2733. case SAMPLING_RATE_192KHZ:
  2734. sample_rate_val = 6;
  2735. break;
  2736. default:
  2737. sample_rate_val = 2;
  2738. break;
  2739. }
  2740. return sample_rate_val;
  2741. }
  2742. static int spdif_get_sample_rate(int value)
  2743. {
  2744. int sample_rate;
  2745. switch (value) {
  2746. case 0:
  2747. sample_rate = SAMPLING_RATE_32KHZ;
  2748. break;
  2749. case 1:
  2750. sample_rate = SAMPLING_RATE_44P1KHZ;
  2751. break;
  2752. case 2:
  2753. sample_rate = SAMPLING_RATE_48KHZ;
  2754. break;
  2755. case 3:
  2756. sample_rate = SAMPLING_RATE_88P2KHZ;
  2757. break;
  2758. case 4:
  2759. sample_rate = SAMPLING_RATE_96KHZ;
  2760. break;
  2761. case 5:
  2762. sample_rate = SAMPLING_RATE_176P4KHZ;
  2763. break;
  2764. case 6:
  2765. sample_rate = SAMPLING_RATE_192KHZ;
  2766. break;
  2767. default:
  2768. sample_rate = SAMPLING_RATE_48KHZ;
  2769. break;
  2770. }
  2771. return sample_rate;
  2772. }
  2773. static int spdif_get_format(int value)
  2774. {
  2775. int format;
  2776. switch (value) {
  2777. case 0:
  2778. format = SNDRV_PCM_FORMAT_S16_LE;
  2779. break;
  2780. case 1:
  2781. format = SNDRV_PCM_FORMAT_S24_LE;
  2782. break;
  2783. default:
  2784. format = SNDRV_PCM_FORMAT_S16_LE;
  2785. break;
  2786. }
  2787. return format;
  2788. }
  2789. static int spdif_get_format_value(int format)
  2790. {
  2791. int value;
  2792. switch (format) {
  2793. case SNDRV_PCM_FORMAT_S16_LE:
  2794. value = 0;
  2795. break;
  2796. case SNDRV_PCM_FORMAT_S24_LE:
  2797. value = 1;
  2798. break;
  2799. default:
  2800. value = 0;
  2801. break;
  2802. }
  2803. return value;
  2804. }
  2805. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2806. struct snd_ctl_elem_value *ucontrol)
  2807. {
  2808. int idx = spdif_get_port_idx(kcontrol);
  2809. if (idx < 0)
  2810. return idx;
  2811. spdif_rx_cfg[idx].sample_rate =
  2812. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2813. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2814. idx, spdif_rx_cfg[idx].sample_rate,
  2815. ucontrol->value.enumerated.item[0]);
  2816. return 0;
  2817. }
  2818. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2819. struct snd_ctl_elem_value *ucontrol)
  2820. {
  2821. int idx = spdif_get_port_idx(kcontrol);
  2822. if (idx < 0)
  2823. return idx;
  2824. ucontrol->value.enumerated.item[0] =
  2825. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2826. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2827. idx, spdif_rx_cfg[idx].sample_rate,
  2828. ucontrol->value.enumerated.item[0]);
  2829. return 0;
  2830. }
  2831. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2832. struct snd_ctl_elem_value *ucontrol)
  2833. {
  2834. int idx = spdif_get_port_idx(kcontrol);
  2835. if (idx < 0)
  2836. return idx;
  2837. spdif_tx_cfg[idx].sample_rate =
  2838. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2839. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2840. idx, spdif_tx_cfg[idx].sample_rate,
  2841. ucontrol->value.enumerated.item[0]);
  2842. return 0;
  2843. }
  2844. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2845. struct snd_ctl_elem_value *ucontrol)
  2846. {
  2847. int idx = spdif_get_port_idx(kcontrol);
  2848. if (idx < 0)
  2849. return idx;
  2850. ucontrol->value.enumerated.item[0] =
  2851. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2852. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2853. idx, spdif_tx_cfg[idx].sample_rate,
  2854. ucontrol->value.enumerated.item[0]);
  2855. return 0;
  2856. }
  2857. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2858. struct snd_ctl_elem_value *ucontrol)
  2859. {
  2860. int idx = spdif_get_port_idx(kcontrol);
  2861. if (idx < 0)
  2862. return idx;
  2863. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2864. idx, spdif_rx_cfg[idx].channels);
  2865. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2866. return 0;
  2867. }
  2868. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2869. struct snd_ctl_elem_value *ucontrol)
  2870. {
  2871. int idx = spdif_get_port_idx(kcontrol);
  2872. if (idx < 0)
  2873. return idx;
  2874. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2875. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2876. idx, spdif_rx_cfg[idx].channels);
  2877. return 1;
  2878. }
  2879. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2880. struct snd_ctl_elem_value *ucontrol)
  2881. {
  2882. int idx = spdif_get_port_idx(kcontrol);
  2883. if (idx < 0)
  2884. return idx;
  2885. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2886. idx, spdif_tx_cfg[idx].channels);
  2887. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2888. return 0;
  2889. }
  2890. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2891. struct snd_ctl_elem_value *ucontrol)
  2892. {
  2893. int idx = spdif_get_port_idx(kcontrol);
  2894. if (idx < 0)
  2895. return idx;
  2896. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2897. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2898. idx, spdif_tx_cfg[idx].channels);
  2899. return 1;
  2900. }
  2901. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2902. struct snd_ctl_elem_value *ucontrol)
  2903. {
  2904. int idx = spdif_get_port_idx(kcontrol);
  2905. if (idx < 0)
  2906. return idx;
  2907. ucontrol->value.enumerated.item[0] =
  2908. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2909. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2910. idx, spdif_rx_cfg[idx].bit_format,
  2911. ucontrol->value.enumerated.item[0]);
  2912. return 0;
  2913. }
  2914. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2915. struct snd_ctl_elem_value *ucontrol)
  2916. {
  2917. int idx = spdif_get_port_idx(kcontrol);
  2918. if (idx < 0)
  2919. return idx;
  2920. spdif_rx_cfg[idx].bit_format =
  2921. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2922. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2923. idx, spdif_rx_cfg[idx].bit_format,
  2924. ucontrol->value.enumerated.item[0]);
  2925. return 0;
  2926. }
  2927. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2928. struct snd_ctl_elem_value *ucontrol)
  2929. {
  2930. int idx = spdif_get_port_idx(kcontrol);
  2931. if (idx < 0)
  2932. return idx;
  2933. ucontrol->value.enumerated.item[0] =
  2934. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2935. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2936. idx, spdif_tx_cfg[idx].bit_format,
  2937. ucontrol->value.enumerated.item[0]);
  2938. return 0;
  2939. }
  2940. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2941. struct snd_ctl_elem_value *ucontrol)
  2942. {
  2943. int idx = spdif_get_port_idx(kcontrol);
  2944. if (idx < 0)
  2945. return idx;
  2946. spdif_tx_cfg[idx].bit_format =
  2947. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2948. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2949. idx, spdif_tx_cfg[idx].bit_format,
  2950. ucontrol->value.enumerated.item[0]);
  2951. return 0;
  2952. }
  2953. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2954. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2955. slim_rx_ch_get, slim_rx_ch_put),
  2956. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2957. slim_rx_ch_get, slim_rx_ch_put),
  2958. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2959. slim_tx_ch_get, slim_tx_ch_put),
  2960. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2961. slim_tx_ch_get, slim_tx_ch_put),
  2962. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2963. slim_rx_ch_get, slim_rx_ch_put),
  2964. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2965. slim_rx_ch_get, slim_rx_ch_put),
  2966. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2967. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2968. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2969. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2970. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2971. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2972. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2973. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2974. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2975. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2976. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2977. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2979. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2980. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2981. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2982. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2983. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2984. };
  2985. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2986. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2987. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2988. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2989. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2990. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2991. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2992. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2993. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2994. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2995. va_cdc_dma_tx_0_sample_rate,
  2996. cdc_dma_tx_sample_rate_get,
  2997. cdc_dma_tx_sample_rate_put),
  2998. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2999. va_cdc_dma_tx_1_sample_rate,
  3000. cdc_dma_tx_sample_rate_get,
  3001. cdc_dma_tx_sample_rate_put),
  3002. };
  3003. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3004. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3005. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3006. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3007. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3008. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3009. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3010. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3011. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3012. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3013. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3014. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3015. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3016. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3017. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3018. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3019. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3020. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3021. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3022. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3023. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3024. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3025. wsa_cdc_dma_rx_0_sample_rate,
  3026. cdc_dma_rx_sample_rate_get,
  3027. cdc_dma_rx_sample_rate_put),
  3028. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3029. wsa_cdc_dma_rx_1_sample_rate,
  3030. cdc_dma_rx_sample_rate_get,
  3031. cdc_dma_rx_sample_rate_put),
  3032. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3033. wsa_cdc_dma_tx_0_sample_rate,
  3034. cdc_dma_tx_sample_rate_get,
  3035. cdc_dma_tx_sample_rate_put),
  3036. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3037. wsa_cdc_dma_tx_1_sample_rate,
  3038. cdc_dma_tx_sample_rate_get,
  3039. cdc_dma_tx_sample_rate_put),
  3040. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3041. wsa_cdc_dma_tx_2_sample_rate,
  3042. cdc_dma_tx_sample_rate_get,
  3043. cdc_dma_tx_sample_rate_put),
  3044. };
  3045. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3046. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3047. msm_bt_sample_rate_sink_get,
  3048. msm_bt_sample_rate_sink_put),
  3049. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3050. msm_bt_sample_rate_get,
  3051. msm_bt_sample_rate_put),
  3052. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3053. msm_bt_sample_rate_get,
  3054. msm_bt_sample_rate_put),
  3055. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3056. proxy_rx_ch_get, proxy_rx_ch_put),
  3057. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3058. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3059. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3060. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3061. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3062. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3063. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3064. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3065. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3066. usb_audio_rx_sample_rate_get,
  3067. usb_audio_rx_sample_rate_put),
  3068. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3069. usb_audio_tx_sample_rate_get,
  3070. usb_audio_tx_sample_rate_put),
  3071. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3072. tdm_rx_sample_rate_get,
  3073. tdm_rx_sample_rate_put),
  3074. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3075. tdm_tx_sample_rate_get,
  3076. tdm_tx_sample_rate_put),
  3077. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3078. tdm_rx_format_get,
  3079. tdm_rx_format_put),
  3080. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3081. tdm_tx_format_get,
  3082. tdm_tx_format_put),
  3083. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3084. tdm_rx_ch_get,
  3085. tdm_rx_ch_put),
  3086. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3087. tdm_tx_ch_get,
  3088. tdm_tx_ch_put),
  3089. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3090. tdm_rx_sample_rate_get,
  3091. tdm_rx_sample_rate_put),
  3092. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3093. tdm_tx_sample_rate_get,
  3094. tdm_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3096. tdm_rx_format_get,
  3097. tdm_rx_format_put),
  3098. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3099. tdm_tx_format_get,
  3100. tdm_tx_format_put),
  3101. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3102. tdm_rx_ch_get,
  3103. tdm_rx_ch_put),
  3104. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3105. tdm_tx_ch_get,
  3106. tdm_tx_ch_put),
  3107. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3108. tdm_rx_sample_rate_get,
  3109. tdm_rx_sample_rate_put),
  3110. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3111. tdm_tx_sample_rate_get,
  3112. tdm_tx_sample_rate_put),
  3113. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3114. tdm_rx_format_get,
  3115. tdm_rx_format_put),
  3116. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3117. tdm_tx_format_get,
  3118. tdm_tx_format_put),
  3119. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3120. tdm_rx_ch_get,
  3121. tdm_rx_ch_put),
  3122. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3123. tdm_tx_ch_get,
  3124. tdm_tx_ch_put),
  3125. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3126. tdm_rx_sample_rate_get,
  3127. tdm_rx_sample_rate_put),
  3128. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3129. tdm_tx_sample_rate_get,
  3130. tdm_tx_sample_rate_put),
  3131. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3132. tdm_rx_format_get,
  3133. tdm_rx_format_put),
  3134. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3135. tdm_tx_format_get,
  3136. tdm_tx_format_put),
  3137. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3138. tdm_rx_ch_get,
  3139. tdm_rx_ch_put),
  3140. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3141. tdm_tx_ch_get,
  3142. tdm_tx_ch_put),
  3143. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3144. tdm_rx_sample_rate_get,
  3145. tdm_rx_sample_rate_put),
  3146. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3147. tdm_tx_sample_rate_get,
  3148. tdm_tx_sample_rate_put),
  3149. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3150. tdm_rx_format_get,
  3151. tdm_rx_format_put),
  3152. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3153. tdm_tx_format_get,
  3154. tdm_tx_format_put),
  3155. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3156. tdm_rx_ch_get,
  3157. tdm_rx_ch_put),
  3158. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3159. tdm_tx_ch_get,
  3160. tdm_tx_ch_put),
  3161. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3162. aux_pcm_rx_sample_rate_get,
  3163. aux_pcm_rx_sample_rate_put),
  3164. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3165. aux_pcm_rx_sample_rate_get,
  3166. aux_pcm_rx_sample_rate_put),
  3167. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3168. aux_pcm_rx_sample_rate_get,
  3169. aux_pcm_rx_sample_rate_put),
  3170. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3171. aux_pcm_rx_sample_rate_get,
  3172. aux_pcm_rx_sample_rate_put),
  3173. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3174. aux_pcm_rx_sample_rate_get,
  3175. aux_pcm_rx_sample_rate_put),
  3176. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3177. aux_pcm_tx_sample_rate_get,
  3178. aux_pcm_tx_sample_rate_put),
  3179. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3180. aux_pcm_tx_sample_rate_get,
  3181. aux_pcm_tx_sample_rate_put),
  3182. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3183. aux_pcm_tx_sample_rate_get,
  3184. aux_pcm_tx_sample_rate_put),
  3185. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3186. aux_pcm_tx_sample_rate_get,
  3187. aux_pcm_tx_sample_rate_put),
  3188. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3189. aux_pcm_tx_sample_rate_get,
  3190. aux_pcm_tx_sample_rate_put),
  3191. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3192. aux_pcm_tx_sample_rate_get,
  3193. aux_pcm_tx_sample_rate_put),
  3194. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3195. mi2s_rx_sample_rate_get,
  3196. mi2s_rx_sample_rate_put),
  3197. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3198. mi2s_rx_sample_rate_get,
  3199. mi2s_rx_sample_rate_put),
  3200. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3201. mi2s_rx_sample_rate_get,
  3202. mi2s_rx_sample_rate_put),
  3203. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3204. mi2s_rx_sample_rate_get,
  3205. mi2s_rx_sample_rate_put),
  3206. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3207. mi2s_rx_sample_rate_get,
  3208. mi2s_rx_sample_rate_put),
  3209. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3210. mi2s_rx_sample_rate_get,
  3211. mi2s_rx_sample_rate_put),
  3212. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3213. mi2s_tx_sample_rate_get,
  3214. mi2s_tx_sample_rate_put),
  3215. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3216. mi2s_tx_sample_rate_get,
  3217. mi2s_tx_sample_rate_put),
  3218. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3219. mi2s_tx_sample_rate_get,
  3220. mi2s_tx_sample_rate_put),
  3221. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3222. mi2s_tx_sample_rate_get,
  3223. mi2s_tx_sample_rate_put),
  3224. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3225. mi2s_tx_sample_rate_get,
  3226. mi2s_tx_sample_rate_put),
  3227. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3228. mi2s_tx_sample_rate_get,
  3229. mi2s_tx_sample_rate_put),
  3230. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3231. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3232. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3233. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3234. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3235. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3236. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3237. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3238. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3239. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3240. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3241. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3242. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3243. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3244. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3245. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3246. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3247. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3248. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3249. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3250. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3251. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3252. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3253. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3254. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3255. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3256. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3257. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3258. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3259. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3260. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3261. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3262. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3263. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3264. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3265. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3266. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3267. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3268. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3269. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3270. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3271. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3272. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3273. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3274. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3275. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3276. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3277. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3278. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3279. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3280. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3281. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3282. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3283. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3284. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3285. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3286. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3287. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3288. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3289. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3290. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3291. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3292. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3293. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3294. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3295. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3296. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3297. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3298. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3299. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3300. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3301. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3302. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3303. msm_snd_vad_cfg_put),
  3304. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3305. msm_spdif_rx_sample_rate_get,
  3306. msm_spdif_rx_sample_rate_put),
  3307. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3308. msm_spdif_tx_sample_rate_get,
  3309. msm_spdif_tx_sample_rate_put),
  3310. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3311. msm_spdif_rx_sample_rate_get,
  3312. msm_spdif_rx_sample_rate_put),
  3313. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3314. msm_spdif_tx_sample_rate_get,
  3315. msm_spdif_tx_sample_rate_put),
  3316. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3317. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3318. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3319. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3320. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3321. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3322. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3323. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3324. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3325. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3326. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3327. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3328. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3329. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3330. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3331. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3332. };
  3333. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3334. int enable, bool dapm)
  3335. {
  3336. int ret = 0;
  3337. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3338. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3339. } else {
  3340. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3341. __func__);
  3342. ret = -EINVAL;
  3343. }
  3344. return ret;
  3345. }
  3346. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3347. int enable, bool dapm)
  3348. {
  3349. int ret = 0;
  3350. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3351. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3352. } else {
  3353. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3354. __func__);
  3355. ret = -EINVAL;
  3356. }
  3357. return ret;
  3358. }
  3359. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3360. struct snd_kcontrol *kcontrol, int event)
  3361. {
  3362. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3363. pr_debug("%s: event = %d\n", __func__, event);
  3364. switch (event) {
  3365. case SND_SOC_DAPM_PRE_PMU:
  3366. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3367. case SND_SOC_DAPM_POST_PMD:
  3368. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3369. }
  3370. return 0;
  3371. }
  3372. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3373. struct snd_kcontrol *kcontrol, int event)
  3374. {
  3375. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3376. pr_debug("%s: event = %d\n", __func__, event);
  3377. switch (event) {
  3378. case SND_SOC_DAPM_PRE_PMU:
  3379. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3380. case SND_SOC_DAPM_POST_PMD:
  3381. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3382. }
  3383. return 0;
  3384. }
  3385. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3386. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3387. msm_mclk_event,
  3388. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3389. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3390. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3391. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3392. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3393. };
  3394. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3395. struct snd_kcontrol *kcontrol, int event)
  3396. {
  3397. struct msm_asoc_mach_data *pdata = NULL;
  3398. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3399. int ret = 0;
  3400. uint32_t dmic_idx;
  3401. int *dmic_gpio_cnt;
  3402. struct device_node *dmic_gpio;
  3403. char *wname;
  3404. wname = strpbrk(w->name, "01234567");
  3405. if (!wname) {
  3406. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3407. return -EINVAL;
  3408. }
  3409. ret = kstrtouint(wname, 10, &dmic_idx);
  3410. if (ret < 0) {
  3411. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3412. __func__);
  3413. return -EINVAL;
  3414. }
  3415. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3416. switch (dmic_idx) {
  3417. case 0:
  3418. case 1:
  3419. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3420. dmic_gpio = pdata->dmic_01_gpio_p;
  3421. break;
  3422. case 2:
  3423. case 3:
  3424. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3425. dmic_gpio = pdata->dmic_23_gpio_p;
  3426. break;
  3427. case 4:
  3428. case 5:
  3429. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3430. dmic_gpio = pdata->dmic_45_gpio_p;
  3431. break;
  3432. case 6:
  3433. case 7:
  3434. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3435. dmic_gpio = pdata->dmic_67_gpio_p;
  3436. break;
  3437. default:
  3438. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3439. __func__);
  3440. return -EINVAL;
  3441. }
  3442. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3443. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3444. switch (event) {
  3445. case SND_SOC_DAPM_PRE_PMU:
  3446. (*dmic_gpio_cnt)++;
  3447. if (*dmic_gpio_cnt == 1) {
  3448. ret = msm_cdc_pinctrl_select_active_state(
  3449. dmic_gpio);
  3450. if (ret < 0) {
  3451. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3452. __func__, "dmic_gpio");
  3453. return ret;
  3454. }
  3455. }
  3456. break;
  3457. case SND_SOC_DAPM_POST_PMD:
  3458. (*dmic_gpio_cnt)--;
  3459. if (*dmic_gpio_cnt == 0) {
  3460. ret = msm_cdc_pinctrl_select_sleep_state(
  3461. dmic_gpio);
  3462. if (ret < 0) {
  3463. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3464. __func__, "dmic_gpio");
  3465. return ret;
  3466. }
  3467. }
  3468. break;
  3469. default:
  3470. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3471. __func__, event);
  3472. return -EINVAL;
  3473. }
  3474. return 0;
  3475. }
  3476. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3477. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3478. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3479. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3480. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3481. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3482. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3483. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3484. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3485. };
  3486. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3487. };
  3488. static inline int param_is_mask(int p)
  3489. {
  3490. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3491. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3492. }
  3493. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3494. int n)
  3495. {
  3496. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3497. }
  3498. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3499. unsigned int bit)
  3500. {
  3501. if (bit >= SNDRV_MASK_MAX)
  3502. return;
  3503. if (param_is_mask(n)) {
  3504. struct snd_mask *m = param_to_mask(p, n);
  3505. m->bits[0] = 0;
  3506. m->bits[1] = 0;
  3507. m->bits[bit >> 5] |= (1 << (bit & 31));
  3508. }
  3509. }
  3510. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3511. {
  3512. int ch_id = 0;
  3513. switch (be_id) {
  3514. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3515. ch_id = SLIM_RX_0;
  3516. break;
  3517. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3518. ch_id = SLIM_RX_1;
  3519. break;
  3520. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3521. ch_id = SLIM_RX_2;
  3522. break;
  3523. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3524. ch_id = SLIM_RX_3;
  3525. break;
  3526. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3527. ch_id = SLIM_RX_4;
  3528. break;
  3529. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3530. ch_id = SLIM_RX_6;
  3531. break;
  3532. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3533. ch_id = SLIM_TX_0;
  3534. break;
  3535. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3536. ch_id = SLIM_TX_3;
  3537. break;
  3538. default:
  3539. ch_id = SLIM_RX_0;
  3540. break;
  3541. }
  3542. return ch_id;
  3543. }
  3544. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3545. {
  3546. *port_id = 0xFFFF;
  3547. switch (be_id) {
  3548. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3549. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3550. break;
  3551. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3552. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3553. break;
  3554. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3555. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3556. break;
  3557. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3558. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3559. break;
  3560. default:
  3561. return -EINVAL;
  3562. }
  3563. return 0;
  3564. }
  3565. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3566. {
  3567. int idx = 0;
  3568. switch (be_id) {
  3569. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3570. idx = WSA_CDC_DMA_RX_0;
  3571. break;
  3572. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3573. idx = WSA_CDC_DMA_TX_0;
  3574. break;
  3575. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3576. idx = WSA_CDC_DMA_RX_1;
  3577. break;
  3578. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3579. idx = WSA_CDC_DMA_TX_1;
  3580. break;
  3581. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3582. idx = WSA_CDC_DMA_TX_2;
  3583. break;
  3584. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3585. idx = VA_CDC_DMA_TX_0;
  3586. break;
  3587. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3588. idx = VA_CDC_DMA_TX_1;
  3589. break;
  3590. default:
  3591. idx = VA_CDC_DMA_TX_0;
  3592. break;
  3593. }
  3594. return idx;
  3595. }
  3596. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3597. struct snd_pcm_hw_params *params)
  3598. {
  3599. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3600. struct snd_interval *rate = hw_param_interval(params,
  3601. SNDRV_PCM_HW_PARAM_RATE);
  3602. struct snd_interval *channels = hw_param_interval(params,
  3603. SNDRV_PCM_HW_PARAM_CHANNELS);
  3604. int rc = 0;
  3605. int idx;
  3606. void *config = NULL;
  3607. struct snd_soc_codec *codec = NULL;
  3608. pr_debug("%s: format = %d, rate = %d\n",
  3609. __func__, params_format(params), params_rate(params));
  3610. switch (dai_link->id) {
  3611. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3612. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3613. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3614. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3615. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3616. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3617. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3618. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3619. slim_rx_cfg[idx].bit_format);
  3620. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3621. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3622. break;
  3623. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3624. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3625. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3626. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3627. slim_tx_cfg[idx].bit_format);
  3628. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3629. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3630. break;
  3631. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3632. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3633. slim_tx_cfg[1].bit_format);
  3634. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3635. channels->min = channels->max = slim_tx_cfg[1].channels;
  3636. break;
  3637. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3638. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3639. SNDRV_PCM_FORMAT_S32_LE);
  3640. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3641. channels->min = channels->max = msm_vi_feed_tx_ch;
  3642. break;
  3643. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3644. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3645. slim_rx_cfg[5].bit_format);
  3646. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3647. channels->min = channels->max = slim_rx_cfg[5].channels;
  3648. break;
  3649. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3650. codec = rtd->codec;
  3651. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3652. channels->min = channels->max = 1;
  3653. config = msm_codec_fn.get_afe_config_fn(codec,
  3654. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3655. if (config) {
  3656. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3657. config, SLIMBUS_5_TX);
  3658. if (rc)
  3659. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3660. __func__, rc);
  3661. }
  3662. break;
  3663. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3664. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3665. slim_rx_cfg[SLIM_RX_7].bit_format);
  3666. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3667. channels->min = channels->max =
  3668. slim_rx_cfg[SLIM_RX_7].channels;
  3669. break;
  3670. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3671. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3672. channels->min = channels->max =
  3673. slim_tx_cfg[SLIM_TX_7].channels;
  3674. break;
  3675. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3676. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3677. channels->min = channels->max =
  3678. slim_tx_cfg[SLIM_TX_8].channels;
  3679. break;
  3680. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3681. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3682. slim_tx_cfg[SLIM_TX_9].bit_format);
  3683. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3684. channels->min = channels->max =
  3685. slim_tx_cfg[SLIM_TX_9].channels;
  3686. break;
  3687. case MSM_BACKEND_DAI_USB_RX:
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. usb_rx_cfg.bit_format);
  3690. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3691. channels->min = channels->max = usb_rx_cfg.channels;
  3692. break;
  3693. case MSM_BACKEND_DAI_USB_TX:
  3694. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3695. usb_tx_cfg.bit_format);
  3696. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3697. channels->min = channels->max = usb_tx_cfg.channels;
  3698. break;
  3699. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3700. channels->min = channels->max = proxy_rx_cfg.channels;
  3701. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3702. break;
  3703. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3704. channels->min = channels->max =
  3705. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3706. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3707. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3708. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3709. break;
  3710. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3711. channels->min = channels->max =
  3712. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3713. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3714. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3715. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3716. break;
  3717. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3718. channels->min = channels->max =
  3719. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3720. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3721. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3722. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3723. break;
  3724. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3725. channels->min = channels->max =
  3726. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3727. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3728. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3729. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3730. break;
  3731. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3732. channels->min = channels->max =
  3733. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3734. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3735. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3736. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3737. break;
  3738. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3739. channels->min = channels->max =
  3740. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3741. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3742. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3743. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3744. break;
  3745. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3746. channels->min = channels->max =
  3747. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3748. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3749. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3750. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3751. break;
  3752. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3753. channels->min = channels->max =
  3754. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3755. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3756. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3757. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3758. break;
  3759. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3760. channels->min = channels->max =
  3761. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3762. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3763. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3764. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3765. break;
  3766. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3767. channels->min = channels->max =
  3768. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3769. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3770. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3771. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3772. break;
  3773. case MSM_BACKEND_DAI_AUXPCM_RX:
  3774. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3775. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3776. rate->min = rate->max =
  3777. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3778. channels->min = channels->max =
  3779. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3780. break;
  3781. case MSM_BACKEND_DAI_AUXPCM_TX:
  3782. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3783. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3784. rate->min = rate->max =
  3785. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3786. channels->min = channels->max =
  3787. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3788. break;
  3789. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3790. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3791. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3792. rate->min = rate->max =
  3793. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3794. channels->min = channels->max =
  3795. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3796. break;
  3797. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3798. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3799. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3800. rate->min = rate->max =
  3801. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3802. channels->min = channels->max =
  3803. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3804. break;
  3805. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3806. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3807. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3808. rate->min = rate->max =
  3809. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3810. channels->min = channels->max =
  3811. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3812. break;
  3813. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3814. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3815. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3816. rate->min = rate->max =
  3817. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3818. channels->min = channels->max =
  3819. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3820. break;
  3821. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3822. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3823. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3824. rate->min = rate->max =
  3825. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3826. channels->min = channels->max =
  3827. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3828. break;
  3829. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3830. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3831. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3832. rate->min = rate->max =
  3833. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3834. channels->min = channels->max =
  3835. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3836. break;
  3837. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3838. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3839. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3840. rate->min = rate->max =
  3841. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3842. channels->min = channels->max =
  3843. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3844. break;
  3845. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3846. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3847. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3848. rate->min = rate->max =
  3849. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3850. channels->min = channels->max =
  3851. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3852. break;
  3853. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3854. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3855. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3856. rate->min = rate->max =
  3857. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3858. channels->min = channels->max =
  3859. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3860. break;
  3861. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3862. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3863. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3864. rate->min = rate->max =
  3865. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3866. channels->min = channels->max =
  3867. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3868. break;
  3869. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3870. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3871. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3872. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3873. channels->min = channels->max =
  3874. mi2s_rx_cfg[PRIM_MI2S].channels;
  3875. break;
  3876. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3877. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3878. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3879. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3880. channels->min = channels->max =
  3881. mi2s_tx_cfg[PRIM_MI2S].channels;
  3882. break;
  3883. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3884. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3885. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3886. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3887. channels->min = channels->max =
  3888. mi2s_rx_cfg[SEC_MI2S].channels;
  3889. break;
  3890. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3891. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3892. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3893. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3894. channels->min = channels->max =
  3895. mi2s_tx_cfg[SEC_MI2S].channels;
  3896. break;
  3897. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3898. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3899. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3900. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3901. channels->min = channels->max =
  3902. mi2s_rx_cfg[TERT_MI2S].channels;
  3903. break;
  3904. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3905. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3906. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3907. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3908. channels->min = channels->max =
  3909. mi2s_tx_cfg[TERT_MI2S].channels;
  3910. break;
  3911. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3912. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3913. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3914. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3915. channels->min = channels->max =
  3916. mi2s_rx_cfg[QUAT_MI2S].channels;
  3917. break;
  3918. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3919. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3920. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3921. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3922. channels->min = channels->max =
  3923. mi2s_tx_cfg[QUAT_MI2S].channels;
  3924. break;
  3925. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3926. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3927. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3928. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3929. channels->min = channels->max =
  3930. mi2s_rx_cfg[QUIN_MI2S].channels;
  3931. break;
  3932. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3933. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3934. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3935. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3936. channels->min = channels->max =
  3937. mi2s_tx_cfg[QUIN_MI2S].channels;
  3938. break;
  3939. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3940. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3941. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3942. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3943. channels->min = channels->max =
  3944. mi2s_rx_cfg[SEN_MI2S].channels;
  3945. break;
  3946. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3947. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3948. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3949. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3950. channels->min = channels->max =
  3951. mi2s_tx_cfg[SEN_MI2S].channels;
  3952. break;
  3953. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3954. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3955. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3956. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3957. cdc_dma_rx_cfg[idx].bit_format);
  3958. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3959. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3960. break;
  3961. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3962. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3963. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3964. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3965. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3966. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3967. cdc_dma_tx_cfg[idx].bit_format);
  3968. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3969. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3970. break;
  3971. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3972. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3973. SNDRV_PCM_FORMAT_S32_LE);
  3974. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3975. channels->min = channels->max = msm_vi_feed_tx_ch;
  3976. break;
  3977. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3978. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3979. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3980. rate->min = rate->max =
  3981. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3982. channels->min = channels->max =
  3983. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3984. break;
  3985. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3986. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3987. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3988. rate->min = rate->max =
  3989. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3990. channels->min = channels->max =
  3991. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3992. break;
  3993. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3994. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3995. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3996. rate->min = rate->max =
  3997. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3998. channels->min = channels->max =
  3999. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4000. break;
  4001. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4002. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4003. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4004. rate->min = rate->max =
  4005. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4006. channels->min = channels->max =
  4007. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4008. break;
  4009. default:
  4010. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4011. break;
  4012. }
  4013. return rc;
  4014. }
  4015. static int msm_afe_set_config(struct snd_soc_codec *codec)
  4016. {
  4017. int ret = 0;
  4018. void *config_data = NULL;
  4019. if (!msm_codec_fn.get_afe_config_fn) {
  4020. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  4021. __func__);
  4022. return -EINVAL;
  4023. }
  4024. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4025. AFE_CDC_REGISTERS_CONFIG);
  4026. if (config_data) {
  4027. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4028. if (ret) {
  4029. dev_err(codec->dev,
  4030. "%s: Failed to set codec registers config %d\n",
  4031. __func__, ret);
  4032. return ret;
  4033. }
  4034. }
  4035. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4036. AFE_CDC_REGISTER_PAGE_CONFIG);
  4037. if (config_data) {
  4038. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4039. 0);
  4040. if (ret)
  4041. dev_err(codec->dev,
  4042. "%s: Failed to set cdc register page config\n",
  4043. __func__);
  4044. }
  4045. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4046. AFE_SLIMBUS_SLAVE_CONFIG);
  4047. if (config_data) {
  4048. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4049. if (ret) {
  4050. dev_err(codec->dev,
  4051. "%s: Failed to set slimbus slave config %d\n",
  4052. __func__, ret);
  4053. return ret;
  4054. }
  4055. }
  4056. return 0;
  4057. }
  4058. static void msm_afe_clear_config(void)
  4059. {
  4060. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4061. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4062. }
  4063. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  4064. struct snd_card *card)
  4065. {
  4066. int ret = 0;
  4067. unsigned long timeout;
  4068. int adsp_ready = 0;
  4069. bool snd_card_online = 0;
  4070. timeout = jiffies +
  4071. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4072. do {
  4073. if (!snd_card_online) {
  4074. snd_card_online = snd_card_is_online_state(card);
  4075. pr_debug("%s: Sound card is %s\n", __func__,
  4076. snd_card_online ? "Online" : "Offline");
  4077. }
  4078. if (!adsp_ready) {
  4079. adsp_ready = q6core_is_adsp_ready();
  4080. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4081. adsp_ready ? "ready" : "not ready");
  4082. }
  4083. if (snd_card_online && adsp_ready)
  4084. break;
  4085. /*
  4086. * Sound card/ADSP will be coming up after subsystem restart and
  4087. * it might not be fully up when the control reaches
  4088. * here. So, wait for 50msec before checking ADSP state
  4089. */
  4090. msleep(50);
  4091. } while (time_after(timeout, jiffies));
  4092. if (!snd_card_online || !adsp_ready) {
  4093. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4094. __func__,
  4095. snd_card_online ? "Online" : "Offline",
  4096. adsp_ready ? "ready" : "not ready");
  4097. ret = -ETIMEDOUT;
  4098. goto err;
  4099. }
  4100. ret = msm_afe_set_config(codec);
  4101. if (ret)
  4102. pr_err("%s: Failed to set AFE config. err %d\n",
  4103. __func__, ret);
  4104. return 0;
  4105. err:
  4106. return ret;
  4107. }
  4108. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4109. unsigned long opcode, void *ptr)
  4110. {
  4111. int ret;
  4112. struct snd_soc_card *card = NULL;
  4113. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4114. struct snd_soc_pcm_runtime *rtd;
  4115. struct snd_soc_codec *codec;
  4116. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4117. switch (opcode) {
  4118. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4119. /*
  4120. * Use flag to ignore initial boot notifications
  4121. * On initial boot msm_adsp_power_up_config is
  4122. * called on init. There is no need to clear
  4123. * and set the config again on initial boot.
  4124. */
  4125. if (is_initial_boot)
  4126. break;
  4127. msm_afe_clear_config();
  4128. break;
  4129. case AUDIO_NOTIFIER_SERVICE_UP:
  4130. if (is_initial_boot) {
  4131. is_initial_boot = false;
  4132. break;
  4133. }
  4134. if (!spdev)
  4135. return -EINVAL;
  4136. card = platform_get_drvdata(spdev);
  4137. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4138. if (!rtd) {
  4139. dev_err(card->dev,
  4140. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4141. __func__, be_dl_name);
  4142. ret = -EINVAL;
  4143. goto err;
  4144. }
  4145. codec = rtd->codec;
  4146. ret = msm_adsp_power_up_config(codec, card->snd_card);
  4147. if (ret < 0) {
  4148. dev_err(card->dev,
  4149. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4150. __func__, ret);
  4151. goto err;
  4152. }
  4153. break;
  4154. default:
  4155. break;
  4156. }
  4157. err:
  4158. return NOTIFY_OK;
  4159. }
  4160. static struct notifier_block service_nb = {
  4161. .notifier_call = qcs405_notifier_service_cb,
  4162. .priority = -INT_MAX,
  4163. };
  4164. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4165. {
  4166. int ret = 0;
  4167. void *config_data;
  4168. struct snd_soc_codec *codec = rtd->codec;
  4169. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4170. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4171. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4172. struct snd_card *card;
  4173. struct msm_asoc_mach_data *pdata =
  4174. snd_soc_card_get_drvdata(rtd->card);
  4175. /*
  4176. * Codec SLIMBUS configuration
  4177. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4178. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4179. * TX14, TX15, TX16
  4180. */
  4181. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4182. 151, 152, 153, 154, 155, 156};
  4183. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4184. 134, 135, 136, 137, 138, 139,
  4185. 140, 141, 142, 143};
  4186. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4187. rtd->pmdown_time = 0;
  4188. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4189. ARRAY_SIZE(msm_snd_sb_controls));
  4190. if (ret < 0) {
  4191. pr_err("%s: add_codec_controls failed, err %d\n",
  4192. __func__, ret);
  4193. return ret;
  4194. }
  4195. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4196. ARRAY_SIZE(msm_dapm_widgets));
  4197. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4198. ARRAY_SIZE(wcd_audio_paths));
  4199. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4200. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4201. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4202. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4203. snd_soc_dapm_sync(dapm);
  4204. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4205. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4206. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4207. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4208. if (ret) {
  4209. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4210. __func__, ret);
  4211. goto err;
  4212. }
  4213. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4214. AFE_AANC_VERSION);
  4215. if (config_data) {
  4216. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4217. if (ret) {
  4218. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4219. __func__, ret);
  4220. goto err;
  4221. }
  4222. }
  4223. card = rtd->card->snd_card;
  4224. if (!pdata->codec_root)
  4225. pdata->codec_root = snd_info_create_subdir(card->module,
  4226. "codecs", card->proc_root);
  4227. if (!pdata->codec_root) {
  4228. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4229. __func__);
  4230. ret = 0;
  4231. goto err;
  4232. }
  4233. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4234. codec_reg_done = true;
  4235. return 0;
  4236. err:
  4237. return ret;
  4238. }
  4239. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4240. {
  4241. int ret = 0;
  4242. struct snd_soc_codec *codec = rtd->codec;
  4243. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4244. struct snd_card *card;
  4245. struct msm_asoc_mach_data *pdata =
  4246. snd_soc_card_get_drvdata(rtd->card);
  4247. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4248. ARRAY_SIZE(msm_snd_va_controls));
  4249. if (ret < 0) {
  4250. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4251. __func__, ret);
  4252. return ret;
  4253. }
  4254. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4255. ARRAY_SIZE(msm_va_dapm_widgets));
  4256. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4257. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4258. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4259. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4260. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4261. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4262. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4263. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4264. snd_soc_dapm_sync(dapm);
  4265. card = rtd->card->snd_card;
  4266. if (!pdata->codec_root)
  4267. pdata->codec_root = snd_info_create_subdir(card->module,
  4268. "codecs", card->proc_root);
  4269. if (!pdata->codec_root) {
  4270. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4271. __func__);
  4272. ret = 0;
  4273. goto done;
  4274. }
  4275. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4276. done:
  4277. return ret;
  4278. }
  4279. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4280. {
  4281. int ret = 0;
  4282. struct snd_soc_codec *codec = rtd->codec;
  4283. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4284. struct snd_soc_component *aux_comp;
  4285. struct snd_card *card;
  4286. struct msm_asoc_mach_data *pdata =
  4287. snd_soc_card_get_drvdata(rtd->card);
  4288. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4289. ARRAY_SIZE(msm_snd_wsa_controls));
  4290. if (ret < 0) {
  4291. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4292. __func__, ret);
  4293. return ret;
  4294. }
  4295. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4296. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4297. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4298. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4299. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4300. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4301. snd_soc_dapm_sync(dapm);
  4302. /*
  4303. * Send speaker configuration only for WSA8810.
  4304. * Default configuration is for WSA8815.
  4305. */
  4306. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4307. __func__, rtd->card->num_aux_devs);
  4308. if (rtd->card->num_aux_devs &&
  4309. !list_empty(&rtd->card->component_dev_list)) {
  4310. aux_comp = list_first_entry(
  4311. &rtd->card->component_dev_list,
  4312. struct snd_soc_component,
  4313. card_aux_list);
  4314. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4315. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4316. wsa_macro_set_spkr_mode(rtd->codec,
  4317. WSA_MACRO_SPKR_MODE_1);
  4318. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4319. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4320. }
  4321. }
  4322. card = rtd->card->snd_card;
  4323. if (!pdata->codec_root)
  4324. pdata->codec_root = snd_info_create_subdir(card->module,
  4325. "codecs", card->proc_root);
  4326. if (!pdata->codec_root) {
  4327. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4328. __func__);
  4329. ret = 0;
  4330. goto done;
  4331. }
  4332. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4333. done:
  4334. return ret;
  4335. }
  4336. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4337. {
  4338. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4339. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4340. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4341. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4342. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4343. }
  4344. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4345. struct snd_pcm_hw_params *params)
  4346. {
  4347. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4348. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4349. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4350. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4351. int ret = 0;
  4352. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4353. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4354. u32 user_set_tx_ch = 0;
  4355. u32 rx_ch_count;
  4356. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4357. ret = snd_soc_dai_get_channel_map(codec_dai,
  4358. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4359. if (ret < 0) {
  4360. pr_err("%s: failed to get codec chan map, err:%d\n",
  4361. __func__, ret);
  4362. goto err;
  4363. }
  4364. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4365. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4366. slim_rx_cfg[5].channels);
  4367. rx_ch_count = slim_rx_cfg[5].channels;
  4368. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4369. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4370. slim_rx_cfg[2].channels);
  4371. rx_ch_count = slim_rx_cfg[2].channels;
  4372. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4373. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4374. slim_rx_cfg[6].channels);
  4375. rx_ch_count = slim_rx_cfg[6].channels;
  4376. } else {
  4377. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4378. slim_rx_cfg[0].channels);
  4379. rx_ch_count = slim_rx_cfg[0].channels;
  4380. }
  4381. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4382. rx_ch_count, rx_ch);
  4383. if (ret < 0) {
  4384. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4385. __func__, ret);
  4386. goto err;
  4387. }
  4388. } else {
  4389. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4390. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4391. ret = snd_soc_dai_get_channel_map(codec_dai,
  4392. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4393. if (ret < 0) {
  4394. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4395. __func__, ret);
  4396. goto err;
  4397. }
  4398. /* For <codec>_tx1 case */
  4399. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4400. user_set_tx_ch = slim_tx_cfg[0].channels;
  4401. /* For <codec>_tx3 case */
  4402. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4403. user_set_tx_ch = slim_tx_cfg[1].channels;
  4404. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4405. user_set_tx_ch = msm_vi_feed_tx_ch;
  4406. else
  4407. user_set_tx_ch = tx_ch_cnt;
  4408. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4409. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4410. tx_ch_cnt, dai_link->id);
  4411. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4412. user_set_tx_ch, tx_ch, 0, 0);
  4413. if (ret < 0)
  4414. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4415. __func__, ret);
  4416. }
  4417. err:
  4418. return ret;
  4419. }
  4420. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4421. struct snd_pcm_hw_params *params)
  4422. {
  4423. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4424. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4425. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4426. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4427. int ret = 0;
  4428. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4429. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4430. u32 user_set_tx_ch = 0;
  4431. u32 user_set_rx_ch = 0;
  4432. u32 ch_id;
  4433. ret = snd_soc_dai_get_channel_map(codec_dai,
  4434. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4435. &rx_ch_cdc_dma);
  4436. if (ret < 0) {
  4437. pr_err("%s: failed to get codec chan map, err:%d\n",
  4438. __func__, ret);
  4439. goto err;
  4440. }
  4441. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4442. switch (dai_link->id) {
  4443. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4444. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4445. {
  4446. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4447. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4448. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4449. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4450. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4451. user_set_rx_ch, &rx_ch_cdc_dma);
  4452. if (ret < 0) {
  4453. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4454. __func__, ret);
  4455. goto err;
  4456. }
  4457. }
  4458. break;
  4459. }
  4460. } else {
  4461. switch (dai_link->id) {
  4462. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4463. {
  4464. user_set_tx_ch = msm_vi_feed_tx_ch;
  4465. }
  4466. break;
  4467. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4468. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4469. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4470. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4471. {
  4472. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4473. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4474. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4475. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4476. }
  4477. break;
  4478. }
  4479. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4480. &tx_ch_cdc_dma, 0, 0);
  4481. if (ret < 0) {
  4482. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4483. __func__, ret);
  4484. goto err;
  4485. }
  4486. }
  4487. err:
  4488. return ret;
  4489. }
  4490. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4491. struct snd_pcm_hw_params *params)
  4492. {
  4493. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4494. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4495. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4496. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4497. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4498. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4499. int ret;
  4500. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4501. codec_dai->name, codec_dai->id);
  4502. ret = snd_soc_dai_get_channel_map(codec_dai,
  4503. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4504. if (ret) {
  4505. dev_err(rtd->dev,
  4506. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4507. __func__, ret);
  4508. goto err;
  4509. }
  4510. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4511. __func__, tx_ch_cnt, dai_link->id);
  4512. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4513. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4514. if (ret)
  4515. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4516. __func__, ret);
  4517. err:
  4518. return ret;
  4519. }
  4520. static int msm_get_port_id(int be_id)
  4521. {
  4522. int afe_port_id;
  4523. switch (be_id) {
  4524. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4525. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4526. break;
  4527. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4528. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4529. break;
  4530. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4531. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4532. break;
  4533. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4534. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4535. break;
  4536. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4537. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4538. break;
  4539. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4540. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4541. break;
  4542. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4543. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4544. break;
  4545. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4546. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4547. break;
  4548. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4549. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4550. break;
  4551. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4552. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4553. break;
  4554. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4555. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4556. break;
  4557. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4558. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4559. break;
  4560. default:
  4561. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4562. afe_port_id = -EINVAL;
  4563. }
  4564. return afe_port_id;
  4565. }
  4566. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4567. {
  4568. u32 bit_per_sample;
  4569. switch (bit_format) {
  4570. case SNDRV_PCM_FORMAT_S32_LE:
  4571. case SNDRV_PCM_FORMAT_S24_3LE:
  4572. case SNDRV_PCM_FORMAT_S24_LE:
  4573. bit_per_sample = 32;
  4574. break;
  4575. case SNDRV_PCM_FORMAT_S16_LE:
  4576. default:
  4577. bit_per_sample = 16;
  4578. break;
  4579. }
  4580. return bit_per_sample;
  4581. }
  4582. static void update_mi2s_clk_val(int dai_id, int stream)
  4583. {
  4584. u32 bit_per_sample;
  4585. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4586. bit_per_sample =
  4587. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4588. mi2s_clk[dai_id].clk_freq_in_hz =
  4589. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4590. } else {
  4591. bit_per_sample =
  4592. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4593. mi2s_clk[dai_id].clk_freq_in_hz =
  4594. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4595. }
  4596. }
  4597. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4598. {
  4599. int ret = 0;
  4600. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4601. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4602. int port_id = 0;
  4603. int index = cpu_dai->id;
  4604. port_id = msm_get_port_id(rtd->dai_link->id);
  4605. if (port_id < 0) {
  4606. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4607. ret = port_id;
  4608. goto err;
  4609. }
  4610. if (enable) {
  4611. update_mi2s_clk_val(index, substream->stream);
  4612. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4613. mi2s_clk[index].clk_freq_in_hz);
  4614. }
  4615. mi2s_clk[index].enable = enable;
  4616. ret = afe_set_lpass_clock_v2(port_id,
  4617. &mi2s_clk[index]);
  4618. if (ret < 0) {
  4619. dev_err(rtd->card->dev,
  4620. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4621. __func__, port_id, ret);
  4622. goto err;
  4623. }
  4624. err:
  4625. return ret;
  4626. }
  4627. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4628. struct snd_pcm_hw_params *params)
  4629. {
  4630. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4631. struct snd_interval *rate = hw_param_interval(params,
  4632. SNDRV_PCM_HW_PARAM_RATE);
  4633. struct snd_interval *channels = hw_param_interval(params,
  4634. SNDRV_PCM_HW_PARAM_CHANNELS);
  4635. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4636. channels->min = channels->max =
  4637. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4638. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4639. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4640. rate->min = rate->max =
  4641. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4642. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4643. channels->min = channels->max =
  4644. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4645. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4646. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4647. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4648. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4649. channels->min = channels->max =
  4650. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4651. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4652. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4653. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4654. } else {
  4655. pr_err("%s: dai id 0x%x not supported\n",
  4656. __func__, cpu_dai->id);
  4657. return -EINVAL;
  4658. }
  4659. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4660. __func__, cpu_dai->id, channels->max, rate->max,
  4661. params_format(params));
  4662. return 0;
  4663. }
  4664. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4665. struct snd_pcm_hw_params *params)
  4666. {
  4667. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4668. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4669. int ret = 0;
  4670. int slot_width = 32;
  4671. int channels, slots = 8;
  4672. unsigned int slot_mask, rate, clk_freq;
  4673. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4674. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4675. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4676. switch (cpu_dai->id) {
  4677. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4678. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4679. break;
  4680. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4681. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4682. break;
  4683. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4684. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4685. break;
  4686. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4687. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4688. break;
  4689. case AFE_PORT_ID_QUINARY_TDM_RX:
  4690. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4691. break;
  4692. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4693. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4694. break;
  4695. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4696. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4697. break;
  4698. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4699. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4700. break;
  4701. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4702. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4703. break;
  4704. case AFE_PORT_ID_QUINARY_TDM_TX:
  4705. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4706. break;
  4707. default:
  4708. pr_err("%s: dai id 0x%x not supported\n",
  4709. __func__, cpu_dai->id);
  4710. return -EINVAL;
  4711. }
  4712. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4713. /*2 slot config - bits 0 and 1 set for the first two slots */
  4714. slot_mask = 0x0000FFFF >> (16-channels);
  4715. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4716. __func__, slot_width, slots);
  4717. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4718. slots, slot_width);
  4719. if (ret < 0) {
  4720. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4721. __func__, ret);
  4722. goto end;
  4723. }
  4724. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4725. 0, NULL, channels, slot_offset);
  4726. if (ret < 0) {
  4727. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4728. __func__, ret);
  4729. goto end;
  4730. }
  4731. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4732. /*2 slot config - bits 0 and 1 set for the first two slots */
  4733. slot_mask = 0x0000FFFF >> (16-channels);
  4734. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4735. __func__, slot_width, slots);
  4736. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4737. slots, slot_width);
  4738. if (ret < 0) {
  4739. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4740. __func__, ret);
  4741. goto end;
  4742. }
  4743. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4744. channels, slot_offset, 0, NULL);
  4745. if (ret < 0) {
  4746. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4747. __func__, ret);
  4748. goto end;
  4749. }
  4750. } else {
  4751. ret = -EINVAL;
  4752. pr_err("%s: invalid use case, err:%d\n",
  4753. __func__, ret);
  4754. goto end;
  4755. }
  4756. rate = params_rate(params);
  4757. clk_freq = rate * slot_width * slots;
  4758. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4759. if (ret < 0)
  4760. pr_err("%s: failed to set tdm clk, err:%d\n",
  4761. __func__, ret);
  4762. end:
  4763. return ret;
  4764. }
  4765. static int msm_get_tdm_mode(u32 port_id)
  4766. {
  4767. u32 tdm_mode;
  4768. switch (port_id) {
  4769. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4770. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4771. tdm_mode = TDM_PRI;
  4772. break;
  4773. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4774. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4775. tdm_mode = TDM_SEC;
  4776. break;
  4777. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4778. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4779. tdm_mode = TDM_TERT;
  4780. break;
  4781. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4782. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4783. tdm_mode = TDM_QUAT;
  4784. break;
  4785. case AFE_PORT_ID_QUINARY_TDM_RX:
  4786. case AFE_PORT_ID_QUINARY_TDM_TX:
  4787. tdm_mode = TDM_QUIN;
  4788. break;
  4789. default:
  4790. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4791. tdm_mode = -EINVAL;
  4792. }
  4793. return tdm_mode;
  4794. }
  4795. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4796. {
  4797. int ret = 0;
  4798. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4799. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4800. struct snd_soc_card *card = rtd->card;
  4801. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4802. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4803. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4804. ret = -EINVAL;
  4805. pr_err("%s: Invalid TDM interface %d\n",
  4806. __func__, ret);
  4807. return ret;
  4808. }
  4809. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4810. ret = msm_cdc_pinctrl_select_active_state(
  4811. pdata->mi2s_gpio_p[tdm_mode]);
  4812. if (ret)
  4813. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4814. __func__, ret);
  4815. }
  4816. /* Enable Mic bias for TDM Mics */
  4817. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4818. if (pdata->tdm_micb_supply) {
  4819. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4820. pdata->tdm_micb_voltage,
  4821. pdata->tdm_micb_voltage);
  4822. if (ret) {
  4823. pr_err("%s: Setting voltage failed, err = %d\n",
  4824. __func__, ret);
  4825. return ret;
  4826. }
  4827. ret = regulator_set_load(pdata->tdm_micb_supply,
  4828. pdata->tdm_micb_current);
  4829. if (ret) {
  4830. pr_err("%s: Setting current failed, err = %d\n",
  4831. __func__, ret);
  4832. return ret;
  4833. }
  4834. ret = regulator_enable(pdata->tdm_micb_supply);
  4835. if (ret) {
  4836. pr_err("%s: regulator enable failed, err = %d\n",
  4837. __func__, ret);
  4838. return ret;
  4839. }
  4840. }
  4841. }
  4842. return ret;
  4843. }
  4844. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4845. {
  4846. int ret = 0;
  4847. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4848. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4849. struct snd_soc_card *card = rtd->card;
  4850. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4851. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4852. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4853. if (pdata->tdm_micb_supply) {
  4854. ret = regulator_disable(pdata->tdm_micb_supply);
  4855. if (ret)
  4856. pr_err("%s: regulator disable failed, err = %d\n",
  4857. __func__, ret);
  4858. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4859. pdata->tdm_micb_voltage);
  4860. regulator_set_load(pdata->tdm_micb_supply, 0);
  4861. }
  4862. }
  4863. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4864. ret = msm_cdc_pinctrl_select_sleep_state(
  4865. pdata->mi2s_gpio_p[tdm_mode]);
  4866. if (ret)
  4867. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4868. __func__, ret);
  4869. }
  4870. }
  4871. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4872. .hw_params = qcs405_tdm_snd_hw_params,
  4873. .startup = qcs405_tdm_snd_startup,
  4874. .shutdown = qcs405_tdm_snd_shutdown
  4875. };
  4876. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4877. {
  4878. cpumask_t mask;
  4879. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4880. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4881. cpumask_clear(&mask);
  4882. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4883. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4884. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4885. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4886. pm_qos_add_request(&substream->latency_pm_qos_req,
  4887. PM_QOS_CPU_DMA_LATENCY,
  4888. MSM_LL_QOS_VALUE);
  4889. return 0;
  4890. }
  4891. static struct snd_soc_ops msm_fe_qos_ops = {
  4892. .prepare = msm_fe_qos_prepare,
  4893. };
  4894. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4895. {
  4896. int ret = 0;
  4897. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4898. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4899. int index = cpu_dai->id;
  4900. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4901. struct snd_soc_card *card = rtd->card;
  4902. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4903. dev_dbg(rtd->card->dev,
  4904. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4905. __func__, substream->name, substream->stream,
  4906. cpu_dai->name, cpu_dai->id);
  4907. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4908. ret = -EINVAL;
  4909. dev_err(rtd->card->dev,
  4910. "%s: CPU DAI id (%d) out of range\n",
  4911. __func__, cpu_dai->id);
  4912. goto err;
  4913. }
  4914. /*
  4915. * Mutex protection in case the same MI2S
  4916. * interface using for both TX and RX so
  4917. * that the same clock won't be enable twice.
  4918. */
  4919. mutex_lock(&mi2s_intf_conf[index].lock);
  4920. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4921. /* Check if msm needs to provide the clock to the interface */
  4922. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4923. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4924. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4925. }
  4926. ret = msm_mi2s_set_sclk(substream, true);
  4927. if (ret < 0) {
  4928. dev_err(rtd->card->dev,
  4929. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4930. __func__, ret);
  4931. goto clean_up;
  4932. }
  4933. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4934. if (ret < 0) {
  4935. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4936. __func__, index, ret);
  4937. goto clk_off;
  4938. }
  4939. if (pdata->mi2s_gpio_p[index])
  4940. msm_cdc_pinctrl_select_active_state(
  4941. pdata->mi2s_gpio_p[index]);
  4942. }
  4943. clk_off:
  4944. if (ret < 0)
  4945. msm_mi2s_set_sclk(substream, false);
  4946. clean_up:
  4947. if (ret < 0)
  4948. mi2s_intf_conf[index].ref_cnt--;
  4949. mutex_unlock(&mi2s_intf_conf[index].lock);
  4950. err:
  4951. return ret;
  4952. }
  4953. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4954. {
  4955. int ret;
  4956. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4957. int index = rtd->cpu_dai->id;
  4958. struct snd_soc_card *card = rtd->card;
  4959. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4960. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4961. substream->name, substream->stream);
  4962. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4963. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4964. return;
  4965. }
  4966. mutex_lock(&mi2s_intf_conf[index].lock);
  4967. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4968. if (pdata->mi2s_gpio_p[index])
  4969. msm_cdc_pinctrl_select_sleep_state(
  4970. pdata->mi2s_gpio_p[index]);
  4971. ret = msm_mi2s_set_sclk(substream, false);
  4972. if (ret < 0)
  4973. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4974. __func__, index, ret);
  4975. }
  4976. mutex_unlock(&mi2s_intf_conf[index].lock);
  4977. }
  4978. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4979. {
  4980. int ret = 0;
  4981. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4982. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4983. int port_id = cpu_dai->id;
  4984. struct afe_clk_set clk_cfg;
  4985. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4986. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4987. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4988. clk_cfg.enable = enable;
  4989. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4990. switch (port_id) {
  4991. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4992. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4993. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4994. clk_cfg.clk_freq_in_hz =
  4995. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4996. break;
  4997. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4998. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4999. clk_cfg.clk_freq_in_hz =
  5000. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5001. break;
  5002. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5003. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5004. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5005. break;
  5006. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5007. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5008. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5009. break;
  5010. }
  5011. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5012. if (ret < 0) {
  5013. dev_err(rtd->card->dev,
  5014. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5015. __func__, port_id, ret);
  5016. goto err;
  5017. }
  5018. /* Set NPL clock for RX in addition */
  5019. switch (port_id) {
  5020. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5021. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5022. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5023. if (ret < 0) {
  5024. dev_err(rtd->card->dev,
  5025. "%s: afe NPL failed port 0x%x, err:%d\n",
  5026. __func__, port_id, ret);
  5027. goto err;
  5028. }
  5029. break;
  5030. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5031. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5032. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5033. if (ret < 0) {
  5034. dev_err(rtd->card->dev,
  5035. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5036. __func__, port_id, ret);
  5037. goto err;
  5038. }
  5039. break;
  5040. }
  5041. if (enable) {
  5042. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5043. clk_cfg.clk_freq_in_hz);
  5044. }
  5045. err:
  5046. return ret;
  5047. }
  5048. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5049. {
  5050. int ret = 0;
  5051. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5052. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5053. int port_id = cpu_dai->id;
  5054. dev_dbg(rtd->card->dev,
  5055. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5056. __func__, substream->name, substream->stream,
  5057. cpu_dai->name, cpu_dai->id);
  5058. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5059. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5060. ret = -EINVAL;
  5061. dev_err(rtd->card->dev,
  5062. "%s: CPU DAI id (%d) out of range\n",
  5063. __func__, cpu_dai->id);
  5064. goto err;
  5065. }
  5066. ret = msm_spdif_set_clk(substream, true);
  5067. if (ret < 0) {
  5068. dev_err(rtd->card->dev,
  5069. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5070. __func__, port_id, ret);
  5071. }
  5072. err:
  5073. return ret;
  5074. }
  5075. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5076. {
  5077. int ret;
  5078. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5079. int port_id = rtd->cpu_dai->id;
  5080. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5081. substream->name, substream->stream);
  5082. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5083. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5084. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5085. return;
  5086. }
  5087. ret = msm_spdif_set_clk(substream, false);
  5088. if (ret < 0)
  5089. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5090. __func__, port_id, ret);
  5091. }
  5092. static struct snd_soc_ops msm_mi2s_be_ops = {
  5093. .startup = msm_mi2s_snd_startup,
  5094. .shutdown = msm_mi2s_snd_shutdown,
  5095. };
  5096. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5097. .hw_params = msm_snd_cdc_dma_hw_params,
  5098. };
  5099. static struct snd_soc_ops msm_be_ops = {
  5100. .hw_params = msm_snd_hw_params,
  5101. };
  5102. static struct snd_soc_ops msm_wcn_ops = {
  5103. .hw_params = msm_wcn_hw_params,
  5104. };
  5105. static struct snd_soc_ops msm_spdif_be_ops = {
  5106. .startup = msm_spdif_snd_startup,
  5107. .shutdown = msm_spdif_snd_shutdown,
  5108. };
  5109. /* Digital audio interface glue - connects codec <---> CPU */
  5110. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5111. /* FrontEnd DAI Links */
  5112. {
  5113. .name = MSM_DAILINK_NAME(Media1),
  5114. .stream_name = "MultiMedia1",
  5115. .cpu_dai_name = "MultiMedia1",
  5116. .platform_name = "msm-pcm-dsp.0",
  5117. .dynamic = 1,
  5118. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5119. .dpcm_playback = 1,
  5120. .dpcm_capture = 1,
  5121. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5122. SND_SOC_DPCM_TRIGGER_POST},
  5123. .codec_dai_name = "snd-soc-dummy-dai",
  5124. .codec_name = "snd-soc-dummy",
  5125. .ignore_suspend = 1,
  5126. /* this dainlink has playback support */
  5127. .ignore_pmdown_time = 1,
  5128. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5129. },
  5130. {
  5131. .name = MSM_DAILINK_NAME(Media2),
  5132. .stream_name = "MultiMedia2",
  5133. .cpu_dai_name = "MultiMedia2",
  5134. .platform_name = "msm-pcm-dsp.0",
  5135. .dynamic = 1,
  5136. .dpcm_playback = 1,
  5137. .dpcm_capture = 1,
  5138. .codec_dai_name = "snd-soc-dummy-dai",
  5139. .codec_name = "snd-soc-dummy",
  5140. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5141. SND_SOC_DPCM_TRIGGER_POST},
  5142. .ignore_suspend = 1,
  5143. /* this dainlink has playback support */
  5144. .ignore_pmdown_time = 1,
  5145. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5146. },
  5147. {
  5148. .name = "VoiceMMode1",
  5149. .stream_name = "VoiceMMode1",
  5150. .cpu_dai_name = "VoiceMMode1",
  5151. .platform_name = "msm-pcm-voice",
  5152. .dynamic = 1,
  5153. .dpcm_playback = 1,
  5154. .dpcm_capture = 1,
  5155. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5156. SND_SOC_DPCM_TRIGGER_POST},
  5157. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5158. .ignore_suspend = 1,
  5159. .ignore_pmdown_time = 1,
  5160. .codec_dai_name = "snd-soc-dummy-dai",
  5161. .codec_name = "snd-soc-dummy",
  5162. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5163. },
  5164. {
  5165. .name = "MSM VoIP",
  5166. .stream_name = "VoIP",
  5167. .cpu_dai_name = "VoIP",
  5168. .platform_name = "msm-voip-dsp",
  5169. .dynamic = 1,
  5170. .dpcm_playback = 1,
  5171. .dpcm_capture = 1,
  5172. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5173. SND_SOC_DPCM_TRIGGER_POST},
  5174. .codec_dai_name = "snd-soc-dummy-dai",
  5175. .codec_name = "snd-soc-dummy",
  5176. .ignore_suspend = 1,
  5177. /* this dainlink has playback support */
  5178. .ignore_pmdown_time = 1,
  5179. .id = MSM_FRONTEND_DAI_VOIP,
  5180. },
  5181. {
  5182. .name = MSM_DAILINK_NAME(ULL),
  5183. .stream_name = "MultiMedia3",
  5184. .cpu_dai_name = "MultiMedia3",
  5185. .platform_name = "msm-pcm-dsp.2",
  5186. .dynamic = 1,
  5187. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5188. .dpcm_playback = 1,
  5189. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5190. SND_SOC_DPCM_TRIGGER_POST},
  5191. .codec_dai_name = "snd-soc-dummy-dai",
  5192. .codec_name = "snd-soc-dummy",
  5193. .ignore_suspend = 1,
  5194. /* this dainlink has playback support */
  5195. .ignore_pmdown_time = 1,
  5196. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5197. },
  5198. /* Hostless PCM purpose */
  5199. {
  5200. .name = "SLIMBUS_0 Hostless",
  5201. .stream_name = "SLIMBUS_0 Hostless",
  5202. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5203. .platform_name = "msm-pcm-hostless",
  5204. .dynamic = 1,
  5205. .dpcm_playback = 1,
  5206. .dpcm_capture = 1,
  5207. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5208. SND_SOC_DPCM_TRIGGER_POST},
  5209. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5210. .ignore_suspend = 1,
  5211. /* this dailink has playback support */
  5212. .ignore_pmdown_time = 1,
  5213. .codec_dai_name = "snd-soc-dummy-dai",
  5214. .codec_name = "snd-soc-dummy",
  5215. },
  5216. {
  5217. .name = "MSM AFE-PCM RX",
  5218. .stream_name = "AFE-PROXY RX",
  5219. .cpu_dai_name = "msm-dai-q6-dev.241",
  5220. .codec_name = "msm-stub-codec.1",
  5221. .codec_dai_name = "msm-stub-rx",
  5222. .platform_name = "msm-pcm-afe",
  5223. .dpcm_playback = 1,
  5224. .ignore_suspend = 1,
  5225. /* this dainlink has playback support */
  5226. .ignore_pmdown_time = 1,
  5227. },
  5228. {
  5229. .name = "MSM AFE-PCM TX",
  5230. .stream_name = "AFE-PROXY TX",
  5231. .cpu_dai_name = "msm-dai-q6-dev.240",
  5232. .codec_name = "msm-stub-codec.1",
  5233. .codec_dai_name = "msm-stub-tx",
  5234. .platform_name = "msm-pcm-afe",
  5235. .dpcm_capture = 1,
  5236. .ignore_suspend = 1,
  5237. },
  5238. {
  5239. .name = MSM_DAILINK_NAME(Compress1),
  5240. .stream_name = "Compress1",
  5241. .cpu_dai_name = "MultiMedia4",
  5242. .platform_name = "msm-compress-dsp",
  5243. .dynamic = 1,
  5244. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5245. .dpcm_playback = 1,
  5246. .dpcm_capture = 1,
  5247. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5248. SND_SOC_DPCM_TRIGGER_POST},
  5249. .codec_dai_name = "snd-soc-dummy-dai",
  5250. .codec_name = "snd-soc-dummy",
  5251. .ignore_suspend = 1,
  5252. .ignore_pmdown_time = 1,
  5253. /* this dainlink has playback support */
  5254. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5255. },
  5256. {
  5257. .name = "AUXPCM Hostless",
  5258. .stream_name = "AUXPCM Hostless",
  5259. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5260. .platform_name = "msm-pcm-hostless",
  5261. .dynamic = 1,
  5262. .dpcm_playback = 1,
  5263. .dpcm_capture = 1,
  5264. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5265. SND_SOC_DPCM_TRIGGER_POST},
  5266. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5267. .ignore_suspend = 1,
  5268. /* this dainlink has playback support */
  5269. .ignore_pmdown_time = 1,
  5270. .codec_dai_name = "snd-soc-dummy-dai",
  5271. .codec_name = "snd-soc-dummy",
  5272. },
  5273. {
  5274. .name = "SLIMBUS_1 Hostless",
  5275. .stream_name = "SLIMBUS_1 Hostless",
  5276. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5277. .platform_name = "msm-pcm-hostless",
  5278. .dynamic = 1,
  5279. .dpcm_playback = 1,
  5280. .dpcm_capture = 1,
  5281. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5282. SND_SOC_DPCM_TRIGGER_POST},
  5283. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5284. .ignore_suspend = 1,
  5285. /* this dailink has playback support */
  5286. .ignore_pmdown_time = 1,
  5287. .codec_dai_name = "snd-soc-dummy-dai",
  5288. .codec_name = "snd-soc-dummy",
  5289. },
  5290. {
  5291. .name = "SLIMBUS_3 Hostless",
  5292. .stream_name = "SLIMBUS_3 Hostless",
  5293. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5294. .platform_name = "msm-pcm-hostless",
  5295. .dynamic = 1,
  5296. .dpcm_playback = 1,
  5297. .dpcm_capture = 1,
  5298. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5299. SND_SOC_DPCM_TRIGGER_POST},
  5300. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5301. .ignore_suspend = 1,
  5302. /* this dailink has playback support */
  5303. .ignore_pmdown_time = 1,
  5304. .codec_dai_name = "snd-soc-dummy-dai",
  5305. .codec_name = "snd-soc-dummy",
  5306. },
  5307. {
  5308. .name = "SLIMBUS_4 Hostless",
  5309. .stream_name = "SLIMBUS_4 Hostless",
  5310. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5311. .platform_name = "msm-pcm-hostless",
  5312. .dynamic = 1,
  5313. .dpcm_playback = 1,
  5314. .dpcm_capture = 1,
  5315. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5316. SND_SOC_DPCM_TRIGGER_POST},
  5317. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5318. .ignore_suspend = 1,
  5319. /* this dailink has playback support */
  5320. .ignore_pmdown_time = 1,
  5321. .codec_dai_name = "snd-soc-dummy-dai",
  5322. .codec_name = "snd-soc-dummy",
  5323. },
  5324. {
  5325. .name = MSM_DAILINK_NAME(LowLatency),
  5326. .stream_name = "MultiMedia5",
  5327. .cpu_dai_name = "MultiMedia5",
  5328. .platform_name = "msm-pcm-dsp.1",
  5329. .dynamic = 1,
  5330. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5331. .dpcm_playback = 1,
  5332. .dpcm_capture = 1,
  5333. .codec_dai_name = "snd-soc-dummy-dai",
  5334. .codec_name = "snd-soc-dummy",
  5335. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5336. SND_SOC_DPCM_TRIGGER_POST},
  5337. .ignore_suspend = 1,
  5338. /* this dainlink has playback support */
  5339. .ignore_pmdown_time = 1,
  5340. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5341. .ops = &msm_fe_qos_ops,
  5342. },
  5343. {
  5344. .name = "Listen 1 Audio Service",
  5345. .stream_name = "Listen 1 Audio Service",
  5346. .cpu_dai_name = "LSM1",
  5347. .platform_name = "msm-lsm-client",
  5348. .dynamic = 1,
  5349. .dpcm_capture = 1,
  5350. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5351. SND_SOC_DPCM_TRIGGER_POST },
  5352. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5353. .ignore_suspend = 1,
  5354. .codec_dai_name = "snd-soc-dummy-dai",
  5355. .codec_name = "snd-soc-dummy",
  5356. .id = MSM_FRONTEND_DAI_LSM1,
  5357. },
  5358. /* Multiple Tunnel instances */
  5359. {
  5360. .name = MSM_DAILINK_NAME(Compress2),
  5361. .stream_name = "Compress2",
  5362. .cpu_dai_name = "MultiMedia7",
  5363. .platform_name = "msm-compress-dsp",
  5364. .dynamic = 1,
  5365. .dpcm_playback = 1,
  5366. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5367. SND_SOC_DPCM_TRIGGER_POST},
  5368. .codec_dai_name = "snd-soc-dummy-dai",
  5369. .codec_name = "snd-soc-dummy",
  5370. .ignore_suspend = 1,
  5371. .ignore_pmdown_time = 1,
  5372. /* this dainlink has playback support */
  5373. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5374. },
  5375. {
  5376. .name = MSM_DAILINK_NAME(MultiMedia10),
  5377. .stream_name = "MultiMedia10",
  5378. .cpu_dai_name = "MultiMedia10",
  5379. .platform_name = "msm-pcm-dsp.1",
  5380. .dynamic = 1,
  5381. .dpcm_playback = 1,
  5382. .dpcm_capture = 1,
  5383. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5384. SND_SOC_DPCM_TRIGGER_POST},
  5385. .codec_dai_name = "snd-soc-dummy-dai",
  5386. .codec_name = "snd-soc-dummy",
  5387. .ignore_suspend = 1,
  5388. .ignore_pmdown_time = 1,
  5389. /* this dainlink has playback support */
  5390. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5391. },
  5392. {
  5393. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5394. .stream_name = "MM_NOIRQ",
  5395. .cpu_dai_name = "MultiMedia8",
  5396. .platform_name = "msm-pcm-dsp-noirq",
  5397. .dynamic = 1,
  5398. .dpcm_playback = 1,
  5399. .dpcm_capture = 1,
  5400. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5401. SND_SOC_DPCM_TRIGGER_POST},
  5402. .codec_dai_name = "snd-soc-dummy-dai",
  5403. .codec_name = "snd-soc-dummy",
  5404. .ignore_suspend = 1,
  5405. .ignore_pmdown_time = 1,
  5406. /* this dainlink has playback support */
  5407. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5408. .ops = &msm_fe_qos_ops,
  5409. },
  5410. /* HDMI Hostless */
  5411. {
  5412. .name = "HDMI_RX_HOSTLESS",
  5413. .stream_name = "HDMI_RX_HOSTLESS",
  5414. .cpu_dai_name = "HDMI_HOSTLESS",
  5415. .platform_name = "msm-pcm-hostless",
  5416. .dynamic = 1,
  5417. .dpcm_playback = 1,
  5418. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5419. SND_SOC_DPCM_TRIGGER_POST},
  5420. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5421. .ignore_suspend = 1,
  5422. .ignore_pmdown_time = 1,
  5423. .codec_dai_name = "snd-soc-dummy-dai",
  5424. .codec_name = "snd-soc-dummy",
  5425. },
  5426. {
  5427. .name = "VoiceMMode2",
  5428. .stream_name = "VoiceMMode2",
  5429. .cpu_dai_name = "VoiceMMode2",
  5430. .platform_name = "msm-pcm-voice",
  5431. .dynamic = 1,
  5432. .dpcm_playback = 1,
  5433. .dpcm_capture = 1,
  5434. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5435. SND_SOC_DPCM_TRIGGER_POST},
  5436. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5437. .ignore_suspend = 1,
  5438. .ignore_pmdown_time = 1,
  5439. .codec_dai_name = "snd-soc-dummy-dai",
  5440. .codec_name = "snd-soc-dummy",
  5441. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5442. },
  5443. /* LSM FE */
  5444. {
  5445. .name = "Listen 2 Audio Service",
  5446. .stream_name = "Listen 2 Audio Service",
  5447. .cpu_dai_name = "LSM2",
  5448. .platform_name = "msm-lsm-client",
  5449. .dynamic = 1,
  5450. .dpcm_capture = 1,
  5451. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5452. SND_SOC_DPCM_TRIGGER_POST },
  5453. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5454. .ignore_suspend = 1,
  5455. .codec_dai_name = "snd-soc-dummy-dai",
  5456. .codec_name = "snd-soc-dummy",
  5457. .id = MSM_FRONTEND_DAI_LSM2,
  5458. },
  5459. {
  5460. .name = "Listen 3 Audio Service",
  5461. .stream_name = "Listen 3 Audio Service",
  5462. .cpu_dai_name = "LSM3",
  5463. .platform_name = "msm-lsm-client",
  5464. .dynamic = 1,
  5465. .dpcm_capture = 1,
  5466. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5467. SND_SOC_DPCM_TRIGGER_POST },
  5468. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5469. .ignore_suspend = 1,
  5470. .codec_dai_name = "snd-soc-dummy-dai",
  5471. .codec_name = "snd-soc-dummy",
  5472. .id = MSM_FRONTEND_DAI_LSM3,
  5473. },
  5474. {
  5475. .name = "Listen 4 Audio Service",
  5476. .stream_name = "Listen 4 Audio Service",
  5477. .cpu_dai_name = "LSM4",
  5478. .platform_name = "msm-lsm-client",
  5479. .dynamic = 1,
  5480. .dpcm_capture = 1,
  5481. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5482. SND_SOC_DPCM_TRIGGER_POST },
  5483. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5484. .ignore_suspend = 1,
  5485. .codec_dai_name = "snd-soc-dummy-dai",
  5486. .codec_name = "snd-soc-dummy",
  5487. .id = MSM_FRONTEND_DAI_LSM4,
  5488. },
  5489. {
  5490. .name = "Listen 5 Audio Service",
  5491. .stream_name = "Listen 5 Audio Service",
  5492. .cpu_dai_name = "LSM5",
  5493. .platform_name = "msm-lsm-client",
  5494. .dynamic = 1,
  5495. .dpcm_capture = 1,
  5496. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5497. SND_SOC_DPCM_TRIGGER_POST },
  5498. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5499. .ignore_suspend = 1,
  5500. .codec_dai_name = "snd-soc-dummy-dai",
  5501. .codec_name = "snd-soc-dummy",
  5502. .id = MSM_FRONTEND_DAI_LSM5,
  5503. },
  5504. {
  5505. .name = "Listen 6 Audio Service",
  5506. .stream_name = "Listen 6 Audio Service",
  5507. .cpu_dai_name = "LSM6",
  5508. .platform_name = "msm-lsm-client",
  5509. .dynamic = 1,
  5510. .dpcm_capture = 1,
  5511. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5512. SND_SOC_DPCM_TRIGGER_POST },
  5513. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5514. .ignore_suspend = 1,
  5515. .codec_dai_name = "snd-soc-dummy-dai",
  5516. .codec_name = "snd-soc-dummy",
  5517. .id = MSM_FRONTEND_DAI_LSM6,
  5518. },
  5519. {
  5520. .name = "Listen 7 Audio Service",
  5521. .stream_name = "Listen 7 Audio Service",
  5522. .cpu_dai_name = "LSM7",
  5523. .platform_name = "msm-lsm-client",
  5524. .dynamic = 1,
  5525. .dpcm_capture = 1,
  5526. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5527. SND_SOC_DPCM_TRIGGER_POST },
  5528. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5529. .ignore_suspend = 1,
  5530. .codec_dai_name = "snd-soc-dummy-dai",
  5531. .codec_name = "snd-soc-dummy",
  5532. .id = MSM_FRONTEND_DAI_LSM7,
  5533. },
  5534. {
  5535. .name = "Listen 8 Audio Service",
  5536. .stream_name = "Listen 8 Audio Service",
  5537. .cpu_dai_name = "LSM8",
  5538. .platform_name = "msm-lsm-client",
  5539. .dynamic = 1,
  5540. .dpcm_capture = 1,
  5541. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5542. SND_SOC_DPCM_TRIGGER_POST },
  5543. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5544. .ignore_suspend = 1,
  5545. .codec_dai_name = "snd-soc-dummy-dai",
  5546. .codec_name = "snd-soc-dummy",
  5547. .id = MSM_FRONTEND_DAI_LSM8,
  5548. },
  5549. {
  5550. .name = MSM_DAILINK_NAME(Media9),
  5551. .stream_name = "MultiMedia9",
  5552. .cpu_dai_name = "MultiMedia9",
  5553. .platform_name = "msm-pcm-dsp.0",
  5554. .dynamic = 1,
  5555. .dpcm_playback = 1,
  5556. .dpcm_capture = 1,
  5557. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5558. SND_SOC_DPCM_TRIGGER_POST},
  5559. .codec_dai_name = "snd-soc-dummy-dai",
  5560. .codec_name = "snd-soc-dummy",
  5561. .ignore_suspend = 1,
  5562. /* this dainlink has playback support */
  5563. .ignore_pmdown_time = 1,
  5564. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5565. },
  5566. {
  5567. .name = MSM_DAILINK_NAME(Compress4),
  5568. .stream_name = "Compress4",
  5569. .cpu_dai_name = "MultiMedia11",
  5570. .platform_name = "msm-compress-dsp",
  5571. .dynamic = 1,
  5572. .dpcm_playback = 1,
  5573. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5574. SND_SOC_DPCM_TRIGGER_POST},
  5575. .codec_dai_name = "snd-soc-dummy-dai",
  5576. .codec_name = "snd-soc-dummy",
  5577. .ignore_suspend = 1,
  5578. .ignore_pmdown_time = 1,
  5579. /* this dainlink has playback support */
  5580. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5581. },
  5582. {
  5583. .name = MSM_DAILINK_NAME(Compress5),
  5584. .stream_name = "Compress5",
  5585. .cpu_dai_name = "MultiMedia12",
  5586. .platform_name = "msm-compress-dsp",
  5587. .dynamic = 1,
  5588. .dpcm_playback = 1,
  5589. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5590. SND_SOC_DPCM_TRIGGER_POST},
  5591. .codec_dai_name = "snd-soc-dummy-dai",
  5592. .codec_name = "snd-soc-dummy",
  5593. .ignore_suspend = 1,
  5594. .ignore_pmdown_time = 1,
  5595. /* this dainlink has playback support */
  5596. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5597. },
  5598. {
  5599. .name = MSM_DAILINK_NAME(Compress6),
  5600. .stream_name = "Compress6",
  5601. .cpu_dai_name = "MultiMedia13",
  5602. .platform_name = "msm-compress-dsp",
  5603. .dynamic = 1,
  5604. .dpcm_playback = 1,
  5605. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5606. SND_SOC_DPCM_TRIGGER_POST},
  5607. .codec_dai_name = "snd-soc-dummy-dai",
  5608. .codec_name = "snd-soc-dummy",
  5609. .ignore_suspend = 1,
  5610. .ignore_pmdown_time = 1,
  5611. /* this dainlink has playback support */
  5612. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5613. },
  5614. {
  5615. .name = MSM_DAILINK_NAME(Compress7),
  5616. .stream_name = "Compress7",
  5617. .cpu_dai_name = "MultiMedia14",
  5618. .platform_name = "msm-compress-dsp",
  5619. .dynamic = 1,
  5620. .dpcm_playback = 1,
  5621. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5622. SND_SOC_DPCM_TRIGGER_POST},
  5623. .codec_dai_name = "snd-soc-dummy-dai",
  5624. .codec_name = "snd-soc-dummy",
  5625. .ignore_suspend = 1,
  5626. .ignore_pmdown_time = 1,
  5627. /* this dainlink has playback support */
  5628. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5629. },
  5630. {
  5631. .name = MSM_DAILINK_NAME(Compress8),
  5632. .stream_name = "Compress8",
  5633. .cpu_dai_name = "MultiMedia15",
  5634. .platform_name = "msm-compress-dsp",
  5635. .dynamic = 1,
  5636. .dpcm_playback = 1,
  5637. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5638. SND_SOC_DPCM_TRIGGER_POST},
  5639. .codec_dai_name = "snd-soc-dummy-dai",
  5640. .codec_name = "snd-soc-dummy",
  5641. .ignore_suspend = 1,
  5642. .ignore_pmdown_time = 1,
  5643. /* this dainlink has playback support */
  5644. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5645. },
  5646. {
  5647. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5648. .stream_name = "MM_NOIRQ_2",
  5649. .cpu_dai_name = "MultiMedia16",
  5650. .platform_name = "msm-pcm-dsp-noirq",
  5651. .dynamic = 1,
  5652. .dpcm_playback = 1,
  5653. .dpcm_capture = 1,
  5654. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5655. SND_SOC_DPCM_TRIGGER_POST},
  5656. .codec_dai_name = "snd-soc-dummy-dai",
  5657. .codec_name = "snd-soc-dummy",
  5658. .ignore_suspend = 1,
  5659. .ignore_pmdown_time = 1,
  5660. /* this dainlink has playback support */
  5661. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5662. },
  5663. {
  5664. .name = "SLIMBUS_8 Hostless",
  5665. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5666. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5667. .platform_name = "msm-pcm-hostless",
  5668. .dynamic = 1,
  5669. .dpcm_capture = 1,
  5670. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5671. SND_SOC_DPCM_TRIGGER_POST},
  5672. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5673. .ignore_suspend = 1,
  5674. .codec_dai_name = "snd-soc-dummy-dai",
  5675. .codec_name = "snd-soc-dummy",
  5676. },
  5677. /* Hostless PCM purpose */
  5678. {
  5679. .name = "CDC_DMA Hostless",
  5680. .stream_name = "CDC_DMA Hostless",
  5681. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5682. .platform_name = "msm-pcm-hostless",
  5683. .dynamic = 1,
  5684. .dpcm_playback = 1,
  5685. .dpcm_capture = 1,
  5686. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5687. SND_SOC_DPCM_TRIGGER_POST},
  5688. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5689. .ignore_suspend = 1,
  5690. /* this dailink has playback support */
  5691. .ignore_pmdown_time = 1,
  5692. .codec_dai_name = "snd-soc-dummy-dai",
  5693. .codec_name = "snd-soc-dummy",
  5694. },
  5695. };
  5696. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5697. {
  5698. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5699. .stream_name = "WSA CDC DMA0 Capture",
  5700. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5701. .platform_name = "msm-pcm-hostless",
  5702. .codec_name = "bolero_codec",
  5703. .codec_dai_name = "wsa_macro_vifeedback",
  5704. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5705. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5706. .ignore_suspend = 1,
  5707. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5708. .ops = &msm_cdc_dma_be_ops,
  5709. },
  5710. };
  5711. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5712. {
  5713. .name = MSM_DAILINK_NAME(ASM Loopback),
  5714. .stream_name = "MultiMedia6",
  5715. .cpu_dai_name = "MultiMedia6",
  5716. .platform_name = "msm-pcm-loopback",
  5717. .dynamic = 1,
  5718. .dpcm_playback = 1,
  5719. .dpcm_capture = 1,
  5720. .codec_dai_name = "snd-soc-dummy-dai",
  5721. .codec_name = "snd-soc-dummy",
  5722. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5723. SND_SOC_DPCM_TRIGGER_POST},
  5724. .ignore_suspend = 1,
  5725. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5726. .ignore_pmdown_time = 1,
  5727. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5728. },
  5729. {
  5730. .name = "USB Audio Hostless",
  5731. .stream_name = "USB Audio Hostless",
  5732. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5733. .platform_name = "msm-pcm-hostless",
  5734. .dynamic = 1,
  5735. .dpcm_playback = 1,
  5736. .dpcm_capture = 1,
  5737. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5738. SND_SOC_DPCM_TRIGGER_POST},
  5739. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5740. .ignore_suspend = 1,
  5741. .ignore_pmdown_time = 1,
  5742. .codec_dai_name = "snd-soc-dummy-dai",
  5743. .codec_name = "snd-soc-dummy",
  5744. },
  5745. {
  5746. .name = "SLIMBUS_7 Hostless",
  5747. .stream_name = "SLIMBUS_7 Hostless",
  5748. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5749. .platform_name = "msm-pcm-hostless",
  5750. .dynamic = 1,
  5751. .dpcm_capture = 1,
  5752. .dpcm_playback = 1,
  5753. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5754. SND_SOC_DPCM_TRIGGER_POST},
  5755. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5756. .ignore_suspend = 1,
  5757. .ignore_pmdown_time = 1,
  5758. .codec_dai_name = "snd-soc-dummy-dai",
  5759. .codec_name = "snd-soc-dummy",
  5760. },
  5761. {
  5762. .name = MSM_DAILINK_NAME(Compr Capture),
  5763. .stream_name = "Compr Capture",
  5764. .cpu_dai_name = "MultiMedia18",
  5765. .platform_name = "msm-compress-dsp",
  5766. .dynamic = 1,
  5767. .dpcm_capture = 1,
  5768. .codec_dai_name = "snd-soc-dummy-dai",
  5769. .codec_name = "snd-soc-dummy",
  5770. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5771. SND_SOC_DPCM_TRIGGER_POST},
  5772. .ignore_pmdown_time = 1,
  5773. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5774. },
  5775. {
  5776. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5777. .stream_name = "Transcode Loopback Playback",
  5778. .cpu_dai_name = "MultiMedia26",
  5779. .platform_name = "msm-transcode-loopback",
  5780. .dynamic = 1,
  5781. .dpcm_playback = 1,
  5782. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5783. SND_SOC_DPCM_TRIGGER_POST},
  5784. .codec_dai_name = "snd-soc-dummy-dai",
  5785. .codec_name = "snd-soc-dummy",
  5786. .ignore_suspend = 1,
  5787. .ignore_pmdown_time = 1,
  5788. /* this dailink has playback support */
  5789. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5790. },
  5791. {
  5792. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5793. .stream_name = "Transcode Loopback Capture",
  5794. .cpu_dai_name = "MultiMedia27",
  5795. .platform_name = "msm-transcode-loopback",
  5796. .dynamic = 1,
  5797. .dpcm_capture = 1,
  5798. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5799. SND_SOC_DPCM_TRIGGER_POST},
  5800. .codec_dai_name = "snd-soc-dummy-dai",
  5801. .codec_name = "snd-soc-dummy",
  5802. .ignore_suspend = 1,
  5803. .ignore_pmdown_time = 1,
  5804. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5805. },
  5806. };
  5807. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5808. /* Backend AFE DAI Links */
  5809. {
  5810. .name = LPASS_BE_AFE_PCM_RX,
  5811. .stream_name = "AFE Playback",
  5812. .cpu_dai_name = "msm-dai-q6-dev.224",
  5813. .platform_name = "msm-pcm-routing",
  5814. .codec_name = "msm-stub-codec.1",
  5815. .codec_dai_name = "msm-stub-rx",
  5816. .no_pcm = 1,
  5817. .dpcm_playback = 1,
  5818. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5819. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5820. /* this dainlink has playback support */
  5821. .ignore_pmdown_time = 1,
  5822. .ignore_suspend = 1,
  5823. },
  5824. {
  5825. .name = LPASS_BE_AFE_PCM_TX,
  5826. .stream_name = "AFE Capture",
  5827. .cpu_dai_name = "msm-dai-q6-dev.225",
  5828. .platform_name = "msm-pcm-routing",
  5829. .codec_name = "msm-stub-codec.1",
  5830. .codec_dai_name = "msm-stub-tx",
  5831. .no_pcm = 1,
  5832. .dpcm_capture = 1,
  5833. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5834. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5835. .ignore_suspend = 1,
  5836. },
  5837. /* Incall Record Uplink BACK END DAI Link */
  5838. {
  5839. .name = LPASS_BE_INCALL_RECORD_TX,
  5840. .stream_name = "Voice Uplink Capture",
  5841. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5842. .platform_name = "msm-pcm-routing",
  5843. .codec_name = "msm-stub-codec.1",
  5844. .codec_dai_name = "msm-stub-tx",
  5845. .no_pcm = 1,
  5846. .dpcm_capture = 1,
  5847. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5849. .ignore_suspend = 1,
  5850. },
  5851. /* Incall Record Downlink BACK END DAI Link */
  5852. {
  5853. .name = LPASS_BE_INCALL_RECORD_RX,
  5854. .stream_name = "Voice Downlink Capture",
  5855. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5856. .platform_name = "msm-pcm-routing",
  5857. .codec_name = "msm-stub-codec.1",
  5858. .codec_dai_name = "msm-stub-tx",
  5859. .no_pcm = 1,
  5860. .dpcm_capture = 1,
  5861. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5862. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5863. .ignore_suspend = 1,
  5864. },
  5865. /* Incall Music BACK END DAI Link */
  5866. {
  5867. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5868. .stream_name = "Voice Farend Playback",
  5869. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5870. .platform_name = "msm-pcm-routing",
  5871. .codec_name = "msm-stub-codec.1",
  5872. .codec_dai_name = "msm-stub-rx",
  5873. .no_pcm = 1,
  5874. .dpcm_playback = 1,
  5875. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5876. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5877. .ignore_suspend = 1,
  5878. .ignore_pmdown_time = 1,
  5879. },
  5880. /* Incall Music 2 BACK END DAI Link */
  5881. {
  5882. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5883. .stream_name = "Voice2 Farend Playback",
  5884. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5885. .platform_name = "msm-pcm-routing",
  5886. .codec_name = "msm-stub-codec.1",
  5887. .codec_dai_name = "msm-stub-rx",
  5888. .no_pcm = 1,
  5889. .dpcm_playback = 1,
  5890. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5891. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5892. .ignore_suspend = 1,
  5893. .ignore_pmdown_time = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_USB_AUDIO_RX,
  5897. .stream_name = "USB Audio Playback",
  5898. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-rx",
  5902. .no_pcm = 1,
  5903. .dpcm_playback = 1,
  5904. .id = MSM_BACKEND_DAI_USB_RX,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ignore_pmdown_time = 1,
  5907. .ignore_suspend = 1,
  5908. },
  5909. {
  5910. .name = LPASS_BE_USB_AUDIO_TX,
  5911. .stream_name = "USB Audio Capture",
  5912. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5913. .platform_name = "msm-pcm-routing",
  5914. .codec_name = "msm-stub-codec.1",
  5915. .codec_dai_name = "msm-stub-tx",
  5916. .no_pcm = 1,
  5917. .dpcm_capture = 1,
  5918. .id = MSM_BACKEND_DAI_USB_TX,
  5919. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5920. .ignore_suspend = 1,
  5921. },
  5922. {
  5923. .name = LPASS_BE_PRI_TDM_RX_0,
  5924. .stream_name = "Primary TDM0 Playback",
  5925. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5926. .platform_name = "msm-pcm-routing",
  5927. .codec_name = "msm-stub-codec.1",
  5928. .codec_dai_name = "msm-stub-rx",
  5929. .no_pcm = 1,
  5930. .dpcm_playback = 1,
  5931. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5932. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5933. .ops = &qcs405_tdm_be_ops,
  5934. .ignore_suspend = 1,
  5935. .ignore_pmdown_time = 1,
  5936. },
  5937. {
  5938. .name = LPASS_BE_PRI_TDM_TX_0,
  5939. .stream_name = "Primary TDM0 Capture",
  5940. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5941. .platform_name = "msm-pcm-routing",
  5942. .codec_name = "msm-stub-codec.1",
  5943. .codec_dai_name = "msm-stub-tx",
  5944. .no_pcm = 1,
  5945. .dpcm_capture = 1,
  5946. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5947. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5948. .ops = &qcs405_tdm_be_ops,
  5949. .ignore_suspend = 1,
  5950. },
  5951. {
  5952. .name = LPASS_BE_SEC_TDM_RX_0,
  5953. .stream_name = "Secondary TDM0 Playback",
  5954. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5955. .platform_name = "msm-pcm-routing",
  5956. .codec_name = "msm-stub-codec.1",
  5957. .codec_dai_name = "msm-stub-rx",
  5958. .no_pcm = 1,
  5959. .dpcm_playback = 1,
  5960. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5961. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5962. .ops = &qcs405_tdm_be_ops,
  5963. .ignore_suspend = 1,
  5964. .ignore_pmdown_time = 1,
  5965. },
  5966. {
  5967. .name = LPASS_BE_SEC_TDM_TX_0,
  5968. .stream_name = "Secondary TDM0 Capture",
  5969. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5970. .platform_name = "msm-pcm-routing",
  5971. .codec_name = "msm-stub-codec.1",
  5972. .codec_dai_name = "msm-stub-tx",
  5973. .no_pcm = 1,
  5974. .dpcm_capture = 1,
  5975. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5976. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5977. .ops = &qcs405_tdm_be_ops,
  5978. .ignore_suspend = 1,
  5979. },
  5980. {
  5981. .name = LPASS_BE_TERT_TDM_RX_0,
  5982. .stream_name = "Tertiary TDM0 Playback",
  5983. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5984. .platform_name = "msm-pcm-routing",
  5985. .codec_name = "msm-stub-codec.1",
  5986. .codec_dai_name = "msm-stub-rx",
  5987. .no_pcm = 1,
  5988. .dpcm_playback = 1,
  5989. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5990. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5991. .ops = &qcs405_tdm_be_ops,
  5992. .ignore_suspend = 1,
  5993. .ignore_pmdown_time = 1,
  5994. },
  5995. {
  5996. .name = LPASS_BE_TERT_TDM_TX_0,
  5997. .stream_name = "Tertiary TDM0 Capture",
  5998. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5999. .platform_name = "msm-pcm-routing",
  6000. .codec_name = "msm-stub-codec.1",
  6001. .codec_dai_name = "msm-stub-tx",
  6002. .no_pcm = 1,
  6003. .dpcm_capture = 1,
  6004. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6005. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6006. .ops = &qcs405_tdm_be_ops,
  6007. .ignore_suspend = 1,
  6008. },
  6009. {
  6010. .name = LPASS_BE_QUAT_TDM_RX_0,
  6011. .stream_name = "Quaternary TDM0 Playback",
  6012. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6013. .platform_name = "msm-pcm-routing",
  6014. .codec_name = "msm-stub-codec.1",
  6015. .codec_dai_name = "msm-stub-rx",
  6016. .no_pcm = 1,
  6017. .dpcm_playback = 1,
  6018. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6019. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6020. .ops = &qcs405_tdm_be_ops,
  6021. .ignore_suspend = 1,
  6022. .ignore_pmdown_time = 1,
  6023. },
  6024. {
  6025. .name = LPASS_BE_QUAT_TDM_TX_0,
  6026. .stream_name = "Quaternary TDM0 Capture",
  6027. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6028. .platform_name = "msm-pcm-routing",
  6029. .codec_name = "msm-stub-codec.1",
  6030. .codec_dai_name = "msm-stub-tx",
  6031. .no_pcm = 1,
  6032. .dpcm_capture = 1,
  6033. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6034. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6035. .ops = &qcs405_tdm_be_ops,
  6036. .ignore_suspend = 1,
  6037. },
  6038. {
  6039. .name = LPASS_BE_QUIN_TDM_RX_0,
  6040. .stream_name = "Quinary TDM0 Playback",
  6041. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6042. .platform_name = "msm-pcm-routing",
  6043. .codec_name = "msm-stub-codec.1",
  6044. .codec_dai_name = "msm-stub-rx",
  6045. .no_pcm = 1,
  6046. .dpcm_playback = 1,
  6047. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6048. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6049. .ops = &qcs405_tdm_be_ops,
  6050. .ignore_suspend = 1,
  6051. .ignore_pmdown_time = 1,
  6052. },
  6053. {
  6054. .name = LPASS_BE_QUIN_TDM_TX_0,
  6055. .stream_name = "Quinary TDM0 Capture",
  6056. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6057. .platform_name = "msm-pcm-routing",
  6058. .codec_name = "msm-stub-codec.1",
  6059. .codec_dai_name = "msm-stub-tx",
  6060. .no_pcm = 1,
  6061. .dpcm_capture = 1,
  6062. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6063. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6064. .ops = &qcs405_tdm_be_ops,
  6065. .ignore_suspend = 1,
  6066. },
  6067. };
  6068. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6069. {
  6070. .name = LPASS_BE_SLIMBUS_0_RX,
  6071. .stream_name = "Slimbus Playback",
  6072. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6073. .platform_name = "msm-pcm-routing",
  6074. .codec_name = "tasha_codec",
  6075. .codec_dai_name = "tasha_mix_rx1",
  6076. .no_pcm = 1,
  6077. .dpcm_playback = 1,
  6078. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6079. .init = &msm_audrx_init,
  6080. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6081. /* this dainlink has playback support */
  6082. .ignore_pmdown_time = 1,
  6083. .ignore_suspend = 1,
  6084. .ops = &msm_be_ops,
  6085. },
  6086. {
  6087. .name = LPASS_BE_SLIMBUS_0_TX,
  6088. .stream_name = "Slimbus Capture",
  6089. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6090. .platform_name = "msm-pcm-routing",
  6091. .codec_name = "tasha_codec",
  6092. .codec_dai_name = "tasha_tx1",
  6093. .no_pcm = 1,
  6094. .dpcm_capture = 1,
  6095. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6096. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6097. .ignore_suspend = 1,
  6098. .ops = &msm_be_ops,
  6099. },
  6100. {
  6101. .name = LPASS_BE_SLIMBUS_1_RX,
  6102. .stream_name = "Slimbus1 Playback",
  6103. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6104. .platform_name = "msm-pcm-routing",
  6105. .codec_name = "tasha_codec",
  6106. .codec_dai_name = "tasha_mix_rx1",
  6107. .no_pcm = 1,
  6108. .dpcm_playback = 1,
  6109. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6110. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6111. .ops = &msm_be_ops,
  6112. /* dai link has playback support */
  6113. .ignore_pmdown_time = 1,
  6114. .ignore_suspend = 1,
  6115. },
  6116. {
  6117. .name = LPASS_BE_SLIMBUS_1_TX,
  6118. .stream_name = "Slimbus1 Capture",
  6119. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6120. .platform_name = "msm-pcm-routing",
  6121. .codec_name = "tasha_codec",
  6122. .codec_dai_name = "tasha_tx3",
  6123. .no_pcm = 1,
  6124. .dpcm_capture = 1,
  6125. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6126. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6127. .ops = &msm_be_ops,
  6128. .ignore_suspend = 1,
  6129. },
  6130. {
  6131. .name = LPASS_BE_SLIMBUS_2_RX,
  6132. .stream_name = "Slimbus2 Playback",
  6133. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6134. .platform_name = "msm-pcm-routing",
  6135. .codec_name = "tasha_codec",
  6136. .codec_dai_name = "tasha_rx2",
  6137. .no_pcm = 1,
  6138. .dpcm_playback = 1,
  6139. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6140. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6141. .ops = &msm_be_ops,
  6142. .ignore_pmdown_time = 1,
  6143. .ignore_suspend = 1,
  6144. },
  6145. {
  6146. .name = LPASS_BE_SLIMBUS_3_RX,
  6147. .stream_name = "Slimbus3 Playback",
  6148. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6149. .platform_name = "msm-pcm-routing",
  6150. .codec_name = "tasha_codec",
  6151. .codec_dai_name = "tasha_mix_rx1",
  6152. .no_pcm = 1,
  6153. .dpcm_playback = 1,
  6154. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6155. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6156. .ops = &msm_be_ops,
  6157. /* dai link has playback support */
  6158. .ignore_pmdown_time = 1,
  6159. .ignore_suspend = 1,
  6160. },
  6161. {
  6162. .name = LPASS_BE_SLIMBUS_3_TX,
  6163. .stream_name = "Slimbus3 Capture",
  6164. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6165. .platform_name = "msm-pcm-routing",
  6166. .codec_name = "tasha_codec",
  6167. .codec_dai_name = "tasha_tx1",
  6168. .no_pcm = 1,
  6169. .dpcm_capture = 1,
  6170. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6171. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6172. .ops = &msm_be_ops,
  6173. .ignore_suspend = 1,
  6174. },
  6175. {
  6176. .name = LPASS_BE_SLIMBUS_4_RX,
  6177. .stream_name = "Slimbus4 Playback",
  6178. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6179. .platform_name = "msm-pcm-routing",
  6180. .codec_name = "tasha_codec",
  6181. .codec_dai_name = "tasha_mix_rx1",
  6182. .no_pcm = 1,
  6183. .dpcm_playback = 1,
  6184. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6185. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6186. .ops = &msm_be_ops,
  6187. /* dai link has playback support */
  6188. .ignore_pmdown_time = 1,
  6189. .ignore_suspend = 1,
  6190. },
  6191. {
  6192. .name = LPASS_BE_SLIMBUS_5_RX,
  6193. .stream_name = "Slimbus5 Playback",
  6194. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6195. .platform_name = "msm-pcm-routing",
  6196. .codec_name = "tasha_codec",
  6197. .codec_dai_name = "tasha_rx3",
  6198. .no_pcm = 1,
  6199. .dpcm_playback = 1,
  6200. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6201. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6202. .ops = &msm_be_ops,
  6203. /* dai link has playback support */
  6204. .ignore_pmdown_time = 1,
  6205. .ignore_suspend = 1,
  6206. },
  6207. {
  6208. .name = LPASS_BE_SLIMBUS_6_RX,
  6209. .stream_name = "Slimbus6 Playback",
  6210. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6211. .platform_name = "msm-pcm-routing",
  6212. .codec_name = "tasha_codec",
  6213. .codec_dai_name = "tasha_rx4",
  6214. .no_pcm = 1,
  6215. .dpcm_playback = 1,
  6216. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6217. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6218. .ops = &msm_be_ops,
  6219. /* dai link has playback support */
  6220. .ignore_pmdown_time = 1,
  6221. .ignore_suspend = 1,
  6222. },
  6223. /* Slimbus VI Recording */
  6224. {
  6225. .name = LPASS_BE_SLIMBUS_TX_VI,
  6226. .stream_name = "Slimbus4 Capture",
  6227. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6228. .platform_name = "msm-pcm-routing",
  6229. .codec_name = "tasha_codec",
  6230. .codec_dai_name = "tasha_vifeedback",
  6231. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6233. .ops = &msm_be_ops,
  6234. .ignore_suspend = 1,
  6235. .no_pcm = 1,
  6236. .dpcm_capture = 1,
  6237. .ignore_pmdown_time = 1,
  6238. },
  6239. };
  6240. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6241. {
  6242. .name = LPASS_BE_SLIMBUS_7_RX,
  6243. .stream_name = "Slimbus7 Playback",
  6244. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6245. .platform_name = "msm-pcm-routing",
  6246. .codec_name = "btfmslim_slave",
  6247. /* BT codec driver determines capabilities based on
  6248. * dai name, bt codecdai name should always contains
  6249. * supported usecase information
  6250. */
  6251. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6252. .no_pcm = 1,
  6253. .dpcm_playback = 1,
  6254. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6255. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6256. .ops = &msm_wcn_ops,
  6257. /* dai link has playback support */
  6258. .ignore_pmdown_time = 1,
  6259. .ignore_suspend = 1,
  6260. },
  6261. {
  6262. .name = LPASS_BE_SLIMBUS_7_TX,
  6263. .stream_name = "Slimbus7 Capture",
  6264. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6265. .platform_name = "msm-pcm-routing",
  6266. .codec_name = "btfmslim_slave",
  6267. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6268. .no_pcm = 1,
  6269. .dpcm_capture = 1,
  6270. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6271. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6272. .ops = &msm_wcn_ops,
  6273. .ignore_suspend = 1,
  6274. },
  6275. {
  6276. .name = LPASS_BE_SLIMBUS_8_TX,
  6277. .stream_name = "Slimbus8 Capture",
  6278. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6279. .platform_name = "msm-pcm-routing",
  6280. .codec_name = "btfmslim_slave",
  6281. .codec_dai_name = "btfm_fm_slim_tx",
  6282. .no_pcm = 1,
  6283. .dpcm_capture = 1,
  6284. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6285. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6286. .init = &msm_wcn_init,
  6287. .ops = &msm_wcn_ops,
  6288. .ignore_suspend = 1,
  6289. },
  6290. {
  6291. .name = LPASS_BE_SLIMBUS_9_TX,
  6292. .stream_name = "Slimbus9 Capture",
  6293. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6294. .platform_name = "msm-pcm-routing",
  6295. .codec_name = "btfmslim_slave",
  6296. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6297. .no_pcm = 1,
  6298. .dpcm_capture = 1,
  6299. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6300. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6301. .ops = &msm_wcn_ops,
  6302. .ignore_suspend = 1,
  6303. },
  6304. };
  6305. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6306. {
  6307. .name = LPASS_BE_PRI_MI2S_RX,
  6308. .stream_name = "Primary MI2S Playback",
  6309. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6310. .platform_name = "msm-pcm-routing",
  6311. .codec_name = "msm-stub-codec.1",
  6312. .codec_dai_name = "msm-stub-rx",
  6313. .no_pcm = 1,
  6314. .dpcm_playback = 1,
  6315. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6316. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6317. .ops = &msm_mi2s_be_ops,
  6318. .ignore_suspend = 1,
  6319. .ignore_pmdown_time = 1,
  6320. },
  6321. {
  6322. .name = LPASS_BE_PRI_MI2S_TX,
  6323. .stream_name = "Primary MI2S Capture",
  6324. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6325. .platform_name = "msm-pcm-routing",
  6326. .codec_name = "msm-stub-codec.1",
  6327. .codec_dai_name = "msm-stub-tx",
  6328. .no_pcm = 1,
  6329. .dpcm_capture = 1,
  6330. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6331. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6332. .ops = &msm_mi2s_be_ops,
  6333. .ignore_suspend = 1,
  6334. },
  6335. {
  6336. .name = LPASS_BE_SEC_MI2S_RX,
  6337. .stream_name = "Secondary MI2S Playback",
  6338. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6339. .platform_name = "msm-pcm-routing",
  6340. .codec_name = "msm-stub-codec.1",
  6341. .codec_dai_name = "msm-stub-rx",
  6342. .no_pcm = 1,
  6343. .dpcm_playback = 1,
  6344. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6345. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6346. .ops = &msm_mi2s_be_ops,
  6347. .ignore_suspend = 1,
  6348. .ignore_pmdown_time = 1,
  6349. },
  6350. {
  6351. .name = LPASS_BE_SEC_MI2S_TX,
  6352. .stream_name = "Secondary MI2S Capture",
  6353. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6354. .platform_name = "msm-pcm-routing",
  6355. .codec_name = "msm-stub-codec.1",
  6356. .codec_dai_name = "msm-stub-tx",
  6357. .no_pcm = 1,
  6358. .dpcm_capture = 1,
  6359. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6360. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6361. .ops = &msm_mi2s_be_ops,
  6362. .ignore_suspend = 1,
  6363. },
  6364. {
  6365. .name = LPASS_BE_TERT_MI2S_RX,
  6366. .stream_name = "Tertiary MI2S Playback",
  6367. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6368. .platform_name = "msm-pcm-routing",
  6369. .codec_name = "msm-stub-codec.1",
  6370. .codec_dai_name = "msm-stub-rx",
  6371. .no_pcm = 1,
  6372. .dpcm_playback = 1,
  6373. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6374. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6375. .ops = &msm_mi2s_be_ops,
  6376. .ignore_suspend = 1,
  6377. .ignore_pmdown_time = 1,
  6378. },
  6379. {
  6380. .name = LPASS_BE_TERT_MI2S_TX,
  6381. .stream_name = "Tertiary MI2S Capture",
  6382. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6383. .platform_name = "msm-pcm-routing",
  6384. .codec_name = "msm-stub-codec.1",
  6385. .codec_dai_name = "msm-stub-tx",
  6386. .no_pcm = 1,
  6387. .dpcm_capture = 1,
  6388. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6389. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6390. .ops = &msm_mi2s_be_ops,
  6391. .ignore_suspend = 1,
  6392. },
  6393. {
  6394. .name = LPASS_BE_QUAT_MI2S_RX,
  6395. .stream_name = "Quaternary MI2S Playback",
  6396. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6397. .platform_name = "msm-pcm-routing",
  6398. .codec_name = "msm-stub-codec.1",
  6399. .codec_dai_name = "msm-stub-rx",
  6400. .no_pcm = 1,
  6401. .dpcm_playback = 1,
  6402. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6403. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6404. .ops = &msm_mi2s_be_ops,
  6405. .ignore_suspend = 1,
  6406. .ignore_pmdown_time = 1,
  6407. },
  6408. {
  6409. .name = LPASS_BE_QUAT_MI2S_TX,
  6410. .stream_name = "Quaternary MI2S Capture",
  6411. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6412. .platform_name = "msm-pcm-routing",
  6413. .codec_name = "msm-stub-codec.1",
  6414. .codec_dai_name = "msm-stub-tx",
  6415. .no_pcm = 1,
  6416. .dpcm_capture = 1,
  6417. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6418. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6419. .ops = &msm_mi2s_be_ops,
  6420. .ignore_suspend = 1,
  6421. },
  6422. {
  6423. .name = LPASS_BE_QUIN_MI2S_RX,
  6424. .stream_name = "Quinary MI2S Playback",
  6425. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6426. .platform_name = "msm-pcm-routing",
  6427. .codec_name = "msm-stub-codec.1",
  6428. .codec_dai_name = "msm-stub-rx",
  6429. .no_pcm = 1,
  6430. .dpcm_playback = 1,
  6431. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6432. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6433. .ops = &msm_mi2s_be_ops,
  6434. .ignore_suspend = 1,
  6435. .ignore_pmdown_time = 1,
  6436. },
  6437. {
  6438. .name = LPASS_BE_QUIN_MI2S_TX,
  6439. .stream_name = "Quinary MI2S Capture",
  6440. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6441. .platform_name = "msm-pcm-routing",
  6442. .codec_name = "msm-stub-codec.1",
  6443. .codec_dai_name = "msm-stub-tx",
  6444. .no_pcm = 1,
  6445. .dpcm_capture = 1,
  6446. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6447. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6448. .ops = &msm_mi2s_be_ops,
  6449. .ignore_suspend = 1,
  6450. },
  6451. };
  6452. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6453. /* Primary AUX PCM Backend DAI Links */
  6454. {
  6455. .name = LPASS_BE_AUXPCM_RX,
  6456. .stream_name = "AUX PCM Playback",
  6457. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6458. .platform_name = "msm-pcm-routing",
  6459. .codec_name = "msm-stub-codec.1",
  6460. .codec_dai_name = "msm-stub-rx",
  6461. .no_pcm = 1,
  6462. .dpcm_playback = 1,
  6463. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6464. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6465. .ignore_pmdown_time = 1,
  6466. .ignore_suspend = 1,
  6467. },
  6468. {
  6469. .name = LPASS_BE_AUXPCM_TX,
  6470. .stream_name = "AUX PCM Capture",
  6471. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6472. .platform_name = "msm-pcm-routing",
  6473. .codec_name = "msm-stub-codec.1",
  6474. .codec_dai_name = "msm-stub-tx",
  6475. .no_pcm = 1,
  6476. .dpcm_capture = 1,
  6477. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6478. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6479. .ignore_suspend = 1,
  6480. },
  6481. /* Secondary AUX PCM Backend DAI Links */
  6482. {
  6483. .name = LPASS_BE_SEC_AUXPCM_RX,
  6484. .stream_name = "Sec AUX PCM Playback",
  6485. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6486. .platform_name = "msm-pcm-routing",
  6487. .codec_name = "msm-stub-codec.1",
  6488. .codec_dai_name = "msm-stub-rx",
  6489. .no_pcm = 1,
  6490. .dpcm_playback = 1,
  6491. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6492. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6493. .ignore_pmdown_time = 1,
  6494. .ignore_suspend = 1,
  6495. },
  6496. {
  6497. .name = LPASS_BE_SEC_AUXPCM_TX,
  6498. .stream_name = "Sec AUX PCM Capture",
  6499. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6500. .platform_name = "msm-pcm-routing",
  6501. .codec_name = "msm-stub-codec.1",
  6502. .codec_dai_name = "msm-stub-tx",
  6503. .no_pcm = 1,
  6504. .dpcm_capture = 1,
  6505. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6506. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6507. .ignore_suspend = 1,
  6508. },
  6509. /* Tertiary AUX PCM Backend DAI Links */
  6510. {
  6511. .name = LPASS_BE_TERT_AUXPCM_RX,
  6512. .stream_name = "Tert AUX PCM Playback",
  6513. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6514. .platform_name = "msm-pcm-routing",
  6515. .codec_name = "msm-stub-codec.1",
  6516. .codec_dai_name = "msm-stub-rx",
  6517. .no_pcm = 1,
  6518. .dpcm_playback = 1,
  6519. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6520. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6521. .ignore_suspend = 1,
  6522. },
  6523. {
  6524. .name = LPASS_BE_TERT_AUXPCM_TX,
  6525. .stream_name = "Tert AUX PCM Capture",
  6526. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6527. .platform_name = "msm-pcm-routing",
  6528. .codec_name = "msm-stub-codec.1",
  6529. .codec_dai_name = "msm-stub-tx",
  6530. .no_pcm = 1,
  6531. .dpcm_capture = 1,
  6532. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6533. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6534. .ignore_suspend = 1,
  6535. },
  6536. /* Quaternary AUX PCM Backend DAI Links */
  6537. {
  6538. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6539. .stream_name = "Quat AUX PCM Playback",
  6540. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6541. .platform_name = "msm-pcm-routing",
  6542. .codec_name = "msm-stub-codec.1",
  6543. .codec_dai_name = "msm-stub-rx",
  6544. .no_pcm = 1,
  6545. .dpcm_playback = 1,
  6546. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6548. .ignore_pmdown_time = 1,
  6549. .ignore_suspend = 1,
  6550. },
  6551. {
  6552. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6553. .stream_name = "Quat AUX PCM Capture",
  6554. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6555. .platform_name = "msm-pcm-routing",
  6556. .codec_name = "msm-stub-codec.1",
  6557. .codec_dai_name = "msm-stub-tx",
  6558. .no_pcm = 1,
  6559. .dpcm_capture = 1,
  6560. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6561. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6562. .ignore_suspend = 1,
  6563. },
  6564. /* Quinary AUX PCM Backend DAI Links */
  6565. {
  6566. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6567. .stream_name = "Quin AUX PCM Playback",
  6568. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6569. .platform_name = "msm-pcm-routing",
  6570. .codec_name = "msm-stub-codec.1",
  6571. .codec_dai_name = "msm-stub-rx",
  6572. .no_pcm = 1,
  6573. .dpcm_playback = 1,
  6574. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6575. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6576. .ignore_pmdown_time = 1,
  6577. .ignore_suspend = 1,
  6578. },
  6579. {
  6580. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6581. .stream_name = "Quin AUX PCM Capture",
  6582. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6583. .platform_name = "msm-pcm-routing",
  6584. .codec_name = "msm-stub-codec.1",
  6585. .codec_dai_name = "msm-stub-tx",
  6586. .no_pcm = 1,
  6587. .dpcm_capture = 1,
  6588. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6589. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6590. .ignore_suspend = 1,
  6591. },
  6592. };
  6593. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6594. /* WSA CDC DMA Backend DAI Links */
  6595. {
  6596. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6597. .stream_name = "WSA CDC DMA0 Playback",
  6598. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6599. .platform_name = "msm-pcm-routing",
  6600. .codec_name = "bolero_codec",
  6601. .codec_dai_name = "wsa_macro_rx1",
  6602. .no_pcm = 1,
  6603. .dpcm_playback = 1,
  6604. .init = &msm_wsa_cdc_dma_init,
  6605. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6606. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6607. .ignore_pmdown_time = 1,
  6608. .ignore_suspend = 1,
  6609. .ops = &msm_cdc_dma_be_ops,
  6610. },
  6611. {
  6612. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6613. .stream_name = "WSA CDC DMA1 Playback",
  6614. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6615. .platform_name = "msm-pcm-routing",
  6616. .codec_name = "bolero_codec",
  6617. .codec_dai_name = "wsa_macro_rx_mix",
  6618. .no_pcm = 1,
  6619. .dpcm_playback = 1,
  6620. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6621. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6622. .ignore_pmdown_time = 1,
  6623. .ignore_suspend = 1,
  6624. .ops = &msm_cdc_dma_be_ops,
  6625. },
  6626. {
  6627. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6628. .stream_name = "WSA CDC DMA1 Capture",
  6629. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6630. .platform_name = "msm-pcm-routing",
  6631. .codec_name = "bolero_codec",
  6632. .codec_dai_name = "wsa_macro_echo",
  6633. .no_pcm = 1,
  6634. .dpcm_capture = 1,
  6635. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6636. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6637. .ignore_suspend = 1,
  6638. .ops = &msm_cdc_dma_be_ops,
  6639. },
  6640. };
  6641. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6642. {
  6643. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6644. .stream_name = "VA CDC DMA0 Capture",
  6645. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6646. .platform_name = "msm-pcm-routing",
  6647. .codec_name = "bolero_codec",
  6648. .codec_dai_name = "va_macro_tx1",
  6649. .no_pcm = 1,
  6650. .dpcm_capture = 1,
  6651. .init = &msm_va_cdc_dma_init,
  6652. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6654. .ignore_suspend = 1,
  6655. .ops = &msm_cdc_dma_be_ops,
  6656. },
  6657. {
  6658. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6659. .stream_name = "VA CDC DMA1 Capture",
  6660. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6661. .platform_name = "msm-pcm-routing",
  6662. .codec_name = "bolero_codec",
  6663. .codec_dai_name = "va_macro_tx2",
  6664. .no_pcm = 1,
  6665. .dpcm_capture = 1,
  6666. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6668. .ignore_suspend = 1,
  6669. .ops = &msm_cdc_dma_be_ops,
  6670. },
  6671. };
  6672. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6673. {
  6674. .name = LPASS_BE_PRI_SPDIF_RX,
  6675. .stream_name = "Primary SPDIF Playback",
  6676. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6677. .platform_name = "msm-pcm-routing",
  6678. .codec_name = "msm-stub-codec.1",
  6679. .codec_dai_name = "msm-stub-rx",
  6680. .no_pcm = 1,
  6681. .dpcm_playback = 1,
  6682. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6683. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6684. .ops = &msm_spdif_be_ops,
  6685. .ignore_suspend = 1,
  6686. .ignore_pmdown_time = 1,
  6687. },
  6688. {
  6689. .name = LPASS_BE_PRI_SPDIF_TX,
  6690. .stream_name = "Primary SPDIF Capture",
  6691. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6692. .platform_name = "msm-pcm-routing",
  6693. .codec_name = "msm-stub-codec.1",
  6694. .codec_dai_name = "msm-stub-tx",
  6695. .no_pcm = 1,
  6696. .dpcm_capture = 1,
  6697. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6698. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6699. .ops = &msm_spdif_be_ops,
  6700. .ignore_suspend = 1,
  6701. },
  6702. {
  6703. .name = LPASS_BE_SEC_SPDIF_RX,
  6704. .stream_name = "Secondary SPDIF Playback",
  6705. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6706. .platform_name = "msm-pcm-routing",
  6707. .codec_name = "msm-stub-codec.1",
  6708. .codec_dai_name = "msm-stub-rx",
  6709. .no_pcm = 1,
  6710. .dpcm_playback = 1,
  6711. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6712. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6713. .ops = &msm_spdif_be_ops,
  6714. .ignore_suspend = 1,
  6715. .ignore_pmdown_time = 1,
  6716. },
  6717. {
  6718. .name = LPASS_BE_SEC_SPDIF_TX,
  6719. .stream_name = "Secondary SPDIF Capture",
  6720. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6721. .platform_name = "msm-pcm-routing",
  6722. .codec_name = "msm-stub-codec.1",
  6723. .codec_dai_name = "msm-stub-tx",
  6724. .no_pcm = 1,
  6725. .dpcm_capture = 1,
  6726. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6727. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6728. .ops = &msm_spdif_be_ops,
  6729. .ignore_suspend = 1,
  6730. },
  6731. };
  6732. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6733. ARRAY_SIZE(msm_common_dai_links) +
  6734. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6735. ARRAY_SIZE(msm_common_be_dai_links) +
  6736. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6737. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6738. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6739. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6740. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6741. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6742. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6743. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6744. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6745. {
  6746. int ret = 0;
  6747. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6748. &service_nb);
  6749. if (ret < 0)
  6750. pr_err("%s: Audio notifier register failed ret = %d\n",
  6751. __func__, ret);
  6752. return ret;
  6753. }
  6754. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6755. struct snd_ctl_elem_value *ucontrol)
  6756. {
  6757. int ret = 0;
  6758. int port_id;
  6759. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6760. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6761. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6762. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6763. (vad_enable < 0) || (vad_enable > 1) ||
  6764. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6765. pr_err("%s: Invalid arguments\n", __func__);
  6766. ret = -EINVAL;
  6767. goto done;
  6768. }
  6769. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6770. vad_enable, preroll_config, vad_intf);
  6771. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6772. if (ret) {
  6773. pr_err("%s: Invalid vad interface\n", __func__);
  6774. goto done;
  6775. }
  6776. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6777. done:
  6778. return ret;
  6779. }
  6780. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6781. {
  6782. int ret = 0;
  6783. uint32_t tasha_codec = 0;
  6784. ret = afe_cal_init_hwdep(card);
  6785. if (ret) {
  6786. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6787. ret = 0;
  6788. }
  6789. /* tasha late probe when it is present */
  6790. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6791. &tasha_codec);
  6792. if (ret) {
  6793. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6794. ret = 0;
  6795. } else {
  6796. if (tasha_codec) {
  6797. ret = msm_snd_card_tasha_late_probe(card);
  6798. if (ret)
  6799. dev_err(card->dev, "%s: tasha late probe err\n",
  6800. __func__);
  6801. }
  6802. }
  6803. return ret;
  6804. }
  6805. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6806. .name = "qcs405-snd-card",
  6807. .controls = msm_snd_controls,
  6808. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6809. .late_probe = msm_snd_card_codec_late_probe,
  6810. };
  6811. static int msm_populate_dai_link_component_of_node(
  6812. struct snd_soc_card *card)
  6813. {
  6814. int i, index, ret = 0;
  6815. struct device *cdev = card->dev;
  6816. struct snd_soc_dai_link *dai_link = card->dai_link;
  6817. struct device_node *np;
  6818. if (!cdev) {
  6819. pr_err("%s: Sound card device memory NULL\n", __func__);
  6820. return -ENODEV;
  6821. }
  6822. for (i = 0; i < card->num_links; i++) {
  6823. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6824. continue;
  6825. /* populate platform_of_node for snd card dai links */
  6826. if (dai_link[i].platform_name &&
  6827. !dai_link[i].platform_of_node) {
  6828. index = of_property_match_string(cdev->of_node,
  6829. "asoc-platform-names",
  6830. dai_link[i].platform_name);
  6831. if (index < 0) {
  6832. pr_err("%s: No match found for platform name: %s\n",
  6833. __func__, dai_link[i].platform_name);
  6834. ret = index;
  6835. goto err;
  6836. }
  6837. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6838. index);
  6839. if (!np) {
  6840. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6841. __func__, dai_link[i].platform_name,
  6842. index);
  6843. ret = -ENODEV;
  6844. goto err;
  6845. }
  6846. dai_link[i].platform_of_node = np;
  6847. dai_link[i].platform_name = NULL;
  6848. }
  6849. /* populate cpu_of_node for snd card dai links */
  6850. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6851. index = of_property_match_string(cdev->of_node,
  6852. "asoc-cpu-names",
  6853. dai_link[i].cpu_dai_name);
  6854. if (index >= 0) {
  6855. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6856. index);
  6857. if (!np) {
  6858. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6859. __func__,
  6860. dai_link[i].cpu_dai_name);
  6861. ret = -ENODEV;
  6862. goto err;
  6863. }
  6864. dai_link[i].cpu_of_node = np;
  6865. dai_link[i].cpu_dai_name = NULL;
  6866. }
  6867. }
  6868. /* populate codec_of_node for snd card dai links */
  6869. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6870. index = of_property_match_string(cdev->of_node,
  6871. "asoc-codec-names",
  6872. dai_link[i].codec_name);
  6873. if (index < 0)
  6874. continue;
  6875. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6876. index);
  6877. if (!np) {
  6878. pr_err("%s: retrieving phandle for codec %s failed\n",
  6879. __func__, dai_link[i].codec_name);
  6880. ret = -ENODEV;
  6881. goto err;
  6882. }
  6883. dai_link[i].codec_of_node = np;
  6884. dai_link[i].codec_name = NULL;
  6885. }
  6886. }
  6887. err:
  6888. return ret;
  6889. }
  6890. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6891. /* FrontEnd DAI Links */
  6892. {
  6893. .name = "MSMSTUB Media1",
  6894. .stream_name = "MultiMedia1",
  6895. .cpu_dai_name = "MultiMedia1",
  6896. .platform_name = "msm-pcm-dsp.0",
  6897. .dynamic = 1,
  6898. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6899. .dpcm_playback = 1,
  6900. .dpcm_capture = 1,
  6901. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6902. SND_SOC_DPCM_TRIGGER_POST},
  6903. .codec_dai_name = "snd-soc-dummy-dai",
  6904. .codec_name = "snd-soc-dummy",
  6905. .ignore_suspend = 1,
  6906. /* this dainlink has playback support */
  6907. .ignore_pmdown_time = 1,
  6908. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6909. },
  6910. };
  6911. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6912. /* Backend DAI Links */
  6913. {
  6914. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6915. .stream_name = "VA CDC DMA0 Capture",
  6916. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6917. .platform_name = "msm-pcm-routing",
  6918. .codec_name = "bolero_codec",
  6919. .codec_dai_name = "va_macro_tx1",
  6920. .no_pcm = 1,
  6921. .dpcm_capture = 1,
  6922. .init = &msm_va_cdc_dma_init,
  6923. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6924. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6925. .ignore_suspend = 1,
  6926. .ops = &msm_cdc_dma_be_ops,
  6927. },
  6928. {
  6929. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6930. .stream_name = "VA CDC DMA1 Capture",
  6931. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6932. .platform_name = "msm-pcm-routing",
  6933. .codec_name = "bolero_codec",
  6934. .codec_dai_name = "va_macro_tx2",
  6935. .no_pcm = 1,
  6936. .dpcm_capture = 1,
  6937. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6939. .ignore_suspend = 1,
  6940. .ops = &msm_cdc_dma_be_ops,
  6941. },
  6942. };
  6943. static struct snd_soc_dai_link msm_stub_dai_links[
  6944. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6945. ARRAY_SIZE(msm_stub_be_dai_links)];
  6946. struct snd_soc_card snd_soc_card_stub_msm = {
  6947. .name = "qcs405-stub-snd-card",
  6948. };
  6949. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6950. { .compatible = "qcom,qcs405-asoc-snd",
  6951. .data = "codec"},
  6952. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6953. .data = "stub_codec"},
  6954. {},
  6955. };
  6956. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6957. {
  6958. struct snd_soc_card *card = NULL;
  6959. struct snd_soc_dai_link *dailink;
  6960. int total_links = 0;
  6961. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6962. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6963. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6964. const struct of_device_id *match;
  6965. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6966. int rc = 0;
  6967. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6968. if (!match) {
  6969. dev_err(dev, "%s: No DT match found for sound card\n",
  6970. __func__);
  6971. return NULL;
  6972. }
  6973. if (!strcmp(match->data, "codec")) {
  6974. card = &snd_soc_card_qcs405_msm;
  6975. memcpy(msm_qcs405_dai_links + total_links,
  6976. msm_common_dai_links,
  6977. sizeof(msm_common_dai_links));
  6978. total_links += ARRAY_SIZE(msm_common_dai_links);
  6979. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6980. &wsa_bolero_codec);
  6981. if (rc) {
  6982. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6983. __func__);
  6984. } else {
  6985. if (wsa_bolero_codec) {
  6986. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6987. __func__);
  6988. memcpy(msm_qcs405_dai_links + total_links,
  6989. msm_bolero_fe_dai_links,
  6990. sizeof(msm_bolero_fe_dai_links));
  6991. total_links +=
  6992. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6993. }
  6994. }
  6995. memcpy(msm_qcs405_dai_links + total_links,
  6996. msm_common_misc_fe_dai_links,
  6997. sizeof(msm_common_misc_fe_dai_links));
  6998. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6999. memcpy(msm_qcs405_dai_links + total_links,
  7000. msm_common_be_dai_links,
  7001. sizeof(msm_common_be_dai_links));
  7002. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7003. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7004. &tasha_codec);
  7005. if (rc) {
  7006. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7007. __func__);
  7008. } else {
  7009. if (tasha_codec) {
  7010. memcpy(msm_qcs405_dai_links + total_links,
  7011. msm_tasha_be_dai_links,
  7012. sizeof(msm_tasha_be_dai_links));
  7013. total_links +=
  7014. ARRAY_SIZE(msm_tasha_be_dai_links);
  7015. }
  7016. }
  7017. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7018. &va_bolero_codec);
  7019. if (rc) {
  7020. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7021. __func__);
  7022. } else {
  7023. if (va_bolero_codec) {
  7024. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7025. __func__);
  7026. memcpy(msm_qcs405_dai_links + total_links,
  7027. msm_va_cdc_dma_be_dai_links,
  7028. sizeof(msm_va_cdc_dma_be_dai_links));
  7029. total_links +=
  7030. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7031. }
  7032. }
  7033. if (wsa_bolero_codec) {
  7034. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7035. __func__);
  7036. memcpy(msm_qcs405_dai_links + total_links,
  7037. msm_wsa_cdc_dma_be_dai_links,
  7038. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7039. total_links +=
  7040. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7041. }
  7042. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7043. &mi2s_audio_intf);
  7044. if (rc) {
  7045. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7046. __func__);
  7047. } else {
  7048. if (mi2s_audio_intf) {
  7049. memcpy(msm_qcs405_dai_links + total_links,
  7050. msm_mi2s_be_dai_links,
  7051. sizeof(msm_mi2s_be_dai_links));
  7052. total_links +=
  7053. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7054. }
  7055. }
  7056. rc = of_property_read_u32(dev->of_node,
  7057. "qcom,auxpcm-audio-intf",
  7058. &auxpcm_audio_intf);
  7059. if (rc) {
  7060. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7061. __func__);
  7062. } else {
  7063. if (auxpcm_audio_intf) {
  7064. memcpy(msm_qcs405_dai_links + total_links,
  7065. msm_auxpcm_be_dai_links,
  7066. sizeof(msm_auxpcm_be_dai_links));
  7067. total_links +=
  7068. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7069. }
  7070. }
  7071. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7072. &spdif_audio_intf);
  7073. if (rc) {
  7074. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7075. __func__);
  7076. } else {
  7077. if (spdif_audio_intf) {
  7078. memcpy(msm_qcs405_dai_links + total_links,
  7079. msm_spdif_be_dai_links,
  7080. sizeof(msm_spdif_be_dai_links));
  7081. total_links +=
  7082. ARRAY_SIZE(msm_spdif_be_dai_links);
  7083. /* enable spdif coax pins */
  7084. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7085. spdif_pin_ctl =
  7086. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7087. iowrite32(0xc0, spdif_cfg);
  7088. iowrite32(0x2220, spdif_pin_ctl);
  7089. }
  7090. }
  7091. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7092. &wcn_audio_intf);
  7093. if (rc) {
  7094. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7095. __func__);
  7096. } else {
  7097. if (wcn_audio_intf) {
  7098. memcpy(msm_qcs405_dai_links + total_links,
  7099. msm_wcn_be_dai_links,
  7100. sizeof(msm_wcn_be_dai_links));
  7101. total_links +=
  7102. ARRAY_SIZE(msm_wcn_be_dai_links);
  7103. }
  7104. }
  7105. dailink = msm_qcs405_dai_links;
  7106. } else if (!strcmp(match->data, "stub_codec")) {
  7107. card = &snd_soc_card_stub_msm;
  7108. memcpy(msm_stub_dai_links + total_links,
  7109. msm_stub_fe_dai_links,
  7110. sizeof(msm_stub_fe_dai_links));
  7111. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7112. memcpy(msm_stub_dai_links + total_links,
  7113. msm_stub_be_dai_links,
  7114. sizeof(msm_stub_be_dai_links));
  7115. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7116. dailink = msm_stub_dai_links;
  7117. }
  7118. if (card) {
  7119. card->dai_link = dailink;
  7120. card->num_links = total_links;
  7121. }
  7122. return card;
  7123. }
  7124. static int msm_wsa881x_init(struct snd_soc_component *component)
  7125. {
  7126. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7127. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7128. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7129. SPKR_L_BOOST, SPKR_L_VI};
  7130. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7131. SPKR_R_BOOST, SPKR_R_VI};
  7132. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7133. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7134. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7135. struct msm_asoc_mach_data *pdata;
  7136. struct snd_soc_dapm_context *dapm;
  7137. int ret = 0;
  7138. if (!codec) {
  7139. pr_err("%s codec is NULL\n", __func__);
  7140. return -EINVAL;
  7141. }
  7142. dapm = snd_soc_codec_get_dapm(codec);
  7143. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7144. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  7145. __func__, codec->component.name);
  7146. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  7147. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7148. &ch_rate[0], &spkleft_port_types[0]);
  7149. if (dapm->component) {
  7150. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7151. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7152. }
  7153. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7154. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  7155. __func__, codec->component.name);
  7156. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7157. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7158. &ch_rate[0], &spkright_port_types[0]);
  7159. if (dapm->component) {
  7160. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7161. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7162. }
  7163. } else {
  7164. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7165. codec->component.name);
  7166. ret = -EINVAL;
  7167. goto err;
  7168. }
  7169. pdata = snd_soc_card_get_drvdata(component->card);
  7170. if (pdata && pdata->codec_root)
  7171. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7172. codec);
  7173. err:
  7174. return ret;
  7175. }
  7176. static int msm_init_wsa_dev(struct platform_device *pdev,
  7177. struct snd_soc_card *card)
  7178. {
  7179. struct device_node *wsa_of_node;
  7180. u32 wsa_max_devs;
  7181. u32 wsa_dev_cnt;
  7182. int i;
  7183. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7184. const char *wsa_auxdev_name_prefix[1];
  7185. char *dev_name_str = NULL;
  7186. int found = 0;
  7187. int ret = 0;
  7188. /* Get maximum WSA device count for this platform */
  7189. ret = of_property_read_u32(pdev->dev.of_node,
  7190. "qcom,wsa-max-devs", &wsa_max_devs);
  7191. if (ret) {
  7192. dev_info(&pdev->dev,
  7193. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7194. __func__, pdev->dev.of_node->full_name, ret);
  7195. card->num_aux_devs = 0;
  7196. return 0;
  7197. }
  7198. if (wsa_max_devs == 0) {
  7199. dev_warn(&pdev->dev,
  7200. "%s: Max WSA devices is 0 for this target?\n",
  7201. __func__);
  7202. card->num_aux_devs = 0;
  7203. return 0;
  7204. }
  7205. /* Get count of WSA device phandles for this platform */
  7206. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7207. "qcom,wsa-devs", NULL);
  7208. if (wsa_dev_cnt == -ENOENT) {
  7209. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7210. __func__);
  7211. goto err;
  7212. } else if (wsa_dev_cnt <= 0) {
  7213. dev_err(&pdev->dev,
  7214. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7215. __func__, wsa_dev_cnt);
  7216. ret = -EINVAL;
  7217. goto err;
  7218. }
  7219. /*
  7220. * Expect total phandles count to be NOT less than maximum possible
  7221. * WSA count. However, if it is less, then assign same value to
  7222. * max count as well.
  7223. */
  7224. if (wsa_dev_cnt < wsa_max_devs) {
  7225. dev_dbg(&pdev->dev,
  7226. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7227. __func__, wsa_max_devs, wsa_dev_cnt);
  7228. wsa_max_devs = wsa_dev_cnt;
  7229. }
  7230. /* Make sure prefix string passed for each WSA device */
  7231. ret = of_property_count_strings(pdev->dev.of_node,
  7232. "qcom,wsa-aux-dev-prefix");
  7233. if (ret != wsa_dev_cnt) {
  7234. dev_err(&pdev->dev,
  7235. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7236. __func__, wsa_dev_cnt, ret);
  7237. ret = -EINVAL;
  7238. goto err;
  7239. }
  7240. /*
  7241. * Alloc mem to store phandle and index info of WSA device, if already
  7242. * registered with ALSA core
  7243. */
  7244. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7245. sizeof(struct msm_wsa881x_dev_info),
  7246. GFP_KERNEL);
  7247. if (!wsa881x_dev_info) {
  7248. ret = -ENOMEM;
  7249. goto err;
  7250. }
  7251. /*
  7252. * search and check whether all WSA devices are already
  7253. * registered with ALSA core or not. If found a node, store
  7254. * the node and the index in a local array of struct for later
  7255. * use.
  7256. */
  7257. for (i = 0; i < wsa_dev_cnt; i++) {
  7258. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7259. "qcom,wsa-devs", i);
  7260. if (unlikely(!wsa_of_node)) {
  7261. /* we should not be here */
  7262. dev_err(&pdev->dev,
  7263. "%s: wsa dev node is not present\n",
  7264. __func__);
  7265. ret = -EINVAL;
  7266. goto err_free_dev_info;
  7267. }
  7268. if (soc_find_component(wsa_of_node, NULL)) {
  7269. /* WSA device registered with ALSA core */
  7270. wsa881x_dev_info[found].of_node = wsa_of_node;
  7271. wsa881x_dev_info[found].index = i;
  7272. found++;
  7273. if (found == wsa_max_devs)
  7274. break;
  7275. }
  7276. }
  7277. if (found < wsa_max_devs) {
  7278. dev_err(&pdev->dev,
  7279. "%s: failed to find %d components. Found only %d\n",
  7280. __func__, wsa_max_devs, found);
  7281. return -EPROBE_DEFER;
  7282. }
  7283. dev_info(&pdev->dev,
  7284. "%s: found %d wsa881x devices registered with ALSA core\n",
  7285. __func__, found);
  7286. card->num_aux_devs = wsa_max_devs;
  7287. card->num_configs = wsa_max_devs;
  7288. /* Alloc array of AUX devs struct */
  7289. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7290. sizeof(struct snd_soc_aux_dev),
  7291. GFP_KERNEL);
  7292. if (!msm_aux_dev) {
  7293. ret = -ENOMEM;
  7294. goto err_free_dev_info;
  7295. }
  7296. /* Alloc array of codec conf struct */
  7297. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7298. sizeof(struct snd_soc_codec_conf),
  7299. GFP_KERNEL);
  7300. if (!msm_codec_conf) {
  7301. ret = -ENOMEM;
  7302. goto err_free_aux_dev;
  7303. }
  7304. for (i = 0; i < card->num_aux_devs; i++) {
  7305. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7306. GFP_KERNEL);
  7307. if (!dev_name_str) {
  7308. ret = -ENOMEM;
  7309. goto err_free_cdc_conf;
  7310. }
  7311. ret = of_property_read_string_index(pdev->dev.of_node,
  7312. "qcom,wsa-aux-dev-prefix",
  7313. wsa881x_dev_info[i].index,
  7314. wsa_auxdev_name_prefix);
  7315. if (ret) {
  7316. dev_err(&pdev->dev,
  7317. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7318. __func__, ret);
  7319. ret = -EINVAL;
  7320. goto err_free_dev_name_str;
  7321. }
  7322. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7323. msm_aux_dev[i].name = dev_name_str;
  7324. msm_aux_dev[i].codec_name = NULL;
  7325. msm_aux_dev[i].codec_of_node =
  7326. wsa881x_dev_info[i].of_node;
  7327. msm_aux_dev[i].init = msm_wsa881x_init;
  7328. msm_codec_conf[i].dev_name = NULL;
  7329. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7330. msm_codec_conf[i].of_node =
  7331. wsa881x_dev_info[i].of_node;
  7332. }
  7333. card->codec_conf = msm_codec_conf;
  7334. card->aux_dev = msm_aux_dev;
  7335. return 0;
  7336. err_free_dev_name_str:
  7337. devm_kfree(&pdev->dev, dev_name_str);
  7338. err_free_cdc_conf:
  7339. devm_kfree(&pdev->dev, msm_codec_conf);
  7340. err_free_aux_dev:
  7341. devm_kfree(&pdev->dev, msm_aux_dev);
  7342. err_free_dev_info:
  7343. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7344. err:
  7345. return ret;
  7346. }
  7347. static int msm_csra66x0_init(struct snd_soc_component *component)
  7348. {
  7349. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7350. if (!codec) {
  7351. pr_err("%s codec is NULL\n", __func__);
  7352. return -EINVAL;
  7353. }
  7354. return 0;
  7355. }
  7356. static int msm_init_csra_dev(struct platform_device *pdev,
  7357. struct snd_soc_card *card)
  7358. {
  7359. struct device_node *csra_of_node;
  7360. u32 csra_max_devs;
  7361. u32 csra_dev_cnt;
  7362. char *dev_name_str = NULL;
  7363. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7364. const char *csra_auxdev_name_prefix[1];
  7365. int i;
  7366. int found = 0;
  7367. int ret = 0;
  7368. /* Get maximum CSRA device count for this platform */
  7369. ret = of_property_read_u32(pdev->dev.of_node,
  7370. "qcom,csra-max-devs", &csra_max_devs);
  7371. if (ret) {
  7372. dev_info(&pdev->dev,
  7373. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7374. __func__, pdev->dev.of_node->full_name, ret);
  7375. card->num_aux_devs = 0;
  7376. return 0;
  7377. }
  7378. if (csra_max_devs == 0) {
  7379. dev_warn(&pdev->dev,
  7380. "%s: Max CSRA devices is 0 for this target?\n",
  7381. __func__);
  7382. return 0;
  7383. }
  7384. /* Get count of CSRA device phandles for this platform */
  7385. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7386. "qcom,csra-devs", NULL);
  7387. if (csra_dev_cnt == -ENOENT) {
  7388. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7389. __func__);
  7390. goto err;
  7391. } else if (csra_dev_cnt <= 0) {
  7392. dev_err(&pdev->dev,
  7393. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7394. __func__, csra_dev_cnt);
  7395. ret = -EINVAL;
  7396. goto err;
  7397. }
  7398. /*
  7399. * Expect total phandles count to be NOT less than maximum possible
  7400. * CSRA count. However, if it is less, then assign same value to
  7401. * max count as well.
  7402. */
  7403. if (csra_dev_cnt < csra_max_devs) {
  7404. dev_dbg(&pdev->dev,
  7405. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7406. __func__, csra_max_devs, csra_dev_cnt);
  7407. csra_max_devs = csra_dev_cnt;
  7408. }
  7409. /* Make sure prefix string passed for each CSRA device */
  7410. ret = of_property_count_strings(pdev->dev.of_node,
  7411. "qcom,csra-aux-dev-prefix");
  7412. if (ret != csra_dev_cnt) {
  7413. dev_err(&pdev->dev,
  7414. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7415. __func__, csra_dev_cnt, ret);
  7416. ret = -EINVAL;
  7417. goto err;
  7418. }
  7419. /*
  7420. * Alloc mem to store phandle and index info of CSRA device, if already
  7421. * registered with ALSA core
  7422. */
  7423. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7424. sizeof(struct msm_csra66x0_dev_info),
  7425. GFP_KERNEL);
  7426. if (!csra66x0_dev_info) {
  7427. ret = -ENOMEM;
  7428. goto err;
  7429. }
  7430. /*
  7431. * search and check whether all CSRA devices are already
  7432. * registered with ALSA core or not. If found a node, store
  7433. * the node and the index in a local array of struct for later
  7434. * use.
  7435. */
  7436. for (i = 0; i < csra_dev_cnt; i++) {
  7437. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7438. "qcom,csra-devs", i);
  7439. if (unlikely(!csra_of_node)) {
  7440. /* we should not be here */
  7441. dev_err(&pdev->dev,
  7442. "%s: csra dev node is not present\n",
  7443. __func__);
  7444. ret = -EINVAL;
  7445. goto err_free_dev_info;
  7446. }
  7447. if (soc_find_component(csra_of_node, NULL)) {
  7448. /* CSRA device registered with ALSA core */
  7449. csra66x0_dev_info[found].of_node = csra_of_node;
  7450. csra66x0_dev_info[found].index = i;
  7451. found++;
  7452. if (found == csra_max_devs)
  7453. break;
  7454. }
  7455. }
  7456. if (found < csra_max_devs) {
  7457. dev_dbg(&pdev->dev,
  7458. "%s: failed to find %d components. Found only %d\n",
  7459. __func__, csra_max_devs, found);
  7460. return -EPROBE_DEFER;
  7461. }
  7462. dev_info(&pdev->dev,
  7463. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7464. __func__, found);
  7465. card->num_aux_devs = csra_max_devs;
  7466. card->num_configs = csra_max_devs;
  7467. /* Alloc array of AUX devs struct */
  7468. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7469. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7470. if (!msm_aux_dev) {
  7471. ret = -ENOMEM;
  7472. goto err_free_dev_info;
  7473. }
  7474. /* Alloc array of codec conf struct */
  7475. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7476. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7477. if (!msm_codec_conf) {
  7478. ret = -ENOMEM;
  7479. goto err_free_aux_dev;
  7480. }
  7481. for (i = 0; i < card->num_aux_devs; i++) {
  7482. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7483. GFP_KERNEL);
  7484. if (!dev_name_str) {
  7485. ret = -ENOMEM;
  7486. goto err_free_cdc_conf;
  7487. }
  7488. ret = of_property_read_string_index(pdev->dev.of_node,
  7489. "qcom,csra-aux-dev-prefix",
  7490. csra66x0_dev_info[i].index,
  7491. csra_auxdev_name_prefix);
  7492. if (ret) {
  7493. dev_err(&pdev->dev,
  7494. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7495. __func__, ret);
  7496. ret = -EINVAL;
  7497. goto err_free_dev_name_str;
  7498. }
  7499. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7500. msm_aux_dev[i].name = dev_name_str;
  7501. msm_aux_dev[i].codec_name = NULL;
  7502. msm_aux_dev[i].codec_of_node =
  7503. csra66x0_dev_info[i].of_node;
  7504. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7505. msm_codec_conf[i].dev_name = NULL;
  7506. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7507. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7508. }
  7509. card->codec_conf = msm_codec_conf;
  7510. card->aux_dev = msm_aux_dev;
  7511. return 0;
  7512. err_free_dev_name_str:
  7513. devm_kfree(&pdev->dev, dev_name_str);
  7514. err_free_cdc_conf:
  7515. devm_kfree(&pdev->dev, msm_codec_conf);
  7516. err_free_aux_dev:
  7517. devm_kfree(&pdev->dev, msm_aux_dev);
  7518. err_free_dev_info:
  7519. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7520. err:
  7521. return ret;
  7522. }
  7523. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7524. {
  7525. int count;
  7526. u32 mi2s_master_slave[MI2S_MAX];
  7527. int ret;
  7528. for (count = 0; count < MI2S_MAX; count++) {
  7529. mutex_init(&mi2s_intf_conf[count].lock);
  7530. mi2s_intf_conf[count].ref_cnt = 0;
  7531. }
  7532. ret = of_property_read_u32_array(pdev->dev.of_node,
  7533. "qcom,msm-mi2s-master",
  7534. mi2s_master_slave, MI2S_MAX);
  7535. if (ret) {
  7536. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7537. __func__);
  7538. } else {
  7539. for (count = 0; count < MI2S_MAX; count++) {
  7540. mi2s_intf_conf[count].msm_is_mi2s_master =
  7541. mi2s_master_slave[count];
  7542. }
  7543. }
  7544. }
  7545. static void msm_i2s_auxpcm_deinit(void)
  7546. {
  7547. int count;
  7548. for (count = 0; count < MI2S_MAX; count++) {
  7549. mutex_destroy(&mi2s_intf_conf[count].lock);
  7550. mi2s_intf_conf[count].ref_cnt = 0;
  7551. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7552. }
  7553. }
  7554. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7555. uint32_t busnum, uint32_t addr)
  7556. {
  7557. struct i2c_adapter *adap;
  7558. u8 rbuf;
  7559. struct i2c_msg msg;
  7560. int status = 0;
  7561. adap = i2c_get_adapter(busnum);
  7562. if (!adap) {
  7563. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7564. __func__, busnum);
  7565. return -EBUSY;
  7566. }
  7567. /* to test presence, read one byte from device */
  7568. msg.addr = addr;
  7569. msg.flags = I2C_M_RD;
  7570. msg.len = 1;
  7571. msg.buf = &rbuf;
  7572. status = i2c_transfer(adap, &msg, 1);
  7573. i2c_put_adapter(adap);
  7574. if (status != 1) {
  7575. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7576. __func__, addr);
  7577. return -ENODEV;
  7578. }
  7579. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7580. __func__, addr);
  7581. return 0;
  7582. }
  7583. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7584. struct snd_soc_card *card)
  7585. {
  7586. int i;
  7587. uint32_t ep92_busnum = 0;
  7588. uint32_t ep92_reg = 0;
  7589. const char *ep92_name = NULL;
  7590. struct snd_soc_dai_link *dai;
  7591. int rc = 0;
  7592. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7593. &ep92_busnum);
  7594. if (rc) {
  7595. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7596. return 0;
  7597. }
  7598. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7599. &ep92_reg);
  7600. if (rc) {
  7601. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7602. return 0;
  7603. }
  7604. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7605. &ep92_name);
  7606. if (rc) {
  7607. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7608. return 0;
  7609. }
  7610. /* check I2C bus for connected ep92 chip */
  7611. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7612. /* check a second time after a short delay */
  7613. msleep(20);
  7614. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7615. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7616. __func__);
  7617. /* continue with snd_card registration without ep92 */
  7618. return 0;
  7619. }
  7620. }
  7621. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7622. /* update codec info in MI2S dai link */
  7623. dai = &msm_mi2s_be_dai_links[0];
  7624. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7625. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7626. dev_dbg(&pdev->dev,
  7627. "%s: Set Sec MI2S dai to ep92 codec\n",
  7628. __func__);
  7629. dai->codec_name = ep92_name;
  7630. dai->codec_dai_name = "ep92-hdmi";
  7631. break;
  7632. }
  7633. dai++;
  7634. }
  7635. /* update codec info in SPDIF dai link */
  7636. dai = &msm_spdif_be_dai_links[0];
  7637. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7638. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7639. dev_dbg(&pdev->dev,
  7640. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7641. __func__);
  7642. dai->codec_name = ep92_name;
  7643. dai->codec_dai_name = "ep92-arc";
  7644. break;
  7645. }
  7646. dai++;
  7647. }
  7648. return 0;
  7649. }
  7650. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7651. {
  7652. struct snd_soc_card *card;
  7653. struct msm_asoc_mach_data *pdata;
  7654. int ret;
  7655. u32 val;
  7656. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7657. const char *micb_supply_str1 = "tdm-vdd-micb";
  7658. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7659. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7660. if (!pdev->dev.of_node) {
  7661. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7662. return -EINVAL;
  7663. }
  7664. pdata = devm_kzalloc(&pdev->dev,
  7665. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7666. if (!pdata)
  7667. return -ENOMEM;
  7668. /* test for ep92 HDMI bridge and update dai links accordingly */
  7669. ret = msm_detect_ep92_dev(pdev, card);
  7670. if (ret)
  7671. goto err;
  7672. card = populate_snd_card_dailinks(&pdev->dev);
  7673. if (!card) {
  7674. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7675. ret = -EINVAL;
  7676. goto err;
  7677. }
  7678. card->dev = &pdev->dev;
  7679. platform_set_drvdata(pdev, card);
  7680. snd_soc_card_set_drvdata(card, pdata);
  7681. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7682. if (ret) {
  7683. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7684. ret);
  7685. goto err;
  7686. }
  7687. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7688. if (ret) {
  7689. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7690. ret);
  7691. goto err;
  7692. }
  7693. ret = msm_populate_dai_link_component_of_node(card);
  7694. if (ret) {
  7695. ret = -EPROBE_DEFER;
  7696. goto err;
  7697. }
  7698. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7699. if (ret) {
  7700. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7701. val = 0;
  7702. }
  7703. if (val) {
  7704. pdata->codec_is_csra = true;
  7705. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7706. ret = msm_init_csra_dev(pdev, card);
  7707. if (ret)
  7708. goto err;
  7709. } else {
  7710. pdata->codec_is_csra = false;
  7711. ret = msm_init_wsa_dev(pdev, card);
  7712. if (ret)
  7713. goto err;
  7714. }
  7715. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7716. "qcom,cdc-dmic01-gpios", 0);
  7717. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7718. "qcom,cdc-dmic23-gpios", 0);
  7719. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7720. "qcom,cdc-dmic45-gpios", 0);
  7721. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7722. "qcom,cdc-dmic67-gpios", 0);
  7723. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7724. "qcom,pri-mi2s-gpios", 0);
  7725. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7726. "qcom,sec-mi2s-gpios", 0);
  7727. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7728. "qcom,tert-mi2s-gpios", 0);
  7729. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7730. "qcom,quat-mi2s-gpios", 0);
  7731. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7732. "qcom,quin-mi2s-gpios", 0);
  7733. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7734. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7735. micb_supply_str1);
  7736. if (IS_ERR(pdata->tdm_micb_supply)) {
  7737. ret = PTR_ERR(pdata->tdm_micb_supply);
  7738. dev_err(&pdev->dev,
  7739. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7740. __func__, ret);
  7741. }
  7742. ret = of_property_read_u32(pdev->dev.of_node,
  7743. micb_voltage_str,
  7744. &pdata->tdm_micb_voltage);
  7745. if (ret) {
  7746. dev_err(&pdev->dev,
  7747. "%s:Looking up %s property in node %s failed\n",
  7748. __func__, micb_voltage_str,
  7749. pdev->dev.of_node->full_name);
  7750. }
  7751. ret = of_property_read_u32(pdev->dev.of_node,
  7752. micb_current_str,
  7753. &pdata->tdm_micb_current);
  7754. if (ret) {
  7755. dev_err(&pdev->dev,
  7756. "%s:Looking up %s property in node %s failed\n",
  7757. __func__, micb_current_str,
  7758. pdev->dev.of_node->full_name);
  7759. }
  7760. }
  7761. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7762. if (ret == -EPROBE_DEFER) {
  7763. if (codec_reg_done)
  7764. ret = -EINVAL;
  7765. goto err;
  7766. } else if (ret) {
  7767. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7768. ret);
  7769. goto err;
  7770. }
  7771. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7772. spdev = pdev;
  7773. ret = msm_mdf_mem_init();
  7774. if (ret)
  7775. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7776. ret);
  7777. msm_i2s_auxpcm_init(pdev);
  7778. is_initial_boot = true;
  7779. return 0;
  7780. err:
  7781. return ret;
  7782. }
  7783. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7784. {
  7785. audio_notifier_deregister("qcs405");
  7786. msm_i2s_auxpcm_deinit();
  7787. msm_mdf_mem_deinit();
  7788. return 0;
  7789. }
  7790. static struct platform_driver qcs405_asoc_machine_driver = {
  7791. .driver = {
  7792. .name = DRV_NAME,
  7793. .owner = THIS_MODULE,
  7794. .pm = &snd_soc_pm_ops,
  7795. .of_match_table = qcs405_asoc_machine_of_match,
  7796. },
  7797. .probe = msm_asoc_machine_probe,
  7798. .remove = msm_asoc_machine_remove,
  7799. };
  7800. module_platform_driver(qcs405_asoc_machine_driver);
  7801. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7802. MODULE_LICENSE("GPL v2");
  7803. MODULE_ALIAS("platform:" DRV_NAME);
  7804. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);