hal_5332.c 86 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
  16. */
  17. #include "qdf_types.h"
  18. #include "qdf_util.h"
  19. #include "qdf_mem.h"
  20. #include "qdf_nbuf.h"
  21. #include "qdf_module.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "hal_be_hw_headers.h"
  25. #include "hal_internal.h"
  26. #include "hal_api.h"
  27. #include "hal_flow.h"
  28. #include "rx_flow_search_entry.h"
  29. #include "hal_rx_flow_info.h"
  30. #include "hal_be_api.h"
  31. #include "tcl_entrance_from_ppe_ring.h"
  32. #include "sw_monitor_ring.h"
  33. #include "wcss_seq_hwioreg_umac.h"
  34. #include "wfss_ce_reg_seq_hwioreg.h"
  35. #include <uniform_reo_status_header.h>
  36. #include <wbm_release_ring_tx.h>
  37. #include <phyrx_location.h>
  38. #ifdef QCA_MONITOR_2_0_SUPPORT
  39. #include <mon_ingress_ring.h>
  40. #include <mon_destination_ring.h>
  41. #endif
  42. #include "rx_reo_queue_1k.h"
  43. #include <hal_be_rx.h>
  44. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  45. RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
  46. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  47. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  48. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  49. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  50. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  51. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  52. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  53. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  54. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
  55. STATUS_HEADER_REO_STATUS_NUMBER
  56. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  57. STATUS_HEADER_TIMESTAMP
  58. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  59. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  60. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  61. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  62. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  63. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  64. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  65. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  66. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  67. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
  68. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  69. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
  70. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  71. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
  72. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  73. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
  74. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  75. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
  76. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  77. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
  78. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  79. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
  80. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  81. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
  82. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  83. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
  84. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  85. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
  86. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  87. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
  88. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  89. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  90. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  91. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  92. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  93. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  94. #include "hal_be_api_mon.h"
  95. #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
  96. #define CMEM_REG_BASE 0x0010e000
  97. #define CMEM_WINDOW_ADDRESS_5332 \
  98. ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  99. #endif
  100. #define CE_WINDOW_ADDRESS_5332 \
  101. ((CE_CFG_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  102. #define UMAC_WINDOW_ADDRESS_5332 \
  103. ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  104. #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
  105. #define WINDOW_CONFIGURATION_VALUE_5332 \
  106. ((CE_WINDOW_ADDRESS_5332 << 6) |\
  107. (UMAC_WINDOW_ADDRESS_5332 << 12) | \
  108. CMEM_WINDOW_ADDRESS_5332 | \
  109. WINDOW_ENABLE_BIT)
  110. #else
  111. #define WINDOW_CONFIGURATION_VALUE_5332 \
  112. ((CE_WINDOW_ADDRESS_5332 << 6) |\
  113. (UMAC_WINDOW_ADDRESS_5332 << 12) | \
  114. WINDOW_ENABLE_BIT)
  115. #endif
  116. /* For Berryllium sw2rxdma ring size increased to 20 bits */
  117. #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
  118. #ifdef CONFIG_WORD_BASED_TLV
  119. #ifndef BIG_ENDIAN_HOST
  120. struct rx_msdu_end_compact_qca5332 {
  121. uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
  122. sw_frame_group_id : 7, // [8:2]
  123. reserved_0 : 7, // [15:9]
  124. phy_ppdu_id : 16; // [31:16]
  125. uint32_t ip_hdr_chksum : 16, // [15:0]
  126. reported_mpdu_length : 14, // [29:16]
  127. reserved_1a : 2; // [31:30]
  128. uint32_t key_id_octet : 8, // [7:0]
  129. cce_super_rule : 6, // [13:8]
  130. cce_classify_not_done_truncate : 1, // [14:14]
  131. cce_classify_not_done_cce_dis : 1, // [15:15]
  132. cumulative_l3_checksum : 16; // [31:16]
  133. uint32_t rule_indication_31_0 : 32; // [31:0]
  134. uint32_t rule_indication_63_32 : 32; // [31:0]
  135. uint32_t da_offset : 6, // [5:0]
  136. sa_offset : 6, // [11:6]
  137. da_offset_valid : 1, // [12:12]
  138. sa_offset_valid : 1, // [13:13]
  139. reserved_5a : 2, // [15:14]
  140. l3_type : 16; // [31:16]
  141. uint32_t ipv6_options_crc : 32; // [31:0]
  142. uint32_t tcp_seq_number : 32; // [31:0]
  143. uint32_t tcp_ack_number : 32; // [31:0]
  144. uint32_t tcp_flag : 9, // [8:0]
  145. lro_eligible : 1, // [9:9]
  146. reserved_9a : 6, // [15:10]
  147. window_size : 16; // [31:16]
  148. uint32_t tcp_udp_chksum : 16, // [15:0]
  149. sa_idx_timeout : 1, // [16:16]
  150. da_idx_timeout : 1, // [17:17]
  151. msdu_limit_error : 1, // [18:18]
  152. flow_idx_timeout : 1, // [19:19]
  153. flow_idx_invalid : 1, // [20:20]
  154. wifi_parser_error : 1, // [21:21]
  155. amsdu_parser_error : 1, // [22:22]
  156. sa_is_valid : 1, // [23:23]
  157. da_is_valid : 1, // [24:24]
  158. da_is_mcbc : 1, // [25:25]
  159. l3_header_padding : 2, // [27:26]
  160. first_msdu : 1, // [28:28]
  161. last_msdu : 1, // [29:29]
  162. tcp_udp_chksum_fail_copy : 1, // [30:30]
  163. ip_chksum_fail_copy : 1; // [31:31]
  164. uint32_t sa_idx : 16, // [15:0]
  165. da_idx_or_sw_peer_id : 16; // [31:16]
  166. uint32_t msdu_drop : 1, // [0:0]
  167. reo_destination_indication : 5, // [5:1]
  168. flow_idx : 20, // [25:6]
  169. use_ppe : 1, // [26:26]
  170. reserved_12a : 5; // [31:27]
  171. uint32_t fse_metadata : 32; // [31:0]
  172. uint32_t cce_metadata : 16, // [15:0]
  173. sa_sw_peer_id : 16; // [31:16]
  174. uint32_t aggregation_count : 8, // [7:0]
  175. flow_aggregation_continuation : 1, // [8:8]
  176. fisa_timeout : 1, // [9:9]
  177. reserved_15a : 22; // [31:10]
  178. uint32_t cumulative_l4_checksum : 16, // [15:0]
  179. cumulative_ip_length : 16; // [31:16]
  180. uint32_t reserved_17a : 6, // [5:0]
  181. service_code : 9, // [14:6]
  182. priority_valid : 1, // [15:15]
  183. intra_bss : 1, // [16:16]
  184. dest_chip_id : 2, // [18:17]
  185. multicast_echo : 1, // [19:19]
  186. wds_learning_event : 1, // [20:20]
  187. wds_roaming_event : 1, // [21:21]
  188. wds_keep_alive_event : 1, // [22:22]
  189. reserved_17b : 9; // [31:23]
  190. uint32_t msdu_length : 14, // [13:0]
  191. stbc : 1, // [14:14]
  192. ipsec_esp : 1, // [15:15]
  193. l3_offset : 7, // [22:16]
  194. ipsec_ah : 1, // [23:23]
  195. l4_offset : 8; // [31:24]
  196. uint32_t msdu_number : 8, // [7:0]
  197. decap_format : 2, // [9:8]
  198. ipv4_proto : 1, // [10:10]
  199. ipv6_proto : 1, // [11:11]
  200. tcp_proto : 1, // [12:12]
  201. udp_proto : 1, // [13:13]
  202. ip_frag : 1, // [14:14]
  203. tcp_only_ack : 1, // [15:15]
  204. da_is_bcast_mcast : 1, // [16:16]
  205. toeplitz_hash_sel : 2, // [18:17]
  206. ip_fixed_header_valid : 1, // [19:19]
  207. ip_extn_header_valid : 1, // [20:20]
  208. tcp_udp_header_valid : 1, // [21:21]
  209. mesh_control_present : 1, // [22:22]
  210. ldpc : 1, // [23:23]
  211. ip4_protocol_ip6_next_header : 8; // [31:24]
  212. uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
  213. uint32_t flow_id_toeplitz : 32; // [31:0]
  214. uint32_t user_rssi : 8, // [7:0]
  215. pkt_type : 4, // [11:8]
  216. sgi : 2, // [13:12]
  217. rate_mcs : 4, // [17:14]
  218. receive_bandwidth : 3, // [20:18]
  219. reception_type : 3, // [23:21]
  220. mimo_ss_bitmap : 8; // [31:24]
  221. uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
  222. uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
  223. uint32_t sw_phy_meta_data : 32; // [31:0]
  224. uint32_t vlan_ctag_ci : 16, // [15:0]
  225. vlan_stag_ci : 16; // [31:16]
  226. uint32_t reserved_27a : 32; // [31:0]
  227. uint32_t reserved_28a : 32; // [31:0]
  228. uint32_t reserved_29a : 32; // [31:0]
  229. uint32_t first_mpdu : 1, // [0:0]
  230. reserved_30a : 1, // [1:1]
  231. mcast_bcast : 1, // [2:2]
  232. ast_index_not_found : 1, // [3:3]
  233. ast_index_timeout : 1, // [4:4]
  234. power_mgmt : 1, // [5:5]
  235. non_qos : 1, // [6:6]
  236. null_data : 1, // [7:7]
  237. mgmt_type : 1, // [8:8]
  238. ctrl_type : 1, // [9:9]
  239. more_data : 1, // [10:10]
  240. eosp : 1, // [11:11]
  241. a_msdu_error : 1, // [12:12]
  242. fragment_flag : 1, // [13:13]
  243. order : 1, // [14:14]
  244. cce_match : 1, // [15:15]
  245. overflow_err : 1, // [16:16]
  246. msdu_length_err : 1, // [17:17]
  247. tcp_udp_chksum_fail : 1, // [18:18]
  248. ip_chksum_fail : 1, // [19:19]
  249. sa_idx_invalid : 1, // [20:20]
  250. da_idx_invalid : 1, // [21:21]
  251. reserved_30b : 1, // [22:22]
  252. rx_in_tx_decrypt_byp : 1, // [23:23]
  253. encrypt_required : 1, // [24:24]
  254. directed : 1, // [25:25]
  255. buffer_fragment : 1, // [26:26]
  256. mpdu_length_err : 1, // [27:27]
  257. tkip_mic_err : 1, // [28:28]
  258. decrypt_err : 1, // [29:29]
  259. unencrypted_frame_err : 1, // [30:30]
  260. fcs_err : 1; // [31:31]
  261. uint32_t reserved_31a : 10, // [9:0]
  262. decrypt_status_code : 3, // [12:10]
  263. rx_bitmap_not_updated : 1, // [13:13]
  264. reserved_31b : 17, // [30:14]
  265. msdu_done : 1; // [31:31]
  266. };
  267. struct rx_mpdu_start_compact_qca5332 {
  268. struct rxpt_classify_info rxpt_classify_info_details;
  269. uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
  270. uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
  271. receive_queue_number : 16, // [23:8]
  272. pre_delim_err_warning : 1, // [24:24]
  273. first_delim_err : 1, // [25:25]
  274. reserved_2a : 6; // [31:26]
  275. uint32_t pn_31_0 : 32; // [31:0]
  276. uint32_t pn_63_32 : 32; // [31:0]
  277. uint32_t pn_95_64 : 32; // [31:0]
  278. uint32_t pn_127_96 : 32; // [31:0]
  279. uint32_t epd_en : 1, // [0:0]
  280. all_frames_shall_be_encrypted : 1, // [1:1]
  281. encrypt_type : 4, // [5:2]
  282. wep_key_width_for_variable_key : 2, // [7:6]
  283. mesh_sta : 2, // [9:8]
  284. bssid_hit : 1, // [10:10]
  285. bssid_number : 4, // [14:11]
  286. tid : 4, // [18:15]
  287. reserved_7a : 13; // [31:19]
  288. uint32_t peer_meta_data : 32; // [31:0]
  289. uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
  290. sw_frame_group_id : 7, // [8:2]
  291. ndp_frame : 1, // [9:9]
  292. phy_err : 1, // [10:10]
  293. phy_err_during_mpdu_header : 1, // [11:11]
  294. protocol_version_err : 1, // [12:12]
  295. ast_based_lookup_valid : 1, // [13:13]
  296. ranging : 1, // [14:14]
  297. reserved_9a : 1, // [15:15]
  298. phy_ppdu_id : 16; // [31:16]
  299. uint32_t ast_index : 16, // [15:0]
  300. sw_peer_id : 16; // [31:16]
  301. uint32_t mpdu_frame_control_valid : 1, // [0:0]
  302. mpdu_duration_valid : 1, // [1:1]
  303. mac_addr_ad1_valid : 1, // [2:2]
  304. mac_addr_ad2_valid : 1, // [3:3]
  305. mac_addr_ad3_valid : 1, // [4:4]
  306. mac_addr_ad4_valid : 1, // [5:5]
  307. mpdu_sequence_control_valid : 1, // [6:6]
  308. mpdu_qos_control_valid : 1, // [7:7]
  309. mpdu_ht_control_valid : 1, // [8:8]
  310. frame_encryption_info_valid : 1, // [9:9]
  311. mpdu_fragment_number : 4, // [13:10]
  312. more_fragment_flag : 1, // [14:14]
  313. reserved_11a : 1, // [15:15]
  314. fr_ds : 1, // [16:16]
  315. to_ds : 1, // [17:17]
  316. encrypted : 1, // [18:18]
  317. mpdu_retry : 1, // [19:19]
  318. mpdu_sequence_number : 12; // [31:20]
  319. uint32_t key_id_octet : 8, // [7:0]
  320. new_peer_entry : 1, // [8:8]
  321. decrypt_needed : 1, // [9:9]
  322. decap_type : 2, // [11:10]
  323. rx_insert_vlan_c_tag_padding : 1, // [12:12]
  324. rx_insert_vlan_s_tag_padding : 1, // [13:13]
  325. strip_vlan_c_tag_decap : 1, // [14:14]
  326. strip_vlan_s_tag_decap : 1, // [15:15]
  327. pre_delim_count : 12, // [27:16]
  328. ampdu_flag : 1, // [28:28]
  329. bar_frame : 1, // [29:29]
  330. raw_mpdu : 1, // [30:30]
  331. reserved_12 : 1; // [31:31]
  332. uint32_t mpdu_length : 14, // [13:0]
  333. first_mpdu : 1, // [14:14]
  334. mcast_bcast : 1, // [15:15]
  335. ast_index_not_found : 1, // [16:16]
  336. ast_index_timeout : 1, // [17:17]
  337. power_mgmt : 1, // [18:18]
  338. non_qos : 1, // [19:19]
  339. null_data : 1, // [20:20]
  340. mgmt_type : 1, // [21:21]
  341. ctrl_type : 1, // [22:22]
  342. more_data : 1, // [23:23]
  343. eosp : 1, // [24:24]
  344. fragment_flag : 1, // [25:25]
  345. order : 1, // [26:26]
  346. u_apsd_trigger : 1, // [27:27]
  347. encrypt_required : 1, // [28:28]
  348. directed : 1, // [29:29]
  349. amsdu_present : 1, // [30:30]
  350. reserved_13 : 1; // [31:31]
  351. uint32_t mpdu_frame_control_field : 16, // [15:0]
  352. mpdu_duration_field : 16; // [31:16]
  353. uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
  354. uint32_t mac_addr_ad1_47_32 : 16, // [15:0]
  355. mac_addr_ad2_15_0 : 16; // [31:16]
  356. uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
  357. uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
  358. uint32_t mac_addr_ad3_47_32 : 16, // [15:0]
  359. mpdu_sequence_control_field : 16; // [31:16]
  360. uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
  361. uint32_t mac_addr_ad4_47_32 : 16, // [15:0]
  362. mpdu_qos_control_field : 16; // [31:16]
  363. uint32_t mpdu_ht_control_field : 32; // [31:0]
  364. uint32_t vdev_id : 8, // [7:0]
  365. service_code : 9, // [16:8]
  366. priority_valid : 1, // [17:17]
  367. src_info : 12, // [29:18]
  368. reserved_23a : 1, // [30:30]
  369. multi_link_addr_ad1_ad2_valid : 1; // [31:31]
  370. uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
  371. uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0]
  372. multi_link_addr_ad2_15_0 : 16; // [31:16]
  373. uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
  374. uint32_t reserved_27a : 32; // [31:0]
  375. uint32_t reserved_28a : 32; // [31:0]
  376. uint32_t reserved_29a : 32; // [31:0]
  377. };
  378. #else
  379. struct rx_msdu_end_compact_qca5332 {
  380. uint32_t phy_ppdu_id : 16, // [31:16]
  381. reserved_0 : 7, // [15:9]
  382. sw_frame_group_id : 7, // [8:2]
  383. rxpcu_mpdu_filter_in_category : 2; // [1:0]
  384. uint32_t reserved_1a : 2, // [31:30]
  385. reported_mpdu_length : 14, // [29:16]
  386. ip_hdr_chksum : 16; // [15:0]
  387. uint32_t cumulative_l3_checksum : 16, // [31:16]
  388. cce_classify_not_done_cce_dis : 1, // [15:15]
  389. cce_classify_not_done_truncate : 1, // [14:14]
  390. cce_super_rule : 6, // [13:8]
  391. key_id_octet : 8; // [7:0]
  392. uint32_t rule_indication_31_0 : 32; // [31:0]
  393. uint32_t rule_indication_63_32 : 32; // [31:0]
  394. uint32_t l3_type : 16, // [31:16]
  395. reserved_5a : 2, // [15:14]
  396. sa_offset_valid : 1, // [13:13]
  397. da_offset_valid : 1, // [12:12]
  398. sa_offset : 6, // [11:6]
  399. da_offset : 6; // [5:0]
  400. uint32_t ipv6_options_crc : 32; // [31:0]
  401. uint32_t tcp_seq_number : 32; // [31:0]
  402. uint32_t tcp_ack_number : 32; // [31:0]
  403. uint32_t window_size : 16, // [31:16]
  404. reserved_9a : 6, // [15:10]
  405. lro_eligible : 1, // [9:9]
  406. tcp_flag : 9; // [8:0]
  407. uint32_t ip_chksum_fail_copy : 1, // [31:31]
  408. tcp_udp_chksum_fail_copy : 1, // [30:30]
  409. last_msdu : 1, // [29:29]
  410. first_msdu : 1, // [28:28]
  411. l3_header_padding : 2, // [27:26]
  412. da_is_mcbc : 1, // [25:25]
  413. da_is_valid : 1, // [24:24]
  414. sa_is_valid : 1, // [23:23]
  415. amsdu_parser_error : 1, // [22:22]
  416. wifi_parser_error : 1, // [21:21]
  417. flow_idx_invalid : 1, // [20:20]
  418. flow_idx_timeout : 1, // [19:19]
  419. msdu_limit_error : 1, // [18:18]
  420. da_idx_timeout : 1, // [17:17]
  421. sa_idx_timeout : 1, // [16:16]
  422. tcp_udp_chksum : 16; // [15:0]
  423. uint32_t da_idx_or_sw_peer_id : 16, // [31:16]
  424. sa_idx : 16; // [15:0]
  425. uint32_t reserved_12a : 5, // [31:27]
  426. use_ppe : 1, // [26:26]
  427. flow_idx : 20, // [25:6]
  428. reo_destination_indication : 5, // [5:1]
  429. msdu_drop : 1; // [0:0]
  430. uint32_t fse_metadata : 32; // [31:0]
  431. uint32_t sa_sw_peer_id : 16, // [31:16]
  432. cce_metadata : 16; // [15:0]
  433. uint32_t reserved_15a : 22, // [31:10]
  434. fisa_timeout : 1, // [9:9]
  435. flow_aggregation_continuation : 1, // [8:8]
  436. aggregation_count : 8; // [7:0]
  437. uint32_t cumulative_ip_length : 16, // [31:16]
  438. cumulative_l4_checksum : 16; // [15:0]
  439. uint32_t reserved_17b : 9, // [31:23]
  440. wds_keep_alive_event : 1, // [22:22]
  441. wds_roaming_event : 1, // [21:21]
  442. wds_learning_event : 1, // [20:20]
  443. multicast_echo : 1, // [19:19]
  444. dest_chip_id : 2, // [18:17]
  445. intra_bss : 1, // [16:16]
  446. priority_valid : 1, // [15:15]
  447. service_code : 9, // [14:6]
  448. reserved_17a : 6; // [5:0]
  449. uint32_t l4_offset : 8, // [31:24]
  450. ipsec_ah : 1, // [23:23]
  451. l3_offset : 7, // [22:16]
  452. ipsec_esp : 1, // [15:15]
  453. stbc : 1, // [14:14]
  454. msdu_length : 14; // [13:0]
  455. uint32_t ip4_protocol_ip6_next_header : 8, // [31:24]
  456. ldpc : 1, // [23:23]
  457. mesh_control_present : 1, // [22:22]
  458. tcp_udp_header_valid : 1, // [21:21]
  459. ip_extn_header_valid : 1, // [20:20]
  460. ip_fixed_header_valid : 1, // [19:19]
  461. toeplitz_hash_sel : 2, // [18:17]
  462. da_is_bcast_mcast : 1, // [16:16]
  463. tcp_only_ack : 1, // [15:15]
  464. ip_frag : 1, // [14:14]
  465. udp_proto : 1, // [13:13]
  466. tcp_proto : 1, // [12:12]
  467. ipv6_proto : 1, // [11:11]
  468. ipv4_proto : 1, // [10:10]
  469. decap_format : 2, // [9:8]
  470. msdu_number : 8; // [7:0]
  471. uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
  472. uint32_t flow_id_toeplitz : 32; // [31:0]
  473. uint32_t mimo_ss_bitmap : 8, // [31:24]
  474. reception_type : 3, // [23:21]
  475. receive_bandwidth : 3, // [20:18]
  476. rate_mcs : 4, // [17:14]
  477. sgi : 2, // [13:12]
  478. pkt_type : 4, // [11:8]
  479. user_rssi : 8; // [7:0]
  480. uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
  481. uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
  482. uint32_t sw_phy_meta_data : 32; // [31:0]
  483. uint32_t vlan_stag_ci : 16, // [31:16]
  484. vlan_ctag_ci : 16; // [15:0]
  485. uint32_t reserved_27a : 32; // [31:0]
  486. uint32_t reserved_28a : 32; // [31:0]
  487. uint32_t reserved_29a : 32; // [31:0]
  488. uint32_t fcs_err : 1, // [31:31]
  489. unencrypted_frame_err : 1, // [30:30]
  490. decrypt_err : 1, // [29:29]
  491. tkip_mic_err : 1, // [28:28]
  492. mpdu_length_err : 1, // [27:27]
  493. buffer_fragment : 1, // [26:26]
  494. directed : 1, // [25:25]
  495. encrypt_required : 1, // [24:24]
  496. rx_in_tx_decrypt_byp : 1, // [23:23]
  497. reserved_30b : 1, // [22:22]
  498. da_idx_invalid : 1, // [21:21]
  499. sa_idx_invalid : 1, // [20:20]
  500. ip_chksum_fail : 1, // [19:19]
  501. tcp_udp_chksum_fail : 1, // [18:18]
  502. msdu_length_err : 1, // [17:17]
  503. overflow_err : 1, // [16:16]
  504. cce_match : 1, // [15:15]
  505. order : 1, // [14:14]
  506. fragment_flag : 1, // [13:13]
  507. a_msdu_error : 1, // [12:12]
  508. eosp : 1, // [11:11]
  509. more_data : 1, // [10:10]
  510. ctrl_type : 1, // [9:9]
  511. mgmt_type : 1, // [8:8]
  512. null_data : 1, // [7:7]
  513. non_qos : 1, // [6:6]
  514. power_mgmt : 1, // [5:5]
  515. ast_index_timeout : 1, // [4:4]
  516. ast_index_not_found : 1, // [3:3]
  517. mcast_bcast : 1, // [2:2]
  518. reserved_30a : 1, // [1:1]
  519. first_mpdu : 1; // [0:0]
  520. uint32_t msdu_done : 1, // [31:31]
  521. reserved_31b : 17, // [30:14]
  522. rx_bitmap_not_updated : 1, // [13:13]
  523. decrypt_status_code : 3, // [12:10]
  524. reserved_31a : 10; // [9:0]
  525. };
  526. struct rx_mpdu_start_compact_qca5332 {
  527. struct rxpt_classify_info rxpt_classify_info_details;
  528. uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
  529. uint32_t reserved_2a : 6, // [31:26]
  530. first_delim_err : 1, // [25:25]
  531. pre_delim_err_warning : 1, // [24:24]
  532. receive_queue_number : 16, // [23:8]
  533. rx_reo_queue_desc_addr_39_32 : 8; // [7:0]
  534. uint32_t pn_31_0 : 32; // [31:0]
  535. uint32_t pn_63_32 : 32; // [31:0]
  536. uint32_t pn_95_64 : 32; // [31:0]
  537. uint32_t pn_127_96 : 32; // [31:0]
  538. uint32_t reserved_7a : 13, // [31:19]
  539. tid : 4, // [18:15]
  540. bssid_number : 4, // [14:11]
  541. bssid_hit : 1, // [10:10]
  542. mesh_sta : 2, // [9:8]
  543. wep_key_width_for_variable_key : 2, // [7:6]
  544. encrypt_type : 4, // [5:2]
  545. all_frames_shall_be_encrypted : 1, // [1:1]
  546. epd_en : 1; // [0:0]
  547. uint32_t peer_meta_data : 32; // [31:0]
  548. uint32_t phy_ppdu_id : 16, // [31:16]
  549. reserved_9a : 1, // [15:15]
  550. ranging : 1, // [14:14]
  551. ast_based_lookup_valid : 1, // [13:13]
  552. protocol_version_err : 1, // [12:12]
  553. phy_err_during_mpdu_header : 1, // [11:11]
  554. phy_err : 1, // [10:10]
  555. ndp_frame : 1, // [9:9]
  556. sw_frame_group_id : 7, // [8:2]
  557. rxpcu_mpdu_filter_in_category : 2; // [1:0]
  558. uint32_t sw_peer_id : 16, // [31:16]
  559. ast_index : 16; // [15:0]
  560. uint32_t mpdu_sequence_number : 12, // [31:20]
  561. mpdu_retry : 1, // [19:19]
  562. encrypted : 1, // [18:18]
  563. to_ds : 1, // [17:17]
  564. fr_ds : 1, // [16:16]
  565. reserved_11a : 1, // [15:15]
  566. more_fragment_flag : 1, // [14:14]
  567. mpdu_fragment_number : 4, // [13:10]
  568. frame_encryption_info_valid : 1, // [9:9]
  569. mpdu_ht_control_valid : 1, // [8:8]
  570. mpdu_qos_control_valid : 1, // [7:7]
  571. mpdu_sequence_control_valid : 1, // [6:6]
  572. mac_addr_ad4_valid : 1, // [5:5]
  573. mac_addr_ad3_valid : 1, // [4:4]
  574. mac_addr_ad2_valid : 1, // [3:3]
  575. mac_addr_ad1_valid : 1, // [2:2]
  576. mpdu_duration_valid : 1, // [1:1]
  577. mpdu_frame_control_valid : 1; // [0:0]
  578. uint32_t reserved_12 : 1, // [31:31]
  579. raw_mpdu : 1, // [30:30]
  580. bar_frame : 1, // [29:29]
  581. ampdu_flag : 1, // [28:28]
  582. pre_delim_count : 12, // [27:16]
  583. strip_vlan_s_tag_decap : 1, // [15:15]
  584. strip_vlan_c_tag_decap : 1, // [14:14]
  585. rx_insert_vlan_s_tag_padding : 1, // [13:13]
  586. rx_insert_vlan_c_tag_padding : 1, // [12:12]
  587. decap_type : 2, // [11:10]
  588. decrypt_needed : 1, // [9:9]
  589. new_peer_entry : 1, // [8:8]
  590. key_id_octet : 8; // [7:0]
  591. uint32_t reserved_13 : 1, // [31:31]
  592. amsdu_present : 1, // [30:30]
  593. directed : 1, // [29:29]
  594. encrypt_required : 1, // [28:28]
  595. u_apsd_trigger : 1, // [27:27]
  596. order : 1, // [26:26]
  597. fragment_flag : 1, // [25:25]
  598. eosp : 1, // [24:24]
  599. more_data : 1, // [23:23]
  600. ctrl_type : 1, // [22:22]
  601. mgmt_type : 1, // [21:21]
  602. null_data : 1, // [20:20]
  603. non_qos : 1, // [19:19]
  604. power_mgmt : 1, // [18:18]
  605. ast_index_timeout : 1, // [17:17]
  606. ast_index_not_found : 1, // [16:16]
  607. mcast_bcast : 1, // [15:15]
  608. first_mpdu : 1, // [14:14]
  609. mpdu_length : 14; // [13:0]
  610. uint32_t mpdu_duration_field : 16, // [31:16]
  611. mpdu_frame_control_field : 16; // [15:0]
  612. uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
  613. uint32_t mac_addr_ad2_15_0 : 16, // [31:16]
  614. mac_addr_ad1_47_32 : 16; // [15:0]
  615. uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
  616. uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
  617. uint32_t mpdu_sequence_control_field : 16, // [31:16]
  618. mac_addr_ad3_47_32 : 16; // [15:0]
  619. uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
  620. uint32_t mpdu_qos_control_field : 16, // [31:16]
  621. mac_addr_ad4_47_32 : 16; // [15:0]
  622. uint32_t mpdu_ht_control_field : 32; // [31:0]
  623. uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31]
  624. reserved_23a : 1, // [30:30]
  625. src_info : 12, // [29:18]
  626. priority_valid : 1, // [17:17]
  627. service_code : 9, // [16:8]
  628. vdev_id : 8; // [7:0]
  629. uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
  630. uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16]
  631. multi_link_addr_ad1_47_32 : 16; // [15:0]
  632. uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
  633. uint32_t reserved_27a : 32; // [31:0]
  634. uint32_t reserved_28a : 32; // [31:0]
  635. uint32_t reserved_29a : 32; // [31:0]
  636. };
  637. #endif /* BIG_ENDIAN_HOST */
  638. /* TLV struct for word based Tlv */
  639. typedef struct rx_mpdu_start_compact_qca5332 hal_rx_mpdu_start_t;
  640. typedef struct rx_msdu_end_compact_qca5332 hal_rx_msdu_end_t;
  641. #endif /* CONFIG_WORD_BASED_TLV */
  642. #include "hal_5332_rx.h"
  643. #include "hal_5332_tx.h"
  644. #include "hal_be_rx_tlv.h"
  645. #include <hal_be_generic_api.h>
  646. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  647. #define HAL_PPE_VP_ENTRIES_MAX 32
  648. /**
  649. * hal_get_link_desc_size_5332(): API to get the link desc size
  650. *
  651. * Return: uint32_t
  652. */
  653. static uint32_t hal_get_link_desc_size_5332(void)
  654. {
  655. return LINK_DESC_SIZE;
  656. }
  657. /**
  658. * hal_rx_get_tlv_5332(): API to get the tlv
  659. *
  660. * @rx_tlv: TLV data extracted from the rx packet
  661. * Return: uint8_t
  662. */
  663. static uint8_t hal_rx_get_tlv_5332(void *rx_tlv)
  664. {
  665. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
  666. }
  667. /**
  668. * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM
  669. * msdu continuation bit is set
  670. *
  671. *@wbm_desc: wbm release ring descriptor
  672. *
  673. * Return: true if msdu continuation bit is set.
  674. */
  675. uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc)
  676. {
  677. uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
  678. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
  679. return (comp_desc &
  680. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
  681. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
  682. }
  683. /**
  684. * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info
  685. *
  686. * Return: uint32_t
  687. */
  688. static inline
  689. void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr,
  690. void *ppdu_info_hdl)
  691. {
  692. uint32_t tlv_tag, tlv_len;
  693. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  694. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  695. void *other_tlv_hdr = NULL;
  696. void *other_tlv = NULL;
  697. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  698. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  699. temp_len = 0;
  700. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  701. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  702. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  703. temp_len += other_tlv_len;
  704. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  705. switch (other_tlv_tag) {
  706. default:
  707. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  708. "%s unhandled TLV type: %d, TLV len:%d",
  709. __func__, other_tlv_tag, other_tlv_len);
  710. break;
  711. }
  712. }
  713. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  714. static inline
  715. void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  716. {
  717. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  718. ppdu_info->cfr_info.bb_captured_channel =
  719. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
  720. ppdu_info->cfr_info.bb_captured_timeout =
  721. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
  722. ppdu_info->cfr_info.bb_captured_reason =
  723. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
  724. }
  725. static inline
  726. void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  727. {
  728. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  729. ppdu_info->cfr_info.rx_location_info_valid =
  730. HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  731. RX_LOCATION_INFO_VALID);
  732. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  733. HAL_RX_GET(rx_tlv,
  734. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  735. RTT_CHE_BUFFER_POINTER_LOW32);
  736. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  737. HAL_RX_GET(rx_tlv,
  738. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  739. RTT_CHE_BUFFER_POINTER_HIGH8);
  740. ppdu_info->cfr_info.chan_capture_status =
  741. HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
  742. ppdu_info->cfr_info.rx_start_ts =
  743. HAL_RX_GET(rx_tlv,
  744. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  745. RX_START_TS);
  746. ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
  747. HAL_RX_GET(rx_tlv,
  748. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  749. RTT_CFO_MEASUREMENT);
  750. ppdu_info->cfr_info.agc_gain_info0 =
  751. HAL_RX_GET(rx_tlv,
  752. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  753. GAIN_CHAIN0);
  754. ppdu_info->cfr_info.agc_gain_info0 |=
  755. (((uint32_t)HAL_RX_GET(rx_tlv,
  756. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  757. GAIN_CHAIN1)) << 16);
  758. ppdu_info->cfr_info.agc_gain_info1 =
  759. HAL_RX_GET(rx_tlv,
  760. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  761. GAIN_CHAIN2);
  762. ppdu_info->cfr_info.agc_gain_info1 |=
  763. (((uint32_t)HAL_RX_GET(rx_tlv,
  764. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  765. GAIN_CHAIN3)) << 16);
  766. ppdu_info->cfr_info.agc_gain_info2 = 0;
  767. ppdu_info->cfr_info.agc_gain_info3 = 0;
  768. }
  769. #endif
  770. /**
  771. * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured
  772. * human readable format.
  773. * @mpdu_start: pointer the rx_attention TLV in pkt.
  774. * @dbg_level: log level.
  775. *
  776. * Return: void
  777. */
  778. static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
  779. uint8_t dbg_level)
  780. {
  781. #ifdef CONFIG_WORD_BASED_TLV
  782. struct rx_mpdu_start_compact_qca5332 *mpdu_info =
  783. (struct rx_mpdu_start_compact_qca5332 *)mpdustart;
  784. #else
  785. struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
  786. struct rx_mpdu_info *mpdu_info =
  787. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  788. #endif
  789. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  790. "rx_mpdu_start tlv (1/5) - "
  791. "rx_reo_queue_desc_addr_31_0 :%x"
  792. "rx_reo_queue_desc_addr_39_32 :%x"
  793. "receive_queue_number:%x "
  794. "pre_delim_err_warning:%x "
  795. "first_delim_err:%x "
  796. "reserved_2a:%x "
  797. "pn_31_0:%x "
  798. "pn_63_32:%x "
  799. "pn_95_64:%x "
  800. "pn_127_96:%x "
  801. "epd_en:%x "
  802. "all_frames_shall_be_encrypted :%x"
  803. "encrypt_type:%x "
  804. "wep_key_width_for_variable_key :%x"
  805. "mesh_sta:%x "
  806. "bssid_hit:%x "
  807. "bssid_number:%x "
  808. "tid:%x "
  809. "reserved_7a:%x ",
  810. mpdu_info->rx_reo_queue_desc_addr_31_0,
  811. mpdu_info->rx_reo_queue_desc_addr_39_32,
  812. mpdu_info->receive_queue_number,
  813. mpdu_info->pre_delim_err_warning,
  814. mpdu_info->first_delim_err,
  815. mpdu_info->reserved_2a,
  816. mpdu_info->pn_31_0,
  817. mpdu_info->pn_63_32,
  818. mpdu_info->pn_95_64,
  819. mpdu_info->pn_127_96,
  820. mpdu_info->epd_en,
  821. mpdu_info->all_frames_shall_be_encrypted,
  822. mpdu_info->encrypt_type,
  823. mpdu_info->wep_key_width_for_variable_key,
  824. mpdu_info->mesh_sta,
  825. mpdu_info->bssid_hit,
  826. mpdu_info->bssid_number,
  827. mpdu_info->tid,
  828. mpdu_info->reserved_7a);
  829. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  830. "rx_mpdu_start tlv (2/5) - "
  831. "ast_index:%x "
  832. "sw_peer_id:%x "
  833. "mpdu_frame_control_valid:%x "
  834. "mpdu_duration_valid:%x "
  835. "mac_addr_ad1_valid:%x "
  836. "mac_addr_ad2_valid:%x "
  837. "mac_addr_ad3_valid:%x "
  838. "mac_addr_ad4_valid:%x "
  839. "mpdu_sequence_control_valid :%x"
  840. "mpdu_qos_control_valid:%x "
  841. "mpdu_ht_control_valid:%x "
  842. "frame_encryption_info_valid :%x",
  843. mpdu_info->ast_index,
  844. mpdu_info->sw_peer_id,
  845. mpdu_info->mpdu_frame_control_valid,
  846. mpdu_info->mpdu_duration_valid,
  847. mpdu_info->mac_addr_ad1_valid,
  848. mpdu_info->mac_addr_ad2_valid,
  849. mpdu_info->mac_addr_ad3_valid,
  850. mpdu_info->mac_addr_ad4_valid,
  851. mpdu_info->mpdu_sequence_control_valid,
  852. mpdu_info->mpdu_qos_control_valid,
  853. mpdu_info->mpdu_ht_control_valid,
  854. mpdu_info->frame_encryption_info_valid);
  855. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  856. "rx_mpdu_start tlv (3/5) - "
  857. "mpdu_fragment_number:%x "
  858. "more_fragment_flag:%x "
  859. "reserved_11a:%x "
  860. "fr_ds:%x "
  861. "to_ds:%x "
  862. "encrypted:%x "
  863. "mpdu_retry:%x "
  864. "mpdu_sequence_number:%x ",
  865. mpdu_info->mpdu_fragment_number,
  866. mpdu_info->more_fragment_flag,
  867. mpdu_info->reserved_11a,
  868. mpdu_info->fr_ds,
  869. mpdu_info->to_ds,
  870. mpdu_info->encrypted,
  871. mpdu_info->mpdu_retry,
  872. mpdu_info->mpdu_sequence_number);
  873. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  874. "rx_mpdu_start tlv (4/5) - "
  875. "mpdu_frame_control_field:%x "
  876. "mpdu_duration_field:%x ",
  877. mpdu_info->mpdu_frame_control_field,
  878. mpdu_info->mpdu_duration_field);
  879. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  880. "rx_mpdu_start tlv (5/5) - "
  881. "mac_addr_ad1_31_0:%x "
  882. "mac_addr_ad1_47_32:%x "
  883. "mac_addr_ad2_15_0:%x "
  884. "mac_addr_ad2_47_16:%x "
  885. "mac_addr_ad3_31_0:%x "
  886. "mac_addr_ad3_47_32:%x "
  887. "mpdu_sequence_control_field :%x"
  888. "mac_addr_ad4_31_0:%x "
  889. "mac_addr_ad4_47_32:%x "
  890. "mpdu_qos_control_field:%x ",
  891. mpdu_info->mac_addr_ad1_31_0,
  892. mpdu_info->mac_addr_ad1_47_32,
  893. mpdu_info->mac_addr_ad2_15_0,
  894. mpdu_info->mac_addr_ad2_47_16,
  895. mpdu_info->mac_addr_ad3_31_0,
  896. mpdu_info->mac_addr_ad3_47_32,
  897. mpdu_info->mpdu_sequence_control_field,
  898. mpdu_info->mac_addr_ad4_31_0,
  899. mpdu_info->mac_addr_ad4_47_32,
  900. mpdu_info->mpdu_qos_control_field);
  901. }
  902. /**
  903. * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured
  904. * human readable format.
  905. * @ msdu_end: pointer the msdu_end TLV in pkt.
  906. * @ dbg_level: log level.
  907. *
  908. * Return: void
  909. */
  910. static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
  911. uint8_t dbg_level)
  912. {
  913. #ifdef CONFIG_WORD_BASED_TLV
  914. struct rx_msdu_end_compact_qca5332 *msdu_end =
  915. (struct rx_msdu_end_compact_qca5332 *)msduend;
  916. #else
  917. struct rx_msdu_end *msdu_end =
  918. (struct rx_msdu_end *)msduend;
  919. #endif
  920. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  921. "rx_msdu_end tlv - "
  922. "key_id_octet: %d "
  923. "cce_super_rule: %d "
  924. "cce_classify_not_done_truncat: %d "
  925. "cce_classify_not_done_cce_dis: %d "
  926. "rule_indication_31_0: %d "
  927. "tcp_udp_chksum: %d "
  928. "sa_idx_timeout: %d "
  929. "da_idx_timeout: %d "
  930. "msdu_limit_error: %d "
  931. "flow_idx_timeout: %d "
  932. "flow_idx_invalid: %d "
  933. "wifi_parser_error: %d "
  934. "sa_is_valid: %d "
  935. "da_is_valid: %d "
  936. "da_is_mcbc: %d "
  937. "tkip_mic_err: %d "
  938. "l3_header_padding: %d "
  939. "first_msdu: %d "
  940. "last_msdu: %d "
  941. "sa_idx: %d "
  942. "msdu_drop: %d "
  943. "reo_destination_indication: %d "
  944. "flow_idx: %d "
  945. "fse_metadata: %d "
  946. "cce_metadata: %d "
  947. "sa_sw_peer_id: %d ",
  948. msdu_end->key_id_octet,
  949. msdu_end->cce_super_rule,
  950. msdu_end->cce_classify_not_done_truncate,
  951. msdu_end->cce_classify_not_done_cce_dis,
  952. msdu_end->rule_indication_31_0,
  953. msdu_end->tcp_udp_chksum,
  954. msdu_end->sa_idx_timeout,
  955. msdu_end->da_idx_timeout,
  956. msdu_end->msdu_limit_error,
  957. msdu_end->flow_idx_timeout,
  958. msdu_end->flow_idx_invalid,
  959. msdu_end->wifi_parser_error,
  960. msdu_end->sa_is_valid,
  961. msdu_end->da_is_valid,
  962. msdu_end->da_is_mcbc,
  963. msdu_end->tkip_mic_err,
  964. msdu_end->l3_header_padding,
  965. msdu_end->first_msdu,
  966. msdu_end->last_msdu,
  967. msdu_end->sa_idx,
  968. msdu_end->msdu_drop,
  969. msdu_end->reo_destination_indication,
  970. msdu_end->flow_idx,
  971. msdu_end->fse_metadata,
  972. msdu_end->cce_metadata,
  973. msdu_end->sa_sw_peer_id);
  974. }
  975. /**
  976. * hal_reo_status_get_header_5332 - Process reo desc info
  977. * @d - Pointer to reo descriptior
  978. * @b - tlv type info
  979. * @h1 - Pointer to hal_reo_status_header where info to be stored
  980. *
  981. * Return - none.
  982. *
  983. */
  984. static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,
  985. int b, void *h1)
  986. {
  987. uint64_t *d = (uint64_t *)ring_desc;
  988. uint64_t val1 = 0;
  989. struct hal_reo_status_header *h =
  990. (struct hal_reo_status_header *)h1;
  991. /* Offsets of descriptor fields defined in HW headers start
  992. * from the field after TLV header
  993. */
  994. d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  995. switch (b) {
  996. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  997. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  998. STATUS_HEADER_REO_STATUS_NUMBER)];
  999. break;
  1000. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1001. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  1002. STATUS_HEADER_REO_STATUS_NUMBER)];
  1003. break;
  1004. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1005. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  1006. STATUS_HEADER_REO_STATUS_NUMBER)];
  1007. break;
  1008. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1009. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  1010. STATUS_HEADER_REO_STATUS_NUMBER)];
  1011. break;
  1012. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1013. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1014. STATUS_HEADER_REO_STATUS_NUMBER)];
  1015. break;
  1016. case HAL_REO_DESC_THRES_STATUS_TLV:
  1017. val1 =
  1018. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1019. STATUS_HEADER_REO_STATUS_NUMBER)];
  1020. break;
  1021. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1022. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  1023. STATUS_HEADER_REO_STATUS_NUMBER)];
  1024. break;
  1025. default:
  1026. qdf_nofl_err("ERROR: Unknown tlv\n");
  1027. break;
  1028. }
  1029. h->cmd_num =
  1030. HAL_GET_FIELD(
  1031. UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
  1032. val1);
  1033. h->exec_time =
  1034. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  1035. CMD_EXECUTION_TIME, val1);
  1036. h->status =
  1037. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  1038. REO_CMD_EXECUTION_STATUS, val1);
  1039. switch (b) {
  1040. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1041. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  1042. STATUS_HEADER_TIMESTAMP)];
  1043. break;
  1044. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1045. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  1046. STATUS_HEADER_TIMESTAMP)];
  1047. break;
  1048. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1049. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  1050. STATUS_HEADER_TIMESTAMP)];
  1051. break;
  1052. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1053. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  1054. STATUS_HEADER_TIMESTAMP)];
  1055. break;
  1056. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1057. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1058. STATUS_HEADER_TIMESTAMP)];
  1059. break;
  1060. case HAL_REO_DESC_THRES_STATUS_TLV:
  1061. val1 =
  1062. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1063. STATUS_HEADER_TIMESTAMP)];
  1064. break;
  1065. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1066. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  1067. STATUS_HEADER_TIMESTAMP)];
  1068. break;
  1069. default:
  1070. qdf_nofl_err("ERROR: Unknown tlv\n");
  1071. break;
  1072. }
  1073. h->tstamp =
  1074. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
  1075. }
  1076. static
  1077. void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va)
  1078. {
  1079. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  1080. }
  1081. static
  1082. void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0)
  1083. {
  1084. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  1085. }
  1086. static
  1087. void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc)
  1088. {
  1089. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  1090. }
  1091. static
  1092. void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc)
  1093. {
  1094. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  1095. }
  1096. /**
  1097. * hal_reo_config_5332(): Set reo config parameters
  1098. * @soc: hal soc handle
  1099. * @reg_val: value to be set
  1100. * @reo_params: reo parameters
  1101. *
  1102. * Return: void
  1103. */
  1104. static void
  1105. hal_reo_config_5332(struct hal_soc *soc,
  1106. uint32_t reg_val,
  1107. struct hal_reo_params *reo_params)
  1108. {
  1109. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  1110. }
  1111. /**
  1112. * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr
  1113. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1114. *
  1115. * Return - Pointer to rx_msdu_desc_info structure.
  1116. *
  1117. */
  1118. static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr)
  1119. {
  1120. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  1121. }
  1122. /**
  1123. * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details
  1124. * @link_desc - Pointer to link desc
  1125. *
  1126. * Return - Pointer to rx_msdu_details structure
  1127. *
  1128. */
  1129. static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc)
  1130. {
  1131. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  1132. }
  1133. /**
  1134. * hal_get_window_address_5332(): Function to get hp/tp address
  1135. * @hal_soc: Pointer to hal_soc
  1136. * @addr: address offset of register
  1137. *
  1138. * Return: modified address offset of register
  1139. */
  1140. static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc,
  1141. qdf_iomem_t addr)
  1142. {
  1143. uint32_t offset = addr - hal_soc->dev_base_addr;
  1144. qdf_iomem_t new_offset;
  1145. /*
  1146. * If offset lies within DP register range, use 3rd window to write
  1147. * into DP region.
  1148. */
  1149. if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) {
  1150. new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
  1151. (offset & WINDOW_RANGE_MASK));
  1152. /*
  1153. * If offset lies within CE register range, use 2nd window to write
  1154. * into CE region.
  1155. */
  1156. } else if ((offset ^ CE_CFG_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
  1157. new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
  1158. (offset & WINDOW_RANGE_MASK));
  1159. } else {
  1160. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1161. "%s: ERROR: Accessing Wrong register\n", __func__);
  1162. qdf_assert_always(0);
  1163. return 0;
  1164. }
  1165. return new_offset;
  1166. }
  1167. static inline void hal_write_window_register(struct hal_soc *hal_soc)
  1168. {
  1169. /* Write value into window configuration register */
  1170. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  1171. WINDOW_CONFIGURATION_VALUE_5332);
  1172. }
  1173. static
  1174. void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings,
  1175. uint32_t *remap1, uint32_t *remap2)
  1176. {
  1177. switch (num_rings) {
  1178. case 1:
  1179. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1180. HAL_REO_REMAP_IX2(ring[0], 17) |
  1181. HAL_REO_REMAP_IX2(ring[0], 18) |
  1182. HAL_REO_REMAP_IX2(ring[0], 19) |
  1183. HAL_REO_REMAP_IX2(ring[0], 20) |
  1184. HAL_REO_REMAP_IX2(ring[0], 21) |
  1185. HAL_REO_REMAP_IX2(ring[0], 22) |
  1186. HAL_REO_REMAP_IX2(ring[0], 23);
  1187. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1188. HAL_REO_REMAP_IX3(ring[0], 25) |
  1189. HAL_REO_REMAP_IX3(ring[0], 26) |
  1190. HAL_REO_REMAP_IX3(ring[0], 27) |
  1191. HAL_REO_REMAP_IX3(ring[0], 28) |
  1192. HAL_REO_REMAP_IX3(ring[0], 29) |
  1193. HAL_REO_REMAP_IX3(ring[0], 30) |
  1194. HAL_REO_REMAP_IX3(ring[0], 31);
  1195. break;
  1196. case 2:
  1197. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1198. HAL_REO_REMAP_IX2(ring[0], 17) |
  1199. HAL_REO_REMAP_IX2(ring[1], 18) |
  1200. HAL_REO_REMAP_IX2(ring[1], 19) |
  1201. HAL_REO_REMAP_IX2(ring[0], 20) |
  1202. HAL_REO_REMAP_IX2(ring[0], 21) |
  1203. HAL_REO_REMAP_IX2(ring[1], 22) |
  1204. HAL_REO_REMAP_IX2(ring[1], 23);
  1205. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1206. HAL_REO_REMAP_IX3(ring[0], 25) |
  1207. HAL_REO_REMAP_IX3(ring[1], 26) |
  1208. HAL_REO_REMAP_IX3(ring[1], 27) |
  1209. HAL_REO_REMAP_IX3(ring[0], 28) |
  1210. HAL_REO_REMAP_IX3(ring[0], 29) |
  1211. HAL_REO_REMAP_IX3(ring[1], 30) |
  1212. HAL_REO_REMAP_IX3(ring[1], 31);
  1213. break;
  1214. case 3:
  1215. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1216. HAL_REO_REMAP_IX2(ring[1], 17) |
  1217. HAL_REO_REMAP_IX2(ring[2], 18) |
  1218. HAL_REO_REMAP_IX2(ring[0], 19) |
  1219. HAL_REO_REMAP_IX2(ring[1], 20) |
  1220. HAL_REO_REMAP_IX2(ring[2], 21) |
  1221. HAL_REO_REMAP_IX2(ring[0], 22) |
  1222. HAL_REO_REMAP_IX2(ring[1], 23);
  1223. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  1224. HAL_REO_REMAP_IX3(ring[0], 25) |
  1225. HAL_REO_REMAP_IX3(ring[1], 26) |
  1226. HAL_REO_REMAP_IX3(ring[2], 27) |
  1227. HAL_REO_REMAP_IX3(ring[0], 28) |
  1228. HAL_REO_REMAP_IX3(ring[1], 29) |
  1229. HAL_REO_REMAP_IX3(ring[2], 30) |
  1230. HAL_REO_REMAP_IX3(ring[0], 31);
  1231. break;
  1232. case 4:
  1233. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1234. HAL_REO_REMAP_IX2(ring[1], 17) |
  1235. HAL_REO_REMAP_IX2(ring[2], 18) |
  1236. HAL_REO_REMAP_IX2(ring[3], 19) |
  1237. HAL_REO_REMAP_IX2(ring[0], 20) |
  1238. HAL_REO_REMAP_IX2(ring[1], 21) |
  1239. HAL_REO_REMAP_IX2(ring[2], 22) |
  1240. HAL_REO_REMAP_IX2(ring[3], 23);
  1241. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1242. HAL_REO_REMAP_IX3(ring[1], 25) |
  1243. HAL_REO_REMAP_IX3(ring[2], 26) |
  1244. HAL_REO_REMAP_IX3(ring[3], 27) |
  1245. HAL_REO_REMAP_IX3(ring[0], 28) |
  1246. HAL_REO_REMAP_IX3(ring[1], 29) |
  1247. HAL_REO_REMAP_IX3(ring[2], 30) |
  1248. HAL_REO_REMAP_IX3(ring[3], 31);
  1249. break;
  1250. }
  1251. }
  1252. /**
  1253. * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST
  1254. * @fst: Pointer to the Rx Flow Search Table
  1255. * @table_offset: offset into the table where the flow is to be setup
  1256. * @flow: Flow Parameters
  1257. *
  1258. * Return: Success/Failure
  1259. */
  1260. static void *
  1261. hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset,
  1262. uint8_t *rx_flow)
  1263. {
  1264. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1265. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  1266. uint8_t *fse;
  1267. bool fse_valid;
  1268. if (table_offset >= fst->max_entries) {
  1269. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1270. "HAL FSE table offset %u exceeds max entries %u",
  1271. table_offset, fst->max_entries);
  1272. return NULL;
  1273. }
  1274. fse = (uint8_t *)fst->base_vaddr +
  1275. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  1276. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1277. if (fse_valid) {
  1278. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1279. "HAL FSE %pK already valid", fse);
  1280. return NULL;
  1281. }
  1282. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
  1283. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
  1284. qdf_htonl(flow->tuple_info.src_ip_127_96));
  1285. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
  1286. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
  1287. qdf_htonl(flow->tuple_info.src_ip_95_64));
  1288. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
  1289. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
  1290. qdf_htonl(flow->tuple_info.src_ip_63_32));
  1291. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
  1292. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
  1293. qdf_htonl(flow->tuple_info.src_ip_31_0));
  1294. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
  1295. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
  1296. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  1297. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
  1298. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
  1299. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  1300. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
  1301. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
  1302. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  1303. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
  1304. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
  1305. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  1306. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
  1307. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
  1308. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
  1309. (flow->tuple_info.dest_port));
  1310. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
  1311. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
  1312. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
  1313. (flow->tuple_info.src_port));
  1314. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
  1315. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
  1316. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
  1317. flow->tuple_info.l4_protocol);
  1318. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
  1319. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
  1320. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
  1321. flow->reo_destination_handler);
  1322. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1323. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
  1324. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
  1325. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
  1326. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
  1327. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
  1328. flow->fse_metadata);
  1329. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
  1330. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
  1331. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
  1332. REO_DESTINATION_INDICATION,
  1333. flow->reo_destination_indication);
  1334. /* Reset all the other fields in FSE */
  1335. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
  1336. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
  1337. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
  1338. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
  1339. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
  1340. return fse;
  1341. }
  1342. #ifndef NO_RX_PKT_HDR_TLV
  1343. /**
  1344. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  1345. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  1346. * @ dbg_level: log level.
  1347. *
  1348. * Return: void
  1349. */
  1350. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  1351. uint8_t dbg_level)
  1352. {
  1353. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  1354. hal_verbose_debug("\n---------------\n"
  1355. "rx_pkt_hdr_tlv\n"
  1356. "---------------\n"
  1357. "phy_ppdu_id %llu ",
  1358. pkt_hdr_tlv->phy_ppdu_id);
  1359. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
  1360. sizeof(pkt_hdr_tlv->rx_pkt_hdr));
  1361. }
  1362. #else
  1363. /**
  1364. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  1365. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  1366. * @ dbg_level: log level.
  1367. *
  1368. * Return: void
  1369. */
  1370. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  1371. uint8_t dbg_level)
  1372. {
  1373. }
  1374. #endif
  1375. /**
  1376. * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332
  1377. * @hal_soc_hdl: hal_soc handle
  1378. * @buf: pointer the pkt buffer
  1379. * @dbg_level: log level
  1380. *
  1381. * Return: void
  1382. */
  1383. #ifdef CONFIG_WORD_BASED_TLV
  1384. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1385. uint8_t *buf, uint8_t dbg_level)
  1386. {
  1387. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1388. struct rx_msdu_end_compact_qca5332 *msdu_end =
  1389. &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1390. struct rx_mpdu_start_compact_qca5332 *mpdu_start =
  1391. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1392. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1393. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1394. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1395. }
  1396. #else
  1397. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1398. uint8_t *buf, uint8_t dbg_level)
  1399. {
  1400. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1401. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1402. struct rx_mpdu_start *mpdu_start =
  1403. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1404. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1405. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1406. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1407. }
  1408. #endif
  1409. #define HAL_NUM_TCL_BANKS_5332 48
  1410. /**
  1411. * hal_cmem_write_5332() - function for CMEM buffer writing
  1412. * @hal_soc_hdl: HAL SOC handle
  1413. * @offset: CMEM address
  1414. * @value: value to write
  1415. *
  1416. * Return: None.
  1417. */
  1418. static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,
  1419. uint32_t offset,
  1420. uint32_t value)
  1421. {
  1422. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1423. pld_reg_write(hal->qdf_dev->dev, offset, value);
  1424. }
  1425. /**
  1426. * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target
  1427. *
  1428. * Returns: number of bank
  1429. */
  1430. static uint8_t hal_tx_get_num_tcl_banks_5332(void)
  1431. {
  1432. return HAL_NUM_TCL_BANKS_5332;
  1433. }
  1434. static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams)
  1435. {
  1436. uint32_t reg_val;
  1437. struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
  1438. reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
  1439. REO_REG_REG_BASE));
  1440. hal_reo_config_5332(soc, reg_val, reo_params);
  1441. /* Other ring enable bits and REO_ENABLE will be set by FW */
  1442. /* TODO: Setup destination ring mapping if enabled */
  1443. /* TODO: Error destination ring setting is left to default.
  1444. * Default setting is to send all errors to release ring.
  1445. */
  1446. /* Set the reo descriptor swap bits in case of BIG endian platform */
  1447. hal_setup_reo_swap(soc);
  1448. HAL_REG_WRITE(soc,
  1449. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
  1450. HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
  1451. HAL_REG_WRITE(soc,
  1452. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
  1453. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1454. HAL_REG_WRITE(soc,
  1455. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
  1456. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1457. HAL_REG_WRITE(soc,
  1458. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
  1459. (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
  1460. /*
  1461. * When hash based routing is enabled, routing of the rx packet
  1462. * is done based on the following value: 1 _ _ _ _ The last 4
  1463. * bits are based on hash[3:0]. This means the possible values
  1464. * are 0x10 to 0x1f. This value is used to look-up the
  1465. * ring ID configured in Destination_Ring_Ctrl_IX_* register.
  1466. * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
  1467. * registers need to be configured to set-up the 16 entries to
  1468. * map the hash values to a ring number. There are 3 bits per
  1469. * hash entry – which are mapped as follows:
  1470. * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
  1471. * 7: NOT_USED.
  1472. */
  1473. if (reo_params->rx_hash_enabled) {
  1474. HAL_REG_WRITE(soc,
  1475. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
  1476. (REO_REG_REG_BASE), reo_params->remap0);
  1477. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1478. HAL_REG_READ(soc,
  1479. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
  1480. REO_REG_REG_BASE)));
  1481. HAL_REG_WRITE(soc,
  1482. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
  1483. (REO_REG_REG_BASE), reo_params->remap1);
  1484. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1485. HAL_REG_READ(soc,
  1486. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
  1487. REO_REG_REG_BASE)));
  1488. HAL_REG_WRITE(soc,
  1489. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
  1490. (REO_REG_REG_BASE), reo_params->remap2);
  1491. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
  1492. HAL_REG_READ(soc,
  1493. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
  1494. REO_REG_REG_BASE)));
  1495. }
  1496. /* TODO: Check if the following registers shoould be setup by host:
  1497. * AGING_CONTROL
  1498. * HIGH_MEMORY_THRESHOLD
  1499. * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
  1500. * GLOBAL_LINK_DESC_COUNT_CTRL
  1501. */
  1502. hal_reo_shared_qaddr_init((hal_soc_handle_t)soc);
  1503. }
  1504. static uint16_t hal_get_rx_max_ba_window_qca5332(int tid)
  1505. {
  1506. return HAL_RX_BA_WINDOW_1024;
  1507. }
  1508. /**
  1509. * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size
  1510. * from the give Block-Ack window size
  1511. * Return: reo queue descriptor size
  1512. */
  1513. static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
  1514. {
  1515. /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
  1516. * NON_QOS_TID until HW issues are resolved.
  1517. */
  1518. if (tid != HAL_NON_QOS_TID)
  1519. ba_window_size = hal_get_rx_max_ba_window_qca5332(tid);
  1520. /* Return descriptor size corresponding to window size of 2 since
  1521. * we set ba_window_size to 2 while setting up REO descriptors as
  1522. * a WAR to get 2k jump exception aggregates are received without
  1523. * a BA session.
  1524. */
  1525. if (ba_window_size <= 1) {
  1526. if (tid != HAL_NON_QOS_TID)
  1527. return sizeof(struct rx_reo_queue) +
  1528. sizeof(struct rx_reo_queue_ext);
  1529. else
  1530. return sizeof(struct rx_reo_queue);
  1531. }
  1532. if (ba_window_size <= 105)
  1533. return sizeof(struct rx_reo_queue) +
  1534. sizeof(struct rx_reo_queue_ext);
  1535. if (ba_window_size <= 210)
  1536. return sizeof(struct rx_reo_queue) +
  1537. (2 * sizeof(struct rx_reo_queue_ext));
  1538. if (ba_window_size <= 256)
  1539. return sizeof(struct rx_reo_queue) +
  1540. (3 * sizeof(struct rx_reo_queue_ext));
  1541. return sizeof(struct rx_reo_queue) +
  1542. (10 * sizeof(struct rx_reo_queue_ext)) +
  1543. sizeof(struct rx_reo_queue_1k);
  1544. }
  1545. /**
  1546. * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv
  1547. *
  1548. * Returns: msdu done copy bit
  1549. */
  1550. static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf)
  1551. {
  1552. return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
  1553. }
  1554. static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
  1555. {
  1556. /* init and setup */
  1557. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1558. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1559. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1560. hal_soc->ops->hal_get_window_address = hal_get_window_address_5332;
  1561. hal_soc->ops->hal_cmem_write = hal_cmem_write_5332;
  1562. /* tx */
  1563. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332;
  1564. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332;
  1565. hal_soc->ops->hal_tx_comp_get_status =
  1566. hal_tx_comp_get_status_generic_be;
  1567. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1568. hal_tx_init_cmd_credit_ring_5332;
  1569. hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL;
  1570. hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL;
  1571. hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL;
  1572. hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL;
  1573. hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL;
  1574. hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL;
  1575. hal_soc->ops->hal_tx_enable_pri2tid_map = NULL;
  1576. hal_soc->ops->hal_tx_config_rbm_mapping_be =
  1577. hal_tx_config_rbm_mapping_be_5332;
  1578. /* rx */
  1579. hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
  1580. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1581. hal_rx_mon_hw_desc_get_mpdu_status_be;
  1582. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332;
  1583. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1584. hal_rx_proc_phyrx_other_receive_info_tlv_5332;
  1585. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332;
  1586. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1587. hal_rx_dump_mpdu_start_tlv_5332;
  1588. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332;
  1589. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332;
  1590. hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
  1591. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1592. hal_rx_tlv_reception_type_get_be;
  1593. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1594. hal_rx_msdu_end_da_idx_get_be;
  1595. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1596. hal_rx_msdu_desc_info_get_ptr_5332;
  1597. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1598. hal_rx_link_desc_msdu0_ptr_5332;
  1599. hal_soc->ops->hal_reo_status_get_header =
  1600. hal_reo_status_get_header_5332;
  1601. hal_soc->ops->hal_rx_status_get_tlv_info =
  1602. hal_rx_status_get_tlv_info_wrapper_be;
  1603. hal_soc->ops->hal_rx_wbm_err_info_get =
  1604. hal_rx_wbm_err_info_get_generic_be;
  1605. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1606. hal_tx_set_pcp_tid_map_generic_be;
  1607. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1608. hal_tx_update_pcp_tid_generic_be;
  1609. hal_soc->ops->hal_tx_set_tidmap_prty =
  1610. hal_tx_update_tidmap_prty_generic_be;
  1611. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1612. hal_rx_get_rx_fragment_number_be,
  1613. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1614. hal_rx_tlv_da_is_mcbc_get_be;
  1615. hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
  1616. hal_rx_tlv_is_tkip_mic_err_get_be;
  1617. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1618. hal_rx_tlv_sa_is_valid_get_be;
  1619. hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
  1620. hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
  1621. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1622. hal_rx_tlv_l3_hdr_padding_get_be;
  1623. hal_soc->ops->hal_rx_encryption_info_valid =
  1624. hal_rx_encryption_info_valid_be;
  1625. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
  1626. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1627. hal_rx_tlv_first_msdu_get_be;
  1628. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1629. hal_rx_tlv_da_is_valid_get_be;
  1630. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1631. hal_rx_tlv_last_msdu_get_be;
  1632. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1633. hal_rx_get_mpdu_mac_ad4_valid_be;
  1634. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1635. hal_rx_mpdu_start_sw_peer_id_get_be;
  1636. hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
  1637. hal_rx_mpdu_peer_meta_data_get_be;
  1638. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
  1639. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
  1640. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1641. hal_rx_get_mpdu_frame_control_valid_be;
  1642. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
  1643. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
  1644. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
  1645. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
  1646. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1647. hal_rx_get_mpdu_sequence_control_valid_be;
  1648. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
  1649. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
  1650. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1651. hal_rx_hw_desc_get_ppduid_get_be;
  1652. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1653. hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
  1654. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1655. hal_rx_msdu_end_sa_sw_peer_id_get_be;
  1656. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1657. hal_rx_msdu0_buffer_addr_lsb_5332;
  1658. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1659. hal_rx_msdu_desc_info_ptr_get_5332;
  1660. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332;
  1661. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332;
  1662. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
  1663. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
  1664. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1665. hal_rx_get_mac_addr2_valid_be;
  1666. hal_soc->ops->hal_rx_get_filter_category =
  1667. hal_rx_get_filter_category_be;
  1668. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
  1669. hal_soc->ops->hal_reo_config = hal_reo_config_5332;
  1670. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
  1671. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1672. hal_rx_msdu_flow_idx_invalid_be;
  1673. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1674. hal_rx_msdu_flow_idx_timeout_be;
  1675. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1676. hal_rx_msdu_fse_metadata_get_be;
  1677. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1678. hal_rx_msdu_cce_match_get_be;
  1679. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1680. hal_rx_msdu_cce_metadata_get_be;
  1681. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1682. hal_rx_msdu_get_flow_params_be;
  1683. hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
  1684. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
  1685. #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \
  1686. defined(WLAN_ENH_CFR_ENABLE)
  1687. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332;
  1688. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332;
  1689. #else
  1690. hal_soc->ops->hal_rx_get_bb_info = NULL;
  1691. hal_soc->ops->hal_rx_get_rtt_info = NULL;
  1692. #endif
  1693. /* rx - msdu fast path info fields */
  1694. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1695. hal_rx_msdu_packet_metadata_get_generic_be;
  1696. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1697. hal_rx_mpdu_start_tlv_tag_valid_be;
  1698. hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
  1699. hal_rx_wbm_err_msdu_continuation_get_5332;
  1700. /* rx - TLV struct offsets */
  1701. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1702. hal_rx_msdu_end_offset_get_generic;
  1703. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1704. hal_rx_mpdu_start_offset_get_generic;
  1705. #ifndef NO_RX_PKT_HDR_TLV
  1706. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1707. hal_rx_pkt_tlv_offset_get_generic;
  1708. #endif
  1709. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332;
  1710. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1711. hal_rx_flow_get_tuple_info_be;
  1712. hal_soc->ops->hal_rx_flow_delete_entry =
  1713. hal_rx_flow_delete_entry_be;
  1714. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
  1715. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1716. hal_compute_reo_remap_ix2_ix3_5332;
  1717. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
  1718. hal_rx_msdu_get_reo_destination_indication_be;
  1719. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
  1720. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1721. hal_rx_msdu_is_wlan_mcast_generic_be;
  1722. hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332;
  1723. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1724. hal_rx_tlv_decap_format_get_be;
  1725. #ifdef RECEIVE_OFFLOAD
  1726. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1727. hal_rx_tlv_get_offload_info_be;
  1728. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
  1729. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
  1730. #endif
  1731. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1732. hal_rx_attn_phy_ppdu_id_get_be;
  1733. hal_soc->ops->hal_rx_tlv_msdu_done_get =
  1734. hal_rx_tlv_msdu_done_copy_get_5332;
  1735. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1736. hal_rx_msdu_start_msdu_len_get_be;
  1737. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1738. hal_rx_get_frame_ctrl_field_be;
  1739. hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
  1740. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1741. hal_rx_mpdu_info_ampdu_flag_get_be;
  1742. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1743. hal_rx_msdu_start_msdu_len_set_be;
  1744. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
  1745. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
  1746. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
  1747. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
  1748. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
  1749. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1750. hal_rx_tlv_decrypt_err_get_be;
  1751. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
  1752. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1753. hal_rx_tlv_get_is_decrypted_be;
  1754. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
  1755. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
  1756. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1757. hal_rx_priv_info_set_in_tlv_be;
  1758. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1759. hal_rx_priv_info_get_from_tlv_be;
  1760. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
  1761. hal_soc->ops->hal_reo_setup = hal_reo_setup_5332;
  1762. #ifdef REO_SHARED_QREF_TABLE_EN
  1763. hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
  1764. hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
  1765. hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
  1766. hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
  1767. hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
  1768. #endif
  1769. /* Overwrite the default BE ops */
  1770. hal_soc->ops->hal_get_rx_max_ba_window =
  1771. hal_get_rx_max_ba_window_qca5332;
  1772. hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size;
  1773. /* TX MONITOR */
  1774. #ifdef QCA_MONITOR_2_0_SUPPORT
  1775. hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
  1776. hal_txmon_is_mon_buf_addr_tlv_generic_be;
  1777. hal_soc->ops->hal_txmon_populate_packet_info =
  1778. hal_txmon_populate_packet_info_generic_be;
  1779. hal_soc->ops->hal_txmon_status_parse_tlv =
  1780. hal_txmon_status_parse_tlv_generic_be;
  1781. hal_soc->ops->hal_txmon_status_get_num_users =
  1782. hal_txmon_status_get_num_users_generic_be;
  1783. #endif /* QCA_MONITOR_2_0_SUPPORT */
  1784. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1785. hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
  1786. hal_tx_vdev_mismatch_routing_set_generic_be;
  1787. hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
  1788. hal_tx_mcast_mlo_reinject_routing_set_generic_be;
  1789. hal_soc->ops->hal_get_ba_aging_timeout =
  1790. hal_get_ba_aging_timeout_be_generic;
  1791. hal_soc->ops->hal_setup_link_idle_list =
  1792. hal_setup_link_idle_list_generic_be;
  1793. hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
  1794. hal_cookie_conversion_reg_cfg_generic_be;
  1795. hal_soc->ops->hal_set_ba_aging_timeout =
  1796. hal_set_ba_aging_timeout_be_generic;
  1797. hal_soc->ops->hal_tx_populate_bank_register =
  1798. hal_tx_populate_bank_register_be;
  1799. hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
  1800. hal_tx_vdev_mcast_ctrl_set_be;
  1801. };
  1802. struct hal_hw_srng_config hw_srng_table_5332[] = {
  1803. /* TODO: max_rings can populated by querying HW capabilities */
  1804. { /* REO_DST */
  1805. .start_ring_id = HAL_SRNG_REO2SW1,
  1806. .max_rings = 8,
  1807. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1808. .lmac_ring = FALSE,
  1809. .ring_dir = HAL_SRNG_DST_RING,
  1810. .reg_start = {
  1811. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1812. REO_REG_REG_BASE),
  1813. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1814. REO_REG_REG_BASE)
  1815. },
  1816. .reg_size = {
  1817. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1818. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1819. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1820. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1821. },
  1822. .max_size =
  1823. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1824. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1825. },
  1826. { /* REO_EXCEPTION */
  1827. /* Designating REO2SW0 ring as exception ring. This ring is
  1828. * similar to other REO2SW rings though it is named as REO2SW0.
  1829. * Any of theREO2SW rings can be used as exception ring.
  1830. */
  1831. .start_ring_id = HAL_SRNG_REO2SW0,
  1832. .max_rings = 1,
  1833. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1834. .lmac_ring = FALSE,
  1835. .ring_dir = HAL_SRNG_DST_RING,
  1836. .reg_start = {
  1837. HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
  1838. REO_REG_REG_BASE),
  1839. HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
  1840. REO_REG_REG_BASE)
  1841. },
  1842. /* Single ring - provide ring size if multiple rings of this
  1843. * type are supported
  1844. */
  1845. .reg_size = {},
  1846. .max_size =
  1847. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
  1848. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
  1849. },
  1850. { /* REO_REINJECT */
  1851. .start_ring_id = HAL_SRNG_SW2REO,
  1852. .max_rings = 4,
  1853. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1854. .lmac_ring = FALSE,
  1855. .ring_dir = HAL_SRNG_SRC_RING,
  1856. .reg_start = {
  1857. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1858. REO_REG_REG_BASE),
  1859. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1860. REO_REG_REG_BASE)
  1861. },
  1862. /* Single ring - provide ring size if multiple rings of this
  1863. * type are supported
  1864. */
  1865. .reg_size = {
  1866. HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
  1867. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
  1868. HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
  1869. HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
  1870. },
  1871. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1872. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1873. },
  1874. { /* REO_CMD */
  1875. .start_ring_id = HAL_SRNG_REO_CMD,
  1876. .max_rings = 1,
  1877. .entry_size = (sizeof(struct tlv_32_hdr) +
  1878. sizeof(struct reo_get_queue_stats)) >> 2,
  1879. .lmac_ring = FALSE,
  1880. .ring_dir = HAL_SRNG_SRC_RING,
  1881. .reg_start = {
  1882. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1883. REO_REG_REG_BASE),
  1884. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1885. REO_REG_REG_BASE),
  1886. },
  1887. /* Single ring - provide ring size if multiple rings of this
  1888. * type are supported
  1889. */
  1890. .reg_size = {},
  1891. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1892. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1893. },
  1894. { /* REO_STATUS */
  1895. .start_ring_id = HAL_SRNG_REO_STATUS,
  1896. .max_rings = 1,
  1897. .entry_size = (sizeof(struct tlv_32_hdr) +
  1898. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1899. .lmac_ring = FALSE,
  1900. .ring_dir = HAL_SRNG_DST_RING,
  1901. .reg_start = {
  1902. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1903. REO_REG_REG_BASE),
  1904. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1905. REO_REG_REG_BASE),
  1906. },
  1907. /* Single ring - provide ring size if multiple rings of this
  1908. * type are supported
  1909. */
  1910. .reg_size = {},
  1911. .max_size =
  1912. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1913. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1914. },
  1915. { /* TCL_DATA */
  1916. .start_ring_id = HAL_SRNG_SW2TCL1,
  1917. .max_rings = 6,
  1918. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1919. .lmac_ring = FALSE,
  1920. .ring_dir = HAL_SRNG_SRC_RING,
  1921. .reg_start = {
  1922. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1923. MAC_TCL_REG_REG_BASE),
  1924. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1925. MAC_TCL_REG_REG_BASE),
  1926. },
  1927. .reg_size = {
  1928. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1929. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1930. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1931. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1932. },
  1933. .max_size =
  1934. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1935. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1936. },
  1937. { /* TCL_CMD/CREDIT */
  1938. /* qca8074v2 and qca5332 uses this ring for data commands */
  1939. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1940. .max_rings = 1,
  1941. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1942. .lmac_ring = FALSE,
  1943. .ring_dir = HAL_SRNG_SRC_RING,
  1944. .reg_start = {
  1945. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1946. MAC_TCL_REG_REG_BASE),
  1947. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1948. MAC_TCL_REG_REG_BASE),
  1949. },
  1950. /* Single ring - provide ring size if multiple rings of this
  1951. * type are supported
  1952. */
  1953. .reg_size = {},
  1954. .max_size =
  1955. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1956. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1957. },
  1958. { /* TCL_STATUS */
  1959. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1960. .max_rings = 1,
  1961. .entry_size = (sizeof(struct tlv_32_hdr) +
  1962. sizeof(struct tcl_status_ring)) >> 2,
  1963. .lmac_ring = FALSE,
  1964. .ring_dir = HAL_SRNG_DST_RING,
  1965. .reg_start = {
  1966. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1967. MAC_TCL_REG_REG_BASE),
  1968. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1969. MAC_TCL_REG_REG_BASE),
  1970. },
  1971. /* Single ring - provide ring size if multiple rings of this
  1972. * type are supported
  1973. */
  1974. .reg_size = {},
  1975. .max_size =
  1976. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1977. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1978. },
  1979. { /* CE_SRC */
  1980. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1981. .max_rings = 16,
  1982. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1983. .lmac_ring = FALSE,
  1984. .ring_dir = HAL_SRNG_SRC_RING,
  1985. .reg_start = {
  1986. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
  1987. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1988. HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
  1989. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1990. },
  1991. .reg_size = {
  1992. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1993. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1994. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1995. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1996. },
  1997. .max_size =
  1998. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
  1999. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
  2000. },
  2001. { /* CE_DST */
  2002. .start_ring_id = HAL_SRNG_CE_0_DST,
  2003. .max_rings = 16,
  2004. .entry_size = 8 >> 2,
  2005. /*TODO: entry_size above should actually be
  2006. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  2007. * of struct ce_dst_desc in HW header files
  2008. */
  2009. .lmac_ring = FALSE,
  2010. .ring_dir = HAL_SRNG_SRC_RING,
  2011. .reg_start = {
  2012. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  2013. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2014. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  2015. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2016. },
  2017. .reg_size = {
  2018. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2019. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2020. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2021. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2022. },
  2023. .max_size =
  2024. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  2025. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  2026. },
  2027. { /* CE_DST_STATUS */
  2028. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  2029. .max_rings = 16,
  2030. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  2031. .lmac_ring = FALSE,
  2032. .ring_dir = HAL_SRNG_DST_RING,
  2033. .reg_start = {
  2034. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  2035. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2036. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  2037. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2038. },
  2039. /* TODO: check destination status ring registers */
  2040. .reg_size = {
  2041. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2042. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2043. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2044. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2045. },
  2046. .max_size =
  2047. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  2048. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  2049. },
  2050. { /* WBM_IDLE_LINK */
  2051. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  2052. .max_rings = 1,
  2053. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  2054. .lmac_ring = FALSE,
  2055. .ring_dir = HAL_SRNG_SRC_RING,
  2056. .reg_start = {
  2057. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  2058. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
  2059. },
  2060. /* Single ring - provide ring size if multiple rings of this
  2061. * type are supported
  2062. */
  2063. .reg_size = {},
  2064. .max_size =
  2065. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  2066. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  2067. },
  2068. { /* SW2WBM_RELEASE */
  2069. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  2070. .max_rings = 1,
  2071. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2072. .lmac_ring = FALSE,
  2073. .ring_dir = HAL_SRNG_SRC_RING,
  2074. .reg_start = {
  2075. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  2076. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
  2077. },
  2078. /* Single ring - provide ring size if multiple rings of this
  2079. * type are supported
  2080. */
  2081. .reg_size = {},
  2082. .max_size =
  2083. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2084. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2085. },
  2086. { /* WBM2SW_RELEASE */
  2087. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  2088. .max_rings = 8,
  2089. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2090. .lmac_ring = FALSE,
  2091. .ring_dir = HAL_SRNG_DST_RING,
  2092. .reg_start = {
  2093. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  2094. WBM_REG_REG_BASE),
  2095. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  2096. WBM_REG_REG_BASE),
  2097. },
  2098. .reg_size = {
  2099. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
  2100. WBM_REG_REG_BASE) -
  2101. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  2102. WBM_REG_REG_BASE),
  2103. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
  2104. WBM_REG_REG_BASE) -
  2105. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  2106. WBM_REG_REG_BASE),
  2107. },
  2108. .max_size =
  2109. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2110. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2111. },
  2112. { /* RXDMA_BUF */
  2113. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  2114. #ifdef IPA_OFFLOAD
  2115. .max_rings = 3,
  2116. #else
  2117. .max_rings = 3,
  2118. #endif
  2119. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2120. .lmac_ring = TRUE,
  2121. .ring_dir = HAL_SRNG_SRC_RING,
  2122. /* reg_start is not set because LMAC rings are not accessed
  2123. * from host
  2124. */
  2125. .reg_start = {},
  2126. .reg_size = {},
  2127. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2128. },
  2129. { /* RXDMA_DST */
  2130. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  2131. .max_rings = 0,
  2132. .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
  2133. .lmac_ring = TRUE,
  2134. .ring_dir = HAL_SRNG_DST_RING,
  2135. /* reg_start is not set because LMAC rings are not accessed
  2136. * from host
  2137. */
  2138. .reg_start = {},
  2139. .reg_size = {},
  2140. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2141. },
  2142. #ifdef QCA_MONITOR_2_0_SUPPORT
  2143. { /* RXDMA_MONITOR_BUF */
  2144. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  2145. .max_rings = 1,
  2146. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  2147. .lmac_ring = TRUE,
  2148. .ring_dir = HAL_SRNG_SRC_RING,
  2149. /* reg_start is not set because LMAC rings are not accessed
  2150. * from host
  2151. */
  2152. .reg_start = {},
  2153. .reg_size = {},
  2154. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2155. },
  2156. #else
  2157. {},
  2158. #endif
  2159. { /* RXDMA_MONITOR_STATUS */
  2160. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  2161. .max_rings = 0,
  2162. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2163. .lmac_ring = TRUE,
  2164. .ring_dir = HAL_SRNG_SRC_RING,
  2165. /* reg_start is not set because LMAC rings are not accessed
  2166. * from host
  2167. */
  2168. .reg_start = {},
  2169. .reg_size = {},
  2170. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2171. },
  2172. #ifdef QCA_MONITOR_2_0_SUPPORT
  2173. { /* RXDMA_MONITOR_DST */
  2174. .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
  2175. .max_rings = 2,
  2176. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  2177. .lmac_ring = TRUE,
  2178. .ring_dir = HAL_SRNG_DST_RING,
  2179. /* reg_start is not set because LMAC rings are not accessed
  2180. * from host
  2181. */
  2182. .reg_start = {},
  2183. .reg_size = {},
  2184. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2185. },
  2186. #else
  2187. {},
  2188. #endif
  2189. { /* RXDMA_MONITOR_DESC */
  2190. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  2191. .max_rings = 0,
  2192. .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
  2193. .lmac_ring = TRUE,
  2194. .ring_dir = HAL_SRNG_DST_RING,
  2195. /* reg_start is not set because LMAC rings are not accessed
  2196. * from host
  2197. */
  2198. .reg_start = {},
  2199. .reg_size = {},
  2200. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2201. },
  2202. { /* DIR_BUF_RX_DMA_SRC */
  2203. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  2204. /* one ring for spectral and one ring for cfr */
  2205. .max_rings = 2,
  2206. .entry_size = 2,
  2207. .lmac_ring = TRUE,
  2208. .ring_dir = HAL_SRNG_SRC_RING,
  2209. /* reg_start is not set because LMAC rings are not accessed
  2210. * from host
  2211. */
  2212. .reg_start = {},
  2213. .reg_size = {},
  2214. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2215. },
  2216. #ifdef WLAN_FEATURE_CIF_CFR
  2217. { /* WIFI_POS_SRC */
  2218. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  2219. .max_rings = 1,
  2220. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  2221. .lmac_ring = TRUE,
  2222. .ring_dir = HAL_SRNG_SRC_RING,
  2223. /* reg_start is not set because LMAC rings are not accessed
  2224. * from host
  2225. */
  2226. .reg_start = {},
  2227. .reg_size = {},
  2228. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2229. },
  2230. #endif
  2231. #ifdef QCA_MONITOR_2_0_SUPPORT
  2232. { /* TX_MONITOR_BUF */
  2233. .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
  2234. .max_rings = 1,
  2235. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  2236. .lmac_ring = TRUE,
  2237. .ring_dir = HAL_SRNG_SRC_RING,
  2238. /* reg_start is not set because LMAC rings are not accessed
  2239. * from host
  2240. */
  2241. .reg_start = {},
  2242. .reg_size = {},
  2243. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2244. },
  2245. { /* TX_MONITOR_DST */
  2246. .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
  2247. .max_rings = 2,
  2248. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  2249. .lmac_ring = TRUE,
  2250. .ring_dir = HAL_SRNG_DST_RING,
  2251. /* reg_start is not set because LMAC rings are not accessed
  2252. * from host
  2253. */
  2254. .reg_start = {},
  2255. .reg_size = {},
  2256. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2257. },
  2258. #else
  2259. {},
  2260. {},
  2261. #endif
  2262. { /* SW2RXDMA */
  2263. .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
  2264. .max_rings = 3,
  2265. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2266. .lmac_ring = TRUE,
  2267. .ring_dir = HAL_SRNG_SRC_RING,
  2268. /* reg_start is not set because LMAC rings are not accessed
  2269. * from host
  2270. */
  2271. .reg_start = {},
  2272. .reg_size = {},
  2273. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2274. .dmac_cmn_ring = TRUE,
  2275. },
  2276. };
  2277. /**
  2278. * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset
  2279. * applicable only for qca5332
  2280. * @hal_soc: HAL Soc handle
  2281. *
  2282. * Return: None
  2283. */
  2284. static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc)
  2285. {
  2286. int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
  2287. hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
  2288. hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
  2289. hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
  2290. hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
  2291. REG_OFFSET(DST, PRODUCER_INT2_SETUP);
  2292. }
  2293. /**
  2294. * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops,
  2295. * offset and srng table
  2296. * Return: void
  2297. */
  2298. void hal_qca5332_attach(struct hal_soc *hal_soc)
  2299. {
  2300. hal_soc->hw_srng_table = hw_srng_table_5332;
  2301. hal_srng_hw_reg_offset_init_generic(hal_soc);
  2302. hal_srng_hw_reg_offset_init_qca5332(hal_soc);
  2303. hal_hw_txrx_default_ops_attach_be(hal_soc);
  2304. hal_hw_txrx_ops_attach_qca5332(hal_soc);
  2305. if (hal_soc->static_window_map)
  2306. hal_write_window_register(hal_soc);
  2307. hal_soc->dmac_cmn_src_rxbuf_ring = true;
  2308. }