wsa884x.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static const struct wsa_reg_mask_val reg_init_2S[] = {
  125. {REG_FIELD_VALUE(CLSH_CTL_1, SLR_MAX, 0x02)},
  126. {REG_FIELD_VALUE(CLSH_V_HD_PA, V_HD_PA, 0x13)},
  127. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_VTH, 0x03)},
  128. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_HYST, 0x03)},
  129. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG2, DAC_VCM_SHIFT, 0x06)},
  130. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG3, DAC_VCM_SHIFT, 0x14)},
  131. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG4, DAC_VCM_SHIFT, 0x19)},
  132. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG5, DAC_VCM_SHIFT, 0x1B)},
  133. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG6, DAC_VCM_SHIFT, 0x1C)},
  134. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG7, DAC_VCM_SHIFT_FINAL_OVERRIDE, 0x01)},
  135. };
  136. static const struct wsa_reg_mask_val reg_init_uvlo[] = {
  137. {WSA884X_UVLO_PROG, 0xFF, 0x77},
  138. {WSA884X_PA_FSM_TIMER0, 0xFF, 0xC0},
  139. {WSA884X_UVLO_DEGLITCH_CTL, 0xFF, 0x1D},
  140. {WSA884X_UVLO_PROG1, 0xFF, 0x40},
  141. };
  142. static int wsa884x_handle_post_irq(void *data);
  143. static int wsa884x_get_temperature(struct snd_soc_component *component,
  144. int *temp);
  145. enum {
  146. WSA8840 = 0,
  147. WSA8845 = 5,
  148. WSA8845H = 0xC,
  149. };
  150. enum {
  151. SPKR_STATUS = 0,
  152. WSA_SUPPLIES_LPM_MODE,
  153. SPKR_ADIE_LB,
  154. };
  155. enum {
  156. COMP_PORT_EN_STATUS_BIT = 0,
  157. VI_PORT_EN_STATUS_BIT,
  158. PBR_PORT_EN_STATUS_BIT,
  159. CPS_PORT_EN_STATUS_BIT,
  160. };
  161. enum {
  162. WSA884X_IRQ_INT_SAF2WAR = 0,
  163. WSA884X_IRQ_INT_WAR2SAF,
  164. WSA884X_IRQ_INT_DISABLE,
  165. WSA884X_IRQ_INT_OCP,
  166. WSA884X_IRQ_INT_CLIP,
  167. WSA884X_IRQ_INT_PDM_WD,
  168. WSA884X_IRQ_INT_CLK_WD,
  169. WSA884X_IRQ_INT_INTR_PIN,
  170. WSA884X_IRQ_INT_UVLO,
  171. WSA884X_IRQ_INT_PA_ON_ERR,
  172. WSA884X_NUM_IRQS,
  173. };
  174. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  175. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  176. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  177. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  178. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  179. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  180. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  181. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  182. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  183. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  184. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  185. };
  186. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  187. .name = "wsa884x",
  188. .irqs = wsa884x_irqs,
  189. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  190. .num_regs = 2,
  191. .status_base = WSA884X_INTR_STATUS0,
  192. .mask_base = WSA884X_INTR_MASK0,
  193. .type_base = WSA884X_INTR_LEVEL0,
  194. .ack_base = WSA884X_INTR_CLEAR0,
  195. .use_ack = 1,
  196. .runtime_pm = false,
  197. .handle_post_irq = wsa884x_handle_post_irq,
  198. .irq_drv_data = NULL,
  199. };
  200. static int wsa884x_handle_post_irq(void *data)
  201. {
  202. struct wsa884x_priv *wsa884x = data;
  203. u32 sts1 = 0, sts2 = 0;
  204. int retry = WSA884X_IRQ_RETRY;
  205. if (!wsa884x)
  206. return IRQ_NONE;
  207. if (!wsa884x->pa_mute) {
  208. do {
  209. wsa884x->pa_mute = 0;
  210. regmap_update_bits(wsa884x->regmap,
  211. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  212. usleep_range(1000, 1100);
  213. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  214. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  215. wsa884x->swr_slave->slave_irq_pending =
  216. ((sts1 || sts2) ? true : false);
  217. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  218. sts1, sts2);
  219. if (wsa884x->swr_slave->slave_irq_pending) {
  220. pr_debug("%s: IRQ retries left: %0d\n",
  221. __func__, retry);
  222. regmap_update_bits(wsa884x->regmap,
  223. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  224. wsa884x->pa_mute = 1;
  225. if (retry--)
  226. usleep_range(1000, 1100);
  227. } else {
  228. break;
  229. }
  230. } while (retry);
  231. }
  232. return IRQ_HANDLED;
  233. }
  234. #ifdef CONFIG_DEBUG_FS
  235. static int codec_debug_open(struct inode *inode, struct file *file)
  236. {
  237. file->private_data = inode->i_private;
  238. return 0;
  239. }
  240. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  241. {
  242. char *token;
  243. int base, cnt;
  244. token = strsep(&buf, " ");
  245. for (cnt = 0; cnt < num_of_par; cnt++) {
  246. if (token) {
  247. if ((token[1] == 'x') || (token[1] == 'X'))
  248. base = 16;
  249. else
  250. base = 10;
  251. if (kstrtou32(token, base, &param1[cnt]) != 0)
  252. return -EINVAL;
  253. token = strsep(&buf, " ");
  254. } else {
  255. return -EINVAL;
  256. }
  257. }
  258. return 0;
  259. }
  260. static bool is_swr_slave_reg_readable(int reg)
  261. {
  262. int ret = true;
  263. if (((reg > 0x46) && (reg < 0x4A)) ||
  264. ((reg > 0x4A) && (reg < 0x50)) ||
  265. ((reg > 0x55) && (reg < 0x60)) ||
  266. ((reg > 0x60) && (reg < 0x70)) ||
  267. ((reg > 0x70) && (reg < 0xC0)) ||
  268. ((reg > 0xC1) && (reg < 0xC8)) ||
  269. ((reg > 0xC8) && (reg < 0xD0)) ||
  270. ((reg > 0xD0) && (reg < 0xE0)) ||
  271. ((reg > 0xE0) && (reg < 0xF0)) ||
  272. ((reg > 0xF0) && (reg < 0x100)) ||
  273. ((reg > 0x105) && (reg < 0x120)) ||
  274. ((reg > 0x205) && (reg < 0x220)) ||
  275. ((reg > 0x305) && (reg < 0x320)) ||
  276. ((reg > 0x405) && (reg < 0x420)) ||
  277. ((reg > 0x505) && (reg < 0x520)) ||
  278. ((reg > 0x605) && (reg < 0x620)) ||
  279. ((reg > 0x127) && (reg < 0x130)) ||
  280. ((reg > 0x227) && (reg < 0x230)) ||
  281. ((reg > 0x327) && (reg < 0x330)) ||
  282. ((reg > 0x427) && (reg < 0x430)) ||
  283. ((reg > 0x527) && (reg < 0x530)) ||
  284. ((reg > 0x627) && (reg < 0x630)) ||
  285. ((reg > 0x137) && (reg < 0x200)) ||
  286. ((reg > 0x237) && (reg < 0x300)) ||
  287. ((reg > 0x337) && (reg < 0x400)) ||
  288. ((reg > 0x437) && (reg < 0x500)) ||
  289. ((reg > 0x537) && (reg < 0x600)) ||
  290. ((reg > 0x637) && (reg < 0xF00)) ||
  291. ((reg > 0xF05) && (reg < 0xF20)) ||
  292. ((reg > 0xF25) && (reg < 0xF30)) ||
  293. ((reg > 0xF35) && (reg < 0x2000)))
  294. ret = false;
  295. return ret;
  296. }
  297. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  298. size_t count, loff_t *ppos)
  299. {
  300. int i, reg_val, len;
  301. ssize_t total = 0;
  302. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  303. if (!ubuf || !ppos)
  304. return 0;
  305. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  306. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  307. if (!is_swr_slave_reg_readable(i))
  308. continue;
  309. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  310. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  311. (reg_val & 0xFF));
  312. if (len < 0) {
  313. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  314. total = -EFAULT;
  315. goto copy_err;
  316. }
  317. if ((total + len) >= count - 1)
  318. break;
  319. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  320. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  321. total = -EFAULT;
  322. goto copy_err;
  323. }
  324. total += len;
  325. *ppos += len;
  326. }
  327. copy_err:
  328. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  329. return total;
  330. }
  331. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  332. size_t count, loff_t *ppos)
  333. {
  334. struct swr_device *pdev;
  335. if (!count || !file || !ppos || !ubuf)
  336. return -EINVAL;
  337. pdev = file->private_data;
  338. if (!pdev)
  339. return -EINVAL;
  340. if (*ppos < 0)
  341. return -EINVAL;
  342. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  343. }
  344. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  345. size_t count, loff_t *ppos)
  346. {
  347. char lbuf[SWR_SLV_RD_BUF_LEN];
  348. struct swr_device *pdev = NULL;
  349. struct wsa884x_priv *wsa884x = NULL;
  350. if (!count || !file || !ppos || !ubuf)
  351. return -EINVAL;
  352. pdev = file->private_data;
  353. if (!pdev)
  354. return -EINVAL;
  355. wsa884x = swr_get_dev_data(pdev);
  356. if (!wsa884x)
  357. return -EINVAL;
  358. if (*ppos < 0)
  359. return -EINVAL;
  360. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  361. (wsa884x->read_data & 0xFF));
  362. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  363. strnlen(lbuf, 7));
  364. }
  365. static ssize_t codec_debug_peek_write(struct file *file,
  366. const char __user *ubuf, size_t cnt, loff_t *ppos)
  367. {
  368. char lbuf[SWR_SLV_WR_BUF_LEN];
  369. int rc = 0;
  370. u32 param[5];
  371. struct swr_device *pdev = NULL;
  372. struct wsa884x_priv *wsa884x = NULL;
  373. if (!cnt || !file || !ppos || !ubuf)
  374. return -EINVAL;
  375. pdev = file->private_data;
  376. if (!pdev)
  377. return -EINVAL;
  378. wsa884x = swr_get_dev_data(pdev);
  379. if (!wsa884x)
  380. return -EINVAL;
  381. if (*ppos < 0)
  382. return -EINVAL;
  383. if (cnt > sizeof(lbuf) - 1)
  384. return -EINVAL;
  385. rc = copy_from_user(lbuf, ubuf, cnt);
  386. if (rc)
  387. return -EFAULT;
  388. lbuf[cnt] = '\0';
  389. rc = get_parameters(lbuf, param, 1);
  390. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  391. return -EINVAL;
  392. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  393. if (rc == 0)
  394. rc = cnt;
  395. else
  396. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  397. return rc;
  398. }
  399. static ssize_t codec_debug_write(struct file *file,
  400. const char __user *ubuf, size_t cnt, loff_t *ppos)
  401. {
  402. char lbuf[SWR_SLV_WR_BUF_LEN];
  403. int rc = 0;
  404. u32 param[5];
  405. struct swr_device *pdev;
  406. if (!file || !ppos || !ubuf)
  407. return -EINVAL;
  408. pdev = file->private_data;
  409. if (!pdev)
  410. return -EINVAL;
  411. if (cnt > sizeof(lbuf) - 1)
  412. return -EINVAL;
  413. rc = copy_from_user(lbuf, ubuf, cnt);
  414. if (rc)
  415. return -EFAULT;
  416. lbuf[cnt] = '\0';
  417. rc = get_parameters(lbuf, param, 2);
  418. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  419. (param[1] <= 0xFF) && (rc == 0)))
  420. return -EINVAL;
  421. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  422. if (rc == 0)
  423. rc = cnt;
  424. else
  425. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  426. return rc;
  427. }
  428. static const struct file_operations codec_debug_write_ops = {
  429. .open = codec_debug_open,
  430. .write = codec_debug_write,
  431. };
  432. static const struct file_operations codec_debug_read_ops = {
  433. .open = codec_debug_open,
  434. .read = codec_debug_read,
  435. .write = codec_debug_peek_write,
  436. };
  437. static const struct file_operations codec_debug_dump_ops = {
  438. .open = codec_debug_open,
  439. .read = codec_debug_dump,
  440. };
  441. #endif
  442. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  443. {
  444. mutex_lock(&wsa884x->res_lock);
  445. regcache_mark_dirty(wsa884x->regmap);
  446. regcache_sync(wsa884x->regmap);
  447. mutex_unlock(&wsa884x->res_lock);
  448. }
  449. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  450. {
  451. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  452. __func__, irq);
  453. return IRQ_HANDLED;
  454. }
  455. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  456. {
  457. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  458. __func__, irq);
  459. return IRQ_HANDLED;
  460. }
  461. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  462. {
  463. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  464. __func__, irq);
  465. return IRQ_HANDLED;
  466. }
  467. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  468. {
  469. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  470. __func__, irq);
  471. return IRQ_HANDLED;
  472. }
  473. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  474. {
  475. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  476. __func__, irq);
  477. return IRQ_HANDLED;
  478. }
  479. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  480. {
  481. struct wsa884x_priv *wsa884x = data;
  482. struct snd_soc_component *component = NULL;
  483. if (!wsa884x)
  484. return IRQ_NONE;
  485. component = wsa884x->component;
  486. snd_soc_component_update_bits(component,
  487. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  488. snd_soc_component_update_bits(component,
  489. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  490. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  491. __func__, irq);
  492. return IRQ_HANDLED;
  493. }
  494. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  495. {
  496. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  497. __func__, irq);
  498. return IRQ_HANDLED;
  499. }
  500. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  501. {
  502. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  503. __func__, irq);
  504. return IRQ_HANDLED;
  505. }
  506. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  507. {
  508. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  509. __func__, irq);
  510. return IRQ_HANDLED;
  511. }
  512. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  513. {
  514. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  515. struct wsa884x_priv *wsa884x = data;
  516. struct snd_soc_component *component = NULL;
  517. if (!wsa884x)
  518. return IRQ_NONE;
  519. component = wsa884x->component;
  520. if (!component)
  521. return IRQ_NONE;
  522. snd_soc_component_update_bits(component,
  523. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  524. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  525. & 0x1F);
  526. if (pa_fsm_sta)
  527. pa_fsm_err = snd_soc_component_read(component,
  528. WSA884X_PA_FSM_ERR_COND0);
  529. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  530. __func__, irq);
  531. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  532. 0x10, 0x00);
  533. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  534. 0x10, 0x10);
  535. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  536. 0x10, 0x00);
  537. return IRQ_HANDLED;
  538. }
  539. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  540. {
  541. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  542. u8 igain;
  543. u8 vgain;
  544. switch (wsa884x->bat_cfg) {
  545. case CONFIG_1S:
  546. case EXT_1S:
  547. switch (wsa884x->system_gain) {
  548. case G_21_DB:
  549. wsa884x->comp_offset = COMP_OFFSET0;
  550. wsa884x->min_gain = G_0_DB;
  551. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  552. break;
  553. case G_19P5_DB:
  554. wsa884x->comp_offset = COMP_OFFSET1;
  555. wsa884x->min_gain = G_M1P5_DB;
  556. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  557. break;
  558. case G_18_DB:
  559. wsa884x->comp_offset = COMP_OFFSET2;
  560. wsa884x->min_gain = G_M3_DB;
  561. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  562. break;
  563. case G_16P5_DB:
  564. wsa884x->comp_offset = COMP_OFFSET3;
  565. wsa884x->min_gain = G_M4P5_DB;
  566. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  567. break;
  568. default:
  569. wsa884x->comp_offset = COMP_OFFSET4;
  570. wsa884x->min_gain = G_M6_DB;
  571. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  572. break;
  573. }
  574. break;
  575. case CONFIG_3S:
  576. case EXT_3S:
  577. wsa884x->comp_offset = COMP_OFFSET0;
  578. wsa884x->min_gain = G_7P5_DB;
  579. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  580. break;
  581. case EXT_ABOVE_3S:
  582. wsa884x->comp_offset = COMP_OFFSET0;
  583. wsa884x->min_gain = G_12_DB;
  584. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  585. break;
  586. default:
  587. wsa884x->comp_offset = COMP_OFFSET0;
  588. wsa884x->min_gain = G_0_DB;
  589. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  590. break;
  591. }
  592. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  593. vgain = vsense_gain_data[wsa884x->system_gain];
  594. snd_soc_component_update_bits(component,
  595. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  596. snd_soc_component_update_bits(component,
  597. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  598. snd_soc_component_update_bits(component,
  599. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  600. if (wsa884x->comp_enable) {
  601. snd_soc_component_update_bits(component,
  602. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  603. wsa884x->comp_offset));
  604. snd_soc_component_update_bits(component,
  605. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  606. } else {
  607. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  608. snd_soc_component_update_bits(component,
  609. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  610. snd_soc_component_update_bits(component,
  611. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  612. }
  613. return 0;
  614. }
  615. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  616. {
  617. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  618. int vth1_reg_val;
  619. int vth2_reg_val;
  620. int vth3_reg_val;
  621. int vth4_reg_val;
  622. int vth5_reg_val;
  623. int vth6_reg_val;
  624. int vth7_reg_val;
  625. int vth8_reg_val;
  626. int vth9_reg_val;
  627. int vth10_reg_val;
  628. int vth11_reg_val;
  629. int vth12_reg_val;
  630. int vth13_reg_val;
  631. int vth14_reg_val;
  632. int vth15_reg_val;
  633. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  634. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  635. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  636. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  637. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  638. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  639. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  640. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  641. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  642. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  643. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  644. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  645. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  646. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  647. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  648. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  649. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  650. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  651. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  652. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  653. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  654. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  655. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  656. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  657. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  658. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  659. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  660. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  661. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  662. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  663. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  664. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  665. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  666. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  667. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  668. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  669. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  670. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  671. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  672. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  673. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  674. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  675. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  676. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  677. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  678. return 0;
  679. }
  680. static void wsa_noise_gate_write(struct snd_soc_component *component,
  681. int imode)
  682. {
  683. switch (imode) {
  684. case NG1:
  685. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  686. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  687. break;
  688. case NG2:
  689. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  690. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  691. break;
  692. case NG3:
  693. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  694. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  695. break;
  696. default:
  697. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  698. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  699. break;
  700. }
  701. }
  702. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  703. struct snd_ctl_elem_value *ucontrol)
  704. {
  705. struct snd_soc_component *component =
  706. snd_soc_kcontrol_component(kcontrol);
  707. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  708. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  709. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  710. wsa884x->dev_mode);
  711. return 0;
  712. }
  713. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  714. struct snd_ctl_elem_value *ucontrol)
  715. {
  716. struct snd_soc_component *component =
  717. snd_soc_kcontrol_component(kcontrol);
  718. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  719. int dev_mode;
  720. int wsa_dev_index;
  721. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  722. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  723. dev_mode = ucontrol->value.integer.value[0];
  724. else
  725. return -EINVAL;
  726. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  727. __func__, wsa884x->dev_mode, dev_mode);
  728. /* Check if input parameter is in range */
  729. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  730. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  731. wsa884x->dev_mode = dev_mode;
  732. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  733. } else {
  734. return -EINVAL;
  735. }
  736. return 0;
  737. }
  738. static const char * const wsa_pa_gain_text[] = {
  739. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  740. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  741. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  742. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  743. };
  744. static const struct soc_enum wsa_pa_gain_enum =
  745. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  746. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  747. struct snd_ctl_elem_value *ucontrol)
  748. {
  749. struct snd_soc_component *component =
  750. snd_soc_kcontrol_component(kcontrol);
  751. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  752. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  753. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  754. wsa884x->pa_gain);
  755. return 0;
  756. }
  757. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  758. struct snd_ctl_elem_value *ucontrol)
  759. {
  760. struct snd_soc_component *component =
  761. snd_soc_kcontrol_component(kcontrol);
  762. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  763. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  764. __func__, ucontrol->value.integer.value[0]);
  765. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  766. return 0;
  767. }
  768. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  769. struct snd_ctl_elem_value *ucontrol)
  770. {
  771. struct snd_soc_component *component =
  772. snd_soc_kcontrol_component(kcontrol);
  773. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  774. int temp = 0;
  775. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  776. temp = wsa884x->curr_temp;
  777. else
  778. wsa884x_get_temperature(component, &temp);
  779. ucontrol->value.integer.value[0] = temp;
  780. return 0;
  781. }
  782. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  783. void *file_private_data, struct file *file,
  784. char __user *buf, size_t count, loff_t pos)
  785. {
  786. struct wsa884x_priv *wsa884x;
  787. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  788. int len = 0;
  789. wsa884x = (struct wsa884x_priv *) entry->private_data;
  790. if (!wsa884x) {
  791. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  792. return -EINVAL;
  793. }
  794. switch (wsa884x->version) {
  795. case WSA884X_VERSION_1_0:
  796. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  797. break;
  798. default:
  799. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  800. break;
  801. }
  802. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  803. }
  804. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  805. .read = wsa884x_codec_version_read,
  806. };
  807. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  808. void *file_private_data,
  809. struct file *file,
  810. char __user *buf, size_t count,
  811. loff_t pos)
  812. {
  813. struct wsa884x_priv *wsa884x;
  814. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  815. int len = 0;
  816. wsa884x = (struct wsa884x_priv *) entry->private_data;
  817. if (!wsa884x) {
  818. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  819. return -EINVAL;
  820. }
  821. switch (wsa884x->variant) {
  822. case WSA8840:
  823. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  824. break;
  825. case WSA8845:
  826. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  827. break;
  828. case WSA8845H:
  829. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  830. break;
  831. default:
  832. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  833. break;
  834. }
  835. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  836. }
  837. static struct snd_info_entry_ops wsa884x_variant_ops = {
  838. .read = wsa884x_variant_read,
  839. };
  840. /*
  841. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  842. * @codec_root: The parent directory
  843. * @component: Codec instance
  844. *
  845. * Creates wsa884x module and version entry under the given
  846. * parent directory.
  847. *
  848. * Return: 0 on success or negative error code on failure.
  849. */
  850. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  851. struct snd_soc_component *component)
  852. {
  853. struct snd_info_entry *version_entry;
  854. struct snd_info_entry *variant_entry;
  855. struct wsa884x_priv *wsa884x;
  856. struct snd_soc_card *card;
  857. char name[80];
  858. if (!codec_root || !component)
  859. return -EINVAL;
  860. wsa884x = snd_soc_component_get_drvdata(component);
  861. if (wsa884x->entry) {
  862. dev_dbg(wsa884x->dev,
  863. "%s:wsa884x module already created\n", __func__);
  864. return 0;
  865. }
  866. card = component->card;
  867. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  868. wsa884x->swr_slave->addr);
  869. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  870. (const char *)name,
  871. codec_root);
  872. if (!wsa884x->entry) {
  873. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  874. __func__);
  875. return -ENOMEM;
  876. }
  877. wsa884x->entry->mode = S_IFDIR | 0555;
  878. if (snd_info_register(wsa884x->entry) < 0) {
  879. snd_info_free_entry(wsa884x->entry);
  880. return -ENOMEM;
  881. }
  882. version_entry = snd_info_create_card_entry(card->snd_card,
  883. "version",
  884. wsa884x->entry);
  885. if (!version_entry) {
  886. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  887. __func__);
  888. snd_info_free_entry(wsa884x->entry);
  889. return -ENOMEM;
  890. }
  891. version_entry->private_data = wsa884x;
  892. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  893. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  894. version_entry->c.ops = &wsa884x_codec_info_ops;
  895. if (snd_info_register(version_entry) < 0) {
  896. snd_info_free_entry(version_entry);
  897. snd_info_free_entry(wsa884x->entry);
  898. return -ENOMEM;
  899. }
  900. wsa884x->version_entry = version_entry;
  901. variant_entry = snd_info_create_card_entry(card->snd_card,
  902. "variant",
  903. wsa884x->entry);
  904. if (!variant_entry) {
  905. dev_dbg(component->dev,
  906. "%s: failed to create wsa884x variant entry\n",
  907. __func__);
  908. snd_info_free_entry(version_entry);
  909. snd_info_free_entry(wsa884x->entry);
  910. return -ENOMEM;
  911. }
  912. variant_entry->private_data = wsa884x;
  913. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  914. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  915. variant_entry->c.ops = &wsa884x_variant_ops;
  916. if (snd_info_register(variant_entry) < 0) {
  917. snd_info_free_entry(variant_entry);
  918. snd_info_free_entry(version_entry);
  919. snd_info_free_entry(wsa884x->entry);
  920. return -ENOMEM;
  921. }
  922. wsa884x->variant_entry = variant_entry;
  923. return 0;
  924. }
  925. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  926. /*
  927. * wsa884x_codec_get_dev_num - returns swr device number
  928. * @component: Codec instance
  929. *
  930. * Return: swr device number on success or negative error
  931. * code on failure.
  932. */
  933. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  934. {
  935. struct wsa884x_priv *wsa884x;
  936. if (!component)
  937. return -EINVAL;
  938. wsa884x = snd_soc_component_get_drvdata(component);
  939. if (!wsa884x) {
  940. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  941. return -EINVAL;
  942. }
  943. return wsa884x->swr_slave->dev_num;
  944. }
  945. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  946. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  947. struct snd_ctl_elem_value *ucontrol)
  948. {
  949. struct snd_soc_component *component =
  950. snd_soc_kcontrol_component(kcontrol);
  951. struct wsa884x_priv *wsa884x;
  952. if (!component)
  953. return -EINVAL;
  954. wsa884x = snd_soc_component_get_drvdata(component);
  955. if (!wsa884x) {
  956. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  957. return -EINVAL;
  958. }
  959. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  960. return 0;
  961. }
  962. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  963. struct snd_ctl_elem_value *ucontrol)
  964. {
  965. struct snd_soc_component *component =
  966. snd_soc_kcontrol_component(kcontrol);
  967. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  968. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  969. return 0;
  970. }
  971. /*
  972. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  973. * Return: 0 Valid configuration, 1 Invalid configuration
  974. */
  975. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  976. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  977. {
  978. u8 bat_cfg_reg;
  979. bool is_invalid_flag = true;
  980. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  981. dev_info(component->dev, "VPHX EN Status: %d", bat_cfg_reg);
  982. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  983. ibat_cfg_dts = EXT_ABOVE_3S;
  984. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  985. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  986. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  987. (ibat_cfg_dts == bat_cfg_reg))
  988. is_invalid_flag = false;
  989. return is_invalid_flag;
  990. }
  991. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  992. struct snd_ctl_elem_value *ucontrol)
  993. {
  994. struct snd_soc_component *component =
  995. snd_soc_kcontrol_component(kcontrol);
  996. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  997. int value = ucontrol->value.integer.value[0];
  998. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  999. __func__, wsa884x->comp_enable, value);
  1000. wsa884x->comp_enable = value;
  1001. return 0;
  1002. }
  1003. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  1004. struct snd_ctl_elem_value *ucontrol)
  1005. {
  1006. struct snd_soc_component *component =
  1007. snd_soc_kcontrol_component(kcontrol);
  1008. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1009. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  1010. return 0;
  1011. }
  1012. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. struct snd_soc_component *component =
  1016. snd_soc_kcontrol_component(kcontrol);
  1017. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1018. int value = ucontrol->value.integer.value[0];
  1019. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  1020. __func__, wsa884x->visense_enable, value);
  1021. wsa884x->visense_enable = value;
  1022. return 0;
  1023. }
  1024. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1025. struct snd_ctl_elem_value *ucontrol)
  1026. {
  1027. struct snd_soc_component *component =
  1028. snd_soc_kcontrol_component(kcontrol);
  1029. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1030. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1031. return 0;
  1032. }
  1033. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1034. struct snd_ctl_elem_value *ucontrol)
  1035. {
  1036. struct snd_soc_component *component =
  1037. snd_soc_kcontrol_component(kcontrol);
  1038. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1039. int value = ucontrol->value.integer.value[0];
  1040. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1041. __func__, wsa884x->pbr_enable, value);
  1042. wsa884x->pbr_enable = value;
  1043. return 0;
  1044. }
  1045. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1046. struct snd_ctl_elem_value *ucontrol)
  1047. {
  1048. struct snd_soc_component *component =
  1049. snd_soc_kcontrol_component(kcontrol);
  1050. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1051. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1052. return 0;
  1053. }
  1054. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1055. struct snd_ctl_elem_value *ucontrol)
  1056. {
  1057. struct snd_soc_component *component =
  1058. snd_soc_kcontrol_component(kcontrol);
  1059. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1060. int value = ucontrol->value.integer.value[0];
  1061. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1062. __func__, wsa884x->cps_enable, value);
  1063. wsa884x->cps_enable = value;
  1064. return 0;
  1065. }
  1066. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1067. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1068. wsa_pa_gain_get, wsa_pa_gain_put),
  1069. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1070. wsa_get_temp, NULL),
  1071. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1072. wsa884x_get_dev_num, NULL),
  1073. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1074. wsa_dev_mode_get, wsa_dev_mode_put),
  1075. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1076. wsa884x_get_compander, wsa884x_set_compander),
  1077. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1078. wsa884x_get_visense, wsa884x_set_visense),
  1079. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1080. wsa884x_get_pbr, wsa884x_set_pbr),
  1081. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1082. wsa884x_get_cps, wsa884x_set_cps),
  1083. };
  1084. static const struct snd_kcontrol_new swr_dac_port[] = {
  1085. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1086. };
  1087. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1088. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1089. u8 *port_type)
  1090. {
  1091. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1092. *port_id = wsa884x->port[port_idx].port_id;
  1093. *num_ch = wsa884x->port[port_idx].num_ch;
  1094. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1095. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1096. *port_type = wsa884x->port[port_idx].port_type;
  1097. return 0;
  1098. }
  1099. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1100. struct snd_kcontrol *kcontrol, int event)
  1101. {
  1102. struct snd_soc_component *component =
  1103. snd_soc_dapm_to_component(w->dapm);
  1104. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1105. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1106. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1107. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1108. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1109. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1110. u8 num_port = 0;
  1111. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1112. event, w->name);
  1113. if (wsa884x == NULL)
  1114. return -EINVAL;
  1115. switch (event) {
  1116. case SND_SOC_DAPM_PRE_PMU:
  1117. wsa884x_set_port(component, SWR_DAC_PORT,
  1118. &port_id[num_port], &num_ch[num_port],
  1119. &ch_mask[num_port], &ch_rate[num_port],
  1120. &port_type[num_port]);
  1121. if (wsa884x->dev_mode == RECEIVER)
  1122. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1123. ++num_port;
  1124. if (wsa884x->comp_enable) {
  1125. wsa884x_set_port(component, SWR_COMP_PORT,
  1126. &port_id[num_port], &num_ch[num_port],
  1127. &ch_mask[num_port], &ch_rate[num_port],
  1128. &port_type[num_port]);
  1129. ++num_port;
  1130. set_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1131. }
  1132. if (wsa884x->pbr_enable) {
  1133. wsa884x_set_port(component, SWR_PBR_PORT,
  1134. &port_id[num_port], &num_ch[num_port],
  1135. &ch_mask[num_port], &ch_rate[num_port],
  1136. &port_type[num_port]);
  1137. ++num_port;
  1138. set_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1139. }
  1140. if (wsa884x->visense_enable) {
  1141. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1142. &port_id[num_port], &num_ch[num_port],
  1143. &ch_mask[num_port], &ch_rate[num_port],
  1144. &port_type[num_port]);
  1145. ++num_port;
  1146. set_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1147. }
  1148. if (wsa884x->cps_enable) {
  1149. wsa884x_set_port(component, SWR_CPS_PORT,
  1150. &port_id[num_port], &num_ch[num_port],
  1151. &ch_mask[num_port], &ch_rate[num_port],
  1152. &port_type[num_port]);
  1153. ++num_port;
  1154. set_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1155. }
  1156. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1157. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1158. &port_type[0]);
  1159. break;
  1160. case SND_SOC_DAPM_POST_PMU:
  1161. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1162. break;
  1163. case SND_SOC_DAPM_PRE_PMD:
  1164. wsa884x_set_port(component, SWR_DAC_PORT,
  1165. &port_id[num_port], &num_ch[num_port],
  1166. &ch_mask[num_port], &ch_rate[num_port],
  1167. &port_type[num_port]);
  1168. ++num_port;
  1169. if (wsa884x->comp_enable &&
  1170. test_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1171. wsa884x_set_port(component, SWR_COMP_PORT,
  1172. &port_id[num_port], &num_ch[num_port],
  1173. &ch_mask[num_port], &ch_rate[num_port],
  1174. &port_type[num_port]);
  1175. ++num_port;
  1176. clear_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1177. }
  1178. if (wsa884x->pbr_enable &&
  1179. test_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1180. wsa884x_set_port(component, SWR_PBR_PORT,
  1181. &port_id[num_port], &num_ch[num_port],
  1182. &ch_mask[num_port], &ch_rate[num_port],
  1183. &port_type[num_port]);
  1184. ++num_port;
  1185. clear_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1186. }
  1187. if (wsa884x->visense_enable &&
  1188. test_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1189. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1190. &port_id[num_port], &num_ch[num_port],
  1191. &ch_mask[num_port], &ch_rate[num_port],
  1192. &port_type[num_port]);
  1193. ++num_port;
  1194. clear_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1195. }
  1196. if (wsa884x->cps_enable &&
  1197. test_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1198. wsa884x_set_port(component, SWR_CPS_PORT,
  1199. &port_id[num_port], &num_ch[num_port],
  1200. &ch_mask[num_port], &ch_rate[num_port],
  1201. &port_type[num_port]);
  1202. ++num_port;
  1203. clear_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1204. }
  1205. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1206. &ch_mask[0], &port_type[0]);
  1207. break;
  1208. case SND_SOC_DAPM_POST_PMD:
  1209. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1210. dev_err_ratelimited(component->dev,
  1211. "%s: set num ch failed\n", __func__);
  1212. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1213. wsa884x->swr_slave->dev_num,
  1214. false);
  1215. break;
  1216. default:
  1217. break;
  1218. }
  1219. return 0;
  1220. }
  1221. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1222. struct snd_kcontrol *kcontrol, int event)
  1223. {
  1224. struct snd_soc_component *component =
  1225. snd_soc_dapm_to_component(w->dapm);
  1226. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1227. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1228. switch (event) {
  1229. case SND_SOC_DAPM_POST_PMU:
  1230. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1231. wsa884x->swr_slave->dev_num,
  1232. true);
  1233. wsa884x_set_gain_parameters(component);
  1234. if (wsa884x->dev_mode == SPEAKER) {
  1235. snd_soc_component_update_bits(component,
  1236. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1237. } else {
  1238. snd_soc_component_update_bits(component,
  1239. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1240. snd_soc_component_update_bits(component,
  1241. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1242. snd_soc_component_update_bits(component,
  1243. REG_FIELD_VALUE(PWM_CLK_CTL,
  1244. PWM_CLK_FREQ_SEL, 0x01));
  1245. }
  1246. if (wsa884x->pbr_enable) {
  1247. snd_soc_component_update_bits(component,
  1248. REG_FIELD_VALUE(CURRENT_LIMIT,
  1249. CURRENT_LIMIT_OVRD_EN, 0x00));
  1250. switch (wsa884x->bat_cfg) {
  1251. case CONFIG_1S:
  1252. snd_soc_component_update_bits(component,
  1253. REG_FIELD_VALUE(CURRENT_LIMIT,
  1254. CURRENT_LIMIT, 0x15));
  1255. break;
  1256. case CONFIG_2S:
  1257. snd_soc_component_update_bits(component,
  1258. REG_FIELD_VALUE(CURRENT_LIMIT,
  1259. CURRENT_LIMIT, 0x11));
  1260. break;
  1261. case CONFIG_3S:
  1262. snd_soc_component_update_bits(component,
  1263. REG_FIELD_VALUE(CURRENT_LIMIT,
  1264. CURRENT_LIMIT, 0x0D));
  1265. break;
  1266. }
  1267. } else {
  1268. snd_soc_component_update_bits(component,
  1269. REG_FIELD_VALUE(CURRENT_LIMIT,
  1270. CURRENT_LIMIT_OVRD_EN, 0x01));
  1271. if (wsa884x->system_gain >= G_12_DB)
  1272. snd_soc_component_update_bits(component,
  1273. REG_FIELD_VALUE(CURRENT_LIMIT,
  1274. CURRENT_LIMIT, 0x15));
  1275. else
  1276. snd_soc_component_update_bits(component,
  1277. REG_FIELD_VALUE(CURRENT_LIMIT,
  1278. CURRENT_LIMIT, 0x09));
  1279. }
  1280. /* Force remove group */
  1281. swr_remove_from_group(wsa884x->swr_slave,
  1282. wsa884x->swr_slave->dev_num);
  1283. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1284. !wsa884x->pa_mute)
  1285. snd_soc_component_update_bits(component,
  1286. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1287. break;
  1288. case SND_SOC_DAPM_PRE_PMD:
  1289. snd_soc_component_update_bits(component,
  1290. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1291. snd_soc_component_update_bits(component,
  1292. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1293. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1294. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1295. wsa884x->pa_mute = 0;
  1296. break;
  1297. }
  1298. return 0;
  1299. }
  1300. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1301. SND_SOC_DAPM_INPUT("IN"),
  1302. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1303. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1304. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1305. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1306. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1307. };
  1308. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1309. {"SWR DAC_Port", "Switch", "IN"},
  1310. {"SPKR", NULL, "SWR DAC_Port"},
  1311. };
  1312. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1313. u8 num_port, unsigned int *ch_mask,
  1314. unsigned int *ch_rate, u8 *port_type)
  1315. {
  1316. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1317. int i;
  1318. if (!port || !ch_mask || !ch_rate ||
  1319. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1320. dev_err_ratelimited(component->dev,
  1321. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1322. __func__, port, ch_mask, ch_rate);
  1323. return -EINVAL;
  1324. }
  1325. for (i = 0; i < num_port; i++) {
  1326. wsa884x->port[i].port_id = port[i];
  1327. wsa884x->port[i].ch_mask = ch_mask[i];
  1328. wsa884x->port[i].ch_rate = ch_rate[i];
  1329. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1330. if (port_type)
  1331. wsa884x->port[i].port_type = port_type[i];
  1332. }
  1333. return 0;
  1334. }
  1335. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1336. static void wsa884x_codec_init(struct snd_soc_component *component)
  1337. {
  1338. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1339. int i;
  1340. if (!wsa884x)
  1341. return;
  1342. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1343. snd_soc_component_update_bits(component, reg_init[i].reg,
  1344. reg_init[i].mask, reg_init[i].val);
  1345. /* Register updates for 2S battery configuration */
  1346. if (wsa884x->bat_cfg == CONFIG_2S) {
  1347. for (i = 0; i < ARRAY_SIZE(reg_init_2S); i++)
  1348. snd_soc_component_update_bits(component, reg_init_2S[i].reg,
  1349. reg_init_2S[i].mask, reg_init_2S[i].val);
  1350. }
  1351. for (i = 0; i < ARRAY_SIZE(reg_init_uvlo); i++)
  1352. snd_soc_component_update_bits(component, reg_init_uvlo[i].reg,
  1353. reg_init_uvlo[i].mask, reg_init_uvlo[i].val);
  1354. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1355. }
  1356. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1357. struct wsa_temp_register *wsa_temp_reg)
  1358. {
  1359. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1360. if (!wsa884x) {
  1361. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1362. return -EINVAL;
  1363. }
  1364. mutex_lock(&wsa884x->res_lock);
  1365. snd_soc_component_update_bits(component,
  1366. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1367. snd_soc_component_update_bits(component,
  1368. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1369. snd_soc_component_update_bits(component,
  1370. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1371. snd_soc_component_update_bits(component,
  1372. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1373. snd_soc_component_update_bits(component,
  1374. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1375. snd_soc_component_update_bits(component,
  1376. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1377. snd_soc_component_update_bits(component,
  1378. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1379. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1380. WSA884X_TEMP_DIN_MSB);
  1381. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1382. WSA884X_TEMP_DIN_LSB);
  1383. snd_soc_component_update_bits(component,
  1384. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1385. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1386. WSA884X_OTP_REG_1);
  1387. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1388. WSA884X_OTP_REG_2);
  1389. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1390. WSA884X_OTP_REG_3);
  1391. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1392. WSA884X_OTP_REG_4);
  1393. snd_soc_component_update_bits(component,
  1394. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1395. mutex_unlock(&wsa884x->res_lock);
  1396. return 0;
  1397. }
  1398. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1399. int *temp)
  1400. {
  1401. struct wsa_temp_register reg;
  1402. int dmeas, d1, d2;
  1403. int ret = 0;
  1404. int temp_val = 0;
  1405. int t1 = T1_TEMP;
  1406. int t2 = T2_TEMP;
  1407. u8 retry = WSA884X_TEMP_RETRY;
  1408. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1409. if (!wsa884x)
  1410. return -EINVAL;
  1411. do {
  1412. ret = wsa884x_temp_reg_read(component, &reg);
  1413. if (ret) {
  1414. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1415. __func__, ret, wsa884x->curr_temp);
  1416. if (temp)
  1417. *temp = wsa884x->curr_temp;
  1418. return 0;
  1419. }
  1420. /*
  1421. * Temperature register values are expected to be in the
  1422. * following range.
  1423. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1424. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1425. */
  1426. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1427. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1428. reg.d1_lsb == 192)) ||
  1429. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1430. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1431. reg.d2_lsb == 192))) {
  1432. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1433. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1434. reg.d2_lsb);
  1435. }
  1436. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1437. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1438. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1439. if (d1 == d2)
  1440. temp_val = TEMP_INVALID;
  1441. else
  1442. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1443. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1444. temp_val >= HIGH_TEMP_THRESHOLD) {
  1445. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1446. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1447. if (retry--)
  1448. msleep(10);
  1449. } else {
  1450. break;
  1451. }
  1452. } while (retry);
  1453. wsa884x->curr_temp = temp_val;
  1454. if (temp)
  1455. *temp = temp_val;
  1456. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1457. __func__, temp_val, dmeas, d1, d2);
  1458. return ret;
  1459. }
  1460. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1461. {
  1462. char w_name[MAX_NAME_LEN];
  1463. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1464. struct swr_device *dev;
  1465. int variant = 0, version = 0;
  1466. struct snd_soc_dapm_context *dapm =
  1467. snd_soc_component_get_dapm(component);
  1468. if (!wsa884x)
  1469. return -EINVAL;
  1470. if (!component->name_prefix)
  1471. return -EINVAL;
  1472. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1473. dev = wsa884x->swr_slave;
  1474. wsa884x->component = component;
  1475. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1476. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1477. wsa884x->variant = variant;
  1478. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1479. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1480. wsa884x->version = version;
  1481. wsa884x->comp_offset = COMP_OFFSET2;
  1482. wsa884x_codec_init(component);
  1483. wsa884x->global_pa_cnt = 0;
  1484. memset(w_name, 0, sizeof(w_name));
  1485. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1486. sizeof(w_name));
  1487. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1488. memset(w_name, 0, sizeof(w_name));
  1489. strlcpy(w_name, "IN", sizeof(w_name));
  1490. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1491. memset(w_name, 0, sizeof(w_name));
  1492. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1493. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1494. memset(w_name, 0, sizeof(w_name));
  1495. strlcpy(w_name, "SPKR", sizeof(w_name));
  1496. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1497. snd_soc_dapm_sync(dapm);
  1498. return 0;
  1499. }
  1500. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1501. {
  1502. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1503. if (!wsa884x)
  1504. return;
  1505. snd_soc_component_exit_regmap(component);
  1506. return;
  1507. }
  1508. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1509. {
  1510. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1511. if (!wsa884x)
  1512. return 0;
  1513. wsa884x->dapm_bias_off = true;
  1514. return 0;
  1515. }
  1516. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1517. {
  1518. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1519. if (!wsa884x)
  1520. return 0;
  1521. wsa884x->dapm_bias_off = false;
  1522. return 0;
  1523. }
  1524. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1525. .name = "",
  1526. .probe = wsa884x_codec_probe,
  1527. .remove = wsa884x_codec_remove,
  1528. .controls = wsa884x_snd_controls,
  1529. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1530. .dapm_widgets = wsa884x_dapm_widgets,
  1531. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1532. .dapm_routes = wsa884x_audio_map,
  1533. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1534. .suspend = wsa884x_soc_codec_suspend,
  1535. .resume = wsa884x_soc_codec_resume,
  1536. };
  1537. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1538. {
  1539. int ret = 0;
  1540. if (enable)
  1541. ret = msm_cdc_pinctrl_select_active_state(
  1542. wsa884x->wsa_rst_np);
  1543. else
  1544. ret = msm_cdc_pinctrl_select_sleep_state(
  1545. wsa884x->wsa_rst_np);
  1546. if (ret != 0)
  1547. dev_err_ratelimited(wsa884x->dev,
  1548. "%s: Failed to turn state %d; ret=%d\n",
  1549. __func__, enable, ret);
  1550. return ret;
  1551. }
  1552. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1553. {
  1554. int ret;
  1555. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1556. if (ret)
  1557. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1558. return ret;
  1559. }
  1560. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1561. {
  1562. int ret;
  1563. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1564. if (ret)
  1565. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1566. return ret;
  1567. }
  1568. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1569. {
  1570. u8 retry = WSA884X_NUM_RETRY;
  1571. u8 devnum = 0;
  1572. struct swr_device *pdev;
  1573. pdev = wsa884x->swr_slave;
  1574. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1575. /* Retry after 1 msec delay */
  1576. usleep_range(1000, 1100);
  1577. }
  1578. pdev->dev_num = devnum;
  1579. wsa884x_regcache_sync(wsa884x);
  1580. return 0;
  1581. }
  1582. static int wsa884x_event_notify(struct notifier_block *nb,
  1583. unsigned long val, void *ptr)
  1584. {
  1585. u16 event = (val & 0xffff);
  1586. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1587. parent_nblock);
  1588. if (!wsa884x)
  1589. return -EINVAL;
  1590. switch (event) {
  1591. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1592. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1593. snd_soc_component_update_bits(wsa884x->component,
  1594. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1595. wsa884x_swr_down(wsa884x);
  1596. break;
  1597. case BOLERO_SLV_EVT_SSR_UP:
  1598. wsa884x_swr_up(wsa884x);
  1599. /* Add delay to allow enumerate */
  1600. usleep_range(20000, 20010);
  1601. wsa884x_swr_reset(wsa884x);
  1602. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1603. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1604. wsa884x->swr_wsa_port_params);
  1605. break;
  1606. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1607. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1608. snd_soc_component_update_bits(wsa884x->component,
  1609. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1610. snd_soc_component_update_bits(wsa884x->component,
  1611. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1612. }
  1613. break;
  1614. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1615. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1616. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1617. break;
  1618. default:
  1619. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1620. __func__, event);
  1621. break;
  1622. }
  1623. return 0;
  1624. }
  1625. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1626. {
  1627. u32 *dt_array, map_size, max_uc;
  1628. int ret = 0;
  1629. u32 cnt = 0;
  1630. u32 i, j;
  1631. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1632. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1633. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1634. map = &wsa884x->wsa_port_params;
  1635. map_uc = &wsa884x->swr_wsa_port_params;
  1636. if (!of_find_property(dev->of_node, prop,
  1637. &map_size)) {
  1638. dev_err(dev, "missing port mapping prop %s\n", prop);
  1639. ret = -EINVAL;
  1640. goto err_port_map;
  1641. }
  1642. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1643. if (max_uc != SWR_UC_MAX) {
  1644. dev_err(dev, "%s: port params not provided for all usecases\n",
  1645. __func__);
  1646. ret = -EINVAL;
  1647. goto err_port_map;
  1648. }
  1649. dt_array = kzalloc(map_size, GFP_KERNEL);
  1650. if (!dt_array) {
  1651. ret = -ENOMEM;
  1652. goto err_port_map;
  1653. }
  1654. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1655. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1656. if (ret) {
  1657. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1658. __func__, prop);
  1659. goto err_pdata_fail;
  1660. }
  1661. for (i = 0; i < max_uc; i++) {
  1662. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1663. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1664. (*map)[i][j].offset1 = dt_array[cnt];
  1665. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1666. }
  1667. (*map_uc)[i].pp = &(*map)[i][0];
  1668. }
  1669. kfree(dt_array);
  1670. return 0;
  1671. err_pdata_fail:
  1672. kfree(dt_array);
  1673. err_port_map:
  1674. return ret;
  1675. }
  1676. static int wsa884x_enable_supplies(struct device *dev,
  1677. struct wsa884x_priv *priv)
  1678. {
  1679. int ret = 0;
  1680. /* Parse power supplies */
  1681. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1682. &priv->num_supplies);
  1683. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1684. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1685. return -EINVAL;
  1686. }
  1687. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1688. priv->regulator, priv->num_supplies);
  1689. if (!priv->supplies) {
  1690. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1691. __func__);
  1692. return ret;
  1693. }
  1694. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1695. priv->regulator,
  1696. priv->num_supplies);
  1697. if (ret)
  1698. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1699. __func__);
  1700. return ret;
  1701. }
  1702. static struct snd_soc_dai_driver wsa_dai[] = {
  1703. {
  1704. .name = "",
  1705. .playback = {
  1706. .stream_name = "",
  1707. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1708. .formats = WSA884X_FORMATS,
  1709. .rate_max = 192000,
  1710. .rate_min = 8000,
  1711. .channels_min = 1,
  1712. .channels_max = 2,
  1713. },
  1714. },
  1715. };
  1716. static int wsa884x_swr_probe(struct swr_device *pdev)
  1717. {
  1718. int ret = 0;
  1719. struct wsa884x_priv *wsa884x;
  1720. u8 devnum = 0;
  1721. bool pin_state_current = false;
  1722. struct wsa_ctrl_platform_data *plat_data = NULL;
  1723. struct snd_soc_component *component;
  1724. u32 noise_gate_mode;
  1725. char buffer[MAX_NAME_LEN];
  1726. int dev_index = 0;
  1727. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1728. u8 wo0_val;
  1729. int sys_gain_size, sys_gain_length;
  1730. int wsa_dev_index;
  1731. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1732. GFP_KERNEL);
  1733. if (!wsa884x)
  1734. return -ENOMEM;
  1735. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1736. GFP_KERNEL);
  1737. if (!wsa884x_sub_regmap_irq_chip)
  1738. return -ENOMEM;
  1739. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1740. sizeof(struct regmap_irq_chip));
  1741. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1742. if (ret) {
  1743. ret = -EPROBE_DEFER;
  1744. goto err;
  1745. }
  1746. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1747. "qcom,spkr-sd-n-node", 0);
  1748. if (!wsa884x->wsa_rst_np) {
  1749. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1750. goto err_supply;
  1751. }
  1752. swr_set_dev_data(pdev, wsa884x);
  1753. wsa884x->swr_slave = pdev;
  1754. wsa884x->dev = &pdev->dev;
  1755. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1756. wsa884x_gpio_ctrl(wsa884x, true);
  1757. /*
  1758. * Add 5msec delay to provide sufficient time for
  1759. * soundwire auto enumeration of slave devices as
  1760. * per HW requirement.
  1761. */
  1762. usleep_range(5000, 5010);
  1763. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1764. if (ret) {
  1765. dev_dbg(&pdev->dev,
  1766. "%s get devnum %d for dev addr %lx failed\n",
  1767. __func__, devnum, pdev->addr);
  1768. ret = -EPROBE_DEFER;
  1769. goto err_supply;
  1770. }
  1771. pdev->dev_num = devnum;
  1772. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1773. &wsa884x_regmap_config);
  1774. if (IS_ERR(wsa884x->regmap)) {
  1775. ret = PTR_ERR(wsa884x->regmap);
  1776. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1777. __func__, ret);
  1778. goto dev_err;
  1779. }
  1780. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1781. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1782. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1783. wsa884x->irq_info.codec_name = "WSA884X";
  1784. wsa884x->irq_info.regmap = wsa884x->regmap;
  1785. wsa884x->irq_info.dev = &pdev->dev;
  1786. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1787. if (ret) {
  1788. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1789. __func__, ret);
  1790. goto dev_err;
  1791. }
  1792. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1793. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1794. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1795. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1796. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1797. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1798. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1799. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1800. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1801. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1802. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1803. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1804. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1805. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1806. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1807. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1808. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1809. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1810. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1811. /* Under Voltage Lock out (UVLO) interrupt handle */
  1812. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1813. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1814. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1815. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1816. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1817. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1818. if (!wsa884x->driver) {
  1819. ret = -ENOMEM;
  1820. goto err_irq;
  1821. }
  1822. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1823. sizeof(struct snd_soc_component_driver));
  1824. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1825. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1826. if (!wsa884x->dai_driver) {
  1827. ret = -ENOMEM;
  1828. goto err_mem;
  1829. }
  1830. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1831. /* Get last digit from HEX format */
  1832. dev_index = (int)((char)(pdev->addr & 0xF));
  1833. dev_index += 1;
  1834. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1835. dev_index += 2;
  1836. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1837. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1838. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1839. wsa884x->dai_driver->name =
  1840. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1841. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1842. wsa884x->dai_driver->playback.stream_name =
  1843. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1844. /* Number of DAI's used is 1 */
  1845. ret = snd_soc_register_component(&pdev->dev,
  1846. wsa884x->driver, wsa884x->dai_driver, 1);
  1847. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1848. if (!component) {
  1849. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1850. ret = -EINVAL;
  1851. goto err_mem;
  1852. }
  1853. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1854. "qcom,bolero-handle", 0);
  1855. if (!wsa884x->parent_np)
  1856. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1857. "qcom,lpass-cdc-handle", 0);
  1858. if (wsa884x->parent_np) {
  1859. wsa884x->parent_dev =
  1860. of_find_device_by_node(wsa884x->parent_np);
  1861. if (wsa884x->parent_dev) {
  1862. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1863. if (plat_data) {
  1864. wsa884x->parent_nblock.notifier_call =
  1865. wsa884x_event_notify;
  1866. if (plat_data->register_notifier)
  1867. plat_data->register_notifier(
  1868. plat_data->handle,
  1869. &wsa884x->parent_nblock,
  1870. true);
  1871. wsa884x->register_notifier =
  1872. plat_data->register_notifier;
  1873. wsa884x->handle = plat_data->handle;
  1874. } else {
  1875. dev_err(&pdev->dev, "%s: plat data not found\n",
  1876. __func__);
  1877. }
  1878. } else {
  1879. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1880. __func__);
  1881. }
  1882. } else {
  1883. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1884. }
  1885. /* Start in speaker mode by default */
  1886. wsa884x->dev_mode = SPEAKER;
  1887. wsa884x->dev_index = dev_index;
  1888. /* wsa_dev_index is macro_agnostic index */
  1889. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1890. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1891. "qcom,wsa-macro-handle", 0);
  1892. if (wsa884x->macro_np) {
  1893. wsa884x->macro_dev =
  1894. of_find_device_by_node(wsa884x->macro_np);
  1895. if (wsa884x->macro_dev) {
  1896. ret = of_property_read_u32_index(
  1897. wsa884x->macro_dev->dev.of_node,
  1898. "qcom,wsa-rloads",
  1899. wsa_dev_index,
  1900. &wsa884x->rload);
  1901. if (ret) {
  1902. dev_err(&pdev->dev,
  1903. "%s: Failed to read wsa rloads\n",
  1904. __func__);
  1905. goto err_mem;
  1906. }
  1907. ret = of_property_read_u32_index(
  1908. wsa884x->macro_dev->dev.of_node,
  1909. "qcom,wsa-bat-cfgs",
  1910. wsa_dev_index,
  1911. &wsa884x->bat_cfg);
  1912. if (ret) {
  1913. dev_err(&pdev->dev,
  1914. "%s: Failed to read wsa bat cfgs\n",
  1915. __func__);
  1916. goto err_mem;
  1917. }
  1918. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1919. "qcom,noise-gate-mode", &noise_gate_mode);
  1920. if (ret) {
  1921. dev_info(&pdev->dev,
  1922. "%s: Failed to read wsa noise gate mode\n",
  1923. __func__);
  1924. wsa884x->noise_gate_mode = IDLE_DETECT;
  1925. } else {
  1926. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1927. wsa884x->noise_gate_mode = noise_gate_mode;
  1928. else
  1929. wsa884x->noise_gate_mode = IDLE_DETECT;
  1930. }
  1931. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1932. "qcom,wsa-system-gains", &sys_gain_size)) {
  1933. dev_err(&pdev->dev,
  1934. "%s: missing wsa-system-gains\n",
  1935. __func__);
  1936. goto err_mem;
  1937. }
  1938. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1939. ret = of_property_read_u32_array(
  1940. wsa884x->macro_dev->dev.of_node,
  1941. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1942. sys_gain_length);
  1943. if (ret) {
  1944. dev_err(&pdev->dev,
  1945. "%s: Failed to read wsa system gains\n",
  1946. __func__);
  1947. goto err_mem;
  1948. }
  1949. wsa884x->system_gain = wsa884x->sys_gains[
  1950. wsa884x->dev_mode + wsa_dev_index * 2];
  1951. } else {
  1952. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1953. __func__);
  1954. goto err_mem;
  1955. }
  1956. } else {
  1957. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1958. goto err_mem;
  1959. }
  1960. dev_dbg(component->dev,
  1961. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1962. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1963. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1964. wsa884x->bat_cfg, wsa884x->system_gain);
  1965. if (ret) {
  1966. dev_err(&pdev->dev,
  1967. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1968. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1969. ret = -EINVAL;
  1970. goto err_mem;
  1971. }
  1972. /* Assume that compander is enabled by default unless it is haptics sku */
  1973. if (wsa884x->variant == WSA8845H)
  1974. wsa884x->comp_enable = false;
  1975. else
  1976. wsa884x->comp_enable = true;
  1977. wsa884x_set_gain_parameters(component);
  1978. wsa884x_set_pbr_parameters(component);
  1979. /* Must write WO registers in a single write */
  1980. wo0_val = (0xC0 | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1981. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1982. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1983. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1984. snd_soc_component_update_bits(component,
  1985. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1986. if (wsa884x->dev_mode == SPEAKER) {
  1987. snd_soc_component_update_bits(component,
  1988. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1989. } else {
  1990. snd_soc_component_update_bits(component,
  1991. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1992. snd_soc_component_update_bits(component,
  1993. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1994. snd_soc_component_update_bits(component,
  1995. REG_FIELD_VALUE(PWM_CLK_CTL,
  1996. PWM_CLK_FREQ_SEL, 0x01));
  1997. }
  1998. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1999. snd_soc_component_update_bits(component,
  2000. REG_FIELD_VALUE(TOP_CTRL1,
  2001. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  2002. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  2003. if (ret) {
  2004. dev_err(&pdev->dev, "Failed to read port params\n");
  2005. goto err;
  2006. }
  2007. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  2008. wsa884x->swr_wsa_port_params);
  2009. mutex_init(&wsa884x->res_lock);
  2010. #ifdef CONFIG_DEBUG_FS
  2011. if (!wsa884x->debugfs_dent) {
  2012. wsa884x->debugfs_dent = debugfs_create_dir(
  2013. dev_name(&pdev->dev), 0);
  2014. if (!IS_ERR(wsa884x->debugfs_dent)) {
  2015. wsa884x->debugfs_peek =
  2016. debugfs_create_file("swrslave_peek",
  2017. S_IFREG | 0444,
  2018. wsa884x->debugfs_dent,
  2019. (void *) pdev,
  2020. &codec_debug_read_ops);
  2021. wsa884x->debugfs_poke =
  2022. debugfs_create_file("swrslave_poke",
  2023. S_IFREG | 0444,
  2024. wsa884x->debugfs_dent,
  2025. (void *) pdev,
  2026. &codec_debug_write_ops);
  2027. wsa884x->debugfs_reg_dump =
  2028. debugfs_create_file(
  2029. "swrslave_reg_dump",
  2030. S_IFREG | 0444,
  2031. wsa884x->debugfs_dent,
  2032. (void *) pdev,
  2033. &codec_debug_dump_ops);
  2034. }
  2035. }
  2036. #endif
  2037. return 0;
  2038. err_mem:
  2039. snd_soc_unregister_component(&pdev->dev);
  2040. if (wsa884x->dai_driver) {
  2041. kfree(wsa884x->dai_driver->name);
  2042. kfree(wsa884x->dai_driver->playback.stream_name);
  2043. devm_kfree(&pdev->dev, wsa884x->dai_driver);
  2044. wsa884x->dai_driver = NULL;
  2045. }
  2046. if (wsa884x->driver) {
  2047. kfree(wsa884x->driver->name);
  2048. devm_kfree(&pdev->dev, wsa884x->driver);
  2049. wsa884x->driver = NULL;
  2050. }
  2051. err_irq:
  2052. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2053. dev_err:
  2054. if (pin_state_current == false)
  2055. wsa884x_gpio_ctrl(wsa884x, false);
  2056. swr_remove_device(pdev);
  2057. err_supply:
  2058. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2059. wsa884x->regulator,
  2060. wsa884x->num_supplies);
  2061. err:
  2062. swr_set_dev_data(pdev, NULL);
  2063. return ret;
  2064. }
  2065. static int wsa884x_swr_remove(struct swr_device *pdev)
  2066. {
  2067. struct wsa884x_priv *wsa884x;
  2068. wsa884x = swr_get_dev_data(pdev);
  2069. if (!wsa884x) {
  2070. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2071. return -EINVAL;
  2072. }
  2073. if (wsa884x->register_notifier)
  2074. wsa884x->register_notifier(wsa884x->handle,
  2075. &wsa884x->parent_nblock, false);
  2076. #ifdef CONFIG_DEBUG_FS
  2077. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2078. wsa884x->debugfs_dent = NULL;
  2079. #endif
  2080. mutex_destroy(&wsa884x->res_lock);
  2081. snd_soc_unregister_component(&pdev->dev);
  2082. if (wsa884x->dai_driver) {
  2083. kfree(wsa884x->dai_driver->name);
  2084. kfree(wsa884x->dai_driver->playback.stream_name);
  2085. kfree(wsa884x->dai_driver);
  2086. }
  2087. if (wsa884x->driver) {
  2088. kfree(wsa884x->driver->name);
  2089. kfree(wsa884x->driver);
  2090. }
  2091. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2092. wsa884x->regulator,
  2093. wsa884x->num_supplies);
  2094. swr_set_dev_data(pdev, NULL);
  2095. return 0;
  2096. }
  2097. #ifdef CONFIG_PM_SLEEP
  2098. static int wsa884x_swr_suspend(struct device *dev)
  2099. {
  2100. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2101. if (!wsa884x) {
  2102. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2103. return -EINVAL;
  2104. }
  2105. dev_dbg(dev, "%s: system suspend\n", __func__);
  2106. if (wsa884x->dapm_bias_off ||
  2107. (wsa884x->component &&
  2108. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2109. SND_SOC_BIAS_OFF))) {
  2110. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2111. wsa884x->regulator,
  2112. wsa884x->num_supplies,
  2113. true);
  2114. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2115. }
  2116. return 0;
  2117. }
  2118. static int wsa884x_swr_resume(struct device *dev)
  2119. {
  2120. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2121. if (!wsa884x) {
  2122. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2123. return -EINVAL;
  2124. }
  2125. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2126. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2127. wsa884x->regulator,
  2128. wsa884x->num_supplies,
  2129. false);
  2130. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2131. }
  2132. dev_dbg(dev, "%s: system resume\n", __func__);
  2133. return 0;
  2134. }
  2135. #endif /* CONFIG_PM_SLEEP */
  2136. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2137. .suspend_late = wsa884x_swr_suspend,
  2138. .resume_early = wsa884x_swr_resume,
  2139. };
  2140. static const struct swr_device_id wsa884x_swr_id[] = {
  2141. {"wsa884x", 0},
  2142. {"wsa884x_2", 0},
  2143. {}
  2144. };
  2145. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2146. {
  2147. .compatible = "qcom,wsa884x",
  2148. },
  2149. {
  2150. .compatible = "qcom,wsa884x_2",
  2151. },
  2152. {}
  2153. };
  2154. static struct swr_driver wsa884x_swr_driver = {
  2155. .driver = {
  2156. .name = "wsa884x",
  2157. .owner = THIS_MODULE,
  2158. .pm = &wsa884x_swr_pm_ops,
  2159. .of_match_table = wsa884x_swr_dt_match,
  2160. },
  2161. .probe = wsa884x_swr_probe,
  2162. .remove = wsa884x_swr_remove,
  2163. .id_table = wsa884x_swr_id,
  2164. };
  2165. static int __init wsa884x_swr_init(void)
  2166. {
  2167. return swr_driver_register(&wsa884x_swr_driver);
  2168. }
  2169. static void __exit wsa884x_swr_exit(void)
  2170. {
  2171. swr_driver_unregister(&wsa884x_swr_driver);
  2172. }
  2173. module_init(wsa884x_swr_init);
  2174. module_exit(wsa884x_swr_exit);
  2175. MODULE_DESCRIPTION("WSA884x codec driver");
  2176. MODULE_LICENSE("GPL v2");