dp_be_tx.c 54 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "hal_tx.h"
  25. #include <hal_be_api.h>
  26. #include <hal_be_tx.h>
  27. #include <dp_htt.h>
  28. #include "dp_internal.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  33. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_mutex_create(lock)
  34. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_mutex_destroy(lock)
  35. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_mutex_acquire(lock)
  36. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_mutex_release(lock)
  37. #else
  38. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_spinlock_create(lock)
  39. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
  40. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_spin_lock_bh(lock)
  41. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_spin_unlock_bh(lock)
  42. #endif
  43. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  44. #ifdef WLAN_MCAST_MLO
  45. /* MLO peer id for reinject*/
  46. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  47. #define MAX_GSN_NUM 0x0FFF
  48. #ifdef QCA_MULTIPASS_SUPPORT
  49. #define INVALID_VLAN_ID 0xFFFF
  50. #define MULTIPASS_WITH_VLAN_ID 0xFFFE
  51. /**
  52. * struct dp_mlo_mpass_buf - Multipass buffer
  53. * @vlan_id: vlan_id of frame
  54. * @nbuf: pointer to skb buf
  55. */
  56. struct dp_mlo_mpass_buf {
  57. uint16_t vlan_id;
  58. qdf_nbuf_t nbuf;
  59. };
  60. #endif
  61. #endif
  62. #endif
  63. #define DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(_var) \
  64. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var)
  65. #define DP_TX_WBM_COMPLETION_V3_VALID_GET(_var) \
  66. HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var)
  67. #define DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(_var) \
  68. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var)
  69. #define DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(_var) \
  70. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var)
  71. #define DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(_var) \
  72. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var)
  73. #define DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(_var) \
  74. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var)
  75. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  76. #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK
  77. /*
  78. * Value to mark ring desc is invalidated by buffer_virt_addr_63_32 field
  79. * of WBM2SW ring Desc.
  80. */
  81. #define DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE 0x12121212
  82. /**
  83. * dp_tx_comp_desc_check_and_invalidate() - sanity check for ring desc and
  84. * invalidate it after each reaping
  85. * @tx_comp_hal_desc: ring desc virtual address
  86. * @r_tx_desc: pointer to current dp TX Desc pointer
  87. * @tx_desc_va: the original 64 bits Desc VA got from ring Desc
  88. * @hw_cc_done: HW cookie conversion done or not
  89. *
  90. * If HW CC is done, check the buffer_virt_addr_63_32 value to know if
  91. * ring Desc is stale or not. if HW CC is not done, then compare PA between
  92. * ring Desc and current TX desc.
  93. *
  94. * Return: None.
  95. */
  96. static inline
  97. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  98. struct dp_tx_desc_s **r_tx_desc,
  99. uint64_t tx_desc_va,
  100. bool hw_cc_done)
  101. {
  102. qdf_dma_addr_t desc_dma_addr;
  103. if (qdf_likely(hw_cc_done)) {
  104. /* Check upper 32 bits */
  105. if (DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE ==
  106. (tx_desc_va >> 32))
  107. *r_tx_desc = NULL;
  108. /* Invalidate the ring desc for 32 ~ 63 bits of VA */
  109. hal_tx_comp_set_desc_va_63_32(
  110. tx_comp_hal_desc,
  111. DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE);
  112. } else {
  113. /* Compare PA between ring desc and current TX desc stored */
  114. desc_dma_addr = hal_tx_comp_get_paddr(tx_comp_hal_desc);
  115. if (desc_dma_addr != (*r_tx_desc)->dma_addr)
  116. *r_tx_desc = NULL;
  117. }
  118. }
  119. #else
  120. static inline
  121. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  122. struct dp_tx_desc_s **r_tx_desc,
  123. uint64_t tx_desc_va,
  124. bool hw_cc_done)
  125. {
  126. }
  127. #endif
  128. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  129. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  130. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  131. void *tx_comp_hal_desc,
  132. struct dp_tx_desc_s **r_tx_desc)
  133. {
  134. uint32_t tx_desc_id;
  135. uint64_t tx_desc_va = 0;
  136. bool hw_cc_done =
  137. hal_tx_comp_get_cookie_convert_done(tx_comp_hal_desc);
  138. if (qdf_likely(hw_cc_done)) {
  139. /* HW cookie conversion done */
  140. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  141. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  142. } else {
  143. /* SW do cookie conversion to VA */
  144. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  145. *r_tx_desc =
  146. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  147. }
  148. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  149. r_tx_desc, tx_desc_va,
  150. hw_cc_done);
  151. if (*r_tx_desc)
  152. (*r_tx_desc)->peer_id =
  153. dp_tx_comp_get_peer_id_be(soc,
  154. tx_comp_hal_desc);
  155. }
  156. #else
  157. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  158. void *tx_comp_hal_desc,
  159. struct dp_tx_desc_s **r_tx_desc)
  160. {
  161. uint64_t tx_desc_va;
  162. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  163. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  164. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  165. r_tx_desc,
  166. tx_desc_va,
  167. true);
  168. if (*r_tx_desc)
  169. (*r_tx_desc)->peer_id =
  170. dp_tx_comp_get_peer_id_be(soc,
  171. tx_comp_hal_desc);
  172. }
  173. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  174. #else
  175. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  176. void *tx_comp_hal_desc,
  177. struct dp_tx_desc_s **r_tx_desc)
  178. {
  179. uint32_t tx_desc_id;
  180. /* SW do cookie conversion to VA */
  181. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  182. *r_tx_desc =
  183. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  184. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  185. r_tx_desc, 0,
  186. false);
  187. if (*r_tx_desc)
  188. (*r_tx_desc)->peer_id =
  189. dp_tx_comp_get_peer_id_be(soc,
  190. tx_comp_hal_desc);
  191. }
  192. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  193. static inline
  194. void dp_tx_process_mec_notify_be(struct dp_soc *soc, uint8_t *status)
  195. {
  196. struct dp_vdev *vdev;
  197. uint8_t vdev_id;
  198. uint32_t *htt_desc = (uint32_t *)status;
  199. dp_assert_always_internal(soc->mec_fw_offload);
  200. /*
  201. * Get vdev id from HTT status word in case of MEC
  202. * notification
  203. */
  204. vdev_id = DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(htt_desc[4]);
  205. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  206. return;
  207. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  208. DP_MOD_ID_HTT_COMP);
  209. if (!vdev)
  210. return;
  211. dp_tx_mec_handler(vdev, status);
  212. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  213. }
  214. void dp_tx_process_htt_completion_be(struct dp_soc *soc,
  215. struct dp_tx_desc_s *tx_desc,
  216. uint8_t *status,
  217. uint8_t ring_id)
  218. {
  219. uint8_t tx_status;
  220. struct dp_pdev *pdev;
  221. struct dp_vdev *vdev = NULL;
  222. struct hal_tx_completion_status ts = {0};
  223. uint32_t *htt_desc = (uint32_t *)status;
  224. struct dp_txrx_peer *txrx_peer;
  225. dp_txrx_ref_handle txrx_ref_handle = NULL;
  226. struct cdp_tid_tx_stats *tid_stats = NULL;
  227. struct htt_soc *htt_handle;
  228. uint8_t vdev_id;
  229. uint16_t peer_id;
  230. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  231. htt_handle = (struct htt_soc *)soc->htt_handle;
  232. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  233. /*
  234. * There can be scenario where WBM consuming descriptor enqueued
  235. * from TQM2WBM first and TQM completion can happen before MEC
  236. * notification comes from FW2WBM. Avoid access any field of tx
  237. * descriptor in case of MEC notify.
  238. */
  239. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  240. return dp_tx_process_mec_notify_be(soc, status);
  241. /*
  242. * If the descriptor is already freed in vdev_detach,
  243. * continue to next descriptor
  244. */
  245. if (qdf_unlikely(!tx_desc->flags)) {
  246. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  247. tx_desc->id);
  248. return;
  249. }
  250. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  251. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  252. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  253. goto release_tx_desc;
  254. }
  255. pdev = tx_desc->pdev;
  256. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  257. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  258. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  259. goto release_tx_desc;
  260. }
  261. qdf_assert(tx_desc->pdev);
  262. vdev_id = tx_desc->vdev_id;
  263. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  264. DP_MOD_ID_HTT_COMP);
  265. if (qdf_unlikely(!vdev)) {
  266. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  267. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  268. goto release_tx_desc;
  269. }
  270. switch (tx_status) {
  271. case HTT_TX_FW2WBM_TX_STATUS_OK:
  272. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  273. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  274. {
  275. uint8_t tid;
  276. if (DP_TX_WBM_COMPLETION_V3_VALID_GET(htt_desc[3])) {
  277. ts.peer_id =
  278. DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(
  279. htt_desc[3]);
  280. ts.tid =
  281. DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(
  282. htt_desc[3]);
  283. } else {
  284. ts.peer_id = HTT_INVALID_PEER;
  285. ts.tid = HTT_INVALID_TID;
  286. }
  287. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  288. ts.ppdu_id =
  289. DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(
  290. htt_desc[2]);
  291. ts.ack_frame_rssi =
  292. DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(
  293. htt_desc[2]);
  294. ts.tsf = htt_desc[4];
  295. ts.first_msdu = 1;
  296. ts.last_msdu = 1;
  297. switch (tx_status) {
  298. case HTT_TX_FW2WBM_TX_STATUS_OK:
  299. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  300. break;
  301. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  302. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  303. break;
  304. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  305. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  306. break;
  307. }
  308. tid = ts.tid;
  309. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  310. tid = CDP_MAX_DATA_TIDS - 1;
  311. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  312. if (qdf_unlikely(pdev->delay_stats_flag) ||
  313. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  314. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  315. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  316. tid_stats->htt_status_cnt[tx_status]++;
  317. peer_id = dp_tx_comp_adjust_peer_id_be(soc, ts.peer_id);
  318. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  319. &txrx_ref_handle,
  320. DP_MOD_ID_HTT_COMP);
  321. if (qdf_likely(txrx_peer))
  322. dp_tx_update_peer_basic_stats(
  323. txrx_peer,
  324. qdf_nbuf_len(tx_desc->nbuf),
  325. tx_status,
  326. pdev->enhanced_stats_en);
  327. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  328. ring_id);
  329. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  330. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  331. if (qdf_likely(txrx_peer))
  332. dp_txrx_peer_unref_delete(txrx_ref_handle,
  333. DP_MOD_ID_HTT_COMP);
  334. break;
  335. }
  336. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  337. {
  338. uint8_t reinject_reason;
  339. reinject_reason =
  340. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(
  341. htt_desc[1]);
  342. dp_tx_reinject_handler(soc, vdev, tx_desc,
  343. status, reinject_reason);
  344. break;
  345. }
  346. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  347. {
  348. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  349. break;
  350. }
  351. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  352. {
  353. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  354. goto release_tx_desc;
  355. }
  356. default:
  357. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  358. tx_status);
  359. goto release_tx_desc;
  360. }
  361. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  362. return;
  363. release_tx_desc:
  364. dp_tx_comp_free_buf(soc, tx_desc, false);
  365. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  366. if (vdev)
  367. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  368. }
  369. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  370. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  371. /**
  372. * dp_tx_get_rbm_id_be() - Get the RBM ID for data transmission completion.
  373. * @soc: DP soc structure pointer
  374. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  375. *
  376. * Return: RBM ID corresponding to TCL ring_id
  377. */
  378. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  379. uint8_t ring_id)
  380. {
  381. return 0;
  382. }
  383. #else
  384. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  385. uint8_t ring_id)
  386. {
  387. return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
  388. HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
  389. }
  390. #endif /*DP_TX_IMPLICIT_RBM_MAPPING*/
  391. #else
  392. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  393. uint8_t tcl_index)
  394. {
  395. uint8_t rbm;
  396. rbm = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_index);
  397. dp_verbose_debug("tcl_id %u rbm %u", tcl_index, rbm);
  398. return rbm;
  399. }
  400. #endif
  401. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  402. /**
  403. * dp_tx_set_min_rates_for_critical_frames()- sets min-rates for critical pkts
  404. * @soc: DP soc structure pointer
  405. * @hal_tx_desc: HAL descriptor where fields are set
  406. * @nbuf: skb to be considered for min rates
  407. *
  408. * The function relies on upper layers to set QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL
  409. * and uses it to determine if the frame is critical. For a critical frame,
  410. * flow override bits are set to classify the frame into HW's high priority
  411. * queue. The HW will pick pre-configured min rates for such packets.
  412. *
  413. * Return: None
  414. */
  415. static void
  416. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  417. uint32_t *hal_tx_desc,
  418. qdf_nbuf_t nbuf)
  419. {
  420. /*
  421. * Critical frames should be queued to the high priority queue for the TID on
  422. * on which they are sent out (for the concerned peer).
  423. * FW is using HTT_MSDU_Q_IDX 2 for HOL (high priority) queue.
  424. * htt_msdu_idx = (2 * who_classify_info_sel) + flow_override
  425. * Hence, using who_classify_info_sel = 1, flow_override = 0 to select
  426. * HOL queue.
  427. */
  428. if (QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL(nbuf)) {
  429. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  430. hal_tx_desc_set_flow_override(hal_tx_desc, 0);
  431. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  432. hal_tx_desc_set_tx_notify_frame(hal_tx_desc,
  433. TX_SEMI_HARD_NOTIFY_E);
  434. }
  435. }
  436. #else
  437. static inline void
  438. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  439. uint32_t *hal_tx_desc_cached,
  440. qdf_nbuf_t nbuf)
  441. {
  442. }
  443. #endif
  444. #ifdef DP_TX_PACKET_INSPECT_FOR_ILP
  445. /**
  446. * dp_tx_set_particular_tx_queue() - set particular TX TQM flow queue 3 for
  447. * TX packets, currently TCP ACK only
  448. * @soc: DP soc structure pointer
  449. * @hal_tx_desc: HAL descriptor where fields are set
  450. * @nbuf: skb to be considered for particular TX queue
  451. *
  452. * Return: None
  453. */
  454. static inline
  455. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  456. uint32_t *hal_tx_desc,
  457. qdf_nbuf_t nbuf)
  458. {
  459. if (!soc->tx_ilp_enable)
  460. return;
  461. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  462. QDF_NBUF_CB_PACKET_TYPE_TCP_ACK)) {
  463. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  464. hal_tx_desc_set_flow_override(hal_tx_desc, 1);
  465. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  466. }
  467. }
  468. #else
  469. static inline
  470. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  471. uint32_t *hal_tx_desc,
  472. qdf_nbuf_t nbuf)
  473. {
  474. }
  475. #endif
  476. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  477. defined(WLAN_MCAST_MLO)
  478. #ifdef QCA_MULTIPASS_SUPPORT
  479. /**
  480. * dp_tx_mlo_mcast_multipass_lookup() - lookup vlan_id in mpass peer list
  481. * @be_vdev: Handle to DP be_vdev structure
  482. * @ptnr_vdev: DP ptnr_vdev handle
  483. * @arg: pointer to dp_mlo_mpass_ buf
  484. *
  485. * Return: None
  486. */
  487. static void
  488. dp_tx_mlo_mcast_multipass_lookup(struct dp_vdev_be *be_vdev,
  489. struct dp_vdev *ptnr_vdev,
  490. void *arg)
  491. {
  492. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  493. struct dp_txrx_peer *txrx_peer = NULL;
  494. struct vlan_ethhdr *veh = NULL;
  495. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(ptr->nbuf);
  496. uint16_t vlan_id = 0;
  497. bool not_vlan = ((ptnr_vdev->tx_encap_type == htt_cmn_pkt_type_raw) ||
  498. (htons(eh->ether_type) != ETH_P_8021Q));
  499. if (qdf_unlikely(not_vlan))
  500. return;
  501. veh = (struct vlan_ethhdr *)eh;
  502. vlan_id = (ntohs(veh->h_vlan_TCI) & VLAN_VID_MASK);
  503. qdf_spin_lock_bh(&ptnr_vdev->mpass_peer_mutex);
  504. TAILQ_FOREACH(txrx_peer, &ptnr_vdev->mpass_peer_list,
  505. mpass_peer_list_elem) {
  506. if (vlan_id == txrx_peer->vlan_id) {
  507. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  508. ptr->vlan_id = vlan_id;
  509. return;
  510. }
  511. }
  512. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  513. }
  514. /**
  515. * dp_tx_mlo_mcast_multipass_send() - send multipass MLO Mcast packets
  516. * @be_vdev: Handle to DP be_vdev structure
  517. * @ptnr_vdev: DP ptnr_vdev handle
  518. * @arg: pointer to dp_mlo_mpass_ buf
  519. *
  520. * Return: None
  521. */
  522. static void
  523. dp_tx_mlo_mcast_multipass_send(struct dp_vdev_be *be_vdev,
  524. struct dp_vdev *ptnr_vdev,
  525. void *arg)
  526. {
  527. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  528. struct dp_tx_msdu_info_s msdu_info;
  529. struct dp_vdev_be *be_ptnr_vdev = NULL;
  530. qdf_nbuf_t nbuf_clone;
  531. uint16_t group_key = 0;
  532. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  533. if (be_vdev != be_ptnr_vdev) {
  534. nbuf_clone = qdf_nbuf_clone(ptr->nbuf);
  535. if (qdf_unlikely(!nbuf_clone)) {
  536. dp_tx_debug("nbuf clone failed");
  537. return;
  538. }
  539. } else {
  540. nbuf_clone = ptr->nbuf;
  541. }
  542. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  543. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  544. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  545. if (ptr->vlan_id == MULTIPASS_WITH_VLAN_ID) {
  546. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  547. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(
  548. msdu_info.meta_data[0], 1);
  549. } else {
  550. /* return when vlan map is not initialized */
  551. if (!ptnr_vdev->iv_vlan_map)
  552. return;
  553. group_key = ptnr_vdev->iv_vlan_map[ptr->vlan_id];
  554. /*
  555. * If group key is not installed, drop the frame.
  556. */
  557. if (!group_key)
  558. return;
  559. dp_tx_remove_vlan_tag(ptnr_vdev, nbuf_clone);
  560. dp_tx_add_groupkey_metadata(ptnr_vdev, &msdu_info, group_key);
  561. msdu_info.exception_fw = 1;
  562. }
  563. nbuf_clone = dp_tx_send_msdu_single(
  564. ptnr_vdev,
  565. nbuf_clone,
  566. &msdu_info,
  567. DP_MLO_MCAST_REINJECT_PEER_ID,
  568. NULL);
  569. if (qdf_unlikely(nbuf_clone)) {
  570. dp_info("pkt send failed");
  571. qdf_nbuf_free(nbuf_clone);
  572. return;
  573. }
  574. }
  575. /**
  576. * dp_tx_mlo_mcast_multipass_handler - If frame needs multipass processing
  577. * @soc: DP soc handle
  578. * @vdev: DP vdev handle
  579. * @nbuf: nbuf to be enqueued
  580. *
  581. * Return: true if handling is done else false
  582. */
  583. static bool
  584. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc,
  585. struct dp_vdev *vdev,
  586. qdf_nbuf_t nbuf)
  587. {
  588. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  589. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  590. qdf_nbuf_t nbuf_copy = NULL;
  591. struct dp_mlo_mpass_buf mpass_buf;
  592. memset(&mpass_buf, 0, sizeof(struct dp_mlo_mpass_buf));
  593. mpass_buf.vlan_id = INVALID_VLAN_ID;
  594. mpass_buf.nbuf = nbuf;
  595. dp_tx_mlo_mcast_multipass_lookup(be_vdev, vdev, &mpass_buf);
  596. if (mpass_buf.vlan_id == INVALID_VLAN_ID) {
  597. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  598. dp_tx_mlo_mcast_multipass_lookup,
  599. &mpass_buf, DP_MOD_ID_TX,
  600. DP_ALL_VDEV_ITER);
  601. /*
  602. * Do not drop the frame when vlan_id doesn't match.
  603. * Send the frame as it is.
  604. */
  605. if (mpass_buf.vlan_id == INVALID_VLAN_ID)
  606. return false;
  607. }
  608. /* AP can have classic clients, special clients &
  609. * classic repeaters.
  610. * 1. Classic clients & special client:
  611. * Remove vlan header, find corresponding group key
  612. * index, fill in metaheader and enqueue multicast
  613. * frame to TCL.
  614. * 2. Classic repeater:
  615. * Pass through to classic repeater with vlan tag
  616. * intact without any group key index. Hardware
  617. * will know which key to use to send frame to
  618. * repeater.
  619. */
  620. nbuf_copy = qdf_nbuf_copy(nbuf);
  621. /*
  622. * Send multicast frame to special peers even
  623. * if pass through to classic repeater fails.
  624. */
  625. if (nbuf_copy) {
  626. struct dp_mlo_mpass_buf mpass_buf_copy = {0};
  627. mpass_buf_copy.vlan_id = MULTIPASS_WITH_VLAN_ID;
  628. mpass_buf_copy.nbuf = nbuf_copy;
  629. /* send frame on partner vdevs */
  630. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  631. dp_tx_mlo_mcast_multipass_send,
  632. &mpass_buf_copy, DP_MOD_ID_TX,
  633. DP_LINK_VDEV_ITER);
  634. /* send frame on mcast primary vdev */
  635. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf_copy);
  636. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  637. be_vdev->mlo_dev_ctxt->seq_num = 0;
  638. else
  639. be_vdev->mlo_dev_ctxt->seq_num++;
  640. }
  641. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  642. dp_tx_mlo_mcast_multipass_send,
  643. &mpass_buf, DP_MOD_ID_TX, DP_LINK_VDEV_ITER);
  644. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf);
  645. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  646. be_vdev->mlo_dev_ctxt->seq_num = 0;
  647. else
  648. be_vdev->mlo_dev_ctxt->seq_num++;
  649. return true;
  650. }
  651. #else
  652. static bool
  653. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  654. qdf_nbuf_t nbuf)
  655. {
  656. return false;
  657. }
  658. #endif
  659. void
  660. dp_tx_mlo_mcast_pkt_send(struct dp_vdev_be *be_vdev,
  661. struct dp_vdev *ptnr_vdev,
  662. void *arg)
  663. {
  664. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  665. qdf_nbuf_t nbuf_clone;
  666. struct dp_vdev_be *be_ptnr_vdev = NULL;
  667. struct dp_tx_msdu_info_s msdu_info;
  668. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  669. if (be_vdev != be_ptnr_vdev) {
  670. nbuf_clone = qdf_nbuf_clone(nbuf);
  671. if (qdf_unlikely(!nbuf_clone)) {
  672. dp_tx_debug("nbuf clone failed");
  673. return;
  674. }
  675. } else {
  676. nbuf_clone = nbuf;
  677. }
  678. /* NAWDS clients will accepts on 4 addr format MCAST packets
  679. * This will ensure to send packets in 4 addr format to NAWDS clients.
  680. */
  681. if (qdf_unlikely(ptnr_vdev->nawds_enabled)) {
  682. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  683. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  684. dp_tx_nawds_handler(ptnr_vdev->pdev->soc, ptnr_vdev,
  685. &msdu_info, nbuf_clone, DP_INVALID_PEER);
  686. }
  687. if (qdf_unlikely(dp_tx_proxy_arp(ptnr_vdev, nbuf_clone) !=
  688. QDF_STATUS_SUCCESS)) {
  689. qdf_nbuf_free(nbuf_clone);
  690. return;
  691. }
  692. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  693. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  694. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  695. DP_STATS_INC(ptnr_vdev, tx_i.mlo_mcast.send_pkt_count, 1);
  696. nbuf_clone = dp_tx_send_msdu_single(
  697. ptnr_vdev,
  698. nbuf_clone,
  699. &msdu_info,
  700. DP_MLO_MCAST_REINJECT_PEER_ID,
  701. NULL);
  702. if (qdf_unlikely(nbuf_clone)) {
  703. DP_STATS_INC(ptnr_vdev, tx_i.mlo_mcast.fail_pkt_count, 1);
  704. dp_info("pkt send failed");
  705. qdf_nbuf_free(nbuf_clone);
  706. return;
  707. }
  708. }
  709. static inline void
  710. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  711. struct dp_vdev *vdev,
  712. struct dp_tx_msdu_info_s *msdu_info)
  713. {
  714. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, msdu_info->vdev_id);
  715. }
  716. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  717. struct dp_vdev *vdev,
  718. qdf_nbuf_t nbuf)
  719. {
  720. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  721. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  722. if (qdf_unlikely(vdev->multipass_en) &&
  723. dp_tx_mlo_mcast_multipass_handler(soc, vdev, nbuf))
  724. return;
  725. /* send frame on partner vdevs */
  726. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  727. dp_tx_mlo_mcast_pkt_send,
  728. nbuf, DP_MOD_ID_REINJECT, DP_LINK_VDEV_ITER);
  729. /* send frame on mcast primary vdev */
  730. dp_tx_mlo_mcast_pkt_send(be_vdev, vdev, nbuf);
  731. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  732. be_vdev->mlo_dev_ctxt->seq_num = 0;
  733. else
  734. be_vdev->mlo_dev_ctxt->seq_num++;
  735. }
  736. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  737. struct dp_vdev *vdev)
  738. {
  739. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  740. if (be_vdev->mcast_primary)
  741. return true;
  742. return false;
  743. }
  744. #if defined(CONFIG_MLO_SINGLE_DEV)
  745. static void
  746. dp_tx_mlo_mcast_enhance_be(struct dp_vdev_be *be_vdev,
  747. struct dp_vdev *ptnr_vdev,
  748. void *arg)
  749. {
  750. struct dp_vdev *vdev = (struct dp_vdev *)be_vdev;
  751. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  752. if (vdev == ptnr_vdev)
  753. return;
  754. /*
  755. * Hold the reference to avoid free of nbuf in
  756. * dp_tx_mcast_enhance() in case of successful
  757. * conversion
  758. */
  759. qdf_nbuf_ref(nbuf);
  760. if (qdf_unlikely(!dp_tx_mcast_enhance(ptnr_vdev, nbuf)))
  761. return;
  762. qdf_nbuf_free(nbuf);
  763. }
  764. qdf_nbuf_t
  765. dp_tx_mlo_mcast_send_be(struct dp_soc *soc, struct dp_vdev *vdev,
  766. qdf_nbuf_t nbuf,
  767. struct cdp_tx_exception_metadata *tx_exc_metadata)
  768. {
  769. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  770. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  771. if (!tx_exc_metadata->is_mlo_mcast)
  772. return nbuf;
  773. if (!be_vdev->mcast_primary) {
  774. qdf_nbuf_free(nbuf);
  775. return NULL;
  776. }
  777. /*
  778. * In the single netdev model avoid reinjection path as mcast
  779. * packet is identified in upper layers while peer search to find
  780. * primary TQM based on dest mac addr
  781. *
  782. * New bonding interface added into the bridge so MCSD will update
  783. * snooping table and wifi driver populates the entries in appropriate
  784. * child net devices.
  785. */
  786. if (vdev->mcast_enhancement_en) {
  787. /*
  788. * As dp_tx_mcast_enhance() can consume the nbuf incase of
  789. * successful conversion hold the reference of nbuf.
  790. *
  791. * Hold the reference to tx on partner links
  792. */
  793. qdf_nbuf_ref(nbuf);
  794. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf))) {
  795. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  796. dp_tx_mlo_mcast_enhance_be,
  797. nbuf, DP_MOD_ID_TX,
  798. DP_ALL_VDEV_ITER);
  799. qdf_nbuf_free(nbuf);
  800. return NULL;
  801. }
  802. /* release reference taken above */
  803. qdf_nbuf_free(nbuf);
  804. }
  805. dp_tx_mlo_mcast_handler_be(soc, vdev, nbuf);
  806. return NULL;
  807. }
  808. #endif
  809. #else
  810. static inline void
  811. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  812. struct dp_vdev *vdev,
  813. struct dp_tx_msdu_info_s *msdu_info)
  814. {
  815. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, vdev->vdev_id);
  816. }
  817. #endif
  818. #if defined(WLAN_FEATURE_11BE_MLO) && !defined(WLAN_MLO_MULTI_CHIP) && \
  819. !defined(WLAN_MCAST_MLO)
  820. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  821. struct dp_vdev *vdev,
  822. qdf_nbuf_t nbuf)
  823. {
  824. }
  825. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  826. struct dp_vdev *vdev)
  827. {
  828. return false;
  829. }
  830. #endif
  831. #ifdef CONFIG_SAWF
  832. /**
  833. * dp_sawf_config_be - Configure sawf specific fields in tcl
  834. *
  835. * @soc: DP soc handle
  836. * @hal_tx_desc_cached: tx descriptor
  837. * @fw_metadata: firmware metadata
  838. * @nbuf: skb buffer
  839. * @msdu_info: msdu info
  840. *
  841. * Return: void
  842. */
  843. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  844. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  845. struct dp_tx_msdu_info_s *msdu_info)
  846. {
  847. uint8_t q_id = 0;
  848. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  849. return;
  850. q_id = dp_sawf_queue_id_get(nbuf);
  851. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  852. return;
  853. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  854. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  855. (q_id & (CDP_DATA_TID_MAX - 1)));
  856. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  857. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  858. return;
  859. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  860. hal_tx_desc_set_flow_override_enable(hal_tx_desc_cached,
  861. DP_TX_FLOW_OVERRIDE_ENABLE);
  862. hal_tx_desc_set_flow_override(hal_tx_desc_cached,
  863. DP_TX_FLOW_OVERRIDE_GET(q_id));
  864. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc_cached,
  865. DP_TX_WHO_CLFY_INF_SEL_GET(q_id));
  866. }
  867. #else
  868. static inline
  869. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  870. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  871. struct dp_tx_msdu_info_s *msdu_info)
  872. {
  873. }
  874. static inline
  875. QDF_STATUS dp_sawf_tx_enqueue_peer_stats(struct dp_soc *soc,
  876. struct dp_tx_desc_s *tx_desc)
  877. {
  878. return QDF_STATUS_SUCCESS;
  879. }
  880. static inline
  881. QDF_STATUS dp_sawf_tx_enqueue_fail_peer_stats(struct dp_soc *soc,
  882. struct dp_tx_desc_s *tx_desc)
  883. {
  884. return QDF_STATUS_SUCCESS;
  885. }
  886. #endif
  887. #ifdef WLAN_SUPPORT_PPEDS
  888. /**
  889. * dp_ppeds_stats() - Accounting fw2wbm_tx_drop drops in Tx path
  890. * @soc: Handle to DP Soc structure
  891. * @peer_id: Peer ID in the descriptor
  892. *
  893. * Return: NONE
  894. */
  895. static inline
  896. void dp_ppeds_stats(struct dp_soc *soc, uint16_t peer_id)
  897. {
  898. struct dp_vdev *vdev = NULL;
  899. struct dp_txrx_peer *txrx_peer = NULL;
  900. dp_txrx_ref_handle txrx_ref_handle = NULL;
  901. DP_STATS_INC(soc, tx.fw2wbm_tx_drop, 1);
  902. txrx_peer = dp_txrx_peer_get_ref_by_id(soc,
  903. peer_id,
  904. &txrx_ref_handle,
  905. DP_MOD_ID_TX_COMP);
  906. if (txrx_peer) {
  907. vdev = txrx_peer->vdev;
  908. DP_STATS_INC(vdev, tx_i.dropped.fw2wbm_tx_drop, 1);
  909. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  910. }
  911. }
  912. int dp_ppeds_tx_comp_handler(struct dp_soc_be *be_soc, uint32_t quota)
  913. {
  914. uint32_t num_avail_for_reap = 0;
  915. void *tx_comp_hal_desc;
  916. uint8_t buf_src, status = 0;
  917. uint32_t count = 0;
  918. struct dp_tx_desc_s *tx_desc = NULL;
  919. struct dp_tx_desc_s *head_desc = NULL;
  920. struct dp_tx_desc_s *tail_desc = NULL;
  921. struct dp_soc *soc = &be_soc->soc;
  922. void *last_prefetch_hw_desc = NULL;
  923. struct dp_tx_desc_s *last_prefetch_sw_desc = NULL;
  924. qdf_nbuf_t nbuf;
  925. hal_soc_handle_t hal_soc = soc->hal_soc;
  926. hal_ring_handle_t hal_ring_hdl =
  927. be_soc->ppeds_wbm_release_ring.hal_srng;
  928. struct dp_txrx_peer *txrx_peer = NULL;
  929. uint16_t peer_id = CDP_INVALID_PEER;
  930. dp_txrx_ref_handle txrx_ref_handle = NULL;
  931. struct dp_vdev *vdev = NULL;
  932. struct dp_pdev *pdev = NULL;
  933. struct dp_srng *srng;
  934. if (qdf_unlikely(dp_srng_access_start(NULL, soc, hal_ring_hdl))) {
  935. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  936. return 0;
  937. }
  938. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  939. if (num_avail_for_reap >= quota)
  940. num_avail_for_reap = quota;
  941. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  942. last_prefetch_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  943. num_avail_for_reap);
  944. srng = &be_soc->ppeds_wbm_release_ring;
  945. if (srng) {
  946. hal_update_ring_util(soc->hal_soc, srng->hal_srng,
  947. WBM2SW_RELEASE,
  948. &be_soc->ppeds_wbm_release_ring.stats);
  949. }
  950. while (qdf_likely(num_avail_for_reap--)) {
  951. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  952. if (qdf_unlikely(!tx_comp_hal_desc))
  953. break;
  954. buf_src = hal_tx_comp_get_buffer_source(hal_soc,
  955. tx_comp_hal_desc);
  956. if (qdf_unlikely(buf_src != HAL_TX_COMP_RELEASE_SOURCE_TQM &&
  957. buf_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  958. dp_err("Tx comp release_src != TQM | FW but from %d",
  959. buf_src);
  960. dp_assert_always_internal_ds_stat(0, be_soc,
  961. tx.tx_comp_buf_src);
  962. continue;
  963. }
  964. dp_tx_comp_get_params_from_hal_desc_be(soc, tx_comp_hal_desc,
  965. &tx_desc);
  966. if (!tx_desc) {
  967. dp_err("unable to retrieve tx_desc!");
  968. dp_assert_always_internal_ds_stat(0, be_soc,
  969. tx.tx_comp_desc_null);
  970. continue;
  971. }
  972. if (qdf_unlikely(!(tx_desc->flags &
  973. DP_TX_DESC_FLAG_ALLOCATED) ||
  974. !(tx_desc->flags & DP_TX_DESC_FLAG_PPEDS))) {
  975. dp_assert_always_internal_ds_stat(0, be_soc,
  976. tx.tx_comp_invalid_flag);
  977. continue;
  978. }
  979. tx_desc->buffer_src = buf_src;
  980. if (qdf_unlikely(buf_src == HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  981. status = hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  982. if (status != HTT_TX_FW2WBM_TX_STATUS_OK)
  983. dp_ppeds_stats(soc, tx_desc->peer_id);
  984. nbuf = dp_ppeds_tx_desc_free(soc, tx_desc);
  985. qdf_nbuf_free(nbuf);
  986. } else {
  987. tx_desc->tx_status =
  988. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  989. /*
  990. * Add desc sync to account for extended statistics
  991. * during Tx completion.
  992. */
  993. if (peer_id != tx_desc->peer_id) {
  994. if (txrx_peer) {
  995. dp_txrx_peer_unref_delete(txrx_ref_handle,
  996. DP_MOD_ID_TX_COMP);
  997. txrx_peer = NULL;
  998. vdev = NULL;
  999. pdev = NULL;
  1000. }
  1001. peer_id = tx_desc->peer_id;
  1002. txrx_peer =
  1003. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  1004. &txrx_ref_handle,
  1005. DP_MOD_ID_TX_COMP);
  1006. if (txrx_peer) {
  1007. vdev = txrx_peer->vdev;
  1008. if (!vdev)
  1009. goto next_desc;
  1010. pdev = vdev->pdev;
  1011. if (!pdev)
  1012. goto next_desc;
  1013. dp_tx_desc_update_fast_comp_flag(soc,
  1014. tx_desc,
  1015. !pdev->enhanced_stats_en);
  1016. if (pdev->enhanced_stats_en) {
  1017. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1018. &tx_desc->comp, 1);
  1019. }
  1020. }
  1021. } else if (txrx_peer && vdev && pdev) {
  1022. dp_tx_desc_update_fast_comp_flag(soc,
  1023. tx_desc,
  1024. !pdev->enhanced_stats_en);
  1025. if (pdev->enhanced_stats_en) {
  1026. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1027. &tx_desc->comp, 1);
  1028. }
  1029. }
  1030. next_desc:
  1031. if (!head_desc) {
  1032. head_desc = tx_desc;
  1033. tail_desc = tx_desc;
  1034. }
  1035. tail_desc->next = tx_desc;
  1036. tx_desc->next = NULL;
  1037. tail_desc = tx_desc;
  1038. count++;
  1039. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  1040. num_avail_for_reap,
  1041. hal_ring_hdl,
  1042. &last_prefetch_hw_desc,
  1043. &last_prefetch_sw_desc);
  1044. }
  1045. }
  1046. dp_srng_access_end(NULL, soc, hal_ring_hdl);
  1047. if (txrx_peer)
  1048. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1049. DP_MOD_ID_TX_COMP);
  1050. if (head_desc)
  1051. dp_tx_comp_process_desc_list(soc, head_desc,
  1052. CDP_MAX_TX_COMP_PPE_RING);
  1053. return count;
  1054. }
  1055. #endif
  1056. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  1057. static inline void
  1058. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1059. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1060. uint16_t *ast_idx, uint16_t *ast_hash)
  1061. {
  1062. struct dp_peer *peer = NULL;
  1063. if (tx_exc_metadata->is_wds_extended) {
  1064. peer = dp_peer_get_ref_by_id(soc, tx_exc_metadata->peer_id,
  1065. DP_MOD_ID_TX);
  1066. if (peer) {
  1067. *ast_idx = peer->ast_idx;
  1068. *ast_hash = peer->ast_hash;
  1069. hal_tx_desc_set_index_lookup_override
  1070. (soc->hal_soc,
  1071. hal_tx_desc_cached,
  1072. 0x1);
  1073. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  1074. }
  1075. } else {
  1076. return;
  1077. }
  1078. }
  1079. #else
  1080. static inline void
  1081. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1082. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1083. uint16_t *ast_idx, uint16_t *ast_hash)
  1084. {
  1085. }
  1086. #endif
  1087. QDF_STATUS
  1088. dp_tx_hw_enqueue_be(struct dp_soc *soc, struct dp_vdev *vdev,
  1089. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1090. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1091. struct dp_tx_msdu_info_s *msdu_info)
  1092. {
  1093. void *hal_tx_desc;
  1094. uint32_t *hal_tx_desc_cached;
  1095. int coalesce = 0;
  1096. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1097. uint8_t ring_id = tx_q->ring_id;
  1098. uint8_t tid;
  1099. struct dp_vdev_be *be_vdev;
  1100. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1101. uint8_t bm_id = dp_tx_get_rbm_id_be(soc, ring_id);
  1102. hal_ring_handle_t hal_ring_hdl = NULL;
  1103. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1104. uint8_t num_desc_bytes = HAL_TX_DESC_LEN_BYTES;
  1105. uint16_t ast_idx = vdev->bss_ast_idx;
  1106. uint16_t ast_hash = vdev->bss_ast_hash;
  1107. be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1108. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1109. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1110. return QDF_STATUS_E_RESOURCES;
  1111. }
  1112. if (qdf_unlikely(tx_exc_metadata)) {
  1113. qdf_assert_always((tx_exc_metadata->tx_encap_type ==
  1114. CDP_INVALID_TX_ENCAP_TYPE) ||
  1115. (tx_exc_metadata->tx_encap_type ==
  1116. vdev->tx_encap_type));
  1117. if (tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)
  1118. qdf_assert_always((tx_exc_metadata->sec_type ==
  1119. CDP_INVALID_SEC_TYPE) ||
  1120. tx_exc_metadata->sec_type ==
  1121. vdev->sec_type);
  1122. dp_get_peer_from_tx_exc_meta(soc, (void *)cached_desc,
  1123. tx_exc_metadata,
  1124. &ast_idx, &ast_hash);
  1125. }
  1126. hal_tx_desc_cached = (void *)cached_desc;
  1127. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  1128. dp_sawf_config_be(soc, hal_tx_desc_cached,
  1129. &fw_metadata, tx_desc->nbuf, msdu_info);
  1130. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  1131. }
  1132. hal_tx_desc_set_buf_addr_be(soc->hal_soc, hal_tx_desc_cached,
  1133. tx_desc->dma_addr, bm_id, tx_desc->id,
  1134. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1135. hal_tx_desc_set_lmac_id_be(soc->hal_soc, hal_tx_desc_cached,
  1136. vdev->lmac_id);
  1137. hal_tx_desc_set_search_index_be(soc->hal_soc, hal_tx_desc_cached,
  1138. ast_idx);
  1139. /*
  1140. * Bank_ID is used as DSCP_TABLE number in beryllium
  1141. * So there is no explicit field used for DSCP_TID_TABLE_NUM.
  1142. */
  1143. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1144. (ast_hash & 0xF));
  1145. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1146. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1147. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1148. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1149. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1150. /* verify checksum offload configuration*/
  1151. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  1152. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  1153. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  1154. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1155. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1156. }
  1157. hal_tx_desc_set_bank_id(hal_tx_desc_cached, vdev->bank_id);
  1158. dp_tx_vdev_id_set_hal_tx_desc(hal_tx_desc_cached, vdev, msdu_info);
  1159. tid = msdu_info->tid;
  1160. if (tid != HTT_TX_EXT_TID_INVALID)
  1161. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1162. dp_tx_set_min_rates_for_critical_frames(soc, hal_tx_desc_cached,
  1163. tx_desc->nbuf);
  1164. dp_tx_set_particular_tx_queue(soc, hal_tx_desc_cached,
  1165. tx_desc->nbuf);
  1166. dp_tx_desc_set_ktimestamp(vdev, tx_desc);
  1167. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1168. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1169. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1170. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1171. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1172. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1173. return status;
  1174. }
  1175. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1176. if (qdf_unlikely(!hal_tx_desc)) {
  1177. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1178. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1179. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1180. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1181. goto ring_access_fail;
  1182. }
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1184. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1185. /* Sync cached descriptor with HW */
  1186. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc, num_desc_bytes);
  1187. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  1188. msdu_info, ring_id);
  1189. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, dp_tx_get_pkt_len(tx_desc));
  1190. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  1191. dp_tx_update_stats(soc, tx_desc, ring_id);
  1192. status = QDF_STATUS_SUCCESS;
  1193. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  1194. hal_ring_hdl, soc, ring_id);
  1195. ring_access_fail:
  1196. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1197. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  1198. qdf_get_log_timestamp(), tx_desc->nbuf);
  1199. return status;
  1200. }
  1201. #ifdef IPA_OFFLOAD
  1202. static void
  1203. dp_tx_get_ipa_bank_config(struct dp_soc_be *be_soc,
  1204. union hal_tx_bank_config *bank_config)
  1205. {
  1206. bank_config->epd = 0;
  1207. bank_config->encap_type = wlan_cfg_pkt_type(be_soc->soc.wlan_cfg_ctx);
  1208. bank_config->encrypt_type = 0;
  1209. bank_config->src_buffer_swap = 0;
  1210. bank_config->link_meta_swap = 0;
  1211. bank_config->index_lookup_enable = 0;
  1212. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1213. bank_config->addrx_en = 1;
  1214. bank_config->addry_en = 1;
  1215. bank_config->mesh_enable = 0;
  1216. bank_config->dscp_tid_map_id = 0;
  1217. bank_config->vdev_id_check_en = 0;
  1218. bank_config->pmac_id = 0;
  1219. }
  1220. static void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1221. {
  1222. union hal_tx_bank_config ipa_config = {0};
  1223. int bid;
  1224. if (!wlan_cfg_is_ipa_enabled(be_soc->soc.wlan_cfg_ctx)) {
  1225. be_soc->ipa_bank_id = DP_BE_INVALID_BANK_ID;
  1226. return;
  1227. }
  1228. dp_tx_get_ipa_bank_config(be_soc, &ipa_config);
  1229. /* Let IPA use last HOST owned bank */
  1230. bid = be_soc->num_bank_profiles - 1;
  1231. be_soc->bank_profiles[bid].is_configured = true;
  1232. be_soc->bank_profiles[bid].bank_config.val = ipa_config.val;
  1233. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1234. &be_soc->bank_profiles[bid].bank_config,
  1235. bid);
  1236. qdf_atomic_inc(&be_soc->bank_profiles[bid].ref_count);
  1237. dp_info("IPA bank at slot %d config:0x%x", bid,
  1238. be_soc->bank_profiles[bid].bank_config.val);
  1239. be_soc->ipa_bank_id = bid;
  1240. }
  1241. #else /* !IPA_OFFLOAD */
  1242. static inline void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1243. {
  1244. }
  1245. #endif /* IPA_OFFLOAD */
  1246. QDF_STATUS dp_tx_init_bank_profiles(struct dp_soc_be *be_soc)
  1247. {
  1248. int i, num_tcl_banks;
  1249. num_tcl_banks = hal_tx_get_num_tcl_banks(be_soc->soc.hal_soc);
  1250. dp_assert_always_internal(num_tcl_banks);
  1251. be_soc->num_bank_profiles = num_tcl_banks;
  1252. be_soc->bank_profiles = qdf_mem_malloc(num_tcl_banks *
  1253. sizeof(*be_soc->bank_profiles));
  1254. if (!be_soc->bank_profiles) {
  1255. dp_err("unable to allocate memory for DP TX Profiles!");
  1256. return QDF_STATUS_E_NOMEM;
  1257. }
  1258. DP_TX_BANK_LOCK_CREATE(&be_soc->tx_bank_lock);
  1259. for (i = 0; i < num_tcl_banks; i++) {
  1260. be_soc->bank_profiles[i].is_configured = false;
  1261. qdf_atomic_init(&be_soc->bank_profiles[i].ref_count);
  1262. }
  1263. dp_info("initialized %u bank profiles", be_soc->num_bank_profiles);
  1264. dp_tx_init_ipa_bank_profile(be_soc);
  1265. return QDF_STATUS_SUCCESS;
  1266. }
  1267. void dp_tx_deinit_bank_profiles(struct dp_soc_be *be_soc)
  1268. {
  1269. qdf_mem_free(be_soc->bank_profiles);
  1270. DP_TX_BANK_LOCK_DESTROY(&be_soc->tx_bank_lock);
  1271. }
  1272. static
  1273. void dp_tx_get_vdev_bank_config(struct dp_vdev_be *be_vdev,
  1274. union hal_tx_bank_config *bank_config)
  1275. {
  1276. struct dp_vdev *vdev = &be_vdev->vdev;
  1277. bank_config->epd = 0;
  1278. bank_config->encap_type = vdev->tx_encap_type;
  1279. /* Only valid for raw frames. Needs work for RAW mode */
  1280. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) {
  1281. bank_config->encrypt_type = sec_type_map[vdev->sec_type];
  1282. } else {
  1283. bank_config->encrypt_type = 0;
  1284. }
  1285. bank_config->src_buffer_swap = 0;
  1286. bank_config->link_meta_swap = 0;
  1287. if ((vdev->search_type == HAL_TX_ADDR_INDEX_SEARCH) &&
  1288. vdev->opmode == wlan_op_mode_sta) {
  1289. bank_config->index_lookup_enable = 1;
  1290. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_MEC_NOTIFY;
  1291. bank_config->addrx_en = 0;
  1292. bank_config->addry_en = 0;
  1293. } else {
  1294. bank_config->index_lookup_enable = 0;
  1295. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1296. bank_config->addrx_en =
  1297. (vdev->hal_desc_addr_search_flags &
  1298. HAL_TX_DESC_ADDRX_EN) ? 1 : 0;
  1299. bank_config->addry_en =
  1300. (vdev->hal_desc_addr_search_flags &
  1301. HAL_TX_DESC_ADDRY_EN) ? 1 : 0;
  1302. }
  1303. bank_config->mesh_enable = vdev->mesh_vdev ? 1 : 0;
  1304. bank_config->dscp_tid_map_id = vdev->dscp_tid_map_id;
  1305. /* Disabling vdev id check for now. Needs revist. */
  1306. bank_config->vdev_id_check_en = be_vdev->vdev_id_check_en;
  1307. bank_config->pmac_id = vdev->lmac_id;
  1308. }
  1309. int dp_tx_get_bank_profile(struct dp_soc_be *be_soc,
  1310. struct dp_vdev_be *be_vdev)
  1311. {
  1312. char *temp_str = "";
  1313. bool found_match = false;
  1314. int bank_id = DP_BE_INVALID_BANK_ID;
  1315. int i;
  1316. int unconfigured_slot = DP_BE_INVALID_BANK_ID;
  1317. int zero_ref_count_slot = DP_BE_INVALID_BANK_ID;
  1318. union hal_tx_bank_config vdev_config = {0};
  1319. /* convert vdev params into hal_tx_bank_config */
  1320. dp_tx_get_vdev_bank_config(be_vdev, &vdev_config);
  1321. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1322. /* go over all banks and find a matching/unconfigured/unused bank */
  1323. for (i = 0; i < be_soc->num_bank_profiles; i++) {
  1324. if (be_soc->bank_profiles[i].is_configured &&
  1325. (be_soc->bank_profiles[i].bank_config.val ^
  1326. vdev_config.val) == 0) {
  1327. found_match = true;
  1328. break;
  1329. }
  1330. if (unconfigured_slot == DP_BE_INVALID_BANK_ID &&
  1331. !be_soc->bank_profiles[i].is_configured)
  1332. unconfigured_slot = i;
  1333. else if (zero_ref_count_slot == DP_BE_INVALID_BANK_ID &&
  1334. !qdf_atomic_read(&be_soc->bank_profiles[i].ref_count))
  1335. zero_ref_count_slot = i;
  1336. }
  1337. if (found_match) {
  1338. temp_str = "matching";
  1339. bank_id = i;
  1340. goto inc_ref_and_return;
  1341. }
  1342. if (unconfigured_slot != DP_BE_INVALID_BANK_ID) {
  1343. temp_str = "unconfigured";
  1344. bank_id = unconfigured_slot;
  1345. goto configure_and_return;
  1346. }
  1347. if (zero_ref_count_slot != DP_BE_INVALID_BANK_ID) {
  1348. temp_str = "zero_ref_count";
  1349. bank_id = zero_ref_count_slot;
  1350. }
  1351. if (bank_id == DP_BE_INVALID_BANK_ID) {
  1352. dp_alert("unable to find TX bank!");
  1353. QDF_BUG(0);
  1354. return bank_id;
  1355. }
  1356. configure_and_return:
  1357. be_soc->bank_profiles[bank_id].is_configured = true;
  1358. be_soc->bank_profiles[bank_id].bank_config.val = vdev_config.val;
  1359. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1360. &be_soc->bank_profiles[bank_id].bank_config,
  1361. bank_id);
  1362. inc_ref_and_return:
  1363. qdf_atomic_inc(&be_soc->bank_profiles[bank_id].ref_count);
  1364. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1365. dp_info("found %s slot at index %d, input:0x%x match:0x%x ref_count %u",
  1366. temp_str, bank_id, vdev_config.val,
  1367. be_soc->bank_profiles[bank_id].bank_config.val,
  1368. qdf_atomic_read(&be_soc->bank_profiles[bank_id].ref_count));
  1369. dp_info("epd:%x encap:%x encryp:%x src_buf_swap:%x link_meta_swap:%x addrx_en:%x addry_en:%x mesh_en:%x vdev_id_check:%x pmac_id:%x mcast_pkt_ctrl:%x",
  1370. be_soc->bank_profiles[bank_id].bank_config.epd,
  1371. be_soc->bank_profiles[bank_id].bank_config.encap_type,
  1372. be_soc->bank_profiles[bank_id].bank_config.encrypt_type,
  1373. be_soc->bank_profiles[bank_id].bank_config.src_buffer_swap,
  1374. be_soc->bank_profiles[bank_id].bank_config.link_meta_swap,
  1375. be_soc->bank_profiles[bank_id].bank_config.addrx_en,
  1376. be_soc->bank_profiles[bank_id].bank_config.addry_en,
  1377. be_soc->bank_profiles[bank_id].bank_config.mesh_enable,
  1378. be_soc->bank_profiles[bank_id].bank_config.vdev_id_check_en,
  1379. be_soc->bank_profiles[bank_id].bank_config.pmac_id,
  1380. be_soc->bank_profiles[bank_id].bank_config.mcast_pkt_ctrl);
  1381. return bank_id;
  1382. }
  1383. void dp_tx_put_bank_profile(struct dp_soc_be *be_soc,
  1384. struct dp_vdev_be *be_vdev)
  1385. {
  1386. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1387. qdf_atomic_dec(&be_soc->bank_profiles[be_vdev->bank_id].ref_count);
  1388. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1389. }
  1390. void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
  1391. struct dp_vdev_be *be_vdev)
  1392. {
  1393. dp_tx_put_bank_profile(be_soc, be_vdev);
  1394. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  1395. be_vdev->vdev.bank_id = be_vdev->bank_id;
  1396. }
  1397. QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
  1398. uint32_t num_elem,
  1399. uint8_t pool_id)
  1400. {
  1401. struct dp_tx_desc_pool_s *tx_desc_pool;
  1402. struct dp_hw_cookie_conversion_t *cc_ctx;
  1403. struct dp_soc_be *be_soc;
  1404. struct dp_spt_page_desc *page_desc;
  1405. struct dp_tx_desc_s *tx_desc;
  1406. uint32_t ppt_idx = 0;
  1407. uint32_t avail_entry_index = 0;
  1408. if (!num_elem) {
  1409. dp_err("desc_num 0 !!");
  1410. return QDF_STATUS_E_FAILURE;
  1411. }
  1412. be_soc = dp_get_be_soc_from_dp_soc(soc);
  1413. tx_desc_pool = &soc->tx_desc[pool_id];
  1414. cc_ctx = &be_soc->tx_cc_ctx[pool_id];
  1415. tx_desc = tx_desc_pool->freelist;
  1416. page_desc = &cc_ctx->page_desc_base[0];
  1417. while (tx_desc) {
  1418. if (avail_entry_index == 0) {
  1419. if (ppt_idx >= cc_ctx->total_page_num) {
  1420. dp_alert("insufficient secondary page tables");
  1421. qdf_assert_always(0);
  1422. }
  1423. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  1424. }
  1425. /* put each TX Desc VA to SPT pages and
  1426. * get corresponding ID
  1427. */
  1428. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  1429. avail_entry_index,
  1430. tx_desc);
  1431. tx_desc->id =
  1432. dp_cc_desc_id_generate(page_desc->ppt_index,
  1433. avail_entry_index);
  1434. tx_desc->pool_id = pool_id;
  1435. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  1436. tx_desc = tx_desc->next;
  1437. avail_entry_index = (avail_entry_index + 1) &
  1438. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  1439. }
  1440. return QDF_STATUS_SUCCESS;
  1441. }
  1442. void dp_tx_desc_pool_deinit_be(struct dp_soc *soc,
  1443. struct dp_tx_desc_pool_s *tx_desc_pool,
  1444. uint8_t pool_id)
  1445. {
  1446. struct dp_spt_page_desc *page_desc;
  1447. struct dp_soc_be *be_soc;
  1448. int i = 0;
  1449. struct dp_hw_cookie_conversion_t *cc_ctx;
  1450. be_soc = dp_get_be_soc_from_dp_soc(soc);
  1451. cc_ctx = &be_soc->tx_cc_ctx[pool_id];
  1452. for (i = 0; i < cc_ctx->total_page_num; i++) {
  1453. page_desc = &cc_ctx->page_desc_base[i];
  1454. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  1455. }
  1456. }
  1457. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1458. uint32_t dp_tx_comp_nf_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  1459. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  1460. uint32_t quota)
  1461. {
  1462. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  1463. uint32_t work_done = 0;
  1464. if (dp_srng_get_near_full_level(soc, tx_comp_ring) <
  1465. DP_SRNG_THRESH_NEAR_FULL)
  1466. return 0;
  1467. qdf_atomic_set(&tx_comp_ring->near_full, 1);
  1468. work_done++;
  1469. return work_done;
  1470. }
  1471. #endif
  1472. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1473. defined(WLAN_CONFIG_TX_DELAY)
  1474. #define PPDUID_GET_HW_LINK_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  1475. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  1476. #define HW_TX_DELAY_MAX 0x1000000
  1477. #define TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US 10
  1478. #define HW_TX_DELAY_MASK 0x1FFFFFFF
  1479. #define TX_COMPL_BUFFER_TSTAMP_US(TSTAMP) \
  1480. (((TSTAMP) << TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US) & \
  1481. HW_TX_DELAY_MASK)
  1482. static inline
  1483. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1484. struct dp_vdev *vdev,
  1485. struct hal_tx_completion_status *ts,
  1486. uint32_t *delay_us)
  1487. {
  1488. uint32_t ppdu_id;
  1489. uint8_t link_id_offset, link_id_bits;
  1490. uint8_t hw_link_id;
  1491. uint32_t msdu_tqm_enqueue_tstamp_us, final_msdu_tqm_enqueue_tstamp_us;
  1492. uint32_t msdu_compl_tsf_tstamp_us, final_msdu_compl_tsf_tstamp_us;
  1493. uint32_t delay;
  1494. int32_t delta_tsf2, delta_tqm;
  1495. if (!ts->valid)
  1496. return QDF_STATUS_E_INVAL;
  1497. link_id_offset = soc->link_id_offset;
  1498. link_id_bits = soc->link_id_bits;
  1499. ppdu_id = ts->ppdu_id;
  1500. hw_link_id = PPDUID_GET_HW_LINK_ID(ppdu_id, link_id_offset,
  1501. link_id_bits);
  1502. msdu_tqm_enqueue_tstamp_us =
  1503. TX_COMPL_BUFFER_TSTAMP_US(ts->buffer_timestamp);
  1504. msdu_compl_tsf_tstamp_us = ts->tsf;
  1505. delta_tsf2 = dp_mlo_get_delta_tsf2_wrt_mlo_offset(soc, hw_link_id);
  1506. delta_tqm = dp_mlo_get_delta_tqm_wrt_mlo_offset(soc);
  1507. final_msdu_tqm_enqueue_tstamp_us = (msdu_tqm_enqueue_tstamp_us +
  1508. delta_tqm) & HW_TX_DELAY_MASK;
  1509. final_msdu_compl_tsf_tstamp_us = (msdu_compl_tsf_tstamp_us +
  1510. delta_tsf2) & HW_TX_DELAY_MASK;
  1511. delay = (final_msdu_compl_tsf_tstamp_us -
  1512. final_msdu_tqm_enqueue_tstamp_us) & HW_TX_DELAY_MASK;
  1513. if (delay > HW_TX_DELAY_MAX)
  1514. return QDF_STATUS_E_FAILURE;
  1515. if (delay_us)
  1516. *delay_us = delay;
  1517. return QDF_STATUS_SUCCESS;
  1518. }
  1519. #else
  1520. static inline
  1521. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1522. struct dp_vdev *vdev,
  1523. struct hal_tx_completion_status *ts,
  1524. uint32_t *delay_us)
  1525. {
  1526. return QDF_STATUS_SUCCESS;
  1527. }
  1528. #endif
  1529. QDF_STATUS dp_tx_compute_tx_delay_be(struct dp_soc *soc,
  1530. struct dp_vdev *vdev,
  1531. struct hal_tx_completion_status *ts,
  1532. uint32_t *delay_us)
  1533. {
  1534. return dp_mlo_compute_hw_delay_us(soc, vdev, ts, delay_us);
  1535. }
  1536. static inline
  1537. qdf_dma_addr_t dp_tx_nbuf_map_be(struct dp_vdev *vdev,
  1538. struct dp_tx_desc_s *tx_desc,
  1539. qdf_nbuf_t nbuf)
  1540. {
  1541. qdf_nbuf_dma_clean_range_no_dsb((void *)nbuf->data,
  1542. (void *)(nbuf->data + 256));
  1543. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1544. }
  1545. static inline
  1546. void dp_tx_nbuf_unmap_be(struct dp_soc *soc,
  1547. struct dp_tx_desc_s *desc)
  1548. {
  1549. }
  1550. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  1551. qdf_nbuf_t dp_tx_fast_send_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1552. qdf_nbuf_t nbuf)
  1553. {
  1554. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1555. struct dp_vdev *vdev = NULL;
  1556. struct dp_pdev *pdev = NULL;
  1557. struct dp_tx_desc_s *tx_desc;
  1558. uint16_t desc_pool_id;
  1559. uint16_t pkt_len;
  1560. qdf_dma_addr_t paddr;
  1561. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1562. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1563. hal_ring_handle_t hal_ring_hdl = NULL;
  1564. uint32_t *hal_tx_desc_cached;
  1565. void *hal_tx_desc;
  1566. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  1567. return nbuf;
  1568. vdev = soc->vdev_id_map[vdev_id];
  1569. if (qdf_unlikely(!vdev))
  1570. return nbuf;
  1571. desc_pool_id = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  1572. pkt_len = qdf_nbuf_headlen(nbuf);
  1573. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, pkt_len);
  1574. DP_STATS_INC(vdev, tx_i.rcvd_in_fast_xmit_flow, 1);
  1575. DP_STATS_INC(vdev, tx_i.rcvd_per_core[desc_pool_id], 1);
  1576. pdev = vdev->pdev;
  1577. if (dp_tx_limit_check(vdev, nbuf))
  1578. return nbuf;
  1579. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1580. if (qdf_unlikely(!tx_desc)) {
  1581. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1582. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1583. return nbuf;
  1584. }
  1585. dp_tx_outstanding_inc(pdev);
  1586. /* Initialize the SW tx descriptor */
  1587. tx_desc->nbuf = nbuf;
  1588. tx_desc->frm_type = dp_tx_frm_std;
  1589. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1590. tx_desc->vdev_id = vdev_id;
  1591. tx_desc->pdev = pdev;
  1592. tx_desc->pkt_offset = 0;
  1593. tx_desc->length = pkt_len;
  1594. tx_desc->flags |= DP_TX_DESC_FLAG_SIMPLE;
  1595. if (soc->hw_txrx_stats_en)
  1596. tx_desc->flags |= DP_TX_DESC_FLAG_FASTPATH_SIMPLE;
  1597. tx_desc->nbuf->fast_recycled = 1;
  1598. if (nbuf->is_from_recycler && nbuf->fast_xmit)
  1599. tx_desc->flags |= DP_TX_DESC_FLAG_FAST;
  1600. paddr = dp_tx_nbuf_map_be(vdev, tx_desc, nbuf);
  1601. if (!paddr) {
  1602. /* Handle failure */
  1603. dp_err("qdf_nbuf_map failed");
  1604. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1605. goto release_desc;
  1606. }
  1607. tx_desc->dma_addr = paddr;
  1608. hal_tx_desc_cached = (void *)cached_desc;
  1609. hal_tx_desc_cached[0] = (uint32_t)tx_desc->dma_addr;
  1610. hal_tx_desc_cached[1] = tx_desc->id <<
  1611. TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  1612. /* bank_id */
  1613. hal_tx_desc_cached[2] = vdev->bank_id << TCL_DATA_CMD_BANK_ID_LSB;
  1614. hal_tx_desc_cached[3] = vdev->htt_tcl_metadata <<
  1615. TCL_DATA_CMD_TCL_CMD_NUMBER_LSB;
  1616. hal_tx_desc_cached[4] = tx_desc->length;
  1617. /* l3 and l4 checksum enable */
  1618. hal_tx_desc_cached[4] |= DP_TX_L3_L4_CSUM_ENABLE <<
  1619. TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB;
  1620. hal_tx_desc_cached[5] = vdev->lmac_id << TCL_DATA_CMD_PMAC_ID_LSB;
  1621. hal_tx_desc_cached[5] |= vdev->vdev_id << TCL_DATA_CMD_VDEV_ID_LSB;
  1622. if (vdev->opmode == wlan_op_mode_sta)
  1623. hal_tx_desc_cached[6] = vdev->bss_ast_idx |
  1624. ((vdev->bss_ast_hash & 0xF) <<
  1625. TCL_DATA_CMD_CACHE_SET_NUM_LSB);
  1626. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, desc_pool_id);
  1627. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1628. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1629. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1630. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1631. goto ring_access_fail2;
  1632. }
  1633. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1634. if (qdf_unlikely(!hal_tx_desc)) {
  1635. dp_verbose_debug("TCL ring full ring_id:%d", desc_pool_id);
  1636. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1637. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1638. goto ring_access_fail;
  1639. }
  1640. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1641. /* Sync cached descriptor with HW */
  1642. qdf_mem_copy(hal_tx_desc, hal_tx_desc_cached, DP_TX_FAST_DESC_SIZE);
  1643. qdf_dsb();
  1644. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1645. DP_STATS_INC(soc, tx.tcl_enq[desc_pool_id], 1);
  1646. status = QDF_STATUS_SUCCESS;
  1647. ring_access_fail:
  1648. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1649. ring_access_fail2:
  1650. if (status != QDF_STATUS_SUCCESS) {
  1651. dp_tx_nbuf_unmap_be(soc, tx_desc);
  1652. goto release_desc;
  1653. }
  1654. return NULL;
  1655. release_desc:
  1656. dp_tx_desc_release(soc, tx_desc, desc_pool_id);
  1657. return nbuf;
  1658. }
  1659. #endif
  1660. QDF_STATUS dp_tx_desc_pool_alloc_be(struct dp_soc *soc, uint32_t num_elem,
  1661. uint8_t pool_id)
  1662. {
  1663. return QDF_STATUS_SUCCESS;
  1664. }
  1665. void dp_tx_desc_pool_free_be(struct dp_soc *soc, uint8_t pool_id)
  1666. {
  1667. }