hal_internal.h 25 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_INTERNAL_H_
  19. #define _HAL_INTERNAL_H_
  20. #include "qdf_types.h"
  21. #include "qdf_atomic.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "pld_common.h"
  26. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  27. #include "qdf_defer.h"
  28. #endif
  29. #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
  30. #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params)
  31. #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params)
  32. #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params)
  33. #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  34. #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
  35. #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
  36. #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
  37. #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
  38. #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
  39. #ifdef ENABLE_VERBOSE_DEBUG
  40. extern bool is_hal_verbose_debug_enabled;
  41. #define hal_verbose_debug(params...) \
  42. if (unlikely(is_hal_verbose_debug_enabled)) \
  43. do {\
  44. QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \
  45. } while (0)
  46. #define hal_verbose_hex_dump(params...) \
  47. if (unlikely(is_hal_verbose_debug_enabled)) \
  48. do {\
  49. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \
  50. QDF_TRACE_LEVEL_DEBUG, \
  51. params); \
  52. } while (0)
  53. #else
  54. #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  55. #define hal_verbose_hex_dump(params...) \
  56. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \
  57. params)
  58. #endif
  59. /*
  60. * dp_hal_soc - opaque handle for DP HAL soc
  61. */
  62. struct hal_soc_handle;
  63. typedef struct hal_soc_handle *hal_soc_handle_t;
  64. /**
  65. * hal_ring_desc - opaque handle for DP ring descriptor
  66. */
  67. struct hal_ring_desc;
  68. typedef struct hal_ring_desc *hal_ring_desc_t;
  69. /**
  70. * hal_link_desc - opaque handle for DP link descriptor
  71. */
  72. struct hal_link_desc;
  73. typedef struct hal_link_desc *hal_link_desc_t;
  74. /**
  75. * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
  76. */
  77. struct hal_rxdma_desc;
  78. typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
  79. /**
  80. * hal_buff_addrinfo - opaque handle for DP buffer address info
  81. */
  82. struct hal_buff_addrinfo;
  83. typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
  84. /**
  85. * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
  86. */
  87. struct hal_rx_mon_desc_info;
  88. typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
  89. /* TBD: This should be movded to shared HW header file */
  90. enum hal_srng_ring_id {
  91. /* UMAC rings */
  92. HAL_SRNG_REO2SW1 = 0,
  93. HAL_SRNG_REO2SW2 = 1,
  94. HAL_SRNG_REO2SW3 = 2,
  95. HAL_SRNG_REO2SW4 = 3,
  96. HAL_SRNG_REO2TCL = 4,
  97. HAL_SRNG_SW2REO = 5,
  98. /* 6-7 unused */
  99. HAL_SRNG_REO_CMD = 8,
  100. HAL_SRNG_REO_STATUS = 9,
  101. /* 10-15 unused */
  102. HAL_SRNG_SW2TCL1 = 16,
  103. HAL_SRNG_SW2TCL2 = 17,
  104. HAL_SRNG_SW2TCL3 = 18,
  105. HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
  106. /* 20-23 unused */
  107. HAL_SRNG_SW2TCL_CMD = 24,
  108. HAL_SRNG_TCL_STATUS = 25,
  109. /* 26-31 unused */
  110. HAL_SRNG_CE_0_SRC = 32,
  111. HAL_SRNG_CE_1_SRC = 33,
  112. HAL_SRNG_CE_2_SRC = 34,
  113. HAL_SRNG_CE_3_SRC = 35,
  114. HAL_SRNG_CE_4_SRC = 36,
  115. HAL_SRNG_CE_5_SRC = 37,
  116. HAL_SRNG_CE_6_SRC = 38,
  117. HAL_SRNG_CE_7_SRC = 39,
  118. HAL_SRNG_CE_8_SRC = 40,
  119. HAL_SRNG_CE_9_SRC = 41,
  120. HAL_SRNG_CE_10_SRC = 42,
  121. HAL_SRNG_CE_11_SRC = 43,
  122. /* 44-55 unused */
  123. HAL_SRNG_CE_0_DST = 56,
  124. HAL_SRNG_CE_1_DST = 57,
  125. HAL_SRNG_CE_2_DST = 58,
  126. HAL_SRNG_CE_3_DST = 59,
  127. HAL_SRNG_CE_4_DST = 60,
  128. HAL_SRNG_CE_5_DST = 61,
  129. HAL_SRNG_CE_6_DST = 62,
  130. HAL_SRNG_CE_7_DST = 63,
  131. HAL_SRNG_CE_8_DST = 64,
  132. HAL_SRNG_CE_9_DST = 65,
  133. HAL_SRNG_CE_10_DST = 66,
  134. HAL_SRNG_CE_11_DST = 67,
  135. /* 68-79 unused */
  136. HAL_SRNG_CE_0_DST_STATUS = 80,
  137. HAL_SRNG_CE_1_DST_STATUS = 81,
  138. HAL_SRNG_CE_2_DST_STATUS = 82,
  139. HAL_SRNG_CE_3_DST_STATUS = 83,
  140. HAL_SRNG_CE_4_DST_STATUS = 84,
  141. HAL_SRNG_CE_5_DST_STATUS = 85,
  142. HAL_SRNG_CE_6_DST_STATUS = 86,
  143. HAL_SRNG_CE_7_DST_STATUS = 87,
  144. HAL_SRNG_CE_8_DST_STATUS = 88,
  145. HAL_SRNG_CE_9_DST_STATUS = 89,
  146. HAL_SRNG_CE_10_DST_STATUS = 90,
  147. HAL_SRNG_CE_11_DST_STATUS = 91,
  148. /* 92-103 unused */
  149. HAL_SRNG_WBM_IDLE_LINK = 104,
  150. HAL_SRNG_WBM_SW_RELEASE = 105,
  151. HAL_SRNG_WBM2SW0_RELEASE = 106,
  152. HAL_SRNG_WBM2SW1_RELEASE = 107,
  153. HAL_SRNG_WBM2SW2_RELEASE = 108,
  154. HAL_SRNG_WBM2SW3_RELEASE = 109,
  155. /* 110-127 unused */
  156. HAL_SRNG_UMAC_ID_END = 127,
  157. /* LMAC rings - The following set will be replicated for each LMAC */
  158. HAL_SRNG_LMAC1_ID_START = 128,
  159. HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
  160. #ifdef IPA_OFFLOAD
  161. HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1),
  162. HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2),
  163. HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1),
  164. #else
  165. HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1),
  166. #endif
  167. HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1),
  168. HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1),
  169. HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF =
  170. (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1),
  171. HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1),
  172. HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1),
  173. HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1),
  174. #ifdef WLAN_FEATURE_CIF_CFR
  175. HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
  176. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1),
  177. #else
  178. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
  179. #endif
  180. /* -142 unused */
  181. HAL_SRNG_LMAC1_ID_END = 143
  182. };
  183. #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
  184. #define HAL_MAX_LMACS 3
  185. #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
  186. #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
  187. #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
  188. enum hal_srng_dir {
  189. HAL_SRNG_SRC_RING,
  190. HAL_SRNG_DST_RING
  191. };
  192. /* Lock wrappers for SRNG */
  193. #define hal_srng_lock_t qdf_spinlock_t
  194. #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
  195. #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
  196. #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock)
  197. #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
  198. #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
  199. struct hal_soc;
  200. /**
  201. * dp_hal_ring - opaque handle for DP HAL SRNG
  202. */
  203. struct hal_ring_handle;
  204. typedef struct hal_ring_handle *hal_ring_handle_t;
  205. #define MAX_SRNG_REG_GROUPS 2
  206. /* Hal Srng bit mask
  207. * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
  208. */
  209. #define HAL_SRNG_FLUSH_EVENT BIT(0)
  210. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  211. /**
  212. * struct hal_reg_write_q_elem - delayed register write queue element
  213. * @srng: hal_srng queued for a delayed write
  214. * @addr: iomem address of the register
  215. * @enqueue_val: register value at the time of delayed write enqueue
  216. * @dequeue_val: register value at the time of delayed write dequeue
  217. * @valid: whether this entry is valid or not
  218. * @enqueue_time: enqueue time (qdf_log_timestamp)
  219. * @work_scheduled_time: work scheduled time (qdf_log_timestamp)
  220. * @dequeue_time: dequeue time (qdf_log_timestamp)
  221. */
  222. struct hal_reg_write_q_elem {
  223. struct hal_srng *srng;
  224. void __iomem *addr;
  225. uint32_t enqueue_val;
  226. uint32_t dequeue_val;
  227. uint8_t valid;
  228. qdf_time_t enqueue_time;
  229. qdf_time_t work_scheduled_time;
  230. qdf_time_t dequeue_time;
  231. };
  232. /**
  233. * struct hal_reg_write_srng_stats - srng stats to keep track of register writes
  234. * @enqueues: writes enqueued to delayed work
  235. * @dequeues: writes dequeued from delayed work (not written yet)
  236. * @coalesces: writes not enqueued since srng is already queued up
  237. * @direct: writes not enqueued and written to register directly
  238. */
  239. struct hal_reg_write_srng_stats {
  240. uint32_t enqueues;
  241. uint32_t dequeues;
  242. uint32_t coalesces;
  243. uint32_t direct;
  244. };
  245. /**
  246. * enum hal_reg_sched_delay - ENUM for write sched delay histogram
  247. * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us
  248. * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us
  249. * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us
  250. * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us
  251. * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array)
  252. */
  253. enum hal_reg_sched_delay {
  254. REG_WRITE_SCHED_DELAY_SUB_100us,
  255. REG_WRITE_SCHED_DELAY_SUB_1000us,
  256. REG_WRITE_SCHED_DELAY_SUB_5000us,
  257. REG_WRITE_SCHED_DELAY_GT_5000us,
  258. REG_WRITE_SCHED_DELAY_HIST_MAX,
  259. };
  260. /**
  261. * struct hal_reg_write_soc_stats - soc stats to keep track of register writes
  262. * @enqueues: writes enqueued to delayed work
  263. * @dequeues: writes dequeued from delayed work (not written yet)
  264. * @coalesces: writes not enqueued since srng is already queued up
  265. * @direct: writes not enqueud and writted to register directly
  266. * @prevent_l1_fails: prevent l1 API failed
  267. * @q_depth: current queue depth in delayed register write queue
  268. * @max_q_depth: maximum queue for delayed register write queue
  269. * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram
  270. */
  271. struct hal_reg_write_soc_stats {
  272. qdf_atomic_t enqueues;
  273. uint32_t dequeues;
  274. qdf_atomic_t coalesces;
  275. qdf_atomic_t direct;
  276. uint32_t prevent_l1_fails;
  277. qdf_atomic_t q_depth;
  278. uint32_t max_q_depth;
  279. uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
  280. };
  281. #endif
  282. /* Common SRNG ring structure for source and destination rings */
  283. struct hal_srng {
  284. /* Unique SRNG ring ID */
  285. uint8_t ring_id;
  286. /* Ring initialization done */
  287. uint8_t initialized;
  288. /* Interrupt/MSI value assigned to this ring */
  289. int irq;
  290. /* Physical base address of the ring */
  291. qdf_dma_addr_t ring_base_paddr;
  292. /* Virtual base address of the ring */
  293. uint32_t *ring_base_vaddr;
  294. /* Number of entries in ring */
  295. uint32_t num_entries;
  296. /* Ring size */
  297. uint32_t ring_size;
  298. /* Ring size mask */
  299. uint32_t ring_size_mask;
  300. /* Size of ring entry */
  301. uint32_t entry_size;
  302. /* Interrupt timer threshold – in micro seconds */
  303. uint32_t intr_timer_thres_us;
  304. /* Interrupt batch counter threshold – in number of ring entries */
  305. uint32_t intr_batch_cntr_thres_entries;
  306. /* Applicable only for CE dest ring */
  307. uint32_t prefetch_timer;
  308. /* MSI Address */
  309. qdf_dma_addr_t msi_addr;
  310. /* MSI data */
  311. uint32_t msi_data;
  312. /* Misc flags */
  313. uint32_t flags;
  314. /* Lock for serializing ring index updates */
  315. hal_srng_lock_t lock;
  316. /* Start offset of SRNG register groups for this ring
  317. * TBD: See if this is required - register address can be derived
  318. * from ring ID
  319. */
  320. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  321. /* Source or Destination ring */
  322. enum hal_srng_dir ring_dir;
  323. union {
  324. struct {
  325. /* SW tail pointer */
  326. uint32_t tp;
  327. /* Shadow head pointer location to be updated by HW */
  328. uint32_t *hp_addr;
  329. /* Cached head pointer */
  330. uint32_t cached_hp;
  331. /* Tail pointer location to be updated by SW – This
  332. * will be a register address and need not be
  333. * accessed through SW structure */
  334. uint32_t *tp_addr;
  335. /* Current SW loop cnt */
  336. uint32_t loop_cnt;
  337. /* max transfer size */
  338. uint16_t max_buffer_length;
  339. } dst_ring;
  340. struct {
  341. /* SW head pointer */
  342. uint32_t hp;
  343. /* SW reap head pointer */
  344. uint32_t reap_hp;
  345. /* Shadow tail pointer location to be updated by HW */
  346. uint32_t *tp_addr;
  347. /* Cached tail pointer */
  348. uint32_t cached_tp;
  349. /* Head pointer location to be updated by SW – This
  350. * will be a register address and need not be accessed
  351. * through SW structure */
  352. uint32_t *hp_addr;
  353. /* Low threshold – in number of ring entries */
  354. uint32_t low_threshold;
  355. } src_ring;
  356. } u;
  357. struct hal_soc *hal_soc;
  358. /* Number of times hp/tp updated in runtime resume */
  359. uint32_t flush_count;
  360. /* hal srng event flag*/
  361. unsigned long srng_event;
  362. /* last flushed time stamp */
  363. uint64_t last_flush_ts;
  364. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  365. /* flag to indicate whether srng is already queued for delayed write */
  366. uint8_t reg_write_in_progress;
  367. /* srng specific delayed write stats */
  368. struct hal_reg_write_srng_stats wstats;
  369. #endif
  370. };
  371. /* HW SRNG configuration table */
  372. struct hal_hw_srng_config {
  373. int start_ring_id;
  374. uint16_t max_rings;
  375. uint16_t entry_size;
  376. uint32_t reg_start[MAX_SRNG_REG_GROUPS];
  377. uint16_t reg_size[MAX_SRNG_REG_GROUPS];
  378. uint8_t lmac_ring;
  379. enum hal_srng_dir ring_dir;
  380. uint32_t max_size;
  381. };
  382. #define MAX_SHADOW_REGISTERS 36
  383. /* REO parameters to be passed to hal_reo_setup */
  384. struct hal_reo_params {
  385. /** rx hash steering enabled or disabled */
  386. bool rx_hash_enabled;
  387. /** reo remap 1 register */
  388. uint32_t remap1;
  389. /** reo remap 2 register */
  390. uint32_t remap2;
  391. /** fragment destination ring */
  392. uint8_t frag_dst_ring;
  393. /** padding */
  394. uint8_t padding[3];
  395. };
  396. struct hal_hw_txrx_ops {
  397. /* init and setup */
  398. void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
  399. struct hal_srng *srng);
  400. void (*hal_srng_src_hw_init)(struct hal_soc *hal,
  401. struct hal_srng *srng);
  402. void (*hal_get_hw_hptp)(struct hal_soc *hal,
  403. hal_ring_handle_t hal_ring_hdl,
  404. uint32_t *headp, uint32_t *tailp,
  405. uint8_t ring_type);
  406. void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams);
  407. void (*hal_setup_link_idle_list)(
  408. struct hal_soc *hal_soc,
  409. qdf_dma_addr_t scatter_bufs_base_paddr[],
  410. void *scatter_bufs_base_vaddr[],
  411. uint32_t num_scatter_bufs,
  412. uint32_t scatter_buf_size,
  413. uint32_t last_buf_end_offset,
  414. uint32_t num_entries);
  415. qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
  416. qdf_iomem_t addr);
  417. void (*hal_reo_set_err_dst_remap)(void *hal_soc);
  418. /* tx */
  419. void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
  420. void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
  421. uint8_t id);
  422. void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
  423. uint8_t id,
  424. uint8_t dscp);
  425. void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
  426. void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
  427. uint8_t pool_id, uint32_t desc_id, uint8_t type);
  428. void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
  429. void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
  430. void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
  431. void (*hal_tx_comp_get_status)(void *desc, void *ts,
  432. struct hal_soc *hal);
  433. uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
  434. uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
  435. void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
  436. void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
  437. hal_ring_handle_t hal_ring_hdl);
  438. /* rx */
  439. uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
  440. void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
  441. struct mon_rx_status *rs);
  442. uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
  443. void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
  444. void *ppdu_info_handle);
  445. void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
  446. void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
  447. uint8_t dbg_level);
  448. uint32_t (*hal_get_link_desc_size)(void);
  449. uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
  450. uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
  451. uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
  452. void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
  453. void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
  454. void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h);
  455. uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
  456. void *ppdu_info,
  457. hal_soc_handle_t hal_soc_hdl,
  458. qdf_nbuf_t nbuf);
  459. void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
  460. void *wbm_er_info);
  461. void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart,
  462. uint8_t dbg_level);
  463. void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
  464. void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
  465. uint8_t id);
  466. void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
  467. uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
  468. uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
  469. uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
  470. uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
  471. uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
  472. uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
  473. uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
  474. void (*hal_rx_print_pn)(uint8_t *buf);
  475. uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
  476. uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
  477. uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
  478. bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
  479. uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
  480. uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
  481. uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
  482. uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
  483. QDF_STATUS
  484. (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
  485. QDF_STATUS
  486. (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
  487. QDF_STATUS
  488. (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
  489. QDF_STATUS
  490. (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
  491. uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
  492. bool (*hal_rx_is_unicast)(uint8_t *buf);
  493. uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
  494. uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
  495. void *rxdma_dst_ring_desc);
  496. uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
  497. uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
  498. void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
  499. void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
  500. void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
  501. void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
  502. uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
  503. uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
  504. uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
  505. uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
  506. uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
  507. void (*hal_reo_config)(struct hal_soc *soc,
  508. uint32_t reg_val,
  509. struct hal_reo_params *reo_params);
  510. uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
  511. bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
  512. bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
  513. uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
  514. uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
  515. void
  516. (*hal_rx_msdu_get_flow_params)(
  517. uint8_t *buf,
  518. bool *flow_invalid,
  519. bool *flow_timeout,
  520. uint32_t *flow_index);
  521. uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
  522. uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
  523. void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
  524. void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
  525. void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
  526. void *msdu_pkt_metadata);
  527. uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
  528. uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
  529. bool (*hal_rx_get_udp_proto)(uint8_t *buf);
  530. bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
  531. uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
  532. bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
  533. uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
  534. void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
  535. hal_rx_mon_desc_info_t mon_desc_info);
  536. uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc);
  537. uint32_t (*hal_rx_msdu_end_offset_get)(void);
  538. uint32_t (*hal_rx_attn_offset_get)(void);
  539. uint32_t (*hal_rx_msdu_start_offset_get)(void);
  540. uint32_t (*hal_rx_mpdu_start_offset_get)(void);
  541. uint32_t (*hal_rx_mpdu_end_offset_get)(void);
  542. void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
  543. uint32_t table_offset,
  544. uint8_t *rx_flow);
  545. void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring,
  546. uint32_t num_rings,
  547. uint32_t *remap1,
  548. uint32_t *remap2);
  549. };
  550. /**
  551. * struct hal_soc_stats - Hal layer stats
  552. * @reg_write_fail: number of failed register writes
  553. * @wstats: delayed register write stats
  554. *
  555. * This structure holds all the statistics at HAL layer.
  556. */
  557. struct hal_soc_stats {
  558. uint32_t reg_write_fail;
  559. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  560. struct hal_reg_write_soc_stats wstats;
  561. #endif
  562. };
  563. #ifdef ENABLE_HAL_REG_WR_HISTORY
  564. /* The history size should always be a power of 2 */
  565. #define HAL_REG_WRITE_HIST_SIZE 8
  566. /**
  567. * struct hal_reg_write_fail_entry - Record of
  568. * register write which failed.
  569. * @timestamp: timestamp of reg write failure
  570. * @reg_offset: offset of register where the write failed
  571. * @write_val: the value which was to be written
  572. * @read_val: the value read back from the register after write
  573. */
  574. struct hal_reg_write_fail_entry {
  575. uint64_t timestamp;
  576. uint32_t reg_offset;
  577. uint32_t write_val;
  578. uint32_t read_val;
  579. };
  580. /**
  581. * struct hal_reg_write_fail_history - Hal layer history
  582. * of all the register write failures.
  583. * @index: index to add the new record
  584. * @record: array of all the records in history
  585. *
  586. * This structure holds the history of register write
  587. * failures at HAL layer.
  588. */
  589. struct hal_reg_write_fail_history {
  590. qdf_atomic_t index;
  591. struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
  592. };
  593. #endif
  594. /**
  595. * HAL context to be used to access SRNG APIs (currently used by data path
  596. * and transport (CE) modules)
  597. */
  598. struct hal_soc {
  599. /* HIF handle to access HW registers */
  600. struct hif_opaque_softc *hif_handle;
  601. /* QDF device handle */
  602. qdf_device_t qdf_dev;
  603. /* Device base address */
  604. void *dev_base_addr;
  605. /* Device base address for ce - qca5018 target */
  606. void *dev_base_addr_ce;
  607. /* HAL internal state for all SRNG rings.
  608. * TODO: See if this is required
  609. */
  610. struct hal_srng srng_list[HAL_SRNG_ID_MAX];
  611. /* Remote pointer memory for HW/FW updates */
  612. uint32_t *shadow_rdptr_mem_vaddr;
  613. qdf_dma_addr_t shadow_rdptr_mem_paddr;
  614. /* Shared memory for ring pointer updates from host to FW */
  615. uint32_t *shadow_wrptr_mem_vaddr;
  616. qdf_dma_addr_t shadow_wrptr_mem_paddr;
  617. /* REO blocking resource index */
  618. uint8_t reo_res_bitmap;
  619. uint8_t index;
  620. uint32_t target_type;
  621. /* shadow register configuration */
  622. struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS];
  623. int num_shadow_registers_configured;
  624. bool use_register_windowing;
  625. uint32_t register_window;
  626. qdf_spinlock_t register_access_lock;
  627. /* Static window map configuration for multiple window write*/
  628. bool static_window_map;
  629. /* srng table */
  630. struct hal_hw_srng_config *hw_srng_table;
  631. int32_t *hal_hw_reg_offset;
  632. struct hal_hw_txrx_ops *ops;
  633. /* Indicate srngs initialization */
  634. bool init_phase;
  635. /* Hal level stats */
  636. struct hal_soc_stats stats;
  637. #ifdef ENABLE_HAL_REG_WR_HISTORY
  638. struct hal_reg_write_fail_history *reg_wr_fail_hist;
  639. #endif
  640. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  641. /* queue(array) to hold register writes */
  642. struct hal_reg_write_q_elem *reg_write_queue;
  643. /* delayed work to be queued into workqueue */
  644. qdf_work_t reg_write_work;
  645. /* workqueue for delayed register writes */
  646. qdf_workqueue_t *reg_write_wq;
  647. /* write index used by caller to enqueue delayed work */
  648. qdf_atomic_t write_idx;
  649. /* read index used by worker thread to dequeue/write registers */
  650. uint32_t read_idx;
  651. #endif
  652. qdf_atomic_t active_work_cnt;
  653. };
  654. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  655. /**
  656. * hal_delayed_reg_write() - delayed regiter write
  657. * @hal_soc: HAL soc handle
  658. * @srng: hal srng
  659. * @addr: iomem address
  660. * @value: value to be written
  661. *
  662. * Return: none
  663. */
  664. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  665. struct hal_srng *srng,
  666. void __iomem *addr,
  667. uint32_t value);
  668. #endif
  669. void hal_qca6750_attach(struct hal_soc *hal_soc);
  670. void hal_qca6490_attach(struct hal_soc *hal_soc);
  671. void hal_qca6390_attach(struct hal_soc *hal_soc);
  672. void hal_qca6290_attach(struct hal_soc *hal_soc);
  673. void hal_qca8074_attach(struct hal_soc *hal_soc);
  674. /*
  675. * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
  676. * dp_hal_soc handle type
  677. * @hal_soc - hal_soc type
  678. *
  679. * Return: hal_soc_handle_t type
  680. */
  681. static inline
  682. hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
  683. {
  684. return (hal_soc_handle_t)hal_soc;
  685. }
  686. /*
  687. * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque
  688. * dp_hal_ring handle type
  689. * @hal_srng - hal_srng type
  690. *
  691. * Return: hal_ring_handle_t type
  692. */
  693. static inline
  694. hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
  695. {
  696. return (hal_ring_handle_t)hal_srng;
  697. }
  698. /*
  699. * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle
  700. * @hal_ring - hal_ring_handle_t type
  701. *
  702. * Return: hal_srng pointer type
  703. */
  704. static inline
  705. struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
  706. {
  707. return (struct hal_srng *)hal_ring;
  708. }
  709. #endif /* _HAL_INTERNAL_H_ */