dp_tx.c 84 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. /**
  68. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  69. * @vdev: DP Virtual device handle
  70. * @nbuf: Buffer pointer
  71. * @queue: queue ids container for nbuf
  72. *
  73. * TX packet queue has 2 instances, software descriptors id and dma ring id
  74. * Based on tx feature and hardware configuration queue id combination could be
  75. * different.
  76. * For example -
  77. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  78. * With no XPS,lock based resource protection, Descriptor pool ids are different
  79. * for each vdev, dma ring id will be same as single pdev id
  80. *
  81. * Return: None
  82. */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. qdf_atomic_dec(&pdev->num_tx_outstanding);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  168. qdf_atomic_dec(&pdev->num_tx_exception);
  169. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  170. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  171. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  172. else
  173. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  175. "Tx Completion Release desc %d status %d outstanding %d",
  176. tx_desc->id, comp_status,
  177. qdf_atomic_read(&pdev->num_tx_outstanding));
  178. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  179. return;
  180. }
  181. /**
  182. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  183. * @vdev: DP vdev Handle
  184. * @nbuf: skb
  185. *
  186. * Prepares and fills HTT metadata in the frame pre-header for special frames
  187. * that should be transmitted using varying transmit parameters.
  188. * There are 2 VDEV modes that currently needs this special metadata -
  189. * 1) Mesh Mode
  190. * 2) DSRC Mode
  191. *
  192. * Return: HTT metadata size
  193. *
  194. */
  195. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  196. uint32_t *meta_data)
  197. {
  198. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  199. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  200. uint8_t htt_desc_size;
  201. /* Size rounded of multiple of 8 bytes */
  202. uint8_t htt_desc_size_aligned;
  203. uint8_t *hdr = NULL;
  204. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  205. /*
  206. * Metadata - HTT MSDU Extension header
  207. */
  208. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  209. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  210. if (vdev->mesh_vdev) {
  211. /* Fill and add HTT metaheader */
  212. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  213. if (hdr == NULL) {
  214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  215. "Error in filling HTT metadata\n");
  216. return 0;
  217. }
  218. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  219. } else if (vdev->opmode == wlan_op_mode_ocb) {
  220. /* Todo - Add support for DSRC */
  221. }
  222. return htt_desc_size_aligned;
  223. }
  224. /**
  225. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  226. * @tso_seg: TSO segment to process
  227. * @ext_desc: Pointer to MSDU extension descriptor
  228. *
  229. * Return: void
  230. */
  231. #if defined(FEATURE_TSO)
  232. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  233. void *ext_desc)
  234. {
  235. uint8_t num_frag;
  236. uint32_t tso_flags;
  237. /*
  238. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  239. * tcp_flag_mask
  240. *
  241. * Checksum enable flags are set in TCL descriptor and not in Extension
  242. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  243. */
  244. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  245. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  246. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  247. tso_seg->tso_flags.ip_len);
  248. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  249. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  250. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  251. uint32_t lo = 0;
  252. uint32_t hi = 0;
  253. qdf_dmaaddr_to_32s(
  254. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  255. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  256. tso_seg->tso_frags[num_frag].length);
  257. }
  258. return;
  259. }
  260. #else
  261. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  262. void *ext_desc)
  263. {
  264. return;
  265. }
  266. #endif
  267. #if defined(FEATURE_TSO)
  268. /**
  269. * dp_tx_free_tso_seg() - Loop through the tso segments
  270. * allocated and free them
  271. *
  272. * @soc: soc handle
  273. * @free_seg: list of tso segments
  274. * @msdu_info: msdu descriptor
  275. *
  276. * Return - void
  277. */
  278. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  279. struct qdf_tso_seg_elem_t *free_seg,
  280. struct dp_tx_msdu_info_s *msdu_info)
  281. {
  282. struct qdf_tso_seg_elem_t *next_seg;
  283. while (free_seg) {
  284. next_seg = free_seg->next;
  285. dp_tx_tso_desc_free(soc,
  286. msdu_info->tx_queue.desc_pool_id,
  287. free_seg);
  288. free_seg = next_seg;
  289. }
  290. }
  291. /**
  292. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  293. * allocated and free them
  294. *
  295. * @soc: soc handle
  296. * @free_seg: list of tso segments
  297. * @msdu_info: msdu descriptor
  298. * Return - void
  299. */
  300. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  301. struct qdf_tso_num_seg_elem_t *free_seg,
  302. struct dp_tx_msdu_info_s *msdu_info)
  303. {
  304. struct qdf_tso_num_seg_elem_t *next_seg;
  305. while (free_seg) {
  306. next_seg = free_seg->next;
  307. dp_tso_num_seg_free(soc,
  308. msdu_info->tx_queue.desc_pool_id,
  309. free_seg);
  310. free_seg = next_seg;
  311. }
  312. }
  313. /**
  314. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  315. * @vdev: virtual device handle
  316. * @msdu: network buffer
  317. * @msdu_info: meta data associated with the msdu
  318. *
  319. * Return: QDF_STATUS_SUCCESS success
  320. */
  321. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  322. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *tso_seg;
  325. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  326. struct dp_soc *soc = vdev->pdev->soc;
  327. struct qdf_tso_info_t *tso_info;
  328. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  329. tso_info = &msdu_info->u.tso_info;
  330. tso_info->curr_seg = NULL;
  331. tso_info->tso_seg_list = NULL;
  332. tso_info->num_segs = num_seg;
  333. msdu_info->frm_type = dp_tx_frm_tso;
  334. tso_info->tso_num_seg_list = NULL;
  335. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  336. while (num_seg) {
  337. tso_seg = dp_tx_tso_desc_alloc(
  338. soc, msdu_info->tx_queue.desc_pool_id);
  339. if (tso_seg) {
  340. tso_seg->next = tso_info->tso_seg_list;
  341. tso_info->tso_seg_list = tso_seg;
  342. num_seg--;
  343. } else {
  344. struct qdf_tso_seg_elem_t *free_seg =
  345. tso_info->tso_seg_list;
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. }
  350. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  351. tso_num_seg = dp_tso_num_seg_alloc(soc,
  352. msdu_info->tx_queue.desc_pool_id);
  353. if (tso_num_seg) {
  354. tso_num_seg->next = tso_info->tso_num_seg_list;
  355. tso_info->tso_num_seg_list = tso_num_seg;
  356. } else {
  357. /* Bug: free tso_num_seg and tso_seg */
  358. /* Free the already allocated num of segments */
  359. struct qdf_tso_seg_elem_t *free_seg =
  360. tso_info->tso_seg_list;
  361. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  362. __func__);
  363. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  364. return QDF_STATUS_E_NOMEM;
  365. }
  366. msdu_info->num_seg =
  367. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  368. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  369. msdu_info->num_seg);
  370. if (!(msdu_info->num_seg)) {
  371. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  372. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  373. msdu_info);
  374. return QDF_STATUS_E_INVAL;
  375. }
  376. tso_info->curr_seg = tso_info->tso_seg_list;
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. #else
  380. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  381. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. return QDF_STATUS_E_NOMEM;
  384. }
  385. #endif
  386. /**
  387. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  388. * @vdev: DP Vdev handle
  389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  390. * @desc_pool_id: Descriptor Pool ID
  391. *
  392. * Return:
  393. */
  394. static
  395. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  396. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  397. {
  398. uint8_t i;
  399. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  400. struct dp_tx_seg_info_s *seg_info;
  401. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  402. struct dp_soc *soc = vdev->pdev->soc;
  403. /* Allocate an extension descriptor */
  404. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  405. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  406. if (!msdu_ext_desc) {
  407. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  408. return NULL;
  409. }
  410. if (qdf_unlikely(vdev->mesh_vdev)) {
  411. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  412. &msdu_info->meta_data[0],
  413. sizeof(struct htt_tx_msdu_desc_ext2_t));
  414. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  415. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  416. }
  417. switch (msdu_info->frm_type) {
  418. case dp_tx_frm_sg:
  419. case dp_tx_frm_me:
  420. case dp_tx_frm_raw:
  421. seg_info = msdu_info->u.sg_info.curr_seg;
  422. /* Update the buffer pointers in MSDU Extension Descriptor */
  423. for (i = 0; i < seg_info->frag_cnt; i++) {
  424. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  425. seg_info->frags[i].paddr_lo,
  426. seg_info->frags[i].paddr_hi,
  427. seg_info->frags[i].len);
  428. }
  429. break;
  430. case dp_tx_frm_tso:
  431. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  432. &cached_ext_desc[0]);
  433. break;
  434. default:
  435. break;
  436. }
  437. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  438. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  439. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  440. msdu_ext_desc->vaddr);
  441. return msdu_ext_desc;
  442. }
  443. /**
  444. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  445. * @vdev: DP vdev handle
  446. * @nbuf: skb
  447. * @desc_pool_id: Descriptor pool ID
  448. * Allocate and prepare Tx descriptor with msdu information.
  449. *
  450. * Return: Pointer to Tx Descriptor on success,
  451. * NULL on failure
  452. */
  453. static
  454. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  455. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  456. uint32_t *meta_data)
  457. {
  458. uint8_t align_pad;
  459. uint8_t is_exception = 0;
  460. uint8_t htt_hdr_size;
  461. struct ether_header *eh;
  462. struct dp_tx_desc_s *tx_desc;
  463. struct dp_pdev *pdev = vdev->pdev;
  464. struct dp_soc *soc = pdev->soc;
  465. /* Allocate software Tx descriptor */
  466. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  467. if (qdf_unlikely(!tx_desc)) {
  468. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  469. return NULL;
  470. }
  471. /* Flow control/Congestion Control counters */
  472. qdf_atomic_inc(&pdev->num_tx_outstanding);
  473. /* Initialize the SW tx descriptor */
  474. tx_desc->nbuf = nbuf;
  475. tx_desc->frm_type = dp_tx_frm_std;
  476. tx_desc->tx_encap_type = vdev->tx_encap_type;
  477. tx_desc->vdev = vdev;
  478. tx_desc->pdev = pdev;
  479. tx_desc->msdu_ext_desc = NULL;
  480. tx_desc->pkt_offset = 0;
  481. /*
  482. * For special modes (vdev_type == ocb or mesh), data frames should be
  483. * transmitted using varying transmit parameters (tx spec) which include
  484. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  485. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  486. * These frames are sent as exception packets to firmware.
  487. *
  488. * HW requirement is that metadata should always point to a
  489. * 8-byte aligned address. So we add alignment pad to start of buffer.
  490. * HTT Metadata should be ensured to be multiple of 8-bytes,
  491. * to get 8-byte aligned start address along with align_pad added
  492. *
  493. * |-----------------------------|
  494. * | |
  495. * |-----------------------------| <-----Buffer Pointer Address given
  496. * | | ^ in HW descriptor (aligned)
  497. * | HTT Metadata | |
  498. * | | |
  499. * | | | Packet Offset given in descriptor
  500. * | | |
  501. * |-----------------------------| |
  502. * | Alignment Pad | v
  503. * |-----------------------------| <----- Actual buffer start address
  504. * | SKB Data | (Unaligned)
  505. * | |
  506. * | |
  507. * | |
  508. * | |
  509. * | |
  510. * |-----------------------------|
  511. */
  512. if (qdf_unlikely(vdev->mesh_vdev ||
  513. (vdev->opmode == wlan_op_mode_ocb))) {
  514. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  515. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  516. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  517. "qdf_nbuf_push_head failed\n");
  518. goto failure;
  519. }
  520. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  521. meta_data);
  522. if (htt_hdr_size == 0)
  523. goto failure;
  524. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  525. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  526. is_exception = 1;
  527. }
  528. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  529. qdf_nbuf_map(soc->osdev, nbuf,
  530. QDF_DMA_TO_DEVICE))) {
  531. /* Handle failure */
  532. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  533. "qdf_nbuf_map failed\n");
  534. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  535. goto failure;
  536. }
  537. if (qdf_unlikely(vdev->nawds_enabled)) {
  538. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  539. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  540. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  541. is_exception = 1;
  542. }
  543. }
  544. #if !TQM_BYPASS_WAR
  545. if (is_exception)
  546. #endif
  547. {
  548. /* Temporary WAR due to TQM VP issues */
  549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  550. qdf_atomic_inc(&pdev->num_tx_exception);
  551. }
  552. return tx_desc;
  553. failure:
  554. dp_tx_desc_release(tx_desc, desc_pool_id);
  555. return NULL;
  556. }
  557. /**
  558. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  559. * @vdev: DP vdev handle
  560. * @nbuf: skb
  561. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  562. * @desc_pool_id : Descriptor Pool ID
  563. *
  564. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  565. * information. For frames wth fragments, allocate and prepare
  566. * an MSDU extension descriptor
  567. *
  568. * Return: Pointer to Tx Descriptor on success,
  569. * NULL on failure
  570. */
  571. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  572. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  573. uint8_t desc_pool_id)
  574. {
  575. struct dp_tx_desc_s *tx_desc;
  576. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  577. struct dp_pdev *pdev = vdev->pdev;
  578. struct dp_soc *soc = pdev->soc;
  579. /* Allocate software Tx descriptor */
  580. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  581. if (!tx_desc) {
  582. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  583. return NULL;
  584. }
  585. /* Flow control/Congestion Control counters */
  586. qdf_atomic_inc(&pdev->num_tx_outstanding);
  587. /* Initialize the SW tx descriptor */
  588. tx_desc->nbuf = nbuf;
  589. tx_desc->frm_type = msdu_info->frm_type;
  590. tx_desc->tx_encap_type = vdev->tx_encap_type;
  591. tx_desc->vdev = vdev;
  592. tx_desc->pdev = pdev;
  593. tx_desc->pkt_offset = 0;
  594. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  595. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  596. /* Handle scattered frames - TSO/SG/ME */
  597. /* Allocate and prepare an extension descriptor for scattered frames */
  598. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  599. if (!msdu_ext_desc) {
  600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  601. "%s Tx Extension Descriptor Alloc Fail\n",
  602. __func__);
  603. goto failure;
  604. }
  605. #if TQM_BYPASS_WAR
  606. /* Temporary WAR due to TQM VP issues */
  607. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  608. qdf_atomic_inc(&pdev->num_tx_exception);
  609. #endif
  610. if (qdf_unlikely(vdev->mesh_vdev))
  611. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  612. tx_desc->msdu_ext_desc = msdu_ext_desc;
  613. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  614. return tx_desc;
  615. failure:
  616. dp_tx_desc_release(tx_desc, desc_pool_id);
  617. return NULL;
  618. }
  619. /**
  620. * dp_tx_prepare_raw() - Prepare RAW packet TX
  621. * @vdev: DP vdev handle
  622. * @nbuf: buffer pointer
  623. * @seg_info: Pointer to Segment info Descriptor to be prepared
  624. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  625. * descriptor
  626. *
  627. * Return:
  628. */
  629. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  630. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  631. {
  632. qdf_nbuf_t curr_nbuf = NULL;
  633. uint16_t total_len = 0;
  634. qdf_dma_addr_t paddr;
  635. int32_t i;
  636. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  637. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  638. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  639. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  640. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  641. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  642. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  643. QDF_DMA_TO_DEVICE)) {
  644. qdf_print("dma map error\n");
  645. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  646. qdf_nbuf_free(nbuf);
  647. return NULL;
  648. }
  649. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  650. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  651. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  652. seg_info->frags[i].paddr_lo = paddr;
  653. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  654. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  655. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  656. total_len += qdf_nbuf_len(curr_nbuf);
  657. }
  658. seg_info->frag_cnt = i;
  659. seg_info->total_len = total_len;
  660. seg_info->next = NULL;
  661. sg_info->curr_seg = seg_info;
  662. msdu_info->frm_type = dp_tx_frm_raw;
  663. msdu_info->num_seg = 1;
  664. return nbuf;
  665. }
  666. /**
  667. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  668. * @soc: DP Soc Handle
  669. * @vdev: DP vdev handle
  670. * @tx_desc: Tx Descriptor Handle
  671. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  672. * @fw_metadata: Metadata to send to Target Firmware along with frame
  673. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  674. *
  675. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  676. * from software Tx descriptor
  677. *
  678. * Return:
  679. */
  680. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  681. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  682. uint16_t fw_metadata, uint8_t ring_id)
  683. {
  684. uint8_t type;
  685. uint16_t length;
  686. void *hal_tx_desc, *hal_tx_desc_cached;
  687. qdf_dma_addr_t dma_addr;
  688. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  689. /* Return Buffer Manager ID */
  690. uint8_t bm_id = ring_id;
  691. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  692. hal_tx_desc_cached = (void *) cached_desc;
  693. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  694. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  695. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  696. type = HAL_TX_BUF_TYPE_EXT_DESC;
  697. dma_addr = tx_desc->msdu_ext_desc->paddr;
  698. } else {
  699. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  700. type = HAL_TX_BUF_TYPE_BUFFER;
  701. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  702. }
  703. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  704. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  705. dma_addr , bm_id, tx_desc->id, type);
  706. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  707. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  708. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  709. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  710. vdev->dscp_tid_map_id);
  711. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  712. sec_type_map[vdev->sec_type]);
  713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  714. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  715. __func__, length, type, (uint64_t)dma_addr,
  716. tx_desc->pkt_offset, tx_desc->id);
  717. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  718. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  719. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  720. vdev->hal_desc_addr_search_flags);
  721. /* verify checksum offload configuration*/
  722. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  723. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  724. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  725. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  726. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  727. }
  728. if (tid != HTT_TX_EXT_TID_INVALID)
  729. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  730. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  731. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  732. /* Sync cached descriptor with HW */
  733. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  734. if (!hal_tx_desc) {
  735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  737. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  738. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  739. return QDF_STATUS_E_RESOURCES;
  740. }
  741. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  742. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  743. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  744. /*
  745. * If one packet is enqueued in HW, PM usage count needs to be
  746. * incremented by one to prevent future runtime suspend. This
  747. * should be tied with the success of enqueuing. It will be
  748. * decremented after the packet has been sent.
  749. */
  750. hif_pm_runtime_get_noresume(soc->hif_handle);
  751. return QDF_STATUS_SUCCESS;
  752. }
  753. /**
  754. * dp_cce_classify() - Classify the frame based on CCE rules
  755. * @vdev: DP vdev handle
  756. * @nbuf: skb
  757. *
  758. * Classify frames based on CCE rules
  759. * Return: bool( true if classified,
  760. * else false)
  761. */
  762. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  763. {
  764. struct ether_header *eh = NULL;
  765. uint16_t ether_type;
  766. qdf_llc_t *llcHdr;
  767. qdf_nbuf_t nbuf_clone = NULL;
  768. qdf_dot3_qosframe_t *qos_wh = NULL;
  769. /* for mesh packets don't do any classification */
  770. if (qdf_unlikely(vdev->mesh_vdev))
  771. return false;
  772. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  773. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  774. ether_type = eh->ether_type;
  775. llcHdr = (qdf_llc_t *)(nbuf->data +
  776. sizeof(struct ether_header));
  777. } else {
  778. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  779. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  780. if (qdf_unlikely(
  781. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  782. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  783. ether_type = *(uint16_t *)(nbuf->data
  784. + QDF_IEEE80211_4ADDR_HDR_LEN
  785. + sizeof(qdf_llc_t)
  786. - sizeof(ether_type));
  787. llcHdr = (qdf_llc_t *)(nbuf->data +
  788. QDF_IEEE80211_4ADDR_HDR_LEN);
  789. } else {
  790. ether_type = *(uint16_t *)(nbuf->data
  791. + QDF_IEEE80211_3ADDR_HDR_LEN
  792. + sizeof(qdf_llc_t)
  793. - sizeof(ether_type));
  794. llcHdr = (qdf_llc_t *)(nbuf->data +
  795. QDF_IEEE80211_3ADDR_HDR_LEN);
  796. }
  797. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  798. && (ether_type ==
  799. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  800. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  801. return true;
  802. }
  803. }
  804. return false;
  805. }
  806. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  807. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  808. sizeof(*llcHdr));
  809. nbuf_clone = qdf_nbuf_clone(nbuf);
  810. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  811. if (ether_type == htons(ETHERTYPE_8021Q)) {
  812. qdf_nbuf_pull_head(nbuf_clone,
  813. sizeof(qdf_net_vlanhdr_t));
  814. }
  815. } else {
  816. if (ether_type == htons(ETHERTYPE_8021Q)) {
  817. nbuf_clone = qdf_nbuf_clone(nbuf);
  818. qdf_nbuf_pull_head(nbuf_clone,
  819. sizeof(qdf_net_vlanhdr_t));
  820. }
  821. }
  822. if (qdf_unlikely(nbuf_clone))
  823. nbuf = nbuf_clone;
  824. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  825. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  826. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  827. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  828. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  829. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  830. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  831. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  832. if (qdf_unlikely(nbuf_clone != NULL))
  833. qdf_nbuf_free(nbuf_clone);
  834. return true;
  835. }
  836. if (qdf_unlikely(nbuf_clone != NULL))
  837. qdf_nbuf_free(nbuf_clone);
  838. return false;
  839. }
  840. /**
  841. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  842. * @vdev: DP vdev handle
  843. * @nbuf: skb
  844. *
  845. * Extract the DSCP or PCP information from frame and map into TID value.
  846. * Software based TID classification is required when more than 2 DSCP-TID
  847. * mapping tables are needed.
  848. * Hardware supports 2 DSCP-TID mapping tables
  849. *
  850. * Return: void
  851. */
  852. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  853. struct dp_tx_msdu_info_s *msdu_info)
  854. {
  855. uint8_t tos = 0, dscp_tid_override = 0;
  856. uint8_t *hdr_ptr, *L3datap;
  857. uint8_t is_mcast = 0;
  858. struct ether_header *eh = NULL;
  859. qdf_ethervlan_header_t *evh = NULL;
  860. uint16_t ether_type;
  861. qdf_llc_t *llcHdr;
  862. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  863. /* for mesh packets don't do any classification */
  864. if (qdf_unlikely(vdev->mesh_vdev))
  865. return;
  866. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  867. eh = (struct ether_header *) nbuf->data;
  868. hdr_ptr = eh->ether_dhost;
  869. L3datap = hdr_ptr + sizeof(struct ether_header);
  870. } else {
  871. qdf_dot3_qosframe_t *qos_wh =
  872. (qdf_dot3_qosframe_t *) nbuf->data;
  873. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  874. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  875. return;
  876. }
  877. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  878. ether_type = eh->ether_type;
  879. /*
  880. * Check if packet is dot3 or eth2 type.
  881. */
  882. if (IS_LLC_PRESENT(ether_type)) {
  883. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  884. sizeof(*llcHdr));
  885. if (ether_type == htons(ETHERTYPE_8021Q)) {
  886. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  887. sizeof(*llcHdr);
  888. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  889. + sizeof(*llcHdr) +
  890. sizeof(qdf_net_vlanhdr_t));
  891. } else {
  892. L3datap = hdr_ptr + sizeof(struct ether_header) +
  893. sizeof(*llcHdr);
  894. }
  895. } else {
  896. if (ether_type == htons(ETHERTYPE_8021Q)) {
  897. evh = (qdf_ethervlan_header_t *) eh;
  898. ether_type = evh->ether_type;
  899. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  900. }
  901. }
  902. /*
  903. * Find priority from IP TOS DSCP field
  904. */
  905. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  906. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  907. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  908. /* Only for unicast frames */
  909. if (!is_mcast) {
  910. /* send it on VO queue */
  911. msdu_info->tid = DP_VO_TID;
  912. }
  913. } else {
  914. /*
  915. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  916. * from TOS byte.
  917. */
  918. tos = ip->ip_tos;
  919. dscp_tid_override = 1;
  920. }
  921. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  922. /* TODO
  923. * use flowlabel
  924. *igmpmld cases to be handled in phase 2
  925. */
  926. unsigned long ver_pri_flowlabel;
  927. unsigned long pri;
  928. ver_pri_flowlabel = *(unsigned long *) L3datap;
  929. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  930. DP_IPV6_PRIORITY_SHIFT;
  931. tos = pri;
  932. dscp_tid_override = 1;
  933. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  934. msdu_info->tid = DP_VO_TID;
  935. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  936. /* Only for unicast frames */
  937. if (!is_mcast) {
  938. /* send ucast arp on VO queue */
  939. msdu_info->tid = DP_VO_TID;
  940. }
  941. }
  942. /*
  943. * Assign all MCAST packets to BE
  944. */
  945. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  946. if (is_mcast) {
  947. tos = 0;
  948. dscp_tid_override = 1;
  949. }
  950. }
  951. if (dscp_tid_override == 1) {
  952. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  953. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  954. }
  955. return;
  956. }
  957. #ifdef CONVERGED_TDLS_ENABLE
  958. /**
  959. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  960. * @tx_desc: TX descriptor
  961. *
  962. * Return: None
  963. */
  964. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  965. {
  966. if (tx_desc->vdev) {
  967. if (tx_desc->vdev->is_tdls_frame)
  968. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  969. tx_desc->vdev->is_tdls_frame = false;
  970. }
  971. }
  972. /**
  973. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  974. * @tx_desc: TX descriptor
  975. * @vdev: datapath vdev handle
  976. *
  977. * Return: None
  978. */
  979. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  980. struct dp_vdev *vdev)
  981. {
  982. struct hal_tx_completion_status ts = {0};
  983. qdf_nbuf_t nbuf = tx_desc->nbuf;
  984. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  985. if (vdev->tx_non_std_data_callback.func) {
  986. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  987. vdev->tx_non_std_data_callback.func(
  988. vdev->tx_non_std_data_callback.ctxt,
  989. nbuf, ts.status);
  990. return;
  991. }
  992. }
  993. #endif
  994. /**
  995. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  996. * @vdev: DP vdev handle
  997. * @nbuf: skb
  998. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  999. * @tx_q: Tx queue to be used for this Tx frame
  1000. * @peer_id: peer_id of the peer in case of NAWDS frames
  1001. *
  1002. * Return: NULL on success,
  1003. * nbuf when it fails to send
  1004. */
  1005. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1006. uint8_t tid, struct dp_tx_queue *tx_q,
  1007. uint32_t *meta_data, uint16_t peer_id)
  1008. {
  1009. struct dp_pdev *pdev = vdev->pdev;
  1010. struct dp_soc *soc = pdev->soc;
  1011. struct dp_tx_desc_s *tx_desc;
  1012. QDF_STATUS status;
  1013. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1014. uint16_t htt_tcl_metadata = 0;
  1015. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  1016. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1017. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  1018. if (!tx_desc) {
  1019. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1020. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1021. __func__, vdev, tx_q->desc_pool_id);
  1022. return nbuf;
  1023. }
  1024. if (qdf_unlikely(soc->cce_disable)) {
  1025. if (dp_cce_classify(vdev, nbuf) == true) {
  1026. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1027. tid = DP_VO_TID;
  1028. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1029. }
  1030. }
  1031. dp_tx_update_tdls_flags(tx_desc);
  1032. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1033. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1034. "%s %d : HAL RING Access Failed -- %pK\n",
  1035. __func__, __LINE__, hal_srng);
  1036. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1037. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1038. goto fail_return;
  1039. }
  1040. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1041. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1042. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1043. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1044. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1045. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1046. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1047. peer_id);
  1048. } else
  1049. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1050. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1051. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1052. htt_tcl_metadata, tx_q->ring_id);
  1053. if (status != QDF_STATUS_SUCCESS) {
  1054. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1055. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1056. __func__, tx_desc, tx_q->ring_id);
  1057. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1058. goto fail_return;
  1059. }
  1060. nbuf = NULL;
  1061. fail_return:
  1062. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1063. hal_srng_access_end(soc->hal_soc, hal_srng);
  1064. hif_pm_runtime_put(soc->hif_handle);
  1065. } else {
  1066. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1067. }
  1068. return nbuf;
  1069. }
  1070. /**
  1071. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1072. * @vdev: DP vdev handle
  1073. * @nbuf: skb
  1074. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1075. *
  1076. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1077. *
  1078. * Return: NULL on success,
  1079. * nbuf when it fails to send
  1080. */
  1081. #if QDF_LOCK_STATS
  1082. static noinline
  1083. #else
  1084. static
  1085. #endif
  1086. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1087. struct dp_tx_msdu_info_s *msdu_info)
  1088. {
  1089. uint8_t i;
  1090. struct dp_pdev *pdev = vdev->pdev;
  1091. struct dp_soc *soc = pdev->soc;
  1092. struct dp_tx_desc_s *tx_desc;
  1093. bool is_cce_classified = false;
  1094. QDF_STATUS status;
  1095. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1096. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1097. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1098. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1099. "%s %d : HAL RING Access Failed -- %pK\n",
  1100. __func__, __LINE__, hal_srng);
  1101. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1102. return nbuf;
  1103. }
  1104. if (qdf_unlikely(soc->cce_disable)) {
  1105. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1106. if (is_cce_classified) {
  1107. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1108. msdu_info->tid = DP_VO_TID;
  1109. }
  1110. }
  1111. if (msdu_info->frm_type == dp_tx_frm_me)
  1112. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1113. i = 0;
  1114. /* Print statement to track i and num_seg */
  1115. /*
  1116. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1117. * descriptors using information in msdu_info
  1118. */
  1119. while (i < msdu_info->num_seg) {
  1120. /*
  1121. * Setup Tx descriptor for an MSDU, and MSDU extension
  1122. * descriptor
  1123. */
  1124. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1125. tx_q->desc_pool_id);
  1126. if (!tx_desc) {
  1127. if (msdu_info->frm_type == dp_tx_frm_me) {
  1128. dp_tx_me_free_buf(pdev,
  1129. (void *)(msdu_info->u.sg_info
  1130. .curr_seg->frags[0].vaddr));
  1131. }
  1132. goto done;
  1133. }
  1134. if (msdu_info->frm_type == dp_tx_frm_me) {
  1135. tx_desc->me_buffer =
  1136. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1137. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1138. }
  1139. if (is_cce_classified)
  1140. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1141. /*
  1142. * Enqueue the Tx MSDU descriptor to HW for transmit
  1143. */
  1144. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1145. vdev->htt_tcl_metadata, tx_q->ring_id);
  1146. if (status != QDF_STATUS_SUCCESS) {
  1147. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1148. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1149. __func__, tx_desc, tx_q->ring_id);
  1150. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1151. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1152. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1153. goto done;
  1154. }
  1155. /*
  1156. * TODO
  1157. * if tso_info structure can be modified to have curr_seg
  1158. * as first element, following 2 blocks of code (for TSO and SG)
  1159. * can be combined into 1
  1160. */
  1161. /*
  1162. * For frames with multiple segments (TSO, ME), jump to next
  1163. * segment.
  1164. */
  1165. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1166. if (msdu_info->u.tso_info.curr_seg->next) {
  1167. msdu_info->u.tso_info.curr_seg =
  1168. msdu_info->u.tso_info.curr_seg->next;
  1169. /*
  1170. * If this is a jumbo nbuf, then increment the number of
  1171. * nbuf users for each additional segment of the msdu.
  1172. * This will ensure that the skb is freed only after
  1173. * receiving tx completion for all segments of an nbuf
  1174. */
  1175. qdf_nbuf_inc_users(nbuf);
  1176. /* Check with MCL if this is needed */
  1177. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1178. }
  1179. }
  1180. /*
  1181. * For Multicast-Unicast converted packets,
  1182. * each converted frame (for a client) is represented as
  1183. * 1 segment
  1184. */
  1185. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1186. (msdu_info->frm_type == dp_tx_frm_me)) {
  1187. if (msdu_info->u.sg_info.curr_seg->next) {
  1188. msdu_info->u.sg_info.curr_seg =
  1189. msdu_info->u.sg_info.curr_seg->next;
  1190. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1191. }
  1192. }
  1193. i++;
  1194. }
  1195. nbuf = NULL;
  1196. done:
  1197. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1198. hal_srng_access_end(soc->hal_soc, hal_srng);
  1199. hif_pm_runtime_put(soc->hif_handle);
  1200. } else {
  1201. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1202. }
  1203. return nbuf;
  1204. }
  1205. /**
  1206. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1207. * for SG frames
  1208. * @vdev: DP vdev handle
  1209. * @nbuf: skb
  1210. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1211. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1212. *
  1213. * Return: NULL on success,
  1214. * nbuf when it fails to send
  1215. */
  1216. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1217. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1218. {
  1219. uint32_t cur_frag, nr_frags;
  1220. qdf_dma_addr_t paddr;
  1221. struct dp_tx_sg_info_s *sg_info;
  1222. sg_info = &msdu_info->u.sg_info;
  1223. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1224. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1225. QDF_DMA_TO_DEVICE)) {
  1226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1227. "dma map error\n");
  1228. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1229. qdf_nbuf_free(nbuf);
  1230. return NULL;
  1231. }
  1232. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1233. seg_info->frags[0].paddr_lo = paddr;
  1234. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1235. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1236. seg_info->frags[0].vaddr = (void *) nbuf;
  1237. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1238. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1239. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1240. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1241. "frag dma map error\n");
  1242. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1243. qdf_nbuf_free(nbuf);
  1244. return NULL;
  1245. }
  1246. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1247. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1248. seg_info->frags[cur_frag + 1].paddr_hi =
  1249. ((uint64_t) paddr) >> 32;
  1250. seg_info->frags[cur_frag + 1].len =
  1251. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1252. }
  1253. seg_info->frag_cnt = (cur_frag + 1);
  1254. seg_info->total_len = qdf_nbuf_len(nbuf);
  1255. seg_info->next = NULL;
  1256. sg_info->curr_seg = seg_info;
  1257. msdu_info->frm_type = dp_tx_frm_sg;
  1258. msdu_info->num_seg = 1;
  1259. return nbuf;
  1260. }
  1261. #ifdef MESH_MODE_SUPPORT
  1262. /**
  1263. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1264. and prepare msdu_info for mesh frames.
  1265. * @vdev: DP vdev handle
  1266. * @nbuf: skb
  1267. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1268. *
  1269. * Return: NULL on failure,
  1270. * nbuf when extracted successfully
  1271. */
  1272. static
  1273. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1274. struct dp_tx_msdu_info_s *msdu_info)
  1275. {
  1276. struct meta_hdr_s *mhdr;
  1277. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1278. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1279. nbuf = qdf_nbuf_unshare(nbuf);
  1280. if (nbuf == NULL) {
  1281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1282. "qdf_nbuf_unshare failed\n");
  1283. return nbuf;
  1284. }
  1285. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1286. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1287. meta_data->host_tx_desc_pool = 1;
  1288. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1289. meta_data->power = mhdr->power;
  1290. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1291. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1292. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1293. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1294. meta_data->dyn_bw = 1;
  1295. meta_data->valid_pwr = 1;
  1296. meta_data->valid_mcs_mask = 1;
  1297. meta_data->valid_nss_mask = 1;
  1298. meta_data->valid_preamble_type = 1;
  1299. meta_data->valid_retries = 1;
  1300. meta_data->valid_bw_info = 1;
  1301. }
  1302. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1303. meta_data->encrypt_type = 0;
  1304. meta_data->valid_encrypt_type = 1;
  1305. }
  1306. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1307. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1308. else
  1309. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1310. meta_data->valid_key_flags = 1;
  1311. meta_data->key_flags = (mhdr->keyix & 0x3);
  1312. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1313. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1314. "qdf_nbuf_pull_head failed\n");
  1315. qdf_nbuf_free(nbuf);
  1316. return NULL;
  1317. }
  1318. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1319. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1320. __func__, msdu_info->meta_data[0],
  1321. msdu_info->meta_data[1],
  1322. msdu_info->meta_data[2],
  1323. msdu_info->meta_data[3],
  1324. msdu_info->meta_data[4]);
  1325. return nbuf;
  1326. }
  1327. #else
  1328. static
  1329. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1330. struct dp_tx_msdu_info_s *msdu_info)
  1331. {
  1332. return nbuf;
  1333. }
  1334. #endif
  1335. #ifdef DP_FEATURE_NAWDS_TX
  1336. /**
  1337. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1338. * @vdev: dp_vdev handle
  1339. * @nbuf: skb
  1340. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1341. * @tx_q: Tx queue to be used for this Tx frame
  1342. * @meta_data: Meta date for mesh
  1343. * @peer_id: peer_id of the peer in case of NAWDS frames
  1344. *
  1345. * return: NULL on success nbuf on failure
  1346. */
  1347. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1348. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data)
  1349. {
  1350. struct dp_peer *peer = NULL;
  1351. struct dp_soc *soc = vdev->pdev->soc;
  1352. struct dp_ast_entry *ast_entry = NULL;
  1353. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1354. uint16_t peer_id = HTT_INVALID_PEER;
  1355. struct dp_peer *sa_peer = NULL;
  1356. qdf_nbuf_t nbuf_copy;
  1357. qdf_spin_lock_bh(&(soc->ast_lock));
  1358. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1359. if (ast_entry)
  1360. sa_peer = ast_entry->peer;
  1361. qdf_spin_unlock_bh(&(soc->ast_lock));
  1362. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1363. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1364. (peer->nawds_enabled)) {
  1365. if (sa_peer == peer) {
  1366. QDF_TRACE(QDF_MODULE_ID_DP,
  1367. QDF_TRACE_LEVEL_DEBUG,
  1368. " %s: broadcast multicast packet",
  1369. __func__);
  1370. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1371. continue;
  1372. }
  1373. nbuf_copy = qdf_nbuf_copy(nbuf);
  1374. if (!nbuf_copy) {
  1375. QDF_TRACE(QDF_MODULE_ID_DP,
  1376. QDF_TRACE_LEVEL_ERROR,
  1377. "nbuf copy failed");
  1378. }
  1379. peer_id = peer->peer_ids[0];
  1380. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1381. tx_q, meta_data, peer_id);
  1382. if (nbuf_copy != NULL) {
  1383. qdf_nbuf_free(nbuf_copy);
  1384. continue;
  1385. }
  1386. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1387. 1, qdf_nbuf_len(nbuf));
  1388. }
  1389. }
  1390. if (peer_id == HTT_INVALID_PEER)
  1391. return nbuf;
  1392. return NULL;
  1393. }
  1394. #endif
  1395. /**
  1396. * dp_tx_send() - Transmit a frame on a given VAP
  1397. * @vap_dev: DP vdev handle
  1398. * @nbuf: skb
  1399. *
  1400. * Entry point for Core Tx layer (DP_TX) invoked from
  1401. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1402. * cases
  1403. *
  1404. * Return: NULL on success,
  1405. * nbuf when it fails to send
  1406. */
  1407. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1408. {
  1409. struct ether_header *eh = NULL;
  1410. struct dp_tx_msdu_info_s msdu_info;
  1411. struct dp_tx_seg_info_s seg_info;
  1412. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1413. uint16_t peer_id = HTT_INVALID_PEER;
  1414. qdf_nbuf_t nbuf_mesh = NULL;
  1415. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1416. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1417. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1418. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1419. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1420. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1421. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1422. /*
  1423. * Set Default Host TID value to invalid TID
  1424. * (TID override disabled)
  1425. */
  1426. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1427. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1428. if (qdf_unlikely(vdev->mesh_vdev)) {
  1429. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1430. &msdu_info);
  1431. if (nbuf_mesh == NULL) {
  1432. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1433. "Extracting mesh metadata failed\n");
  1434. return nbuf;
  1435. }
  1436. nbuf = nbuf_mesh;
  1437. }
  1438. /*
  1439. * Get HW Queue to use for this frame.
  1440. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1441. * dedicated for data and 1 for command.
  1442. * "queue_id" maps to one hardware ring.
  1443. * With each ring, we also associate a unique Tx descriptor pool
  1444. * to minimize lock contention for these resources.
  1445. */
  1446. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1447. /*
  1448. * TCL H/W supports 2 DSCP-TID mapping tables.
  1449. * Table 1 - Default DSCP-TID mapping table
  1450. * Table 2 - 1 DSCP-TID override table
  1451. *
  1452. * If we need a different DSCP-TID mapping for this vap,
  1453. * call tid_classify to extract DSCP/ToS from frame and
  1454. * map to a TID and store in msdu_info. This is later used
  1455. * to fill in TCL Input descriptor (per-packet TID override).
  1456. */
  1457. if (vdev->dscp_tid_map_id > 1)
  1458. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1459. /* Reset the control block */
  1460. qdf_nbuf_reset_ctxt(nbuf);
  1461. /*
  1462. * Classify the frame and call corresponding
  1463. * "prepare" function which extracts the segment (TSO)
  1464. * and fragmentation information (for TSO , SG, ME, or Raw)
  1465. * into MSDU_INFO structure which is later used to fill
  1466. * SW and HW descriptors.
  1467. */
  1468. if (qdf_nbuf_is_tso(nbuf)) {
  1469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1470. "%s TSO frame %pK\n", __func__, vdev);
  1471. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1472. qdf_nbuf_len(nbuf));
  1473. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1474. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1475. return nbuf;
  1476. }
  1477. goto send_multiple;
  1478. }
  1479. /* SG */
  1480. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1481. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1483. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1484. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1485. qdf_nbuf_len(nbuf));
  1486. goto send_multiple;
  1487. }
  1488. #ifdef ATH_SUPPORT_IQUE
  1489. /* Mcast to Ucast Conversion*/
  1490. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1491. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1492. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1493. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1494. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1495. DP_STATS_INC_PKT(vdev,
  1496. tx_i.mcast_en.mcast_pkt, 1,
  1497. qdf_nbuf_len(nbuf));
  1498. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1499. qdf_nbuf_free(nbuf);
  1500. return NULL;
  1501. }
  1502. return nbuf;
  1503. }
  1504. }
  1505. #endif
  1506. /* RAW */
  1507. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1508. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1509. if (nbuf == NULL)
  1510. return NULL;
  1511. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1512. "%s Raw frame %pK\n", __func__, vdev);
  1513. goto send_multiple;
  1514. }
  1515. /* Single linear frame */
  1516. /*
  1517. * If nbuf is a simple linear frame, use send_single function to
  1518. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1519. * SRNG. There is no need to setup a MSDU extension descriptor.
  1520. */
  1521. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1522. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1523. return nbuf;
  1524. send_multiple:
  1525. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1526. return nbuf;
  1527. }
  1528. /**
  1529. * dp_tx_reinject_handler() - Tx Reinject Handler
  1530. * @tx_desc: software descriptor head pointer
  1531. * @status : Tx completion status from HTT descriptor
  1532. *
  1533. * This function reinjects frames back to Target.
  1534. * Todo - Host queue needs to be added
  1535. *
  1536. * Return: none
  1537. */
  1538. static
  1539. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1540. {
  1541. struct dp_vdev *vdev;
  1542. struct dp_peer *peer = NULL;
  1543. uint32_t peer_id = HTT_INVALID_PEER;
  1544. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1545. qdf_nbuf_t nbuf_copy = NULL;
  1546. struct dp_tx_msdu_info_s msdu_info;
  1547. struct dp_peer *sa_peer = NULL;
  1548. struct dp_ast_entry *ast_entry = NULL;
  1549. struct dp_soc *soc = NULL;
  1550. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1551. #ifdef WDS_VENDOR_EXTENSION
  1552. int is_mcast = 0, is_ucast = 0;
  1553. int num_peers_3addr = 0;
  1554. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1555. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1556. #endif
  1557. vdev = tx_desc->vdev;
  1558. soc = vdev->pdev->soc;
  1559. qdf_assert(vdev);
  1560. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1561. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1562. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1563. "%s Tx reinject path\n", __func__);
  1564. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1565. qdf_nbuf_len(tx_desc->nbuf));
  1566. qdf_spin_lock_bh(&(soc->ast_lock));
  1567. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1568. if (ast_entry)
  1569. sa_peer = ast_entry->peer;
  1570. qdf_spin_unlock_bh(&(soc->ast_lock));
  1571. #ifdef WDS_VENDOR_EXTENSION
  1572. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1573. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1574. } else {
  1575. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1576. }
  1577. is_ucast = !is_mcast;
  1578. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1579. if (peer->bss_peer)
  1580. continue;
  1581. /* Detect wds peers that use 3-addr framing for mcast.
  1582. * if there are any, the bss_peer is used to send the
  1583. * the mcast frame using 3-addr format. all wds enabled
  1584. * peers that use 4-addr framing for mcast frames will
  1585. * be duplicated and sent as 4-addr frames below.
  1586. */
  1587. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1588. num_peers_3addr = 1;
  1589. break;
  1590. }
  1591. }
  1592. #endif
  1593. if (qdf_unlikely(vdev->mesh_vdev)) {
  1594. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1595. } else {
  1596. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1597. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1598. #ifdef WDS_VENDOR_EXTENSION
  1599. /*
  1600. * . if 3-addr STA, then send on BSS Peer
  1601. * . if Peer WDS enabled and accept 4-addr mcast,
  1602. * send mcast on that peer only
  1603. * . if Peer WDS enabled and accept 4-addr ucast,
  1604. * send ucast on that peer only
  1605. */
  1606. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1607. (peer->wds_enabled &&
  1608. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1609. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1610. #else
  1611. ((peer->bss_peer &&
  1612. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1613. peer->nawds_enabled)) {
  1614. #endif
  1615. peer_id = DP_INVALID_PEER;
  1616. if (peer->nawds_enabled) {
  1617. peer_id = peer->peer_ids[0];
  1618. if (sa_peer == peer) {
  1619. QDF_TRACE(
  1620. QDF_MODULE_ID_DP,
  1621. QDF_TRACE_LEVEL_DEBUG,
  1622. " %s: multicast packet",
  1623. __func__);
  1624. DP_STATS_INC(peer,
  1625. tx.nawds_mcast_drop, 1);
  1626. continue;
  1627. }
  1628. }
  1629. nbuf_copy = qdf_nbuf_copy(nbuf);
  1630. if (!nbuf_copy) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP,
  1632. QDF_TRACE_LEVEL_DEBUG,
  1633. FL("nbuf copy failed"));
  1634. break;
  1635. }
  1636. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1637. nbuf_copy,
  1638. msdu_info.tid,
  1639. &msdu_info.tx_queue,
  1640. msdu_info.meta_data,
  1641. peer_id);
  1642. if (nbuf_copy) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP,
  1644. QDF_TRACE_LEVEL_DEBUG,
  1645. FL("pkt send failed"));
  1646. qdf_nbuf_free(nbuf_copy);
  1647. } else {
  1648. if (peer_id != DP_INVALID_PEER)
  1649. DP_STATS_INC_PKT(peer,
  1650. tx.nawds_mcast,
  1651. 1, qdf_nbuf_len(nbuf));
  1652. }
  1653. }
  1654. }
  1655. }
  1656. if (vdev->nawds_enabled) {
  1657. peer_id = DP_INVALID_PEER;
  1658. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1659. 1, qdf_nbuf_len(nbuf));
  1660. nbuf = dp_tx_send_msdu_single(vdev,
  1661. nbuf, msdu_info.tid,
  1662. &msdu_info.tx_queue,
  1663. msdu_info.meta_data, peer_id);
  1664. if (nbuf) {
  1665. QDF_TRACE(QDF_MODULE_ID_DP,
  1666. QDF_TRACE_LEVEL_DEBUG,
  1667. FL("pkt send failed"));
  1668. qdf_nbuf_free(nbuf);
  1669. }
  1670. } else
  1671. qdf_nbuf_free(nbuf);
  1672. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1673. }
  1674. /**
  1675. * dp_tx_inspect_handler() - Tx Inspect Handler
  1676. * @tx_desc: software descriptor head pointer
  1677. * @status : Tx completion status from HTT descriptor
  1678. *
  1679. * Handles Tx frames sent back to Host for inspection
  1680. * (ProxyARP)
  1681. *
  1682. * Return: none
  1683. */
  1684. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1685. {
  1686. struct dp_soc *soc;
  1687. struct dp_pdev *pdev = tx_desc->pdev;
  1688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1689. "%s Tx inspect path\n",
  1690. __func__);
  1691. qdf_assert(pdev);
  1692. soc = pdev->soc;
  1693. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1694. qdf_nbuf_len(tx_desc->nbuf));
  1695. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1696. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1697. }
  1698. #ifdef FEATURE_PERPKT_INFO
  1699. QDF_STATUS
  1700. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1701. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1702. {
  1703. struct tx_capture_hdr *ppdu_hdr;
  1704. struct dp_peer *peer = NULL;
  1705. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->am_copy_mode))
  1706. return QDF_STATUS_E_NOSUPPORT;
  1707. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1708. dp_peer_find_by_id(soc, peer_id);
  1709. if (!peer) {
  1710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1711. FL("Peer Invalid"));
  1712. return QDF_STATUS_E_INVAL;
  1713. }
  1714. if (pdev->am_copy_mode) {
  1715. if ((pdev->am_copy_id.tx_ppdu_id == ppdu_id) &&
  1716. (pdev->am_copy_id.tx_peer_id == peer_id)) {
  1717. return QDF_STATUS_E_INVAL;
  1718. }
  1719. pdev->am_copy_id.tx_ppdu_id = ppdu_id;
  1720. pdev->am_copy_id.tx_peer_id = peer_id;
  1721. }
  1722. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1724. FL("No headroom"));
  1725. return QDF_STATUS_E_NOMEM;
  1726. }
  1727. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1728. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1729. IEEE80211_ADDR_LEN);
  1730. ppdu_hdr->ppdu_id = ppdu_id;
  1731. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1732. IEEE80211_ADDR_LEN);
  1733. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1734. netbuf, peer_id,
  1735. WDI_NO_VAL, pdev->pdev_id);
  1736. return QDF_STATUS_SUCCESS;
  1737. }
  1738. #else
  1739. static QDF_STATUS
  1740. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1741. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1742. {
  1743. return QDF_STATUS_E_NOSUPPORT;
  1744. }
  1745. #endif
  1746. /**
  1747. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1748. * @soc: Soc handle
  1749. * @desc: software Tx descriptor to be processed
  1750. *
  1751. * Return: none
  1752. */
  1753. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1754. struct dp_tx_desc_s *desc)
  1755. {
  1756. struct dp_vdev *vdev = desc->vdev;
  1757. qdf_nbuf_t nbuf = desc->nbuf;
  1758. struct hal_tx_completion_status ts = {0};
  1759. if (desc)
  1760. hal_tx_comp_get_status(&desc->comp, &ts);
  1761. /* If it is TDLS mgmt, don't unmap or free the frame */
  1762. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1763. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1764. /* 0 : MSDU buffer, 1 : MLE */
  1765. if (desc->msdu_ext_desc) {
  1766. /* TSO free */
  1767. if (hal_tx_ext_desc_get_tso_enable(
  1768. desc->msdu_ext_desc->vaddr)) {
  1769. /* If remaining number of segment is 0
  1770. * actual TSO may unmap and free */
  1771. if (!DP_DESC_NUM_FRAG(desc)) {
  1772. qdf_nbuf_unmap(soc->osdev, nbuf,
  1773. QDF_DMA_TO_DEVICE);
  1774. qdf_nbuf_free(nbuf);
  1775. return;
  1776. }
  1777. }
  1778. }
  1779. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1780. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1781. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1782. if (dp_send_compl_to_stack(soc, desc->pdev, ts.peer_id,
  1783. ts.ppdu_id, nbuf) == QDF_STATUS_SUCCESS)
  1784. return;
  1785. if (!vdev->mesh_vdev) {
  1786. qdf_nbuf_free(nbuf);
  1787. } else {
  1788. vdev->osif_tx_free_ext((nbuf));
  1789. }
  1790. }
  1791. /**
  1792. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1793. * @vdev: pointer to dp dev handler
  1794. * @status : Tx completion status from HTT descriptor
  1795. *
  1796. * Handles MEC notify event sent from fw to Host
  1797. *
  1798. * Return: none
  1799. */
  1800. #ifdef FEATURE_WDS
  1801. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1802. {
  1803. struct dp_soc *soc;
  1804. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1805. struct dp_peer *peer;
  1806. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1807. soc = vdev->pdev->soc;
  1808. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1809. peer = TAILQ_FIRST(&vdev->peer_list);
  1810. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1811. if (!peer) {
  1812. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1813. FL("peer is NULL"));
  1814. return;
  1815. }
  1816. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1817. "%s Tx MEC Handler\n",
  1818. __func__);
  1819. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1820. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1821. status[(DP_MAC_ADDR_LEN - 2) + i];
  1822. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1823. !dp_peer_add_ast(soc, peer, mac_addr, dp_ast_type_mec)) {
  1824. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1825. vdev->osif_vdev,
  1826. mac_addr,
  1827. vdev->mac_addr.raw,
  1828. flags);
  1829. }
  1830. }
  1831. #else
  1832. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1833. {
  1834. }
  1835. #endif
  1836. /**
  1837. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1838. * @tx_desc: software descriptor head pointer
  1839. * @status : Tx completion status from HTT descriptor
  1840. *
  1841. * This function will process HTT Tx indication messages from Target
  1842. *
  1843. * Return: none
  1844. */
  1845. static
  1846. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1847. {
  1848. uint8_t tx_status;
  1849. struct dp_pdev *pdev;
  1850. struct dp_vdev *vdev;
  1851. struct dp_soc *soc;
  1852. uint32_t *htt_status_word = (uint32_t *) status;
  1853. qdf_assert(tx_desc->pdev);
  1854. pdev = tx_desc->pdev;
  1855. vdev = tx_desc->vdev;
  1856. soc = pdev->soc;
  1857. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1858. switch (tx_status) {
  1859. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1860. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1861. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1862. {
  1863. dp_tx_comp_free_buf(soc, tx_desc);
  1864. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1865. break;
  1866. }
  1867. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1868. {
  1869. dp_tx_reinject_handler(tx_desc, status);
  1870. break;
  1871. }
  1872. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1873. {
  1874. dp_tx_inspect_handler(tx_desc, status);
  1875. break;
  1876. }
  1877. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1878. {
  1879. dp_tx_mec_handler(vdev, status);
  1880. break;
  1881. }
  1882. default:
  1883. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1884. "%s Invalid HTT tx_status %d\n",
  1885. __func__, tx_status);
  1886. break;
  1887. }
  1888. }
  1889. #ifdef MESH_MODE_SUPPORT
  1890. /**
  1891. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1892. * in mesh meta header
  1893. * @tx_desc: software descriptor head pointer
  1894. * @ts: pointer to tx completion stats
  1895. * Return: none
  1896. */
  1897. static
  1898. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1899. struct hal_tx_completion_status *ts)
  1900. {
  1901. struct meta_hdr_s *mhdr;
  1902. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1903. if (!tx_desc->msdu_ext_desc) {
  1904. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1906. "netbuf %pK offset %d\n",
  1907. netbuf, tx_desc->pkt_offset);
  1908. return;
  1909. }
  1910. }
  1911. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1913. "netbuf %pK offset %d\n", netbuf,
  1914. sizeof(struct meta_hdr_s));
  1915. return;
  1916. }
  1917. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1918. mhdr->rssi = ts->ack_frame_rssi;
  1919. mhdr->channel = tx_desc->pdev->operating_channel;
  1920. }
  1921. #else
  1922. static
  1923. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1924. struct hal_tx_completion_status *ts)
  1925. {
  1926. }
  1927. #endif
  1928. /**
  1929. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1930. * @peer: Handle to DP peer
  1931. * @ts: pointer to HAL Tx completion stats
  1932. * @length: MSDU length
  1933. *
  1934. * Return: None
  1935. */
  1936. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1937. struct hal_tx_completion_status *ts, uint32_t length)
  1938. {
  1939. struct dp_pdev *pdev = peer->vdev->pdev;
  1940. struct dp_soc *soc = pdev->soc;
  1941. uint8_t mcs, pkt_type;
  1942. mcs = ts->mcs;
  1943. pkt_type = ts->pkt_type;
  1944. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1945. return;
  1946. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1947. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1948. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1949. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1950. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1951. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1952. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1953. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1954. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1955. return;
  1956. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1957. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1958. if (!(soc->process_tx_status))
  1959. return;
  1960. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1961. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  1962. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1963. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  1964. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1965. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1966. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1967. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1968. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1969. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1970. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1971. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1972. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1973. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1974. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1975. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1976. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1977. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1978. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1979. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1980. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1981. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1982. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1983. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1984. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1985. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1986. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1987. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1988. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1989. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1990. &peer->stats, ts->peer_id,
  1991. UPDATE_PEER_STATS);
  1992. }
  1993. }
  1994. /**
  1995. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1996. * @tx_desc: software descriptor head pointer
  1997. * @length: packet length
  1998. *
  1999. * Return: none
  2000. */
  2001. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2002. uint32_t length)
  2003. {
  2004. struct hal_tx_completion_status ts;
  2005. struct dp_soc *soc = NULL;
  2006. struct dp_vdev *vdev = tx_desc->vdev;
  2007. struct dp_peer *peer = NULL;
  2008. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2009. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2010. "-------------------- \n"
  2011. "Tx Completion Stats: \n"
  2012. "-------------------- \n"
  2013. "ack_frame_rssi = %d \n"
  2014. "first_msdu = %d \n"
  2015. "last_msdu = %d \n"
  2016. "msdu_part_of_amsdu = %d \n"
  2017. "rate_stats valid = %d \n"
  2018. "bw = %d \n"
  2019. "pkt_type = %d \n"
  2020. "stbc = %d \n"
  2021. "ldpc = %d \n"
  2022. "sgi = %d \n"
  2023. "mcs = %d \n"
  2024. "ofdma = %d \n"
  2025. "tones_in_ru = %d \n"
  2026. "tsf = %d \n"
  2027. "ppdu_id = %d \n"
  2028. "transmit_cnt = %d \n"
  2029. "tid = %d \n"
  2030. "peer_id = %d \n",
  2031. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2032. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2033. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2034. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2035. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2036. ts.peer_id);
  2037. if (!vdev) {
  2038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2039. "invalid vdev");
  2040. goto out;
  2041. }
  2042. soc = vdev->pdev->soc;
  2043. /* Update SoC level stats */
  2044. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2045. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2046. /* Update per-packet stats */
  2047. if (qdf_unlikely(vdev->mesh_vdev))
  2048. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2049. /* Update peer level stats */
  2050. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2051. if (!peer) {
  2052. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2053. "invalid peer");
  2054. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2055. goto out;
  2056. }
  2057. dp_tx_update_peer_stats(peer, &ts, length);
  2058. out:
  2059. return;
  2060. }
  2061. /**
  2062. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2063. * @soc: core txrx main context
  2064. * @comp_head: software descriptor head pointer
  2065. *
  2066. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2067. * and release the software descriptors after processing is complete
  2068. *
  2069. * Return: none
  2070. */
  2071. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2072. struct dp_tx_desc_s *comp_head)
  2073. {
  2074. struct dp_tx_desc_s *desc;
  2075. struct dp_tx_desc_s *next;
  2076. struct hal_tx_completion_status ts = {0};
  2077. uint32_t length;
  2078. struct dp_peer *peer;
  2079. DP_HIST_INIT();
  2080. desc = comp_head;
  2081. while (desc) {
  2082. hal_tx_comp_get_status(&desc->comp, &ts);
  2083. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2084. length = qdf_nbuf_len(desc->nbuf);
  2085. dp_tx_comp_process_tx_status(desc, length);
  2086. dp_tx_comp_free_buf(soc, desc);
  2087. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2088. next = desc->next;
  2089. dp_tx_desc_release(desc, desc->pool_id);
  2090. desc = next;
  2091. }
  2092. DP_TX_HIST_STATS_PER_PDEV();
  2093. }
  2094. /**
  2095. * dp_tx_comp_handler() - Tx completion handler
  2096. * @soc: core txrx main context
  2097. * @ring_id: completion ring id
  2098. * @quota: No. of packets/descriptors that can be serviced in one loop
  2099. *
  2100. * This function will collect hardware release ring element contents and
  2101. * handle descriptor contents. Based on contents, free packet or handle error
  2102. * conditions
  2103. *
  2104. * Return: none
  2105. */
  2106. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2107. {
  2108. void *tx_comp_hal_desc;
  2109. uint8_t buffer_src;
  2110. uint8_t pool_id;
  2111. uint32_t tx_desc_id;
  2112. struct dp_tx_desc_s *tx_desc = NULL;
  2113. struct dp_tx_desc_s *head_desc = NULL;
  2114. struct dp_tx_desc_s *tail_desc = NULL;
  2115. uint32_t num_processed;
  2116. uint32_t count;
  2117. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2118. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2119. "%s %d : HAL RING Access Failed -- %pK\n",
  2120. __func__, __LINE__, hal_srng);
  2121. return 0;
  2122. }
  2123. num_processed = 0;
  2124. count = 0;
  2125. /* Find head descriptor from completion ring */
  2126. while (qdf_likely(tx_comp_hal_desc =
  2127. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2128. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2129. /* If this buffer was not released by TQM or FW, then it is not
  2130. * Tx completion indication, assert */
  2131. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2132. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2133. QDF_TRACE(QDF_MODULE_ID_DP,
  2134. QDF_TRACE_LEVEL_FATAL,
  2135. "Tx comp release_src != TQM | FW");
  2136. qdf_assert_always(0);
  2137. }
  2138. /* Get descriptor id */
  2139. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2140. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2141. DP_TX_DESC_ID_POOL_OS;
  2142. /* Pool ID is out of limit. Error */
  2143. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2144. soc->wlan_cfg_ctx)) {
  2145. QDF_TRACE(QDF_MODULE_ID_DP,
  2146. QDF_TRACE_LEVEL_FATAL,
  2147. "Tx Comp pool id %d not valid",
  2148. pool_id);
  2149. qdf_assert_always(0);
  2150. }
  2151. /* Find Tx descriptor */
  2152. tx_desc = dp_tx_desc_find(soc, pool_id,
  2153. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2154. DP_TX_DESC_ID_PAGE_OS,
  2155. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2156. DP_TX_DESC_ID_OFFSET_OS);
  2157. /* Pool id is not matching. Error */
  2158. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  2159. QDF_TRACE(QDF_MODULE_ID_DP,
  2160. QDF_TRACE_LEVEL_FATAL,
  2161. "Tx Comp pool id %d not matched %d",
  2162. pool_id, tx_desc->pool_id);
  2163. qdf_assert_always(0);
  2164. }
  2165. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2166. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2167. QDF_TRACE(QDF_MODULE_ID_DP,
  2168. QDF_TRACE_LEVEL_FATAL,
  2169. "Txdesc invalid, flgs = %x,id = %d",
  2170. tx_desc->flags, tx_desc_id);
  2171. qdf_assert_always(0);
  2172. }
  2173. /*
  2174. * If the release source is FW, process the HTT status
  2175. */
  2176. if (qdf_unlikely(buffer_src ==
  2177. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2178. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2179. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2180. htt_tx_status);
  2181. dp_tx_process_htt_completion(tx_desc,
  2182. htt_tx_status);
  2183. } else {
  2184. /* First ring descriptor on the cycle */
  2185. if (!head_desc) {
  2186. head_desc = tx_desc;
  2187. tail_desc = tx_desc;
  2188. }
  2189. tail_desc->next = tx_desc;
  2190. tx_desc->next = NULL;
  2191. tail_desc = tx_desc;
  2192. /* Collect hw completion contents */
  2193. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2194. &tx_desc->comp, 1);
  2195. }
  2196. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2197. /* Decrement PM usage count if the packet has been sent.*/
  2198. hif_pm_runtime_put(soc->hif_handle);
  2199. /*
  2200. * Processed packet count is more than given quota
  2201. * stop to processing
  2202. */
  2203. if ((num_processed >= quota))
  2204. break;
  2205. count++;
  2206. }
  2207. hal_srng_access_end(soc->hal_soc, hal_srng);
  2208. /* Process the reaped descriptors */
  2209. if (head_desc)
  2210. dp_tx_comp_process_desc(soc, head_desc);
  2211. return num_processed;
  2212. }
  2213. #ifdef CONVERGED_TDLS_ENABLE
  2214. /**
  2215. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2216. *
  2217. * @data_vdev - which vdev should transmit the tx data frames
  2218. * @tx_spec - what non-standard handling to apply to the tx data frames
  2219. * @msdu_list - NULL-terminated list of tx MSDUs
  2220. *
  2221. * Return: NULL on success,
  2222. * nbuf when it fails to send
  2223. */
  2224. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2225. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2226. {
  2227. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2228. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2229. vdev->is_tdls_frame = true;
  2230. return dp_tx_send(vdev_handle, msdu_list);
  2231. }
  2232. #endif
  2233. /**
  2234. * dp_tx_vdev_attach() - attach vdev to dp tx
  2235. * @vdev: virtual device instance
  2236. *
  2237. * Return: QDF_STATUS_SUCCESS: success
  2238. * QDF_STATUS_E_RESOURCES: Error return
  2239. */
  2240. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2241. {
  2242. /*
  2243. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2244. */
  2245. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2246. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2247. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2248. vdev->vdev_id);
  2249. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2250. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2251. /*
  2252. * Set HTT Extension Valid bit to 0 by default
  2253. */
  2254. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2255. dp_tx_vdev_update_search_flags(vdev);
  2256. return QDF_STATUS_SUCCESS;
  2257. }
  2258. /**
  2259. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2260. * @vdev: virtual device instance
  2261. *
  2262. * Return: void
  2263. *
  2264. */
  2265. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2266. {
  2267. /*
  2268. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2269. * for TDLS link
  2270. *
  2271. * Enable AddrY (SA based search) only for non-WDS STA and
  2272. * ProxySTA VAP modes.
  2273. *
  2274. * In all other VAP modes, only DA based search should be
  2275. * enabled
  2276. */
  2277. if (vdev->opmode == wlan_op_mode_sta &&
  2278. vdev->tdls_link_connected)
  2279. vdev->hal_desc_addr_search_flags =
  2280. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2281. else if ((vdev->opmode == wlan_op_mode_sta &&
  2282. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2283. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2284. else
  2285. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2286. }
  2287. /**
  2288. * dp_tx_vdev_detach() - detach vdev from dp tx
  2289. * @vdev: virtual device instance
  2290. *
  2291. * Return: QDF_STATUS_SUCCESS: success
  2292. * QDF_STATUS_E_RESOURCES: Error return
  2293. */
  2294. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2295. {
  2296. return QDF_STATUS_SUCCESS;
  2297. }
  2298. /**
  2299. * dp_tx_pdev_attach() - attach pdev to dp tx
  2300. * @pdev: physical device instance
  2301. *
  2302. * Return: QDF_STATUS_SUCCESS: success
  2303. * QDF_STATUS_E_RESOURCES: Error return
  2304. */
  2305. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2306. {
  2307. struct dp_soc *soc = pdev->soc;
  2308. /* Initialize Flow control counters */
  2309. qdf_atomic_init(&pdev->num_tx_exception);
  2310. qdf_atomic_init(&pdev->num_tx_outstanding);
  2311. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2312. /* Initialize descriptors in TCL Ring */
  2313. hal_tx_init_data_ring(soc->hal_soc,
  2314. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2315. }
  2316. return QDF_STATUS_SUCCESS;
  2317. }
  2318. /**
  2319. * dp_tx_pdev_detach() - detach pdev from dp tx
  2320. * @pdev: physical device instance
  2321. *
  2322. * Return: QDF_STATUS_SUCCESS: success
  2323. * QDF_STATUS_E_RESOURCES: Error return
  2324. */
  2325. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2326. {
  2327. /* What should do here? */
  2328. return QDF_STATUS_SUCCESS;
  2329. }
  2330. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2331. /* Pools will be allocated dynamically */
  2332. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2333. int num_desc)
  2334. {
  2335. uint8_t i;
  2336. for (i = 0; i < num_pool; i++) {
  2337. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2338. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2339. }
  2340. return 0;
  2341. }
  2342. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2343. {
  2344. uint8_t i;
  2345. for (i = 0; i < num_pool; i++)
  2346. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2347. }
  2348. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2349. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2350. int num_desc)
  2351. {
  2352. uint8_t i;
  2353. /* Allocate software Tx descriptor pools */
  2354. for (i = 0; i < num_pool; i++) {
  2355. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2356. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2357. "%s Tx Desc Pool alloc %d failed %pK\n",
  2358. __func__, i, soc);
  2359. return ENOMEM;
  2360. }
  2361. }
  2362. return 0;
  2363. }
  2364. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2365. {
  2366. uint8_t i;
  2367. for (i = 0; i < num_pool; i++) {
  2368. if (dp_tx_desc_pool_free(soc, i)) {
  2369. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2370. "%s Tx Desc Pool Free failed\n", __func__);
  2371. }
  2372. }
  2373. }
  2374. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2375. /**
  2376. * dp_tx_soc_detach() - detach soc from dp tx
  2377. * @soc: core txrx main context
  2378. *
  2379. * This function will detach dp tx into main device context
  2380. * will free dp tx resource and initialize resources
  2381. *
  2382. * Return: QDF_STATUS_SUCCESS: success
  2383. * QDF_STATUS_E_RESOURCES: Error return
  2384. */
  2385. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2386. {
  2387. uint8_t num_pool;
  2388. uint16_t num_desc;
  2389. uint16_t num_ext_desc;
  2390. uint8_t i;
  2391. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2392. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2393. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2394. dp_tx_flow_control_deinit(soc);
  2395. dp_tx_delete_static_pools(soc, num_pool);
  2396. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2397. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2398. __func__, num_pool, num_desc);
  2399. for (i = 0; i < num_pool; i++) {
  2400. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2401. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2402. "%s Tx Ext Desc Pool Free failed\n",
  2403. __func__);
  2404. return QDF_STATUS_E_RESOURCES;
  2405. }
  2406. }
  2407. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2408. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2409. __func__, num_pool, num_ext_desc);
  2410. for (i = 0; i < num_pool; i++) {
  2411. dp_tx_tso_desc_pool_free(soc, i);
  2412. }
  2413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2414. "%s TSO Desc Pool %d Free descs = %d\n",
  2415. __func__, num_pool, num_desc);
  2416. for (i = 0; i < num_pool; i++)
  2417. dp_tx_tso_num_seg_pool_free(soc, i);
  2418. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2419. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2420. __func__, num_pool, num_desc);
  2421. return QDF_STATUS_SUCCESS;
  2422. }
  2423. /**
  2424. * dp_tx_soc_attach() - attach soc to dp tx
  2425. * @soc: core txrx main context
  2426. *
  2427. * This function will attach dp tx into main device context
  2428. * will allocate dp tx resource and initialize resources
  2429. *
  2430. * Return: QDF_STATUS_SUCCESS: success
  2431. * QDF_STATUS_E_RESOURCES: Error return
  2432. */
  2433. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2434. {
  2435. uint8_t i;
  2436. uint8_t num_pool;
  2437. uint32_t num_desc;
  2438. uint32_t num_ext_desc;
  2439. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2440. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2441. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2442. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2443. goto fail;
  2444. dp_tx_flow_control_init(soc);
  2445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2446. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2447. __func__, num_pool, num_desc);
  2448. /* Allocate extension tx descriptor pools */
  2449. for (i = 0; i < num_pool; i++) {
  2450. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2451. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2452. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2453. i, soc);
  2454. goto fail;
  2455. }
  2456. }
  2457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2458. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2459. __func__, num_pool, num_ext_desc);
  2460. for (i = 0; i < num_pool; i++) {
  2461. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2463. "TSO Desc Pool alloc %d failed %pK\n",
  2464. i, soc);
  2465. goto fail;
  2466. }
  2467. }
  2468. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2469. "%s TSO Desc Alloc %d, descs = %d\n",
  2470. __func__, num_pool, num_desc);
  2471. for (i = 0; i < num_pool; i++) {
  2472. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2474. "TSO Num of seg Pool alloc %d failed %pK\n",
  2475. i, soc);
  2476. goto fail;
  2477. }
  2478. }
  2479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2480. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2481. __func__, num_pool, num_desc);
  2482. /* Initialize descriptors in TCL Rings */
  2483. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2484. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2485. hal_tx_init_data_ring(soc->hal_soc,
  2486. soc->tcl_data_ring[i].hal_srng);
  2487. }
  2488. }
  2489. /*
  2490. * todo - Add a runtime config option to enable this.
  2491. */
  2492. /*
  2493. * Due to multiple issues on NPR EMU, enable it selectively
  2494. * only for NPR EMU, should be removed, once NPR platforms
  2495. * are stable.
  2496. */
  2497. soc->process_tx_status = 0;
  2498. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2499. "%s HAL Tx init Success\n", __func__);
  2500. return QDF_STATUS_SUCCESS;
  2501. fail:
  2502. /* Detach will take care of freeing only allocated resources */
  2503. dp_tx_soc_detach(soc);
  2504. return QDF_STATUS_E_RESOURCES;
  2505. }
  2506. /*
  2507. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2508. * pdev: pointer to DP PDEV structure
  2509. * seg_info_head: Pointer to the head of list
  2510. *
  2511. * return: void
  2512. */
  2513. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2514. struct dp_tx_seg_info_s *seg_info_head)
  2515. {
  2516. struct dp_tx_me_buf_t *mc_uc_buf;
  2517. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2518. qdf_nbuf_t nbuf = NULL;
  2519. uint64_t phy_addr;
  2520. while (seg_info_head) {
  2521. nbuf = seg_info_head->nbuf;
  2522. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2523. seg_info_new->frags[0].vaddr;
  2524. phy_addr = seg_info_head->frags[0].paddr_hi;
  2525. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2526. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2527. phy_addr,
  2528. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2529. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2530. qdf_nbuf_free(nbuf);
  2531. seg_info_new = seg_info_head;
  2532. seg_info_head = seg_info_head->next;
  2533. qdf_mem_free(seg_info_new);
  2534. }
  2535. }
  2536. /**
  2537. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2538. * @vdev: DP VDEV handle
  2539. * @nbuf: Multicast nbuf
  2540. * @newmac: Table of the clients to which packets have to be sent
  2541. * @new_mac_cnt: No of clients
  2542. *
  2543. * return: no of converted packets
  2544. */
  2545. uint16_t
  2546. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2547. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2548. {
  2549. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2550. struct dp_pdev *pdev = vdev->pdev;
  2551. struct ether_header *eh;
  2552. uint8_t *data;
  2553. uint16_t len;
  2554. /* reference to frame dst addr */
  2555. uint8_t *dstmac;
  2556. /* copy of original frame src addr */
  2557. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2558. /* local index into newmac */
  2559. uint8_t new_mac_idx = 0;
  2560. struct dp_tx_me_buf_t *mc_uc_buf;
  2561. qdf_nbuf_t nbuf_clone;
  2562. struct dp_tx_msdu_info_s msdu_info;
  2563. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2564. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2565. struct dp_tx_seg_info_s *seg_info_new;
  2566. struct dp_tx_frag_info_s data_frag;
  2567. qdf_dma_addr_t paddr_data;
  2568. qdf_dma_addr_t paddr_mcbuf = 0;
  2569. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2570. QDF_STATUS status;
  2571. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2572. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2573. eh = (struct ether_header *) nbuf;
  2574. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2575. len = qdf_nbuf_len(nbuf);
  2576. data = qdf_nbuf_data(nbuf);
  2577. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2578. QDF_DMA_TO_DEVICE);
  2579. if (status) {
  2580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2581. "Mapping failure Error:%d", status);
  2582. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2583. return 0;
  2584. }
  2585. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2586. /*preparing data fragment*/
  2587. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2588. data_frag.paddr_lo = (uint32_t)paddr_data;
  2589. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2590. data_frag.len = len - DP_MAC_ADDR_LEN;
  2591. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2592. dstmac = newmac[new_mac_idx];
  2593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2594. "added mac addr (%pM)", dstmac);
  2595. /* Check for NULL Mac Address */
  2596. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2597. continue;
  2598. /* frame to self mac. skip */
  2599. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2600. continue;
  2601. /*
  2602. * TODO: optimize to avoid malloc in per-packet path
  2603. * For eg. seg_pool can be made part of vdev structure
  2604. */
  2605. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2606. if (!seg_info_new) {
  2607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2608. "alloc failed");
  2609. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2610. goto fail_seg_alloc;
  2611. }
  2612. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2613. if (mc_uc_buf == NULL)
  2614. goto fail_buf_alloc;
  2615. /*
  2616. * TODO: Check if we need to clone the nbuf
  2617. * Or can we just use the reference for all cases
  2618. */
  2619. if (new_mac_idx < (new_mac_cnt - 1)) {
  2620. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2621. if (nbuf_clone == NULL) {
  2622. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2623. goto fail_clone;
  2624. }
  2625. } else {
  2626. /*
  2627. * Update the ref
  2628. * to account for frame sent without cloning
  2629. */
  2630. qdf_nbuf_ref(nbuf);
  2631. nbuf_clone = nbuf;
  2632. }
  2633. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2634. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2635. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2636. &paddr_mcbuf);
  2637. if (status) {
  2638. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2639. "Mapping failure Error:%d", status);
  2640. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2641. goto fail_map;
  2642. }
  2643. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2644. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2645. seg_info_new->frags[0].paddr_hi =
  2646. ((uint64_t) paddr_mcbuf >> 32);
  2647. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2648. seg_info_new->frags[1] = data_frag;
  2649. seg_info_new->nbuf = nbuf_clone;
  2650. seg_info_new->frag_cnt = 2;
  2651. seg_info_new->total_len = len;
  2652. seg_info_new->next = NULL;
  2653. if (seg_info_head == NULL)
  2654. seg_info_head = seg_info_new;
  2655. else
  2656. seg_info_tail->next = seg_info_new;
  2657. seg_info_tail = seg_info_new;
  2658. }
  2659. if (!seg_info_head)
  2660. return 0;
  2661. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2662. msdu_info.num_seg = new_mac_cnt;
  2663. msdu_info.frm_type = dp_tx_frm_me;
  2664. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2665. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2666. while (seg_info_head->next) {
  2667. seg_info_new = seg_info_head;
  2668. seg_info_head = seg_info_head->next;
  2669. qdf_mem_free(seg_info_new);
  2670. }
  2671. qdf_mem_free(seg_info_head);
  2672. return new_mac_cnt;
  2673. fail_map:
  2674. qdf_nbuf_free(nbuf_clone);
  2675. fail_clone:
  2676. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2677. fail_buf_alloc:
  2678. qdf_mem_free(seg_info_new);
  2679. fail_seg_alloc:
  2680. dp_tx_me_mem_free(pdev, seg_info_head);
  2681. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2682. return 0;
  2683. }