dp_ipa.c 64 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifdef IPA_OFFLOAD
  17. #include <qdf_ipa_wdi3.h>
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <hal_hw_headers.h>
  21. #include <hal_api.h>
  22. #include <hif.h>
  23. #include <htt.h>
  24. #include <wdi_event.h>
  25. #include <queue.h>
  26. #include "dp_types.h"
  27. #include "dp_htt.h"
  28. #include "dp_tx.h"
  29. #include "dp_rx.h"
  30. #include "dp_ipa.h"
  31. /* Ring index for WBM2SW2 release ring */
  32. #define IPA_TX_COMP_RING_IDX HAL_IPA_TX_COMP_RING_IDX
  33. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  34. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  35. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  36. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  37. * This causes back pressure, resulting in a FW crash.
  38. * By leaving some entries with no buffer attached, WBM will be able to write
  39. * to the ring, and from dumps we can figure out the buffer which is causing
  40. * this issue.
  41. */
  42. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  43. /**
  44. *struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  45. * @ix0_reg: reo destination ring IX0 value
  46. * @ix2_reg: reo destination ring IX2 value
  47. * @ix3_reg: reo destination ring IX3 value
  48. */
  49. struct dp_ipa_reo_remap_record {
  50. uint64_t timestamp;
  51. uint32_t ix0_reg;
  52. uint32_t ix2_reg;
  53. uint32_t ix3_reg;
  54. };
  55. #define REO_REMAP_HISTORY_SIZE 32
  56. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  57. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  58. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  59. {
  60. int next = qdf_atomic_inc_return(index);
  61. if (next == REO_REMAP_HISTORY_SIZE)
  62. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  63. return next % REO_REMAP_HISTORY_SIZE;
  64. }
  65. /**
  66. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  67. * @ix0_val: reo destination ring IX0 value
  68. * @ix2_val: reo destination ring IX2 value
  69. * @ix3_val: reo destination ring IX3 value
  70. *
  71. * Return: None
  72. */
  73. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  74. uint32_t ix3_val)
  75. {
  76. int idx = dp_ipa_reo_remap_record_index_next(
  77. &dp_ipa_reo_remap_history_index);
  78. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  79. record->timestamp = qdf_get_log_timestamp();
  80. record->ix0_reg = ix0_val;
  81. record->ix2_reg = ix2_val;
  82. record->ix3_reg = ix3_val;
  83. }
  84. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  85. qdf_nbuf_t nbuf,
  86. uint32_t size,
  87. bool create)
  88. {
  89. qdf_mem_info_t mem_map_table = {0};
  90. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  91. qdf_nbuf_get_frag_paddr(nbuf, 0),
  92. size);
  93. if (create)
  94. return qdf_ipa_wdi_create_smmu_mapping(1, &mem_map_table);
  95. else
  96. return qdf_ipa_wdi_release_smmu_mapping(1, &mem_map_table);
  97. }
  98. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  99. qdf_nbuf_t nbuf,
  100. uint32_t size,
  101. bool create)
  102. {
  103. struct dp_pdev *pdev;
  104. int i;
  105. for (i = 0; i < soc->pdev_count; i++) {
  106. pdev = soc->pdev_list[i];
  107. if (pdev && pdev->monitor_configured)
  108. return QDF_STATUS_SUCCESS;
  109. }
  110. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  111. !qdf_mem_smmu_s1_enabled(soc->osdev))
  112. return QDF_STATUS_SUCCESS;
  113. /**
  114. * Even if ipa pipes is disabled, but if it's unmap
  115. * operation and nbuf has done ipa smmu map before,
  116. * do ipa smmu unmap as well.
  117. */
  118. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  119. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  120. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  121. } else {
  122. return QDF_STATUS_SUCCESS;
  123. }
  124. }
  125. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  126. if (create) {
  127. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  128. } else {
  129. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  130. }
  131. return QDF_STATUS_E_INVAL;
  132. }
  133. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  134. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create);
  135. }
  136. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  137. struct dp_soc *soc,
  138. struct dp_pdev *pdev,
  139. bool create)
  140. {
  141. uint32_t index;
  142. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  143. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  144. qdf_nbuf_t nbuf;
  145. uint32_t buf_len;
  146. if (!ipa_is_ready()) {
  147. dp_info("IPA is not READY");
  148. return 0;
  149. }
  150. for (index = 0; index < tx_buffer_cnt; index++) {
  151. nbuf = (qdf_nbuf_t)
  152. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  153. if (!nbuf)
  154. continue;
  155. buf_len = qdf_nbuf_get_data_len(nbuf);
  156. ret = __dp_ipa_handle_buf_smmu_mapping(
  157. soc, nbuf, buf_len, create);
  158. qdf_assert_always(!ret);
  159. }
  160. return ret;
  161. }
  162. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  163. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  164. struct dp_pdev *pdev,
  165. bool create)
  166. {
  167. struct rx_desc_pool *rx_pool;
  168. uint8_t pdev_id;
  169. uint32_t num_desc, page_id, offset, i;
  170. uint16_t num_desc_per_page;
  171. union dp_rx_desc_list_elem_t *rx_desc_elem;
  172. struct dp_rx_desc *rx_desc;
  173. qdf_nbuf_t nbuf;
  174. if (!qdf_ipa_is_ready())
  175. return QDF_STATUS_SUCCESS;
  176. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  177. return QDF_STATUS_SUCCESS;
  178. pdev_id = pdev->pdev_id;
  179. rx_pool = &soc->rx_desc_buf[pdev_id];
  180. qdf_spin_lock_bh(&rx_pool->lock);
  181. num_desc = rx_pool->pool_size;
  182. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  183. for (i = 0; i < num_desc; i++) {
  184. page_id = i / num_desc_per_page;
  185. offset = i % num_desc_per_page;
  186. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  187. break;
  188. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  189. rx_desc = &rx_desc_elem->rx_desc;
  190. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  191. continue;
  192. nbuf = rx_desc->nbuf;
  193. if (qdf_unlikely(create ==
  194. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  195. if (create) {
  196. DP_STATS_INC(soc,
  197. rx.err.ipa_smmu_map_dup, 1);
  198. } else {
  199. DP_STATS_INC(soc,
  200. rx.err.ipa_smmu_unmap_dup, 1);
  201. }
  202. continue;
  203. }
  204. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  205. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  206. rx_pool->buf_size, create);
  207. }
  208. qdf_spin_unlock_bh(&rx_pool->lock);
  209. return QDF_STATUS_SUCCESS;
  210. }
  211. #else
  212. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  213. struct dp_pdev *pdev,
  214. bool create)
  215. {
  216. struct rx_desc_pool *rx_pool;
  217. uint8_t pdev_id;
  218. qdf_nbuf_t nbuf;
  219. int i;
  220. if (!qdf_ipa_is_ready())
  221. return QDF_STATUS_SUCCESS;
  222. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  223. return QDF_STATUS_SUCCESS;
  224. pdev_id = pdev->pdev_id;
  225. rx_pool = &soc->rx_desc_buf[pdev_id];
  226. qdf_spin_lock_bh(&rx_pool->lock);
  227. for (i = 0; i < rx_pool->pool_size; i++) {
  228. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  229. rx_pool->array[i].rx_desc.unmapped)
  230. continue;
  231. nbuf = rx_pool->array[i].rx_desc.nbuf;
  232. if (qdf_unlikely(create ==
  233. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  234. if (create) {
  235. DP_STATS_INC(soc,
  236. rx.err.ipa_smmu_map_dup, 1);
  237. } else {
  238. DP_STATS_INC(soc,
  239. rx.err.ipa_smmu_unmap_dup, 1);
  240. }
  241. continue;
  242. }
  243. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  244. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  245. rx_pool->buf_size, create);
  246. }
  247. qdf_spin_unlock_bh(&rx_pool->lock);
  248. return QDF_STATUS_SUCCESS;
  249. }
  250. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  251. /**
  252. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  253. * @soc: data path instance
  254. * @pdev: core txrx pdev context
  255. *
  256. * Free allocated TX buffers with WBM SRNG
  257. *
  258. * Return: none
  259. */
  260. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  261. {
  262. int idx;
  263. qdf_nbuf_t nbuf;
  264. struct dp_ipa_resources *ipa_res;
  265. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  266. nbuf = (qdf_nbuf_t)
  267. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  268. if (!nbuf)
  269. continue;
  270. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  271. qdf_mem_dp_tx_skb_cnt_dec();
  272. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  273. qdf_nbuf_free(nbuf);
  274. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  275. (void *)NULL;
  276. }
  277. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  278. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  279. ipa_res = &pdev->ipa_resource;
  280. if (!ipa_res->is_db_ddr_mapped)
  281. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  282. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  283. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  284. }
  285. /**
  286. * dp_rx_ipa_uc_detach - free autonomy RX resources
  287. * @soc: data path instance
  288. * @pdev: core txrx pdev context
  289. *
  290. * This function will detach DP RX into main device context
  291. * will free DP Rx resources.
  292. *
  293. * Return: none
  294. */
  295. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  296. {
  297. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  298. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  299. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  300. }
  301. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  302. {
  303. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  304. return QDF_STATUS_SUCCESS;
  305. /* TX resource detach */
  306. dp_tx_ipa_uc_detach(soc, pdev);
  307. /* RX resource detach */
  308. dp_rx_ipa_uc_detach(soc, pdev);
  309. return QDF_STATUS_SUCCESS; /* success */
  310. }
  311. /**
  312. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  313. * @soc: data path instance
  314. * @pdev: Physical device handle
  315. *
  316. * Allocate TX buffer from non-cacheable memory
  317. * Attache allocated TX buffers with WBM SRNG
  318. *
  319. * Return: int
  320. */
  321. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  322. {
  323. uint32_t tx_buffer_count;
  324. uint32_t ring_base_align = 8;
  325. qdf_dma_addr_t buffer_paddr;
  326. struct hal_srng *wbm_srng = (struct hal_srng *)
  327. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  328. struct hal_srng_params srng_params;
  329. uint32_t paddr_lo;
  330. uint32_t paddr_hi;
  331. void *ring_entry;
  332. int num_entries;
  333. qdf_nbuf_t nbuf;
  334. int retval = QDF_STATUS_SUCCESS;
  335. int max_alloc_count = 0;
  336. /*
  337. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  338. * unsigned int uc_tx_buf_sz =
  339. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  340. */
  341. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  342. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  343. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  344. &srng_params);
  345. num_entries = srng_params.num_entries;
  346. max_alloc_count =
  347. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  348. if (max_alloc_count <= 0) {
  349. dp_err("incorrect value for buffer count %u", max_alloc_count);
  350. return -EINVAL;
  351. }
  352. dp_info("requested %d buffers to be posted to wbm ring",
  353. max_alloc_count);
  354. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  355. qdf_mem_malloc(num_entries *
  356. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  357. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  358. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  359. return -ENOMEM;
  360. }
  361. hal_srng_access_start_unlocked(soc->hal_soc,
  362. hal_srng_to_hal_ring_handle(wbm_srng));
  363. /*
  364. * Allocate Tx buffers as many as possible.
  365. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  366. * Populate Tx buffers into WBM2IPA ring
  367. * This initial buffer population will simulate H/W as source ring,
  368. * and update HP
  369. */
  370. for (tx_buffer_count = 0;
  371. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  372. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  373. if (!nbuf)
  374. break;
  375. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  376. hal_srng_to_hal_ring_handle(wbm_srng));
  377. if (!ring_entry) {
  378. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  379. "%s: Failed to get WBM ring entry",
  380. __func__);
  381. qdf_nbuf_free(nbuf);
  382. break;
  383. }
  384. qdf_nbuf_map_single(soc->osdev, nbuf,
  385. QDF_DMA_BIDIRECTIONAL);
  386. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  387. qdf_mem_dp_tx_skb_cnt_inc();
  388. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  389. paddr_lo = ((uint64_t)buffer_paddr & 0x00000000ffffffff);
  390. paddr_hi = ((uint64_t)buffer_paddr & 0x0000001f00000000) >> 32;
  391. HAL_RXDMA_PADDR_LO_SET(ring_entry, paddr_lo);
  392. HAL_RXDMA_PADDR_HI_SET(ring_entry, paddr_hi);
  393. HAL_RXDMA_MANAGER_SET(ring_entry, (IPA_TCL_DATA_RING_IDX +
  394. HAL_WBM_SW0_BM_ID));
  395. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  396. = (void *)nbuf;
  397. }
  398. hal_srng_access_end_unlocked(soc->hal_soc,
  399. hal_srng_to_hal_ring_handle(wbm_srng));
  400. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  401. if (tx_buffer_count) {
  402. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  403. } else {
  404. dp_err("No IPA WDI TX buffer allocated!");
  405. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  406. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  407. retval = -ENOMEM;
  408. }
  409. return retval;
  410. }
  411. /**
  412. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  413. * @soc: data path instance
  414. * @pdev: core txrx pdev context
  415. *
  416. * This function will attach a DP RX instance into the main
  417. * device (SOC) context.
  418. *
  419. * Return: QDF_STATUS_SUCCESS: success
  420. * QDF_STATUS_E_RESOURCES: Error return
  421. */
  422. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  423. {
  424. return QDF_STATUS_SUCCESS;
  425. }
  426. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  427. {
  428. int error;
  429. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  430. return QDF_STATUS_SUCCESS;
  431. /* TX resource attach */
  432. error = dp_tx_ipa_uc_attach(soc, pdev);
  433. if (error) {
  434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  435. "%s: DP IPA UC TX attach fail code %d",
  436. __func__, error);
  437. return error;
  438. }
  439. /* RX resource attach */
  440. error = dp_rx_ipa_uc_attach(soc, pdev);
  441. if (error) {
  442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  443. "%s: DP IPA UC RX attach fail code %d",
  444. __func__, error);
  445. dp_tx_ipa_uc_detach(soc, pdev);
  446. return error;
  447. }
  448. return QDF_STATUS_SUCCESS; /* success */
  449. }
  450. /*
  451. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  452. * @soc: data path SoC handle
  453. *
  454. * Return: none
  455. */
  456. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  457. struct dp_pdev *pdev)
  458. {
  459. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  460. struct hal_srng *hal_srng;
  461. struct hal_srng_params srng_params;
  462. qdf_dma_addr_t hp_addr;
  463. unsigned long addr_offset, dev_base_paddr;
  464. uint32_t ix0;
  465. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  466. return QDF_STATUS_SUCCESS;
  467. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  468. hal_srng = (struct hal_srng *)
  469. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  470. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  471. hal_srng_to_hal_ring_handle(hal_srng),
  472. &srng_params);
  473. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  474. srng_params.ring_base_paddr;
  475. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  476. srng_params.ring_base_vaddr;
  477. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  478. (srng_params.num_entries * srng_params.entry_size) << 2;
  479. /*
  480. * For the register backed memory addresses, use the scn->mem_pa to
  481. * calculate the physical address of the shadow registers
  482. */
  483. dev_base_paddr =
  484. (unsigned long)
  485. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  486. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  487. (unsigned long)(hal_soc->dev_base_addr);
  488. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  489. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  490. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  491. (unsigned int)addr_offset,
  492. (unsigned int)dev_base_paddr,
  493. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  494. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  495. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  496. srng_params.num_entries,
  497. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  498. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  499. hal_srng = (struct hal_srng *)
  500. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  501. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  502. hal_srng_to_hal_ring_handle(hal_srng),
  503. &srng_params);
  504. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  505. srng_params.ring_base_paddr;
  506. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  507. srng_params.ring_base_vaddr;
  508. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  509. (srng_params.num_entries * srng_params.entry_size) << 2;
  510. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  511. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  512. hal_srng_to_hal_ring_handle(hal_srng));
  513. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  514. (unsigned long)(hal_soc->dev_base_addr);
  515. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  516. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  517. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  518. (unsigned int)addr_offset,
  519. (unsigned int)dev_base_paddr,
  520. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  521. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  522. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  523. srng_params.num_entries,
  524. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  525. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  526. hal_srng = (struct hal_srng *)
  527. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  528. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  529. hal_srng_to_hal_ring_handle(hal_srng),
  530. &srng_params);
  531. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  532. srng_params.ring_base_paddr;
  533. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  534. srng_params.ring_base_vaddr;
  535. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  536. (srng_params.num_entries * srng_params.entry_size) << 2;
  537. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  538. (unsigned long)(hal_soc->dev_base_addr);
  539. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  540. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  541. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  542. (unsigned int)addr_offset,
  543. (unsigned int)dev_base_paddr,
  544. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  545. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  546. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  547. srng_params.num_entries,
  548. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  549. hal_srng = (struct hal_srng *)
  550. pdev->rx_refill_buf_ring2.hal_srng;
  551. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  552. hal_srng_to_hal_ring_handle(hal_srng),
  553. &srng_params);
  554. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  555. srng_params.ring_base_paddr;
  556. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  557. srng_params.ring_base_vaddr;
  558. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  559. (srng_params.num_entries * srng_params.entry_size) << 2;
  560. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  561. hal_srng_to_hal_ring_handle(hal_srng));
  562. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  563. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  564. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  565. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  566. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  567. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  568. srng_params.num_entries,
  569. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  570. /*
  571. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  572. * DESTINATION_RING_CTRL_IX_0.
  573. */
  574. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  575. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  576. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  577. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  578. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  579. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  580. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  581. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  582. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  583. return 0;
  584. }
  585. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  586. qdf_shared_mem_t *shared_mem,
  587. void *cpu_addr,
  588. qdf_dma_addr_t dma_addr,
  589. uint32_t size)
  590. {
  591. qdf_dma_addr_t paddr;
  592. int ret;
  593. shared_mem->vaddr = cpu_addr;
  594. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  595. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  596. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  597. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  598. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  599. shared_mem->vaddr, dma_addr, size);
  600. if (ret) {
  601. dp_err("Unable to get DMA sgtable");
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  605. return QDF_STATUS_SUCCESS;
  606. }
  607. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  608. {
  609. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  610. struct dp_pdev *pdev =
  611. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  612. struct dp_ipa_resources *ipa_res;
  613. if (!pdev) {
  614. dp_err("Invalid instance");
  615. return QDF_STATUS_E_FAILURE;
  616. }
  617. ipa_res = &pdev->ipa_resource;
  618. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  619. return QDF_STATUS_SUCCESS;
  620. ipa_res->tx_num_alloc_buffer =
  621. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  622. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  623. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  624. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  625. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  626. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  627. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  628. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  629. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  630. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  631. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  632. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  633. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  634. dp_ipa_get_shared_mem_info(
  635. soc->osdev, &ipa_res->rx_refill_ring,
  636. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  637. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  638. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  639. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  640. !qdf_mem_get_dma_addr(soc->osdev,
  641. &ipa_res->tx_comp_ring.mem_info) ||
  642. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  643. !qdf_mem_get_dma_addr(soc->osdev,
  644. &ipa_res->rx_refill_ring.mem_info))
  645. return QDF_STATUS_E_FAILURE;
  646. return QDF_STATUS_SUCCESS;
  647. }
  648. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  649. struct dp_ipa_resources *ipa_res)
  650. {
  651. struct hal_srng *wbm_srng = (struct hal_srng *)
  652. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  653. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  654. ipa_res->tx_comp_doorbell_paddr);
  655. dp_info("paddr %pK vaddr %pK",
  656. (void *)ipa_res->tx_comp_doorbell_paddr,
  657. (void *)ipa_res->tx_comp_doorbell_vaddr);
  658. }
  659. #ifdef IPA_SET_RESET_TX_DB_PA
  660. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  661. #else
  662. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  663. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  664. #endif
  665. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  666. {
  667. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  668. struct dp_pdev *pdev =
  669. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  670. struct dp_ipa_resources *ipa_res;
  671. struct hal_srng *reo_srng = (struct hal_srng *)
  672. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  673. uint32_t tx_comp_doorbell_dmaaddr;
  674. uint32_t rx_ready_doorbell_dmaaddr;
  675. if (!pdev) {
  676. dp_err("Invalid instance");
  677. return QDF_STATUS_E_FAILURE;
  678. }
  679. ipa_res = &pdev->ipa_resource;
  680. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  681. return QDF_STATUS_SUCCESS;
  682. if (ipa_res->is_db_ddr_mapped)
  683. ipa_res->tx_comp_doorbell_vaddr =
  684. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  685. else
  686. ipa_res->tx_comp_doorbell_vaddr =
  687. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  688. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  689. pld_smmu_map(soc->osdev->dev, ipa_res->tx_comp_doorbell_paddr,
  690. &tx_comp_doorbell_dmaaddr, sizeof(uint32_t));
  691. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  692. pld_smmu_map(soc->osdev->dev, ipa_res->rx_ready_doorbell_paddr,
  693. &rx_ready_doorbell_dmaaddr, sizeof(uint32_t));
  694. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  695. }
  696. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  697. /*
  698. * For RX, REO module on Napier/Hastings does reordering on incoming
  699. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  700. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  701. * to IPA.
  702. * Set the doorbell addr for the REO ring.
  703. */
  704. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  705. ipa_res->rx_ready_doorbell_paddr);
  706. return QDF_STATUS_SUCCESS;
  707. }
  708. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  709. uint8_t *op_msg)
  710. {
  711. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  712. struct dp_pdev *pdev =
  713. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  714. if (!pdev) {
  715. dp_err("Invalid instance");
  716. return QDF_STATUS_E_FAILURE;
  717. }
  718. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  719. return QDF_STATUS_SUCCESS;
  720. if (pdev->ipa_uc_op_cb) {
  721. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  722. } else {
  723. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  724. "%s: IPA callback function is not registered", __func__);
  725. qdf_mem_free(op_msg);
  726. return QDF_STATUS_E_FAILURE;
  727. }
  728. return QDF_STATUS_SUCCESS;
  729. }
  730. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  731. ipa_uc_op_cb_type op_cb,
  732. void *usr_ctxt)
  733. {
  734. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  735. struct dp_pdev *pdev =
  736. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  737. if (!pdev) {
  738. dp_err("Invalid instance");
  739. return QDF_STATUS_E_FAILURE;
  740. }
  741. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  742. return QDF_STATUS_SUCCESS;
  743. pdev->ipa_uc_op_cb = op_cb;
  744. pdev->usr_ctxt = usr_ctxt;
  745. return QDF_STATUS_SUCCESS;
  746. }
  747. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  748. {
  749. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  750. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  751. if (!pdev) {
  752. dp_err("Invalid instance");
  753. return;
  754. }
  755. dp_debug("Deregister OP handler callback");
  756. pdev->ipa_uc_op_cb = NULL;
  757. pdev->usr_ctxt = NULL;
  758. }
  759. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  760. {
  761. /* TBD */
  762. return QDF_STATUS_SUCCESS;
  763. }
  764. /**
  765. * dp_tx_send_ipa_data_frame() - send IPA data frame
  766. * @soc_hdl: datapath soc handle
  767. * @vdev_id: id of the virtual device
  768. * @skb: skb to transmit
  769. *
  770. * Return: skb/ NULL is for success
  771. */
  772. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  773. qdf_nbuf_t skb)
  774. {
  775. qdf_nbuf_t ret;
  776. /* Terminate the (single-element) list of tx frames */
  777. qdf_nbuf_set_next(skb, NULL);
  778. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  779. if (ret) {
  780. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  781. "%s: Failed to tx", __func__);
  782. return ret;
  783. }
  784. return NULL;
  785. }
  786. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  787. {
  788. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  789. struct dp_pdev *pdev =
  790. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  791. uint32_t ix0;
  792. uint32_t ix2;
  793. if (!pdev) {
  794. dp_err("Invalid instance");
  795. return QDF_STATUS_E_FAILURE;
  796. }
  797. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  798. return QDF_STATUS_SUCCESS;
  799. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  800. return QDF_STATUS_E_AGAIN;
  801. /* Call HAL API to remap REO rings to REO2IPA ring */
  802. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  803. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 1) |
  804. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 2) |
  805. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 3) |
  806. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 4) |
  807. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  808. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  809. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  810. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  811. ix2 = HAL_REO_REMAP_IX2(REO_REMAP_SW4, 16) |
  812. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 17) |
  813. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 18) |
  814. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 19) |
  815. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 20) |
  816. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 21) |
  817. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 22) |
  818. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 23);
  819. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  820. &ix2, &ix2);
  821. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  822. } else {
  823. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  824. NULL, NULL);
  825. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  826. }
  827. return QDF_STATUS_SUCCESS;
  828. }
  829. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  830. {
  831. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  832. struct dp_pdev *pdev =
  833. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  834. uint32_t ix0;
  835. uint32_t ix2;
  836. uint32_t ix3;
  837. if (!pdev) {
  838. dp_err("Invalid instance");
  839. return QDF_STATUS_E_FAILURE;
  840. }
  841. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  842. return QDF_STATUS_SUCCESS;
  843. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  844. return QDF_STATUS_E_AGAIN;
  845. /* Call HAL API to remap REO rings to REO2IPA ring */
  846. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  847. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  848. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  849. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  850. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  851. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  852. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  853. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  854. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  855. dp_reo_remap_config(soc, &ix2, &ix3);
  856. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  857. &ix2, &ix3);
  858. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  859. } else {
  860. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  861. NULL, NULL);
  862. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  863. }
  864. return QDF_STATUS_SUCCESS;
  865. }
  866. /* This should be configurable per H/W configuration enable status */
  867. #define L3_HEADER_PADDING 2
  868. #ifdef CONFIG_IPA_WDI_UNIFIED_API
  869. #ifndef QCA_LL_TX_FLOW_CONTROL_V2
  870. static inline void dp_setup_mcc_sys_pipes(
  871. qdf_ipa_sys_connect_params_t *sys_in,
  872. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  873. {
  874. /* Setup MCC sys pipe */
  875. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  876. DP_IPA_MAX_IFACE;
  877. for (int i = 0; i < DP_IPA_MAX_IFACE; i++)
  878. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  879. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  880. }
  881. #else
  882. static inline void dp_setup_mcc_sys_pipes(
  883. qdf_ipa_sys_connect_params_t *sys_in,
  884. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  885. {
  886. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  887. }
  888. #endif
  889. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  890. struct dp_ipa_resources *ipa_res,
  891. qdf_ipa_wdi_pipe_setup_info_t *tx,
  892. bool over_gsi)
  893. {
  894. struct tcl_data_cmd *tcl_desc_ptr;
  895. uint8_t *desc_addr;
  896. uint32_t desc_size;
  897. if (over_gsi)
  898. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  899. else
  900. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  901. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  902. qdf_mem_get_dma_addr(soc->osdev,
  903. &ipa_res->tx_comp_ring.mem_info);
  904. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  905. qdf_mem_get_dma_size(soc->osdev,
  906. &ipa_res->tx_comp_ring.mem_info);
  907. /* WBM Tail Pointer Address */
  908. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  909. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  910. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  911. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  912. qdf_mem_get_dma_addr(soc->osdev,
  913. &ipa_res->tx_ring.mem_info);
  914. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  915. qdf_mem_get_dma_size(soc->osdev,
  916. &ipa_res->tx_ring.mem_info);
  917. /* TCL Head Pointer Address */
  918. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  919. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  920. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  921. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  922. ipa_res->tx_num_alloc_buffer;
  923. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  924. /* Preprogram TCL descriptor */
  925. desc_addr =
  926. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  927. desc_size = sizeof(struct tcl_data_cmd);
  928. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  929. tcl_desc_ptr = (struct tcl_data_cmd *)
  930. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  931. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  932. HAL_RX_BUF_RBM_SW2_BM;
  933. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  934. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  935. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  936. }
  937. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  938. struct dp_ipa_resources *ipa_res,
  939. qdf_ipa_wdi_pipe_setup_info_t *rx,
  940. bool over_gsi)
  941. {
  942. if (over_gsi)
  943. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  944. IPA_CLIENT_WLAN2_PROD;
  945. else
  946. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  947. IPA_CLIENT_WLAN1_PROD;
  948. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  949. qdf_mem_get_dma_addr(soc->osdev,
  950. &ipa_res->rx_rdy_ring.mem_info);
  951. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  952. qdf_mem_get_dma_size(soc->osdev,
  953. &ipa_res->rx_rdy_ring.mem_info);
  954. /* REO Tail Pointer Address */
  955. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  956. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  957. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  958. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  959. qdf_mem_get_dma_addr(soc->osdev,
  960. &ipa_res->rx_refill_ring.mem_info);
  961. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  962. qdf_mem_get_dma_size(soc->osdev,
  963. &ipa_res->rx_refill_ring.mem_info);
  964. /* FW Head Pointer Address */
  965. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  966. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  967. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  968. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  969. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  970. }
  971. static void
  972. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  973. struct dp_ipa_resources *ipa_res,
  974. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  975. bool over_gsi)
  976. {
  977. struct tcl_data_cmd *tcl_desc_ptr;
  978. uint8_t *desc_addr;
  979. uint32_t desc_size;
  980. if (over_gsi)
  981. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  982. IPA_CLIENT_WLAN2_CONS;
  983. else
  984. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  985. IPA_CLIENT_WLAN1_CONS;
  986. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  987. &ipa_res->tx_comp_ring.sgtable,
  988. sizeof(sgtable_t));
  989. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  990. qdf_mem_get_dma_size(soc->osdev,
  991. &ipa_res->tx_comp_ring.mem_info);
  992. /* WBM Tail Pointer Address */
  993. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  994. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  995. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  996. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  997. &ipa_res->tx_ring.sgtable,
  998. sizeof(sgtable_t));
  999. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  1000. qdf_mem_get_dma_size(soc->osdev,
  1001. &ipa_res->tx_ring.mem_info);
  1002. /* TCL Head Pointer Address */
  1003. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  1004. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1005. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  1006. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  1007. ipa_res->tx_num_alloc_buffer;
  1008. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  1009. /* Preprogram TCL descriptor */
  1010. desc_addr = (uint8_t *)QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(
  1011. tx_smmu);
  1012. desc_size = sizeof(struct tcl_data_cmd);
  1013. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  1014. tcl_desc_ptr = (struct tcl_data_cmd *)
  1015. (QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(tx_smmu) + 1);
  1016. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  1017. HAL_RX_BUF_RBM_SW2_BM;
  1018. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1019. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1020. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1021. }
  1022. static void
  1023. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  1024. struct dp_ipa_resources *ipa_res,
  1025. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  1026. bool over_gsi)
  1027. {
  1028. if (over_gsi)
  1029. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1030. IPA_CLIENT_WLAN2_PROD;
  1031. else
  1032. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1033. IPA_CLIENT_WLAN1_PROD;
  1034. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  1035. &ipa_res->rx_rdy_ring.sgtable,
  1036. sizeof(sgtable_t));
  1037. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  1038. qdf_mem_get_dma_size(soc->osdev,
  1039. &ipa_res->rx_rdy_ring.mem_info);
  1040. /* REO Tail Pointer Address */
  1041. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  1042. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1043. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  1044. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  1045. &ipa_res->rx_refill_ring.sgtable,
  1046. sizeof(sgtable_t));
  1047. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  1048. qdf_mem_get_dma_size(soc->osdev,
  1049. &ipa_res->rx_refill_ring.mem_info);
  1050. /* FW Head Pointer Address */
  1051. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  1052. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1053. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  1054. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  1055. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  1056. }
  1057. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1058. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1059. void *ipa_wdi_meter_notifier_cb,
  1060. uint32_t ipa_desc_size, void *ipa_priv,
  1061. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1062. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  1063. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi)
  1064. {
  1065. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1066. struct dp_pdev *pdev =
  1067. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1068. struct dp_ipa_resources *ipa_res;
  1069. qdf_ipa_ep_cfg_t *tx_cfg;
  1070. qdf_ipa_ep_cfg_t *rx_cfg;
  1071. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  1072. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  1073. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  1074. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu;
  1075. qdf_ipa_wdi_conn_in_params_t pipe_in;
  1076. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1077. int ret;
  1078. if (!pdev) {
  1079. dp_err("Invalid instance");
  1080. return QDF_STATUS_E_FAILURE;
  1081. }
  1082. ipa_res = &pdev->ipa_resource;
  1083. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1084. return QDF_STATUS_SUCCESS;
  1085. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  1086. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1087. if (is_smmu_enabled)
  1088. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in) = true;
  1089. else
  1090. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in) = false;
  1091. dp_setup_mcc_sys_pipes(sys_in, &pipe_in);
  1092. /* TX PIPE */
  1093. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in)) {
  1094. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(&pipe_in);
  1095. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  1096. } else {
  1097. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  1098. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  1099. }
  1100. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  1101. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1102. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  1103. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  1104. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  1105. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  1106. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  1107. /**
  1108. * Transfer Ring: WBM Ring
  1109. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1110. * Event Ring: TCL ring
  1111. * Event Ring Doorbell PA: TCL Head Pointer Address
  1112. */
  1113. if (is_smmu_enabled)
  1114. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi);
  1115. else
  1116. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  1117. /* RX PIPE */
  1118. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in)) {
  1119. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(&pipe_in);
  1120. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  1121. } else {
  1122. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  1123. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  1124. }
  1125. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  1126. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1127. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  1128. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  1129. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  1130. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  1131. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  1132. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  1133. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  1134. /**
  1135. * Transfer Ring: REO Ring
  1136. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1137. * Event Ring: FW ring
  1138. * Event Ring Doorbell PA: FW Head Pointer Address
  1139. */
  1140. if (is_smmu_enabled)
  1141. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi);
  1142. else
  1143. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  1144. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  1145. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  1146. /* Connect WDI IPA PIPEs */
  1147. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  1148. if (ret) {
  1149. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1150. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1151. __func__, ret);
  1152. return QDF_STATUS_E_FAILURE;
  1153. }
  1154. /* IPA uC Doorbell registers */
  1155. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  1156. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1157. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1158. ipa_res->tx_comp_doorbell_paddr =
  1159. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1160. ipa_res->rx_ready_doorbell_paddr =
  1161. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1162. ipa_res->is_db_ddr_mapped =
  1163. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  1164. soc->ipa_first_tx_db_access = true;
  1165. return QDF_STATUS_SUCCESS;
  1166. }
  1167. /**
  1168. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1169. * @ifname: Interface name
  1170. * @mac_addr: Interface MAC address
  1171. * @prod_client: IPA prod client type
  1172. * @cons_client: IPA cons client type
  1173. * @session_id: Session ID
  1174. * @is_ipv6_enabled: Is IPV6 enabled or not
  1175. *
  1176. * Return: QDF_STATUS
  1177. */
  1178. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1179. qdf_ipa_client_type_t prod_client,
  1180. qdf_ipa_client_type_t cons_client,
  1181. uint8_t session_id, bool is_ipv6_enabled)
  1182. {
  1183. qdf_ipa_wdi_reg_intf_in_params_t in;
  1184. qdf_ipa_wdi_hdr_info_t hdr_info;
  1185. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1186. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1187. int ret = -EINVAL;
  1188. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  1189. QDF_MAC_ADDR_REF(mac_addr));
  1190. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1191. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1192. /* IPV4 header */
  1193. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1194. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1195. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1196. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1197. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1198. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1199. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1200. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1201. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1202. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  1203. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1204. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1205. htonl(session_id << 16);
  1206. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1207. /* IPV6 header */
  1208. if (is_ipv6_enabled) {
  1209. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1210. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1211. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1212. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1213. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1214. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1215. }
  1216. dp_debug("registering for session_id: %u", session_id);
  1217. ret = qdf_ipa_wdi_reg_intf(&in);
  1218. if (ret) {
  1219. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1220. "%s: ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1221. __func__, ret);
  1222. return QDF_STATUS_E_FAILURE;
  1223. }
  1224. return QDF_STATUS_SUCCESS;
  1225. }
  1226. #else /* CONFIG_IPA_WDI_UNIFIED_API */
  1227. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1228. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1229. void *ipa_wdi_meter_notifier_cb,
  1230. uint32_t ipa_desc_size, void *ipa_priv,
  1231. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1232. uint32_t *rx_pipe_handle)
  1233. {
  1234. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1235. struct dp_pdev *pdev =
  1236. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1237. struct dp_ipa_resources *ipa_res;
  1238. qdf_ipa_wdi_pipe_setup_info_t *tx;
  1239. qdf_ipa_wdi_pipe_setup_info_t *rx;
  1240. qdf_ipa_wdi_conn_in_params_t pipe_in;
  1241. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1242. struct tcl_data_cmd *tcl_desc_ptr;
  1243. uint8_t *desc_addr;
  1244. uint32_t desc_size;
  1245. int ret;
  1246. if (!pdev) {
  1247. dp_err("Invalid instance");
  1248. return QDF_STATUS_E_FAILURE;
  1249. }
  1250. ipa_res = &pdev->ipa_resource;
  1251. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1252. return QDF_STATUS_SUCCESS;
  1253. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1254. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1255. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  1256. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1257. /* TX PIPE */
  1258. /**
  1259. * Transfer Ring: WBM Ring
  1260. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1261. * Event Ring: TCL ring
  1262. * Event Ring Doorbell PA: TCL Head Pointer Address
  1263. */
  1264. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  1265. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  1266. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1267. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  1268. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  1269. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  1270. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  1271. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  1272. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1273. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1274. ipa_res->tx_comp_ring_base_paddr;
  1275. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  1276. ipa_res->tx_comp_ring_size;
  1277. /* WBM Tail Pointer Address */
  1278. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  1279. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1280. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  1281. ipa_res->tx_ring_base_paddr;
  1282. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  1283. /* TCL Head Pointer Address */
  1284. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  1285. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1286. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  1287. ipa_res->tx_num_alloc_buffer;
  1288. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  1289. /* Preprogram TCL descriptor */
  1290. desc_addr =
  1291. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  1292. desc_size = sizeof(struct tcl_data_cmd);
  1293. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  1294. tcl_desc_ptr = (struct tcl_data_cmd *)
  1295. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  1296. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  1297. HAL_RX_BUF_RBM_SW2_BM;
  1298. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1299. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1300. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1301. /* RX PIPE */
  1302. /**
  1303. * Transfer Ring: REO Ring
  1304. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1305. * Event Ring: FW ring
  1306. * Event Ring Doorbell PA: FW Head Pointer Address
  1307. */
  1308. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  1309. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  1310. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1311. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  1312. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  1313. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  1314. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  1315. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  1316. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  1317. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  1318. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  1319. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  1320. ipa_res->rx_rdy_ring_base_paddr;
  1321. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  1322. ipa_res->rx_rdy_ring_size;
  1323. /* REO Tail Pointer Address */
  1324. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  1325. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1326. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  1327. ipa_res->rx_refill_ring_base_paddr;
  1328. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  1329. ipa_res->rx_refill_ring_size;
  1330. /* FW Head Pointer Address */
  1331. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  1332. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1333. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = RX_PKT_TLVS_LEN +
  1334. L3_HEADER_PADDING;
  1335. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  1336. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  1337. /* Connect WDI IPA PIPE */
  1338. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  1339. if (ret) {
  1340. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1341. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1342. __func__, ret);
  1343. return QDF_STATUS_E_FAILURE;
  1344. }
  1345. /* IPA uC Doorbell registers */
  1346. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1347. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  1348. __func__,
  1349. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1350. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1351. ipa_res->tx_comp_doorbell_paddr =
  1352. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1353. ipa_res->tx_comp_doorbell_vaddr =
  1354. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  1355. ipa_res->rx_ready_doorbell_paddr =
  1356. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1357. soc->ipa_first_tx_db_access = true;
  1358. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1359. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1360. __func__,
  1361. "transfer_ring_base_pa",
  1362. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  1363. "transfer_ring_size",
  1364. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  1365. "transfer_ring_doorbell_pa",
  1366. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  1367. "event_ring_base_pa",
  1368. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  1369. "event_ring_size",
  1370. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  1371. "event_ring_doorbell_pa",
  1372. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  1373. "num_pkt_buffers",
  1374. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  1375. "tx_comp_doorbell_paddr",
  1376. (void *)ipa_res->tx_comp_doorbell_paddr);
  1377. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1378. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1379. __func__,
  1380. "transfer_ring_base_pa",
  1381. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  1382. "transfer_ring_size",
  1383. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  1384. "transfer_ring_doorbell_pa",
  1385. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  1386. "event_ring_base_pa",
  1387. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  1388. "event_ring_size",
  1389. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  1390. "event_ring_doorbell_pa",
  1391. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  1392. "num_pkt_buffers",
  1393. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  1394. "tx_comp_doorbell_paddr",
  1395. (void *)ipa_res->rx_ready_doorbell_paddr);
  1396. return QDF_STATUS_SUCCESS;
  1397. }
  1398. /**
  1399. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1400. * @ifname: Interface name
  1401. * @mac_addr: Interface MAC address
  1402. * @prod_client: IPA prod client type
  1403. * @cons_client: IPA cons client type
  1404. * @session_id: Session ID
  1405. * @is_ipv6_enabled: Is IPV6 enabled or not
  1406. *
  1407. * Return: QDF_STATUS
  1408. */
  1409. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1410. qdf_ipa_client_type_t prod_client,
  1411. qdf_ipa_client_type_t cons_client,
  1412. uint8_t session_id, bool is_ipv6_enabled)
  1413. {
  1414. qdf_ipa_wdi_reg_intf_in_params_t in;
  1415. qdf_ipa_wdi_hdr_info_t hdr_info;
  1416. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1417. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1418. int ret = -EINVAL;
  1419. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1420. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  1421. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  1422. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1423. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1424. /* IPV4 header */
  1425. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1426. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1427. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1428. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1429. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1430. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1431. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1432. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1433. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1434. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1435. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1436. htonl(session_id << 16);
  1437. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1438. /* IPV6 header */
  1439. if (is_ipv6_enabled) {
  1440. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1441. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1442. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1443. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1444. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1445. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1446. }
  1447. ret = qdf_ipa_wdi_reg_intf(&in);
  1448. if (ret) {
  1449. dp_err("ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1450. ret);
  1451. return QDF_STATUS_E_FAILURE;
  1452. }
  1453. return QDF_STATUS_SUCCESS;
  1454. }
  1455. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  1456. /**
  1457. * dp_ipa_cleanup() - Disconnect IPA pipes
  1458. * @soc_hdl: dp soc handle
  1459. * @pdev_id: dp pdev id
  1460. * @tx_pipe_handle: Tx pipe handle
  1461. * @rx_pipe_handle: Rx pipe handle
  1462. *
  1463. * Return: QDF_STATUS
  1464. */
  1465. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1466. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle)
  1467. {
  1468. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1469. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1470. struct dp_ipa_resources *ipa_res;
  1471. struct dp_pdev *pdev;
  1472. int ret;
  1473. ret = qdf_ipa_wdi_disconn_pipes();
  1474. if (ret) {
  1475. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  1476. ret);
  1477. status = QDF_STATUS_E_FAILURE;
  1478. }
  1479. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1480. if (qdf_unlikely(!pdev)) {
  1481. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  1482. status = QDF_STATUS_E_FAILURE;
  1483. goto exit;
  1484. }
  1485. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1486. ipa_res = &pdev->ipa_resource;
  1487. /* unmap has to be the reverse order of smmu map */
  1488. ret = pld_smmu_unmap(soc->osdev->dev,
  1489. ipa_res->rx_ready_doorbell_paddr,
  1490. sizeof(uint32_t));
  1491. if (ret)
  1492. dp_err_rl("IPA RX DB smmu unmap failed");
  1493. ret = pld_smmu_unmap(soc->osdev->dev,
  1494. ipa_res->tx_comp_doorbell_paddr,
  1495. sizeof(uint32_t));
  1496. if (ret)
  1497. dp_err_rl("IPA TX DB smmu unmap failed");
  1498. }
  1499. exit:
  1500. return status;
  1501. }
  1502. /**
  1503. * dp_ipa_cleanup_iface() - Cleanup IPA header and deregister interface
  1504. * @ifname: Interface name
  1505. * @is_ipv6_enabled: Is IPV6 enabled or not
  1506. *
  1507. * Return: QDF_STATUS
  1508. */
  1509. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled)
  1510. {
  1511. int ret;
  1512. ret = qdf_ipa_wdi_dereg_intf(ifname);
  1513. if (ret) {
  1514. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1515. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  1516. __func__, ret);
  1517. return QDF_STATUS_E_FAILURE;
  1518. }
  1519. return QDF_STATUS_SUCCESS;
  1520. }
  1521. #ifdef IPA_SET_RESET_TX_DB_PA
  1522. static
  1523. QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1524. struct dp_ipa_resources *ipa_res)
  1525. {
  1526. hal_ring_handle_t wbm_srng =
  1527. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1528. qdf_dma_addr_t hp_addr;
  1529. if (!wbm_srng)
  1530. return QDF_STATUS_E_FAILURE;
  1531. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1532. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1533. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1534. return QDF_STATUS_SUCCESS;
  1535. }
  1536. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  1537. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  1538. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  1539. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  1540. #else
  1541. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  1542. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  1543. #endif
  1544. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1545. {
  1546. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1547. struct dp_pdev *pdev =
  1548. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1549. struct hal_srng *wbm_srng = (struct hal_srng *)
  1550. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1551. struct dp_ipa_resources *ipa_res;
  1552. QDF_STATUS result;
  1553. if (!pdev) {
  1554. dp_err("Invalid instance");
  1555. return QDF_STATUS_E_FAILURE;
  1556. }
  1557. ipa_res = &pdev->ipa_resource;
  1558. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  1559. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  1560. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true);
  1561. result = qdf_ipa_wdi_enable_pipes();
  1562. if (result) {
  1563. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1564. "%s: Enable WDI PIPE fail, code %d",
  1565. __func__, result);
  1566. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1567. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  1568. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1569. return QDF_STATUS_E_FAILURE;
  1570. }
  1571. if (soc->ipa_first_tx_db_access) {
  1572. hal_srng_dst_init_hp(
  1573. soc->hal_soc, wbm_srng,
  1574. ipa_res->tx_comp_doorbell_vaddr);
  1575. soc->ipa_first_tx_db_access = false;
  1576. }
  1577. return QDF_STATUS_SUCCESS;
  1578. }
  1579. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1580. {
  1581. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1582. struct dp_pdev *pdev =
  1583. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1584. QDF_STATUS result;
  1585. struct dp_ipa_resources *ipa_res;
  1586. if (!pdev) {
  1587. dp_err("Invalid instance");
  1588. return QDF_STATUS_E_FAILURE;
  1589. }
  1590. ipa_res = &pdev->ipa_resource;
  1591. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  1592. /*
  1593. * Reset the tx completion doorbell address before invoking IPA disable
  1594. * pipes API to ensure that there is no access to IPA tx doorbell
  1595. * address post disable pipes.
  1596. */
  1597. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  1598. result = qdf_ipa_wdi_disable_pipes();
  1599. if (result) {
  1600. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1601. "%s: Disable WDI PIPE fail, code %d",
  1602. __func__, result);
  1603. qdf_assert_always(0);
  1604. return QDF_STATUS_E_FAILURE;
  1605. }
  1606. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1607. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1608. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  1609. }
  1610. /**
  1611. * dp_ipa_set_perf_level() - Set IPA clock bandwidth based on data rates
  1612. * @client: Client type
  1613. * @max_supported_bw_mbps: Maximum bandwidth needed (in Mbps)
  1614. *
  1615. * Return: QDF_STATUS
  1616. */
  1617. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps)
  1618. {
  1619. qdf_ipa_wdi_perf_profile_t profile;
  1620. QDF_STATUS result;
  1621. profile.client = client;
  1622. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  1623. result = qdf_ipa_wdi_set_perf_profile(&profile);
  1624. if (result) {
  1625. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1626. "%s: ipa_wdi_set_perf_profile fail, code %d",
  1627. __func__, result);
  1628. return QDF_STATUS_E_FAILURE;
  1629. }
  1630. return QDF_STATUS_SUCCESS;
  1631. }
  1632. /**
  1633. * dp_ipa_intrabss_send - send IPA RX intra-bss frames
  1634. * @pdev: pdev
  1635. * @vdev: vdev
  1636. * @nbuf: skb
  1637. *
  1638. * Return: nbuf if TX fails and NULL if TX succeeds
  1639. */
  1640. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  1641. struct dp_vdev *vdev,
  1642. qdf_nbuf_t nbuf)
  1643. {
  1644. struct dp_peer *vdev_peer;
  1645. uint16_t len;
  1646. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  1647. if (qdf_unlikely(!vdev_peer))
  1648. return nbuf;
  1649. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  1650. len = qdf_nbuf_len(nbuf);
  1651. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  1652. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.fail, 1, len);
  1653. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1654. return nbuf;
  1655. }
  1656. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.pkts, 1, len);
  1657. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1658. return NULL;
  1659. }
  1660. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1661. qdf_nbuf_t nbuf, bool *fwd_success)
  1662. {
  1663. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1664. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  1665. DP_MOD_ID_IPA);
  1666. struct dp_pdev *pdev;
  1667. struct dp_peer *da_peer;
  1668. struct dp_peer *sa_peer;
  1669. qdf_nbuf_t nbuf_copy;
  1670. uint8_t da_is_bcmc;
  1671. struct ethhdr *eh;
  1672. bool status = false;
  1673. *fwd_success = false; /* set default as failure */
  1674. /*
  1675. * WDI 3.0 skb->cb[] info from IPA driver
  1676. * skb->cb[0] = vdev_id
  1677. * skb->cb[1].bit#1 = da_is_bcmc
  1678. */
  1679. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  1680. if (qdf_unlikely(!vdev))
  1681. return false;
  1682. pdev = vdev->pdev;
  1683. if (qdf_unlikely(!pdev))
  1684. goto out;
  1685. /* no fwd for station mode and just pass up to stack */
  1686. if (vdev->opmode == wlan_op_mode_sta)
  1687. goto out;
  1688. if (da_is_bcmc) {
  1689. nbuf_copy = qdf_nbuf_copy(nbuf);
  1690. if (!nbuf_copy)
  1691. goto out;
  1692. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  1693. qdf_nbuf_free(nbuf_copy);
  1694. else
  1695. *fwd_success = true;
  1696. /* return false to pass original pkt up to stack */
  1697. goto out;
  1698. }
  1699. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  1700. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  1701. goto out;
  1702. da_peer = dp_peer_find_hash_find(soc, eh->h_dest, 0, vdev->vdev_id,
  1703. DP_MOD_ID_IPA);
  1704. if (!da_peer)
  1705. goto out;
  1706. dp_peer_unref_delete(da_peer, DP_MOD_ID_IPA);
  1707. sa_peer = dp_peer_find_hash_find(soc, eh->h_source, 0, vdev->vdev_id,
  1708. DP_MOD_ID_IPA);
  1709. if (!sa_peer)
  1710. goto out;
  1711. dp_peer_unref_delete(sa_peer, DP_MOD_ID_IPA);
  1712. /*
  1713. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  1714. * Need to add skb to internal tracking table to avoid nbuf memory
  1715. * leak check for unallocated skb.
  1716. */
  1717. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  1718. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  1719. qdf_nbuf_free(nbuf);
  1720. else
  1721. *fwd_success = true;
  1722. status = true;
  1723. out:
  1724. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  1725. return status;
  1726. }
  1727. #ifdef MDM_PLATFORM
  1728. bool dp_ipa_is_mdm_platform(void)
  1729. {
  1730. return true;
  1731. }
  1732. #else
  1733. bool dp_ipa_is_mdm_platform(void)
  1734. {
  1735. return false;
  1736. }
  1737. #endif
  1738. /**
  1739. * dp_ipa_frag_nbuf_linearize - linearize nbuf for IPA
  1740. * @soc: soc
  1741. * @nbuf: source skb
  1742. *
  1743. * Return: new nbuf if success and otherwise NULL
  1744. */
  1745. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  1746. qdf_nbuf_t nbuf)
  1747. {
  1748. uint8_t *src_nbuf_data;
  1749. uint8_t *dst_nbuf_data;
  1750. qdf_nbuf_t dst_nbuf;
  1751. qdf_nbuf_t temp_nbuf = nbuf;
  1752. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  1753. bool is_nbuf_head = true;
  1754. uint32_t copy_len = 0;
  1755. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  1756. RX_BUFFER_RESERVATION,
  1757. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  1758. if (!dst_nbuf) {
  1759. dp_err_rl("nbuf allocate fail");
  1760. return NULL;
  1761. }
  1762. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  1763. qdf_nbuf_free(dst_nbuf);
  1764. dp_err_rl("nbuf is jumbo data");
  1765. return NULL;
  1766. }
  1767. /* prepeare to copy all data into new skb */
  1768. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  1769. while (temp_nbuf) {
  1770. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  1771. /* first head nbuf */
  1772. if (is_nbuf_head) {
  1773. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  1774. RX_PKT_TLVS_LEN);
  1775. /* leave extra 2 bytes L3_HEADER_PADDING */
  1776. dst_nbuf_data += (RX_PKT_TLVS_LEN + L3_HEADER_PADDING);
  1777. src_nbuf_data += RX_PKT_TLVS_LEN;
  1778. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  1779. RX_PKT_TLVS_LEN;
  1780. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  1781. is_nbuf_head = false;
  1782. } else {
  1783. copy_len = qdf_nbuf_len(temp_nbuf);
  1784. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  1785. }
  1786. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  1787. dst_nbuf_data += copy_len;
  1788. }
  1789. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  1790. /* copy is done, free original nbuf */
  1791. qdf_nbuf_free(nbuf);
  1792. return dst_nbuf;
  1793. }
  1794. /**
  1795. * dp_ipa_handle_rx_reo_reinject - Handle RX REO reinject skb buffer
  1796. * @soc: soc
  1797. * @nbuf: skb
  1798. *
  1799. * Return: nbuf if success and otherwise NULL
  1800. */
  1801. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  1802. {
  1803. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1804. return nbuf;
  1805. /* WLAN IPA is run-time disabled */
  1806. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  1807. return nbuf;
  1808. if (!qdf_nbuf_is_frag(nbuf))
  1809. return nbuf;
  1810. /* linearize skb for IPA */
  1811. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  1812. }
  1813. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  1814. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1815. {
  1816. QDF_STATUS ret;
  1817. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1818. struct dp_pdev *pdev =
  1819. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1820. if (!pdev) {
  1821. dp_err("%s invalid instance", __func__);
  1822. return QDF_STATUS_E_FAILURE;
  1823. }
  1824. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1825. dp_debug("SMMU S1 disabled");
  1826. return QDF_STATUS_SUCCESS;
  1827. }
  1828. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true);
  1829. return ret;
  1830. }
  1831. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  1832. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1833. {
  1834. QDF_STATUS ret;
  1835. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1836. struct dp_pdev *pdev =
  1837. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1838. if (!pdev) {
  1839. dp_err("%s invalid instance", __func__);
  1840. return QDF_STATUS_E_FAILURE;
  1841. }
  1842. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1843. dp_debug("SMMU S1 disabled");
  1844. return QDF_STATUS_SUCCESS;
  1845. }
  1846. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false);
  1847. return ret;
  1848. }
  1849. #endif