hal_6390_rx.h 23 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "qdf_util.h"
  19. #include "qdf_types.h"
  20. #include "qdf_lock.h"
  21. #include "qdf_mem.h"
  22. #include "qdf_nbuf.h"
  23. #include "tcl_data_cmd.h"
  24. #include "mac_tcl_reg_seq_hwioreg.h"
  25. #include "phyrx_rssi_legacy.h"
  26. #include "rx_msdu_start.h"
  27. #include "tlv_tag_def.h"
  28. #include "hal_hw_headers.h"
  29. #include "hal_internal.h"
  30. #include "cdp_txrx_mon_struct.h"
  31. #include "qdf_trace.h"
  32. #include "hal_rx.h"
  33. #include "hal_tx.h"
  34. #include "dp_types.h"
  35. #include "hal_api_mon.h"
  36. #include "phyrx_other_receive_info_ru_details.h"
  37. #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
  38. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  39. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
  40. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
  41. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
  42. #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
  43. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  44. RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
  45. RX_MSDU_END_5_DA_IS_MCBC_MASK, \
  46. RX_MSDU_END_5_DA_IS_MCBC_LSB))
  47. #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
  48. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  49. RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
  50. RX_MSDU_END_5_SA_IS_VALID_MASK, \
  51. RX_MSDU_END_5_SA_IS_VALID_LSB))
  52. #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
  53. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  54. RX_MSDU_END_13_SA_IDX_OFFSET)), \
  55. RX_MSDU_END_13_SA_IDX_MASK, \
  56. RX_MSDU_END_13_SA_IDX_LSB))
  57. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  58. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  59. RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
  60. RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
  61. RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
  62. #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
  63. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  64. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
  65. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
  66. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
  67. #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
  68. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  69. RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
  70. RX_MPDU_INFO_4_PN_31_0_MASK, \
  71. RX_MPDU_INFO_4_PN_31_0_LSB))
  72. #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
  73. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  74. RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
  75. RX_MPDU_INFO_5_PN_63_32_MASK, \
  76. RX_MPDU_INFO_5_PN_63_32_LSB))
  77. #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
  78. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  79. RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
  80. RX_MPDU_INFO_6_PN_95_64_MASK, \
  81. RX_MPDU_INFO_6_PN_95_64_LSB))
  82. #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
  83. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  84. RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
  85. RX_MPDU_INFO_7_PN_127_96_MASK, \
  86. RX_MPDU_INFO_7_PN_127_96_LSB))
  87. #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
  88. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  89. RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
  90. RX_MSDU_END_5_FIRST_MSDU_MASK, \
  91. RX_MSDU_END_5_FIRST_MSDU_LSB))
  92. #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
  93. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  94. RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
  95. RX_MSDU_END_5_DA_IS_VALID_MASK, \
  96. RX_MSDU_END_5_DA_IS_VALID_LSB))
  97. #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
  98. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  99. RX_MSDU_END_5_LAST_MSDU_OFFSET)), \
  100. RX_MSDU_END_5_LAST_MSDU_MASK, \
  101. RX_MSDU_END_5_LAST_MSDU_LSB))
  102. #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
  103. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  104. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
  105. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
  106. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
  107. #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
  108. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  109. RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
  110. RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
  111. RX_MPDU_INFO_1_SW_PEER_ID_LSB))
  112. #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
  113. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  114. RX_MPDU_INFO_2_TO_DS_OFFSET)), \
  115. RX_MPDU_INFO_2_TO_DS_MASK, \
  116. RX_MPDU_INFO_2_TO_DS_LSB))
  117. #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
  118. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  119. RX_MPDU_INFO_2_FR_DS_OFFSET)), \
  120. RX_MPDU_INFO_2_FR_DS_MASK, \
  121. RX_MPDU_INFO_2_FR_DS_LSB))
  122. #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
  123. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  124. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
  125. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \
  126. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB))
  127. #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
  128. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  129. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \
  130. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \
  131. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB))
  132. #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
  133. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  134. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
  135. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
  136. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
  137. #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
  138. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  139. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
  140. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
  141. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
  142. #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
  143. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  144. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \
  145. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \
  146. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB))
  147. #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
  148. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  149. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
  150. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
  151. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
  152. #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
  153. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  154. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
  155. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
  156. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
  157. #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
  158. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  159. RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \
  160. RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \
  161. RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB))
  162. #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
  163. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  164. RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
  165. RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
  166. RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
  167. #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
  168. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  169. RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
  170. RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
  171. RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
  172. #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
  173. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  174. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
  175. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
  176. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
  177. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  178. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  179. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  180. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  181. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  182. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  183. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  184. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  185. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  186. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  187. #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
  188. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  189. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
  190. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
  191. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
  192. #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
  193. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  194. RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
  195. RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
  196. RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
  197. #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
  198. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  199. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \
  200. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \
  201. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
  202. #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
  203. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  204. RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
  205. RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
  206. RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
  207. #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
  208. (uint8_t *)(link_desc_va) + \
  209. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  210. #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
  211. (uint8_t *)(msdu0) + \
  212. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  213. #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
  214. (uint8_t *)(ent_ring_desc) + \
  215. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  216. #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
  217. (uint8_t *)(dst_ring_desc) + \
  218. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  219. #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
  220. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID)
  221. #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
  222. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS)
  223. #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
  224. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID)
  225. #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
  226. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID)
  227. #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
  228. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY)
  229. #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
  230. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID)
  231. #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
  232. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID)
  233. #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
  234. do { \
  235. reg_val &= \
  236. ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\
  237. HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \
  238. HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
  239. reg_val |= \
  240. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  241. FRAGMENT_DEST_RING, \
  242. (reo_params)->frag_dst_ring) | \
  243. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  244. AGING_LIST_ENABLE, 1) |\
  245. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  246. AGING_FLUSH_ENABLE, 1);\
  247. HAL_REG_WRITE((soc), \
  248. HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
  249. SEQ_WCSS_UMAC_REO_REG_OFFSET), \
  250. (reg_val)); \
  251. } while (0)
  252. #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
  253. ((struct rx_msdu_desc_info *) \
  254. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  255. UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
  256. #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
  257. ((struct rx_msdu_details *) \
  258. _OFFSET_TO_BYTE_PTR((link_desc),\
  259. UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
  260. #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
  261. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  262. RX_MSDU_END_14_FLOW_IDX_OFFSET)), \
  263. RX_MSDU_END_14_FLOW_IDX_MASK, \
  264. RX_MSDU_END_14_FLOW_IDX_LSB))
  265. #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
  266. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  267. RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \
  268. RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
  269. RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
  270. #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
  271. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  272. RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
  273. RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
  274. RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
  275. #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
  276. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  277. RX_MSDU_END_15_FSE_METADATA_OFFSET)), \
  278. RX_MSDU_END_15_FSE_METADATA_MASK, \
  279. RX_MSDU_END_15_FSE_METADATA_LSB))
  280. #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
  281. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  282. RX_MSDU_END_16_CCE_METADATA_OFFSET)), \
  283. RX_MSDU_END_16_CCE_METADATA_MASK, \
  284. RX_MSDU_END_16_CCE_METADATA_LSB))
  285. #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
  286. (_HAL_MS( \
  287. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  288. msdu_end_tlv.rx_msdu_end), \
  289. RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \
  290. RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \
  291. RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB))
  292. /*
  293. * hal_rx_msdu_start_nss_get_6390(): API to get the NSS
  294. * Interval from rx_msdu_start
  295. *
  296. * @buf: pointer to the start of RX PKT TLV header
  297. * Return: uint32_t(nss)
  298. */
  299. static uint32_t
  300. hal_rx_msdu_start_nss_get_6390(uint8_t *buf)
  301. {
  302. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  303. struct rx_msdu_start *msdu_start =
  304. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  305. uint8_t mimo_ss_bitmap;
  306. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  307. return qdf_get_hweight8(mimo_ss_bitmap);
  308. }
  309. /**
  310. * hal_rx_mon_hw_desc_get_mpdu_status_6390(): Retrieve MPDU status
  311. *
  312. * @ hw_desc_addr: Start address of Rx HW TLVs
  313. * @ rs: Status for monitor mode
  314. *
  315. * Return: void
  316. */
  317. static void hal_rx_mon_hw_desc_get_mpdu_status_6390(void *hw_desc_addr,
  318. struct mon_rx_status *rs)
  319. {
  320. struct rx_msdu_start *rx_msdu_start;
  321. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  322. uint32_t reg_value;
  323. const uint32_t sgi_hw_to_cdp[] = {
  324. CDP_SGI_0_8_US,
  325. CDP_SGI_0_4_US,
  326. CDP_SGI_1_6_US,
  327. CDP_SGI_3_2_US,
  328. };
  329. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  330. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  331. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  332. RX_MSDU_START_5, USER_RSSI);
  333. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  334. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  335. rs->sgi = sgi_hw_to_cdp[reg_value];
  336. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  337. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  338. /* TODO: rs->beamformed should be set for SU beamforming also */
  339. }
  340. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  341. static uint32_t hal_get_link_desc_size_6390(void)
  342. {
  343. return LINK_DESC_SIZE;
  344. }
  345. /*
  346. * hal_rx_get_tlv_6390(): API to get the tlv
  347. *
  348. * @rx_tlv: TLV data extracted from the rx packet
  349. * Return: uint8_t
  350. */
  351. static uint8_t hal_rx_get_tlv_6390(void *rx_tlv)
  352. {
  353. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  354. }
  355. /**
  356. * hal_rx_proc_phyrx_other_receive_info_tlv_6390()
  357. * - process other receive info TLV
  358. * @rx_tlv_hdr: pointer to TLV header
  359. * @ppdu_info: pointer to ppdu_info
  360. *
  361. * Return: None
  362. */
  363. static
  364. void hal_rx_proc_phyrx_other_receive_info_tlv_6390(void *rx_tlv_hdr,
  365. void *ppdu_info_handle)
  366. {
  367. uint32_t tlv_tag, tlv_len;
  368. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  369. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  370. void *other_tlv_hdr = NULL;
  371. void *other_tlv = NULL;
  372. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  373. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  374. temp_len = 0;
  375. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  376. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  377. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  378. temp_len += other_tlv_len;
  379. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  380. switch (other_tlv_tag) {
  381. default:
  382. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  383. "%s unhandled TLV type: %d, TLV len:%d",
  384. __func__, other_tlv_tag, other_tlv_len);
  385. break;
  386. }
  387. }
  388. /**
  389. * hal_rx_dump_msdu_start_tlv_6390() : dump RX msdu_start TLV in structured
  390. * human readable format.
  391. * @ msdu_start: pointer the msdu_start TLV in pkt.
  392. * @ dbg_level: log level.
  393. *
  394. * Return: void
  395. */
  396. static void hal_rx_dump_msdu_start_tlv_6390(void *msdustart, uint8_t dbg_level)
  397. {
  398. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  399. hal_verbose_debug(
  400. "rx_msdu_start tlv (1/2) - "
  401. "rxpcu_mpdu_filter_in_category: %x "
  402. "sw_frame_group_id: %x "
  403. "phy_ppdu_id: %x "
  404. "msdu_length: %x "
  405. "ipsec_esp: %x "
  406. "l3_offset: %x "
  407. "ipsec_ah: %x "
  408. "l4_offset: %x "
  409. "msdu_number: %x "
  410. "decap_format: %x "
  411. "ipv4_proto: %x "
  412. "ipv6_proto: %x "
  413. "tcp_proto: %x "
  414. "udp_proto: %x "
  415. "ip_frag: %x "
  416. "tcp_only_ack: %x "
  417. "da_is_bcast_mcast: %x "
  418. "ip4_protocol_ip6_next_header: %x "
  419. "toeplitz_hash_2_or_4: %x "
  420. "flow_id_toeplitz: %x "
  421. "user_rssi: %x "
  422. "pkt_type: %x "
  423. "stbc: %x "
  424. "sgi: %x "
  425. "rate_mcs: %x "
  426. "receive_bandwidth: %x "
  427. "reception_type: %x "
  428. "ppdu_start_timestamp: %u ",
  429. msdu_start->rxpcu_mpdu_filter_in_category,
  430. msdu_start->sw_frame_group_id,
  431. msdu_start->phy_ppdu_id,
  432. msdu_start->msdu_length,
  433. msdu_start->ipsec_esp,
  434. msdu_start->l3_offset,
  435. msdu_start->ipsec_ah,
  436. msdu_start->l4_offset,
  437. msdu_start->msdu_number,
  438. msdu_start->decap_format,
  439. msdu_start->ipv4_proto,
  440. msdu_start->ipv6_proto,
  441. msdu_start->tcp_proto,
  442. msdu_start->udp_proto,
  443. msdu_start->ip_frag,
  444. msdu_start->tcp_only_ack,
  445. msdu_start->da_is_bcast_mcast,
  446. msdu_start->ip4_protocol_ip6_next_header,
  447. msdu_start->toeplitz_hash_2_or_4,
  448. msdu_start->flow_id_toeplitz,
  449. msdu_start->user_rssi,
  450. msdu_start->pkt_type,
  451. msdu_start->stbc,
  452. msdu_start->sgi,
  453. msdu_start->rate_mcs,
  454. msdu_start->receive_bandwidth,
  455. msdu_start->reception_type,
  456. msdu_start->ppdu_start_timestamp);
  457. hal_verbose_debug(
  458. "rx_msdu_start tlv (2/2) - "
  459. "sw_phy_meta_data: %x ",
  460. msdu_start->sw_phy_meta_data);
  461. }
  462. /**
  463. * hal_rx_dump_msdu_end_tlv_6390: dump RX msdu_end TLV in structured
  464. * human readable format.
  465. * @ msdu_end: pointer the msdu_end TLV in pkt.
  466. * @ dbg_level: log level.
  467. *
  468. * Return: void
  469. */
  470. static void hal_rx_dump_msdu_end_tlv_6390(void *msduend,
  471. uint8_t dbg_level)
  472. {
  473. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  474. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  475. "rx_msdu_end tlv (1/2) - "
  476. "rxpcu_mpdu_filter_in_category: %x "
  477. "sw_frame_group_id: %x "
  478. "phy_ppdu_id: %x "
  479. "ip_hdr_chksum: %x "
  480. "tcp_udp_chksum: %x "
  481. "key_id_octet: %x "
  482. "cce_super_rule: %x "
  483. "cce_classify_not_done_truncat: %x "
  484. "cce_classify_not_done_cce_dis: %x "
  485. "ext_wapi_pn_63_48: %x "
  486. "ext_wapi_pn_95_64: %x "
  487. "ext_wapi_pn_127_96: %x "
  488. "reported_mpdu_length: %x "
  489. "first_msdu: %x "
  490. "last_msdu: %x "
  491. "sa_idx_timeout: %x "
  492. "da_idx_timeout: %x "
  493. "msdu_limit_error: %x "
  494. "flow_idx_timeout: %x "
  495. "flow_idx_invalid: %x "
  496. "wifi_parser_error: %x "
  497. "amsdu_parser_error: %x",
  498. msdu_end->rxpcu_mpdu_filter_in_category,
  499. msdu_end->sw_frame_group_id,
  500. msdu_end->phy_ppdu_id,
  501. msdu_end->ip_hdr_chksum,
  502. msdu_end->tcp_udp_chksum,
  503. msdu_end->key_id_octet,
  504. msdu_end->cce_super_rule,
  505. msdu_end->cce_classify_not_done_truncate,
  506. msdu_end->cce_classify_not_done_cce_dis,
  507. msdu_end->ext_wapi_pn_63_48,
  508. msdu_end->ext_wapi_pn_95_64,
  509. msdu_end->ext_wapi_pn_127_96,
  510. msdu_end->reported_mpdu_length,
  511. msdu_end->first_msdu,
  512. msdu_end->last_msdu,
  513. msdu_end->sa_idx_timeout,
  514. msdu_end->da_idx_timeout,
  515. msdu_end->msdu_limit_error,
  516. msdu_end->flow_idx_timeout,
  517. msdu_end->flow_idx_invalid,
  518. msdu_end->wifi_parser_error,
  519. msdu_end->amsdu_parser_error);
  520. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  521. "rx_msdu_end tlv (2/2)- "
  522. "sa_is_valid: %x "
  523. "da_is_valid: %x "
  524. "da_is_mcbc: %x "
  525. "l3_header_padding: %x "
  526. "ipv6_options_crc: %x "
  527. "tcp_seq_number: %x "
  528. "tcp_ack_number: %x "
  529. "tcp_flag: %x "
  530. "lro_eligible: %x "
  531. "window_size: %x "
  532. "da_offset: %x "
  533. "sa_offset: %x "
  534. "da_offset_valid: %x "
  535. "sa_offset_valid: %x "
  536. "rule_indication_31_0: %x "
  537. "rule_indication_63_32: %x "
  538. "sa_idx: %x "
  539. "da_idx: %x "
  540. "msdu_drop: %x "
  541. "reo_destination_indication: %x "
  542. "flow_idx: %x "
  543. "fse_metadata: %x "
  544. "cce_metadata: %x "
  545. "sa_sw_peer_id: %x ",
  546. msdu_end->sa_is_valid,
  547. msdu_end->da_is_valid,
  548. msdu_end->da_is_mcbc,
  549. msdu_end->l3_header_padding,
  550. msdu_end->ipv6_options_crc,
  551. msdu_end->tcp_seq_number,
  552. msdu_end->tcp_ack_number,
  553. msdu_end->tcp_flag,
  554. msdu_end->lro_eligible,
  555. msdu_end->window_size,
  556. msdu_end->da_offset,
  557. msdu_end->sa_offset,
  558. msdu_end->da_offset_valid,
  559. msdu_end->sa_offset_valid,
  560. msdu_end->rule_indication_31_0,
  561. msdu_end->rule_indication_63_32,
  562. msdu_end->sa_idx,
  563. msdu_end->da_idx_or_sw_peer_id,
  564. msdu_end->msdu_drop,
  565. msdu_end->reo_destination_indication,
  566. msdu_end->flow_idx,
  567. msdu_end->fse_metadata,
  568. msdu_end->cce_metadata,
  569. msdu_end->sa_sw_peer_id);
  570. }
  571. /*
  572. * Get tid from RX_MPDU_START
  573. */
  574. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  575. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  576. RX_MPDU_INFO_3_TID_OFFSET)), \
  577. RX_MPDU_INFO_3_TID_MASK, \
  578. RX_MPDU_INFO_3_TID_LSB))
  579. static uint32_t hal_rx_mpdu_start_tid_get_6390(uint8_t *buf)
  580. {
  581. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  582. struct rx_mpdu_start *mpdu_start =
  583. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  584. uint32_t tid;
  585. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  586. return tid;
  587. }
  588. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  589. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  590. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  591. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  592. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  593. /*
  594. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  595. * Interval from rx_msdu_start
  596. *
  597. * @buf: pointer to the start of RX PKT TLV header
  598. * Return: uint32_t(reception_type)
  599. */
  600. static
  601. uint32_t hal_rx_msdu_start_reception_type_get_6390(uint8_t *buf)
  602. {
  603. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  604. struct rx_msdu_start *msdu_start =
  605. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  606. uint32_t reception_type;
  607. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  608. return reception_type;
  609. }
  610. #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
  611. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  612. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
  613. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \
  614. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
  615. /**
  616. * hal_rx_msdu_end_da_idx_get_6390: API to get da_idx
  617. * from rx_msdu_end TLV
  618. *
  619. * @ buf: pointer to the start of RX PKT TLV headers
  620. * Return: da index
  621. */
  622. static uint16_t hal_rx_msdu_end_da_idx_get_6390(uint8_t *buf)
  623. {
  624. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  625. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  626. uint16_t da_idx;
  627. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  628. return da_idx;
  629. }