dp_tx.c 116 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. /* TODO Add support in TSO */
  43. #define DP_DESC_NUM_FRAG(x) 0
  44. /* disable TQM_BYPASS */
  45. #define TQM_BYPASS_WAR 0
  46. /* invalid peer id for reinject*/
  47. #define DP_INVALID_PEER 0XFFFE
  48. /*mapping between hal encrypt type and cdp_sec_type*/
  49. #define MAX_CDP_SEC_TYPE 12
  50. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  51. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  52. HAL_TX_ENCRYPT_TYPE_WEP_128,
  53. HAL_TX_ENCRYPT_TYPE_WEP_104,
  54. HAL_TX_ENCRYPT_TYPE_WEP_40,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  58. HAL_TX_ENCRYPT_TYPE_WAPI,
  59. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  62. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  63. #ifdef QCA_TX_LIMIT_CHECK
  64. /**
  65. * dp_tx_limit_check - Check if allocated tx descriptors reached
  66. * soc max limit and pdev max limit
  67. * @vdev: DP vdev handle
  68. *
  69. * Return: true if allocated tx descriptors reached max configured value, else
  70. * false
  71. */
  72. static inline bool
  73. dp_tx_limit_check(struct dp_vdev *vdev)
  74. {
  75. struct dp_pdev *pdev = vdev->pdev;
  76. struct dp_soc *soc = pdev->soc;
  77. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  78. soc->num_tx_allowed) {
  79. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  80. "%s: queued packets are more than max tx, drop the frame",
  81. __func__);
  82. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  83. return true;
  84. }
  85. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  86. pdev->num_tx_allowed) {
  87. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  88. "%s: queued packets are more than max tx, drop the frame",
  89. __func__);
  90. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  91. return true;
  92. }
  93. return false;
  94. }
  95. /**
  96. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  97. * @vdev: DP pdev handle
  98. *
  99. * Return: void
  100. */
  101. static inline void
  102. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  103. {
  104. struct dp_soc *soc = pdev->soc;
  105. qdf_atomic_inc(&pdev->num_tx_outstanding);
  106. qdf_atomic_inc(&soc->num_tx_outstanding);
  107. }
  108. /**
  109. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  110. * @vdev: DP pdev handle
  111. *
  112. * Return: void
  113. */
  114. static inline void
  115. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  116. {
  117. struct dp_soc *soc = pdev->soc;
  118. qdf_atomic_dec(&pdev->num_tx_outstanding);
  119. qdf_atomic_dec(&soc->num_tx_outstanding);
  120. }
  121. #else //QCA_TX_LIMIT_CHECK
  122. static inline bool
  123. dp_tx_limit_check(struct dp_vdev *vdev)
  124. {
  125. return false;
  126. }
  127. static inline void
  128. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  129. {
  130. qdf_atomic_inc(&pdev->num_tx_outstanding);
  131. }
  132. static inline void
  133. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  134. {
  135. qdf_atomic_dec(&pdev->num_tx_outstanding);
  136. }
  137. #endif //QCA_TX_LIMIT_CHECK
  138. #if defined(FEATURE_TSO)
  139. /**
  140. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  141. *
  142. * @soc - core txrx main context
  143. * @seg_desc - tso segment descriptor
  144. * @num_seg_desc - tso number segment descriptor
  145. */
  146. static void dp_tx_tso_unmap_segment(
  147. struct dp_soc *soc,
  148. struct qdf_tso_seg_elem_t *seg_desc,
  149. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  150. {
  151. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  152. if (qdf_unlikely(!seg_desc)) {
  153. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  154. __func__, __LINE__);
  155. qdf_assert(0);
  156. } else if (qdf_unlikely(!num_seg_desc)) {
  157. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  158. __func__, __LINE__);
  159. qdf_assert(0);
  160. } else {
  161. bool is_last_seg;
  162. /* no tso segment left to do dma unmap */
  163. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  164. return;
  165. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  166. true : false;
  167. qdf_nbuf_unmap_tso_segment(soc->osdev,
  168. seg_desc, is_last_seg);
  169. num_seg_desc->num_seg.tso_cmn_num_seg--;
  170. }
  171. }
  172. /**
  173. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  174. * back to the freelist
  175. *
  176. * @soc - soc device handle
  177. * @tx_desc - Tx software descriptor
  178. */
  179. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  180. struct dp_tx_desc_s *tx_desc)
  181. {
  182. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  183. if (qdf_unlikely(!tx_desc->tso_desc)) {
  184. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  185. "%s %d TSO desc is NULL!",
  186. __func__, __LINE__);
  187. qdf_assert(0);
  188. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  189. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  190. "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  195. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  196. /* Add the tso num segment into the free list */
  197. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  198. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  199. tx_desc->tso_num_desc);
  200. tx_desc->tso_num_desc = NULL;
  201. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  202. }
  203. /* Add the tso segment into the free list*/
  204. dp_tx_tso_desc_free(soc,
  205. tx_desc->pool_id, tx_desc->tso_desc);
  206. tx_desc->tso_desc = NULL;
  207. }
  208. }
  209. #else
  210. static void dp_tx_tso_unmap_segment(
  211. struct dp_soc *soc,
  212. struct qdf_tso_seg_elem_t *seg_desc,
  213. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  214. {
  215. }
  216. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc)
  218. {
  219. }
  220. #endif
  221. /**
  222. * dp_tx_desc_release() - Release Tx Descriptor
  223. * @tx_desc : Tx Descriptor
  224. * @desc_pool_id: Descriptor Pool ID
  225. *
  226. * Deallocate all resources attached to Tx descriptor and free the Tx
  227. * descriptor.
  228. *
  229. * Return:
  230. */
  231. static void
  232. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  233. {
  234. struct dp_pdev *pdev = tx_desc->pdev;
  235. struct dp_soc *soc;
  236. uint8_t comp_status = 0;
  237. qdf_assert(pdev);
  238. soc = pdev->soc;
  239. if (tx_desc->frm_type == dp_tx_frm_tso)
  240. dp_tx_tso_desc_release(soc, tx_desc);
  241. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  242. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  243. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  244. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  245. dp_tx_outstanding_dec(pdev);
  246. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  247. qdf_atomic_dec(&pdev->num_tx_exception);
  248. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  249. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  250. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  251. soc->hal_soc);
  252. else
  253. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  255. "Tx Completion Release desc %d status %d outstanding %d",
  256. tx_desc->id, comp_status,
  257. qdf_atomic_read(&pdev->num_tx_outstanding));
  258. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  259. return;
  260. }
  261. /**
  262. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  263. * @vdev: DP vdev Handle
  264. * @nbuf: skb
  265. * @msdu_info: msdu_info required to create HTT metadata
  266. *
  267. * Prepares and fills HTT metadata in the frame pre-header for special frames
  268. * that should be transmitted using varying transmit parameters.
  269. * There are 2 VDEV modes that currently needs this special metadata -
  270. * 1) Mesh Mode
  271. * 2) DSRC Mode
  272. *
  273. * Return: HTT metadata size
  274. *
  275. */
  276. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  277. struct dp_tx_msdu_info_s *msdu_info)
  278. {
  279. uint32_t *meta_data = msdu_info->meta_data;
  280. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  281. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  282. uint8_t htt_desc_size;
  283. /* Size rounded of multiple of 8 bytes */
  284. uint8_t htt_desc_size_aligned;
  285. uint8_t *hdr = NULL;
  286. /*
  287. * Metadata - HTT MSDU Extension header
  288. */
  289. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  290. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  291. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  292. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  293. meta_data[0])) {
  294. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  295. htt_desc_size_aligned)) {
  296. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  297. htt_desc_size_aligned);
  298. if (!nbuf) {
  299. /*
  300. * qdf_nbuf_realloc_headroom won't do skb_clone
  301. * as skb_realloc_headroom does. so, no free is
  302. * needed here.
  303. */
  304. DP_STATS_INC(vdev,
  305. tx_i.dropped.headroom_insufficient,
  306. 1);
  307. qdf_print(" %s[%d] skb_realloc_headroom failed",
  308. __func__, __LINE__);
  309. return 0;
  310. }
  311. }
  312. /* Fill and add HTT metaheader */
  313. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  314. if (!hdr) {
  315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  316. "Error in filling HTT metadata");
  317. return 0;
  318. }
  319. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  320. } else if (vdev->opmode == wlan_op_mode_ocb) {
  321. /* Todo - Add support for DSRC */
  322. }
  323. return htt_desc_size_aligned;
  324. }
  325. /**
  326. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  327. * @tso_seg: TSO segment to process
  328. * @ext_desc: Pointer to MSDU extension descriptor
  329. *
  330. * Return: void
  331. */
  332. #if defined(FEATURE_TSO)
  333. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  334. void *ext_desc)
  335. {
  336. uint8_t num_frag;
  337. uint32_t tso_flags;
  338. /*
  339. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  340. * tcp_flag_mask
  341. *
  342. * Checksum enable flags are set in TCL descriptor and not in Extension
  343. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  344. */
  345. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  346. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  347. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  348. tso_seg->tso_flags.ip_len);
  349. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  350. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  351. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  352. uint32_t lo = 0;
  353. uint32_t hi = 0;
  354. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  355. (tso_seg->tso_frags[num_frag].length));
  356. qdf_dmaaddr_to_32s(
  357. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  358. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  359. tso_seg->tso_frags[num_frag].length);
  360. }
  361. return;
  362. }
  363. #else
  364. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  365. void *ext_desc)
  366. {
  367. return;
  368. }
  369. #endif
  370. #if defined(FEATURE_TSO)
  371. /**
  372. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  373. * allocated and free them
  374. *
  375. * @soc: soc handle
  376. * @free_seg: list of tso segments
  377. * @msdu_info: msdu descriptor
  378. *
  379. * Return - void
  380. */
  381. static void dp_tx_free_tso_seg_list(
  382. struct dp_soc *soc,
  383. struct qdf_tso_seg_elem_t *free_seg,
  384. struct dp_tx_msdu_info_s *msdu_info)
  385. {
  386. struct qdf_tso_seg_elem_t *next_seg;
  387. while (free_seg) {
  388. next_seg = free_seg->next;
  389. dp_tx_tso_desc_free(soc,
  390. msdu_info->tx_queue.desc_pool_id,
  391. free_seg);
  392. free_seg = next_seg;
  393. }
  394. }
  395. /**
  396. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  397. * allocated and free them
  398. *
  399. * @soc: soc handle
  400. * @free_num_seg: list of tso number segments
  401. * @msdu_info: msdu descriptor
  402. * Return - void
  403. */
  404. static void dp_tx_free_tso_num_seg_list(
  405. struct dp_soc *soc,
  406. struct qdf_tso_num_seg_elem_t *free_num_seg,
  407. struct dp_tx_msdu_info_s *msdu_info)
  408. {
  409. struct qdf_tso_num_seg_elem_t *next_num_seg;
  410. while (free_num_seg) {
  411. next_num_seg = free_num_seg->next;
  412. dp_tso_num_seg_free(soc,
  413. msdu_info->tx_queue.desc_pool_id,
  414. free_num_seg);
  415. free_num_seg = next_num_seg;
  416. }
  417. }
  418. /**
  419. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  420. * do dma unmap for each segment
  421. *
  422. * @soc: soc handle
  423. * @free_seg: list of tso segments
  424. * @num_seg_desc: tso number segment descriptor
  425. *
  426. * Return - void
  427. */
  428. static void dp_tx_unmap_tso_seg_list(
  429. struct dp_soc *soc,
  430. struct qdf_tso_seg_elem_t *free_seg,
  431. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  432. {
  433. struct qdf_tso_seg_elem_t *next_seg;
  434. if (qdf_unlikely(!num_seg_desc)) {
  435. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  436. return;
  437. }
  438. while (free_seg) {
  439. next_seg = free_seg->next;
  440. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  441. free_seg = next_seg;
  442. }
  443. }
  444. #ifdef FEATURE_TSO_STATS
  445. /**
  446. * dp_tso_get_stats_idx: Retrieve the tso packet id
  447. * @pdev - pdev handle
  448. *
  449. * Return: id
  450. */
  451. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  452. {
  453. uint32_t stats_idx;
  454. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  455. % CDP_MAX_TSO_PACKETS);
  456. return stats_idx;
  457. }
  458. #else
  459. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  460. {
  461. return 0;
  462. }
  463. #endif /* FEATURE_TSO_STATS */
  464. /**
  465. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  466. * free the tso segments descriptor and
  467. * tso num segments descriptor
  468. *
  469. * @soc: soc handle
  470. * @msdu_info: msdu descriptor
  471. * @tso_seg_unmap: flag to show if dma unmap is necessary
  472. *
  473. * Return - void
  474. */
  475. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  476. struct dp_tx_msdu_info_s *msdu_info,
  477. bool tso_seg_unmap)
  478. {
  479. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  480. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  481. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  482. tso_info->tso_num_seg_list;
  483. /* do dma unmap for each segment */
  484. if (tso_seg_unmap)
  485. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  486. /* free all tso number segment descriptor though looks only have 1 */
  487. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  488. /* free all tso segment descriptor */
  489. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  490. }
  491. /**
  492. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  493. * @vdev: virtual device handle
  494. * @msdu: network buffer
  495. * @msdu_info: meta data associated with the msdu
  496. *
  497. * Return: QDF_STATUS_SUCCESS success
  498. */
  499. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  500. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  501. {
  502. struct qdf_tso_seg_elem_t *tso_seg;
  503. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  504. struct dp_soc *soc = vdev->pdev->soc;
  505. struct dp_pdev *pdev = vdev->pdev;
  506. struct qdf_tso_info_t *tso_info;
  507. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  508. tso_info = &msdu_info->u.tso_info;
  509. tso_info->curr_seg = NULL;
  510. tso_info->tso_seg_list = NULL;
  511. tso_info->num_segs = num_seg;
  512. msdu_info->frm_type = dp_tx_frm_tso;
  513. tso_info->tso_num_seg_list = NULL;
  514. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  515. while (num_seg) {
  516. tso_seg = dp_tx_tso_desc_alloc(
  517. soc, msdu_info->tx_queue.desc_pool_id);
  518. if (tso_seg) {
  519. tso_seg->next = tso_info->tso_seg_list;
  520. tso_info->tso_seg_list = tso_seg;
  521. num_seg--;
  522. } else {
  523. dp_err_rl("Failed to alloc tso seg desc");
  524. DP_STATS_INC_PKT(vdev->pdev,
  525. tso_stats.tso_no_mem_dropped, 1,
  526. qdf_nbuf_len(msdu));
  527. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  528. return QDF_STATUS_E_NOMEM;
  529. }
  530. }
  531. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  532. tso_num_seg = dp_tso_num_seg_alloc(soc,
  533. msdu_info->tx_queue.desc_pool_id);
  534. if (tso_num_seg) {
  535. tso_num_seg->next = tso_info->tso_num_seg_list;
  536. tso_info->tso_num_seg_list = tso_num_seg;
  537. } else {
  538. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  539. __func__);
  540. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  541. return QDF_STATUS_E_NOMEM;
  542. }
  543. msdu_info->num_seg =
  544. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  545. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  546. msdu_info->num_seg);
  547. if (!(msdu_info->num_seg)) {
  548. /*
  549. * Free allocated TSO seg desc and number seg desc,
  550. * do unmap for segments if dma map has done.
  551. */
  552. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  553. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  554. return QDF_STATUS_E_INVAL;
  555. }
  556. tso_info->curr_seg = tso_info->tso_seg_list;
  557. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  558. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  559. msdu, msdu_info->num_seg);
  560. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  561. tso_info->msdu_stats_idx);
  562. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  563. return QDF_STATUS_SUCCESS;
  564. }
  565. #else
  566. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  567. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  568. {
  569. return QDF_STATUS_E_NOMEM;
  570. }
  571. #endif
  572. /**
  573. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  574. * @vdev: DP Vdev handle
  575. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  576. * @desc_pool_id: Descriptor Pool ID
  577. *
  578. * Return:
  579. */
  580. static
  581. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  582. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  583. {
  584. uint8_t i;
  585. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  586. struct dp_tx_seg_info_s *seg_info;
  587. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  588. struct dp_soc *soc = vdev->pdev->soc;
  589. /* Allocate an extension descriptor */
  590. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  591. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  592. if (!msdu_ext_desc) {
  593. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  594. return NULL;
  595. }
  596. if (msdu_info->exception_fw &&
  597. qdf_unlikely(vdev->mesh_vdev)) {
  598. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  599. &msdu_info->meta_data[0],
  600. sizeof(struct htt_tx_msdu_desc_ext2_t));
  601. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  602. }
  603. switch (msdu_info->frm_type) {
  604. case dp_tx_frm_sg:
  605. case dp_tx_frm_me:
  606. case dp_tx_frm_raw:
  607. seg_info = msdu_info->u.sg_info.curr_seg;
  608. /* Update the buffer pointers in MSDU Extension Descriptor */
  609. for (i = 0; i < seg_info->frag_cnt; i++) {
  610. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  611. seg_info->frags[i].paddr_lo,
  612. seg_info->frags[i].paddr_hi,
  613. seg_info->frags[i].len);
  614. }
  615. break;
  616. case dp_tx_frm_tso:
  617. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  618. &cached_ext_desc[0]);
  619. break;
  620. default:
  621. break;
  622. }
  623. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  624. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  625. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  626. msdu_ext_desc->vaddr);
  627. return msdu_ext_desc;
  628. }
  629. /**
  630. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  631. *
  632. * @skb: skb to be traced
  633. * @msdu_id: msdu_id of the packet
  634. * @vdev_id: vdev_id of the packet
  635. *
  636. * Return: None
  637. */
  638. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  639. uint8_t vdev_id)
  640. {
  641. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  642. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  643. DPTRACE(qdf_dp_trace_ptr(skb,
  644. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  645. QDF_TRACE_DEFAULT_PDEV_ID,
  646. qdf_nbuf_data_addr(skb),
  647. sizeof(qdf_nbuf_data(skb)),
  648. msdu_id, vdev_id));
  649. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  650. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  651. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  652. msdu_id, QDF_TX));
  653. }
  654. /**
  655. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  656. * @vdev: DP vdev handle
  657. * @nbuf: skb
  658. * @desc_pool_id: Descriptor pool ID
  659. * @meta_data: Metadata to the fw
  660. * @tx_exc_metadata: Handle that holds exception path metadata
  661. * Allocate and prepare Tx descriptor with msdu information.
  662. *
  663. * Return: Pointer to Tx Descriptor on success,
  664. * NULL on failure
  665. */
  666. static
  667. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  668. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  669. struct dp_tx_msdu_info_s *msdu_info,
  670. struct cdp_tx_exception_metadata *tx_exc_metadata)
  671. {
  672. uint8_t align_pad;
  673. uint8_t is_exception = 0;
  674. uint8_t htt_hdr_size;
  675. qdf_ether_header_t *eh;
  676. struct dp_tx_desc_s *tx_desc;
  677. struct dp_pdev *pdev = vdev->pdev;
  678. struct dp_soc *soc = pdev->soc;
  679. if (dp_tx_limit_check(vdev))
  680. return NULL;
  681. /* Allocate software Tx descriptor */
  682. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  683. if (qdf_unlikely(!tx_desc)) {
  684. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  685. return NULL;
  686. }
  687. dp_tx_outstanding_inc(pdev);
  688. /* Initialize the SW tx descriptor */
  689. tx_desc->nbuf = nbuf;
  690. tx_desc->frm_type = dp_tx_frm_std;
  691. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  692. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  693. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  694. tx_desc->vdev = vdev;
  695. tx_desc->pdev = pdev;
  696. tx_desc->msdu_ext_desc = NULL;
  697. tx_desc->pkt_offset = 0;
  698. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  699. if (qdf_unlikely(vdev->multipass_en)) {
  700. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  701. goto failure;
  702. }
  703. /*
  704. * For special modes (vdev_type == ocb or mesh), data frames should be
  705. * transmitted using varying transmit parameters (tx spec) which include
  706. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  707. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  708. * These frames are sent as exception packets to firmware.
  709. *
  710. * HW requirement is that metadata should always point to a
  711. * 8-byte aligned address. So we add alignment pad to start of buffer.
  712. * HTT Metadata should be ensured to be multiple of 8-bytes,
  713. * to get 8-byte aligned start address along with align_pad added
  714. *
  715. * |-----------------------------|
  716. * | |
  717. * |-----------------------------| <-----Buffer Pointer Address given
  718. * | | ^ in HW descriptor (aligned)
  719. * | HTT Metadata | |
  720. * | | |
  721. * | | | Packet Offset given in descriptor
  722. * | | |
  723. * |-----------------------------| |
  724. * | Alignment Pad | v
  725. * |-----------------------------| <----- Actual buffer start address
  726. * | SKB Data | (Unaligned)
  727. * | |
  728. * | |
  729. * | |
  730. * | |
  731. * | |
  732. * |-----------------------------|
  733. */
  734. if (qdf_unlikely((msdu_info->exception_fw)) ||
  735. (vdev->opmode == wlan_op_mode_ocb) ||
  736. (tx_exc_metadata &&
  737. tx_exc_metadata->is_tx_sniffer)) {
  738. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  739. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  740. DP_STATS_INC(vdev,
  741. tx_i.dropped.headroom_insufficient, 1);
  742. goto failure;
  743. }
  744. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  745. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  746. "qdf_nbuf_push_head failed");
  747. goto failure;
  748. }
  749. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  750. msdu_info);
  751. if (htt_hdr_size == 0)
  752. goto failure;
  753. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  754. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  755. is_exception = 1;
  756. }
  757. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  758. qdf_nbuf_map(soc->osdev, nbuf,
  759. QDF_DMA_TO_DEVICE))) {
  760. /* Handle failure */
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  762. "qdf_nbuf_map failed");
  763. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  764. goto failure;
  765. }
  766. if (qdf_unlikely(vdev->nawds_enabled)) {
  767. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  768. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  769. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  770. is_exception = 1;
  771. }
  772. }
  773. #if !TQM_BYPASS_WAR
  774. if (is_exception || tx_exc_metadata)
  775. #endif
  776. {
  777. /* Temporary WAR due to TQM VP issues */
  778. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  779. qdf_atomic_inc(&pdev->num_tx_exception);
  780. }
  781. return tx_desc;
  782. failure:
  783. dp_tx_desc_release(tx_desc, desc_pool_id);
  784. return NULL;
  785. }
  786. /**
  787. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  788. * @vdev: DP vdev handle
  789. * @nbuf: skb
  790. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  791. * @desc_pool_id : Descriptor Pool ID
  792. *
  793. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  794. * information. For frames wth fragments, allocate and prepare
  795. * an MSDU extension descriptor
  796. *
  797. * Return: Pointer to Tx Descriptor on success,
  798. * NULL on failure
  799. */
  800. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  801. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  802. uint8_t desc_pool_id)
  803. {
  804. struct dp_tx_desc_s *tx_desc;
  805. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  806. struct dp_pdev *pdev = vdev->pdev;
  807. struct dp_soc *soc = pdev->soc;
  808. if (dp_tx_limit_check(vdev))
  809. return NULL;
  810. /* Allocate software Tx descriptor */
  811. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  812. if (!tx_desc) {
  813. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  814. return NULL;
  815. }
  816. dp_tx_outstanding_inc(pdev);
  817. /* Initialize the SW tx descriptor */
  818. tx_desc->nbuf = nbuf;
  819. tx_desc->frm_type = msdu_info->frm_type;
  820. tx_desc->tx_encap_type = vdev->tx_encap_type;
  821. tx_desc->vdev = vdev;
  822. tx_desc->pdev = pdev;
  823. tx_desc->pkt_offset = 0;
  824. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  825. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  826. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  827. /* Handle scattered frames - TSO/SG/ME */
  828. /* Allocate and prepare an extension descriptor for scattered frames */
  829. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  830. if (!msdu_ext_desc) {
  831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  832. "%s Tx Extension Descriptor Alloc Fail",
  833. __func__);
  834. goto failure;
  835. }
  836. #if TQM_BYPASS_WAR
  837. /* Temporary WAR due to TQM VP issues */
  838. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  839. qdf_atomic_inc(&pdev->num_tx_exception);
  840. #endif
  841. if (qdf_unlikely(msdu_info->exception_fw))
  842. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  843. tx_desc->msdu_ext_desc = msdu_ext_desc;
  844. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  845. return tx_desc;
  846. failure:
  847. dp_tx_desc_release(tx_desc, desc_pool_id);
  848. return NULL;
  849. }
  850. /**
  851. * dp_tx_prepare_raw() - Prepare RAW packet TX
  852. * @vdev: DP vdev handle
  853. * @nbuf: buffer pointer
  854. * @seg_info: Pointer to Segment info Descriptor to be prepared
  855. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  856. * descriptor
  857. *
  858. * Return:
  859. */
  860. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  861. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  862. {
  863. qdf_nbuf_t curr_nbuf = NULL;
  864. uint16_t total_len = 0;
  865. qdf_dma_addr_t paddr;
  866. int32_t i;
  867. int32_t mapped_buf_num = 0;
  868. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  869. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  870. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  871. /* Continue only if frames are of DATA type */
  872. if (!DP_FRAME_IS_DATA(qos_wh)) {
  873. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  875. "Pkt. recd is of not data type");
  876. goto error;
  877. }
  878. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  879. if (vdev->raw_mode_war &&
  880. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  881. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  882. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  883. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  884. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  885. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  886. QDF_DMA_TO_DEVICE)) {
  887. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  888. "%s dma map error ", __func__);
  889. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  890. mapped_buf_num = i;
  891. goto error;
  892. }
  893. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  894. seg_info->frags[i].paddr_lo = paddr;
  895. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  896. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  897. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  898. total_len += qdf_nbuf_len(curr_nbuf);
  899. }
  900. seg_info->frag_cnt = i;
  901. seg_info->total_len = total_len;
  902. seg_info->next = NULL;
  903. sg_info->curr_seg = seg_info;
  904. msdu_info->frm_type = dp_tx_frm_raw;
  905. msdu_info->num_seg = 1;
  906. return nbuf;
  907. error:
  908. i = 0;
  909. while (nbuf) {
  910. curr_nbuf = nbuf;
  911. if (i < mapped_buf_num) {
  912. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  913. i++;
  914. }
  915. nbuf = qdf_nbuf_next(nbuf);
  916. qdf_nbuf_free(curr_nbuf);
  917. }
  918. return NULL;
  919. }
  920. /**
  921. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  922. * @soc: DP soc handle
  923. * @nbuf: Buffer pointer
  924. *
  925. * unmap the chain of nbufs that belong to this RAW frame.
  926. *
  927. * Return: None
  928. */
  929. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  930. qdf_nbuf_t nbuf)
  931. {
  932. qdf_nbuf_t cur_nbuf = nbuf;
  933. do {
  934. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  935. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  936. } while (cur_nbuf);
  937. }
  938. #ifdef VDEV_PEER_PROTOCOL_COUNT
  939. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  940. { \
  941. qdf_nbuf_t nbuf_local; \
  942. struct dp_vdev *vdev_local = vdev_hdl; \
  943. do { \
  944. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  945. break; \
  946. nbuf_local = nbuf; \
  947. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  948. htt_cmn_pkt_type_raw)) \
  949. break; \
  950. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  951. break; \
  952. else if (qdf_nbuf_is_tso((nbuf_local))) \
  953. break; \
  954. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  955. (nbuf_local), \
  956. NULL, 1, 0); \
  957. } while (0); \
  958. }
  959. #else
  960. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  961. #endif
  962. /**
  963. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  964. * @soc: DP Soc Handle
  965. * @vdev: DP vdev handle
  966. * @tx_desc: Tx Descriptor Handle
  967. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  968. * @fw_metadata: Metadata to send to Target Firmware along with frame
  969. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  970. * @tx_exc_metadata: Handle that holds exception path meta data
  971. *
  972. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  973. * from software Tx descriptor
  974. *
  975. * Return:
  976. */
  977. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  978. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  979. uint16_t fw_metadata, uint8_t ring_id,
  980. struct cdp_tx_exception_metadata
  981. *tx_exc_metadata)
  982. {
  983. uint8_t type;
  984. uint16_t length;
  985. void *hal_tx_desc, *hal_tx_desc_cached;
  986. qdf_dma_addr_t dma_addr;
  987. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  988. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  989. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  990. tx_exc_metadata->sec_type : vdev->sec_type);
  991. /* Return Buffer Manager ID */
  992. uint8_t bm_id = ring_id;
  993. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  994. hal_tx_desc_cached = (void *) cached_desc;
  995. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  996. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  997. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  998. type = HAL_TX_BUF_TYPE_EXT_DESC;
  999. dma_addr = tx_desc->msdu_ext_desc->paddr;
  1000. } else {
  1001. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  1002. type = HAL_TX_BUF_TYPE_BUFFER;
  1003. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1004. }
  1005. qdf_assert_always(dma_addr);
  1006. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1007. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  1008. dma_addr, bm_id, tx_desc->id,
  1009. type, soc->hal_soc);
  1010. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  1011. return QDF_STATUS_E_RESOURCES;
  1012. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  1013. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1014. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1015. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1016. vdev->pdev->lmac_id);
  1017. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1018. vdev->search_type);
  1019. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1020. vdev->bss_ast_idx);
  1021. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1022. vdev->dscp_tid_map_id);
  1023. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1024. sec_type_map[sec_type]);
  1025. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1026. (vdev->bss_ast_hash & 0xF));
  1027. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1028. length, type, (uint64_t)dma_addr,
  1029. tx_desc->pkt_offset, tx_desc->id);
  1030. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1031. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1032. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1033. vdev->hal_desc_addr_search_flags);
  1034. /* verify checksum offload configuration*/
  1035. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1036. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1037. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1038. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1039. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1040. }
  1041. if (tid != HTT_TX_EXT_TID_INVALID)
  1042. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1043. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1044. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1045. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1046. /* Sync cached descriptor with HW */
  1047. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1048. if (!hal_tx_desc) {
  1049. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1050. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1051. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1052. return QDF_STATUS_E_RESOURCES;
  1053. }
  1054. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1055. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1056. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1057. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1058. return QDF_STATUS_SUCCESS;
  1059. }
  1060. /**
  1061. * dp_cce_classify() - Classify the frame based on CCE rules
  1062. * @vdev: DP vdev handle
  1063. * @nbuf: skb
  1064. *
  1065. * Classify frames based on CCE rules
  1066. * Return: bool( true if classified,
  1067. * else false)
  1068. */
  1069. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1070. {
  1071. qdf_ether_header_t *eh = NULL;
  1072. uint16_t ether_type;
  1073. qdf_llc_t *llcHdr;
  1074. qdf_nbuf_t nbuf_clone = NULL;
  1075. qdf_dot3_qosframe_t *qos_wh = NULL;
  1076. /* for mesh packets don't do any classification */
  1077. if (qdf_unlikely(vdev->mesh_vdev))
  1078. return false;
  1079. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1080. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1081. ether_type = eh->ether_type;
  1082. llcHdr = (qdf_llc_t *)(nbuf->data +
  1083. sizeof(qdf_ether_header_t));
  1084. } else {
  1085. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1086. /* For encrypted packets don't do any classification */
  1087. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1088. return false;
  1089. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1090. if (qdf_unlikely(
  1091. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1092. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1093. ether_type = *(uint16_t *)(nbuf->data
  1094. + QDF_IEEE80211_4ADDR_HDR_LEN
  1095. + sizeof(qdf_llc_t)
  1096. - sizeof(ether_type));
  1097. llcHdr = (qdf_llc_t *)(nbuf->data +
  1098. QDF_IEEE80211_4ADDR_HDR_LEN);
  1099. } else {
  1100. ether_type = *(uint16_t *)(nbuf->data
  1101. + QDF_IEEE80211_3ADDR_HDR_LEN
  1102. + sizeof(qdf_llc_t)
  1103. - sizeof(ether_type));
  1104. llcHdr = (qdf_llc_t *)(nbuf->data +
  1105. QDF_IEEE80211_3ADDR_HDR_LEN);
  1106. }
  1107. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1108. && (ether_type ==
  1109. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1110. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1111. return true;
  1112. }
  1113. }
  1114. return false;
  1115. }
  1116. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1117. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1118. sizeof(*llcHdr));
  1119. nbuf_clone = qdf_nbuf_clone(nbuf);
  1120. if (qdf_unlikely(nbuf_clone)) {
  1121. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1122. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1123. qdf_nbuf_pull_head(nbuf_clone,
  1124. sizeof(qdf_net_vlanhdr_t));
  1125. }
  1126. }
  1127. } else {
  1128. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1129. nbuf_clone = qdf_nbuf_clone(nbuf);
  1130. if (qdf_unlikely(nbuf_clone)) {
  1131. qdf_nbuf_pull_head(nbuf_clone,
  1132. sizeof(qdf_net_vlanhdr_t));
  1133. }
  1134. }
  1135. }
  1136. if (qdf_unlikely(nbuf_clone))
  1137. nbuf = nbuf_clone;
  1138. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1139. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1140. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1141. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1142. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1143. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1144. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1145. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1146. if (qdf_unlikely(nbuf_clone))
  1147. qdf_nbuf_free(nbuf_clone);
  1148. return true;
  1149. }
  1150. if (qdf_unlikely(nbuf_clone))
  1151. qdf_nbuf_free(nbuf_clone);
  1152. return false;
  1153. }
  1154. /**
  1155. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1156. * @vdev: DP vdev handle
  1157. * @nbuf: skb
  1158. *
  1159. * Extract the DSCP or PCP information from frame and map into TID value.
  1160. *
  1161. * Return: void
  1162. */
  1163. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1164. struct dp_tx_msdu_info_s *msdu_info)
  1165. {
  1166. uint8_t tos = 0, dscp_tid_override = 0;
  1167. uint8_t *hdr_ptr, *L3datap;
  1168. uint8_t is_mcast = 0;
  1169. qdf_ether_header_t *eh = NULL;
  1170. qdf_ethervlan_header_t *evh = NULL;
  1171. uint16_t ether_type;
  1172. qdf_llc_t *llcHdr;
  1173. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1174. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1175. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1176. eh = (qdf_ether_header_t *)nbuf->data;
  1177. hdr_ptr = eh->ether_dhost;
  1178. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1179. } else {
  1180. qdf_dot3_qosframe_t *qos_wh =
  1181. (qdf_dot3_qosframe_t *) nbuf->data;
  1182. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1183. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1184. return;
  1185. }
  1186. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1187. ether_type = eh->ether_type;
  1188. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1189. /*
  1190. * Check if packet is dot3 or eth2 type.
  1191. */
  1192. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1193. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1194. sizeof(*llcHdr));
  1195. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1196. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1197. sizeof(*llcHdr);
  1198. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1199. + sizeof(*llcHdr) +
  1200. sizeof(qdf_net_vlanhdr_t));
  1201. } else {
  1202. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1203. sizeof(*llcHdr);
  1204. }
  1205. } else {
  1206. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1207. evh = (qdf_ethervlan_header_t *) eh;
  1208. ether_type = evh->ether_type;
  1209. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1210. }
  1211. }
  1212. /*
  1213. * Find priority from IP TOS DSCP field
  1214. */
  1215. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1216. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1217. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1218. /* Only for unicast frames */
  1219. if (!is_mcast) {
  1220. /* send it on VO queue */
  1221. msdu_info->tid = DP_VO_TID;
  1222. }
  1223. } else {
  1224. /*
  1225. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1226. * from TOS byte.
  1227. */
  1228. tos = ip->ip_tos;
  1229. dscp_tid_override = 1;
  1230. }
  1231. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1232. /* TODO
  1233. * use flowlabel
  1234. *igmpmld cases to be handled in phase 2
  1235. */
  1236. unsigned long ver_pri_flowlabel;
  1237. unsigned long pri;
  1238. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1239. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1240. DP_IPV6_PRIORITY_SHIFT;
  1241. tos = pri;
  1242. dscp_tid_override = 1;
  1243. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1244. msdu_info->tid = DP_VO_TID;
  1245. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1246. /* Only for unicast frames */
  1247. if (!is_mcast) {
  1248. /* send ucast arp on VO queue */
  1249. msdu_info->tid = DP_VO_TID;
  1250. }
  1251. }
  1252. /*
  1253. * Assign all MCAST packets to BE
  1254. */
  1255. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1256. if (is_mcast) {
  1257. tos = 0;
  1258. dscp_tid_override = 1;
  1259. }
  1260. }
  1261. if (dscp_tid_override == 1) {
  1262. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1263. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1264. }
  1265. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1266. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1267. return;
  1268. }
  1269. /**
  1270. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1271. * @vdev: DP vdev handle
  1272. * @nbuf: skb
  1273. *
  1274. * Software based TID classification is required when more than 2 DSCP-TID
  1275. * mapping tables are needed.
  1276. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1277. *
  1278. * Return: void
  1279. */
  1280. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1281. struct dp_tx_msdu_info_s *msdu_info)
  1282. {
  1283. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1284. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1285. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1286. return;
  1287. /* for mesh packets don't do any classification */
  1288. if (qdf_unlikely(vdev->mesh_vdev))
  1289. return;
  1290. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1291. }
  1292. #ifdef FEATURE_WLAN_TDLS
  1293. /**
  1294. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1295. * @tx_desc: TX descriptor
  1296. *
  1297. * Return: None
  1298. */
  1299. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1300. {
  1301. if (tx_desc->vdev) {
  1302. if (tx_desc->vdev->is_tdls_frame) {
  1303. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1304. tx_desc->vdev->is_tdls_frame = false;
  1305. }
  1306. }
  1307. }
  1308. /**
  1309. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1310. * @tx_desc: TX descriptor
  1311. * @vdev: datapath vdev handle
  1312. *
  1313. * Return: None
  1314. */
  1315. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1316. struct dp_vdev *vdev)
  1317. {
  1318. struct hal_tx_completion_status ts = {0};
  1319. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1320. if (qdf_unlikely(!vdev)) {
  1321. dp_err("vdev is null!");
  1322. return;
  1323. }
  1324. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1325. if (vdev->tx_non_std_data_callback.func) {
  1326. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1327. vdev->tx_non_std_data_callback.func(
  1328. vdev->tx_non_std_data_callback.ctxt,
  1329. nbuf, ts.status);
  1330. return;
  1331. }
  1332. }
  1333. #else
  1334. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1335. {
  1336. }
  1337. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1338. struct dp_vdev *vdev)
  1339. {
  1340. }
  1341. #endif
  1342. /**
  1343. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1344. * @vdev: DP vdev handle
  1345. * @nbuf: skb
  1346. *
  1347. * Return: 1 if frame needs to be dropped else 0
  1348. */
  1349. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1350. {
  1351. struct dp_pdev *pdev = NULL;
  1352. struct dp_ast_entry *src_ast_entry = NULL;
  1353. struct dp_ast_entry *dst_ast_entry = NULL;
  1354. struct dp_soc *soc = NULL;
  1355. qdf_assert(vdev);
  1356. pdev = vdev->pdev;
  1357. qdf_assert(pdev);
  1358. soc = pdev->soc;
  1359. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1360. (soc, dstmac, vdev->pdev->pdev_id);
  1361. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1362. (soc, srcmac, vdev->pdev->pdev_id);
  1363. if (dst_ast_entry && src_ast_entry) {
  1364. if (dst_ast_entry->peer->peer_ids[0] ==
  1365. src_ast_entry->peer->peer_ids[0])
  1366. return 1;
  1367. }
  1368. return 0;
  1369. }
  1370. /**
  1371. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1372. * @vdev: DP vdev handle
  1373. * @nbuf: skb
  1374. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1375. * @meta_data: Metadata to the fw
  1376. * @tx_q: Tx queue to be used for this Tx frame
  1377. * @peer_id: peer_id of the peer in case of NAWDS frames
  1378. * @tx_exc_metadata: Handle that holds exception path metadata
  1379. *
  1380. * Return: NULL on success,
  1381. * nbuf when it fails to send
  1382. */
  1383. qdf_nbuf_t
  1384. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1385. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1386. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1387. {
  1388. struct dp_pdev *pdev = vdev->pdev;
  1389. struct dp_soc *soc = pdev->soc;
  1390. struct dp_tx_desc_s *tx_desc;
  1391. QDF_STATUS status;
  1392. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1393. hal_ring_handle_t hal_ring_hdl =
  1394. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1395. uint16_t htt_tcl_metadata = 0;
  1396. uint8_t tid = msdu_info->tid;
  1397. struct cdp_tid_tx_stats *tid_stats = NULL;
  1398. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1399. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1400. msdu_info, tx_exc_metadata);
  1401. if (!tx_desc) {
  1402. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1403. vdev, tx_q->desc_pool_id);
  1404. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1405. tid_stats = &pdev->stats.tid_stats.
  1406. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1407. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1408. return nbuf;
  1409. }
  1410. if (qdf_unlikely(soc->cce_disable)) {
  1411. if (dp_cce_classify(vdev, nbuf) == true) {
  1412. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1413. tid = DP_VO_TID;
  1414. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1415. }
  1416. }
  1417. dp_tx_update_tdls_flags(tx_desc);
  1418. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1419. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1420. "%s %d : HAL RING Access Failed -- %pK",
  1421. __func__, __LINE__, hal_ring_hdl);
  1422. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1423. tid_stats = &pdev->stats.tid_stats.
  1424. tid_tx_stats[tx_q->ring_id][tid];
  1425. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1426. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1427. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1428. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1429. goto fail_return;
  1430. }
  1431. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1432. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1433. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1434. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1435. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1436. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1437. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1438. peer_id);
  1439. } else
  1440. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1441. if (msdu_info->exception_fw) {
  1442. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1443. }
  1444. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1445. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1446. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1447. if (status != QDF_STATUS_SUCCESS) {
  1448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1449. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1450. __func__, tx_desc, tx_q->ring_id);
  1451. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1452. tid_stats = &pdev->stats.tid_stats.
  1453. tid_tx_stats[tx_q->ring_id][tid];
  1454. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1455. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1456. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1457. goto fail_return;
  1458. }
  1459. nbuf = NULL;
  1460. fail_return:
  1461. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1462. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1463. hif_pm_runtime_put(soc->hif_handle);
  1464. } else {
  1465. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1466. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1467. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1468. }
  1469. return nbuf;
  1470. }
  1471. /**
  1472. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1473. * @vdev: DP vdev handle
  1474. * @nbuf: skb
  1475. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1476. *
  1477. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1478. *
  1479. * Return: NULL on success,
  1480. * nbuf when it fails to send
  1481. */
  1482. #if QDF_LOCK_STATS
  1483. noinline
  1484. #else
  1485. #endif
  1486. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1487. struct dp_tx_msdu_info_s *msdu_info)
  1488. {
  1489. uint8_t i;
  1490. struct dp_pdev *pdev = vdev->pdev;
  1491. struct dp_soc *soc = pdev->soc;
  1492. struct dp_tx_desc_s *tx_desc;
  1493. bool is_cce_classified = false;
  1494. QDF_STATUS status;
  1495. uint16_t htt_tcl_metadata = 0;
  1496. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1497. hal_ring_handle_t hal_ring_hdl =
  1498. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1499. struct cdp_tid_tx_stats *tid_stats = NULL;
  1500. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1501. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1502. "%s %d : HAL RING Access Failed -- %pK",
  1503. __func__, __LINE__, hal_ring_hdl);
  1504. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1505. tid_stats = &pdev->stats.tid_stats.
  1506. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1507. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1508. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1509. return nbuf;
  1510. }
  1511. if (qdf_unlikely(soc->cce_disable)) {
  1512. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1513. if (is_cce_classified) {
  1514. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1515. msdu_info->tid = DP_VO_TID;
  1516. }
  1517. }
  1518. if (msdu_info->frm_type == dp_tx_frm_me)
  1519. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1520. i = 0;
  1521. /* Print statement to track i and num_seg */
  1522. /*
  1523. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1524. * descriptors using information in msdu_info
  1525. */
  1526. while (i < msdu_info->num_seg) {
  1527. /*
  1528. * Setup Tx descriptor for an MSDU, and MSDU extension
  1529. * descriptor
  1530. */
  1531. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1532. tx_q->desc_pool_id);
  1533. if (!tx_desc) {
  1534. if (msdu_info->frm_type == dp_tx_frm_me) {
  1535. dp_tx_me_free_buf(pdev,
  1536. (void *)(msdu_info->u.sg_info
  1537. .curr_seg->frags[0].vaddr));
  1538. i++;
  1539. continue;
  1540. }
  1541. goto done;
  1542. }
  1543. if (msdu_info->frm_type == dp_tx_frm_me) {
  1544. tx_desc->me_buffer =
  1545. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1546. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1547. }
  1548. if (is_cce_classified)
  1549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1550. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1551. if (msdu_info->exception_fw) {
  1552. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1553. }
  1554. /*
  1555. * Enqueue the Tx MSDU descriptor to HW for transmit
  1556. */
  1557. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1558. htt_tcl_metadata, tx_q->ring_id, NULL);
  1559. if (status != QDF_STATUS_SUCCESS) {
  1560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1561. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1562. __func__, tx_desc, tx_q->ring_id);
  1563. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1564. tid_stats = &pdev->stats.tid_stats.
  1565. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1566. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1567. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1568. if (msdu_info->frm_type == dp_tx_frm_me) {
  1569. i++;
  1570. continue;
  1571. }
  1572. goto done;
  1573. }
  1574. /*
  1575. * TODO
  1576. * if tso_info structure can be modified to have curr_seg
  1577. * as first element, following 2 blocks of code (for TSO and SG)
  1578. * can be combined into 1
  1579. */
  1580. /*
  1581. * For frames with multiple segments (TSO, ME), jump to next
  1582. * segment.
  1583. */
  1584. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1585. if (msdu_info->u.tso_info.curr_seg->next) {
  1586. msdu_info->u.tso_info.curr_seg =
  1587. msdu_info->u.tso_info.curr_seg->next;
  1588. /*
  1589. * If this is a jumbo nbuf, then increment the number of
  1590. * nbuf users for each additional segment of the msdu.
  1591. * This will ensure that the skb is freed only after
  1592. * receiving tx completion for all segments of an nbuf
  1593. */
  1594. qdf_nbuf_inc_users(nbuf);
  1595. /* Check with MCL if this is needed */
  1596. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1597. }
  1598. }
  1599. /*
  1600. * For Multicast-Unicast converted packets,
  1601. * each converted frame (for a client) is represented as
  1602. * 1 segment
  1603. */
  1604. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1605. (msdu_info->frm_type == dp_tx_frm_me)) {
  1606. if (msdu_info->u.sg_info.curr_seg->next) {
  1607. msdu_info->u.sg_info.curr_seg =
  1608. msdu_info->u.sg_info.curr_seg->next;
  1609. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1610. }
  1611. }
  1612. i++;
  1613. }
  1614. nbuf = NULL;
  1615. done:
  1616. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1617. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1618. hif_pm_runtime_put(soc->hif_handle);
  1619. } else {
  1620. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1621. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1622. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1623. }
  1624. return nbuf;
  1625. }
  1626. /**
  1627. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1628. * for SG frames
  1629. * @vdev: DP vdev handle
  1630. * @nbuf: skb
  1631. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1632. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1633. *
  1634. * Return: NULL on success,
  1635. * nbuf when it fails to send
  1636. */
  1637. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1638. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1639. {
  1640. uint32_t cur_frag, nr_frags;
  1641. qdf_dma_addr_t paddr;
  1642. struct dp_tx_sg_info_s *sg_info;
  1643. sg_info = &msdu_info->u.sg_info;
  1644. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1645. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1646. QDF_DMA_TO_DEVICE)) {
  1647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1648. "dma map error");
  1649. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1650. qdf_nbuf_free(nbuf);
  1651. return NULL;
  1652. }
  1653. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1654. seg_info->frags[0].paddr_lo = paddr;
  1655. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1656. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1657. seg_info->frags[0].vaddr = (void *) nbuf;
  1658. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1659. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1660. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1662. "frag dma map error");
  1663. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1664. qdf_nbuf_free(nbuf);
  1665. return NULL;
  1666. }
  1667. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1668. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1669. seg_info->frags[cur_frag + 1].paddr_hi =
  1670. ((uint64_t) paddr) >> 32;
  1671. seg_info->frags[cur_frag + 1].len =
  1672. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1673. }
  1674. seg_info->frag_cnt = (cur_frag + 1);
  1675. seg_info->total_len = qdf_nbuf_len(nbuf);
  1676. seg_info->next = NULL;
  1677. sg_info->curr_seg = seg_info;
  1678. msdu_info->frm_type = dp_tx_frm_sg;
  1679. msdu_info->num_seg = 1;
  1680. return nbuf;
  1681. }
  1682. /**
  1683. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1684. * @vdev: DP vdev handle
  1685. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1686. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1687. *
  1688. * Return: NULL on failure,
  1689. * nbuf when extracted successfully
  1690. */
  1691. static
  1692. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1693. struct dp_tx_msdu_info_s *msdu_info,
  1694. uint16_t ppdu_cookie)
  1695. {
  1696. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1697. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1698. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1699. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1700. (msdu_info->meta_data[5], 1);
  1701. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1702. (msdu_info->meta_data[5], 1);
  1703. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1704. (msdu_info->meta_data[6], ppdu_cookie);
  1705. msdu_info->exception_fw = 1;
  1706. msdu_info->is_tx_sniffer = 1;
  1707. }
  1708. #ifdef MESH_MODE_SUPPORT
  1709. /**
  1710. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1711. and prepare msdu_info for mesh frames.
  1712. * @vdev: DP vdev handle
  1713. * @nbuf: skb
  1714. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1715. *
  1716. * Return: NULL on failure,
  1717. * nbuf when extracted successfully
  1718. */
  1719. static
  1720. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1721. struct dp_tx_msdu_info_s *msdu_info)
  1722. {
  1723. struct meta_hdr_s *mhdr;
  1724. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1725. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1726. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1727. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1728. msdu_info->exception_fw = 0;
  1729. goto remove_meta_hdr;
  1730. }
  1731. msdu_info->exception_fw = 1;
  1732. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1733. meta_data->host_tx_desc_pool = 1;
  1734. meta_data->update_peer_cache = 1;
  1735. meta_data->learning_frame = 1;
  1736. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1737. meta_data->power = mhdr->power;
  1738. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1739. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1740. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1741. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1742. meta_data->dyn_bw = 1;
  1743. meta_data->valid_pwr = 1;
  1744. meta_data->valid_mcs_mask = 1;
  1745. meta_data->valid_nss_mask = 1;
  1746. meta_data->valid_preamble_type = 1;
  1747. meta_data->valid_retries = 1;
  1748. meta_data->valid_bw_info = 1;
  1749. }
  1750. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1751. meta_data->encrypt_type = 0;
  1752. meta_data->valid_encrypt_type = 1;
  1753. meta_data->learning_frame = 0;
  1754. }
  1755. meta_data->valid_key_flags = 1;
  1756. meta_data->key_flags = (mhdr->keyix & 0x3);
  1757. remove_meta_hdr:
  1758. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1759. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1760. "qdf_nbuf_pull_head failed");
  1761. qdf_nbuf_free(nbuf);
  1762. return NULL;
  1763. }
  1764. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1766. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1767. " tid %d to_fw %d",
  1768. __func__, msdu_info->meta_data[0],
  1769. msdu_info->meta_data[1],
  1770. msdu_info->meta_data[2],
  1771. msdu_info->meta_data[3],
  1772. msdu_info->meta_data[4],
  1773. msdu_info->meta_data[5],
  1774. msdu_info->tid, msdu_info->exception_fw);
  1775. return nbuf;
  1776. }
  1777. #else
  1778. static
  1779. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1780. struct dp_tx_msdu_info_s *msdu_info)
  1781. {
  1782. return nbuf;
  1783. }
  1784. #endif
  1785. /**
  1786. * dp_check_exc_metadata() - Checks if parameters are valid
  1787. * @tx_exc - holds all exception path parameters
  1788. *
  1789. * Returns true when all the parameters are valid else false
  1790. *
  1791. */
  1792. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1793. {
  1794. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1795. HTT_INVALID_TID);
  1796. bool invalid_encap_type =
  1797. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1798. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1799. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1800. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1801. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1802. tx_exc->ppdu_cookie == 0);
  1803. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1804. invalid_cookie) {
  1805. return false;
  1806. }
  1807. return true;
  1808. }
  1809. /**
  1810. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1811. * @soc: DP soc handle
  1812. * @vdev_id: id of DP vdev handle
  1813. * @nbuf: skb
  1814. * @tx_exc_metadata: Handle that holds exception path meta data
  1815. *
  1816. * Entry point for Core Tx layer (DP_TX) invoked from
  1817. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1818. *
  1819. * Return: NULL on success,
  1820. * nbuf when it fails to send
  1821. */
  1822. qdf_nbuf_t
  1823. dp_tx_send_exception(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf,
  1824. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1825. {
  1826. qdf_ether_header_t *eh = NULL;
  1827. struct dp_tx_msdu_info_s msdu_info;
  1828. struct dp_vdev *vdev =
  1829. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1830. vdev_id);
  1831. if (qdf_unlikely(!vdev))
  1832. goto fail;
  1833. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1834. if (!tx_exc_metadata)
  1835. goto fail;
  1836. msdu_info.tid = tx_exc_metadata->tid;
  1837. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1838. dp_verbose_debug("skb %pM", nbuf->data);
  1839. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1840. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1842. "Invalid parameters in exception path");
  1843. goto fail;
  1844. }
  1845. /* Basic sanity checks for unsupported packets */
  1846. /* MESH mode */
  1847. if (qdf_unlikely(vdev->mesh_vdev)) {
  1848. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1849. "Mesh mode is not supported in exception path");
  1850. goto fail;
  1851. }
  1852. /* TSO or SG */
  1853. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1854. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1856. "TSO and SG are not supported in exception path");
  1857. goto fail;
  1858. }
  1859. /* RAW */
  1860. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1861. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1862. "Raw frame is not supported in exception path");
  1863. goto fail;
  1864. }
  1865. /* Mcast enhancement*/
  1866. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1867. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1868. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1869. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1870. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1871. }
  1872. }
  1873. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1874. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1875. qdf_nbuf_len(nbuf));
  1876. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1877. tx_exc_metadata->ppdu_cookie);
  1878. }
  1879. /*
  1880. * Get HW Queue to use for this frame.
  1881. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1882. * dedicated for data and 1 for command.
  1883. * "queue_id" maps to one hardware ring.
  1884. * With each ring, we also associate a unique Tx descriptor pool
  1885. * to minimize lock contention for these resources.
  1886. */
  1887. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1888. /* Single linear frame */
  1889. /*
  1890. * If nbuf is a simple linear frame, use send_single function to
  1891. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1892. * SRNG. There is no need to setup a MSDU extension descriptor.
  1893. */
  1894. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1895. tx_exc_metadata->peer_id, tx_exc_metadata);
  1896. return nbuf;
  1897. fail:
  1898. dp_verbose_debug("pkt send failed");
  1899. return nbuf;
  1900. }
  1901. /**
  1902. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1903. * @soc: DP soc handle
  1904. * @vdev_id: DP vdev handle
  1905. * @nbuf: skb
  1906. *
  1907. * Entry point for Core Tx layer (DP_TX) invoked from
  1908. * hard_start_xmit in OSIF/HDD
  1909. *
  1910. * Return: NULL on success,
  1911. * nbuf when it fails to send
  1912. */
  1913. #ifdef MESH_MODE_SUPPORT
  1914. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1915. qdf_nbuf_t nbuf)
  1916. {
  1917. struct meta_hdr_s *mhdr;
  1918. qdf_nbuf_t nbuf_mesh = NULL;
  1919. qdf_nbuf_t nbuf_clone = NULL;
  1920. struct dp_vdev *vdev;
  1921. uint8_t no_enc_frame = 0;
  1922. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1923. if (!nbuf_mesh) {
  1924. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1925. "qdf_nbuf_unshare failed");
  1926. return nbuf;
  1927. }
  1928. vdev = dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1929. vdev_id);
  1930. if (!vdev) {
  1931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1932. "vdev is NULL for vdev_id %d", vdev_id);
  1933. return nbuf;
  1934. }
  1935. nbuf = nbuf_mesh;
  1936. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1937. if ((vdev->sec_type != cdp_sec_type_none) &&
  1938. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1939. no_enc_frame = 1;
  1940. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1941. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1942. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1943. !no_enc_frame) {
  1944. nbuf_clone = qdf_nbuf_clone(nbuf);
  1945. if (!nbuf_clone) {
  1946. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1947. "qdf_nbuf_clone failed");
  1948. return nbuf;
  1949. }
  1950. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1951. }
  1952. if (nbuf_clone) {
  1953. if (!dp_tx_send(soc, vdev_id, nbuf_clone)) {
  1954. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1955. } else {
  1956. qdf_nbuf_free(nbuf_clone);
  1957. }
  1958. }
  1959. if (no_enc_frame)
  1960. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1961. else
  1962. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1963. nbuf = dp_tx_send(soc, vdev_id, nbuf);
  1964. if ((!nbuf) && no_enc_frame) {
  1965. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1966. }
  1967. return nbuf;
  1968. }
  1969. #else
  1970. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1971. qdf_nbuf_t nbuf)
  1972. {
  1973. return dp_tx_send(soc, vdev_id, nbuf);
  1974. }
  1975. #endif
  1976. /**
  1977. * dp_tx_send() - Transmit a frame on a given VAP
  1978. * @soc: DP soc handle
  1979. * @vdev_id: id of DP vdev handle
  1980. * @nbuf: skb
  1981. *
  1982. * Entry point for Core Tx layer (DP_TX) invoked from
  1983. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1984. * cases
  1985. *
  1986. * Return: NULL on success,
  1987. * nbuf when it fails to send
  1988. */
  1989. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf)
  1990. {
  1991. qdf_ether_header_t *eh = NULL;
  1992. struct dp_tx_msdu_info_s msdu_info;
  1993. struct dp_tx_seg_info_s seg_info;
  1994. uint16_t peer_id = HTT_INVALID_PEER;
  1995. qdf_nbuf_t nbuf_mesh = NULL;
  1996. struct dp_vdev *vdev =
  1997. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1998. vdev_id);
  1999. if (qdf_unlikely(!vdev))
  2000. return nbuf;
  2001. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2002. qdf_mem_zero(&seg_info, sizeof(seg_info));
  2003. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2004. dp_verbose_debug("skb %pM", nbuf->data);
  2005. /*
  2006. * Set Default Host TID value to invalid TID
  2007. * (TID override disabled)
  2008. */
  2009. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2010. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2011. if (qdf_unlikely(vdev->mesh_vdev)) {
  2012. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2013. &msdu_info);
  2014. if (!nbuf_mesh) {
  2015. dp_verbose_debug("Extracting mesh metadata failed");
  2016. return nbuf;
  2017. }
  2018. nbuf = nbuf_mesh;
  2019. }
  2020. /*
  2021. * Get HW Queue to use for this frame.
  2022. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2023. * dedicated for data and 1 for command.
  2024. * "queue_id" maps to one hardware ring.
  2025. * With each ring, we also associate a unique Tx descriptor pool
  2026. * to minimize lock contention for these resources.
  2027. */
  2028. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2029. /*
  2030. * TCL H/W supports 2 DSCP-TID mapping tables.
  2031. * Table 1 - Default DSCP-TID mapping table
  2032. * Table 2 - 1 DSCP-TID override table
  2033. *
  2034. * If we need a different DSCP-TID mapping for this vap,
  2035. * call tid_classify to extract DSCP/ToS from frame and
  2036. * map to a TID and store in msdu_info. This is later used
  2037. * to fill in TCL Input descriptor (per-packet TID override).
  2038. */
  2039. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2040. /*
  2041. * Classify the frame and call corresponding
  2042. * "prepare" function which extracts the segment (TSO)
  2043. * and fragmentation information (for TSO , SG, ME, or Raw)
  2044. * into MSDU_INFO structure which is later used to fill
  2045. * SW and HW descriptors.
  2046. */
  2047. if (qdf_nbuf_is_tso(nbuf)) {
  2048. dp_verbose_debug("TSO frame %pK", vdev);
  2049. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2050. qdf_nbuf_len(nbuf));
  2051. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2052. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2053. qdf_nbuf_len(nbuf));
  2054. return nbuf;
  2055. }
  2056. goto send_multiple;
  2057. }
  2058. /* SG */
  2059. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2060. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2061. if (!nbuf)
  2062. return NULL;
  2063. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2064. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2065. qdf_nbuf_len(nbuf));
  2066. goto send_multiple;
  2067. }
  2068. #ifdef ATH_SUPPORT_IQUE
  2069. /* Mcast to Ucast Conversion*/
  2070. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2071. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2072. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2073. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2074. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2075. DP_STATS_INC_PKT(vdev,
  2076. tx_i.mcast_en.mcast_pkt, 1,
  2077. qdf_nbuf_len(nbuf));
  2078. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2079. QDF_STATUS_SUCCESS) {
  2080. return NULL;
  2081. }
  2082. }
  2083. }
  2084. #endif
  2085. /* RAW */
  2086. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2087. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2088. if (!nbuf)
  2089. return NULL;
  2090. dp_verbose_debug("Raw frame %pK", vdev);
  2091. goto send_multiple;
  2092. }
  2093. /* Single linear frame */
  2094. /*
  2095. * If nbuf is a simple linear frame, use send_single function to
  2096. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2097. * SRNG. There is no need to setup a MSDU extension descriptor.
  2098. */
  2099. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2100. return nbuf;
  2101. send_multiple:
  2102. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2103. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2104. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2105. return nbuf;
  2106. }
  2107. /**
  2108. * dp_tx_reinject_handler() - Tx Reinject Handler
  2109. * @tx_desc: software descriptor head pointer
  2110. * @status : Tx completion status from HTT descriptor
  2111. *
  2112. * This function reinjects frames back to Target.
  2113. * Todo - Host queue needs to be added
  2114. *
  2115. * Return: none
  2116. */
  2117. static
  2118. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2119. {
  2120. struct dp_vdev *vdev;
  2121. struct dp_peer *peer = NULL;
  2122. uint32_t peer_id = HTT_INVALID_PEER;
  2123. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2124. qdf_nbuf_t nbuf_copy = NULL;
  2125. struct dp_tx_msdu_info_s msdu_info;
  2126. struct dp_peer *sa_peer = NULL;
  2127. struct dp_ast_entry *ast_entry = NULL;
  2128. struct dp_soc *soc = NULL;
  2129. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2130. #ifdef WDS_VENDOR_EXTENSION
  2131. int is_mcast = 0, is_ucast = 0;
  2132. int num_peers_3addr = 0;
  2133. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2134. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2135. #endif
  2136. vdev = tx_desc->vdev;
  2137. soc = vdev->pdev->soc;
  2138. qdf_assert(vdev);
  2139. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2140. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2142. "%s Tx reinject path", __func__);
  2143. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2144. qdf_nbuf_len(tx_desc->nbuf));
  2145. qdf_spin_lock_bh(&(soc->ast_lock));
  2146. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2147. (soc,
  2148. (uint8_t *)(eh->ether_shost),
  2149. vdev->pdev->pdev_id);
  2150. if (ast_entry)
  2151. sa_peer = ast_entry->peer;
  2152. qdf_spin_unlock_bh(&(soc->ast_lock));
  2153. #ifdef WDS_VENDOR_EXTENSION
  2154. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2155. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2156. } else {
  2157. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2158. }
  2159. is_ucast = !is_mcast;
  2160. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2161. if (peer->bss_peer)
  2162. continue;
  2163. /* Detect wds peers that use 3-addr framing for mcast.
  2164. * if there are any, the bss_peer is used to send the
  2165. * the mcast frame using 3-addr format. all wds enabled
  2166. * peers that use 4-addr framing for mcast frames will
  2167. * be duplicated and sent as 4-addr frames below.
  2168. */
  2169. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2170. num_peers_3addr = 1;
  2171. break;
  2172. }
  2173. }
  2174. #endif
  2175. if (qdf_unlikely(vdev->mesh_vdev)) {
  2176. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2177. } else {
  2178. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2179. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2180. #ifdef WDS_VENDOR_EXTENSION
  2181. /*
  2182. * . if 3-addr STA, then send on BSS Peer
  2183. * . if Peer WDS enabled and accept 4-addr mcast,
  2184. * send mcast on that peer only
  2185. * . if Peer WDS enabled and accept 4-addr ucast,
  2186. * send ucast on that peer only
  2187. */
  2188. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2189. (peer->wds_enabled &&
  2190. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2191. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2192. #else
  2193. ((peer->bss_peer &&
  2194. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2195. peer->nawds_enabled)) {
  2196. #endif
  2197. peer_id = DP_INVALID_PEER;
  2198. if (peer->nawds_enabled) {
  2199. peer_id = peer->peer_ids[0];
  2200. if (sa_peer == peer) {
  2201. QDF_TRACE(
  2202. QDF_MODULE_ID_DP,
  2203. QDF_TRACE_LEVEL_DEBUG,
  2204. " %s: multicast packet",
  2205. __func__);
  2206. DP_STATS_INC(peer,
  2207. tx.nawds_mcast_drop, 1);
  2208. continue;
  2209. }
  2210. }
  2211. nbuf_copy = qdf_nbuf_copy(nbuf);
  2212. if (!nbuf_copy) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP,
  2214. QDF_TRACE_LEVEL_DEBUG,
  2215. FL("nbuf copy failed"));
  2216. break;
  2217. }
  2218. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2219. nbuf_copy,
  2220. &msdu_info,
  2221. peer_id,
  2222. NULL);
  2223. if (nbuf_copy) {
  2224. QDF_TRACE(QDF_MODULE_ID_DP,
  2225. QDF_TRACE_LEVEL_DEBUG,
  2226. FL("pkt send failed"));
  2227. qdf_nbuf_free(nbuf_copy);
  2228. } else {
  2229. if (peer_id != DP_INVALID_PEER)
  2230. DP_STATS_INC_PKT(peer,
  2231. tx.nawds_mcast,
  2232. 1, qdf_nbuf_len(nbuf));
  2233. }
  2234. }
  2235. }
  2236. }
  2237. if (vdev->nawds_enabled) {
  2238. peer_id = DP_INVALID_PEER;
  2239. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2240. 1, qdf_nbuf_len(nbuf));
  2241. nbuf = dp_tx_send_msdu_single(vdev,
  2242. nbuf,
  2243. &msdu_info,
  2244. peer_id, NULL);
  2245. if (nbuf) {
  2246. QDF_TRACE(QDF_MODULE_ID_DP,
  2247. QDF_TRACE_LEVEL_DEBUG,
  2248. FL("pkt send failed"));
  2249. qdf_nbuf_free(nbuf);
  2250. }
  2251. } else
  2252. qdf_nbuf_free(nbuf);
  2253. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2254. }
  2255. /**
  2256. * dp_tx_inspect_handler() - Tx Inspect Handler
  2257. * @tx_desc: software descriptor head pointer
  2258. * @status : Tx completion status from HTT descriptor
  2259. *
  2260. * Handles Tx frames sent back to Host for inspection
  2261. * (ProxyARP)
  2262. *
  2263. * Return: none
  2264. */
  2265. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2266. {
  2267. struct dp_soc *soc;
  2268. struct dp_pdev *pdev = tx_desc->pdev;
  2269. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2270. "%s Tx inspect path",
  2271. __func__);
  2272. qdf_assert(pdev);
  2273. soc = pdev->soc;
  2274. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2275. qdf_nbuf_len(tx_desc->nbuf));
  2276. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2277. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2278. }
  2279. #ifdef FEATURE_PERPKT_INFO
  2280. /**
  2281. * dp_get_completion_indication_for_stack() - send completion to stack
  2282. * @soc : dp_soc handle
  2283. * @pdev: dp_pdev handle
  2284. * @peer: dp peer handle
  2285. * @ts: transmit completion status structure
  2286. * @netbuf: Buffer pointer for free
  2287. *
  2288. * This function is used for indication whether buffer needs to be
  2289. * sent to stack for freeing or not
  2290. */
  2291. QDF_STATUS
  2292. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2293. struct dp_pdev *pdev,
  2294. struct dp_peer *peer,
  2295. struct hal_tx_completion_status *ts,
  2296. qdf_nbuf_t netbuf,
  2297. uint64_t time_latency)
  2298. {
  2299. struct tx_capture_hdr *ppdu_hdr;
  2300. uint16_t peer_id = ts->peer_id;
  2301. uint32_t ppdu_id = ts->ppdu_id;
  2302. uint8_t first_msdu = ts->first_msdu;
  2303. uint8_t last_msdu = ts->last_msdu;
  2304. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2305. !pdev->latency_capture_enable))
  2306. return QDF_STATUS_E_NOSUPPORT;
  2307. if (!peer) {
  2308. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2309. FL("Peer Invalid"));
  2310. return QDF_STATUS_E_INVAL;
  2311. }
  2312. if (pdev->mcopy_mode) {
  2313. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2314. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2315. return QDF_STATUS_E_INVAL;
  2316. }
  2317. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2318. pdev->m_copy_id.tx_peer_id = peer_id;
  2319. }
  2320. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2321. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2322. FL("No headroom"));
  2323. return QDF_STATUS_E_NOMEM;
  2324. }
  2325. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2326. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2327. QDF_MAC_ADDR_SIZE);
  2328. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2329. QDF_MAC_ADDR_SIZE);
  2330. ppdu_hdr->ppdu_id = ppdu_id;
  2331. ppdu_hdr->peer_id = peer_id;
  2332. ppdu_hdr->first_msdu = first_msdu;
  2333. ppdu_hdr->last_msdu = last_msdu;
  2334. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2335. ppdu_hdr->tsf = ts->tsf;
  2336. ppdu_hdr->time_latency = time_latency;
  2337. }
  2338. return QDF_STATUS_SUCCESS;
  2339. }
  2340. /**
  2341. * dp_send_completion_to_stack() - send completion to stack
  2342. * @soc : dp_soc handle
  2343. * @pdev: dp_pdev handle
  2344. * @peer_id: peer_id of the peer for which completion came
  2345. * @ppdu_id: ppdu_id
  2346. * @netbuf: Buffer pointer for free
  2347. *
  2348. * This function is used to send completion to stack
  2349. * to free buffer
  2350. */
  2351. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2352. uint16_t peer_id, uint32_t ppdu_id,
  2353. qdf_nbuf_t netbuf)
  2354. {
  2355. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2356. netbuf, peer_id,
  2357. WDI_NO_VAL, pdev->pdev_id);
  2358. }
  2359. #else
  2360. static QDF_STATUS
  2361. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2362. struct dp_pdev *pdev,
  2363. struct dp_peer *peer,
  2364. struct hal_tx_completion_status *ts,
  2365. qdf_nbuf_t netbuf,
  2366. uint64_t time_latency)
  2367. {
  2368. return QDF_STATUS_E_NOSUPPORT;
  2369. }
  2370. static void
  2371. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2372. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2373. {
  2374. }
  2375. #endif
  2376. /**
  2377. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2378. * @soc: Soc handle
  2379. * @desc: software Tx descriptor to be processed
  2380. *
  2381. * Return: none
  2382. */
  2383. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2384. struct dp_tx_desc_s *desc)
  2385. {
  2386. struct dp_vdev *vdev = desc->vdev;
  2387. qdf_nbuf_t nbuf = desc->nbuf;
  2388. /* nbuf already freed in vdev detach path */
  2389. if (!nbuf)
  2390. return;
  2391. /* If it is TDLS mgmt, don't unmap or free the frame */
  2392. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2393. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2394. /* 0 : MSDU buffer, 1 : MLE */
  2395. if (desc->msdu_ext_desc) {
  2396. /* TSO free */
  2397. if (hal_tx_ext_desc_get_tso_enable(
  2398. desc->msdu_ext_desc->vaddr)) {
  2399. /* unmap eash TSO seg before free the nbuf */
  2400. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2401. desc->tso_num_desc);
  2402. qdf_nbuf_free(nbuf);
  2403. return;
  2404. }
  2405. }
  2406. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2407. if (qdf_unlikely(!vdev)) {
  2408. qdf_nbuf_free(nbuf);
  2409. return;
  2410. }
  2411. if (qdf_likely(!vdev->mesh_vdev))
  2412. qdf_nbuf_free(nbuf);
  2413. else {
  2414. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2415. qdf_nbuf_free(nbuf);
  2416. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2417. } else
  2418. vdev->osif_tx_free_ext((nbuf));
  2419. }
  2420. }
  2421. #ifdef MESH_MODE_SUPPORT
  2422. /**
  2423. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2424. * in mesh meta header
  2425. * @tx_desc: software descriptor head pointer
  2426. * @ts: pointer to tx completion stats
  2427. * Return: none
  2428. */
  2429. static
  2430. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2431. struct hal_tx_completion_status *ts)
  2432. {
  2433. struct meta_hdr_s *mhdr;
  2434. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2435. if (!tx_desc->msdu_ext_desc) {
  2436. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2437. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2438. "netbuf %pK offset %d",
  2439. netbuf, tx_desc->pkt_offset);
  2440. return;
  2441. }
  2442. }
  2443. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2444. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2445. "netbuf %pK offset %lu", netbuf,
  2446. sizeof(struct meta_hdr_s));
  2447. return;
  2448. }
  2449. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2450. mhdr->rssi = ts->ack_frame_rssi;
  2451. mhdr->band = tx_desc->pdev->operating_channel.band;
  2452. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2453. }
  2454. #else
  2455. static
  2456. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2457. struct hal_tx_completion_status *ts)
  2458. {
  2459. }
  2460. #endif
  2461. /**
  2462. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2463. * to pass in correct fields
  2464. *
  2465. * @vdev: pdev handle
  2466. * @tx_desc: tx descriptor
  2467. * @tid: tid value
  2468. * @ring_id: TCL or WBM ring number for transmit path
  2469. * Return: none
  2470. */
  2471. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2472. struct dp_tx_desc_s *tx_desc,
  2473. uint8_t tid, uint8_t ring_id)
  2474. {
  2475. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2476. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2477. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2478. return;
  2479. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2480. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2481. timestamp_hw_enqueue = tx_desc->timestamp;
  2482. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2483. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2484. timestamp_hw_enqueue);
  2485. interframe_delay = (uint32_t)(timestamp_ingress -
  2486. vdev->prev_tx_enq_tstamp);
  2487. /*
  2488. * Delay in software enqueue
  2489. */
  2490. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2491. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2492. /*
  2493. * Delay between packet enqueued to HW and Tx completion
  2494. */
  2495. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2496. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2497. /*
  2498. * Update interframe delay stats calculated at hardstart receive point.
  2499. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2500. * interframe delay will not be calculate correctly for 1st frame.
  2501. * On the other side, this will help in avoiding extra per packet check
  2502. * of !vdev->prev_tx_enq_tstamp.
  2503. */
  2504. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2505. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2506. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2507. }
  2508. /**
  2509. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2510. * per wbm ring
  2511. *
  2512. * @tx_desc: software descriptor head pointer
  2513. * @ts: Tx completion status
  2514. * @peer: peer handle
  2515. * @ring_id: ring number
  2516. *
  2517. * Return: None
  2518. */
  2519. static inline void
  2520. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2521. struct hal_tx_completion_status *ts,
  2522. struct dp_peer *peer, uint8_t ring_id)
  2523. {
  2524. struct dp_pdev *pdev = peer->vdev->pdev;
  2525. struct dp_soc *soc = NULL;
  2526. uint8_t mcs, pkt_type;
  2527. uint8_t tid = ts->tid;
  2528. uint32_t length;
  2529. struct cdp_tid_tx_stats *tid_stats;
  2530. if (!pdev)
  2531. return;
  2532. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2533. tid = CDP_MAX_DATA_TIDS - 1;
  2534. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2535. soc = pdev->soc;
  2536. mcs = ts->mcs;
  2537. pkt_type = ts->pkt_type;
  2538. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2539. dp_err("Release source is not from TQM");
  2540. return;
  2541. }
  2542. length = qdf_nbuf_len(tx_desc->nbuf);
  2543. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2544. if (qdf_unlikely(pdev->delay_stats_flag))
  2545. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2546. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2547. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2548. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2549. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2550. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2551. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2552. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2553. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2554. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2555. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2556. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2557. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2558. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2559. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2560. /*
  2561. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2562. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2563. * are no completions for failed cases. Hence updating tx_failed from
  2564. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2565. * then this has to be removed
  2566. */
  2567. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2568. peer->stats.tx.dropped.fw_rem_notx +
  2569. peer->stats.tx.dropped.fw_rem_tx +
  2570. peer->stats.tx.dropped.age_out +
  2571. peer->stats.tx.dropped.fw_reason1 +
  2572. peer->stats.tx.dropped.fw_reason2 +
  2573. peer->stats.tx.dropped.fw_reason3;
  2574. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2575. tid_stats->tqm_status_cnt[ts->status]++;
  2576. }
  2577. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2578. return;
  2579. }
  2580. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2581. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2582. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2583. /*
  2584. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2585. * Return from here if HTT PPDU events are enabled.
  2586. */
  2587. if (!(soc->process_tx_status))
  2588. return;
  2589. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2590. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2591. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2592. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2593. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2594. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2595. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2596. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2597. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2598. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2599. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2600. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2601. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2602. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2603. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2604. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2605. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2606. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2607. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2608. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2609. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2610. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2611. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2612. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2613. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2614. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2615. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2616. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2617. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2618. &peer->stats, ts->peer_id,
  2619. UPDATE_PEER_STATS, pdev->pdev_id);
  2620. #endif
  2621. }
  2622. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2623. /**
  2624. * dp_tx_flow_pool_lock() - take flow pool lock
  2625. * @soc: core txrx main context
  2626. * @tx_desc: tx desc
  2627. *
  2628. * Return: None
  2629. */
  2630. static inline
  2631. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2632. struct dp_tx_desc_s *tx_desc)
  2633. {
  2634. struct dp_tx_desc_pool_s *pool;
  2635. uint8_t desc_pool_id;
  2636. desc_pool_id = tx_desc->pool_id;
  2637. pool = &soc->tx_desc[desc_pool_id];
  2638. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2639. }
  2640. /**
  2641. * dp_tx_flow_pool_unlock() - release flow pool lock
  2642. * @soc: core txrx main context
  2643. * @tx_desc: tx desc
  2644. *
  2645. * Return: None
  2646. */
  2647. static inline
  2648. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2649. struct dp_tx_desc_s *tx_desc)
  2650. {
  2651. struct dp_tx_desc_pool_s *pool;
  2652. uint8_t desc_pool_id;
  2653. desc_pool_id = tx_desc->pool_id;
  2654. pool = &soc->tx_desc[desc_pool_id];
  2655. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2656. }
  2657. #else
  2658. static inline
  2659. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2660. {
  2661. }
  2662. static inline
  2663. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2664. {
  2665. }
  2666. #endif
  2667. /**
  2668. * dp_tx_notify_completion() - Notify tx completion for this desc
  2669. * @soc: core txrx main context
  2670. * @tx_desc: tx desc
  2671. * @netbuf: buffer
  2672. *
  2673. * Return: none
  2674. */
  2675. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2676. struct dp_tx_desc_s *tx_desc,
  2677. qdf_nbuf_t netbuf)
  2678. {
  2679. void *osif_dev;
  2680. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2681. qdf_assert(tx_desc);
  2682. dp_tx_flow_pool_lock(soc, tx_desc);
  2683. if (!tx_desc->vdev ||
  2684. !tx_desc->vdev->osif_vdev) {
  2685. dp_tx_flow_pool_unlock(soc, tx_desc);
  2686. return;
  2687. }
  2688. osif_dev = tx_desc->vdev->osif_vdev;
  2689. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2690. dp_tx_flow_pool_unlock(soc, tx_desc);
  2691. if (tx_compl_cbk)
  2692. tx_compl_cbk(netbuf, osif_dev);
  2693. }
  2694. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2695. * @pdev: pdev handle
  2696. * @tid: tid value
  2697. * @txdesc_ts: timestamp from txdesc
  2698. * @ppdu_id: ppdu id
  2699. *
  2700. * Return: none
  2701. */
  2702. #ifdef FEATURE_PERPKT_INFO
  2703. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2704. struct dp_peer *peer,
  2705. uint8_t tid,
  2706. uint64_t txdesc_ts,
  2707. uint32_t ppdu_id)
  2708. {
  2709. uint64_t delta_ms;
  2710. struct cdp_tx_sojourn_stats *sojourn_stats;
  2711. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2712. return;
  2713. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2714. tid >= CDP_DATA_TID_MAX))
  2715. return;
  2716. if (qdf_unlikely(!pdev->sojourn_buf))
  2717. return;
  2718. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2719. qdf_nbuf_data(pdev->sojourn_buf);
  2720. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2721. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2722. txdesc_ts;
  2723. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2724. delta_ms);
  2725. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2726. sojourn_stats->num_msdus[tid] = 1;
  2727. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2728. peer->avg_sojourn_msdu[tid].internal;
  2729. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2730. pdev->sojourn_buf, HTT_INVALID_PEER,
  2731. WDI_NO_VAL, pdev->pdev_id);
  2732. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2733. sojourn_stats->num_msdus[tid] = 0;
  2734. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2735. }
  2736. #else
  2737. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2738. struct dp_peer *peer,
  2739. uint8_t tid,
  2740. uint64_t txdesc_ts,
  2741. uint32_t ppdu_id)
  2742. {
  2743. }
  2744. #endif
  2745. /**
  2746. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2747. * @soc: DP Soc handle
  2748. * @tx_desc: software Tx descriptor
  2749. * @ts : Tx completion status from HAL/HTT descriptor
  2750. *
  2751. * Return: none
  2752. */
  2753. static inline void
  2754. dp_tx_comp_process_desc(struct dp_soc *soc,
  2755. struct dp_tx_desc_s *desc,
  2756. struct hal_tx_completion_status *ts,
  2757. struct dp_peer *peer)
  2758. {
  2759. uint64_t time_latency = 0;
  2760. /*
  2761. * m_copy/tx_capture modes are not supported for
  2762. * scatter gather packets
  2763. */
  2764. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2765. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2766. desc->timestamp);
  2767. }
  2768. if (!(desc->msdu_ext_desc)) {
  2769. if (QDF_STATUS_SUCCESS ==
  2770. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2771. return;
  2772. }
  2773. if (QDF_STATUS_SUCCESS ==
  2774. dp_get_completion_indication_for_stack(soc,
  2775. desc->pdev,
  2776. peer, ts,
  2777. desc->nbuf,
  2778. time_latency)) {
  2779. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2780. QDF_DMA_TO_DEVICE);
  2781. dp_send_completion_to_stack(soc,
  2782. desc->pdev,
  2783. ts->peer_id,
  2784. ts->ppdu_id,
  2785. desc->nbuf);
  2786. return;
  2787. }
  2788. }
  2789. dp_tx_comp_free_buf(soc, desc);
  2790. }
  2791. /**
  2792. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2793. * @tx_desc: software descriptor head pointer
  2794. * @ts: Tx completion status
  2795. * @peer: peer handle
  2796. * @ring_id: ring number
  2797. *
  2798. * Return: none
  2799. */
  2800. static inline
  2801. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2802. struct hal_tx_completion_status *ts,
  2803. struct dp_peer *peer, uint8_t ring_id)
  2804. {
  2805. uint32_t length;
  2806. qdf_ether_header_t *eh;
  2807. struct dp_soc *soc = NULL;
  2808. struct dp_vdev *vdev = tx_desc->vdev;
  2809. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2810. if (!vdev || !nbuf) {
  2811. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  2812. goto out;
  2813. }
  2814. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2815. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2816. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2817. QDF_TRACE_DEFAULT_PDEV_ID,
  2818. qdf_nbuf_data_addr(nbuf),
  2819. sizeof(qdf_nbuf_data(nbuf)),
  2820. tx_desc->id,
  2821. ts->status));
  2822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2823. "-------------------- \n"
  2824. "Tx Completion Stats: \n"
  2825. "-------------------- \n"
  2826. "ack_frame_rssi = %d \n"
  2827. "first_msdu = %d \n"
  2828. "last_msdu = %d \n"
  2829. "msdu_part_of_amsdu = %d \n"
  2830. "rate_stats valid = %d \n"
  2831. "bw = %d \n"
  2832. "pkt_type = %d \n"
  2833. "stbc = %d \n"
  2834. "ldpc = %d \n"
  2835. "sgi = %d \n"
  2836. "mcs = %d \n"
  2837. "ofdma = %d \n"
  2838. "tones_in_ru = %d \n"
  2839. "tsf = %d \n"
  2840. "ppdu_id = %d \n"
  2841. "transmit_cnt = %d \n"
  2842. "tid = %d \n"
  2843. "peer_id = %d\n",
  2844. ts->ack_frame_rssi, ts->first_msdu,
  2845. ts->last_msdu, ts->msdu_part_of_amsdu,
  2846. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2847. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2848. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2849. ts->transmit_cnt, ts->tid, ts->peer_id);
  2850. soc = vdev->pdev->soc;
  2851. /* Update SoC level stats */
  2852. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2853. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2854. /* Update per-packet stats for mesh mode */
  2855. if (qdf_unlikely(vdev->mesh_vdev) &&
  2856. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2857. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2858. length = qdf_nbuf_len(nbuf);
  2859. /* Update peer level stats */
  2860. if (!peer) {
  2861. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2862. "peer is null or deletion in progress");
  2863. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2864. goto out;
  2865. }
  2866. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2867. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2868. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2869. if ((peer->vdev->tx_encap_type ==
  2870. htt_cmn_pkt_type_ethernet) &&
  2871. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2872. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2873. }
  2874. }
  2875. } else {
  2876. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2877. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2878. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2879. }
  2880. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2881. #ifdef QCA_SUPPORT_RDK_STATS
  2882. if (soc->wlanstats_enabled)
  2883. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2884. tx_desc->timestamp,
  2885. ts->ppdu_id);
  2886. #endif
  2887. out:
  2888. return;
  2889. }
  2890. /**
  2891. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2892. * @soc: core txrx main context
  2893. * @comp_head: software descriptor head pointer
  2894. * @ring_id: ring number
  2895. *
  2896. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2897. * and release the software descriptors after processing is complete
  2898. *
  2899. * Return: none
  2900. */
  2901. static void
  2902. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2903. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2904. {
  2905. struct dp_tx_desc_s *desc;
  2906. struct dp_tx_desc_s *next;
  2907. struct hal_tx_completion_status ts = {0};
  2908. struct dp_peer *peer;
  2909. qdf_nbuf_t netbuf;
  2910. desc = comp_head;
  2911. while (desc) {
  2912. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2913. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2914. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2915. netbuf = desc->nbuf;
  2916. /* check tx complete notification */
  2917. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2918. dp_tx_notify_completion(soc, desc, netbuf);
  2919. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2920. if (peer)
  2921. dp_peer_unref_del_find_by_id(peer);
  2922. next = desc->next;
  2923. dp_tx_desc_release(desc, desc->pool_id);
  2924. desc = next;
  2925. }
  2926. }
  2927. /**
  2928. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2929. * @tx_desc: software descriptor head pointer
  2930. * @status : Tx completion status from HTT descriptor
  2931. * @ring_id: ring number
  2932. *
  2933. * This function will process HTT Tx indication messages from Target
  2934. *
  2935. * Return: none
  2936. */
  2937. static
  2938. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2939. uint8_t ring_id)
  2940. {
  2941. uint8_t tx_status;
  2942. struct dp_pdev *pdev;
  2943. struct dp_vdev *vdev;
  2944. struct dp_soc *soc;
  2945. struct hal_tx_completion_status ts = {0};
  2946. uint32_t *htt_desc = (uint32_t *)status;
  2947. struct dp_peer *peer;
  2948. struct cdp_tid_tx_stats *tid_stats = NULL;
  2949. struct htt_soc *htt_handle;
  2950. qdf_assert(tx_desc->pdev);
  2951. pdev = tx_desc->pdev;
  2952. vdev = tx_desc->vdev;
  2953. soc = pdev->soc;
  2954. if (!vdev)
  2955. return;
  2956. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2957. htt_handle = (struct htt_soc *)soc->htt_handle;
  2958. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2959. switch (tx_status) {
  2960. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2961. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2962. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2963. {
  2964. uint8_t tid;
  2965. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2966. ts.peer_id =
  2967. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2968. htt_desc[2]);
  2969. ts.tid =
  2970. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2971. htt_desc[2]);
  2972. } else {
  2973. ts.peer_id = HTT_INVALID_PEER;
  2974. ts.tid = HTT_INVALID_TID;
  2975. }
  2976. ts.ppdu_id =
  2977. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2978. htt_desc[1]);
  2979. ts.ack_frame_rssi =
  2980. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2981. htt_desc[1]);
  2982. ts.first_msdu = 1;
  2983. ts.last_msdu = 1;
  2984. tid = ts.tid;
  2985. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2986. tid = CDP_MAX_DATA_TIDS - 1;
  2987. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2988. if (qdf_unlikely(pdev->delay_stats_flag))
  2989. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2990. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2991. tid_stats->htt_status_cnt[tx_status]++;
  2992. }
  2993. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2994. if (qdf_likely(peer))
  2995. dp_peer_unref_del_find_by_id(peer);
  2996. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2997. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2998. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2999. break;
  3000. }
  3001. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3002. {
  3003. dp_tx_reinject_handler(tx_desc, status);
  3004. break;
  3005. }
  3006. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3007. {
  3008. dp_tx_inspect_handler(tx_desc, status);
  3009. break;
  3010. }
  3011. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3012. {
  3013. dp_tx_mec_handler(vdev, status);
  3014. break;
  3015. }
  3016. default:
  3017. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3018. "%s Invalid HTT tx_status %d\n",
  3019. __func__, tx_status);
  3020. break;
  3021. }
  3022. }
  3023. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3024. static inline
  3025. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3026. {
  3027. bool limit_hit = false;
  3028. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3029. limit_hit =
  3030. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3031. if (limit_hit)
  3032. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3033. return limit_hit;
  3034. }
  3035. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3036. {
  3037. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3038. }
  3039. #else
  3040. static inline
  3041. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3042. {
  3043. return false;
  3044. }
  3045. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3046. {
  3047. return false;
  3048. }
  3049. #endif
  3050. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3051. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3052. uint32_t quota)
  3053. {
  3054. void *tx_comp_hal_desc;
  3055. uint8_t buffer_src;
  3056. uint8_t pool_id;
  3057. uint32_t tx_desc_id;
  3058. struct dp_tx_desc_s *tx_desc = NULL;
  3059. struct dp_tx_desc_s *head_desc = NULL;
  3060. struct dp_tx_desc_s *tail_desc = NULL;
  3061. uint32_t num_processed = 0;
  3062. uint32_t count = 0;
  3063. bool force_break = false;
  3064. DP_HIST_INIT();
  3065. more_data:
  3066. /* Re-initialize local variables to be re-used */
  3067. head_desc = NULL;
  3068. tail_desc = NULL;
  3069. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3070. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3071. return 0;
  3072. }
  3073. /* Find head descriptor from completion ring */
  3074. while (qdf_likely(tx_comp_hal_desc =
  3075. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  3076. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3077. /* If this buffer was not released by TQM or FW, then it is not
  3078. * Tx completion indication, assert */
  3079. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3080. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3081. uint8_t wbm_internal_error;
  3082. dp_err_rl(
  3083. "Tx comp release_src != TQM | FW but from %d",
  3084. buffer_src);
  3085. hal_dump_comp_desc(tx_comp_hal_desc);
  3086. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3087. /* When WBM sees NULL buffer_addr_info in any of
  3088. * ingress rings it sends an error indication,
  3089. * with wbm_internal_error=1, to a specific ring.
  3090. * The WBM2SW ring used to indicate these errors is
  3091. * fixed in HW, and that ring is being used as Tx
  3092. * completion ring. These errors are not related to
  3093. * Tx completions, and should just be ignored
  3094. */
  3095. wbm_internal_error = hal_get_wbm_internal_error(
  3096. soc->hal_soc,
  3097. tx_comp_hal_desc);
  3098. if (wbm_internal_error) {
  3099. dp_err_rl("Tx comp wbm_internal_error!!");
  3100. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3101. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3102. buffer_src)
  3103. dp_handle_wbm_internal_error(
  3104. soc,
  3105. tx_comp_hal_desc,
  3106. hal_tx_comp_get_buffer_type(
  3107. tx_comp_hal_desc));
  3108. } else {
  3109. dp_err_rl("Tx comp wbm_internal_error false");
  3110. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3111. }
  3112. continue;
  3113. }
  3114. /* Get descriptor id */
  3115. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3116. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3117. DP_TX_DESC_ID_POOL_OS;
  3118. /* Find Tx descriptor */
  3119. tx_desc = dp_tx_desc_find(soc, pool_id,
  3120. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3121. DP_TX_DESC_ID_PAGE_OS,
  3122. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3123. DP_TX_DESC_ID_OFFSET_OS);
  3124. /*
  3125. * If the descriptor is already freed in vdev_detach,
  3126. * continue to next descriptor
  3127. */
  3128. if (!tx_desc->vdev && !tx_desc->flags) {
  3129. QDF_TRACE(QDF_MODULE_ID_DP,
  3130. QDF_TRACE_LEVEL_INFO,
  3131. "Descriptor freed in vdev_detach %d",
  3132. tx_desc_id);
  3133. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3134. count++;
  3135. continue;
  3136. }
  3137. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3138. QDF_TRACE(QDF_MODULE_ID_DP,
  3139. QDF_TRACE_LEVEL_INFO,
  3140. "pdev in down state %d",
  3141. tx_desc_id);
  3142. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3143. count++;
  3144. dp_tx_comp_free_buf(soc, tx_desc);
  3145. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3146. continue;
  3147. }
  3148. /*
  3149. * If the release source is FW, process the HTT status
  3150. */
  3151. if (qdf_unlikely(buffer_src ==
  3152. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3153. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3154. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3155. htt_tx_status);
  3156. dp_tx_process_htt_completion(tx_desc,
  3157. htt_tx_status, ring_id);
  3158. } else {
  3159. /* Pool id is not matching. Error */
  3160. if (tx_desc->pool_id != pool_id) {
  3161. QDF_TRACE(QDF_MODULE_ID_DP,
  3162. QDF_TRACE_LEVEL_FATAL,
  3163. "Tx Comp pool id %d not matched %d",
  3164. pool_id, tx_desc->pool_id);
  3165. qdf_assert_always(0);
  3166. }
  3167. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3168. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3169. QDF_TRACE(QDF_MODULE_ID_DP,
  3170. QDF_TRACE_LEVEL_FATAL,
  3171. "Txdesc invalid, flgs = %x,id = %d",
  3172. tx_desc->flags, tx_desc_id);
  3173. qdf_assert_always(0);
  3174. }
  3175. /* First ring descriptor on the cycle */
  3176. if (!head_desc) {
  3177. head_desc = tx_desc;
  3178. tail_desc = tx_desc;
  3179. }
  3180. tail_desc->next = tx_desc;
  3181. tx_desc->next = NULL;
  3182. tail_desc = tx_desc;
  3183. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3184. /* Collect hw completion contents */
  3185. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3186. &tx_desc->comp, 1);
  3187. }
  3188. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3189. /*
  3190. * Processed packet count is more than given quota
  3191. * stop to processing
  3192. */
  3193. if (num_processed >= quota) {
  3194. force_break = true;
  3195. break;
  3196. }
  3197. count++;
  3198. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3199. break;
  3200. }
  3201. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3202. /* Process the reaped descriptors */
  3203. if (head_desc)
  3204. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3205. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3206. if (!force_break &&
  3207. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3208. hal_ring_hdl)) {
  3209. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3210. if (!hif_exec_should_yield(soc->hif_handle,
  3211. int_ctx->dp_intr_id))
  3212. goto more_data;
  3213. }
  3214. }
  3215. DP_TX_HIST_STATS_PER_PDEV();
  3216. return num_processed;
  3217. }
  3218. #ifdef FEATURE_WLAN_TDLS
  3219. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3220. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3221. {
  3222. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3223. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3224. if (!vdev) {
  3225. dp_err("vdev handle for id %d is NULL", vdev_id);
  3226. return NULL;
  3227. }
  3228. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3229. vdev->is_tdls_frame = true;
  3230. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3231. }
  3232. #endif
  3233. /**
  3234. * dp_tx_vdev_attach() - attach vdev to dp tx
  3235. * @vdev: virtual device instance
  3236. *
  3237. * Return: QDF_STATUS_SUCCESS: success
  3238. * QDF_STATUS_E_RESOURCES: Error return
  3239. */
  3240. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3241. {
  3242. int pdev_id;
  3243. /*
  3244. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3245. */
  3246. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3247. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3248. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3249. vdev->vdev_id);
  3250. pdev_id =
  3251. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3252. vdev->pdev->pdev_id);
  3253. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3254. /*
  3255. * Set HTT Extension Valid bit to 0 by default
  3256. */
  3257. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3258. dp_tx_vdev_update_search_flags(vdev);
  3259. return QDF_STATUS_SUCCESS;
  3260. }
  3261. #ifndef FEATURE_WDS
  3262. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3263. {
  3264. return false;
  3265. }
  3266. #endif
  3267. /**
  3268. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3269. * @vdev: virtual device instance
  3270. *
  3271. * Return: void
  3272. *
  3273. */
  3274. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3275. {
  3276. struct dp_soc *soc = vdev->pdev->soc;
  3277. /*
  3278. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3279. * for TDLS link
  3280. *
  3281. * Enable AddrY (SA based search) only for non-WDS STA and
  3282. * ProxySTA VAP (in HKv1) modes.
  3283. *
  3284. * In all other VAP modes, only DA based search should be
  3285. * enabled
  3286. */
  3287. if (vdev->opmode == wlan_op_mode_sta &&
  3288. vdev->tdls_link_connected)
  3289. vdev->hal_desc_addr_search_flags =
  3290. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3291. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3292. !dp_tx_da_search_override(vdev))
  3293. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3294. else
  3295. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3296. /* Set search type only when peer map v2 messaging is enabled
  3297. * as we will have the search index (AST hash) only when v2 is
  3298. * enabled
  3299. */
  3300. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3301. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3302. else
  3303. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3304. }
  3305. static inline bool
  3306. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3307. struct dp_vdev *vdev,
  3308. struct dp_tx_desc_s *tx_desc)
  3309. {
  3310. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3311. return false;
  3312. /*
  3313. * if vdev is given, then only check whether desc
  3314. * vdev match. if vdev is NULL, then check whether
  3315. * desc pdev match.
  3316. */
  3317. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3318. }
  3319. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3320. /**
  3321. * dp_tx_desc_flush() - release resources associated
  3322. * to TX Desc
  3323. *
  3324. * @dp_pdev: Handle to DP pdev structure
  3325. * @vdev: virtual device instance
  3326. * NULL: no specific Vdev is required and check all allcated TX desc
  3327. * on this pdev.
  3328. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3329. *
  3330. * @force_free:
  3331. * true: flush the TX desc.
  3332. * false: only reset the Vdev in each allocated TX desc
  3333. * that associated to current Vdev.
  3334. *
  3335. * This function will go through the TX desc pool to flush
  3336. * the outstanding TX data or reset Vdev to NULL in associated TX
  3337. * Desc.
  3338. */
  3339. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3340. struct dp_vdev *vdev,
  3341. bool force_free)
  3342. {
  3343. uint8_t i;
  3344. uint32_t j;
  3345. uint32_t num_desc, page_id, offset;
  3346. uint16_t num_desc_per_page;
  3347. struct dp_soc *soc = pdev->soc;
  3348. struct dp_tx_desc_s *tx_desc = NULL;
  3349. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3350. if (!vdev && !force_free) {
  3351. dp_err("Reset TX desc vdev, Vdev param is required!");
  3352. return;
  3353. }
  3354. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3355. tx_desc_pool = &soc->tx_desc[i];
  3356. if (!(tx_desc_pool->pool_size) ||
  3357. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3358. !(tx_desc_pool->desc_pages.cacheable_pages))
  3359. continue;
  3360. /*
  3361. * Add flow pool lock protection in case pool is freed
  3362. * due to all tx_desc is recycled when handle TX completion.
  3363. * this is not necessary when do force flush as:
  3364. * a. double lock will happen if dp_tx_desc_release is
  3365. * also trying to acquire it.
  3366. * b. dp interrupt has been disabled before do force TX desc
  3367. * flush in dp_pdev_deinit().
  3368. */
  3369. if (!force_free)
  3370. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3371. num_desc = tx_desc_pool->pool_size;
  3372. num_desc_per_page =
  3373. tx_desc_pool->desc_pages.num_element_per_page;
  3374. for (j = 0; j < num_desc; j++) {
  3375. page_id = j / num_desc_per_page;
  3376. offset = j % num_desc_per_page;
  3377. if (qdf_unlikely(!(tx_desc_pool->
  3378. desc_pages.cacheable_pages)))
  3379. break;
  3380. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3381. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3382. /*
  3383. * Free TX desc if force free is
  3384. * required, otherwise only reset vdev
  3385. * in this TX desc.
  3386. */
  3387. if (force_free) {
  3388. dp_tx_comp_free_buf(soc, tx_desc);
  3389. dp_tx_desc_release(tx_desc, i);
  3390. } else {
  3391. tx_desc->vdev = NULL;
  3392. }
  3393. }
  3394. }
  3395. if (!force_free)
  3396. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3397. }
  3398. }
  3399. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3400. /**
  3401. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3402. *
  3403. * @soc: Handle to DP soc structure
  3404. * @tx_desc: pointer of one TX desc
  3405. * @desc_pool_id: TX Desc pool id
  3406. */
  3407. static inline void
  3408. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3409. uint8_t desc_pool_id)
  3410. {
  3411. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3412. tx_desc->vdev = NULL;
  3413. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3414. }
  3415. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3416. struct dp_vdev *vdev,
  3417. bool force_free)
  3418. {
  3419. uint8_t i, num_pool;
  3420. uint32_t j;
  3421. uint32_t num_desc, page_id, offset;
  3422. uint16_t num_desc_per_page;
  3423. struct dp_soc *soc = pdev->soc;
  3424. struct dp_tx_desc_s *tx_desc = NULL;
  3425. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3426. if (!vdev && !force_free) {
  3427. dp_err("Reset TX desc vdev, Vdev param is required!");
  3428. return;
  3429. }
  3430. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3431. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3432. for (i = 0; i < num_pool; i++) {
  3433. tx_desc_pool = &soc->tx_desc[i];
  3434. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3435. continue;
  3436. num_desc_per_page =
  3437. tx_desc_pool->desc_pages.num_element_per_page;
  3438. for (j = 0; j < num_desc; j++) {
  3439. page_id = j / num_desc_per_page;
  3440. offset = j % num_desc_per_page;
  3441. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3442. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3443. if (force_free) {
  3444. dp_tx_comp_free_buf(soc, tx_desc);
  3445. dp_tx_desc_release(tx_desc, i);
  3446. } else {
  3447. dp_tx_desc_reset_vdev(soc, tx_desc,
  3448. i);
  3449. }
  3450. }
  3451. }
  3452. }
  3453. }
  3454. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3455. /**
  3456. * dp_tx_vdev_detach() - detach vdev from dp tx
  3457. * @vdev: virtual device instance
  3458. *
  3459. * Return: QDF_STATUS_SUCCESS: success
  3460. * QDF_STATUS_E_RESOURCES: Error return
  3461. */
  3462. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3463. {
  3464. struct dp_pdev *pdev = vdev->pdev;
  3465. /* Reset TX desc associated to this Vdev as NULL */
  3466. dp_tx_desc_flush(pdev, vdev, false);
  3467. dp_tx_vdev_multipass_deinit(vdev);
  3468. return QDF_STATUS_SUCCESS;
  3469. }
  3470. /**
  3471. * dp_tx_pdev_attach() - attach pdev to dp tx
  3472. * @pdev: physical device instance
  3473. *
  3474. * Return: QDF_STATUS_SUCCESS: success
  3475. * QDF_STATUS_E_RESOURCES: Error return
  3476. */
  3477. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3478. {
  3479. struct dp_soc *soc = pdev->soc;
  3480. /* Initialize Flow control counters */
  3481. qdf_atomic_init(&pdev->num_tx_exception);
  3482. qdf_atomic_init(&pdev->num_tx_outstanding);
  3483. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3484. /* Initialize descriptors in TCL Ring */
  3485. hal_tx_init_data_ring(soc->hal_soc,
  3486. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3487. }
  3488. return QDF_STATUS_SUCCESS;
  3489. }
  3490. /**
  3491. * dp_tx_pdev_detach() - detach pdev from dp tx
  3492. * @pdev: physical device instance
  3493. *
  3494. * Return: QDF_STATUS_SUCCESS: success
  3495. * QDF_STATUS_E_RESOURCES: Error return
  3496. */
  3497. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3498. {
  3499. /* flush TX outstanding data per pdev */
  3500. dp_tx_desc_flush(pdev, NULL, true);
  3501. dp_tx_me_exit(pdev);
  3502. return QDF_STATUS_SUCCESS;
  3503. }
  3504. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3505. /* Pools will be allocated dynamically */
  3506. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3507. int num_desc)
  3508. {
  3509. uint8_t i;
  3510. for (i = 0; i < num_pool; i++) {
  3511. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3512. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3513. }
  3514. return 0;
  3515. }
  3516. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3517. {
  3518. uint8_t i;
  3519. for (i = 0; i < num_pool; i++)
  3520. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3521. }
  3522. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3523. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3524. int num_desc)
  3525. {
  3526. uint8_t i;
  3527. /* Allocate software Tx descriptor pools */
  3528. for (i = 0; i < num_pool; i++) {
  3529. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3530. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3531. "%s Tx Desc Pool alloc %d failed %pK",
  3532. __func__, i, soc);
  3533. return ENOMEM;
  3534. }
  3535. }
  3536. return 0;
  3537. }
  3538. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3539. {
  3540. uint8_t i;
  3541. for (i = 0; i < num_pool; i++) {
  3542. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3543. if (dp_tx_desc_pool_free(soc, i)) {
  3544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3545. "%s Tx Desc Pool Free failed", __func__);
  3546. }
  3547. }
  3548. }
  3549. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3550. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3551. /**
  3552. * dp_tso_attach_wifi3() - TSO attach handler
  3553. * @txrx_soc: Opaque Dp handle
  3554. *
  3555. * Reserve TSO descriptor buffers
  3556. *
  3557. * Return: QDF_STATUS_E_FAILURE on failure or
  3558. * QDF_STATUS_SUCCESS on success
  3559. */
  3560. static
  3561. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3562. {
  3563. return dp_tso_soc_attach(txrx_soc);
  3564. }
  3565. /**
  3566. * dp_tso_detach_wifi3() - TSO Detach handler
  3567. * @txrx_soc: Opaque Dp handle
  3568. *
  3569. * Deallocate TSO descriptor buffers
  3570. *
  3571. * Return: QDF_STATUS_E_FAILURE on failure or
  3572. * QDF_STATUS_SUCCESS on success
  3573. */
  3574. static
  3575. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3576. {
  3577. return dp_tso_soc_detach(txrx_soc);
  3578. }
  3579. #else
  3580. static
  3581. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3582. {
  3583. return QDF_STATUS_SUCCESS;
  3584. }
  3585. static
  3586. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3587. {
  3588. return QDF_STATUS_SUCCESS;
  3589. }
  3590. #endif
  3591. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  3592. {
  3593. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3594. uint8_t i;
  3595. uint8_t num_pool;
  3596. uint32_t num_desc;
  3597. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3598. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3599. for (i = 0; i < num_pool; i++)
  3600. dp_tx_tso_desc_pool_free(soc, i);
  3601. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3602. __func__, num_pool, num_desc);
  3603. for (i = 0; i < num_pool; i++)
  3604. dp_tx_tso_num_seg_pool_free(soc, i);
  3605. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3606. __func__, num_pool, num_desc);
  3607. return QDF_STATUS_SUCCESS;
  3608. }
  3609. /**
  3610. * dp_tso_attach() - TSO attach handler
  3611. * @txrx_soc: Opaque Dp handle
  3612. *
  3613. * Reserve TSO descriptor buffers
  3614. *
  3615. * Return: QDF_STATUS_E_FAILURE on failure or
  3616. * QDF_STATUS_SUCCESS on success
  3617. */
  3618. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  3619. {
  3620. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3621. uint8_t i;
  3622. uint8_t num_pool;
  3623. uint32_t num_desc;
  3624. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3625. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3626. for (i = 0; i < num_pool; i++) {
  3627. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3628. dp_err("TSO Desc Pool alloc %d failed %pK",
  3629. i, soc);
  3630. return QDF_STATUS_E_FAILURE;
  3631. }
  3632. }
  3633. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3634. __func__, num_pool, num_desc);
  3635. for (i = 0; i < num_pool; i++) {
  3636. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3637. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3638. i, soc);
  3639. return QDF_STATUS_E_FAILURE;
  3640. }
  3641. }
  3642. return QDF_STATUS_SUCCESS;
  3643. }
  3644. /**
  3645. * dp_tx_soc_detach() - detach soc from dp tx
  3646. * @soc: core txrx main context
  3647. *
  3648. * This function will detach dp tx into main device context
  3649. * will free dp tx resource and initialize resources
  3650. *
  3651. * Return: QDF_STATUS_SUCCESS: success
  3652. * QDF_STATUS_E_RESOURCES: Error return
  3653. */
  3654. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3655. {
  3656. uint8_t num_pool;
  3657. uint16_t num_desc;
  3658. uint16_t num_ext_desc;
  3659. uint8_t i;
  3660. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3661. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3662. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3663. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3664. dp_tx_flow_control_deinit(soc);
  3665. dp_tx_delete_static_pools(soc, num_pool);
  3666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3667. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3668. __func__, num_pool, num_desc);
  3669. for (i = 0; i < num_pool; i++) {
  3670. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3671. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3672. "%s Tx Ext Desc Pool Free failed",
  3673. __func__);
  3674. return QDF_STATUS_E_RESOURCES;
  3675. }
  3676. }
  3677. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3678. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3679. __func__, num_pool, num_ext_desc);
  3680. status = dp_tso_detach_wifi3(soc);
  3681. if (status != QDF_STATUS_SUCCESS)
  3682. return status;
  3683. return QDF_STATUS_SUCCESS;
  3684. }
  3685. /**
  3686. * dp_tx_soc_attach() - attach soc to dp tx
  3687. * @soc: core txrx main context
  3688. *
  3689. * This function will attach dp tx into main device context
  3690. * will allocate dp tx resource and initialize resources
  3691. *
  3692. * Return: QDF_STATUS_SUCCESS: success
  3693. * QDF_STATUS_E_RESOURCES: Error return
  3694. */
  3695. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3696. {
  3697. uint8_t i;
  3698. uint8_t num_pool;
  3699. uint32_t num_desc;
  3700. uint32_t num_ext_desc;
  3701. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3702. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3703. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3704. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3706. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3707. __func__, num_pool, num_desc);
  3708. if ((num_pool > MAX_TXDESC_POOLS) ||
  3709. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  3710. goto fail;
  3711. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3712. goto fail;
  3713. dp_tx_flow_control_init(soc);
  3714. /* Allocate extension tx descriptor pools */
  3715. for (i = 0; i < num_pool; i++) {
  3716. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3718. "MSDU Ext Desc Pool alloc %d failed %pK",
  3719. i, soc);
  3720. goto fail;
  3721. }
  3722. }
  3723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3724. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3725. __func__, num_pool, num_ext_desc);
  3726. status = dp_tso_attach_wifi3((void *)soc);
  3727. if (status != QDF_STATUS_SUCCESS)
  3728. goto fail;
  3729. /* Initialize descriptors in TCL Rings */
  3730. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3731. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3732. hal_tx_init_data_ring(soc->hal_soc,
  3733. soc->tcl_data_ring[i].hal_srng);
  3734. }
  3735. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3736. hal_tx_init_data_ring(soc->hal_soc,
  3737. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng);
  3738. }
  3739. /*
  3740. * Initialize command/credit ring descriptor
  3741. * Command/CREDIT ring also used for sending DATA cmds
  3742. */
  3743. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  3744. soc->tcl_cmd_credit_ring.hal_srng);
  3745. /*
  3746. * todo - Add a runtime config option to enable this.
  3747. */
  3748. /*
  3749. * Due to multiple issues on NPR EMU, enable it selectively
  3750. * only for NPR EMU, should be removed, once NPR platforms
  3751. * are stable.
  3752. */
  3753. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3754. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3755. "%s HAL Tx init Success", __func__);
  3756. return QDF_STATUS_SUCCESS;
  3757. fail:
  3758. /* Detach will take care of freeing only allocated resources */
  3759. dp_tx_soc_detach(soc);
  3760. return QDF_STATUS_E_RESOURCES;
  3761. }