dsi_drm.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. }
  48. if (msm_is_mode_seamless(drm_mode))
  49. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  50. if (msm_is_mode_dynamic_fps(drm_mode))
  51. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  52. if (msm_needs_vblank_pre_modeset(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  54. if (msm_is_mode_seamless_dms(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  56. if (msm_is_mode_seamless_vrr(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  58. if (msm_is_mode_seamless_poms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  60. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  62. dsi_mode->timing.h_sync_polarity =
  63. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  64. dsi_mode->timing.v_sync_polarity =
  65. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  66. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  67. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  68. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  69. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  70. }
  71. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  72. struct drm_display_mode *drm_mode)
  73. {
  74. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  75. memset(drm_mode, 0, sizeof(*drm_mode));
  76. drm_mode->hdisplay = dsi_mode->timing.h_active;
  77. drm_mode->hsync_start = drm_mode->hdisplay +
  78. dsi_mode->timing.h_front_porch;
  79. drm_mode->hsync_end = drm_mode->hsync_start +
  80. dsi_mode->timing.h_sync_width;
  81. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  82. drm_mode->hskew = dsi_mode->timing.h_skew;
  83. drm_mode->vdisplay = dsi_mode->timing.v_active;
  84. drm_mode->vsync_start = drm_mode->vdisplay +
  85. dsi_mode->timing.v_front_porch;
  86. drm_mode->vsync_end = drm_mode->vsync_start +
  87. dsi_mode->timing.v_sync_width;
  88. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  89. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  90. drm_mode->clock = dsi_mode->pixel_clk_khz;
  91. drm_mode->private = (int *)dsi_mode->priv_info;
  92. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  93. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  94. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  95. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  97. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  106. if (dsi_mode->timing.h_sync_polarity)
  107. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  108. if (dsi_mode->timing.v_sync_polarity)
  109. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  110. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  111. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  112. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  113. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  114. /* set mode name */
  115. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  116. drm_mode->hdisplay, drm_mode->vdisplay,
  117. drm_mode->vrefresh, drm_mode->clock,
  118. video_mode ? "vid" : "cmd");
  119. }
  120. static int dsi_bridge_attach(struct drm_bridge *bridge)
  121. {
  122. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  123. if (!bridge) {
  124. DSI_ERR("Invalid params\n");
  125. return -EINVAL;
  126. }
  127. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  128. return 0;
  129. }
  130. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  131. {
  132. int rc = 0;
  133. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  134. if (!bridge) {
  135. DSI_ERR("Invalid params\n");
  136. return;
  137. }
  138. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  139. DSI_ERR("Incorrect bridge details\n");
  140. return;
  141. }
  142. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  143. /* By this point mode should have been validated through mode_fixup */
  144. rc = dsi_display_set_mode(c_bridge->display,
  145. &(c_bridge->dsi_mode), 0x0);
  146. if (rc) {
  147. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  148. c_bridge->id, rc);
  149. return;
  150. }
  151. if (c_bridge->dsi_mode.dsi_mode_flags &
  152. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  153. DSI_MODE_FLAG_DYN_CLK)) {
  154. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  155. return;
  156. }
  157. SDE_ATRACE_BEGIN("dsi_display_prepare");
  158. rc = dsi_display_prepare(c_bridge->display);
  159. if (rc) {
  160. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  161. c_bridge->id, rc);
  162. SDE_ATRACE_END("dsi_display_prepare");
  163. return;
  164. }
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  175. if (rc)
  176. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  177. rc);
  178. }
  179. static void dsi_bridge_enable(struct drm_bridge *bridge)
  180. {
  181. int rc = 0;
  182. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  183. struct dsi_display *display;
  184. if (!bridge) {
  185. DSI_ERR("Invalid params\n");
  186. return;
  187. }
  188. if (c_bridge->dsi_mode.dsi_mode_flags &
  189. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  190. DSI_MODE_FLAG_DYN_CLK)) {
  191. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  192. return;
  193. }
  194. display = c_bridge->display;
  195. rc = dsi_display_post_enable(display);
  196. if (rc)
  197. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  198. c_bridge->id, rc);
  199. if (display && display->drm_conn) {
  200. sde_connector_helper_bridge_enable(display->drm_conn);
  201. if (c_bridge->dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)
  202. sde_connector_schedule_status_work(display->drm_conn,
  203. true);
  204. }
  205. }
  206. static void dsi_bridge_disable(struct drm_bridge *bridge)
  207. {
  208. int rc = 0;
  209. struct dsi_display *display;
  210. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  211. if (!bridge) {
  212. DSI_ERR("Invalid params\n");
  213. return;
  214. }
  215. display = c_bridge->display;
  216. if (display && display->drm_conn) {
  217. if (bridge->encoder->crtc->state->adjusted_mode.private_flags &
  218. MSM_MODE_FLAG_SEAMLESS_POMS) {
  219. display->poms_pending = true;
  220. /* Disable ESD thread, during panel mode switch */
  221. sde_connector_schedule_status_work(display->drm_conn,
  222. false);
  223. } else {
  224. display->poms_pending = false;
  225. sde_connector_helper_bridge_disable(display->drm_conn);
  226. }
  227. }
  228. rc = dsi_display_pre_disable(c_bridge->display);
  229. if (rc) {
  230. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  231. c_bridge->id, rc);
  232. }
  233. }
  234. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  235. {
  236. int rc = 0;
  237. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  238. if (!bridge) {
  239. DSI_ERR("Invalid params\n");
  240. return;
  241. }
  242. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  243. SDE_ATRACE_BEGIN("dsi_display_disable");
  244. rc = dsi_display_disable(c_bridge->display);
  245. if (rc) {
  246. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  247. c_bridge->id, rc);
  248. SDE_ATRACE_END("dsi_display_disable");
  249. return;
  250. }
  251. SDE_ATRACE_END("dsi_display_disable");
  252. rc = dsi_display_unprepare(c_bridge->display);
  253. if (rc) {
  254. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  255. c_bridge->id, rc);
  256. SDE_ATRACE_END("dsi_bridge_post_disable");
  257. return;
  258. }
  259. SDE_ATRACE_END("dsi_bridge_post_disable");
  260. }
  261. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  262. struct drm_display_mode *mode,
  263. struct drm_display_mode *adjusted_mode)
  264. {
  265. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  266. if (!bridge || !mode || !adjusted_mode) {
  267. DSI_ERR("Invalid params\n");
  268. return;
  269. }
  270. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  271. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  272. /* restore bit_clk_rate also for dynamic clk use cases */
  273. c_bridge->dsi_mode.timing.clk_rate_hz =
  274. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  275. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  276. }
  277. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  278. const struct drm_display_mode *mode,
  279. struct drm_display_mode *adjusted_mode)
  280. {
  281. int rc = 0;
  282. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  283. struct dsi_display *display;
  284. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  285. struct drm_crtc_state *crtc_state;
  286. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  287. if (!bridge || !mode || !adjusted_mode) {
  288. DSI_ERR("Invalid params\n");
  289. return false;
  290. }
  291. display = c_bridge->display;
  292. if (!display) {
  293. DSI_ERR("Invalid params\n");
  294. return false;
  295. }
  296. /*
  297. * if no timing defined in panel, it must be external mode
  298. * and we'll use empty priv info to populate the mode
  299. */
  300. if (display->panel && !display->panel->num_timing_nodes) {
  301. *adjusted_mode = *mode;
  302. adjusted_mode->private = (int *)&default_priv_info;
  303. adjusted_mode->private_flags = 0;
  304. return true;
  305. }
  306. convert_to_dsi_mode(mode, &dsi_mode);
  307. /*
  308. * retrieve dsi mode from dsi driver's cache since not safe to take
  309. * the drm mode config mutex in all paths
  310. */
  311. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  312. if (rc)
  313. return rc;
  314. /* propagate the private info to the adjusted_mode derived dsi mode */
  315. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  316. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  317. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  318. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  319. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  320. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  321. if (rc) {
  322. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  323. return false;
  324. }
  325. if (bridge->encoder && bridge->encoder->crtc &&
  326. crtc_state->crtc) {
  327. const struct drm_display_mode *cur_mode =
  328. &crtc_state->crtc->state->mode;
  329. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  330. cur_dsi_mode.timing.dsc_enabled =
  331. dsi_mode.priv_info->dsc_enabled;
  332. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  333. rc = dsi_display_validate_mode_change(c_bridge->display,
  334. &cur_dsi_mode, &dsi_mode);
  335. if (rc) {
  336. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  337. c_bridge->display->name, rc);
  338. return false;
  339. }
  340. /* No panel mode switch when drm pipeline is changing */
  341. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  342. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  343. (crtc_state->enable ==
  344. crtc_state->crtc->state->enable))
  345. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  346. /* No DMS/VRR when drm pipeline is changing */
  347. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  348. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  349. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  350. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  351. (!crtc_state->active_changed ||
  352. display->is_cont_splash_enabled))
  353. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  354. }
  355. /* Reject seamless transition when active changed */
  356. if (crtc_state->active_changed &&
  357. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  358. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))) {
  359. DSI_ERR("seamless upon active changed 0x%x %d\n",
  360. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  361. return false;
  362. }
  363. /* convert back to drm mode, propagating the private info & flags */
  364. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  365. return true;
  366. }
  367. u64 dsi_drm_find_bit_clk_rate(void *display,
  368. const struct drm_display_mode *drm_mode)
  369. {
  370. int i = 0, count = 0;
  371. struct dsi_display *dsi_display = display;
  372. struct dsi_display_mode *dsi_mode;
  373. u64 bit_clk_rate = 0;
  374. if (!dsi_display || !drm_mode)
  375. return 0;
  376. dsi_display_get_mode_count(dsi_display, &count);
  377. for (i = 0; i < count; i++) {
  378. dsi_mode = &dsi_display->modes[i];
  379. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  380. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  381. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  382. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  383. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  384. break;
  385. }
  386. }
  387. return bit_clk_rate;
  388. }
  389. int dsi_conn_get_mode_info(struct drm_connector *connector,
  390. const struct drm_display_mode *drm_mode,
  391. struct msm_mode_info *mode_info,
  392. void *display, const struct msm_resource_caps_info *avail_res)
  393. {
  394. struct dsi_display_mode dsi_mode;
  395. struct dsi_mode_info *timing;
  396. if (!drm_mode || !mode_info)
  397. return -EINVAL;
  398. convert_to_dsi_mode(drm_mode, &dsi_mode);
  399. if (!dsi_mode.priv_info)
  400. return -EINVAL;
  401. memset(mode_info, 0, sizeof(*mode_info));
  402. timing = &dsi_mode.timing;
  403. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  404. mode_info->vtotal = DSI_V_TOTAL(timing);
  405. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  406. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  407. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  408. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  409. mode_info->mdp_transfer_time_us =
  410. dsi_mode.priv_info->mdp_transfer_time_us;
  411. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  412. sizeof(struct msm_display_topology));
  413. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  414. if (dsi_mode.priv_info->dsc_enabled) {
  415. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  416. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  417. sizeof(dsi_mode.priv_info->dsc));
  418. mode_info->comp_info.comp_ratio =
  419. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1;
  420. }
  421. if (dsi_mode.priv_info->roi_caps.enabled) {
  422. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  423. sizeof(dsi_mode.priv_info->roi_caps));
  424. }
  425. return 0;
  426. }
  427. static const struct drm_bridge_funcs dsi_bridge_ops = {
  428. .attach = dsi_bridge_attach,
  429. .mode_fixup = dsi_bridge_mode_fixup,
  430. .pre_enable = dsi_bridge_pre_enable,
  431. .enable = dsi_bridge_enable,
  432. .disable = dsi_bridge_disable,
  433. .post_disable = dsi_bridge_post_disable,
  434. .mode_set = dsi_bridge_mode_set,
  435. };
  436. int dsi_conn_set_info_blob(struct drm_connector *connector,
  437. void *info, void *display, struct msm_mode_info *mode_info)
  438. {
  439. struct dsi_display *dsi_display = display;
  440. struct dsi_panel *panel;
  441. enum dsi_pixel_format fmt;
  442. u32 bpp;
  443. if (!info || !dsi_display)
  444. return -EINVAL;
  445. dsi_display->drm_conn = connector;
  446. sde_kms_info_add_keystr(info,
  447. "display type", dsi_display->display_type);
  448. switch (dsi_display->type) {
  449. case DSI_DISPLAY_SINGLE:
  450. sde_kms_info_add_keystr(info, "display config",
  451. "single display");
  452. break;
  453. case DSI_DISPLAY_EXT_BRIDGE:
  454. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  455. break;
  456. case DSI_DISPLAY_SPLIT:
  457. sde_kms_info_add_keystr(info, "display config",
  458. "split display");
  459. break;
  460. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  461. sde_kms_info_add_keystr(info, "display config",
  462. "split ext bridge");
  463. break;
  464. default:
  465. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  466. break;
  467. }
  468. if (!dsi_display->panel) {
  469. DSI_DEBUG("invalid panel data\n");
  470. goto end;
  471. }
  472. panel = dsi_display->panel;
  473. sde_kms_info_add_keystr(info, "panel name", panel->name);
  474. switch (panel->panel_mode) {
  475. case DSI_OP_VIDEO_MODE:
  476. sde_kms_info_add_keystr(info, "panel mode", "video");
  477. sde_kms_info_add_keystr(info, "qsync support",
  478. panel->qsync_min_fps ? "true" : "false");
  479. break;
  480. case DSI_OP_CMD_MODE:
  481. sde_kms_info_add_keystr(info, "panel mode", "command");
  482. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  483. mode_info->mdp_transfer_time_us);
  484. sde_kms_info_add_keystr(info, "qsync support",
  485. panel->qsync_min_fps ? "true" : "false");
  486. break;
  487. default:
  488. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  489. break;
  490. }
  491. sde_kms_info_add_keystr(info, "dfps support",
  492. panel->dfps_caps.dfps_support ? "true" : "false");
  493. if (panel->dfps_caps.dfps_support) {
  494. sde_kms_info_add_keyint(info, "min_fps",
  495. panel->dfps_caps.min_refresh_rate);
  496. sde_kms_info_add_keyint(info, "max_fps",
  497. panel->dfps_caps.max_refresh_rate);
  498. }
  499. sde_kms_info_add_keystr(info, "dyn bitclk support",
  500. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  501. switch (panel->phy_props.rotation) {
  502. case DSI_PANEL_ROTATE_NONE:
  503. sde_kms_info_add_keystr(info, "panel orientation", "none");
  504. break;
  505. case DSI_PANEL_ROTATE_H_FLIP:
  506. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  507. break;
  508. case DSI_PANEL_ROTATE_V_FLIP:
  509. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  510. break;
  511. case DSI_PANEL_ROTATE_HV_FLIP:
  512. sde_kms_info_add_keystr(info, "panel orientation",
  513. "horz & vert flip");
  514. break;
  515. default:
  516. DSI_DEBUG("invalid panel rotation:%d\n",
  517. panel->phy_props.rotation);
  518. break;
  519. }
  520. switch (panel->bl_config.type) {
  521. case DSI_BACKLIGHT_PWM:
  522. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  523. break;
  524. case DSI_BACKLIGHT_WLED:
  525. sde_kms_info_add_keystr(info, "backlight type", "wled");
  526. break;
  527. case DSI_BACKLIGHT_DCS:
  528. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  529. break;
  530. default:
  531. DSI_DEBUG("invalid panel backlight type:%d\n",
  532. panel->bl_config.type);
  533. break;
  534. }
  535. if (mode_info && mode_info->roi_caps.enabled) {
  536. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  537. mode_info->roi_caps.num_roi);
  538. sde_kms_info_add_keyint(info, "partial_update_xstart",
  539. mode_info->roi_caps.align.xstart_pix_align);
  540. sde_kms_info_add_keyint(info, "partial_update_walign",
  541. mode_info->roi_caps.align.width_pix_align);
  542. sde_kms_info_add_keyint(info, "partial_update_wmin",
  543. mode_info->roi_caps.align.min_width);
  544. sde_kms_info_add_keyint(info, "partial_update_ystart",
  545. mode_info->roi_caps.align.ystart_pix_align);
  546. sde_kms_info_add_keyint(info, "partial_update_halign",
  547. mode_info->roi_caps.align.height_pix_align);
  548. sde_kms_info_add_keyint(info, "partial_update_hmin",
  549. mode_info->roi_caps.align.min_height);
  550. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  551. mode_info->roi_caps.merge_rois);
  552. }
  553. fmt = dsi_display->config.common_config.dst_format;
  554. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  555. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  556. end:
  557. return 0;
  558. }
  559. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  560. bool force,
  561. void *display)
  562. {
  563. enum drm_connector_status status = connector_status_unknown;
  564. struct msm_display_info info;
  565. int rc;
  566. if (!conn || !display)
  567. return status;
  568. /* get display dsi_info */
  569. memset(&info, 0x0, sizeof(info));
  570. rc = dsi_display_get_info(conn, &info, display);
  571. if (rc) {
  572. DSI_ERR("failed to get display info, rc=%d\n", rc);
  573. return connector_status_disconnected;
  574. }
  575. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  576. status = (info.is_connected ? connector_status_connected :
  577. connector_status_disconnected);
  578. else
  579. status = connector_status_connected;
  580. conn->display_info.width_mm = info.width_mm;
  581. conn->display_info.height_mm = info.height_mm;
  582. return status;
  583. }
  584. void dsi_connector_put_modes(struct drm_connector *connector,
  585. void *display)
  586. {
  587. struct drm_display_mode *drm_mode;
  588. struct dsi_display_mode dsi_mode;
  589. struct dsi_display *dsi_display;
  590. if (!connector || !display)
  591. return;
  592. list_for_each_entry(drm_mode, &connector->modes, head) {
  593. convert_to_dsi_mode(drm_mode, &dsi_mode);
  594. dsi_display_put_mode(display, &dsi_mode);
  595. }
  596. /* free the display structure modes also */
  597. dsi_display = display;
  598. kfree(dsi_display->modes);
  599. dsi_display->modes = NULL;
  600. }
  601. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  602. {
  603. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  604. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  605. u32 dtd_size = 18;
  606. u32 header_size = sizeof(standard_header);
  607. if (!name)
  608. return -EINVAL;
  609. /* Fill standard header */
  610. memcpy(dtd, standard_header, header_size);
  611. dtd_size -= header_size;
  612. dtd_size = min_t(u32, dtd_size, strlen(name));
  613. memcpy(dtd + header_size, name, dtd_size);
  614. return 0;
  615. }
  616. static void dsi_drm_update_dtd(struct edid *edid,
  617. struct dsi_display_mode *modes, u32 modes_count)
  618. {
  619. u32 i;
  620. u32 count = min_t(u32, modes_count, 3);
  621. for (i = 0; i < count; i++) {
  622. struct detailed_timing *dtd = &edid->detailed_timings[i];
  623. struct dsi_display_mode *mode = &modes[i];
  624. struct dsi_mode_info *timing = &mode->timing;
  625. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  626. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  627. timing->h_back_porch;
  628. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  629. timing->v_back_porch;
  630. u32 h_img = 0, v_img = 0;
  631. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  632. pd->hactive_lo = timing->h_active & 0xFF;
  633. pd->hblank_lo = h_blank & 0xFF;
  634. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  635. ((timing->h_active >> 8) & 0xF) << 4;
  636. pd->vactive_lo = timing->v_active & 0xFF;
  637. pd->vblank_lo = v_blank & 0xFF;
  638. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  639. ((timing->v_active >> 8) & 0xF) << 4;
  640. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  641. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  642. pd->vsync_offset_pulse_width_lo =
  643. ((timing->v_front_porch & 0xF) << 4) |
  644. (timing->v_sync_width & 0xF);
  645. pd->hsync_vsync_offset_pulse_width_hi =
  646. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  647. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  648. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  649. (((timing->v_sync_width >> 4) & 0x3) << 0);
  650. pd->width_mm_lo = h_img & 0xFF;
  651. pd->height_mm_lo = v_img & 0xFF;
  652. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  653. ((v_img >> 8) & 0xF);
  654. pd->hborder = 0;
  655. pd->vborder = 0;
  656. pd->misc = 0;
  657. }
  658. }
  659. static void dsi_drm_update_checksum(struct edid *edid)
  660. {
  661. u8 *data = (u8 *)edid;
  662. u32 i, sum = 0;
  663. for (i = 0; i < EDID_LENGTH - 1; i++)
  664. sum += data[i];
  665. edid->checksum = 0x100 - (sum & 0xFF);
  666. }
  667. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  668. const struct msm_resource_caps_info *avail_res)
  669. {
  670. int rc, i;
  671. u32 count = 0, edid_size;
  672. struct dsi_display_mode *modes = NULL;
  673. struct drm_display_mode drm_mode;
  674. struct dsi_display *display = data;
  675. struct edid edid;
  676. u8 width_mm = connector->display_info.width_mm;
  677. u8 height_mm = connector->display_info.height_mm;
  678. const u8 edid_buf[EDID_LENGTH] = {
  679. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  680. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  681. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  682. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  683. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  684. 0x01, 0x01, 0x01, 0x01,
  685. };
  686. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  687. memcpy(&edid, edid_buf, edid_size);
  688. rc = dsi_display_get_mode_count(display, &count);
  689. if (rc) {
  690. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  691. goto end;
  692. }
  693. rc = dsi_display_get_modes(display, &modes);
  694. if (rc) {
  695. DSI_ERR("failed to get modes, rc=%d\n", rc);
  696. count = 0;
  697. goto end;
  698. }
  699. for (i = 0; i < count; i++) {
  700. struct drm_display_mode *m;
  701. memset(&drm_mode, 0x0, sizeof(drm_mode));
  702. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  703. m = drm_mode_duplicate(connector->dev, &drm_mode);
  704. if (!m) {
  705. DSI_ERR("failed to add mode %ux%u\n",
  706. drm_mode.hdisplay,
  707. drm_mode.vdisplay);
  708. count = -ENOMEM;
  709. goto end;
  710. }
  711. m->width_mm = connector->display_info.width_mm;
  712. m->height_mm = connector->display_info.height_mm;
  713. /* set the first mode in list as preferred */
  714. if (i == 0)
  715. m->type |= DRM_MODE_TYPE_PREFERRED;
  716. drm_mode_probed_add(connector, m);
  717. }
  718. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  719. if (rc) {
  720. count = 0;
  721. goto end;
  722. }
  723. edid.width_cm = (connector->display_info.width_mm) / 10;
  724. edid.height_cm = (connector->display_info.height_mm) / 10;
  725. dsi_drm_update_dtd(&edid, modes, count);
  726. dsi_drm_update_checksum(&edid);
  727. rc = drm_connector_update_edid_property(connector, &edid);
  728. if (rc)
  729. count = 0;
  730. /*
  731. * DRM EDID structure maintains panel physical dimensions in
  732. * centimeters, we will be losing the precision anything below cm.
  733. * Changing DRM framework will effect other clients at this
  734. * moment, overriding the values back to millimeter.
  735. */
  736. connector->display_info.width_mm = width_mm;
  737. connector->display_info.height_mm = height_mm;
  738. end:
  739. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  740. return count;
  741. }
  742. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  743. struct drm_display_mode *mode,
  744. void *display, const struct msm_resource_caps_info *avail_res)
  745. {
  746. struct dsi_display_mode dsi_mode;
  747. int rc;
  748. if (!connector || !mode) {
  749. DSI_ERR("Invalid params\n");
  750. return MODE_ERROR;
  751. }
  752. convert_to_dsi_mode(mode, &dsi_mode);
  753. rc = dsi_display_validate_mode(display, &dsi_mode,
  754. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  755. if (rc) {
  756. DSI_ERR("mode not supported, rc=%d\n", rc);
  757. return MODE_BAD;
  758. }
  759. return MODE_OK;
  760. }
  761. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  762. void *display,
  763. struct msm_display_kickoff_params *params)
  764. {
  765. if (!connector || !display || !params) {
  766. DSI_ERR("Invalid params\n");
  767. return -EINVAL;
  768. }
  769. return dsi_display_pre_kickoff(connector, display, params);
  770. }
  771. void dsi_conn_enable_event(struct drm_connector *connector,
  772. uint32_t event_idx, bool enable, void *display)
  773. {
  774. struct dsi_event_cb_info event_info;
  775. memset(&event_info, 0, sizeof(event_info));
  776. event_info.event_cb = sde_connector_trigger_event;
  777. event_info.event_usr_ptr = connector;
  778. dsi_display_enable_event(connector, display,
  779. event_idx, &event_info, enable);
  780. }
  781. int dsi_conn_post_kickoff(struct drm_connector *connector)
  782. {
  783. struct drm_encoder *encoder;
  784. struct dsi_bridge *c_bridge;
  785. struct dsi_display_mode adj_mode;
  786. struct dsi_display *display;
  787. struct dsi_display_ctrl *m_ctrl, *ctrl;
  788. int i, rc = 0;
  789. if (!connector || !connector->state) {
  790. DSI_ERR("invalid connector or connector state\n");
  791. return -EINVAL;
  792. }
  793. encoder = connector->state->best_encoder;
  794. if (!encoder) {
  795. DSI_DEBUG("best encoder is not available\n");
  796. return 0;
  797. }
  798. c_bridge = to_dsi_bridge(encoder->bridge);
  799. adj_mode = c_bridge->dsi_mode;
  800. display = c_bridge->display;
  801. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  802. m_ctrl = &display->ctrl[display->clk_master_idx];
  803. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  804. if (rc) {
  805. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  806. display->name, rc);
  807. return -EINVAL;
  808. }
  809. /* Update the rest of the controllers */
  810. display_for_each_ctrl(i, display) {
  811. ctrl = &display->ctrl[i];
  812. if (!ctrl->ctrl || (ctrl == m_ctrl))
  813. continue;
  814. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  815. if (rc) {
  816. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  817. display->name, rc);
  818. return -EINVAL;
  819. }
  820. }
  821. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  822. }
  823. /* ensure dynamic clk switch flag is reset */
  824. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  825. return 0;
  826. }
  827. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  828. struct drm_device *dev,
  829. struct drm_encoder *encoder)
  830. {
  831. int rc = 0;
  832. struct dsi_bridge *bridge;
  833. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  834. if (!bridge) {
  835. rc = -ENOMEM;
  836. goto error;
  837. }
  838. bridge->display = display;
  839. bridge->base.funcs = &dsi_bridge_ops;
  840. bridge->base.encoder = encoder;
  841. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  842. if (rc) {
  843. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  844. goto error_free_bridge;
  845. }
  846. encoder->bridge = &bridge->base;
  847. return bridge;
  848. error_free_bridge:
  849. kfree(bridge);
  850. error:
  851. return ERR_PTR(rc);
  852. }
  853. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  854. {
  855. if (bridge && bridge->base.encoder)
  856. bridge->base.encoder->bridge = NULL;
  857. kfree(bridge);
  858. }