dp_power.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/pm_runtime.h>
  8. #include "dp_power.h"
  9. #include "dp_catalog.h"
  10. #include "dp_debug.h"
  11. #include "dp_pll.h"
  12. #define DP_CLIENT_NAME_SIZE 20
  13. #define XO_CLK_KHZ 19200
  14. struct dp_power_private {
  15. struct dp_parser *parser;
  16. struct dp_pll *pll;
  17. struct platform_device *pdev;
  18. struct clk *pixel_clk_rcg;
  19. struct clk *pixel_parent;
  20. struct clk *pixel1_clk_rcg;
  21. struct clk *xo_clk;
  22. struct clk *link_clk_rcg;
  23. struct clk *link_parent;
  24. struct dp_power dp_power;
  25. bool core_clks_on;
  26. bool link_clks_on;
  27. bool strm0_clks_on;
  28. bool strm1_clks_on;
  29. bool strm0_clks_parked;
  30. bool strm1_clks_parked;
  31. };
  32. static int dp_power_regulator_init(struct dp_power_private *power)
  33. {
  34. int rc = 0, i = 0, j = 0;
  35. struct platform_device *pdev;
  36. struct dp_parser *parser;
  37. parser = power->parser;
  38. pdev = power->pdev;
  39. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  40. rc = msm_dss_get_vreg(&pdev->dev,
  41. parser->mp[i].vreg_config,
  42. parser->mp[i].num_vreg, 1);
  43. if (rc) {
  44. DP_ERR("failed to init vregs for %s\n",
  45. dp_parser_pm_name(i));
  46. for (j = i - 1; j >= DP_CORE_PM; j--) {
  47. msm_dss_get_vreg(&pdev->dev,
  48. parser->mp[j].vreg_config,
  49. parser->mp[j].num_vreg, 0);
  50. }
  51. goto error;
  52. }
  53. }
  54. error:
  55. return rc;
  56. }
  57. static void dp_power_regulator_deinit(struct dp_power_private *power)
  58. {
  59. int rc = 0, i = 0;
  60. struct platform_device *pdev;
  61. struct dp_parser *parser;
  62. parser = power->parser;
  63. pdev = power->pdev;
  64. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  65. rc = msm_dss_get_vreg(&pdev->dev,
  66. parser->mp[i].vreg_config,
  67. parser->mp[i].num_vreg, 0);
  68. if (rc)
  69. DP_ERR("failed to deinit vregs for %s\n",
  70. dp_parser_pm_name(i));
  71. }
  72. }
  73. static void dp_power_phy_gdsc(struct dp_power *dp_power, bool on)
  74. {
  75. int rc = 0;
  76. if (IS_ERR_OR_NULL(dp_power->dp_phy_gdsc))
  77. return;
  78. if (on)
  79. rc = regulator_enable(dp_power->dp_phy_gdsc);
  80. else
  81. rc = regulator_disable(dp_power->dp_phy_gdsc);
  82. if (rc)
  83. DP_ERR("Fail to %s dp_phy_gdsc regulator ret =%d\n",
  84. on ? "enable" : "disable", rc);
  85. }
  86. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  87. {
  88. int rc = 0, i = 0, j = 0;
  89. struct dp_parser *parser;
  90. parser = power->parser;
  91. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  92. /*
  93. * The DP_PLL_PM regulator is controlled by dp_display based
  94. * on the link configuration.
  95. */
  96. if (i == DP_PLL_PM) {
  97. /* DP GDSC vote is needed for new chipsets, define gdsc phandle if needed */
  98. dp_power_phy_gdsc(&power->dp_power, enable);
  99. DP_DEBUG("skipping: '%s' vregs for %s\n",
  100. enable ? "enable" : "disable",
  101. dp_parser_pm_name(i));
  102. continue;
  103. }
  104. rc = msm_dss_enable_vreg(
  105. parser->mp[i].vreg_config,
  106. parser->mp[i].num_vreg, enable);
  107. if (rc) {
  108. DP_ERR("failed to '%s' vregs for %s\n",
  109. enable ? "enable" : "disable",
  110. dp_parser_pm_name(i));
  111. if (enable) {
  112. for (j = i-1; j >= DP_CORE_PM; j--) {
  113. msm_dss_enable_vreg(
  114. parser->mp[j].vreg_config,
  115. parser->mp[j].num_vreg, 0);
  116. }
  117. }
  118. goto error;
  119. }
  120. }
  121. error:
  122. return rc;
  123. }
  124. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  125. {
  126. int rc = -EFAULT;
  127. struct pinctrl_state *pin_state;
  128. struct dp_parser *parser;
  129. parser = power->parser;
  130. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  131. return 0;
  132. pin_state = active ? parser->pinctrl.state_active
  133. : parser->pinctrl.state_suspend;
  134. if (!IS_ERR_OR_NULL(pin_state)) {
  135. rc = pinctrl_select_state(parser->pinctrl.pin,
  136. pin_state);
  137. if (rc)
  138. DP_ERR("can not set %s pins\n",
  139. active ? "dp_active"
  140. : "dp_sleep");
  141. } else {
  142. DP_ERR("invalid '%s' pinstate\n",
  143. active ? "dp_active"
  144. : "dp_sleep");
  145. }
  146. return rc;
  147. }
  148. static void dp_power_clk_put(struct dp_power_private *power)
  149. {
  150. enum dp_pm_type module;
  151. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  152. struct dss_module_power *pm = &power->parser->mp[module];
  153. if (!pm->num_clk)
  154. continue;
  155. msm_dss_mmrm_deregister(&power->pdev->dev, pm);
  156. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  157. }
  158. }
  159. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  160. {
  161. int rc = 0;
  162. struct device *dev;
  163. enum dp_pm_type module;
  164. dev = &power->pdev->dev;
  165. if (enable) {
  166. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  167. struct dss_module_power *pm =
  168. &power->parser->mp[module];
  169. if (!pm->num_clk)
  170. continue;
  171. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  172. if (rc) {
  173. DP_ERR("failed to get %s clk. err=%d\n",
  174. dp_parser_pm_name(module), rc);
  175. goto exit;
  176. }
  177. }
  178. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  179. if (IS_ERR(power->pixel_clk_rcg)) {
  180. DP_ERR("Unable to get DP pixel clk RCG: %ld\n",
  181. PTR_ERR(power->pixel_clk_rcg));
  182. rc = PTR_ERR(power->pixel_clk_rcg);
  183. power->pixel_clk_rcg = NULL;
  184. goto err_pixel_clk_rcg;
  185. }
  186. power->pixel_parent = clk_get(dev, "pixel_parent");
  187. if (IS_ERR(power->pixel_parent)) {
  188. DP_ERR("Unable to get DP pixel RCG parent: %d\n",
  189. PTR_ERR(power->pixel_parent));
  190. rc = PTR_ERR(power->pixel_parent);
  191. power->pixel_parent = NULL;
  192. goto err_pixel_parent;
  193. }
  194. power->xo_clk = clk_get(dev, "rpmh_cxo_clk");
  195. if (IS_ERR(power->xo_clk)) {
  196. DP_ERR("Unable to get XO clk: %d\n", PTR_ERR(power->xo_clk));
  197. rc = PTR_ERR(power->xo_clk);
  198. power->xo_clk = NULL;
  199. goto err_xo_clk;
  200. }
  201. if (power->parser->has_mst) {
  202. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  203. if (IS_ERR(power->pixel1_clk_rcg)) {
  204. DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",
  205. PTR_ERR(power->pixel1_clk_rcg));
  206. rc = PTR_ERR(power->pixel1_clk_rcg);
  207. power->pixel1_clk_rcg = NULL;
  208. goto err_pixel1_clk_rcg;
  209. }
  210. }
  211. power->link_clk_rcg = clk_get(dev, "link_clk_src");
  212. if (IS_ERR(power->link_clk_rcg)) {
  213. DP_ERR("Unable to get DP link clk RCG: %ld\n",
  214. PTR_ERR(power->link_clk_rcg));
  215. rc = PTR_ERR(power->link_clk_rcg);
  216. power->link_clk_rcg = NULL;
  217. goto err_link_clk_rcg;
  218. }
  219. /* If link_parent node is available, convert clk rates to HZ for byte2 ops */
  220. power->pll->clk_factor = 1000;
  221. power->link_parent = clk_get(dev, "link_parent");
  222. if (IS_ERR(power->link_parent)) {
  223. DP_WARN("Unable to get DP link parent: %ld\n",
  224. PTR_ERR(power->link_parent));
  225. power->link_parent = NULL;
  226. power->pll->clk_factor = 1;
  227. }
  228. } else {
  229. if (power->pixel1_clk_rcg)
  230. clk_put(power->pixel1_clk_rcg);
  231. if (power->pixel_parent)
  232. clk_put(power->pixel_parent);
  233. if (power->pixel_clk_rcg)
  234. clk_put(power->pixel_clk_rcg);
  235. if (power->link_parent)
  236. clk_put(power->link_parent);
  237. if (power->link_clk_rcg)
  238. clk_put(power->link_clk_rcg);
  239. dp_power_clk_put(power);
  240. }
  241. return rc;
  242. err_link_clk_rcg:
  243. if (power->pixel1_clk_rcg)
  244. clk_put(power->pixel1_clk_rcg);
  245. err_pixel1_clk_rcg:
  246. clk_put(power->xo_clk);
  247. err_xo_clk:
  248. clk_put(power->pixel_parent);
  249. err_pixel_parent:
  250. clk_put(power->pixel_clk_rcg);
  251. err_pixel_clk_rcg:
  252. dp_power_clk_put(power);
  253. exit:
  254. return rc;
  255. }
  256. static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type module)
  257. {
  258. struct dss_module_power *mp;
  259. struct clk *clk = NULL;
  260. int rc = 0;
  261. bool *parked;
  262. mp = &power->parser->mp[module];
  263. if (module == DP_STREAM0_PM) {
  264. clk = power->pixel_clk_rcg;
  265. parked = &power->strm0_clks_parked;
  266. } else if (module == DP_STREAM1_PM) {
  267. clk = power->pixel1_clk_rcg;
  268. parked = &power->strm1_clks_parked;
  269. } else {
  270. goto exit;
  271. }
  272. if (!clk) {
  273. DP_WARN("clk type %d not supported\n", module);
  274. rc = -EINVAL;
  275. goto exit;
  276. }
  277. if (!power->xo_clk) {
  278. rc = -EINVAL;
  279. goto exit;
  280. }
  281. if (*parked)
  282. goto exit;
  283. rc = clk_set_parent(clk, power->xo_clk);
  284. if (rc) {
  285. DP_ERR("unable to set xo parent on clk %d\n", module);
  286. goto exit;
  287. }
  288. mp->clk_config->rate = XO_CLK_KHZ;
  289. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  290. if (rc) {
  291. DP_ERR("failed to set clk rate.\n");
  292. goto exit;
  293. }
  294. *parked = true;
  295. exit:
  296. return rc;
  297. }
  298. static int dp_power_clk_set_rate(struct dp_power_private *power,
  299. enum dp_pm_type module, bool enable)
  300. {
  301. int rc = 0;
  302. struct dss_module_power *mp;
  303. if (!power) {
  304. DP_ERR("invalid power data\n");
  305. rc = -EINVAL;
  306. goto exit;
  307. }
  308. mp = &power->parser->mp[module];
  309. if (enable) {
  310. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  311. if (rc) {
  312. DP_ERR("failed to set clks rate.\n");
  313. goto exit;
  314. }
  315. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  316. if (rc) {
  317. DP_ERR("failed to enable clks\n");
  318. goto exit;
  319. }
  320. } else {
  321. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  322. if (rc) {
  323. DP_ERR("failed to disable clks\n");
  324. goto exit;
  325. }
  326. dp_power_park_module(power, module);
  327. }
  328. exit:
  329. return rc;
  330. }
  331. static bool dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
  332. {
  333. struct dp_power_private *power;
  334. if (!dp_power) {
  335. DP_ERR("invalid power data\n");
  336. return false;
  337. }
  338. power = container_of(dp_power, struct dp_power_private, dp_power);
  339. if (pm_type == DP_LINK_PM)
  340. return power->link_clks_on;
  341. else if (pm_type == DP_CORE_PM)
  342. return power->core_clks_on;
  343. else if (pm_type == DP_STREAM0_PM)
  344. return power->strm0_clks_on;
  345. else if (pm_type == DP_STREAM1_PM)
  346. return power->strm1_clks_on;
  347. else
  348. return false;
  349. }
  350. static int dp_power_clk_enable(struct dp_power *dp_power,
  351. enum dp_pm_type pm_type, bool enable)
  352. {
  353. int rc = 0;
  354. struct dss_module_power *mp;
  355. struct dp_power_private *power;
  356. if (!dp_power) {
  357. DP_ERR("invalid power data\n");
  358. rc = -EINVAL;
  359. goto error;
  360. }
  361. power = container_of(dp_power, struct dp_power_private, dp_power);
  362. mp = &power->parser->mp[pm_type];
  363. if (pm_type >= DP_MAX_PM) {
  364. DP_ERR("unsupported power module: %s\n",
  365. dp_parser_pm_name(pm_type));
  366. return -EINVAL;
  367. }
  368. if (enable) {
  369. if (dp_power_clk_status(dp_power, pm_type)) {
  370. DP_DEBUG("%s clks already enabled\n", dp_parser_pm_name(pm_type));
  371. return 0;
  372. }
  373. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  374. DP_DEBUG("Need to enable core clks before link clks\n");
  375. rc = dp_power_clk_set_rate(power, pm_type, enable);
  376. if (rc) {
  377. DP_ERR("failed to enable clks: %s. err=%d\n",
  378. dp_parser_pm_name(DP_CORE_PM), rc);
  379. goto error;
  380. } else {
  381. power->core_clks_on = true;
  382. }
  383. }
  384. if (pm_type == DP_LINK_PM && power->link_parent) {
  385. rc = clk_set_parent(power->link_clk_rcg, power->link_parent);
  386. if (rc) {
  387. DP_ERR("failed to set link parent\n");
  388. goto error;
  389. }
  390. }
  391. }
  392. rc = dp_power_clk_set_rate(power, pm_type, enable);
  393. if (rc) {
  394. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  395. enable ? "enable" : "disable",
  396. dp_parser_pm_name(pm_type), rc);
  397. goto error;
  398. }
  399. if (pm_type == DP_CORE_PM)
  400. power->core_clks_on = enable;
  401. else if (pm_type == DP_STREAM0_PM)
  402. power->strm0_clks_on = enable;
  403. else if (pm_type == DP_STREAM1_PM)
  404. power->strm1_clks_on = enable;
  405. else if (pm_type == DP_LINK_PM)
  406. power->link_clks_on = enable;
  407. if (pm_type == DP_STREAM0_PM)
  408. power->strm0_clks_parked = false;
  409. if (pm_type == DP_STREAM1_PM)
  410. power->strm1_clks_parked = false;
  411. /*
  412. * This log is printed only when user connects or disconnects
  413. * a DP cable. As this is a user-action and not a frequent
  414. * usecase, it is not going to flood the kernel logs. Also,
  415. * helpful in debugging the NOC issues.
  416. */
  417. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  418. power->core_clks_on ? "on" : "off",
  419. power->link_clks_on ? "on" : "off",
  420. power->strm0_clks_on ? "on" : "off",
  421. power->strm1_clks_on ? "on" : "off");
  422. error:
  423. return rc;
  424. }
  425. static int dp_power_request_gpios(struct dp_power_private *power)
  426. {
  427. int rc = 0, i;
  428. struct device *dev;
  429. struct dss_module_power *mp;
  430. static const char * const gpio_names[] = {
  431. "aux_enable", "aux_sel", "usbplug_cc",
  432. };
  433. if (!power) {
  434. DP_ERR("invalid power data\n");
  435. return -EINVAL;
  436. }
  437. dev = &power->pdev->dev;
  438. mp = &power->parser->mp[DP_CORE_PM];
  439. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  440. unsigned int gpio = mp->gpio_config[i].gpio;
  441. if (gpio_is_valid(gpio)) {
  442. rc = gpio_request(gpio, gpio_names[i]);
  443. if (rc) {
  444. DP_ERR("request %s gpio failed, rc=%d\n",
  445. gpio_names[i], rc);
  446. goto error;
  447. }
  448. }
  449. }
  450. return 0;
  451. error:
  452. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  453. unsigned int gpio = mp->gpio_config[i].gpio;
  454. if (gpio_is_valid(gpio))
  455. gpio_free(gpio);
  456. }
  457. return rc;
  458. }
  459. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  460. {
  461. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  462. }
  463. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  464. {
  465. int i;
  466. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  467. struct dss_gpio *config = mp->gpio_config;
  468. for (i = 0; i < mp->num_gpio; i++) {
  469. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  470. config->value = flip;
  471. if (gpio_is_valid(config->gpio)) {
  472. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  473. config->value);
  474. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  475. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  476. gpio_direction_output(config->gpio,
  477. config->value);
  478. else
  479. gpio_set_value(config->gpio, config->value);
  480. }
  481. config++;
  482. }
  483. }
  484. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  485. bool enable)
  486. {
  487. int rc = 0, i;
  488. struct dss_module_power *mp;
  489. struct dss_gpio *config;
  490. mp = &power->parser->mp[DP_CORE_PM];
  491. config = mp->gpio_config;
  492. if (enable) {
  493. rc = dp_power_request_gpios(power);
  494. if (rc) {
  495. DP_ERR("gpio request failed\n");
  496. return rc;
  497. }
  498. dp_power_set_gpio(power, flip);
  499. } else {
  500. for (i = 0; i < mp->num_gpio; i++) {
  501. if (gpio_is_valid(config[i].gpio)) {
  502. gpio_set_value(config[i].gpio, 0);
  503. gpio_free(config[i].gpio);
  504. }
  505. }
  506. }
  507. return 0;
  508. }
  509. static int dp_power_mmrm_init(struct dp_power *dp_power, struct sde_power_handle *phandle, void *dp,
  510. int (*dp_display_mmrm_callback)(struct mmrm_client_notifier_data *notifier_data))
  511. {
  512. int rc = 0;
  513. enum dp_pm_type module;
  514. struct dp_power_private *power = container_of(dp_power, struct dp_power_private, dp_power);
  515. struct device *dev = &power->pdev->dev;
  516. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  517. struct dss_module_power *pm = &power->parser->mp[module];
  518. if (!pm->num_clk)
  519. continue;
  520. rc = msm_dss_mmrm_register(dev, pm, dp_display_mmrm_callback,
  521. dp, &phandle->mmrm_enable);
  522. if (rc)
  523. DP_ERR("mmrm register failed rc=%d\n", rc);
  524. }
  525. return rc;
  526. }
  527. static int dp_power_client_init(struct dp_power *dp_power,
  528. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  529. {
  530. int rc = 0;
  531. struct dp_power_private *power;
  532. if (!drm_dev) {
  533. DP_ERR("invalid drm_dev\n");
  534. return -EINVAL;
  535. }
  536. power = container_of(dp_power, struct dp_power_private, dp_power);
  537. rc = dp_power_regulator_init(power);
  538. if (rc) {
  539. DP_ERR("failed to init regulators\n");
  540. goto error_power;
  541. }
  542. rc = dp_power_clk_init(power, true);
  543. if (rc) {
  544. DP_ERR("failed to init clocks\n");
  545. goto error_clk;
  546. }
  547. dp_power->phandle = phandle;
  548. dp_power->drm_dev = drm_dev;
  549. return 0;
  550. error_clk:
  551. dp_power_regulator_deinit(power);
  552. error_power:
  553. return rc;
  554. }
  555. static void dp_power_client_deinit(struct dp_power *dp_power)
  556. {
  557. struct dp_power_private *power;
  558. if (!dp_power) {
  559. DP_ERR("invalid power data\n");
  560. return;
  561. }
  562. power = container_of(dp_power, struct dp_power_private, dp_power);
  563. dp_power_clk_init(power, false);
  564. dp_power_regulator_deinit(power);
  565. }
  566. static int dp_power_park_clocks(struct dp_power *dp_power)
  567. {
  568. int rc = 0;
  569. struct dp_power_private *power;
  570. if (!dp_power) {
  571. DP_ERR("invalid power data\n");
  572. return -EINVAL;
  573. }
  574. power = container_of(dp_power, struct dp_power_private, dp_power);
  575. rc = dp_power_park_module(power, DP_STREAM0_PM);
  576. if (rc) {
  577. DP_ERR("failed to park stream 0. err=%d\n", rc);
  578. goto error;
  579. }
  580. rc = dp_power_park_module(power, DP_STREAM1_PM);
  581. if (rc) {
  582. DP_ERR("failed to park stream 1. err=%d\n", rc);
  583. goto error;
  584. }
  585. error:
  586. return rc;
  587. }
  588. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  589. {
  590. int rc = 0;
  591. struct dp_power_private *power;
  592. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  593. DP_ERR("invalid power data. stream %d\n", strm_id);
  594. rc = -EINVAL;
  595. goto exit;
  596. }
  597. power = container_of(dp_power, struct dp_power_private, dp_power);
  598. if (strm_id == DP_STREAM_0) {
  599. if (power->pixel_clk_rcg && power->pixel_parent)
  600. rc = clk_set_parent(power->pixel_clk_rcg,
  601. power->pixel_parent);
  602. else
  603. DP_WARN("skipped for strm_id=%d\n", strm_id);
  604. } else if (strm_id == DP_STREAM_1) {
  605. if (power->pixel1_clk_rcg && power->pixel_parent)
  606. rc = clk_set_parent(power->pixel1_clk_rcg,
  607. power->pixel_parent);
  608. else
  609. DP_WARN("skipped for strm_id=%d\n", strm_id);
  610. }
  611. if (rc)
  612. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  613. exit:
  614. return rc;
  615. }
  616. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  617. {
  618. size_t i;
  619. enum dp_pm_type j;
  620. struct dss_module_power *mp;
  621. struct dp_power_private *power;
  622. bool clk_found = false;
  623. u64 rate = 0;
  624. if (!clk_name) {
  625. DP_ERR("invalid pointer for clk_name\n");
  626. return 0;
  627. }
  628. power = container_of(dp_power, struct dp_power_private, dp_power);
  629. mp = &dp_power->phandle->mp;
  630. for (i = 0; i < mp->num_clk; i++) {
  631. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  632. rate = clk_get_rate(mp->clk_config[i].clk);
  633. clk_found = true;
  634. break;
  635. }
  636. }
  637. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  638. mp = &power->parser->mp[j];
  639. for (i = 0; i < mp->num_clk; i++) {
  640. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  641. rate = clk_get_rate(mp->clk_config[i].clk);
  642. clk_found = true;
  643. break;
  644. }
  645. }
  646. }
  647. return rate;
  648. }
  649. static int dp_power_init(struct dp_power *dp_power, bool flip)
  650. {
  651. int rc = 0;
  652. struct dp_power_private *power;
  653. if (!dp_power) {
  654. DP_ERR("invalid power data\n");
  655. rc = -EINVAL;
  656. goto exit;
  657. }
  658. power = container_of(dp_power, struct dp_power_private, dp_power);
  659. rc = dp_power_regulator_ctrl(power, true);
  660. if (rc) {
  661. DP_ERR("failed to enable regulators\n");
  662. goto exit;
  663. }
  664. rc = dp_power_pinctrl_set(power, true);
  665. if (rc) {
  666. DP_ERR("failed to set pinctrl state\n");
  667. goto err_pinctrl;
  668. }
  669. rc = dp_power_config_gpios(power, flip, true);
  670. if (rc) {
  671. DP_ERR("failed to enable gpios\n");
  672. goto err_gpio;
  673. }
  674. rc = pm_runtime_resume_and_get(dp_power->drm_dev->dev);
  675. if (rc < 0) {
  676. DP_ERR("failed to enable power resource %d\n", rc);
  677. goto err_sde_power;
  678. }
  679. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  680. if (rc) {
  681. DP_ERR("failed to enable DP core clocks\n");
  682. goto err_clk;
  683. }
  684. return 0;
  685. err_clk:
  686. pm_runtime_put_sync(dp_power->drm_dev->dev);
  687. err_sde_power:
  688. dp_power_config_gpios(power, flip, false);
  689. err_gpio:
  690. dp_power_pinctrl_set(power, false);
  691. err_pinctrl:
  692. dp_power_regulator_ctrl(power, false);
  693. exit:
  694. return rc;
  695. }
  696. static int dp_power_deinit(struct dp_power *dp_power)
  697. {
  698. int rc = 0;
  699. struct dp_power_private *power;
  700. if (!dp_power) {
  701. DP_ERR("invalid power data\n");
  702. rc = -EINVAL;
  703. goto exit;
  704. }
  705. power = container_of(dp_power, struct dp_power_private, dp_power);
  706. if (power->link_clks_on)
  707. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  708. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  709. pm_runtime_put_sync(dp_power->drm_dev->dev);
  710. dp_power_config_gpios(power, false, false);
  711. dp_power_pinctrl_set(power, false);
  712. dp_power_regulator_ctrl(power, false);
  713. exit:
  714. return rc;
  715. }
  716. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  717. {
  718. int rc = 0;
  719. struct dp_power_private *power;
  720. struct dp_power *dp_power;
  721. struct device *dev;
  722. if (!parser || !pll) {
  723. DP_ERR("invalid input\n");
  724. rc = -EINVAL;
  725. goto error;
  726. }
  727. power = kzalloc(sizeof(*power), GFP_KERNEL);
  728. if (!power) {
  729. rc = -ENOMEM;
  730. goto error;
  731. }
  732. power->parser = parser;
  733. power->pll = pll;
  734. power->pdev = parser->pdev;
  735. dp_power = &power->dp_power;
  736. dev = &power->pdev->dev;
  737. dp_power->init = dp_power_init;
  738. dp_power->deinit = dp_power_deinit;
  739. dp_power->clk_enable = dp_power_clk_enable;
  740. dp_power->clk_status = dp_power_clk_status;
  741. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  742. dp_power->park_clocks = dp_power_park_clocks;
  743. dp_power->clk_get_rate = dp_power_clk_get_rate;
  744. dp_power->power_client_init = dp_power_client_init;
  745. dp_power->power_client_deinit = dp_power_client_deinit;
  746. dp_power->power_mmrm_init = dp_power_mmrm_init;
  747. dp_power->dp_phy_gdsc = devm_regulator_get(dev, "dp_phy_gdsc");
  748. if (IS_ERR(dp_power->dp_phy_gdsc)) {
  749. dp_power->dp_phy_gdsc = NULL;
  750. DP_DEBUG("Optional GDSC regulator is missing\n");
  751. }
  752. return dp_power;
  753. error:
  754. return ERR_PTR(rc);
  755. }
  756. void dp_power_put(struct dp_power *dp_power)
  757. {
  758. struct dp_power_private *power = NULL;
  759. if (!dp_power)
  760. return;
  761. power = container_of(dp_power, struct dp_power_private, dp_power);
  762. kfree(power);
  763. }