dp_tx.c 170 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. #define DP_RETRY_COUNT 7
  63. #ifdef WLAN_PEER_JITTER
  64. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  65. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  66. #endif
  67. #ifdef QCA_DP_TX_FW_METADATA_V2
  68. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  69. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  80. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  82. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  84. #else
  85. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  86. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  97. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  98. HTT_TCL_METADATA_TYPE_PEER_BASED
  99. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  100. HTT_TCL_METADATA_TYPE_VDEV_BASED
  101. #endif
  102. /*mapping between hal encrypt type and cdp_sec_type*/
  103. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  104. HAL_TX_ENCRYPT_TYPE_WEP_128,
  105. HAL_TX_ENCRYPT_TYPE_WEP_104,
  106. HAL_TX_ENCRYPT_TYPE_WEP_40,
  107. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  108. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  110. HAL_TX_ENCRYPT_TYPE_WAPI,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  113. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  115. qdf_export_symbol(sec_type_map);
  116. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  117. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  118. {
  119. enum dp_tx_event_type type;
  120. if (flags & DP_TX_DESC_FLAG_FLUSH)
  121. type = DP_TX_DESC_FLUSH;
  122. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  123. type = DP_TX_COMP_UNMAP_ERR;
  124. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  125. type = DP_TX_COMP_UNMAP;
  126. else
  127. type = DP_TX_DESC_UNMAP;
  128. return type;
  129. }
  130. static inline void
  131. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  132. qdf_nbuf_t skb, uint32_t sw_cookie,
  133. enum dp_tx_event_type type)
  134. {
  135. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  136. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  137. struct dp_tx_desc_event *entry;
  138. uint32_t idx;
  139. uint16_t slot;
  140. switch (type) {
  141. case DP_TX_COMP_UNMAP:
  142. case DP_TX_COMP_UNMAP_ERR:
  143. case DP_TX_COMP_MSDU_EXT:
  144. if (qdf_unlikely(!tx_comp_history->allocated))
  145. return;
  146. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  147. &slot,
  148. DP_TX_COMP_HIST_SLOT_SHIFT,
  149. DP_TX_COMP_HIST_PER_SLOT_MAX,
  150. DP_TX_COMP_HISTORY_SIZE);
  151. entry = &tx_comp_history->entry[slot][idx];
  152. break;
  153. case DP_TX_DESC_MAP:
  154. case DP_TX_DESC_UNMAP:
  155. case DP_TX_DESC_COOKIE:
  156. case DP_TX_DESC_FLUSH:
  157. if (qdf_unlikely(!tx_tcl_history->allocated))
  158. return;
  159. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  160. &slot,
  161. DP_TX_TCL_HIST_SLOT_SHIFT,
  162. DP_TX_TCL_HIST_PER_SLOT_MAX,
  163. DP_TX_TCL_HISTORY_SIZE);
  164. entry = &tx_tcl_history->entry[slot][idx];
  165. break;
  166. default:
  167. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  168. return;
  169. }
  170. entry->skb = skb;
  171. entry->paddr = paddr;
  172. entry->sw_cookie = sw_cookie;
  173. entry->type = type;
  174. entry->ts = qdf_get_log_timestamp();
  175. }
  176. static inline void
  177. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  178. struct qdf_tso_seg_elem_t *tso_seg,
  179. qdf_nbuf_t skb, uint32_t sw_cookie,
  180. enum dp_tx_event_type type)
  181. {
  182. int i;
  183. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  184. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  185. skb, sw_cookie, type);
  186. }
  187. if (!tso_seg->next)
  188. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  189. skb, 0xFFFFFFFF, type);
  190. }
  191. static inline void
  192. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  193. qdf_nbuf_t skb, uint32_t sw_cookie,
  194. enum dp_tx_event_type type)
  195. {
  196. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  197. uint32_t num_segs = tso_info.num_segs;
  198. while (num_segs) {
  199. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  200. curr_seg = curr_seg->next;
  201. num_segs--;
  202. }
  203. }
  204. #else
  205. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  206. {
  207. return DP_TX_DESC_INVAL_EVT;
  208. }
  209. static inline void
  210. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  211. qdf_nbuf_t skb, uint32_t sw_cookie,
  212. enum dp_tx_event_type type)
  213. {
  214. }
  215. static inline void
  216. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  217. struct qdf_tso_seg_elem_t *tso_seg,
  218. qdf_nbuf_t skb, uint32_t sw_cookie,
  219. enum dp_tx_event_type type)
  220. {
  221. }
  222. static inline void
  223. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  224. qdf_nbuf_t skb, uint32_t sw_cookie,
  225. enum dp_tx_event_type type)
  226. {
  227. }
  228. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  229. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  230. /**
  231. * dp_is_tput_high() - Check if throughput is high
  232. *
  233. * @soc: core txrx main context
  234. *
  235. * The current function is based of the RTPM tput policy variable where RTPM is
  236. * avoided based on throughput.
  237. */
  238. static inline int dp_is_tput_high(struct dp_soc *soc)
  239. {
  240. return dp_get_rtpm_tput_policy_requirement(soc);
  241. }
  242. #if defined(FEATURE_TSO)
  243. /**
  244. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  245. *
  246. * @soc: core txrx main context
  247. * @seg_desc: tso segment descriptor
  248. * @num_seg_desc: tso number segment descriptor
  249. */
  250. static void dp_tx_tso_unmap_segment(
  251. struct dp_soc *soc,
  252. struct qdf_tso_seg_elem_t *seg_desc,
  253. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  254. {
  255. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  256. if (qdf_unlikely(!seg_desc)) {
  257. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  258. __func__, __LINE__);
  259. qdf_assert(0);
  260. } else if (qdf_unlikely(!num_seg_desc)) {
  261. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  262. __func__, __LINE__);
  263. qdf_assert(0);
  264. } else {
  265. bool is_last_seg;
  266. /* no tso segment left to do dma unmap */
  267. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  268. return;
  269. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  270. true : false;
  271. qdf_nbuf_unmap_tso_segment(soc->osdev,
  272. seg_desc, is_last_seg);
  273. num_seg_desc->num_seg.tso_cmn_num_seg--;
  274. }
  275. }
  276. /**
  277. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  278. * back to the freelist
  279. *
  280. * @soc: soc device handle
  281. * @tx_desc: Tx software descriptor
  282. */
  283. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  284. struct dp_tx_desc_s *tx_desc)
  285. {
  286. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  287. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  288. dp_tx_err("SO desc is NULL!");
  289. qdf_assert(0);
  290. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  291. dp_tx_err("TSO num desc is NULL!");
  292. qdf_assert(0);
  293. } else {
  294. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  295. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  296. msdu_ext_desc->tso_num_desc;
  297. /* Add the tso num segment into the free list */
  298. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  299. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  300. tx_desc->msdu_ext_desc->
  301. tso_num_desc);
  302. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  303. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  304. }
  305. /* Add the tso segment into the free list*/
  306. dp_tx_tso_desc_free(soc,
  307. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  308. tso_desc);
  309. tx_desc->msdu_ext_desc->tso_desc = NULL;
  310. }
  311. }
  312. #else
  313. static void dp_tx_tso_unmap_segment(
  314. struct dp_soc *soc,
  315. struct qdf_tso_seg_elem_t *seg_desc,
  316. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  317. {
  318. }
  319. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  320. struct dp_tx_desc_s *tx_desc)
  321. {
  322. }
  323. #endif
  324. void
  325. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  326. {
  327. struct dp_pdev *pdev = tx_desc->pdev;
  328. struct dp_soc *soc;
  329. uint8_t comp_status = 0;
  330. qdf_assert(pdev);
  331. soc = pdev->soc;
  332. dp_tx_outstanding_dec(pdev);
  333. if (tx_desc->msdu_ext_desc) {
  334. if (tx_desc->frm_type == dp_tx_frm_tso)
  335. dp_tx_tso_desc_release(soc, tx_desc);
  336. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  337. dp_tx_me_free_buf(tx_desc->pdev,
  338. tx_desc->msdu_ext_desc->me_buffer);
  339. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  340. }
  341. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  342. qdf_atomic_dec(&soc->num_tx_exception);
  343. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  344. tx_desc->buffer_src)
  345. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  346. soc->hal_soc);
  347. else
  348. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  349. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  350. tx_desc->id, comp_status,
  351. qdf_atomic_read(&pdev->num_tx_outstanding));
  352. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  353. return;
  354. }
  355. /**
  356. * dp_tx_prepare_htt_metadata() - Prepare HTT metadata for special frames
  357. * @vdev: DP vdev Handle
  358. * @nbuf: skb
  359. * @msdu_info: msdu_info required to create HTT metadata
  360. *
  361. * Prepares and fills HTT metadata in the frame pre-header for special frames
  362. * that should be transmitted using varying transmit parameters.
  363. * There are 2 VDEV modes that currently needs this special metadata -
  364. * 1) Mesh Mode
  365. * 2) DSRC Mode
  366. *
  367. * Return: HTT metadata size
  368. *
  369. */
  370. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  371. struct dp_tx_msdu_info_s *msdu_info)
  372. {
  373. uint32_t *meta_data = msdu_info->meta_data;
  374. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  375. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  376. uint8_t htt_desc_size;
  377. /* Size rounded of multiple of 8 bytes */
  378. uint8_t htt_desc_size_aligned;
  379. uint8_t *hdr = NULL;
  380. /*
  381. * Metadata - HTT MSDU Extension header
  382. */
  383. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  384. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  385. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  386. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  387. meta_data[0]) ||
  388. msdu_info->exception_fw) {
  389. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  390. htt_desc_size_aligned)) {
  391. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  392. htt_desc_size_aligned);
  393. if (!nbuf) {
  394. /*
  395. * qdf_nbuf_realloc_headroom won't do skb_clone
  396. * as skb_realloc_headroom does. so, no free is
  397. * needed here.
  398. */
  399. DP_STATS_INC(vdev,
  400. tx_i.dropped.headroom_insufficient,
  401. 1);
  402. qdf_print(" %s[%d] skb_realloc_headroom failed",
  403. __func__, __LINE__);
  404. return 0;
  405. }
  406. }
  407. /* Fill and add HTT metaheader */
  408. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  409. if (!hdr) {
  410. dp_tx_err("Error in filling HTT metadata");
  411. return 0;
  412. }
  413. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  414. } else if (vdev->opmode == wlan_op_mode_ocb) {
  415. /* Todo - Add support for DSRC */
  416. }
  417. return htt_desc_size_aligned;
  418. }
  419. /**
  420. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  421. * @tso_seg: TSO segment to process
  422. * @ext_desc: Pointer to MSDU extension descriptor
  423. *
  424. * Return: void
  425. */
  426. #if defined(FEATURE_TSO)
  427. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  428. void *ext_desc)
  429. {
  430. uint8_t num_frag;
  431. uint32_t tso_flags;
  432. /*
  433. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  434. * tcp_flag_mask
  435. *
  436. * Checksum enable flags are set in TCL descriptor and not in Extension
  437. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  438. */
  439. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  440. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  441. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  442. tso_seg->tso_flags.ip_len);
  443. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  444. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  445. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  446. uint32_t lo = 0;
  447. uint32_t hi = 0;
  448. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  449. (tso_seg->tso_frags[num_frag].length));
  450. qdf_dmaaddr_to_32s(
  451. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  452. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  453. tso_seg->tso_frags[num_frag].length);
  454. }
  455. return;
  456. }
  457. #else
  458. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  459. void *ext_desc)
  460. {
  461. return;
  462. }
  463. #endif
  464. #if defined(FEATURE_TSO)
  465. /**
  466. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  467. * allocated and free them
  468. * @soc: soc handle
  469. * @free_seg: list of tso segments
  470. * @msdu_info: msdu descriptor
  471. *
  472. * Return: void
  473. */
  474. static void dp_tx_free_tso_seg_list(
  475. struct dp_soc *soc,
  476. struct qdf_tso_seg_elem_t *free_seg,
  477. struct dp_tx_msdu_info_s *msdu_info)
  478. {
  479. struct qdf_tso_seg_elem_t *next_seg;
  480. while (free_seg) {
  481. next_seg = free_seg->next;
  482. dp_tx_tso_desc_free(soc,
  483. msdu_info->tx_queue.desc_pool_id,
  484. free_seg);
  485. free_seg = next_seg;
  486. }
  487. }
  488. /**
  489. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  490. * allocated and free them
  491. * @soc: soc handle
  492. * @free_num_seg: list of tso number segments
  493. * @msdu_info: msdu descriptor
  494. *
  495. * Return: void
  496. */
  497. static void dp_tx_free_tso_num_seg_list(
  498. struct dp_soc *soc,
  499. struct qdf_tso_num_seg_elem_t *free_num_seg,
  500. struct dp_tx_msdu_info_s *msdu_info)
  501. {
  502. struct qdf_tso_num_seg_elem_t *next_num_seg;
  503. while (free_num_seg) {
  504. next_num_seg = free_num_seg->next;
  505. dp_tso_num_seg_free(soc,
  506. msdu_info->tx_queue.desc_pool_id,
  507. free_num_seg);
  508. free_num_seg = next_num_seg;
  509. }
  510. }
  511. /**
  512. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  513. * do dma unmap for each segment
  514. * @soc: soc handle
  515. * @free_seg: list of tso segments
  516. * @num_seg_desc: tso number segment descriptor
  517. *
  518. * Return: void
  519. */
  520. static void dp_tx_unmap_tso_seg_list(
  521. struct dp_soc *soc,
  522. struct qdf_tso_seg_elem_t *free_seg,
  523. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  524. {
  525. struct qdf_tso_seg_elem_t *next_seg;
  526. if (qdf_unlikely(!num_seg_desc)) {
  527. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  528. return;
  529. }
  530. while (free_seg) {
  531. next_seg = free_seg->next;
  532. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  533. free_seg = next_seg;
  534. }
  535. }
  536. #ifdef FEATURE_TSO_STATS
  537. /**
  538. * dp_tso_get_stats_idx() - Retrieve the tso packet id
  539. * @pdev: pdev handle
  540. *
  541. * Return: id
  542. */
  543. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  544. {
  545. uint32_t stats_idx;
  546. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  547. % CDP_MAX_TSO_PACKETS);
  548. return stats_idx;
  549. }
  550. #else
  551. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  552. {
  553. return 0;
  554. }
  555. #endif /* FEATURE_TSO_STATS */
  556. /**
  557. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  558. * free the tso segments descriptor and
  559. * tso num segments descriptor
  560. * @soc: soc handle
  561. * @msdu_info: msdu descriptor
  562. * @tso_seg_unmap: flag to show if dma unmap is necessary
  563. *
  564. * Return: void
  565. */
  566. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  567. struct dp_tx_msdu_info_s *msdu_info,
  568. bool tso_seg_unmap)
  569. {
  570. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  571. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  572. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  573. tso_info->tso_num_seg_list;
  574. /* do dma unmap for each segment */
  575. if (tso_seg_unmap)
  576. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  577. /* free all tso number segment descriptor though looks only have 1 */
  578. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  579. /* free all tso segment descriptor */
  580. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  581. }
  582. /**
  583. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  584. * @vdev: virtual device handle
  585. * @msdu: network buffer
  586. * @msdu_info: meta data associated with the msdu
  587. *
  588. * Return: QDF_STATUS_SUCCESS success
  589. */
  590. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  591. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  592. {
  593. struct qdf_tso_seg_elem_t *tso_seg;
  594. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  595. struct dp_soc *soc = vdev->pdev->soc;
  596. struct dp_pdev *pdev = vdev->pdev;
  597. struct qdf_tso_info_t *tso_info;
  598. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  599. tso_info = &msdu_info->u.tso_info;
  600. tso_info->curr_seg = NULL;
  601. tso_info->tso_seg_list = NULL;
  602. tso_info->num_segs = num_seg;
  603. msdu_info->frm_type = dp_tx_frm_tso;
  604. tso_info->tso_num_seg_list = NULL;
  605. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  606. while (num_seg) {
  607. tso_seg = dp_tx_tso_desc_alloc(
  608. soc, msdu_info->tx_queue.desc_pool_id);
  609. if (tso_seg) {
  610. tso_seg->next = tso_info->tso_seg_list;
  611. tso_info->tso_seg_list = tso_seg;
  612. num_seg--;
  613. } else {
  614. dp_err_rl("Failed to alloc tso seg desc");
  615. DP_STATS_INC_PKT(vdev->pdev,
  616. tso_stats.tso_no_mem_dropped, 1,
  617. qdf_nbuf_len(msdu));
  618. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  619. return QDF_STATUS_E_NOMEM;
  620. }
  621. }
  622. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  623. tso_num_seg = dp_tso_num_seg_alloc(soc,
  624. msdu_info->tx_queue.desc_pool_id);
  625. if (tso_num_seg) {
  626. tso_num_seg->next = tso_info->tso_num_seg_list;
  627. tso_info->tso_num_seg_list = tso_num_seg;
  628. } else {
  629. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  630. __func__);
  631. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  632. return QDF_STATUS_E_NOMEM;
  633. }
  634. msdu_info->num_seg =
  635. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  636. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  637. msdu_info->num_seg);
  638. if (!(msdu_info->num_seg)) {
  639. /*
  640. * Free allocated TSO seg desc and number seg desc,
  641. * do unmap for segments if dma map has done.
  642. */
  643. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  644. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  645. return QDF_STATUS_E_INVAL;
  646. }
  647. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  648. msdu, 0, DP_TX_DESC_MAP);
  649. tso_info->curr_seg = tso_info->tso_seg_list;
  650. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  651. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  652. msdu, msdu_info->num_seg);
  653. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  654. tso_info->msdu_stats_idx);
  655. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  656. return QDF_STATUS_SUCCESS;
  657. }
  658. #else
  659. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  660. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  661. {
  662. return QDF_STATUS_E_NOMEM;
  663. }
  664. #endif
  665. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  666. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  667. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  668. /**
  669. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  670. * @vdev: DP Vdev handle
  671. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  672. * @desc_pool_id: Descriptor Pool ID
  673. *
  674. * Return:
  675. */
  676. static
  677. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  678. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  679. {
  680. uint8_t i;
  681. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  682. struct dp_tx_seg_info_s *seg_info;
  683. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  684. struct dp_soc *soc = vdev->pdev->soc;
  685. /* Allocate an extension descriptor */
  686. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  687. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  688. if (!msdu_ext_desc) {
  689. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  690. return NULL;
  691. }
  692. if (msdu_info->exception_fw &&
  693. qdf_unlikely(vdev->mesh_vdev)) {
  694. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  695. &msdu_info->meta_data[0],
  696. sizeof(struct htt_tx_msdu_desc_ext2_t));
  697. qdf_atomic_inc(&soc->num_tx_exception);
  698. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  699. }
  700. switch (msdu_info->frm_type) {
  701. case dp_tx_frm_sg:
  702. case dp_tx_frm_me:
  703. case dp_tx_frm_raw:
  704. seg_info = msdu_info->u.sg_info.curr_seg;
  705. /* Update the buffer pointers in MSDU Extension Descriptor */
  706. for (i = 0; i < seg_info->frag_cnt; i++) {
  707. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  708. seg_info->frags[i].paddr_lo,
  709. seg_info->frags[i].paddr_hi,
  710. seg_info->frags[i].len);
  711. }
  712. break;
  713. case dp_tx_frm_tso:
  714. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  715. &cached_ext_desc[0]);
  716. break;
  717. default:
  718. break;
  719. }
  720. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  721. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  722. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  723. msdu_ext_desc->vaddr);
  724. return msdu_ext_desc;
  725. }
  726. /**
  727. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  728. * @soc: datapath SOC
  729. * @skb: skb to be traced
  730. * @msdu_id: msdu_id of the packet
  731. * @vdev_id: vdev_id of the packet
  732. *
  733. * Return: None
  734. */
  735. #ifdef DP_DISABLE_TX_PKT_TRACE
  736. static void dp_tx_trace_pkt(struct dp_soc *soc,
  737. qdf_nbuf_t skb, uint16_t msdu_id,
  738. uint8_t vdev_id)
  739. {
  740. }
  741. #else
  742. static void dp_tx_trace_pkt(struct dp_soc *soc,
  743. qdf_nbuf_t skb, uint16_t msdu_id,
  744. uint8_t vdev_id)
  745. {
  746. if (dp_is_tput_high(soc))
  747. return;
  748. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  749. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  750. DPTRACE(qdf_dp_trace_ptr(skb,
  751. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  752. QDF_TRACE_DEFAULT_PDEV_ID,
  753. qdf_nbuf_data_addr(skb),
  754. sizeof(qdf_nbuf_data(skb)),
  755. msdu_id, vdev_id, 0));
  756. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  757. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  758. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  759. msdu_id, QDF_TX));
  760. }
  761. #endif
  762. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  763. /**
  764. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  765. * exception by the upper layer (OS_IF)
  766. * @soc: DP soc handle
  767. * @nbuf: packet to be transmitted
  768. *
  769. * Return: 1 if the packet is marked as exception,
  770. * 0, if the packet is not marked as exception.
  771. */
  772. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  773. qdf_nbuf_t nbuf)
  774. {
  775. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  776. }
  777. #else
  778. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  779. qdf_nbuf_t nbuf)
  780. {
  781. return 0;
  782. }
  783. #endif
  784. #ifdef DP_TRAFFIC_END_INDICATION
  785. /**
  786. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  787. * as indication to fw to inform that
  788. * data stream has ended
  789. * @vdev: DP vdev handle
  790. * @nbuf: original buffer from network stack
  791. *
  792. * Return: NULL on failure,
  793. * nbuf on success
  794. */
  795. static inline qdf_nbuf_t
  796. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  797. qdf_nbuf_t nbuf)
  798. {
  799. /* Packet length should be enough to copy upto L3 header */
  800. uint8_t end_nbuf_len = 64;
  801. uint8_t htt_desc_size_aligned;
  802. uint8_t htt_desc_size;
  803. qdf_nbuf_t end_nbuf;
  804. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  805. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  806. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  807. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  808. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  809. if (!end_nbuf) {
  810. end_nbuf = qdf_nbuf_alloc(NULL,
  811. (htt_desc_size_aligned +
  812. end_nbuf_len),
  813. htt_desc_size_aligned,
  814. 8, false);
  815. if (!end_nbuf) {
  816. dp_err("Packet allocation failed");
  817. goto out;
  818. }
  819. } else {
  820. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  821. }
  822. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  823. end_nbuf_len);
  824. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  825. return end_nbuf;
  826. }
  827. out:
  828. return NULL;
  829. }
  830. /**
  831. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  832. * via exception path.
  833. * @vdev: DP vdev handle
  834. * @end_nbuf: skb to send as indication
  835. * @msdu_info: msdu_info of original nbuf
  836. * @peer_id: peer id
  837. *
  838. * Return: None
  839. */
  840. static inline void
  841. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  842. qdf_nbuf_t end_nbuf,
  843. struct dp_tx_msdu_info_s *msdu_info,
  844. uint16_t peer_id)
  845. {
  846. struct dp_tx_msdu_info_s e_msdu_info = {0};
  847. qdf_nbuf_t nbuf;
  848. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  849. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  850. e_msdu_info.tx_queue = msdu_info->tx_queue;
  851. e_msdu_info.tid = msdu_info->tid;
  852. e_msdu_info.exception_fw = 1;
  853. desc_ext->host_tx_desc_pool = 1;
  854. desc_ext->traffic_end_indication = 1;
  855. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  856. peer_id, NULL);
  857. if (nbuf) {
  858. dp_err("Traffic end indication packet tx failed");
  859. qdf_nbuf_free(nbuf);
  860. }
  861. }
  862. /**
  863. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  864. * mark it traffic end indication
  865. * packet.
  866. * @tx_desc: Tx descriptor pointer
  867. * @msdu_info: msdu_info structure pointer
  868. *
  869. * Return: None
  870. */
  871. static inline void
  872. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  873. struct dp_tx_msdu_info_s *msdu_info)
  874. {
  875. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  876. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  877. if (qdf_unlikely(desc_ext->traffic_end_indication))
  878. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  879. }
  880. /**
  881. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  882. * freeing which are associated
  883. * with traffic end indication
  884. * flagged descriptor.
  885. * @soc: dp soc handle
  886. * @desc: Tx descriptor pointer
  887. * @nbuf: buffer pointer
  888. *
  889. * Return: True if packet gets enqueued else false
  890. */
  891. static bool
  892. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  893. struct dp_tx_desc_s *desc,
  894. qdf_nbuf_t nbuf)
  895. {
  896. struct dp_vdev *vdev = NULL;
  897. if (qdf_unlikely((desc->flags &
  898. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  899. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  900. DP_MOD_ID_TX_COMP);
  901. if (vdev) {
  902. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  903. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  904. return true;
  905. }
  906. }
  907. return false;
  908. }
  909. /**
  910. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  911. * enable/disable status
  912. * @vdev: dp vdev handle
  913. *
  914. * Return: True if feature is enable else false
  915. */
  916. static inline bool
  917. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  918. {
  919. return qdf_unlikely(vdev->traffic_end_ind_en);
  920. }
  921. static inline qdf_nbuf_t
  922. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  923. struct dp_tx_msdu_info_s *msdu_info,
  924. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  925. {
  926. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  927. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  928. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  929. if (qdf_unlikely(end_nbuf))
  930. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  931. msdu_info, peer_id);
  932. return nbuf;
  933. }
  934. #else
  935. static inline qdf_nbuf_t
  936. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  937. qdf_nbuf_t nbuf)
  938. {
  939. return NULL;
  940. }
  941. static inline void
  942. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  943. qdf_nbuf_t end_nbuf,
  944. struct dp_tx_msdu_info_s *msdu_info,
  945. uint16_t peer_id)
  946. {}
  947. static inline void
  948. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  949. struct dp_tx_msdu_info_s *msdu_info)
  950. {}
  951. static inline bool
  952. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  953. struct dp_tx_desc_s *desc,
  954. qdf_nbuf_t nbuf)
  955. {
  956. return false;
  957. }
  958. static inline bool
  959. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  960. {
  961. return false;
  962. }
  963. static inline qdf_nbuf_t
  964. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  965. struct dp_tx_msdu_info_s *msdu_info,
  966. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  967. {
  968. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  969. }
  970. #endif
  971. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  972. static bool
  973. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  974. struct cdp_tx_exception_metadata *tx_exc_metadata)
  975. {
  976. if (soc->features.wds_ext_ast_override_enable &&
  977. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  978. return true;
  979. return false;
  980. }
  981. #else
  982. static bool
  983. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  984. struct cdp_tx_exception_metadata *tx_exc_metadata)
  985. {
  986. return false;
  987. }
  988. #endif
  989. /**
  990. * dp_tx_prepare_desc_single() - Allocate and prepare Tx descriptor
  991. * @vdev: DP vdev handle
  992. * @nbuf: skb
  993. * @desc_pool_id: Descriptor pool ID
  994. * @msdu_info: Metadata to the fw
  995. * @tx_exc_metadata: Handle that holds exception path metadata
  996. *
  997. * Allocate and prepare Tx descriptor with msdu information.
  998. *
  999. * Return: Pointer to Tx Descriptor on success,
  1000. * NULL on failure
  1001. */
  1002. static
  1003. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1004. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1005. struct dp_tx_msdu_info_s *msdu_info,
  1006. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1007. {
  1008. uint8_t align_pad;
  1009. uint8_t is_exception = 0;
  1010. uint8_t htt_hdr_size;
  1011. struct dp_tx_desc_s *tx_desc;
  1012. struct dp_pdev *pdev = vdev->pdev;
  1013. struct dp_soc *soc = pdev->soc;
  1014. if (dp_tx_limit_check(vdev, nbuf))
  1015. return NULL;
  1016. /* Allocate software Tx descriptor */
  1017. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1018. if (qdf_unlikely(!tx_desc)) {
  1019. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1020. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1021. return NULL;
  1022. }
  1023. dp_tx_outstanding_inc(pdev);
  1024. /* Initialize the SW tx descriptor */
  1025. tx_desc->nbuf = nbuf;
  1026. tx_desc->frm_type = dp_tx_frm_std;
  1027. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1028. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1029. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1030. tx_desc->vdev_id = vdev->vdev_id;
  1031. tx_desc->pdev = pdev;
  1032. tx_desc->msdu_ext_desc = NULL;
  1033. tx_desc->pkt_offset = 0;
  1034. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1035. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1036. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1037. if (qdf_unlikely(vdev->multipass_en)) {
  1038. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1039. goto failure;
  1040. }
  1041. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1042. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1043. is_exception = 1;
  1044. /* for BE chipsets if wds extension was enbled will not mark FW
  1045. * in desc will mark ast index based search for ast index.
  1046. */
  1047. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1048. return tx_desc;
  1049. /*
  1050. * For special modes (vdev_type == ocb or mesh), data frames should be
  1051. * transmitted using varying transmit parameters (tx spec) which include
  1052. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1053. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1054. * These frames are sent as exception packets to firmware.
  1055. *
  1056. * HW requirement is that metadata should always point to a
  1057. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1058. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1059. * to get 8-byte aligned start address along with align_pad added
  1060. *
  1061. * |-----------------------------|
  1062. * | |
  1063. * |-----------------------------| <-----Buffer Pointer Address given
  1064. * | | ^ in HW descriptor (aligned)
  1065. * | HTT Metadata | |
  1066. * | | |
  1067. * | | | Packet Offset given in descriptor
  1068. * | | |
  1069. * |-----------------------------| |
  1070. * | Alignment Pad | v
  1071. * |-----------------------------| <----- Actual buffer start address
  1072. * | SKB Data | (Unaligned)
  1073. * | |
  1074. * | |
  1075. * | |
  1076. * | |
  1077. * | |
  1078. * |-----------------------------|
  1079. */
  1080. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1081. (vdev->opmode == wlan_op_mode_ocb) ||
  1082. (tx_exc_metadata &&
  1083. tx_exc_metadata->is_tx_sniffer)) {
  1084. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1085. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1086. DP_STATS_INC(vdev,
  1087. tx_i.dropped.headroom_insufficient, 1);
  1088. goto failure;
  1089. }
  1090. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1091. dp_tx_err("qdf_nbuf_push_head failed");
  1092. goto failure;
  1093. }
  1094. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1095. msdu_info);
  1096. if (htt_hdr_size == 0)
  1097. goto failure;
  1098. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1099. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1100. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1101. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1102. msdu_info);
  1103. is_exception = 1;
  1104. tx_desc->length -= tx_desc->pkt_offset;
  1105. }
  1106. #if !TQM_BYPASS_WAR
  1107. if (is_exception || tx_exc_metadata)
  1108. #endif
  1109. {
  1110. /* Temporary WAR due to TQM VP issues */
  1111. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1112. qdf_atomic_inc(&soc->num_tx_exception);
  1113. }
  1114. return tx_desc;
  1115. failure:
  1116. dp_tx_desc_release(tx_desc, desc_pool_id);
  1117. return NULL;
  1118. }
  1119. /**
  1120. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment
  1121. * frame
  1122. * @vdev: DP vdev handle
  1123. * @nbuf: skb
  1124. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1125. * @desc_pool_id : Descriptor Pool ID
  1126. *
  1127. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1128. * information. For frames with fragments, allocate and prepare
  1129. * an MSDU extension descriptor
  1130. *
  1131. * Return: Pointer to Tx Descriptor on success,
  1132. * NULL on failure
  1133. */
  1134. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1135. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1136. uint8_t desc_pool_id)
  1137. {
  1138. struct dp_tx_desc_s *tx_desc;
  1139. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1140. struct dp_pdev *pdev = vdev->pdev;
  1141. struct dp_soc *soc = pdev->soc;
  1142. if (dp_tx_limit_check(vdev, nbuf))
  1143. return NULL;
  1144. /* Allocate software Tx descriptor */
  1145. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1146. if (!tx_desc) {
  1147. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1148. return NULL;
  1149. }
  1150. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1151. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1152. dp_tx_outstanding_inc(pdev);
  1153. /* Initialize the SW tx descriptor */
  1154. tx_desc->nbuf = nbuf;
  1155. tx_desc->frm_type = msdu_info->frm_type;
  1156. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1157. tx_desc->vdev_id = vdev->vdev_id;
  1158. tx_desc->pdev = pdev;
  1159. tx_desc->pkt_offset = 0;
  1160. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1161. /* Handle scattered frames - TSO/SG/ME */
  1162. /* Allocate and prepare an extension descriptor for scattered frames */
  1163. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1164. if (!msdu_ext_desc) {
  1165. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1166. goto failure;
  1167. }
  1168. #if TQM_BYPASS_WAR
  1169. /* Temporary WAR due to TQM VP issues */
  1170. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1171. qdf_atomic_inc(&soc->num_tx_exception);
  1172. #endif
  1173. if (qdf_unlikely(msdu_info->exception_fw))
  1174. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1175. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1176. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1177. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1178. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1179. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1180. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1181. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1182. else
  1183. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1184. return tx_desc;
  1185. failure:
  1186. dp_tx_desc_release(tx_desc, desc_pool_id);
  1187. return NULL;
  1188. }
  1189. /**
  1190. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1191. * @vdev: DP vdev handle
  1192. * @nbuf: buffer pointer
  1193. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1194. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1195. * descriptor
  1196. *
  1197. * Return:
  1198. */
  1199. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1200. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1201. {
  1202. qdf_nbuf_t curr_nbuf = NULL;
  1203. uint16_t total_len = 0;
  1204. qdf_dma_addr_t paddr;
  1205. int32_t i;
  1206. int32_t mapped_buf_num = 0;
  1207. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1208. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1209. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1210. /* Continue only if frames are of DATA type */
  1211. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1212. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1213. dp_tx_debug("Pkt. recd is of not data type");
  1214. goto error;
  1215. }
  1216. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1217. if (vdev->raw_mode_war &&
  1218. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1219. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1220. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1221. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1222. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1223. /*
  1224. * Number of nbuf's must not exceed the size of the frags
  1225. * array in seg_info.
  1226. */
  1227. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1228. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1229. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1230. goto error;
  1231. }
  1232. if (QDF_STATUS_SUCCESS !=
  1233. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1234. curr_nbuf,
  1235. QDF_DMA_TO_DEVICE,
  1236. curr_nbuf->len)) {
  1237. dp_tx_err("%s dma map error ", __func__);
  1238. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1239. goto error;
  1240. }
  1241. /* Update the count of mapped nbuf's */
  1242. mapped_buf_num++;
  1243. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1244. seg_info->frags[i].paddr_lo = paddr;
  1245. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1246. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1247. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1248. total_len += qdf_nbuf_len(curr_nbuf);
  1249. }
  1250. seg_info->frag_cnt = i;
  1251. seg_info->total_len = total_len;
  1252. seg_info->next = NULL;
  1253. sg_info->curr_seg = seg_info;
  1254. msdu_info->frm_type = dp_tx_frm_raw;
  1255. msdu_info->num_seg = 1;
  1256. return nbuf;
  1257. error:
  1258. i = 0;
  1259. while (nbuf) {
  1260. curr_nbuf = nbuf;
  1261. if (i < mapped_buf_num) {
  1262. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1263. QDF_DMA_TO_DEVICE,
  1264. curr_nbuf->len);
  1265. i++;
  1266. }
  1267. nbuf = qdf_nbuf_next(nbuf);
  1268. qdf_nbuf_free(curr_nbuf);
  1269. }
  1270. return NULL;
  1271. }
  1272. /**
  1273. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1274. * @soc: DP soc handle
  1275. * @nbuf: Buffer pointer
  1276. *
  1277. * unmap the chain of nbufs that belong to this RAW frame.
  1278. *
  1279. * Return: None
  1280. */
  1281. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1282. qdf_nbuf_t nbuf)
  1283. {
  1284. qdf_nbuf_t cur_nbuf = nbuf;
  1285. do {
  1286. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1287. QDF_DMA_TO_DEVICE,
  1288. cur_nbuf->len);
  1289. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1290. } while (cur_nbuf);
  1291. }
  1292. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1293. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1294. qdf_nbuf_t nbuf)
  1295. {
  1296. qdf_nbuf_t nbuf_local;
  1297. struct dp_vdev *vdev_local = vdev_hdl;
  1298. do {
  1299. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1300. break;
  1301. nbuf_local = nbuf;
  1302. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1303. htt_cmn_pkt_type_raw))
  1304. break;
  1305. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1306. break;
  1307. else if (qdf_nbuf_is_tso((nbuf_local)))
  1308. break;
  1309. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1310. (nbuf_local),
  1311. NULL, 1, 0);
  1312. } while (0);
  1313. }
  1314. #endif
  1315. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1316. void dp_tx_update_stats(struct dp_soc *soc,
  1317. struct dp_tx_desc_s *tx_desc,
  1318. uint8_t ring_id)
  1319. {
  1320. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1321. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1322. }
  1323. int
  1324. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1325. struct dp_tx_desc_s *tx_desc,
  1326. uint8_t tid,
  1327. struct dp_tx_msdu_info_s *msdu_info,
  1328. uint8_t ring_id)
  1329. {
  1330. struct dp_swlm *swlm = &soc->swlm;
  1331. union swlm_data swlm_query_data;
  1332. struct dp_swlm_tcl_data tcl_data;
  1333. QDF_STATUS status;
  1334. int ret;
  1335. if (!swlm->is_enabled)
  1336. return msdu_info->skip_hp_update;
  1337. tcl_data.nbuf = tx_desc->nbuf;
  1338. tcl_data.tid = tid;
  1339. tcl_data.ring_id = ring_id;
  1340. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1341. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1342. swlm_query_data.tcl_data = &tcl_data;
  1343. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1344. if (QDF_IS_STATUS_ERROR(status)) {
  1345. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1346. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1347. return 0;
  1348. }
  1349. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1350. if (ret) {
  1351. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1352. } else {
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1354. }
  1355. return ret;
  1356. }
  1357. void
  1358. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1359. int coalesce)
  1360. {
  1361. if (coalesce)
  1362. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1363. else
  1364. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1365. }
  1366. static inline void
  1367. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1368. {
  1369. if (((i + 1) < msdu_info->num_seg))
  1370. msdu_info->skip_hp_update = 1;
  1371. else
  1372. msdu_info->skip_hp_update = 0;
  1373. }
  1374. static inline void
  1375. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1376. {
  1377. hal_ring_handle_t hal_ring_hdl =
  1378. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1379. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1380. dp_err("Fillmore: SRNG access start failed");
  1381. return;
  1382. }
  1383. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1384. }
  1385. static inline void
  1386. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1387. QDF_STATUS status,
  1388. struct dp_tx_msdu_info_s *msdu_info)
  1389. {
  1390. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1391. dp_flush_tcp_hp(soc,
  1392. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1393. }
  1394. }
  1395. #else
  1396. static inline void
  1397. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1398. {
  1399. }
  1400. static inline void
  1401. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1402. QDF_STATUS status,
  1403. struct dp_tx_msdu_info_s *msdu_info)
  1404. {
  1405. }
  1406. #endif
  1407. #ifdef FEATURE_RUNTIME_PM
  1408. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1409. {
  1410. int ret;
  1411. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1412. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1413. return ret;
  1414. }
  1415. void
  1416. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1417. hal_ring_handle_t hal_ring_hdl,
  1418. int coalesce)
  1419. {
  1420. int ret;
  1421. /*
  1422. * Avoid runtime get and put APIs under high throughput scenarios.
  1423. */
  1424. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1425. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1426. return;
  1427. }
  1428. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1429. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1430. if (hif_system_pm_state_check(soc->hif_handle)) {
  1431. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1432. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1433. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1434. } else {
  1435. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1436. }
  1437. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1438. } else {
  1439. dp_runtime_get(soc);
  1440. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1441. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1442. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1443. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1444. dp_runtime_put(soc);
  1445. }
  1446. }
  1447. #else
  1448. #ifdef DP_POWER_SAVE
  1449. void
  1450. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1451. hal_ring_handle_t hal_ring_hdl,
  1452. int coalesce)
  1453. {
  1454. if (hif_system_pm_state_check(soc->hif_handle)) {
  1455. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1456. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1457. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1458. } else {
  1459. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1460. }
  1461. }
  1462. #endif
  1463. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1464. {
  1465. return 0;
  1466. }
  1467. #endif
  1468. /**
  1469. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1470. * @vdev: DP vdev handle
  1471. * @nbuf: skb
  1472. * @msdu_info: msdu descriptor
  1473. *
  1474. * Extract the DSCP or PCP information from frame and map into TID value.
  1475. *
  1476. * Return: void
  1477. */
  1478. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1479. struct dp_tx_msdu_info_s *msdu_info)
  1480. {
  1481. uint8_t tos = 0, dscp_tid_override = 0;
  1482. uint8_t *hdr_ptr, *L3datap;
  1483. uint8_t is_mcast = 0;
  1484. qdf_ether_header_t *eh = NULL;
  1485. qdf_ethervlan_header_t *evh = NULL;
  1486. uint16_t ether_type;
  1487. qdf_llc_t *llcHdr;
  1488. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1489. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1490. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1491. eh = (qdf_ether_header_t *)nbuf->data;
  1492. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1493. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1494. } else {
  1495. qdf_dot3_qosframe_t *qos_wh =
  1496. (qdf_dot3_qosframe_t *) nbuf->data;
  1497. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1498. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1499. return;
  1500. }
  1501. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1502. ether_type = eh->ether_type;
  1503. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1504. /*
  1505. * Check if packet is dot3 or eth2 type.
  1506. */
  1507. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1508. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1509. sizeof(*llcHdr));
  1510. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1511. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1512. sizeof(*llcHdr);
  1513. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1514. + sizeof(*llcHdr) +
  1515. sizeof(qdf_net_vlanhdr_t));
  1516. } else {
  1517. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1518. sizeof(*llcHdr);
  1519. }
  1520. } else {
  1521. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1522. evh = (qdf_ethervlan_header_t *) eh;
  1523. ether_type = evh->ether_type;
  1524. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1525. }
  1526. }
  1527. /*
  1528. * Find priority from IP TOS DSCP field
  1529. */
  1530. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1531. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1532. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1533. /* Only for unicast frames */
  1534. if (!is_mcast) {
  1535. /* send it on VO queue */
  1536. msdu_info->tid = DP_VO_TID;
  1537. }
  1538. } else {
  1539. /*
  1540. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1541. * from TOS byte.
  1542. */
  1543. tos = ip->ip_tos;
  1544. dscp_tid_override = 1;
  1545. }
  1546. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1547. /* TODO
  1548. * use flowlabel
  1549. *igmpmld cases to be handled in phase 2
  1550. */
  1551. unsigned long ver_pri_flowlabel;
  1552. unsigned long pri;
  1553. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1554. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1555. DP_IPV6_PRIORITY_SHIFT;
  1556. tos = pri;
  1557. dscp_tid_override = 1;
  1558. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1559. msdu_info->tid = DP_VO_TID;
  1560. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1561. /* Only for unicast frames */
  1562. if (!is_mcast) {
  1563. /* send ucast arp on VO queue */
  1564. msdu_info->tid = DP_VO_TID;
  1565. }
  1566. }
  1567. /*
  1568. * Assign all MCAST packets to BE
  1569. */
  1570. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1571. if (is_mcast) {
  1572. tos = 0;
  1573. dscp_tid_override = 1;
  1574. }
  1575. }
  1576. if (dscp_tid_override == 1) {
  1577. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1578. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1579. }
  1580. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1581. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1582. return;
  1583. }
  1584. /**
  1585. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1586. * @vdev: DP vdev handle
  1587. * @nbuf: skb
  1588. * @msdu_info: msdu descriptor
  1589. *
  1590. * Software based TID classification is required when more than 2 DSCP-TID
  1591. * mapping tables are needed.
  1592. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1593. *
  1594. * Return: void
  1595. */
  1596. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1597. struct dp_tx_msdu_info_s *msdu_info)
  1598. {
  1599. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1600. /*
  1601. * skip_sw_tid_classification flag will set in below cases-
  1602. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1603. * 2. hlos_tid_override enabled for vdev
  1604. * 3. mesh mode enabled for vdev
  1605. */
  1606. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1607. /* Update tid in msdu_info from skb priority */
  1608. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1609. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1610. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1611. if (tid == DP_TX_INVALID_QOS_TAG)
  1612. return;
  1613. msdu_info->tid = tid;
  1614. return;
  1615. }
  1616. return;
  1617. }
  1618. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1619. }
  1620. #ifdef FEATURE_WLAN_TDLS
  1621. /**
  1622. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1623. * @soc: datapath SOC
  1624. * @vdev: datapath vdev
  1625. * @tx_desc: TX descriptor
  1626. *
  1627. * Return: None
  1628. */
  1629. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1630. struct dp_vdev *vdev,
  1631. struct dp_tx_desc_s *tx_desc)
  1632. {
  1633. if (vdev) {
  1634. if (vdev->is_tdls_frame) {
  1635. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1636. vdev->is_tdls_frame = false;
  1637. }
  1638. }
  1639. }
  1640. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1641. {
  1642. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1643. switch (soc->arch_id) {
  1644. case CDP_ARCH_TYPE_LI:
  1645. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1646. break;
  1647. case CDP_ARCH_TYPE_BE:
  1648. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1649. break;
  1650. default:
  1651. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1652. QDF_BUG(0);
  1653. }
  1654. return tx_status;
  1655. }
  1656. /**
  1657. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1658. * @soc: dp_soc handle
  1659. * @tx_desc: TX descriptor
  1660. *
  1661. * Return: None
  1662. */
  1663. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1664. struct dp_tx_desc_s *tx_desc)
  1665. {
  1666. uint8_t tx_status = 0;
  1667. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1668. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1669. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1670. DP_MOD_ID_TDLS);
  1671. if (qdf_unlikely(!vdev)) {
  1672. dp_err_rl("vdev is null!");
  1673. goto error;
  1674. }
  1675. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1676. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1677. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1678. if (vdev->tx_non_std_data_callback.func) {
  1679. qdf_nbuf_set_next(nbuf, NULL);
  1680. vdev->tx_non_std_data_callback.func(
  1681. vdev->tx_non_std_data_callback.ctxt,
  1682. nbuf, tx_status);
  1683. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1684. return;
  1685. } else {
  1686. dp_err_rl("callback func is null");
  1687. }
  1688. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1689. error:
  1690. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1691. qdf_nbuf_free(nbuf);
  1692. }
  1693. /**
  1694. * dp_tx_msdu_single_map() - do nbuf map
  1695. * @vdev: DP vdev handle
  1696. * @tx_desc: DP TX descriptor pointer
  1697. * @nbuf: skb pointer
  1698. *
  1699. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1700. * operation done in other component.
  1701. *
  1702. * Return: QDF_STATUS
  1703. */
  1704. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1705. struct dp_tx_desc_s *tx_desc,
  1706. qdf_nbuf_t nbuf)
  1707. {
  1708. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1709. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1710. nbuf,
  1711. QDF_DMA_TO_DEVICE,
  1712. nbuf->len);
  1713. else
  1714. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1715. QDF_DMA_TO_DEVICE);
  1716. }
  1717. #else
  1718. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1719. struct dp_vdev *vdev,
  1720. struct dp_tx_desc_s *tx_desc)
  1721. {
  1722. }
  1723. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1724. struct dp_tx_desc_s *tx_desc)
  1725. {
  1726. }
  1727. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1728. struct dp_tx_desc_s *tx_desc,
  1729. qdf_nbuf_t nbuf)
  1730. {
  1731. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1732. nbuf,
  1733. QDF_DMA_TO_DEVICE,
  1734. nbuf->len);
  1735. }
  1736. #endif
  1737. static inline
  1738. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1739. struct dp_tx_desc_s *tx_desc,
  1740. qdf_nbuf_t nbuf)
  1741. {
  1742. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1743. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1744. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1745. return 0;
  1746. return qdf_nbuf_mapped_paddr_get(nbuf);
  1747. }
  1748. static inline
  1749. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1750. {
  1751. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1752. desc->nbuf,
  1753. desc->dma_addr,
  1754. QDF_DMA_TO_DEVICE,
  1755. desc->length);
  1756. }
  1757. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1758. static inline bool
  1759. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1760. {
  1761. struct net_device *ingress_dev;
  1762. skb_frag_t *frag;
  1763. uint16_t buf_len = 0;
  1764. uint16_t linear_data_len = 0;
  1765. uint8_t *payload_addr = NULL;
  1766. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1767. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1768. dev_put(ingress_dev);
  1769. frag = &(skb_shinfo(nbuf)->frags[0]);
  1770. buf_len = skb_frag_size(frag);
  1771. payload_addr = (uint8_t *)skb_frag_address(frag);
  1772. linear_data_len = skb_headlen(nbuf);
  1773. buf_len += linear_data_len;
  1774. payload_addr = payload_addr - linear_data_len;
  1775. memcpy(payload_addr, nbuf->data, linear_data_len);
  1776. msdu_info->frm_type = dp_tx_frm_rmnet;
  1777. msdu_info->buf_len = buf_len;
  1778. msdu_info->payload_addr = payload_addr;
  1779. return true;
  1780. }
  1781. dev_put(ingress_dev);
  1782. return false;
  1783. }
  1784. static inline
  1785. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1786. struct dp_tx_desc_s *tx_desc)
  1787. {
  1788. qdf_dma_addr_t paddr;
  1789. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1790. tx_desc->length = msdu_info->buf_len;
  1791. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1792. (void *)(msdu_info->payload_addr +
  1793. msdu_info->buf_len));
  1794. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1795. return paddr;
  1796. }
  1797. #else
  1798. static inline bool
  1799. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1800. {
  1801. return false;
  1802. }
  1803. static inline
  1804. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1805. struct dp_tx_desc_s *tx_desc)
  1806. {
  1807. return 0;
  1808. }
  1809. #endif
  1810. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1811. static inline
  1812. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1813. struct dp_tx_desc_s *tx_desc,
  1814. qdf_nbuf_t nbuf)
  1815. {
  1816. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1817. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1818. (void *)(nbuf->data + nbuf->len));
  1819. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1820. } else {
  1821. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1822. }
  1823. }
  1824. static inline
  1825. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1826. struct dp_tx_desc_s *desc)
  1827. {
  1828. if (qdf_unlikely(!(desc->flags &
  1829. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1830. return dp_tx_nbuf_unmap_regular(soc, desc);
  1831. }
  1832. #else
  1833. static inline
  1834. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1835. struct dp_tx_desc_s *tx_desc,
  1836. qdf_nbuf_t nbuf)
  1837. {
  1838. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1839. }
  1840. static inline
  1841. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1842. struct dp_tx_desc_s *desc)
  1843. {
  1844. return dp_tx_nbuf_unmap_regular(soc, desc);
  1845. }
  1846. #endif
  1847. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1848. static inline
  1849. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1850. {
  1851. dp_tx_nbuf_unmap(soc, desc);
  1852. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1853. }
  1854. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1855. {
  1856. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1857. dp_tx_nbuf_unmap(soc, desc);
  1858. }
  1859. #else
  1860. static inline
  1861. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1862. {
  1863. }
  1864. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1865. {
  1866. dp_tx_nbuf_unmap(soc, desc);
  1867. }
  1868. #endif
  1869. #ifdef MESH_MODE_SUPPORT
  1870. /**
  1871. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1872. * @soc: datapath SOC
  1873. * @vdev: datapath vdev
  1874. * @tx_desc: TX descriptor
  1875. *
  1876. * Return: None
  1877. */
  1878. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1879. struct dp_vdev *vdev,
  1880. struct dp_tx_desc_s *tx_desc)
  1881. {
  1882. if (qdf_unlikely(vdev->mesh_vdev))
  1883. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1884. }
  1885. /**
  1886. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1887. * @soc: dp_soc handle
  1888. * @tx_desc: TX descriptor
  1889. * @delayed_free: delay the nbuf free
  1890. *
  1891. * Return: nbuf to be freed late
  1892. */
  1893. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1894. struct dp_tx_desc_s *tx_desc,
  1895. bool delayed_free)
  1896. {
  1897. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1898. struct dp_vdev *vdev = NULL;
  1899. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1900. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1901. if (vdev)
  1902. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1903. if (delayed_free)
  1904. return nbuf;
  1905. qdf_nbuf_free(nbuf);
  1906. } else {
  1907. if (vdev && vdev->osif_tx_free_ext) {
  1908. vdev->osif_tx_free_ext((nbuf));
  1909. } else {
  1910. if (delayed_free)
  1911. return nbuf;
  1912. qdf_nbuf_free(nbuf);
  1913. }
  1914. }
  1915. if (vdev)
  1916. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1917. return NULL;
  1918. }
  1919. #else
  1920. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1921. struct dp_vdev *vdev,
  1922. struct dp_tx_desc_s *tx_desc)
  1923. {
  1924. }
  1925. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1926. struct dp_tx_desc_s *tx_desc,
  1927. bool delayed_free)
  1928. {
  1929. return NULL;
  1930. }
  1931. #endif
  1932. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1933. {
  1934. struct dp_pdev *pdev = NULL;
  1935. struct dp_ast_entry *src_ast_entry = NULL;
  1936. struct dp_ast_entry *dst_ast_entry = NULL;
  1937. struct dp_soc *soc = NULL;
  1938. qdf_assert(vdev);
  1939. pdev = vdev->pdev;
  1940. qdf_assert(pdev);
  1941. soc = pdev->soc;
  1942. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1943. (soc, dstmac, vdev->pdev->pdev_id);
  1944. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1945. (soc, srcmac, vdev->pdev->pdev_id);
  1946. if (dst_ast_entry && src_ast_entry) {
  1947. if (dst_ast_entry->peer_id ==
  1948. src_ast_entry->peer_id)
  1949. return 1;
  1950. }
  1951. return 0;
  1952. }
  1953. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1954. defined(WLAN_MCAST_MLO)
  1955. /* MLO peer id for reinject*/
  1956. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1957. /* MLO vdev id inc offset */
  1958. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1959. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1960. static inline bool
  1961. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1962. {
  1963. if (tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  1964. return true;
  1965. return false;
  1966. }
  1967. #else
  1968. static inline bool
  1969. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1970. {
  1971. return false;
  1972. }
  1973. #endif
  1974. static inline void
  1975. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  1976. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1977. {
  1978. /* wds ext enabled will not set the TO_FW bit */
  1979. if (dp_tx_wds_ext_check(tx_exc_metadata))
  1980. return;
  1981. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1982. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1983. qdf_atomic_inc(&soc->num_tx_exception);
  1984. }
  1985. }
  1986. static inline void
  1987. dp_tx_update_mcast_param(uint16_t peer_id,
  1988. uint16_t *htt_tcl_metadata,
  1989. struct dp_vdev *vdev,
  1990. struct dp_tx_msdu_info_s *msdu_info)
  1991. {
  1992. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1993. *htt_tcl_metadata = 0;
  1994. DP_TX_TCL_METADATA_TYPE_SET(
  1995. *htt_tcl_metadata,
  1996. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1997. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1998. msdu_info->gsn);
  1999. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2000. if (qdf_unlikely(vdev->nawds_enabled ||
  2001. dp_vdev_is_wds_ext_enabled(vdev)))
  2002. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2003. *htt_tcl_metadata, 1);
  2004. } else {
  2005. msdu_info->vdev_id = vdev->vdev_id;
  2006. }
  2007. }
  2008. #else
  2009. static inline void
  2010. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  2011. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2012. {
  2013. }
  2014. static inline void
  2015. dp_tx_update_mcast_param(uint16_t peer_id,
  2016. uint16_t *htt_tcl_metadata,
  2017. struct dp_vdev *vdev,
  2018. struct dp_tx_msdu_info_s *msdu_info)
  2019. {
  2020. }
  2021. #endif
  2022. #ifdef DP_TX_SW_DROP_STATS_INC
  2023. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2024. qdf_nbuf_t nbuf,
  2025. enum cdp_tx_sw_drop drop_code)
  2026. {
  2027. /* EAPOL Drop stats */
  2028. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2029. switch (drop_code) {
  2030. case TX_DESC_ERR:
  2031. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2032. break;
  2033. case TX_HAL_RING_ACCESS_ERR:
  2034. DP_STATS_INC(pdev,
  2035. eap_drop_stats.tx_hal_ring_access_err, 1);
  2036. break;
  2037. case TX_DMA_MAP_ERR:
  2038. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2039. break;
  2040. case TX_HW_ENQUEUE:
  2041. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2042. break;
  2043. case TX_SW_ENQUEUE:
  2044. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2045. break;
  2046. default:
  2047. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2048. break;
  2049. }
  2050. }
  2051. }
  2052. #else
  2053. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2054. qdf_nbuf_t nbuf,
  2055. enum cdp_tx_sw_drop drop_code)
  2056. {
  2057. }
  2058. #endif
  2059. qdf_nbuf_t
  2060. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2061. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2062. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2063. {
  2064. struct dp_pdev *pdev = vdev->pdev;
  2065. struct dp_soc *soc = pdev->soc;
  2066. struct dp_tx_desc_s *tx_desc;
  2067. QDF_STATUS status;
  2068. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2069. uint16_t htt_tcl_metadata = 0;
  2070. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2071. uint8_t tid = msdu_info->tid;
  2072. struct cdp_tid_tx_stats *tid_stats = NULL;
  2073. qdf_dma_addr_t paddr;
  2074. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2075. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2076. msdu_info, tx_exc_metadata);
  2077. if (!tx_desc) {
  2078. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2079. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2080. drop_code = TX_DESC_ERR;
  2081. goto fail_return;
  2082. }
  2083. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2084. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2085. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2086. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2087. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2088. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2089. DP_TCL_METADATA_TYPE_PEER_BASED);
  2090. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2091. peer_id);
  2092. dp_tx_bypass_reinjection(soc, tx_desc, tx_exc_metadata);
  2093. } else
  2094. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2095. if (msdu_info->exception_fw)
  2096. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2097. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2098. !pdev->enhanced_stats_en);
  2099. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2100. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2101. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2102. else
  2103. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2104. if (!paddr) {
  2105. /* Handle failure */
  2106. dp_err("qdf_nbuf_map failed");
  2107. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2108. drop_code = TX_DMA_MAP_ERR;
  2109. goto release_desc;
  2110. }
  2111. tx_desc->dma_addr = paddr;
  2112. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2113. tx_desc->id, DP_TX_DESC_MAP);
  2114. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2115. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2116. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2117. htt_tcl_metadata,
  2118. tx_exc_metadata, msdu_info);
  2119. if (status != QDF_STATUS_SUCCESS) {
  2120. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2121. tx_desc, tx_q->ring_id);
  2122. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2123. tx_desc->id, DP_TX_DESC_UNMAP);
  2124. dp_tx_nbuf_unmap(soc, tx_desc);
  2125. drop_code = TX_HW_ENQUEUE;
  2126. goto release_desc;
  2127. }
  2128. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2129. return NULL;
  2130. release_desc:
  2131. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2132. fail_return:
  2133. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2134. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2135. tid_stats = &pdev->stats.tid_stats.
  2136. tid_tx_stats[tx_q->ring_id][tid];
  2137. tid_stats->swdrop_cnt[drop_code]++;
  2138. return nbuf;
  2139. }
  2140. /**
  2141. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2142. * @soc: Soc handle
  2143. * @desc: software Tx descriptor to be processed
  2144. *
  2145. * Return: 0 if Success
  2146. */
  2147. #ifdef FEATURE_WLAN_TDLS
  2148. static inline int
  2149. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2150. {
  2151. /* If it is TDLS mgmt, don't unmap or free the frame */
  2152. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2153. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2154. return 0;
  2155. }
  2156. return 1;
  2157. }
  2158. #else
  2159. static inline int
  2160. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2161. {
  2162. return 1;
  2163. }
  2164. #endif
  2165. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2166. bool delayed_free)
  2167. {
  2168. qdf_nbuf_t nbuf = desc->nbuf;
  2169. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2170. /* nbuf already freed in vdev detach path */
  2171. if (!nbuf)
  2172. return NULL;
  2173. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2174. return NULL;
  2175. /* 0 : MSDU buffer, 1 : MLE */
  2176. if (desc->msdu_ext_desc) {
  2177. /* TSO free */
  2178. if (hal_tx_ext_desc_get_tso_enable(
  2179. desc->msdu_ext_desc->vaddr)) {
  2180. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2181. desc->id, DP_TX_COMP_MSDU_EXT);
  2182. dp_tx_tso_seg_history_add(soc,
  2183. desc->msdu_ext_desc->tso_desc,
  2184. desc->nbuf, desc->id, type);
  2185. /* unmap eash TSO seg before free the nbuf */
  2186. dp_tx_tso_unmap_segment(soc,
  2187. desc->msdu_ext_desc->tso_desc,
  2188. desc->msdu_ext_desc->
  2189. tso_num_desc);
  2190. goto nbuf_free;
  2191. }
  2192. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2193. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2194. qdf_dma_addr_t iova;
  2195. uint32_t frag_len;
  2196. uint32_t i;
  2197. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2198. QDF_DMA_TO_DEVICE,
  2199. qdf_nbuf_headlen(nbuf));
  2200. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2201. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2202. &iova,
  2203. &frag_len);
  2204. if (!iova || !frag_len)
  2205. break;
  2206. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2207. QDF_DMA_TO_DEVICE);
  2208. }
  2209. goto nbuf_free;
  2210. }
  2211. }
  2212. /* If it's ME frame, dont unmap the cloned nbuf's */
  2213. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2214. goto nbuf_free;
  2215. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2216. dp_tx_unmap(soc, desc);
  2217. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2218. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2219. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2220. return NULL;
  2221. nbuf_free:
  2222. if (delayed_free)
  2223. return nbuf;
  2224. qdf_nbuf_free(nbuf);
  2225. return NULL;
  2226. }
  2227. /**
  2228. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2229. * @soc: DP soc handle
  2230. * @nbuf: skb
  2231. * @msdu_info: MSDU info
  2232. *
  2233. * Return: None
  2234. */
  2235. static inline void
  2236. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2237. struct dp_tx_msdu_info_s *msdu_info)
  2238. {
  2239. uint32_t cur_idx;
  2240. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2241. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2242. qdf_nbuf_headlen(nbuf));
  2243. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2244. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2245. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2246. seg->frags[cur_idx].paddr_hi) << 32),
  2247. seg->frags[cur_idx].len,
  2248. QDF_DMA_TO_DEVICE);
  2249. }
  2250. #if QDF_LOCK_STATS
  2251. noinline
  2252. #else
  2253. #endif
  2254. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2255. struct dp_tx_msdu_info_s *msdu_info)
  2256. {
  2257. uint32_t i;
  2258. struct dp_pdev *pdev = vdev->pdev;
  2259. struct dp_soc *soc = pdev->soc;
  2260. struct dp_tx_desc_s *tx_desc;
  2261. bool is_cce_classified = false;
  2262. QDF_STATUS status;
  2263. uint16_t htt_tcl_metadata = 0;
  2264. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2265. struct cdp_tid_tx_stats *tid_stats = NULL;
  2266. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2267. if (msdu_info->frm_type == dp_tx_frm_me)
  2268. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2269. i = 0;
  2270. /* Print statement to track i and num_seg */
  2271. /*
  2272. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2273. * descriptors using information in msdu_info
  2274. */
  2275. while (i < msdu_info->num_seg) {
  2276. /*
  2277. * Setup Tx descriptor for an MSDU, and MSDU extension
  2278. * descriptor
  2279. */
  2280. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2281. tx_q->desc_pool_id);
  2282. if (!tx_desc) {
  2283. if (msdu_info->frm_type == dp_tx_frm_me) {
  2284. prep_desc_fail++;
  2285. dp_tx_me_free_buf(pdev,
  2286. (void *)(msdu_info->u.sg_info
  2287. .curr_seg->frags[0].vaddr));
  2288. if (prep_desc_fail == msdu_info->num_seg) {
  2289. /*
  2290. * Unmap is needed only if descriptor
  2291. * preparation failed for all segments.
  2292. */
  2293. qdf_nbuf_unmap(soc->osdev,
  2294. msdu_info->u.sg_info.
  2295. curr_seg->nbuf,
  2296. QDF_DMA_TO_DEVICE);
  2297. }
  2298. /*
  2299. * Free the nbuf for the current segment
  2300. * and make it point to the next in the list.
  2301. * For me, there are as many segments as there
  2302. * are no of clients.
  2303. */
  2304. qdf_nbuf_free(msdu_info->u.sg_info
  2305. .curr_seg->nbuf);
  2306. if (msdu_info->u.sg_info.curr_seg->next) {
  2307. msdu_info->u.sg_info.curr_seg =
  2308. msdu_info->u.sg_info
  2309. .curr_seg->next;
  2310. nbuf = msdu_info->u.sg_info
  2311. .curr_seg->nbuf;
  2312. }
  2313. i++;
  2314. continue;
  2315. }
  2316. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2317. dp_tx_tso_seg_history_add(
  2318. soc,
  2319. msdu_info->u.tso_info.curr_seg,
  2320. nbuf, 0, DP_TX_DESC_UNMAP);
  2321. dp_tx_tso_unmap_segment(soc,
  2322. msdu_info->u.tso_info.
  2323. curr_seg,
  2324. msdu_info->u.tso_info.
  2325. tso_num_seg_list);
  2326. if (msdu_info->u.tso_info.curr_seg->next) {
  2327. msdu_info->u.tso_info.curr_seg =
  2328. msdu_info->u.tso_info.curr_seg->next;
  2329. i++;
  2330. continue;
  2331. }
  2332. }
  2333. if (msdu_info->frm_type == dp_tx_frm_sg)
  2334. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2335. goto done;
  2336. }
  2337. if (msdu_info->frm_type == dp_tx_frm_me) {
  2338. tx_desc->msdu_ext_desc->me_buffer =
  2339. (struct dp_tx_me_buf_t *)msdu_info->
  2340. u.sg_info.curr_seg->frags[0].vaddr;
  2341. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2342. }
  2343. if (is_cce_classified)
  2344. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2345. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2346. if (msdu_info->exception_fw) {
  2347. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2348. }
  2349. dp_tx_is_hp_update_required(i, msdu_info);
  2350. /*
  2351. * For frames with multiple segments (TSO, ME), jump to next
  2352. * segment.
  2353. */
  2354. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2355. if (msdu_info->u.tso_info.curr_seg->next) {
  2356. msdu_info->u.tso_info.curr_seg =
  2357. msdu_info->u.tso_info.curr_seg->next;
  2358. /*
  2359. * If this is a jumbo nbuf, then increment the
  2360. * number of nbuf users for each additional
  2361. * segment of the msdu. This will ensure that
  2362. * the skb is freed only after receiving tx
  2363. * completion for all segments of an nbuf
  2364. */
  2365. qdf_nbuf_inc_users(nbuf);
  2366. /* Check with MCL if this is needed */
  2367. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2368. */
  2369. }
  2370. }
  2371. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2372. &htt_tcl_metadata,
  2373. vdev,
  2374. msdu_info);
  2375. /*
  2376. * Enqueue the Tx MSDU descriptor to HW for transmit
  2377. */
  2378. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2379. htt_tcl_metadata,
  2380. NULL, msdu_info);
  2381. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2382. if (status != QDF_STATUS_SUCCESS) {
  2383. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2384. tx_desc, tx_q->ring_id);
  2385. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2386. tid_stats = &pdev->stats.tid_stats.
  2387. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2388. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2389. if (msdu_info->frm_type == dp_tx_frm_me) {
  2390. hw_enq_fail++;
  2391. if (hw_enq_fail == msdu_info->num_seg) {
  2392. /*
  2393. * Unmap is needed only if enqueue
  2394. * failed for all segments.
  2395. */
  2396. qdf_nbuf_unmap(soc->osdev,
  2397. msdu_info->u.sg_info.
  2398. curr_seg->nbuf,
  2399. QDF_DMA_TO_DEVICE);
  2400. }
  2401. /*
  2402. * Free the nbuf for the current segment
  2403. * and make it point to the next in the list.
  2404. * For me, there are as many segments as there
  2405. * are no of clients.
  2406. */
  2407. qdf_nbuf_free(msdu_info->u.sg_info
  2408. .curr_seg->nbuf);
  2409. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2410. if (msdu_info->u.sg_info.curr_seg->next) {
  2411. msdu_info->u.sg_info.curr_seg =
  2412. msdu_info->u.sg_info
  2413. .curr_seg->next;
  2414. nbuf = msdu_info->u.sg_info
  2415. .curr_seg->nbuf;
  2416. } else
  2417. break;
  2418. i++;
  2419. continue;
  2420. }
  2421. /*
  2422. * For TSO frames, the nbuf users increment done for
  2423. * the current segment has to be reverted, since the
  2424. * hw enqueue for this segment failed
  2425. */
  2426. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2427. msdu_info->u.tso_info.curr_seg) {
  2428. /*
  2429. * unmap and free current,
  2430. * retransmit remaining segments
  2431. */
  2432. dp_tx_comp_free_buf(soc, tx_desc, false);
  2433. i++;
  2434. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2435. continue;
  2436. }
  2437. if (msdu_info->frm_type == dp_tx_frm_sg)
  2438. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2439. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2440. goto done;
  2441. }
  2442. /*
  2443. * TODO
  2444. * if tso_info structure can be modified to have curr_seg
  2445. * as first element, following 2 blocks of code (for TSO and SG)
  2446. * can be combined into 1
  2447. */
  2448. /*
  2449. * For Multicast-Unicast converted packets,
  2450. * each converted frame (for a client) is represented as
  2451. * 1 segment
  2452. */
  2453. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2454. (msdu_info->frm_type == dp_tx_frm_me)) {
  2455. if (msdu_info->u.sg_info.curr_seg->next) {
  2456. msdu_info->u.sg_info.curr_seg =
  2457. msdu_info->u.sg_info.curr_seg->next;
  2458. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2459. } else
  2460. break;
  2461. }
  2462. i++;
  2463. }
  2464. nbuf = NULL;
  2465. done:
  2466. return nbuf;
  2467. }
  2468. /**
  2469. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2470. * for SG frames
  2471. * @vdev: DP vdev handle
  2472. * @nbuf: skb
  2473. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2474. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2475. *
  2476. * Return: NULL on success,
  2477. * nbuf when it fails to send
  2478. */
  2479. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2480. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2481. {
  2482. uint32_t cur_frag, nr_frags, i;
  2483. qdf_dma_addr_t paddr;
  2484. struct dp_tx_sg_info_s *sg_info;
  2485. sg_info = &msdu_info->u.sg_info;
  2486. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2487. if (QDF_STATUS_SUCCESS !=
  2488. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2489. QDF_DMA_TO_DEVICE,
  2490. qdf_nbuf_headlen(nbuf))) {
  2491. dp_tx_err("dma map error");
  2492. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2493. qdf_nbuf_free(nbuf);
  2494. return NULL;
  2495. }
  2496. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2497. seg_info->frags[0].paddr_lo = paddr;
  2498. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2499. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2500. seg_info->frags[0].vaddr = (void *) nbuf;
  2501. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2502. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2503. nbuf, 0,
  2504. QDF_DMA_TO_DEVICE,
  2505. cur_frag)) {
  2506. dp_tx_err("frag dma map error");
  2507. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2508. goto map_err;
  2509. }
  2510. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2511. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2512. seg_info->frags[cur_frag + 1].paddr_hi =
  2513. ((uint64_t) paddr) >> 32;
  2514. seg_info->frags[cur_frag + 1].len =
  2515. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2516. }
  2517. seg_info->frag_cnt = (cur_frag + 1);
  2518. seg_info->total_len = qdf_nbuf_len(nbuf);
  2519. seg_info->next = NULL;
  2520. sg_info->curr_seg = seg_info;
  2521. msdu_info->frm_type = dp_tx_frm_sg;
  2522. msdu_info->num_seg = 1;
  2523. return nbuf;
  2524. map_err:
  2525. /* restore paddr into nbuf before calling unmap */
  2526. qdf_nbuf_mapped_paddr_set(nbuf,
  2527. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2528. ((uint64_t)
  2529. seg_info->frags[0].paddr_hi) << 32));
  2530. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2531. QDF_DMA_TO_DEVICE,
  2532. seg_info->frags[0].len);
  2533. for (i = 1; i <= cur_frag; i++) {
  2534. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2535. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2536. seg_info->frags[i].paddr_hi) << 32),
  2537. seg_info->frags[i].len,
  2538. QDF_DMA_TO_DEVICE);
  2539. }
  2540. qdf_nbuf_free(nbuf);
  2541. return NULL;
  2542. }
  2543. /**
  2544. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2545. * @vdev: DP vdev handle
  2546. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2547. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2548. *
  2549. * Return: NULL on failure,
  2550. * nbuf when extracted successfully
  2551. */
  2552. static
  2553. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2554. struct dp_tx_msdu_info_s *msdu_info,
  2555. uint16_t ppdu_cookie)
  2556. {
  2557. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2558. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2559. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2560. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2561. (msdu_info->meta_data[5], 1);
  2562. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2563. (msdu_info->meta_data[5], 1);
  2564. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2565. (msdu_info->meta_data[6], ppdu_cookie);
  2566. msdu_info->exception_fw = 1;
  2567. msdu_info->is_tx_sniffer = 1;
  2568. }
  2569. #ifdef MESH_MODE_SUPPORT
  2570. /**
  2571. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2572. * and prepare msdu_info for mesh frames.
  2573. * @vdev: DP vdev handle
  2574. * @nbuf: skb
  2575. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2576. *
  2577. * Return: NULL on failure,
  2578. * nbuf when extracted successfully
  2579. */
  2580. static
  2581. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2582. struct dp_tx_msdu_info_s *msdu_info)
  2583. {
  2584. struct meta_hdr_s *mhdr;
  2585. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2586. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2587. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2588. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2589. msdu_info->exception_fw = 0;
  2590. goto remove_meta_hdr;
  2591. }
  2592. msdu_info->exception_fw = 1;
  2593. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2594. meta_data->host_tx_desc_pool = 1;
  2595. meta_data->update_peer_cache = 1;
  2596. meta_data->learning_frame = 1;
  2597. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2598. meta_data->power = mhdr->power;
  2599. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2600. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2601. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2602. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2603. meta_data->dyn_bw = 1;
  2604. meta_data->valid_pwr = 1;
  2605. meta_data->valid_mcs_mask = 1;
  2606. meta_data->valid_nss_mask = 1;
  2607. meta_data->valid_preamble_type = 1;
  2608. meta_data->valid_retries = 1;
  2609. meta_data->valid_bw_info = 1;
  2610. }
  2611. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2612. meta_data->encrypt_type = 0;
  2613. meta_data->valid_encrypt_type = 1;
  2614. meta_data->learning_frame = 0;
  2615. }
  2616. meta_data->valid_key_flags = 1;
  2617. meta_data->key_flags = (mhdr->keyix & 0x3);
  2618. remove_meta_hdr:
  2619. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2620. dp_tx_err("qdf_nbuf_pull_head failed");
  2621. qdf_nbuf_free(nbuf);
  2622. return NULL;
  2623. }
  2624. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2625. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2626. " tid %d to_fw %d",
  2627. msdu_info->meta_data[0],
  2628. msdu_info->meta_data[1],
  2629. msdu_info->meta_data[2],
  2630. msdu_info->meta_data[3],
  2631. msdu_info->meta_data[4],
  2632. msdu_info->meta_data[5],
  2633. msdu_info->tid, msdu_info->exception_fw);
  2634. return nbuf;
  2635. }
  2636. #else
  2637. static
  2638. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2639. struct dp_tx_msdu_info_s *msdu_info)
  2640. {
  2641. return nbuf;
  2642. }
  2643. #endif
  2644. /**
  2645. * dp_check_exc_metadata() - Checks if parameters are valid
  2646. * @tx_exc: holds all exception path parameters
  2647. *
  2648. * Return: true when all the parameters are valid else false
  2649. *
  2650. */
  2651. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2652. {
  2653. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2654. HTT_INVALID_TID);
  2655. bool invalid_encap_type =
  2656. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2657. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2658. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2659. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2660. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2661. tx_exc->ppdu_cookie == 0);
  2662. if (tx_exc->is_intrabss_fwd)
  2663. return true;
  2664. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2665. invalid_cookie) {
  2666. return false;
  2667. }
  2668. return true;
  2669. }
  2670. #ifdef ATH_SUPPORT_IQUE
  2671. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2672. {
  2673. qdf_ether_header_t *eh;
  2674. /* Mcast to Ucast Conversion*/
  2675. if (qdf_likely(!vdev->mcast_enhancement_en))
  2676. return true;
  2677. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2678. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2679. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2680. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2681. qdf_nbuf_set_next(nbuf, NULL);
  2682. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2683. qdf_nbuf_len(nbuf));
  2684. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2685. QDF_STATUS_SUCCESS) {
  2686. return false;
  2687. }
  2688. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2689. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2690. QDF_STATUS_SUCCESS) {
  2691. return false;
  2692. }
  2693. }
  2694. }
  2695. return true;
  2696. }
  2697. #else
  2698. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2699. {
  2700. return true;
  2701. }
  2702. #endif
  2703. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2704. /**
  2705. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2706. * @vdev: vdev handle
  2707. * @nbuf: skb
  2708. *
  2709. * Return: true if frame is dropped, false otherwise
  2710. */
  2711. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2712. {
  2713. /* Drop tx mcast and WDS Extended feature check */
  2714. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2715. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2716. qdf_nbuf_data(nbuf);
  2717. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2718. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2719. return true;
  2720. }
  2721. }
  2722. return false;
  2723. }
  2724. #else
  2725. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2726. {
  2727. return false;
  2728. }
  2729. #endif
  2730. /**
  2731. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2732. * @nbuf: qdf_nbuf_t
  2733. * @vdev: struct dp_vdev *
  2734. *
  2735. * Allow packet for processing only if it is for peer client which is
  2736. * connected with same vap. Drop packet if client is connected to
  2737. * different vap.
  2738. *
  2739. * Return: QDF_STATUS
  2740. */
  2741. static inline QDF_STATUS
  2742. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2743. {
  2744. struct dp_ast_entry *dst_ast_entry = NULL;
  2745. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2746. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2747. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2748. return QDF_STATUS_SUCCESS;
  2749. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2750. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2751. eh->ether_dhost,
  2752. vdev->vdev_id);
  2753. /* If there is no ast entry, return failure */
  2754. if (qdf_unlikely(!dst_ast_entry)) {
  2755. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2756. return QDF_STATUS_E_FAILURE;
  2757. }
  2758. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2759. return QDF_STATUS_SUCCESS;
  2760. }
  2761. /**
  2762. * dp_tx_nawds_handler() - NAWDS handler
  2763. *
  2764. * @soc: DP soc handle
  2765. * @vdev: DP vdev handle
  2766. * @msdu_info: msdu_info required to create HTT metadata
  2767. * @nbuf: skb
  2768. * @sa_peer_id:
  2769. *
  2770. * This API transfers the multicast frames with the peer id
  2771. * on NAWDS enabled peer.
  2772. *
  2773. * Return: none
  2774. */
  2775. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2776. struct dp_tx_msdu_info_s *msdu_info,
  2777. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2778. {
  2779. struct dp_peer *peer = NULL;
  2780. qdf_nbuf_t nbuf_clone = NULL;
  2781. uint16_t peer_id = DP_INVALID_PEER;
  2782. struct dp_txrx_peer *txrx_peer;
  2783. /* This check avoids pkt forwarding which is entered
  2784. * in the ast table but still doesn't have valid peerid.
  2785. */
  2786. if (sa_peer_id == HTT_INVALID_PEER)
  2787. return;
  2788. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2789. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2790. txrx_peer = dp_get_txrx_peer(peer);
  2791. if (!txrx_peer)
  2792. continue;
  2793. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2794. peer_id = peer->peer_id;
  2795. if (!dp_peer_is_primary_link_peer(peer))
  2796. continue;
  2797. /* In the case of wds ext peer mcast traffic will be
  2798. * sent as part of VLAN interface
  2799. */
  2800. if (dp_peer_is_wds_ext_peer(txrx_peer))
  2801. continue;
  2802. /* Multicast packets needs to be
  2803. * dropped in case of intra bss forwarding
  2804. */
  2805. if (sa_peer_id == txrx_peer->peer_id) {
  2806. dp_tx_debug("multicast packet");
  2807. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2808. tx.nawds_mcast_drop,
  2809. 1);
  2810. continue;
  2811. }
  2812. nbuf_clone = qdf_nbuf_clone(nbuf);
  2813. if (!nbuf_clone) {
  2814. QDF_TRACE(QDF_MODULE_ID_DP,
  2815. QDF_TRACE_LEVEL_ERROR,
  2816. FL("nbuf clone failed"));
  2817. break;
  2818. }
  2819. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2820. msdu_info, peer_id,
  2821. NULL);
  2822. if (nbuf_clone) {
  2823. dp_tx_debug("pkt send failed");
  2824. qdf_nbuf_free(nbuf_clone);
  2825. } else {
  2826. if (peer_id != DP_INVALID_PEER)
  2827. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2828. tx.nawds_mcast,
  2829. 1, qdf_nbuf_len(nbuf));
  2830. }
  2831. }
  2832. }
  2833. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2834. }
  2835. qdf_nbuf_t
  2836. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2837. qdf_nbuf_t nbuf,
  2838. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2839. {
  2840. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2841. struct dp_tx_msdu_info_s msdu_info;
  2842. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2843. DP_MOD_ID_TX_EXCEPTION);
  2844. if (qdf_unlikely(!vdev))
  2845. goto fail;
  2846. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2847. if (!tx_exc_metadata)
  2848. goto fail;
  2849. msdu_info.tid = tx_exc_metadata->tid;
  2850. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2851. QDF_MAC_ADDR_REF(nbuf->data));
  2852. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2853. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2854. dp_tx_err("Invalid parameters in exception path");
  2855. goto fail;
  2856. }
  2857. /* for peer based metadata check if peer is valid */
  2858. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2859. struct dp_peer *peer = NULL;
  2860. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2861. tx_exc_metadata->peer_id,
  2862. DP_MOD_ID_TX_EXCEPTION);
  2863. if (qdf_unlikely(!peer)) {
  2864. DP_STATS_INC(vdev,
  2865. tx_i.dropped.invalid_peer_id_in_exc_path,
  2866. 1);
  2867. goto fail;
  2868. }
  2869. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2870. }
  2871. /* Basic sanity checks for unsupported packets */
  2872. /* MESH mode */
  2873. if (qdf_unlikely(vdev->mesh_vdev)) {
  2874. dp_tx_err("Mesh mode is not supported in exception path");
  2875. goto fail;
  2876. }
  2877. /*
  2878. * Classify the frame and call corresponding
  2879. * "prepare" function which extracts the segment (TSO)
  2880. * and fragmentation information (for TSO , SG, ME, or Raw)
  2881. * into MSDU_INFO structure which is later used to fill
  2882. * SW and HW descriptors.
  2883. */
  2884. if (qdf_nbuf_is_tso(nbuf)) {
  2885. dp_verbose_debug("TSO frame %pK", vdev);
  2886. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2887. qdf_nbuf_len(nbuf));
  2888. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2889. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2890. qdf_nbuf_len(nbuf));
  2891. goto fail;
  2892. }
  2893. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2894. goto send_multiple;
  2895. }
  2896. /* SG */
  2897. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2898. struct dp_tx_seg_info_s seg_info = {0};
  2899. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2900. if (!nbuf)
  2901. goto fail;
  2902. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2903. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2904. qdf_nbuf_len(nbuf));
  2905. goto send_multiple;
  2906. }
  2907. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2908. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2909. qdf_nbuf_len(nbuf));
  2910. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2911. tx_exc_metadata->ppdu_cookie);
  2912. }
  2913. /*
  2914. * Get HW Queue to use for this frame.
  2915. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2916. * dedicated for data and 1 for command.
  2917. * "queue_id" maps to one hardware ring.
  2918. * With each ring, we also associate a unique Tx descriptor pool
  2919. * to minimize lock contention for these resources.
  2920. */
  2921. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2922. /*
  2923. * if the packet is mcast packet send through mlo_macst handler
  2924. * for all prnt_vdevs
  2925. */
  2926. if (soc->arch_ops.dp_tx_mlo_mcast_send) {
  2927. nbuf = soc->arch_ops.dp_tx_mlo_mcast_send(soc, vdev,
  2928. nbuf,
  2929. tx_exc_metadata);
  2930. if (!nbuf)
  2931. goto fail;
  2932. }
  2933. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2934. if (qdf_unlikely(vdev->nawds_enabled)) {
  2935. /*
  2936. * This is a multicast packet
  2937. */
  2938. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2939. tx_exc_metadata->peer_id);
  2940. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2941. 1, qdf_nbuf_len(nbuf));
  2942. }
  2943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2944. DP_INVALID_PEER, NULL);
  2945. } else {
  2946. /*
  2947. * Check exception descriptors
  2948. */
  2949. if (dp_tx_exception_limit_check(vdev))
  2950. goto fail;
  2951. /* Single linear frame */
  2952. /*
  2953. * If nbuf is a simple linear frame, use send_single function to
  2954. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2955. * SRNG. There is no need to setup a MSDU extension descriptor.
  2956. */
  2957. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2958. tx_exc_metadata->peer_id,
  2959. tx_exc_metadata);
  2960. }
  2961. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2962. return nbuf;
  2963. send_multiple:
  2964. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2965. fail:
  2966. if (vdev)
  2967. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2968. dp_verbose_debug("pkt send failed");
  2969. return nbuf;
  2970. }
  2971. qdf_nbuf_t
  2972. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2973. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2974. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2975. {
  2976. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2977. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2978. DP_MOD_ID_TX_EXCEPTION);
  2979. if (qdf_unlikely(!vdev))
  2980. goto fail;
  2981. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2982. == QDF_STATUS_E_FAILURE)) {
  2983. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2984. goto fail;
  2985. }
  2986. /* Unref count as it will again be taken inside dp_tx_exception */
  2987. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2988. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2989. fail:
  2990. if (vdev)
  2991. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2992. dp_verbose_debug("pkt send failed");
  2993. return nbuf;
  2994. }
  2995. #ifdef MESH_MODE_SUPPORT
  2996. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2997. qdf_nbuf_t nbuf)
  2998. {
  2999. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3000. struct meta_hdr_s *mhdr;
  3001. qdf_nbuf_t nbuf_mesh = NULL;
  3002. qdf_nbuf_t nbuf_clone = NULL;
  3003. struct dp_vdev *vdev;
  3004. uint8_t no_enc_frame = 0;
  3005. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3006. if (!nbuf_mesh) {
  3007. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3008. "qdf_nbuf_unshare failed");
  3009. return nbuf;
  3010. }
  3011. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3012. if (!vdev) {
  3013. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3014. "vdev is NULL for vdev_id %d", vdev_id);
  3015. return nbuf;
  3016. }
  3017. nbuf = nbuf_mesh;
  3018. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3019. if ((vdev->sec_type != cdp_sec_type_none) &&
  3020. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3021. no_enc_frame = 1;
  3022. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3023. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3024. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3025. !no_enc_frame) {
  3026. nbuf_clone = qdf_nbuf_clone(nbuf);
  3027. if (!nbuf_clone) {
  3028. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3029. "qdf_nbuf_clone failed");
  3030. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3031. return nbuf;
  3032. }
  3033. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3034. }
  3035. if (nbuf_clone) {
  3036. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3037. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3038. } else {
  3039. qdf_nbuf_free(nbuf_clone);
  3040. }
  3041. }
  3042. if (no_enc_frame)
  3043. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3044. else
  3045. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3046. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3047. if ((!nbuf) && no_enc_frame) {
  3048. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3049. }
  3050. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3051. return nbuf;
  3052. }
  3053. #else
  3054. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3055. qdf_nbuf_t nbuf)
  3056. {
  3057. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3058. }
  3059. #endif
  3060. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3061. static inline
  3062. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3063. {
  3064. if (nbuf) {
  3065. qdf_prefetch(&nbuf->len);
  3066. qdf_prefetch(&nbuf->data);
  3067. }
  3068. }
  3069. #else
  3070. static inline
  3071. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3072. {
  3073. }
  3074. #endif
  3075. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3076. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3077. qdf_nbuf_t nbuf)
  3078. {
  3079. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3080. struct dp_vdev *vdev = NULL;
  3081. vdev = soc->vdev_id_map[vdev_id];
  3082. if (qdf_unlikely(!vdev))
  3083. return nbuf;
  3084. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3085. return nbuf;
  3086. }
  3087. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3088. qdf_nbuf_t nbuf,
  3089. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3090. {
  3091. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3092. }
  3093. #endif
  3094. #ifdef FEATURE_DIRECT_LINK
  3095. /**
  3096. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3097. * @nbuf: skb
  3098. * @vdev: DP vdev handle
  3099. *
  3100. * Return: None
  3101. */
  3102. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3103. {
  3104. if (qdf_unlikely(vdev->to_fw))
  3105. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3106. }
  3107. #else
  3108. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3109. {
  3110. }
  3111. #endif
  3112. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3113. qdf_nbuf_t nbuf)
  3114. {
  3115. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3116. uint16_t peer_id = HTT_INVALID_PEER;
  3117. /*
  3118. * doing a memzero is causing additional function call overhead
  3119. * so doing static stack clearing
  3120. */
  3121. struct dp_tx_msdu_info_s msdu_info = {0};
  3122. struct dp_vdev *vdev = NULL;
  3123. qdf_nbuf_t end_nbuf = NULL;
  3124. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3125. return nbuf;
  3126. /*
  3127. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3128. * this in per packet path.
  3129. *
  3130. * As in this path vdev memory is already protected with netdev
  3131. * tx lock
  3132. */
  3133. vdev = soc->vdev_id_map[vdev_id];
  3134. if (qdf_unlikely(!vdev))
  3135. return nbuf;
  3136. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3137. /*
  3138. * Set Default Host TID value to invalid TID
  3139. * (TID override disabled)
  3140. */
  3141. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3142. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3143. if (qdf_unlikely(vdev->mesh_vdev)) {
  3144. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3145. &msdu_info);
  3146. if (!nbuf_mesh) {
  3147. dp_verbose_debug("Extracting mesh metadata failed");
  3148. return nbuf;
  3149. }
  3150. nbuf = nbuf_mesh;
  3151. }
  3152. /*
  3153. * Get HW Queue to use for this frame.
  3154. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3155. * dedicated for data and 1 for command.
  3156. * "queue_id" maps to one hardware ring.
  3157. * With each ring, we also associate a unique Tx descriptor pool
  3158. * to minimize lock contention for these resources.
  3159. */
  3160. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3161. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3162. 1);
  3163. /*
  3164. * TCL H/W supports 2 DSCP-TID mapping tables.
  3165. * Table 1 - Default DSCP-TID mapping table
  3166. * Table 2 - 1 DSCP-TID override table
  3167. *
  3168. * If we need a different DSCP-TID mapping for this vap,
  3169. * call tid_classify to extract DSCP/ToS from frame and
  3170. * map to a TID and store in msdu_info. This is later used
  3171. * to fill in TCL Input descriptor (per-packet TID override).
  3172. */
  3173. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3174. /*
  3175. * Classify the frame and call corresponding
  3176. * "prepare" function which extracts the segment (TSO)
  3177. * and fragmentation information (for TSO , SG, ME, or Raw)
  3178. * into MSDU_INFO structure which is later used to fill
  3179. * SW and HW descriptors.
  3180. */
  3181. if (qdf_nbuf_is_tso(nbuf)) {
  3182. dp_verbose_debug("TSO frame %pK", vdev);
  3183. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3184. qdf_nbuf_len(nbuf));
  3185. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3186. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3187. qdf_nbuf_len(nbuf));
  3188. return nbuf;
  3189. }
  3190. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3191. goto send_multiple;
  3192. }
  3193. /* SG */
  3194. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3195. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3196. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3197. return nbuf;
  3198. } else {
  3199. struct dp_tx_seg_info_s seg_info = {0};
  3200. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3201. goto send_single;
  3202. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3203. &msdu_info);
  3204. if (!nbuf)
  3205. return NULL;
  3206. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3207. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3208. qdf_nbuf_len(nbuf));
  3209. goto send_multiple;
  3210. }
  3211. }
  3212. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3213. return NULL;
  3214. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3215. return nbuf;
  3216. /* RAW */
  3217. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3218. struct dp_tx_seg_info_s seg_info = {0};
  3219. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3220. if (!nbuf)
  3221. return NULL;
  3222. dp_verbose_debug("Raw frame %pK", vdev);
  3223. goto send_multiple;
  3224. }
  3225. if (qdf_unlikely(vdev->nawds_enabled)) {
  3226. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3227. qdf_nbuf_data(nbuf);
  3228. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3229. uint16_t sa_peer_id = DP_INVALID_PEER;
  3230. if (!soc->ast_offload_support) {
  3231. struct dp_ast_entry *ast_entry = NULL;
  3232. qdf_spin_lock_bh(&soc->ast_lock);
  3233. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3234. (soc,
  3235. (uint8_t *)(eh->ether_shost),
  3236. vdev->pdev->pdev_id);
  3237. if (ast_entry)
  3238. sa_peer_id = ast_entry->peer_id;
  3239. qdf_spin_unlock_bh(&soc->ast_lock);
  3240. }
  3241. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3242. sa_peer_id);
  3243. }
  3244. peer_id = DP_INVALID_PEER;
  3245. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3246. 1, qdf_nbuf_len(nbuf));
  3247. }
  3248. send_single:
  3249. /* Single linear frame */
  3250. /*
  3251. * If nbuf is a simple linear frame, use send_single function to
  3252. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3253. * SRNG. There is no need to setup a MSDU extension descriptor.
  3254. */
  3255. dp_tx_prefetch_nbuf_data(nbuf);
  3256. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3257. peer_id, end_nbuf);
  3258. return nbuf;
  3259. send_multiple:
  3260. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3261. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3262. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3263. return nbuf;
  3264. }
  3265. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3266. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3267. {
  3268. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3269. struct dp_vdev *vdev = NULL;
  3270. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3271. return nbuf;
  3272. /*
  3273. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3274. * this in per packet path.
  3275. *
  3276. * As in this path vdev memory is already protected with netdev
  3277. * tx lock
  3278. */
  3279. vdev = soc->vdev_id_map[vdev_id];
  3280. if (qdf_unlikely(!vdev))
  3281. return nbuf;
  3282. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3283. == QDF_STATUS_E_FAILURE)) {
  3284. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3285. return nbuf;
  3286. }
  3287. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3288. }
  3289. #ifdef UMAC_SUPPORT_PROXY_ARP
  3290. /**
  3291. * dp_tx_proxy_arp() - Tx proxy arp handler
  3292. * @vdev: datapath vdev handle
  3293. * @nbuf: sk buffer
  3294. *
  3295. * Return: status
  3296. */
  3297. static inline
  3298. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3299. {
  3300. if (vdev->osif_proxy_arp)
  3301. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3302. /*
  3303. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3304. * osif_proxy_arp has a valid function pointer assigned
  3305. * to it
  3306. */
  3307. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3308. return QDF_STATUS_NOT_INITIALIZED;
  3309. }
  3310. #else
  3311. static inline
  3312. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3313. {
  3314. return QDF_STATUS_SUCCESS;
  3315. }
  3316. #endif
  3317. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  3318. !defined(CONFIG_MLO_SINGLE_DEV)
  3319. #ifdef WLAN_MCAST_MLO
  3320. static bool
  3321. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3322. struct dp_tx_desc_s *tx_desc,
  3323. qdf_nbuf_t nbuf,
  3324. uint8_t reinject_reason)
  3325. {
  3326. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3327. if (soc->arch_ops.dp_tx_mcast_handler)
  3328. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3329. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3330. return true;
  3331. }
  3332. return false;
  3333. }
  3334. #else /* WLAN_MCAST_MLO */
  3335. static inline bool
  3336. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3337. struct dp_tx_desc_s *tx_desc,
  3338. qdf_nbuf_t nbuf,
  3339. uint8_t reinject_reason)
  3340. {
  3341. return false;
  3342. }
  3343. #endif /* WLAN_MCAST_MLO */
  3344. #else
  3345. static inline bool
  3346. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3347. struct dp_tx_desc_s *tx_desc,
  3348. qdf_nbuf_t nbuf,
  3349. uint8_t reinject_reason)
  3350. {
  3351. return false;
  3352. }
  3353. #endif
  3354. void dp_tx_reinject_handler(struct dp_soc *soc,
  3355. struct dp_vdev *vdev,
  3356. struct dp_tx_desc_s *tx_desc,
  3357. uint8_t *status,
  3358. uint8_t reinject_reason)
  3359. {
  3360. struct dp_peer *peer = NULL;
  3361. uint32_t peer_id = HTT_INVALID_PEER;
  3362. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3363. qdf_nbuf_t nbuf_copy = NULL;
  3364. struct dp_tx_msdu_info_s msdu_info;
  3365. #ifdef WDS_VENDOR_EXTENSION
  3366. int is_mcast = 0, is_ucast = 0;
  3367. int num_peers_3addr = 0;
  3368. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3369. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3370. #endif
  3371. struct dp_txrx_peer *txrx_peer;
  3372. qdf_assert(vdev);
  3373. dp_tx_debug("Tx reinject path");
  3374. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3375. qdf_nbuf_len(tx_desc->nbuf));
  3376. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3377. return;
  3378. #ifdef WDS_VENDOR_EXTENSION
  3379. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3380. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3381. } else {
  3382. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3383. }
  3384. is_ucast = !is_mcast;
  3385. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3386. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3387. txrx_peer = dp_get_txrx_peer(peer);
  3388. if (!txrx_peer || txrx_peer->bss_peer)
  3389. continue;
  3390. /* Detect wds peers that use 3-addr framing for mcast.
  3391. * if there are any, the bss_peer is used to send the
  3392. * the mcast frame using 3-addr format. all wds enabled
  3393. * peers that use 4-addr framing for mcast frames will
  3394. * be duplicated and sent as 4-addr frames below.
  3395. */
  3396. if (!txrx_peer->wds_enabled ||
  3397. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3398. num_peers_3addr = 1;
  3399. break;
  3400. }
  3401. }
  3402. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3403. #endif
  3404. if (qdf_unlikely(vdev->mesh_vdev)) {
  3405. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3406. } else {
  3407. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3408. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3409. txrx_peer = dp_get_txrx_peer(peer);
  3410. if (!txrx_peer)
  3411. continue;
  3412. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3413. #ifdef WDS_VENDOR_EXTENSION
  3414. /*
  3415. * . if 3-addr STA, then send on BSS Peer
  3416. * . if Peer WDS enabled and accept 4-addr mcast,
  3417. * send mcast on that peer only
  3418. * . if Peer WDS enabled and accept 4-addr ucast,
  3419. * send ucast on that peer only
  3420. */
  3421. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3422. (txrx_peer->wds_enabled &&
  3423. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3424. (is_ucast &&
  3425. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3426. #else
  3427. (txrx_peer->bss_peer &&
  3428. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3429. #endif
  3430. peer_id = DP_INVALID_PEER;
  3431. nbuf_copy = qdf_nbuf_copy(nbuf);
  3432. if (!nbuf_copy) {
  3433. dp_tx_debug("nbuf copy failed");
  3434. break;
  3435. }
  3436. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3437. dp_tx_get_queue(vdev, nbuf,
  3438. &msdu_info.tx_queue);
  3439. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3440. nbuf_copy,
  3441. &msdu_info,
  3442. peer_id,
  3443. NULL);
  3444. if (nbuf_copy) {
  3445. dp_tx_debug("pkt send failed");
  3446. qdf_nbuf_free(nbuf_copy);
  3447. }
  3448. }
  3449. }
  3450. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3451. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3452. QDF_DMA_TO_DEVICE, nbuf->len);
  3453. qdf_nbuf_free(nbuf);
  3454. }
  3455. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3456. }
  3457. void dp_tx_inspect_handler(struct dp_soc *soc,
  3458. struct dp_vdev *vdev,
  3459. struct dp_tx_desc_s *tx_desc,
  3460. uint8_t *status)
  3461. {
  3462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3463. "%s Tx inspect path",
  3464. __func__);
  3465. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3466. qdf_nbuf_len(tx_desc->nbuf));
  3467. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3468. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3469. }
  3470. #ifdef MESH_MODE_SUPPORT
  3471. /**
  3472. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3473. * in mesh meta header
  3474. * @tx_desc: software descriptor head pointer
  3475. * @ts: pointer to tx completion stats
  3476. * Return: none
  3477. */
  3478. static
  3479. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3480. struct hal_tx_completion_status *ts)
  3481. {
  3482. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3483. if (!tx_desc->msdu_ext_desc) {
  3484. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3486. "netbuf %pK offset %d",
  3487. netbuf, tx_desc->pkt_offset);
  3488. return;
  3489. }
  3490. }
  3491. }
  3492. #else
  3493. static
  3494. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3495. struct hal_tx_completion_status *ts)
  3496. {
  3497. }
  3498. #endif
  3499. #ifdef CONFIG_SAWF
  3500. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3501. struct dp_vdev *vdev,
  3502. struct dp_txrx_peer *txrx_peer,
  3503. struct dp_tx_desc_s *tx_desc,
  3504. struct hal_tx_completion_status *ts,
  3505. uint8_t tid)
  3506. {
  3507. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3508. ts, tid);
  3509. }
  3510. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3511. uint32_t nw_delay,
  3512. uint32_t sw_delay,
  3513. uint32_t hw_delay)
  3514. {
  3515. dp_peer_tid_delay_avg(tx_delay,
  3516. nw_delay,
  3517. sw_delay,
  3518. hw_delay);
  3519. }
  3520. #else
  3521. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3522. struct dp_vdev *vdev,
  3523. struct dp_txrx_peer *txrx_peer,
  3524. struct dp_tx_desc_s *tx_desc,
  3525. struct hal_tx_completion_status *ts,
  3526. uint8_t tid)
  3527. {
  3528. }
  3529. static inline void
  3530. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3531. uint32_t nw_delay, uint32_t sw_delay,
  3532. uint32_t hw_delay)
  3533. {
  3534. }
  3535. #endif
  3536. #ifdef QCA_PEER_EXT_STATS
  3537. #ifdef WLAN_CONFIG_TX_DELAY
  3538. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3539. struct dp_tx_desc_s *tx_desc,
  3540. struct hal_tx_completion_status *ts,
  3541. struct dp_vdev *vdev)
  3542. {
  3543. struct dp_soc *soc = vdev->pdev->soc;
  3544. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3545. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3546. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3547. if (!ts->valid)
  3548. return;
  3549. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3550. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3551. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3552. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3553. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3554. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3555. &fwhw_transmit_delay))
  3556. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3557. fwhw_transmit_delay);
  3558. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3559. fwhw_transmit_delay);
  3560. }
  3561. #else
  3562. /**
  3563. * dp_tx_compute_tid_delay() - Compute per TID delay
  3564. * @stats: Per TID delay stats
  3565. * @tx_desc: Software Tx descriptor
  3566. * @ts: Tx completion status
  3567. * @vdev: vdev
  3568. *
  3569. * Compute the software enqueue and hw enqueue delays and
  3570. * update the respective histograms
  3571. *
  3572. * Return: void
  3573. */
  3574. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3575. struct dp_tx_desc_s *tx_desc,
  3576. struct hal_tx_completion_status *ts,
  3577. struct dp_vdev *vdev)
  3578. {
  3579. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3580. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3581. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3582. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3583. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3584. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3585. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3586. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3587. timestamp_hw_enqueue);
  3588. /*
  3589. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3590. */
  3591. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3592. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3593. }
  3594. #endif
  3595. /**
  3596. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3597. * @txrx_peer: DP peer context
  3598. * @tx_desc: Tx software descriptor
  3599. * @ts: Tx completion status
  3600. * @ring_id: Rx CPU context ID/CPU_ID
  3601. *
  3602. * Update the peer extended stats. These are enhanced other
  3603. * delay stats per msdu level.
  3604. *
  3605. * Return: void
  3606. */
  3607. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3608. struct dp_tx_desc_s *tx_desc,
  3609. struct hal_tx_completion_status *ts,
  3610. uint8_t ring_id)
  3611. {
  3612. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3613. struct dp_soc *soc = NULL;
  3614. struct dp_peer_delay_stats *delay_stats = NULL;
  3615. uint8_t tid;
  3616. soc = pdev->soc;
  3617. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3618. return;
  3619. if (!txrx_peer->delay_stats)
  3620. return;
  3621. tid = ts->tid;
  3622. delay_stats = txrx_peer->delay_stats;
  3623. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3624. /*
  3625. * For non-TID packets use the TID 9
  3626. */
  3627. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3628. tid = CDP_MAX_DATA_TIDS - 1;
  3629. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3630. tx_desc, ts, txrx_peer->vdev);
  3631. }
  3632. #else
  3633. static inline
  3634. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3635. struct dp_tx_desc_s *tx_desc,
  3636. struct hal_tx_completion_status *ts,
  3637. uint8_t ring_id)
  3638. {
  3639. }
  3640. #endif
  3641. #ifdef WLAN_PEER_JITTER
  3642. /**
  3643. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3644. * @curr_delay: Current delay
  3645. * @prev_delay: Previous delay
  3646. * @avg_jitter: Average Jitter
  3647. * Return: Newly Computed Average Jitter
  3648. */
  3649. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3650. uint32_t prev_delay,
  3651. uint32_t avg_jitter)
  3652. {
  3653. uint32_t curr_jitter;
  3654. int32_t jitter_diff;
  3655. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3656. if (!avg_jitter)
  3657. return curr_jitter;
  3658. jitter_diff = curr_jitter - avg_jitter;
  3659. if (jitter_diff < 0)
  3660. avg_jitter = avg_jitter -
  3661. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3662. else
  3663. avg_jitter = avg_jitter +
  3664. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3665. return avg_jitter;
  3666. }
  3667. /**
  3668. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3669. * @curr_delay: Current delay
  3670. * @avg_delay: Average delay
  3671. * Return: Newly Computed Average Delay
  3672. */
  3673. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3674. uint32_t avg_delay)
  3675. {
  3676. int32_t delay_diff;
  3677. if (!avg_delay)
  3678. return curr_delay;
  3679. delay_diff = curr_delay - avg_delay;
  3680. if (delay_diff < 0)
  3681. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3682. DP_AVG_DELAY_WEIGHT_DENOM);
  3683. else
  3684. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3685. DP_AVG_DELAY_WEIGHT_DENOM);
  3686. return avg_delay;
  3687. }
  3688. #ifdef WLAN_CONFIG_TX_DELAY
  3689. /**
  3690. * dp_tx_compute_cur_delay() - get the current delay
  3691. * @soc: soc handle
  3692. * @vdev: vdev structure for data path state
  3693. * @ts: Tx completion status
  3694. * @curr_delay: current delay
  3695. * @tx_desc: tx descriptor
  3696. * Return: void
  3697. */
  3698. static
  3699. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3700. struct dp_vdev *vdev,
  3701. struct hal_tx_completion_status *ts,
  3702. uint32_t *curr_delay,
  3703. struct dp_tx_desc_s *tx_desc)
  3704. {
  3705. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3706. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3707. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3708. curr_delay);
  3709. return status;
  3710. }
  3711. #else
  3712. static
  3713. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3714. struct dp_vdev *vdev,
  3715. struct hal_tx_completion_status *ts,
  3716. uint32_t *curr_delay,
  3717. struct dp_tx_desc_s *tx_desc)
  3718. {
  3719. int64_t current_timestamp, timestamp_hw_enqueue;
  3720. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3721. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3722. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3723. return QDF_STATUS_SUCCESS;
  3724. }
  3725. #endif
  3726. /**
  3727. * dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3728. * @jitter: per tid per ring jitter stats
  3729. * @ts: Tx completion status
  3730. * @vdev: vdev structure for data path state
  3731. * @tx_desc: tx descriptor
  3732. * Return: void
  3733. */
  3734. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3735. struct hal_tx_completion_status *ts,
  3736. struct dp_vdev *vdev,
  3737. struct dp_tx_desc_s *tx_desc)
  3738. {
  3739. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3740. struct dp_soc *soc = vdev->pdev->soc;
  3741. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3742. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3743. jitter->tx_drop += 1;
  3744. return;
  3745. }
  3746. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3747. tx_desc);
  3748. if (QDF_IS_STATUS_SUCCESS(status)) {
  3749. avg_delay = jitter->tx_avg_delay;
  3750. avg_jitter = jitter->tx_avg_jitter;
  3751. prev_delay = jitter->tx_prev_delay;
  3752. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3753. prev_delay,
  3754. avg_jitter);
  3755. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3756. jitter->tx_avg_delay = avg_delay;
  3757. jitter->tx_avg_jitter = avg_jitter;
  3758. jitter->tx_prev_delay = curr_delay;
  3759. jitter->tx_total_success += 1;
  3760. } else if (status == QDF_STATUS_E_FAILURE) {
  3761. jitter->tx_avg_err += 1;
  3762. }
  3763. }
  3764. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3765. * @txrx_peer: DP peer context
  3766. * @tx_desc: Tx software descriptor
  3767. * @ts: Tx completion status
  3768. * @ring_id: Rx CPU context ID/CPU_ID
  3769. * Return: void
  3770. */
  3771. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3772. struct dp_tx_desc_s *tx_desc,
  3773. struct hal_tx_completion_status *ts,
  3774. uint8_t ring_id)
  3775. {
  3776. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3777. struct dp_soc *soc = pdev->soc;
  3778. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3779. uint8_t tid;
  3780. struct cdp_peer_tid_stats *rx_tid = NULL;
  3781. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3782. return;
  3783. tid = ts->tid;
  3784. jitter_stats = txrx_peer->jitter_stats;
  3785. qdf_assert_always(jitter_stats);
  3786. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3787. /*
  3788. * For non-TID packets use the TID 9
  3789. */
  3790. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3791. tid = CDP_MAX_DATA_TIDS - 1;
  3792. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3793. dp_tx_compute_tid_jitter(rx_tid,
  3794. ts, txrx_peer->vdev, tx_desc);
  3795. }
  3796. #else
  3797. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3798. struct dp_tx_desc_s *tx_desc,
  3799. struct hal_tx_completion_status *ts,
  3800. uint8_t ring_id)
  3801. {
  3802. }
  3803. #endif
  3804. #ifdef HW_TX_DELAY_STATS_ENABLE
  3805. /**
  3806. * dp_update_tx_delay_stats() - update the delay stats
  3807. * @vdev: vdev handle
  3808. * @delay: delay in ms or us based on the flag delay_in_us
  3809. * @tid: tid value
  3810. * @mode: type of tx delay mode
  3811. * @ring_id: ring number
  3812. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3813. *
  3814. * Return: none
  3815. */
  3816. static inline
  3817. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3818. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3819. {
  3820. struct cdp_tid_tx_stats *tstats =
  3821. &vdev->stats.tid_tx_stats[ring_id][tid];
  3822. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3823. delay_in_us);
  3824. }
  3825. #else
  3826. static inline
  3827. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3828. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3829. {
  3830. struct cdp_tid_tx_stats *tstats =
  3831. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3832. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3833. delay_in_us);
  3834. }
  3835. #endif
  3836. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3837. uint8_t tid, uint8_t ring_id)
  3838. {
  3839. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3840. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3841. uint32_t fwhw_transmit_delay_us;
  3842. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3843. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3844. return;
  3845. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3846. fwhw_transmit_delay_us =
  3847. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3848. qdf_ktime_to_us(tx_desc->timestamp);
  3849. /*
  3850. * Delay between packet enqueued to HW and Tx completion in us
  3851. */
  3852. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3853. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3854. ring_id, true);
  3855. /*
  3856. * For MCL, only enqueue to completion delay is required
  3857. * so return if the vdev flag is enabled.
  3858. */
  3859. return;
  3860. }
  3861. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3862. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3863. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3864. timestamp_hw_enqueue);
  3865. if (!timestamp_hw_enqueue)
  3866. return;
  3867. /*
  3868. * Delay between packet enqueued to HW and Tx completion in ms
  3869. */
  3870. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3871. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3872. false);
  3873. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3874. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3875. interframe_delay = (uint32_t)(timestamp_ingress -
  3876. vdev->prev_tx_enq_tstamp);
  3877. /*
  3878. * Delay in software enqueue
  3879. */
  3880. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3881. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3882. false);
  3883. /*
  3884. * Update interframe delay stats calculated at hardstart receive point.
  3885. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3886. * interframe delay will not be calculate correctly for 1st frame.
  3887. * On the other side, this will help in avoiding extra per packet check
  3888. * of !vdev->prev_tx_enq_tstamp.
  3889. */
  3890. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3891. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3892. false);
  3893. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3894. }
  3895. #ifdef DISABLE_DP_STATS
  3896. static
  3897. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3898. struct dp_txrx_peer *txrx_peer)
  3899. {
  3900. }
  3901. #else
  3902. static inline void
  3903. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3904. {
  3905. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3906. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3907. if (subtype != QDF_PROTO_INVALID)
  3908. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3909. 1);
  3910. }
  3911. #endif
  3912. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3913. #ifdef DP_PEER_EXTENDED_API
  3914. static inline uint8_t
  3915. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3916. {
  3917. return txrx_peer->mpdu_retry_threshold;
  3918. }
  3919. #else
  3920. static inline uint8_t
  3921. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3922. {
  3923. return 0;
  3924. }
  3925. #endif
  3926. /**
  3927. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3928. *
  3929. * @ts: Tx compltion status
  3930. * @txrx_peer: datapath txrx_peer handle
  3931. *
  3932. * Return: void
  3933. */
  3934. static inline void
  3935. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3936. struct dp_txrx_peer *txrx_peer)
  3937. {
  3938. uint8_t mcs, pkt_type, dst_mcs_idx;
  3939. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3940. mcs = ts->mcs;
  3941. pkt_type = ts->pkt_type;
  3942. /* do HW to SW pkt type conversion */
  3943. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3944. hal_2_dp_pkt_type_map[pkt_type]);
  3945. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3946. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3947. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3948. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3949. 1);
  3950. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3951. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3952. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3953. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3954. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3955. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3956. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3957. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3958. if (ts->first_msdu) {
  3959. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3960. ts->transmit_cnt > 1);
  3961. if (!retry_threshold)
  3962. return;
  3963. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3964. qdf_do_div(ts->transmit_cnt,
  3965. retry_threshold),
  3966. ts->transmit_cnt > retry_threshold);
  3967. }
  3968. }
  3969. #else
  3970. static inline void
  3971. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3972. struct dp_txrx_peer *txrx_peer)
  3973. {
  3974. }
  3975. #endif
  3976. /**
  3977. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3978. * per wbm ring
  3979. *
  3980. * @tx_desc: software descriptor head pointer
  3981. * @ts: Tx completion status
  3982. * @txrx_peer: peer handle
  3983. * @ring_id: ring number
  3984. *
  3985. * Return: None
  3986. */
  3987. static inline void
  3988. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3989. struct hal_tx_completion_status *ts,
  3990. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3991. {
  3992. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3993. uint8_t tid = ts->tid;
  3994. uint32_t length;
  3995. struct cdp_tid_tx_stats *tid_stats;
  3996. if (!pdev)
  3997. return;
  3998. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3999. tid = CDP_MAX_DATA_TIDS - 1;
  4000. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4001. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4002. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4003. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4004. return;
  4005. }
  4006. length = qdf_nbuf_len(tx_desc->nbuf);
  4007. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4008. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4009. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4010. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4011. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4012. tid_stats->tqm_status_cnt[ts->status]++;
  4013. }
  4014. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4015. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4016. ts->transmit_cnt > 1);
  4017. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4018. 1, ts->transmit_cnt > 2);
  4019. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4020. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4021. ts->msdu_part_of_amsdu);
  4022. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4023. !ts->msdu_part_of_amsdu);
  4024. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4025. qdf_system_ticks();
  4026. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4027. return;
  4028. }
  4029. /*
  4030. * tx_failed is ideally supposed to be updated from HTT ppdu
  4031. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4032. * hw limitation there are no completions for failed cases.
  4033. * Hence updating tx_failed from data path. Please note that
  4034. * if tx_failed is fixed to be from ppdu, then this has to be
  4035. * removed
  4036. */
  4037. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4038. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4039. ts->transmit_cnt > DP_RETRY_COUNT);
  4040. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4041. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4042. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4043. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4044. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4045. length);
  4046. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4047. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4048. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4049. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4050. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4051. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4052. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4053. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4054. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4055. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4056. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4057. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4058. tx.dropped.fw_rem_queue_disable, 1);
  4059. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4060. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4061. tx.dropped.fw_rem_no_match, 1);
  4062. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4063. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4064. tx.dropped.drop_threshold, 1);
  4065. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4066. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4067. tx.dropped.drop_link_desc_na, 1);
  4068. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4069. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4070. tx.dropped.invalid_drop, 1);
  4071. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4072. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4073. tx.dropped.mcast_vdev_drop, 1);
  4074. } else {
  4075. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4076. }
  4077. }
  4078. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4079. /**
  4080. * dp_tx_flow_pool_lock() - take flow pool lock
  4081. * @soc: core txrx main context
  4082. * @tx_desc: tx desc
  4083. *
  4084. * Return: None
  4085. */
  4086. static inline
  4087. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4088. struct dp_tx_desc_s *tx_desc)
  4089. {
  4090. struct dp_tx_desc_pool_s *pool;
  4091. uint8_t desc_pool_id;
  4092. desc_pool_id = tx_desc->pool_id;
  4093. pool = &soc->tx_desc[desc_pool_id];
  4094. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4095. }
  4096. /**
  4097. * dp_tx_flow_pool_unlock() - release flow pool lock
  4098. * @soc: core txrx main context
  4099. * @tx_desc: tx desc
  4100. *
  4101. * Return: None
  4102. */
  4103. static inline
  4104. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4105. struct dp_tx_desc_s *tx_desc)
  4106. {
  4107. struct dp_tx_desc_pool_s *pool;
  4108. uint8_t desc_pool_id;
  4109. desc_pool_id = tx_desc->pool_id;
  4110. pool = &soc->tx_desc[desc_pool_id];
  4111. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4112. }
  4113. #else
  4114. static inline
  4115. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4116. {
  4117. }
  4118. static inline
  4119. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4120. {
  4121. }
  4122. #endif
  4123. /**
  4124. * dp_tx_notify_completion() - Notify tx completion for this desc
  4125. * @soc: core txrx main context
  4126. * @vdev: datapath vdev handle
  4127. * @tx_desc: tx desc
  4128. * @netbuf: buffer
  4129. * @status: tx status
  4130. *
  4131. * Return: none
  4132. */
  4133. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4134. struct dp_vdev *vdev,
  4135. struct dp_tx_desc_s *tx_desc,
  4136. qdf_nbuf_t netbuf,
  4137. uint8_t status)
  4138. {
  4139. void *osif_dev;
  4140. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4141. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4142. qdf_assert(tx_desc);
  4143. if (!vdev ||
  4144. !vdev->osif_vdev) {
  4145. return;
  4146. }
  4147. osif_dev = vdev->osif_vdev;
  4148. tx_compl_cbk = vdev->tx_comp;
  4149. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4150. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4151. if (tx_compl_cbk)
  4152. tx_compl_cbk(netbuf, osif_dev, flag);
  4153. }
  4154. /**
  4155. * dp_tx_sojourn_stats_process() - Collect sojourn stats
  4156. * @pdev: pdev handle
  4157. * @txrx_peer: DP peer context
  4158. * @tid: tid value
  4159. * @txdesc_ts: timestamp from txdesc
  4160. * @ppdu_id: ppdu id
  4161. *
  4162. * Return: none
  4163. */
  4164. #ifdef FEATURE_PERPKT_INFO
  4165. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4166. struct dp_txrx_peer *txrx_peer,
  4167. uint8_t tid,
  4168. uint64_t txdesc_ts,
  4169. uint32_t ppdu_id)
  4170. {
  4171. uint64_t delta_ms;
  4172. struct cdp_tx_sojourn_stats *sojourn_stats;
  4173. struct dp_peer *primary_link_peer = NULL;
  4174. struct dp_soc *link_peer_soc = NULL;
  4175. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4176. return;
  4177. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4178. tid >= CDP_DATA_TID_MAX))
  4179. return;
  4180. if (qdf_unlikely(!pdev->sojourn_buf))
  4181. return;
  4182. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4183. txrx_peer->peer_id,
  4184. DP_MOD_ID_TX_COMP);
  4185. if (qdf_unlikely(!primary_link_peer))
  4186. return;
  4187. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4188. qdf_nbuf_data(pdev->sojourn_buf);
  4189. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4190. sojourn_stats->cookie = (void *)
  4191. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4192. primary_link_peer);
  4193. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4194. txdesc_ts;
  4195. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4196. delta_ms);
  4197. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4198. sojourn_stats->num_msdus[tid] = 1;
  4199. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4200. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4201. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4202. pdev->sojourn_buf, HTT_INVALID_PEER,
  4203. WDI_NO_VAL, pdev->pdev_id);
  4204. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4205. sojourn_stats->num_msdus[tid] = 0;
  4206. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4207. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4208. }
  4209. #else
  4210. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4211. struct dp_txrx_peer *txrx_peer,
  4212. uint8_t tid,
  4213. uint64_t txdesc_ts,
  4214. uint32_t ppdu_id)
  4215. {
  4216. }
  4217. #endif
  4218. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4219. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4220. struct dp_tx_desc_s *desc,
  4221. struct hal_tx_completion_status *ts)
  4222. {
  4223. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4224. desc, ts->peer_id,
  4225. WDI_NO_VAL, desc->pdev->pdev_id);
  4226. }
  4227. #endif
  4228. void
  4229. dp_tx_comp_process_desc(struct dp_soc *soc,
  4230. struct dp_tx_desc_s *desc,
  4231. struct hal_tx_completion_status *ts,
  4232. struct dp_txrx_peer *txrx_peer)
  4233. {
  4234. uint64_t time_latency = 0;
  4235. uint16_t peer_id = DP_INVALID_PEER_ID;
  4236. /*
  4237. * m_copy/tx_capture modes are not supported for
  4238. * scatter gather packets
  4239. */
  4240. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4241. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4242. qdf_ktime_to_ms(desc->timestamp));
  4243. }
  4244. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4245. if (dp_tx_pkt_tracepoints_enabled())
  4246. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4247. desc->msdu_ext_desc ?
  4248. desc->msdu_ext_desc->tso_desc : NULL,
  4249. qdf_ktime_to_ms(desc->timestamp));
  4250. if (!(desc->msdu_ext_desc)) {
  4251. dp_tx_enh_unmap(soc, desc);
  4252. if (txrx_peer)
  4253. peer_id = txrx_peer->peer_id;
  4254. if (QDF_STATUS_SUCCESS ==
  4255. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4256. return;
  4257. }
  4258. if (QDF_STATUS_SUCCESS ==
  4259. dp_get_completion_indication_for_stack(soc,
  4260. desc->pdev,
  4261. txrx_peer, ts,
  4262. desc->nbuf,
  4263. time_latency)) {
  4264. dp_send_completion_to_stack(soc,
  4265. desc->pdev,
  4266. ts->peer_id,
  4267. ts->ppdu_id,
  4268. desc->nbuf);
  4269. return;
  4270. }
  4271. }
  4272. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4273. dp_tx_comp_free_buf(soc, desc, false);
  4274. }
  4275. #ifdef DISABLE_DP_STATS
  4276. /**
  4277. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4278. * @soc: core txrx main context
  4279. * @vdev: virtual device instance
  4280. * @tx_desc: tx desc
  4281. * @status: tx status
  4282. *
  4283. * Return: none
  4284. */
  4285. static inline
  4286. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4287. struct dp_vdev *vdev,
  4288. struct dp_tx_desc_s *tx_desc,
  4289. uint8_t status)
  4290. {
  4291. }
  4292. #else
  4293. static inline
  4294. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4295. struct dp_vdev *vdev,
  4296. struct dp_tx_desc_s *tx_desc,
  4297. uint8_t status)
  4298. {
  4299. void *osif_dev;
  4300. ol_txrx_stats_rx_fp stats_cbk;
  4301. uint8_t pkt_type;
  4302. qdf_assert(tx_desc);
  4303. if (!vdev ||
  4304. !vdev->osif_vdev ||
  4305. !vdev->stats_cb)
  4306. return;
  4307. osif_dev = vdev->osif_vdev;
  4308. stats_cbk = vdev->stats_cb;
  4309. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4310. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4311. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4312. &pkt_type);
  4313. }
  4314. #endif
  4315. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4316. /* Mask for bit29 ~ bit31 */
  4317. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4318. /* Timestamp value (unit us) if bit29 is set */
  4319. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4320. /**
  4321. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4322. * @ack_ts: OTA ack timestamp, unit us.
  4323. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4324. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4325. *
  4326. * this function will restore the bit29 ~ bit31 3 bits value for
  4327. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4328. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4329. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4330. *
  4331. * Return: the adjusted buffer_timestamp value
  4332. */
  4333. static inline
  4334. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4335. uint32_t enqueue_ts,
  4336. uint32_t base_delta_ts)
  4337. {
  4338. uint32_t ack_buffer_ts;
  4339. uint32_t ack_buffer_ts_bit29_31;
  4340. uint32_t adjusted_enqueue_ts;
  4341. /* corresponding buffer_timestamp value when receive OTA Ack */
  4342. ack_buffer_ts = ack_ts - base_delta_ts;
  4343. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4344. /* restore the bit29 ~ bit31 value */
  4345. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4346. /*
  4347. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4348. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4349. * should not be marked, otherwise extra 0x20000000 us is added to
  4350. * enqueue_ts.
  4351. */
  4352. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4353. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4354. return adjusted_enqueue_ts;
  4355. }
  4356. QDF_STATUS
  4357. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4358. uint32_t delta_tsf,
  4359. uint32_t *delay_us)
  4360. {
  4361. uint32_t buffer_ts;
  4362. uint32_t delay;
  4363. if (!delay_us)
  4364. return QDF_STATUS_E_INVAL;
  4365. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4366. if (!ts->valid)
  4367. return QDF_STATUS_E_INVAL;
  4368. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4369. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4370. * valid up to 29 bits.
  4371. */
  4372. buffer_ts = ts->buffer_timestamp << 10;
  4373. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4374. buffer_ts, delta_tsf);
  4375. delay = ts->tsf - buffer_ts - delta_tsf;
  4376. if (qdf_unlikely(delay & 0x80000000)) {
  4377. dp_err_rl("delay = 0x%x (-ve)\n"
  4378. "release_src = %d\n"
  4379. "ppdu_id = 0x%x\n"
  4380. "peer_id = 0x%x\n"
  4381. "tid = 0x%x\n"
  4382. "release_reason = %d\n"
  4383. "tsf = %u (0x%x)\n"
  4384. "buffer_timestamp = %u (0x%x)\n"
  4385. "delta_tsf = %u (0x%x)\n",
  4386. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4387. ts->tid, ts->status, ts->tsf, ts->tsf,
  4388. ts->buffer_timestamp, ts->buffer_timestamp,
  4389. delta_tsf, delta_tsf);
  4390. delay = 0;
  4391. goto end;
  4392. }
  4393. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4394. if (delay > 0x1000000) {
  4395. dp_info_rl("----------------------\n"
  4396. "Tx completion status:\n"
  4397. "----------------------\n"
  4398. "release_src = %d\n"
  4399. "ppdu_id = 0x%x\n"
  4400. "release_reason = %d\n"
  4401. "tsf = %u (0x%x)\n"
  4402. "buffer_timestamp = %u (0x%x)\n"
  4403. "delta_tsf = %u (0x%x)\n",
  4404. ts->release_src, ts->ppdu_id, ts->status,
  4405. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4406. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4407. return QDF_STATUS_E_FAILURE;
  4408. }
  4409. end:
  4410. *delay_us = delay;
  4411. return QDF_STATUS_SUCCESS;
  4412. }
  4413. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4414. uint32_t delta_tsf)
  4415. {
  4416. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4417. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4418. DP_MOD_ID_CDP);
  4419. if (!vdev) {
  4420. dp_err_rl("vdev %d does not exist", vdev_id);
  4421. return;
  4422. }
  4423. vdev->delta_tsf = delta_tsf;
  4424. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4425. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4426. }
  4427. #endif
  4428. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4429. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4430. uint8_t vdev_id, bool enable)
  4431. {
  4432. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4433. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4434. DP_MOD_ID_CDP);
  4435. if (!vdev) {
  4436. dp_err_rl("vdev %d does not exist", vdev_id);
  4437. return QDF_STATUS_E_FAILURE;
  4438. }
  4439. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4440. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4441. return QDF_STATUS_SUCCESS;
  4442. }
  4443. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4444. uint32_t *val)
  4445. {
  4446. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4447. struct dp_vdev *vdev;
  4448. uint32_t delay_accum;
  4449. uint32_t pkts_accum;
  4450. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4451. if (!vdev) {
  4452. dp_err_rl("vdev %d does not exist", vdev_id);
  4453. return QDF_STATUS_E_FAILURE;
  4454. }
  4455. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4456. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4457. return QDF_STATUS_E_FAILURE;
  4458. }
  4459. /* Average uplink delay based on current accumulated values */
  4460. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4461. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4462. *val = delay_accum / pkts_accum;
  4463. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4464. delay_accum, pkts_accum);
  4465. /* Reset accumulated values to 0 */
  4466. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4467. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4468. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4469. return QDF_STATUS_SUCCESS;
  4470. }
  4471. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4472. struct hal_tx_completion_status *ts)
  4473. {
  4474. uint32_t ul_delay;
  4475. if (qdf_unlikely(!vdev)) {
  4476. dp_info_rl("vdev is null or delete in progress");
  4477. return;
  4478. }
  4479. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4480. return;
  4481. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4482. vdev->delta_tsf,
  4483. &ul_delay)))
  4484. return;
  4485. ul_delay /= 1000; /* in unit of ms */
  4486. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4487. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4488. }
  4489. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4490. static inline
  4491. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4492. struct hal_tx_completion_status *ts)
  4493. {
  4494. }
  4495. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4496. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4497. struct dp_tx_desc_s *tx_desc,
  4498. struct hal_tx_completion_status *ts,
  4499. struct dp_txrx_peer *txrx_peer,
  4500. uint8_t ring_id)
  4501. {
  4502. uint32_t length;
  4503. qdf_ether_header_t *eh;
  4504. struct dp_vdev *vdev = NULL;
  4505. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4506. enum qdf_dp_tx_rx_status dp_status;
  4507. if (!nbuf) {
  4508. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4509. goto out;
  4510. }
  4511. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4512. length = dp_tx_get_pkt_len(tx_desc);
  4513. dp_status = dp_tx_hw_to_qdf(ts->status);
  4514. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4515. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4516. QDF_TRACE_DEFAULT_PDEV_ID,
  4517. qdf_nbuf_data_addr(nbuf),
  4518. sizeof(qdf_nbuf_data(nbuf)),
  4519. tx_desc->id, ts->status, dp_status));
  4520. dp_tx_comp_debug("-------------------- \n"
  4521. "Tx Completion Stats: \n"
  4522. "-------------------- \n"
  4523. "ack_frame_rssi = %d \n"
  4524. "first_msdu = %d \n"
  4525. "last_msdu = %d \n"
  4526. "msdu_part_of_amsdu = %d \n"
  4527. "rate_stats valid = %d \n"
  4528. "bw = %d \n"
  4529. "pkt_type = %d \n"
  4530. "stbc = %d \n"
  4531. "ldpc = %d \n"
  4532. "sgi = %d \n"
  4533. "mcs = %d \n"
  4534. "ofdma = %d \n"
  4535. "tones_in_ru = %d \n"
  4536. "tsf = %d \n"
  4537. "ppdu_id = %d \n"
  4538. "transmit_cnt = %d \n"
  4539. "tid = %d \n"
  4540. "peer_id = %d\n"
  4541. "tx_status = %d\n",
  4542. ts->ack_frame_rssi, ts->first_msdu,
  4543. ts->last_msdu, ts->msdu_part_of_amsdu,
  4544. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4545. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4546. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4547. ts->transmit_cnt, ts->tid, ts->peer_id,
  4548. ts->status);
  4549. /* Update SoC level stats */
  4550. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4551. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4552. if (!txrx_peer) {
  4553. dp_info_rl("peer is null or deletion in progress");
  4554. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4555. goto out;
  4556. }
  4557. vdev = txrx_peer->vdev;
  4558. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4559. dp_tx_update_uplink_delay(soc, vdev, ts);
  4560. /* check tx complete notification */
  4561. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4562. dp_tx_notify_completion(soc, vdev, tx_desc,
  4563. nbuf, ts->status);
  4564. /* Update per-packet stats for mesh mode */
  4565. if (qdf_unlikely(vdev->mesh_vdev) &&
  4566. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4567. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4568. /* Update peer level stats */
  4569. if (qdf_unlikely(txrx_peer->bss_peer &&
  4570. vdev->opmode == wlan_op_mode_ap)) {
  4571. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4572. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4573. length);
  4574. if (txrx_peer->vdev->tx_encap_type ==
  4575. htt_cmn_pkt_type_ethernet &&
  4576. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4577. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4578. tx.bcast, 1,
  4579. length);
  4580. }
  4581. }
  4582. } else {
  4583. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4584. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4585. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4586. 1, length);
  4587. if (qdf_unlikely(txrx_peer->in_twt)) {
  4588. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4589. tx.tx_success_twt,
  4590. 1, length);
  4591. }
  4592. }
  4593. }
  4594. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4595. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4596. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4597. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4598. ts, ts->tid);
  4599. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4600. #ifdef QCA_SUPPORT_RDK_STATS
  4601. if (soc->peerstats_enabled)
  4602. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4603. qdf_ktime_to_ms(tx_desc->timestamp),
  4604. ts->ppdu_id);
  4605. #endif
  4606. out:
  4607. return;
  4608. }
  4609. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4610. defined(QCA_ENHANCED_STATS_SUPPORT)
  4611. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4612. uint32_t length, uint8_t tx_status,
  4613. bool update)
  4614. {
  4615. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4616. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4617. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4618. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4619. }
  4620. }
  4621. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4622. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4623. uint32_t length, uint8_t tx_status,
  4624. bool update)
  4625. {
  4626. if (!txrx_peer->hw_txrx_stats_en) {
  4627. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4628. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4629. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4630. }
  4631. }
  4632. #else
  4633. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4634. uint32_t length, uint8_t tx_status,
  4635. bool update)
  4636. {
  4637. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4638. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4639. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4640. }
  4641. #endif
  4642. /**
  4643. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4644. * @next: descriptor of the nrxt buffer
  4645. *
  4646. * Return: none
  4647. */
  4648. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4649. static inline
  4650. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4651. {
  4652. qdf_nbuf_t nbuf = NULL;
  4653. if (next)
  4654. nbuf = next->nbuf;
  4655. if (nbuf)
  4656. qdf_prefetch(nbuf);
  4657. }
  4658. #else
  4659. static inline
  4660. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4661. {
  4662. }
  4663. #endif
  4664. /**
  4665. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4666. * @soc: core txrx main context
  4667. * @desc: software descriptor
  4668. *
  4669. * Return: true when packet is reinjected
  4670. */
  4671. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4672. defined(WLAN_MCAST_MLO) && !defined(CONFIG_MLO_SINGLE_DEV)
  4673. static inline bool
  4674. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4675. {
  4676. struct dp_vdev *vdev = NULL;
  4677. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4678. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4679. !soc->arch_ops.dp_tx_is_mcast_primary)
  4680. return false;
  4681. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4682. DP_MOD_ID_REINJECT);
  4683. if (qdf_unlikely(!vdev)) {
  4684. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4685. desc->id);
  4686. return false;
  4687. }
  4688. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4689. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4690. return false;
  4691. }
  4692. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4693. qdf_nbuf_len(desc->nbuf));
  4694. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4695. dp_tx_desc_release(desc, desc->pool_id);
  4696. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4697. return true;
  4698. }
  4699. return false;
  4700. }
  4701. #else
  4702. static inline bool
  4703. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4704. {
  4705. return false;
  4706. }
  4707. #endif
  4708. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4709. static inline void
  4710. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4711. {
  4712. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4713. }
  4714. static inline void
  4715. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4716. struct dp_tx_desc_s *desc)
  4717. {
  4718. qdf_nbuf_t nbuf = NULL;
  4719. nbuf = desc->nbuf;
  4720. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4721. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4722. else
  4723. qdf_nbuf_free(nbuf);
  4724. }
  4725. static inline void
  4726. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4727. qdf_nbuf_t nbuf)
  4728. {
  4729. if (!nbuf)
  4730. return;
  4731. if (nbuf->is_from_recycler)
  4732. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4733. else
  4734. qdf_nbuf_free(nbuf);
  4735. }
  4736. static inline void
  4737. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4738. {
  4739. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4740. }
  4741. #else
  4742. static inline void
  4743. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4744. {
  4745. }
  4746. static inline void
  4747. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4748. struct dp_tx_desc_s *desc)
  4749. {
  4750. qdf_nbuf_free(desc->nbuf);
  4751. }
  4752. static inline void
  4753. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4754. qdf_nbuf_t nbuf)
  4755. {
  4756. qdf_nbuf_free(nbuf);
  4757. }
  4758. static inline void
  4759. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4760. {
  4761. }
  4762. #endif
  4763. void
  4764. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4765. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4766. {
  4767. struct dp_tx_desc_s *desc;
  4768. struct dp_tx_desc_s *next;
  4769. struct hal_tx_completion_status ts;
  4770. struct dp_txrx_peer *txrx_peer = NULL;
  4771. uint16_t peer_id = DP_INVALID_PEER;
  4772. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4773. qdf_nbuf_queue_head_t h;
  4774. desc = comp_head;
  4775. dp_tx_nbuf_queue_head_init(&h);
  4776. while (desc) {
  4777. next = desc->next;
  4778. dp_tx_prefetch_next_nbuf_data(next);
  4779. if (peer_id != desc->peer_id) {
  4780. if (txrx_peer)
  4781. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4782. DP_MOD_ID_TX_COMP);
  4783. peer_id = desc->peer_id;
  4784. txrx_peer =
  4785. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4786. &txrx_ref_handle,
  4787. DP_MOD_ID_TX_COMP);
  4788. }
  4789. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4790. desc = next;
  4791. continue;
  4792. }
  4793. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4794. qdf_nbuf_t nbuf;
  4795. if (qdf_likely(txrx_peer))
  4796. dp_tx_update_peer_basic_stats(txrx_peer,
  4797. desc->length,
  4798. desc->tx_status,
  4799. false);
  4800. nbuf = dp_ppeds_tx_desc_free(soc, desc);
  4801. dp_tx_nbuf_dev_queue_free_no_flag(&h, nbuf);
  4802. desc = next;
  4803. continue;
  4804. }
  4805. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4806. struct dp_pdev *pdev = desc->pdev;
  4807. if (qdf_likely(txrx_peer))
  4808. dp_tx_update_peer_basic_stats(txrx_peer,
  4809. desc->length,
  4810. desc->tx_status,
  4811. false);
  4812. qdf_assert(pdev);
  4813. dp_tx_outstanding_dec(pdev);
  4814. /*
  4815. * Calling a QDF WRAPPER here is creating significant
  4816. * performance impact so avoided the wrapper call here
  4817. */
  4818. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4819. desc->id, DP_TX_COMP_UNMAP);
  4820. dp_tx_nbuf_unmap(soc, desc);
  4821. dp_tx_nbuf_dev_queue_free(&h, desc);
  4822. dp_tx_desc_free(soc, desc, desc->pool_id);
  4823. desc = next;
  4824. continue;
  4825. }
  4826. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4827. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4828. ring_id);
  4829. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4830. dp_tx_desc_release(desc, desc->pool_id);
  4831. desc = next;
  4832. }
  4833. dp_tx_nbuf_dev_kfree_list(&h);
  4834. if (txrx_peer)
  4835. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4836. }
  4837. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4838. static inline
  4839. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4840. int max_reap_limit)
  4841. {
  4842. bool limit_hit = false;
  4843. limit_hit =
  4844. (num_reaped >= max_reap_limit) ? true : false;
  4845. if (limit_hit)
  4846. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4847. return limit_hit;
  4848. }
  4849. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4850. {
  4851. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4852. }
  4853. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4854. {
  4855. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4856. return cfg->tx_comp_loop_pkt_limit;
  4857. }
  4858. #else
  4859. static inline
  4860. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4861. int max_reap_limit)
  4862. {
  4863. return false;
  4864. }
  4865. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4866. {
  4867. return false;
  4868. }
  4869. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4870. {
  4871. return 0;
  4872. }
  4873. #endif
  4874. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4875. static inline int
  4876. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4877. int *max_reap_limit)
  4878. {
  4879. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4880. max_reap_limit);
  4881. }
  4882. #else
  4883. static inline int
  4884. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4885. int *max_reap_limit)
  4886. {
  4887. return 0;
  4888. }
  4889. #endif
  4890. #ifdef DP_TX_TRACKING
  4891. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4892. {
  4893. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4894. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4895. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4896. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4897. }
  4898. }
  4899. #endif
  4900. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4901. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4902. uint32_t quota)
  4903. {
  4904. void *tx_comp_hal_desc;
  4905. void *last_prefetched_hw_desc = NULL;
  4906. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4907. hal_soc_handle_t hal_soc;
  4908. uint8_t buffer_src;
  4909. struct dp_tx_desc_s *tx_desc = NULL;
  4910. struct dp_tx_desc_s *head_desc = NULL;
  4911. struct dp_tx_desc_s *tail_desc = NULL;
  4912. uint32_t num_processed = 0;
  4913. uint32_t count;
  4914. uint32_t num_avail_for_reap = 0;
  4915. bool force_break = false;
  4916. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4917. int max_reap_limit, ring_near_full;
  4918. uint32_t num_entries;
  4919. DP_HIST_INIT();
  4920. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  4921. more_data:
  4922. hal_soc = soc->hal_soc;
  4923. /* Re-initialize local variables to be re-used */
  4924. head_desc = NULL;
  4925. tail_desc = NULL;
  4926. count = 0;
  4927. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4928. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4929. &max_reap_limit);
  4930. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4931. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4932. return 0;
  4933. }
  4934. if (!num_avail_for_reap)
  4935. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  4936. hal_ring_hdl, 0);
  4937. if (num_avail_for_reap >= quota)
  4938. num_avail_for_reap = quota;
  4939. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4940. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4941. hal_ring_hdl,
  4942. num_avail_for_reap);
  4943. /* Find head descriptor from completion ring */
  4944. while (qdf_likely(num_avail_for_reap--)) {
  4945. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4946. if (qdf_unlikely(!tx_comp_hal_desc))
  4947. break;
  4948. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4949. tx_comp_hal_desc);
  4950. /* If this buffer was not released by TQM or FW, then it is not
  4951. * Tx completion indication, assert */
  4952. if (qdf_unlikely(buffer_src !=
  4953. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4954. (qdf_unlikely(buffer_src !=
  4955. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4956. uint8_t wbm_internal_error;
  4957. dp_err_rl(
  4958. "Tx comp release_src != TQM | FW but from %d",
  4959. buffer_src);
  4960. hal_dump_comp_desc(tx_comp_hal_desc);
  4961. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4962. /* When WBM sees NULL buffer_addr_info in any of
  4963. * ingress rings it sends an error indication,
  4964. * with wbm_internal_error=1, to a specific ring.
  4965. * The WBM2SW ring used to indicate these errors is
  4966. * fixed in HW, and that ring is being used as Tx
  4967. * completion ring. These errors are not related to
  4968. * Tx completions, and should just be ignored
  4969. */
  4970. wbm_internal_error = hal_get_wbm_internal_error(
  4971. hal_soc,
  4972. tx_comp_hal_desc);
  4973. if (wbm_internal_error) {
  4974. dp_err_rl("Tx comp wbm_internal_error!!");
  4975. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4976. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4977. buffer_src)
  4978. dp_handle_wbm_internal_error(
  4979. soc,
  4980. tx_comp_hal_desc,
  4981. hal_tx_comp_get_buffer_type(
  4982. tx_comp_hal_desc));
  4983. } else {
  4984. dp_err_rl("Tx comp wbm_internal_error false");
  4985. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4986. }
  4987. continue;
  4988. }
  4989. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4990. tx_comp_hal_desc,
  4991. &tx_desc);
  4992. if (qdf_unlikely(!tx_desc)) {
  4993. dp_err("unable to retrieve tx_desc!");
  4994. hal_dump_comp_desc(tx_comp_hal_desc);
  4995. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  4996. QDF_BUG(0);
  4997. continue;
  4998. }
  4999. tx_desc->buffer_src = buffer_src;
  5000. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5001. goto add_to_pool2;
  5002. /*
  5003. * If the release source is FW, process the HTT status
  5004. */
  5005. if (qdf_unlikely(buffer_src ==
  5006. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5007. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5008. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5009. htt_tx_status);
  5010. /* Collect hw completion contents */
  5011. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5012. &tx_desc->comp, 1);
  5013. soc->arch_ops.dp_tx_process_htt_completion(
  5014. soc,
  5015. tx_desc,
  5016. htt_tx_status,
  5017. ring_id);
  5018. } else {
  5019. tx_desc->tx_status =
  5020. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5021. tx_desc->buffer_src = buffer_src;
  5022. /*
  5023. * If the fast completion mode is enabled extended
  5024. * metadata from descriptor is not copied
  5025. */
  5026. if (qdf_likely(tx_desc->flags &
  5027. DP_TX_DESC_FLAG_SIMPLE))
  5028. goto add_to_pool;
  5029. /*
  5030. * If the descriptor is already freed in vdev_detach,
  5031. * continue to next descriptor
  5032. */
  5033. if (qdf_unlikely
  5034. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5035. !tx_desc->flags)) {
  5036. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5037. tx_desc->id);
  5038. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5039. dp_tx_desc_check_corruption(tx_desc);
  5040. continue;
  5041. }
  5042. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5043. dp_tx_comp_info_rl("pdev in down state %d",
  5044. tx_desc->id);
  5045. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5046. dp_tx_comp_free_buf(soc, tx_desc, false);
  5047. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5048. goto next_desc;
  5049. }
  5050. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5051. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5052. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5053. tx_desc->flags, tx_desc->id);
  5054. qdf_assert_always(0);
  5055. }
  5056. /* Collect hw completion contents */
  5057. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5058. &tx_desc->comp, 1);
  5059. add_to_pool:
  5060. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5061. add_to_pool2:
  5062. /* First ring descriptor on the cycle */
  5063. if (!head_desc) {
  5064. head_desc = tx_desc;
  5065. tail_desc = tx_desc;
  5066. }
  5067. tail_desc->next = tx_desc;
  5068. tx_desc->next = NULL;
  5069. tail_desc = tx_desc;
  5070. }
  5071. next_desc:
  5072. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5073. /*
  5074. * Processed packet count is more than given quota
  5075. * stop to processing
  5076. */
  5077. count++;
  5078. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5079. num_avail_for_reap,
  5080. hal_ring_hdl,
  5081. &last_prefetched_hw_desc,
  5082. &last_prefetched_sw_desc);
  5083. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5084. break;
  5085. }
  5086. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5087. /* Process the reaped descriptors */
  5088. if (head_desc)
  5089. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5090. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5091. /*
  5092. * If we are processing in near-full condition, there are 3 scenario
  5093. * 1) Ring entries has reached critical state
  5094. * 2) Ring entries are still near high threshold
  5095. * 3) Ring entries are below the safe level
  5096. *
  5097. * One more loop will move the state to normal processing and yield
  5098. */
  5099. if (ring_near_full)
  5100. goto more_data;
  5101. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5102. if (num_processed >= quota)
  5103. force_break = true;
  5104. if (!force_break &&
  5105. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5106. hal_ring_hdl)) {
  5107. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5108. if (!hif_exec_should_yield(soc->hif_handle,
  5109. int_ctx->dp_intr_id))
  5110. goto more_data;
  5111. num_avail_for_reap =
  5112. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5113. hal_ring_hdl,
  5114. true);
  5115. if (qdf_unlikely(num_entries &&
  5116. (num_avail_for_reap >=
  5117. num_entries >> 1))) {
  5118. DP_STATS_INC(soc, tx.near_full, 1);
  5119. goto more_data;
  5120. }
  5121. }
  5122. }
  5123. DP_TX_HIST_STATS_PER_PDEV();
  5124. return num_processed;
  5125. }
  5126. #ifdef FEATURE_WLAN_TDLS
  5127. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5128. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5129. {
  5130. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5131. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5132. DP_MOD_ID_TDLS);
  5133. if (!vdev) {
  5134. dp_err("vdev handle for id %d is NULL", vdev_id);
  5135. return NULL;
  5136. }
  5137. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5138. vdev->is_tdls_frame = true;
  5139. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5140. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5141. }
  5142. #endif
  5143. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5144. {
  5145. int pdev_id;
  5146. /*
  5147. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5148. */
  5149. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5150. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5151. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5152. vdev->vdev_id);
  5153. pdev_id =
  5154. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5155. vdev->pdev->pdev_id);
  5156. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5157. /*
  5158. * Set HTT Extension Valid bit to 0 by default
  5159. */
  5160. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5161. dp_tx_vdev_update_search_flags(vdev);
  5162. return QDF_STATUS_SUCCESS;
  5163. }
  5164. #ifndef FEATURE_WDS
  5165. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5166. {
  5167. return false;
  5168. }
  5169. #endif
  5170. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5171. {
  5172. struct dp_soc *soc = vdev->pdev->soc;
  5173. /*
  5174. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5175. * for TDLS link
  5176. *
  5177. * Enable AddrY (SA based search) only for non-WDS STA and
  5178. * ProxySTA VAP (in HKv1) modes.
  5179. *
  5180. * In all other VAP modes, only DA based search should be
  5181. * enabled
  5182. */
  5183. if (vdev->opmode == wlan_op_mode_sta &&
  5184. vdev->tdls_link_connected)
  5185. vdev->hal_desc_addr_search_flags =
  5186. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5187. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5188. !dp_tx_da_search_override(vdev))
  5189. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5190. else
  5191. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5192. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5193. vdev->search_type = soc->sta_mode_search_policy;
  5194. else
  5195. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5196. }
  5197. static inline bool
  5198. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5199. struct dp_vdev *vdev,
  5200. struct dp_tx_desc_s *tx_desc)
  5201. {
  5202. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5203. return false;
  5204. /*
  5205. * if vdev is given, then only check whether desc
  5206. * vdev match. if vdev is NULL, then check whether
  5207. * desc pdev match.
  5208. */
  5209. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5210. (tx_desc->pdev == pdev);
  5211. }
  5212. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5213. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5214. bool force_free)
  5215. {
  5216. uint8_t i;
  5217. uint32_t j;
  5218. uint32_t num_desc, page_id, offset;
  5219. uint16_t num_desc_per_page;
  5220. struct dp_soc *soc = pdev->soc;
  5221. struct dp_tx_desc_s *tx_desc = NULL;
  5222. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5223. if (!vdev && !force_free) {
  5224. dp_err("Reset TX desc vdev, Vdev param is required!");
  5225. return;
  5226. }
  5227. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5228. tx_desc_pool = &soc->tx_desc[i];
  5229. if (!(tx_desc_pool->pool_size) ||
  5230. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5231. !(tx_desc_pool->desc_pages.cacheable_pages))
  5232. continue;
  5233. /*
  5234. * Add flow pool lock protection in case pool is freed
  5235. * due to all tx_desc is recycled when handle TX completion.
  5236. * this is not necessary when do force flush as:
  5237. * a. double lock will happen if dp_tx_desc_release is
  5238. * also trying to acquire it.
  5239. * b. dp interrupt has been disabled before do force TX desc
  5240. * flush in dp_pdev_deinit().
  5241. */
  5242. if (!force_free)
  5243. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5244. num_desc = tx_desc_pool->pool_size;
  5245. num_desc_per_page =
  5246. tx_desc_pool->desc_pages.num_element_per_page;
  5247. for (j = 0; j < num_desc; j++) {
  5248. page_id = j / num_desc_per_page;
  5249. offset = j % num_desc_per_page;
  5250. if (qdf_unlikely(!(tx_desc_pool->
  5251. desc_pages.cacheable_pages)))
  5252. break;
  5253. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5254. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5255. /*
  5256. * Free TX desc if force free is
  5257. * required, otherwise only reset vdev
  5258. * in this TX desc.
  5259. */
  5260. if (force_free) {
  5261. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5262. dp_tx_comp_free_buf(soc, tx_desc,
  5263. false);
  5264. dp_tx_desc_release(tx_desc, i);
  5265. } else {
  5266. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5267. }
  5268. }
  5269. }
  5270. if (!force_free)
  5271. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5272. }
  5273. }
  5274. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5275. /**
  5276. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5277. *
  5278. * @soc: Handle to DP soc structure
  5279. * @tx_desc: pointer of one TX desc
  5280. * @desc_pool_id: TX Desc pool id
  5281. */
  5282. static inline void
  5283. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5284. uint8_t desc_pool_id)
  5285. {
  5286. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5287. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5288. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5289. }
  5290. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5291. bool force_free)
  5292. {
  5293. uint8_t i, num_pool;
  5294. uint32_t j;
  5295. uint32_t num_desc, page_id, offset;
  5296. uint16_t num_desc_per_page;
  5297. struct dp_soc *soc = pdev->soc;
  5298. struct dp_tx_desc_s *tx_desc = NULL;
  5299. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5300. if (!vdev && !force_free) {
  5301. dp_err("Reset TX desc vdev, Vdev param is required!");
  5302. return;
  5303. }
  5304. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5305. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5306. for (i = 0; i < num_pool; i++) {
  5307. tx_desc_pool = &soc->tx_desc[i];
  5308. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5309. continue;
  5310. num_desc_per_page =
  5311. tx_desc_pool->desc_pages.num_element_per_page;
  5312. for (j = 0; j < num_desc; j++) {
  5313. page_id = j / num_desc_per_page;
  5314. offset = j % num_desc_per_page;
  5315. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5316. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5317. if (force_free) {
  5318. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5319. dp_tx_comp_free_buf(soc, tx_desc,
  5320. false);
  5321. dp_tx_desc_release(tx_desc, i);
  5322. } else {
  5323. dp_tx_desc_reset_vdev(soc, tx_desc,
  5324. i);
  5325. }
  5326. }
  5327. }
  5328. }
  5329. }
  5330. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5331. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5332. {
  5333. struct dp_pdev *pdev = vdev->pdev;
  5334. /* Reset TX desc associated to this Vdev as NULL */
  5335. dp_tx_desc_flush(pdev, vdev, false);
  5336. return QDF_STATUS_SUCCESS;
  5337. }
  5338. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5339. /* Pools will be allocated dynamically */
  5340. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5341. int num_desc)
  5342. {
  5343. uint8_t i;
  5344. for (i = 0; i < num_pool; i++) {
  5345. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5346. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5347. }
  5348. return QDF_STATUS_SUCCESS;
  5349. }
  5350. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5351. uint32_t num_desc)
  5352. {
  5353. return QDF_STATUS_SUCCESS;
  5354. }
  5355. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5356. {
  5357. }
  5358. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5359. {
  5360. uint8_t i;
  5361. for (i = 0; i < num_pool; i++)
  5362. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5363. }
  5364. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5365. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5366. uint32_t num_desc)
  5367. {
  5368. uint8_t i, count;
  5369. /* Allocate software Tx descriptor pools */
  5370. for (i = 0; i < num_pool; i++) {
  5371. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5372. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5373. FL("Tx Desc Pool alloc %d failed %pK"),
  5374. i, soc);
  5375. goto fail;
  5376. }
  5377. }
  5378. return QDF_STATUS_SUCCESS;
  5379. fail:
  5380. for (count = 0; count < i; count++)
  5381. dp_tx_desc_pool_free(soc, count);
  5382. return QDF_STATUS_E_NOMEM;
  5383. }
  5384. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5385. uint32_t num_desc)
  5386. {
  5387. uint8_t i;
  5388. for (i = 0; i < num_pool; i++) {
  5389. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5390. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5391. FL("Tx Desc Pool init %d failed %pK"),
  5392. i, soc);
  5393. return QDF_STATUS_E_NOMEM;
  5394. }
  5395. }
  5396. return QDF_STATUS_SUCCESS;
  5397. }
  5398. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5399. {
  5400. uint8_t i;
  5401. for (i = 0; i < num_pool; i++)
  5402. dp_tx_desc_pool_deinit(soc, i);
  5403. }
  5404. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5405. {
  5406. uint8_t i;
  5407. for (i = 0; i < num_pool; i++)
  5408. dp_tx_desc_pool_free(soc, i);
  5409. }
  5410. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5411. /**
  5412. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5413. * @soc: core txrx main context
  5414. * @num_pool: number of pools
  5415. *
  5416. */
  5417. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5418. {
  5419. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5420. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5421. }
  5422. /**
  5423. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5424. * @soc: core txrx main context
  5425. * @num_pool: number of pools
  5426. *
  5427. */
  5428. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5429. {
  5430. dp_tx_tso_desc_pool_free(soc, num_pool);
  5431. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5432. }
  5433. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5434. {
  5435. uint8_t num_pool;
  5436. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5437. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5438. dp_tx_ext_desc_pool_free(soc, num_pool);
  5439. dp_tx_delete_static_pools(soc, num_pool);
  5440. }
  5441. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5442. {
  5443. uint8_t num_pool;
  5444. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5445. dp_tx_flow_control_deinit(soc);
  5446. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5447. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5448. dp_tx_deinit_static_pools(soc, num_pool);
  5449. }
  5450. /**
  5451. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5452. * @soc: DP soc handle
  5453. * @num_pool: Number of pools
  5454. * @num_desc: Number of descriptors
  5455. *
  5456. * Reserve TSO descriptor buffers
  5457. *
  5458. * Return: QDF_STATUS_E_FAILURE on failure or
  5459. * QDF_STATUS_SUCCESS on success
  5460. */
  5461. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5462. uint8_t num_pool,
  5463. uint32_t num_desc)
  5464. {
  5465. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5466. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5467. return QDF_STATUS_E_FAILURE;
  5468. }
  5469. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5470. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5471. num_pool, soc);
  5472. return QDF_STATUS_E_FAILURE;
  5473. }
  5474. return QDF_STATUS_SUCCESS;
  5475. }
  5476. /**
  5477. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5478. * @soc: DP soc handle
  5479. * @num_pool: Number of pools
  5480. * @num_desc: Number of descriptors
  5481. *
  5482. * Initialize TSO descriptor pools
  5483. *
  5484. * Return: QDF_STATUS_E_FAILURE on failure or
  5485. * QDF_STATUS_SUCCESS on success
  5486. */
  5487. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5488. uint8_t num_pool,
  5489. uint32_t num_desc)
  5490. {
  5491. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5492. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5493. return QDF_STATUS_E_FAILURE;
  5494. }
  5495. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5496. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5497. num_pool, soc);
  5498. return QDF_STATUS_E_FAILURE;
  5499. }
  5500. return QDF_STATUS_SUCCESS;
  5501. }
  5502. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5503. {
  5504. uint8_t num_pool;
  5505. uint32_t num_desc;
  5506. uint32_t num_ext_desc;
  5507. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5508. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5509. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5511. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5512. __func__, num_pool, num_desc);
  5513. if ((num_pool > MAX_TXDESC_POOLS) ||
  5514. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5515. goto fail1;
  5516. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5517. goto fail1;
  5518. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5519. goto fail2;
  5520. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5521. return QDF_STATUS_SUCCESS;
  5522. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5523. goto fail3;
  5524. return QDF_STATUS_SUCCESS;
  5525. fail3:
  5526. dp_tx_ext_desc_pool_free(soc, num_pool);
  5527. fail2:
  5528. dp_tx_delete_static_pools(soc, num_pool);
  5529. fail1:
  5530. return QDF_STATUS_E_RESOURCES;
  5531. }
  5532. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5533. {
  5534. uint8_t num_pool;
  5535. uint32_t num_desc;
  5536. uint32_t num_ext_desc;
  5537. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5538. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5539. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5540. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5541. goto fail1;
  5542. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5543. goto fail2;
  5544. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5545. return QDF_STATUS_SUCCESS;
  5546. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5547. goto fail3;
  5548. dp_tx_flow_control_init(soc);
  5549. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5550. return QDF_STATUS_SUCCESS;
  5551. fail3:
  5552. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5553. fail2:
  5554. dp_tx_deinit_static_pools(soc, num_pool);
  5555. fail1:
  5556. return QDF_STATUS_E_RESOURCES;
  5557. }
  5558. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5559. {
  5560. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5561. uint8_t num_pool;
  5562. uint32_t num_ext_desc;
  5563. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5564. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5565. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5566. return QDF_STATUS_E_FAILURE;
  5567. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5568. return QDF_STATUS_E_FAILURE;
  5569. return QDF_STATUS_SUCCESS;
  5570. }
  5571. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5572. {
  5573. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5574. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5575. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5576. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5577. return QDF_STATUS_SUCCESS;
  5578. }
  5579. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5580. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5581. enum qdf_pkt_timestamp_index index, uint64_t time,
  5582. qdf_nbuf_t nbuf)
  5583. {
  5584. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5585. uint64_t tsf_time;
  5586. if (vdev->get_tsf_time) {
  5587. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5588. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5589. }
  5590. }
  5591. }
  5592. void dp_pkt_get_timestamp(uint64_t *time)
  5593. {
  5594. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5595. *time = qdf_get_log_timestamp();
  5596. }
  5597. #endif