msm-analog-cdc.c 136 KB

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  1. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/printk.h>
  16. #include <linux/debugfs.h>
  17. #include <linux/delay.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/workqueue.h>
  20. #include <linux/regmap.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/tlv.h>
  26. #include <dsp/audio_notifier.h>
  27. #include <dsp/q6afe-v2.h>
  28. #include <dsp/q6core.h>
  29. #include <ipc/apr.h>
  30. #include "msm-analog-cdc.h"
  31. #include "msm-cdc-common.h"
  32. #include "sdm660-cdc-irq.h"
  33. #include "msm-analog-cdc-regmap.h"
  34. #include "../../sdm660-common.h"
  35. #include "../wcd-mbhc-v2-api.h"
  36. #define DRV_NAME "pmic_analog_codec"
  37. #define SDM660_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  38. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
  39. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |\
  40. SNDRV_PCM_RATE_192000)
  41. #define SDM660_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  42. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE)
  43. #define MSM_DIG_CDC_STRING_LEN 80
  44. #define MSM_ANLG_CDC_VERSION_ENTRY_SIZE 32
  45. #define CODEC_DT_MAX_PROP_SIZE 40
  46. #define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64
  47. #define BUS_DOWN 1
  48. /*
  49. * 200 Milliseconds sufficient for DSP bring up in the lpass
  50. * after Sub System Restart
  51. */
  52. #define ADSP_STATE_READY_TIMEOUT_MS 200
  53. #define EAR_PMD 0
  54. #define EAR_PMU 1
  55. #define SPK_PMD 2
  56. #define SPK_PMU 3
  57. #define MICBIAS_DEFAULT_VAL 1800000
  58. #define MICBIAS_MIN_VAL 1600000
  59. #define MICBIAS_STEP_SIZE 50000
  60. #define DEFAULT_BOOST_VOLTAGE 5000
  61. #define MIN_BOOST_VOLTAGE 4000
  62. #define MAX_BOOST_VOLTAGE 5550
  63. #define BOOST_VOLTAGE_STEP 50
  64. #define SDM660_CDC_MBHC_BTN_COARSE_ADJ 100 /* in mV */
  65. #define SDM660_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */
  66. #define VOLTAGE_CONVERTER(value, min_value, step_size)\
  67. ((value - min_value)/step_size)
  68. enum {
  69. BOOST_SWITCH = 0,
  70. BOOST_ALWAYS,
  71. BYPASS_ALWAYS,
  72. BOOST_ON_FOREVER,
  73. };
  74. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  75. static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[];
  76. /* By default enable the internal speaker boost */
  77. static bool spkr_boost_en = true;
  78. static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = {
  79. "cdc-vdd-mic-bias",
  80. };
  81. static struct wcd_mbhc_register
  82. wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = {
  83. WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN",
  84. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x80, 7, 0),
  85. WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN",
  86. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x40, 6, 0),
  87. WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE",
  88. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x20, 5, 0),
  89. WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL",
  90. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x18, 3, 0),
  91. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE",
  92. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0),
  93. WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL",
  94. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0xC0, 6, 0),
  95. WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL",
  96. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x20, 5, 0),
  97. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE",
  98. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x10, 4, 0),
  99. WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE",
  100. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08, 3, 0),
  101. WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND",
  102. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0),
  103. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC",
  104. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x06, 1, 0),
  105. WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN",
  106. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x80, 7, 0),
  107. WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC",
  108. MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0xF0, 4, 0),
  109. WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC",
  110. MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x0C, 2, 0),
  111. WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF",
  112. MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x03, 0, 0),
  113. WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT",
  114. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x01,
  115. 0, 0),
  116. WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT",
  117. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x02,
  118. 1, 0),
  119. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT",
  120. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x08,
  121. 3, 0),
  122. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT",
  123. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x04,
  124. 2, 0),
  125. WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN",
  126. MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0x10, 4, 0),
  127. WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT",
  128. MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0xFF, 0, 0),
  129. WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL",
  130. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x70, 4, 0),
  131. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
  132. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0xFF,
  133. 0, 0),
  134. WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
  135. MSM89XX_PMIC_ANALOG_MICB_2_EN, 0xC0, 6, 0),
  136. WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
  137. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFC, 2, 0),
  138. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
  139. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x10, 4, 0),
  140. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN",
  141. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x20, 5, 0),
  142. WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN",
  143. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x30, 4, 0),
  144. WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE",
  145. MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT,
  146. 0x10, 4, 0),
  147. WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL",
  148. MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20, 5, 0),
  149. WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN", 0, 0, 0, 0),
  150. WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS", 0, 0, 0, 0),
  151. WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL", 0, 0, 0, 0),
  152. };
  153. /* Multiply gain_adj and offset by 1000 and 100 to avoid float arithmetic */
  154. static const struct wcd_imped_i_ref imped_i_ref[] = {
  155. {I_h4_UA, 8, 800, 9000, 10000},
  156. {I_pt5_UA, 10, 100, 990, 4600},
  157. {I_14_UA, 17, 14, 1050, 700},
  158. {I_l4_UA, 10, 4, 1165, 110},
  159. {I_1_UA, 0, 1, 1200, 65},
  160. };
  161. static const struct wcd_mbhc_intr intr_ids = {
  162. .mbhc_sw_intr = MSM89XX_IRQ_MBHC_HS_DET,
  163. .mbhc_btn_press_intr = MSM89XX_IRQ_MBHC_PRESS,
  164. .mbhc_btn_release_intr = MSM89XX_IRQ_MBHC_RELEASE,
  165. .mbhc_hs_ins_intr = MSM89XX_IRQ_MBHC_INSREM_DET1,
  166. .mbhc_hs_rem_intr = MSM89XX_IRQ_MBHC_INSREM_DET,
  167. .hph_left_ocp = MSM89XX_IRQ_HPHL_OCP,
  168. .hph_right_ocp = MSM89XX_IRQ_HPHR_OCP,
  169. };
  170. static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev,
  171. struct sdm660_cdc_regulator *vreg,
  172. const char *vreg_name,
  173. bool ondemand);
  174. static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
  175. struct device *dev);
  176. static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc,
  177. bool turn_on);
  178. static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec);
  179. static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec);
  180. static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec);
  181. static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec,
  182. bool enable);
  183. static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec,
  184. bool micbias1, bool micbias2);
  185. static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec);
  186. static int get_codec_version(struct sdm660_cdc_priv *sdm660_cdc)
  187. {
  188. if (sdm660_cdc->codec_version == DRAX_CDC)
  189. return DRAX_CDC;
  190. else if (sdm660_cdc->codec_version == DIANGU)
  191. return DIANGU;
  192. else if (sdm660_cdc->codec_version == CAJON_2_0)
  193. return CAJON_2_0;
  194. else if (sdm660_cdc->codec_version == CAJON)
  195. return CAJON;
  196. else if (sdm660_cdc->codec_version == CONGA)
  197. return CONGA;
  198. else if (sdm660_cdc->pmic_rev == TOMBAK_2_0)
  199. return TOMBAK_2_0;
  200. else if (sdm660_cdc->pmic_rev == TOMBAK_1_0)
  201. return TOMBAK_1_0;
  202. pr_err("%s: unsupported codec version\n", __func__);
  203. return UNSUPPORTED;
  204. }
  205. static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec,
  206. s16 *impedance_l, s16 *impedance_r)
  207. {
  208. struct sdm660_cdc_priv *sdm660_cdc =
  209. snd_soc_codec_get_drvdata(codec);
  210. if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
  211. (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) {
  212. /* Enable ZDET_L_MEAS_EN */
  213. snd_soc_update_bits(codec,
  214. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  215. 0x08, 0x08);
  216. /* Wait for 2ms for measurement to complete */
  217. usleep_range(2000, 2100);
  218. /* Read Left impedance value from Result1 */
  219. *impedance_l = snd_soc_read(codec,
  220. MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT);
  221. /* Enable ZDET_R_MEAS_EN */
  222. snd_soc_update_bits(codec,
  223. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  224. 0x08, 0x00);
  225. }
  226. if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
  227. (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) {
  228. snd_soc_update_bits(codec,
  229. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  230. 0x04, 0x04);
  231. /* Wait for 2ms for measurement to complete */
  232. usleep_range(2000, 2100);
  233. /* Read Right impedance value from Result1 */
  234. *impedance_r = snd_soc_read(codec,
  235. MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT);
  236. snd_soc_update_bits(codec,
  237. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  238. 0x04, 0x00);
  239. }
  240. }
  241. static void msm_anlg_cdc_set_ref_current(struct snd_soc_codec *codec,
  242. enum wcd_curr_ref curr_ref)
  243. {
  244. struct sdm660_cdc_priv *sdm660_cdc =
  245. snd_soc_codec_get_drvdata(codec);
  246. dev_dbg(codec->dev, "%s: curr_ref: %d\n", __func__, curr_ref);
  247. if (get_codec_version(sdm660_cdc) < CAJON)
  248. dev_dbg(codec->dev, "%s: Setting ref current not required\n",
  249. __func__);
  250. sdm660_cdc->imped_i_ref = imped_i_ref[curr_ref];
  251. switch (curr_ref) {
  252. case I_h4_UA:
  253. snd_soc_update_bits(codec,
  254. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  255. 0x07, 0x01);
  256. break;
  257. case I_pt5_UA:
  258. snd_soc_update_bits(codec,
  259. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  260. 0x07, 0x04);
  261. break;
  262. case I_14_UA:
  263. snd_soc_update_bits(codec,
  264. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  265. 0x07, 0x03);
  266. break;
  267. case I_l4_UA:
  268. snd_soc_update_bits(codec,
  269. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  270. 0x07, 0x01);
  271. break;
  272. case I_1_UA:
  273. snd_soc_update_bits(codec,
  274. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  275. 0x07, 0x00);
  276. break;
  277. default:
  278. pr_debug("%s: No ref current set\n", __func__);
  279. break;
  280. }
  281. }
  282. static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec,
  283. s16 *impedance_l, s16 *impedance_r)
  284. {
  285. int i = 2;
  286. s16 compare_imp = 0;
  287. struct sdm660_cdc_priv *sdm660_cdc =
  288. snd_soc_codec_get_drvdata(codec);
  289. if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
  290. compare_imp = *impedance_r;
  291. else
  292. compare_imp = *impedance_l;
  293. if (get_codec_version(sdm660_cdc) < CAJON) {
  294. dev_dbg(codec->dev,
  295. "%s: Reference current adjustment not required\n",
  296. __func__);
  297. return false;
  298. }
  299. while (compare_imp < imped_i_ref[i].min_val) {
  300. msm_anlg_cdc_set_ref_current(codec, imped_i_ref[++i].curr_ref);
  301. wcd_mbhc_meas_imped(codec, impedance_l, impedance_r);
  302. compare_imp = (sdm660_cdc->imped_det_pin ==
  303. WCD_MBHC_DET_HPHR) ? *impedance_r : *impedance_l;
  304. if (i >= I_1_UA)
  305. break;
  306. }
  307. return true;
  308. }
  309. void msm_anlg_cdc_spk_ext_pa_cb(
  310. int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
  311. int enable), struct snd_soc_codec *codec)
  312. {
  313. struct sdm660_cdc_priv *sdm660_cdc;
  314. if (!codec) {
  315. pr_err("%s: NULL codec pointer!\n", __func__);
  316. return;
  317. }
  318. sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  319. dev_dbg(codec->dev, "%s: Enter\n", __func__);
  320. sdm660_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa;
  321. }
  322. EXPORT_SYMBOL(msm_anlg_cdc_spk_ext_pa_cb);
  323. static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l,
  324. s16 r, uint32_t *zl, uint32_t *zr,
  325. bool high)
  326. {
  327. struct sdm660_cdc_priv *sdm660_cdc =
  328. snd_soc_codec_get_drvdata(codec);
  329. uint32_t rl = 0, rr = 0;
  330. struct wcd_imped_i_ref R = sdm660_cdc->imped_i_ref;
  331. int codec_ver = get_codec_version(sdm660_cdc);
  332. switch (codec_ver) {
  333. case TOMBAK_1_0:
  334. case TOMBAK_2_0:
  335. case CONGA:
  336. if (high) {
  337. dev_dbg(codec->dev,
  338. "%s: This plug has high range impedance\n",
  339. __func__);
  340. rl = (uint32_t)(((100 * (l * 400 - 200))/96) - 230);
  341. rr = (uint32_t)(((100 * (r * 400 - 200))/96) - 230);
  342. } else {
  343. dev_dbg(codec->dev,
  344. "%s: This plug has low range impedance\n",
  345. __func__);
  346. rl = (uint32_t)(((1000 * (l * 2 - 1))/1165) - (13/10));
  347. rr = (uint32_t)(((1000 * (r * 2 - 1))/1165) - (13/10));
  348. }
  349. break;
  350. case CAJON:
  351. case CAJON_2_0:
  352. case DIANGU:
  353. case DRAX_CDC:
  354. if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) {
  355. rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) -
  356. (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
  357. rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5)))
  358. - R.offset * R.gain_adj)/(R.gain_adj * 100));
  359. } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) {
  360. rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5)))
  361. - R.offset * R.gain_adj)/(R.gain_adj * 100));
  362. rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))-
  363. (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
  364. } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) {
  365. rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) -
  366. (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
  367. rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))-
  368. (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
  369. } else {
  370. rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5)))
  371. - R.offset * R.gain_adj)/(R.gain_adj * 100));
  372. rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5)))
  373. - R.offset * R.gain_adj)/(R.gain_adj * 100));
  374. }
  375. break;
  376. default:
  377. dev_dbg(codec->dev, "%s: No codec mentioned\n", __func__);
  378. break;
  379. }
  380. *zl = rl;
  381. *zr = rr;
  382. }
  383. static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal(
  384. struct wcd_mbhc *wcd_mbhc,
  385. enum wcd_cal_type type)
  386. {
  387. struct sdm660_cdc_priv *sdm660_cdc;
  388. struct firmware_cal *hwdep_cal;
  389. struct snd_soc_codec *codec = wcd_mbhc->codec;
  390. if (!codec) {
  391. pr_err("%s: NULL codec pointer\n", __func__);
  392. return NULL;
  393. }
  394. sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  395. hwdep_cal = wcdcal_get_fw_cal(sdm660_cdc->fw_data, type);
  396. if (!hwdep_cal) {
  397. dev_err(codec->dev, "%s: cal not sent by %d\n",
  398. __func__, type);
  399. return NULL;
  400. }
  401. return hwdep_cal;
  402. }
  403. static void wcd9xxx_spmi_irq_control(struct snd_soc_codec *codec,
  404. int irq, bool enable)
  405. {
  406. if (enable)
  407. wcd9xxx_spmi_enable_irq(irq);
  408. else
  409. wcd9xxx_spmi_disable_irq(irq);
  410. }
  411. static void msm_anlg_cdc_mbhc_clk_setup(struct snd_soc_codec *codec,
  412. bool enable)
  413. {
  414. if (enable)
  415. snd_soc_update_bits(codec,
  416. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  417. 0x08, 0x08);
  418. else
  419. snd_soc_update_bits(codec,
  420. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  421. 0x08, 0x00);
  422. }
  423. static int msm_anlg_cdc_mbhc_map_btn_code_to_num(struct snd_soc_codec *codec)
  424. {
  425. int btn_code;
  426. int btn;
  427. btn_code = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT);
  428. switch (btn_code) {
  429. case 0:
  430. btn = 0;
  431. break;
  432. case 1:
  433. btn = 1;
  434. break;
  435. case 3:
  436. btn = 2;
  437. break;
  438. case 7:
  439. btn = 3;
  440. break;
  441. case 15:
  442. btn = 4;
  443. break;
  444. default:
  445. btn = -EINVAL;
  446. break;
  447. };
  448. return btn;
  449. }
  450. static bool msm_anlg_cdc_spmi_lock_sleep(struct wcd_mbhc *mbhc, bool lock)
  451. {
  452. if (lock)
  453. return wcd9xxx_spmi_lock_sleep();
  454. wcd9xxx_spmi_unlock_sleep();
  455. return 0;
  456. }
  457. static bool msm_anlg_cdc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num)
  458. {
  459. if (micb_num == MIC_BIAS_1)
  460. return (snd_soc_read(mbhc->codec,
  461. MSM89XX_PMIC_ANALOG_MICB_1_EN) &
  462. 0x80);
  463. if (micb_num == MIC_BIAS_2)
  464. return (snd_soc_read(mbhc->codec,
  465. MSM89XX_PMIC_ANALOG_MICB_2_EN) &
  466. 0x80);
  467. return false;
  468. }
  469. static void msm_anlg_cdc_enable_master_bias(struct snd_soc_codec *codec,
  470. bool enable)
  471. {
  472. if (enable)
  473. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL,
  474. 0x30, 0x30);
  475. else
  476. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL,
  477. 0x30, 0x00);
  478. }
  479. static void msm_anlg_cdc_mbhc_common_micb_ctrl(struct snd_soc_codec *codec,
  480. int event, bool enable)
  481. {
  482. u16 reg;
  483. u8 mask;
  484. u8 val;
  485. switch (event) {
  486. case MBHC_COMMON_MICB_PRECHARGE:
  487. reg = MSM89XX_PMIC_ANALOG_MICB_1_CTL;
  488. mask = 0x60;
  489. val = (enable ? 0x60 : 0x00);
  490. break;
  491. case MBHC_COMMON_MICB_SET_VAL:
  492. reg = MSM89XX_PMIC_ANALOG_MICB_1_VAL;
  493. mask = 0xFF;
  494. val = (enable ? 0xC0 : 0x00);
  495. break;
  496. case MBHC_COMMON_MICB_TAIL_CURR:
  497. reg = MSM89XX_PMIC_ANALOG_MICB_1_EN;
  498. mask = 0x04;
  499. val = (enable ? 0x04 : 0x00);
  500. break;
  501. default:
  502. dev_err(codec->dev,
  503. "%s: Invalid event received\n", __func__);
  504. return;
  505. };
  506. snd_soc_update_bits(codec, reg, mask, val);
  507. }
  508. static void msm_anlg_cdc_mbhc_internal_micbias_ctrl(struct snd_soc_codec *codec,
  509. int micbias_num,
  510. bool enable)
  511. {
  512. if (micbias_num == 1) {
  513. if (enable)
  514. snd_soc_update_bits(codec,
  515. MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS,
  516. 0x10, 0x10);
  517. else
  518. snd_soc_update_bits(codec,
  519. MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS,
  520. 0x10, 0x00);
  521. }
  522. }
  523. static bool msm_anlg_cdc_mbhc_hph_pa_on_status(struct snd_soc_codec *codec)
  524. {
  525. return (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN) &
  526. 0x30) ? true : false;
  527. }
  528. static void msm_anlg_cdc_mbhc_program_btn_thr(struct snd_soc_codec *codec,
  529. s16 *btn_low, s16 *btn_high,
  530. int num_btn, bool is_micbias)
  531. {
  532. int i;
  533. u32 course, fine, reg_val;
  534. u16 reg_addr = MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL;
  535. s16 *btn_voltage;
  536. btn_voltage = ((is_micbias) ? btn_high : btn_low);
  537. for (i = 0; i < num_btn; i++) {
  538. course = (btn_voltage[i] / SDM660_CDC_MBHC_BTN_COARSE_ADJ);
  539. fine = ((btn_voltage[i] % SDM660_CDC_MBHC_BTN_COARSE_ADJ) /
  540. SDM660_CDC_MBHC_BTN_FINE_ADJ);
  541. reg_val = (course << 5) | (fine << 2);
  542. snd_soc_update_bits(codec, reg_addr, 0xFC, reg_val);
  543. dev_dbg(codec->dev,
  544. "%s: course: %d fine: %d reg_addr: %x reg_val: %x\n",
  545. __func__, course, fine, reg_addr, reg_val);
  546. reg_addr++;
  547. }
  548. }
  549. static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
  550. uint32_t *zl, uint32_t *zr)
  551. {
  552. struct snd_soc_codec *codec = mbhc->codec;
  553. struct sdm660_cdc_priv *sdm660_cdc =
  554. snd_soc_codec_get_drvdata(codec);
  555. s16 impedance_l, impedance_r;
  556. s16 impedance_l_fixed;
  557. s16 reg0, reg1, reg2, reg3, reg4;
  558. bool high = false;
  559. bool min_range_used = false;
  560. WCD_MBHC_RSC_ASSERT_LOCKED(mbhc);
  561. reg0 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER);
  562. reg1 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL);
  563. reg2 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2);
  564. reg3 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN);
  565. reg4 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL);
  566. sdm660_cdc->imped_det_pin = WCD_MBHC_DET_BOTH;
  567. mbhc->hph_type = WCD_MBHC_HPH_NONE;
  568. /* disable FSM and micbias and enable pullup*/
  569. snd_soc_update_bits(codec,
  570. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  571. 0x80, 0x00);
  572. snd_soc_update_bits(codec,
  573. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  574. 0xA5, 0x25);
  575. /*
  576. * Enable legacy electrical detection current sources
  577. * and disable fast ramp and enable manual switching
  578. * of extra capacitance
  579. */
  580. dev_dbg(codec->dev, "%s: Setup for impedance det\n", __func__);
  581. msm_anlg_cdc_set_ref_current(codec, I_h4_UA);
  582. snd_soc_update_bits(codec,
  583. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2,
  584. 0x06, 0x02);
  585. snd_soc_update_bits(codec,
  586. MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER,
  587. 0x02, 0x02);
  588. snd_soc_update_bits(codec,
  589. MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL,
  590. 0x02, 0x00);
  591. dev_dbg(codec->dev, "%s: Start performing impedance detection\n",
  592. __func__);
  593. wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r);
  594. if (impedance_l > 2 || impedance_r > 2) {
  595. high = true;
  596. if (!mbhc->mbhc_cfg->mono_stero_detection) {
  597. /* Set ZDET_CHG to 0 to discharge ramp */
  598. snd_soc_update_bits(codec,
  599. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  600. 0x02, 0x00);
  601. /* wait 40ms for the discharge ramp to complete */
  602. usleep_range(40000, 40100);
  603. snd_soc_update_bits(codec,
  604. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  605. 0x03, 0x00);
  606. sdm660_cdc->imped_det_pin = (impedance_l > 2 &&
  607. impedance_r > 2) ?
  608. WCD_MBHC_DET_NONE :
  609. ((impedance_l > 2) ?
  610. WCD_MBHC_DET_HPHR :
  611. WCD_MBHC_DET_HPHL);
  612. if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE)
  613. goto exit;
  614. } else {
  615. if (get_codec_version(sdm660_cdc) >= CAJON) {
  616. if (impedance_l == 63 && impedance_r == 63) {
  617. dev_dbg(codec->dev,
  618. "%s: HPHL and HPHR are floating\n",
  619. __func__);
  620. sdm660_cdc->imped_det_pin =
  621. WCD_MBHC_DET_NONE;
  622. mbhc->hph_type = WCD_MBHC_HPH_NONE;
  623. } else if (impedance_l == 63
  624. && impedance_r < 63) {
  625. dev_dbg(codec->dev,
  626. "%s: Mono HS with HPHL floating\n",
  627. __func__);
  628. sdm660_cdc->imped_det_pin =
  629. WCD_MBHC_DET_HPHR;
  630. mbhc->hph_type = WCD_MBHC_HPH_MONO;
  631. } else if (impedance_r == 63 &&
  632. impedance_l < 63) {
  633. dev_dbg(codec->dev,
  634. "%s: Mono HS with HPHR floating\n",
  635. __func__);
  636. sdm660_cdc->imped_det_pin =
  637. WCD_MBHC_DET_HPHL;
  638. mbhc->hph_type = WCD_MBHC_HPH_MONO;
  639. } else if (impedance_l > 3 && impedance_r > 3 &&
  640. (impedance_l == impedance_r)) {
  641. snd_soc_update_bits(codec,
  642. MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2,
  643. 0x06, 0x06);
  644. wcd_mbhc_meas_imped(codec, &impedance_l,
  645. &impedance_r);
  646. if (impedance_r == impedance_l)
  647. dev_dbg(codec->dev,
  648. "%s: Mono Headset\n",
  649. __func__);
  650. sdm660_cdc->imped_det_pin =
  651. WCD_MBHC_DET_NONE;
  652. mbhc->hph_type =
  653. WCD_MBHC_HPH_MONO;
  654. } else {
  655. dev_dbg(codec->dev,
  656. "%s: STEREO headset is found\n",
  657. __func__);
  658. sdm660_cdc->imped_det_pin =
  659. WCD_MBHC_DET_BOTH;
  660. mbhc->hph_type = WCD_MBHC_HPH_STEREO;
  661. }
  662. }
  663. }
  664. }
  665. msm_anlg_cdc_set_ref_current(codec, I_pt5_UA);
  666. msm_anlg_cdc_set_ref_current(codec, I_14_UA);
  667. /* Enable RAMP_L , RAMP_R & ZDET_CHG*/
  668. snd_soc_update_bits(codec,
  669. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  670. 0x03, 0x03);
  671. snd_soc_update_bits(codec,
  672. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  673. 0x02, 0x02);
  674. /* wait for 50msec for the HW to apply ramp on HPHL and HPHR */
  675. usleep_range(50000, 50100);
  676. /* Enable ZDET_DISCHG_CAP_CTL to add extra capacitance */
  677. snd_soc_update_bits(codec,
  678. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  679. 0x01, 0x01);
  680. /* wait for 5msec for the voltage to get stable */
  681. usleep_range(5000, 5100);
  682. wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r);
  683. min_range_used = msm_anlg_cdc_adj_ref_current(codec,
  684. &impedance_l, &impedance_r);
  685. if (!mbhc->mbhc_cfg->mono_stero_detection) {
  686. /* Set ZDET_CHG to 0 to discharge ramp */
  687. snd_soc_update_bits(codec,
  688. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  689. 0x02, 0x00);
  690. /* wait for 40msec for the capacitor to discharge */
  691. usleep_range(40000, 40100);
  692. snd_soc_update_bits(codec,
  693. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  694. 0x03, 0x00);
  695. goto exit;
  696. }
  697. /* we are setting ref current to the minimun range or the measured
  698. * value larger than the minimum value, so min_range_used is true.
  699. * If the headset is mono headset with either HPHL or HPHR floating
  700. * then we have already done the mono stereo detection and do not
  701. * need to continue further.
  702. */
  703. if (!min_range_used ||
  704. sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL ||
  705. sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
  706. goto exit;
  707. /* Disable Set ZDET_CONN_RAMP_L and enable ZDET_CONN_FIXED_L */
  708. snd_soc_update_bits(codec,
  709. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  710. 0x02, 0x00);
  711. snd_soc_update_bits(codec,
  712. MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL,
  713. 0x02, 0x02);
  714. /* Set ZDET_CHG to 0 */
  715. snd_soc_update_bits(codec,
  716. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  717. 0x02, 0x00);
  718. /* wait for 40msec for the capacitor to discharge */
  719. usleep_range(40000, 40100);
  720. /* Set ZDET_CONN_RAMP_R to 0 */
  721. snd_soc_update_bits(codec,
  722. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  723. 0x01, 0x00);
  724. /* Enable ZDET_L_MEAS_EN */
  725. snd_soc_update_bits(codec,
  726. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  727. 0x08, 0x08);
  728. /* wait for 2msec for the HW to compute left inpedance value */
  729. usleep_range(2000, 2100);
  730. /* Read Left impedance value from Result1 */
  731. impedance_l_fixed = snd_soc_read(codec,
  732. MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT);
  733. /* Disable ZDET_L_MEAS_EN */
  734. snd_soc_update_bits(codec,
  735. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  736. 0x08, 0x00);
  737. /*
  738. * Assume impedance_l is L1, impedance_l_fixed is L2.
  739. * If the following condition is met, we can take this
  740. * headset as mono one with impedance of L2.
  741. * Otherwise, take it as stereo with impedance of L1.
  742. * Condition:
  743. * abs[(L2-0.5L1)/(L2+0.5L1)] < abs [(L2-L1)/(L2+L1)]
  744. */
  745. if ((abs(impedance_l_fixed - impedance_l/2) *
  746. (impedance_l_fixed + impedance_l)) >=
  747. (abs(impedance_l_fixed - impedance_l) *
  748. (impedance_l_fixed + impedance_l/2))) {
  749. dev_dbg(codec->dev,
  750. "%s: STEREO plug type detected\n",
  751. __func__);
  752. mbhc->hph_type = WCD_MBHC_HPH_STEREO;
  753. } else {
  754. dev_dbg(codec->dev,
  755. "%s: MONO plug type detected\n",
  756. __func__);
  757. mbhc->hph_type = WCD_MBHC_HPH_MONO;
  758. impedance_l = impedance_l_fixed;
  759. }
  760. /* Enable ZDET_CHG */
  761. snd_soc_update_bits(codec,
  762. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  763. 0x02, 0x02);
  764. /* wait for 10msec for the capacitor to charge */
  765. usleep_range(10000, 10100);
  766. snd_soc_update_bits(codec,
  767. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  768. 0x02, 0x02);
  769. snd_soc_update_bits(codec,
  770. MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL,
  771. 0x02, 0x00);
  772. /* Set ZDET_CHG to 0 to discharge HPHL */
  773. snd_soc_update_bits(codec,
  774. MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
  775. 0x02, 0x00);
  776. /* wait for 40msec for the capacitor to discharge */
  777. usleep_range(40000, 40100);
  778. snd_soc_update_bits(codec,
  779. MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
  780. 0x02, 0x00);
  781. exit:
  782. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, reg4);
  783. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN, reg3);
  784. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, reg1);
  785. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, reg0);
  786. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, reg2);
  787. msm_anlg_cdc_compute_impedance(codec, impedance_l, impedance_r,
  788. zl, zr, high);
  789. dev_dbg(codec->dev, "%s: RL %d ohm, RR %d ohm\n", __func__, *zl, *zr);
  790. dev_dbg(codec->dev, "%s: Impedance detection completed\n", __func__);
  791. }
  792. static int msm_anlg_cdc_dig_register_notifier(void *handle,
  793. struct notifier_block *nblock,
  794. bool enable)
  795. {
  796. struct sdm660_cdc_priv *handle_cdc = handle;
  797. if (enable)
  798. return blocking_notifier_chain_register(&handle_cdc->notifier,
  799. nblock);
  800. return blocking_notifier_chain_unregister(&handle_cdc->notifier,
  801. nblock);
  802. }
  803. static int msm_anlg_cdc_mbhc_register_notifier(struct wcd_mbhc *wcd_mbhc,
  804. struct notifier_block *nblock,
  805. bool enable)
  806. {
  807. struct snd_soc_codec *codec = wcd_mbhc->codec;
  808. struct sdm660_cdc_priv *sdm660_cdc =
  809. snd_soc_codec_get_drvdata(codec);
  810. if (enable)
  811. return blocking_notifier_chain_register(
  812. &sdm660_cdc->notifier_mbhc,
  813. nblock);
  814. return blocking_notifier_chain_unregister(&sdm660_cdc->notifier_mbhc,
  815. nblock);
  816. }
  817. static int msm_anlg_cdc_request_irq(struct snd_soc_codec *codec,
  818. int irq, irq_handler_t handler,
  819. const char *name, void *data)
  820. {
  821. return wcd9xxx_spmi_request_irq(irq, handler, name, data);
  822. }
  823. static int msm_anlg_cdc_free_irq(struct snd_soc_codec *codec,
  824. int irq, void *data)
  825. {
  826. return wcd9xxx_spmi_free_irq(irq, data);
  827. }
  828. static const struct wcd_mbhc_cb mbhc_cb = {
  829. .enable_mb_source = msm_anlg_cdc_enable_ext_mb_source,
  830. .trim_btn_reg = msm_anlg_cdc_trim_btn_reg,
  831. .compute_impedance = msm_anlg_cdc_mbhc_calc_impedance,
  832. .set_micbias_value = msm_anlg_cdc_set_micb_v,
  833. .set_auto_zeroing = msm_anlg_cdc_set_auto_zeroing,
  834. .get_hwdep_fw_cal = msm_anlg_cdc_get_hwdep_fw_cal,
  835. .set_cap_mode = msm_anlg_cdc_configure_cap,
  836. .register_notifier = msm_anlg_cdc_mbhc_register_notifier,
  837. .request_irq = msm_anlg_cdc_request_irq,
  838. .irq_control = wcd9xxx_spmi_irq_control,
  839. .free_irq = msm_anlg_cdc_free_irq,
  840. .clk_setup = msm_anlg_cdc_mbhc_clk_setup,
  841. .map_btn_code_to_num = msm_anlg_cdc_mbhc_map_btn_code_to_num,
  842. .lock_sleep = msm_anlg_cdc_spmi_lock_sleep,
  843. .micbias_enable_status = msm_anlg_cdc_micb_en_status,
  844. .mbhc_bias = msm_anlg_cdc_enable_master_bias,
  845. .mbhc_common_micb_ctrl = msm_anlg_cdc_mbhc_common_micb_ctrl,
  846. .micb_internal = msm_anlg_cdc_mbhc_internal_micbias_ctrl,
  847. .hph_pa_on_status = msm_anlg_cdc_mbhc_hph_pa_on_status,
  848. .set_btn_thr = msm_anlg_cdc_mbhc_program_btn_thr,
  849. .extn_use_mb = msm_anlg_cdc_use_mb,
  850. };
  851. static const uint32_t wcd_imped_val[] = {4, 8, 12, 13, 16,
  852. 20, 24, 28, 32,
  853. 36, 40, 44, 48};
  854. static void msm_anlg_cdc_dig_notifier_call(struct snd_soc_codec *codec,
  855. const enum dig_cdc_notify_event event)
  856. {
  857. struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  858. pr_debug("%s: notifier call event %d\n", __func__, event);
  859. blocking_notifier_call_chain(&sdm660_cdc->notifier,
  860. event, NULL);
  861. }
  862. static void msm_anlg_cdc_notifier_call(struct snd_soc_codec *codec,
  863. const enum wcd_notify_event event)
  864. {
  865. struct sdm660_cdc_priv *sdm660_cdc =
  866. snd_soc_codec_get_drvdata(codec);
  867. dev_dbg(codec->dev, "%s: notifier call event %d\n", __func__, event);
  868. blocking_notifier_call_chain(&sdm660_cdc->notifier_mbhc, event,
  869. &sdm660_cdc->mbhc);
  870. }
  871. static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec)
  872. {
  873. struct sdm660_cdc_priv *sdm660_cdc =
  874. snd_soc_codec_get_drvdata(codec);
  875. snd_soc_update_bits(codec,
  876. MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F, 0x0F);
  877. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5);
  878. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F);
  879. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30);
  880. if (get_codec_version(sdm660_cdc) < CAJON_2_0)
  881. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82);
  882. else
  883. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2);
  884. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  885. 0x69, 0x69);
  886. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG,
  887. 0x01, 0x01);
  888. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO,
  889. 0x88, 0x88);
  890. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
  891. 0x03, 0x03);
  892. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL,
  893. 0xE1, 0xE1);
  894. if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
  895. snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  896. 0x20, 0x20);
  897. /* Wait for 1ms after clock ctl enable */
  898. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  899. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  900. 0xDF, 0xDF);
  901. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  902. } else {
  903. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  904. 0x40, 0x00);
  905. snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  906. 0x20, 0x20);
  907. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  908. 0x80, 0x80);
  909. /* Wait for 500us after BOOST_EN to happen */
  910. usleep_range(500, 510);
  911. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  912. 0x40, 0x40);
  913. /* Wait for 500us after BOOST pulse_skip */
  914. usleep_range(500, 510);
  915. }
  916. }
  917. static void msm_anlg_cdc_boost_off(struct snd_soc_codec *codec)
  918. {
  919. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  920. 0xDF, 0x5F);
  921. snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  922. 0x20, 0x00);
  923. }
  924. static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec)
  925. {
  926. struct sdm660_cdc_priv *sdm660_cdc =
  927. snd_soc_codec_get_drvdata(codec);
  928. if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
  929. snd_soc_write(codec,
  930. MSM89XX_PMIC_ANALOG_SEC_ACCESS,
  931. 0xA5);
  932. snd_soc_write(codec,
  933. MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3,
  934. 0x07);
  935. snd_soc_update_bits(codec,
  936. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  937. 0x02, 0x02);
  938. snd_soc_update_bits(codec,
  939. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  940. 0x01, 0x00);
  941. snd_soc_update_bits(codec,
  942. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  943. 0x40, 0x40);
  944. snd_soc_update_bits(codec,
  945. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  946. 0x80, 0x80);
  947. snd_soc_update_bits(codec,
  948. MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  949. 0xDF, 0xDF);
  950. } else {
  951. snd_soc_update_bits(codec,
  952. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  953. 0x20, 0x20);
  954. snd_soc_update_bits(codec,
  955. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  956. 0x20, 0x20);
  957. }
  958. }
  959. static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec)
  960. {
  961. struct sdm660_cdc_priv *sdm660_cdc =
  962. snd_soc_codec_get_drvdata(codec);
  963. if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
  964. snd_soc_update_bits(codec,
  965. MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
  966. 0x80, 0x00);
  967. snd_soc_update_bits(codec,
  968. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  969. 0x80, 0x00);
  970. snd_soc_update_bits(codec,
  971. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  972. 0x02, 0x00);
  973. snd_soc_update_bits(codec,
  974. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  975. 0x40, 0x00);
  976. } else {
  977. snd_soc_update_bits(codec,
  978. MSM89XX_PMIC_ANALOG_BYPASS_MODE,
  979. 0x20, 0x00);
  980. snd_soc_update_bits(codec,
  981. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  982. 0x20, 0x00);
  983. }
  984. }
  985. static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
  986. int flag)
  987. {
  988. struct sdm660_cdc_priv *sdm660_cdc =
  989. snd_soc_codec_get_drvdata(codec);
  990. if (flag == EAR_PMU) {
  991. switch (sdm660_cdc->boost_option) {
  992. case BOOST_SWITCH:
  993. if (sdm660_cdc->ear_pa_boost_set) {
  994. msm_anlg_cdc_boost_off(codec);
  995. msm_anlg_cdc_bypass_on(codec);
  996. }
  997. break;
  998. case BOOST_ALWAYS:
  999. msm_anlg_cdc_boost_on(codec);
  1000. break;
  1001. case BYPASS_ALWAYS:
  1002. msm_anlg_cdc_bypass_on(codec);
  1003. break;
  1004. case BOOST_ON_FOREVER:
  1005. msm_anlg_cdc_boost_on(codec);
  1006. break;
  1007. default:
  1008. dev_err(codec->dev,
  1009. "%s: invalid boost option: %d\n", __func__,
  1010. sdm660_cdc->boost_option);
  1011. break;
  1012. }
  1013. } else if (flag == EAR_PMD) {
  1014. switch (sdm660_cdc->boost_option) {
  1015. case BOOST_SWITCH:
  1016. if (sdm660_cdc->ear_pa_boost_set)
  1017. msm_anlg_cdc_bypass_off(codec);
  1018. break;
  1019. case BOOST_ALWAYS:
  1020. msm_anlg_cdc_boost_off(codec);
  1021. /* 80ms for EAR boost to settle down */
  1022. msleep(80);
  1023. break;
  1024. case BYPASS_ALWAYS:
  1025. /* nothing to do as bypass on always */
  1026. break;
  1027. case BOOST_ON_FOREVER:
  1028. /* nothing to do as boost on forever */
  1029. break;
  1030. default:
  1031. dev_err(codec->dev,
  1032. "%s: invalid boost option: %d\n", __func__,
  1033. sdm660_cdc->boost_option);
  1034. break;
  1035. }
  1036. } else if (flag == SPK_PMU) {
  1037. switch (sdm660_cdc->boost_option) {
  1038. case BOOST_SWITCH:
  1039. if (sdm660_cdc->spk_boost_set) {
  1040. msm_anlg_cdc_bypass_off(codec);
  1041. msm_anlg_cdc_boost_on(codec);
  1042. }
  1043. break;
  1044. case BOOST_ALWAYS:
  1045. msm_anlg_cdc_boost_on(codec);
  1046. break;
  1047. case BYPASS_ALWAYS:
  1048. msm_anlg_cdc_bypass_on(codec);
  1049. break;
  1050. case BOOST_ON_FOREVER:
  1051. msm_anlg_cdc_boost_on(codec);
  1052. break;
  1053. default:
  1054. dev_err(codec->dev,
  1055. "%s: invalid boost option: %d\n", __func__,
  1056. sdm660_cdc->boost_option);
  1057. break;
  1058. }
  1059. } else if (flag == SPK_PMD) {
  1060. switch (sdm660_cdc->boost_option) {
  1061. case BOOST_SWITCH:
  1062. if (sdm660_cdc->spk_boost_set) {
  1063. msm_anlg_cdc_boost_off(codec);
  1064. /*
  1065. * Add 40 ms sleep for the spk
  1066. * boost to settle down
  1067. */
  1068. msleep(40);
  1069. }
  1070. break;
  1071. case BOOST_ALWAYS:
  1072. msm_anlg_cdc_boost_off(codec);
  1073. /*
  1074. * Add 40 ms sleep for the spk
  1075. * boost to settle down
  1076. */
  1077. msleep(40);
  1078. break;
  1079. case BYPASS_ALWAYS:
  1080. /* nothing to do as bypass on always */
  1081. break;
  1082. case BOOST_ON_FOREVER:
  1083. /* nothing to do as boost on forever */
  1084. break;
  1085. default:
  1086. dev_err(codec->dev,
  1087. "%s: invalid boost option: %d\n", __func__,
  1088. sdm660_cdc->boost_option);
  1089. break;
  1090. }
  1091. }
  1092. }
  1093. static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev,
  1094. struct sdm660_cdc_regulator *vreg, const char *vreg_name,
  1095. bool ondemand)
  1096. {
  1097. int len, ret = 0;
  1098. const __be32 *prop;
  1099. char prop_name[CODEC_DT_MAX_PROP_SIZE];
  1100. struct device_node *regnode = NULL;
  1101. u32 prop_val;
  1102. snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply",
  1103. vreg_name);
  1104. regnode = of_parse_phandle(dev->of_node, prop_name, 0);
  1105. if (!regnode) {
  1106. dev_err(dev, "Looking up %s property in node %s failed\n",
  1107. prop_name, dev->of_node->full_name);
  1108. return -ENODEV;
  1109. }
  1110. dev_dbg(dev, "Looking up %s property in node %s\n",
  1111. prop_name, dev->of_node->full_name);
  1112. vreg->name = vreg_name;
  1113. vreg->ondemand = ondemand;
  1114. snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
  1115. "qcom,%s-voltage", vreg_name);
  1116. prop = of_get_property(dev->of_node, prop_name, &len);
  1117. if (!prop || (len != (2 * sizeof(__be32)))) {
  1118. dev_err(dev, "%s %s property\n",
  1119. prop ? "invalid format" : "no", prop_name);
  1120. return -EINVAL;
  1121. }
  1122. vreg->min_uv = be32_to_cpup(&prop[0]);
  1123. vreg->max_uv = be32_to_cpup(&prop[1]);
  1124. snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
  1125. "qcom,%s-current", vreg_name);
  1126. ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
  1127. if (ret) {
  1128. dev_err(dev, "Looking up %s property in node %s failed",
  1129. prop_name, dev->of_node->full_name);
  1130. return -EFAULT;
  1131. }
  1132. vreg->optimum_ua = prop_val;
  1133. dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA, ond %d\n\n", vreg->name,
  1134. vreg->min_uv, vreg->max_uv, vreg->optimum_ua, vreg->ondemand);
  1135. return 0;
  1136. }
  1137. static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec)
  1138. {
  1139. struct sdm660_cdc_priv *sdm660_cdc_priv =
  1140. snd_soc_codec_get_drvdata(codec);
  1141. const char *prop_name = "qcom,cdc-boost-voltage";
  1142. int boost_voltage, ret;
  1143. ret = of_property_read_u32(codec->dev->of_node, prop_name,
  1144. &boost_voltage);
  1145. if (ret) {
  1146. dev_dbg(codec->dev, "Looking up %s property in node %s failed\n",
  1147. prop_name, codec->dev->of_node->full_name);
  1148. boost_voltage = DEFAULT_BOOST_VOLTAGE;
  1149. }
  1150. if (boost_voltage < MIN_BOOST_VOLTAGE ||
  1151. boost_voltage > MAX_BOOST_VOLTAGE) {
  1152. dev_err(codec->dev,
  1153. "Incorrect boost voltage. Reverting to default\n");
  1154. boost_voltage = DEFAULT_BOOST_VOLTAGE;
  1155. }
  1156. sdm660_cdc_priv->boost_voltage =
  1157. VOLTAGE_CONVERTER(boost_voltage, MIN_BOOST_VOLTAGE,
  1158. BOOST_VOLTAGE_STEP);
  1159. dev_dbg(codec->dev, "Boost voltage value is: %d\n",
  1160. boost_voltage);
  1161. }
  1162. static void msm_anlg_cdc_dt_parse_micbias_info(struct device *dev,
  1163. struct wcd_micbias_setting *micbias)
  1164. {
  1165. const char *prop_name = "qcom,cdc-micbias-cfilt-mv";
  1166. int ret;
  1167. ret = of_property_read_u32(dev->of_node, prop_name,
  1168. &micbias->cfilt1_mv);
  1169. if (ret) {
  1170. dev_dbg(dev, "Looking up %s property in node %s failed",
  1171. prop_name, dev->of_node->full_name);
  1172. micbias->cfilt1_mv = MICBIAS_DEFAULT_VAL;
  1173. }
  1174. }
  1175. static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
  1176. struct device *dev)
  1177. {
  1178. struct sdm660_cdc_pdata *pdata;
  1179. int ret, static_cnt, ond_cnt, idx, i;
  1180. const char *name = NULL;
  1181. const char *static_prop_name = "qcom,cdc-static-supplies";
  1182. const char *ond_prop_name = "qcom,cdc-on-demand-supplies";
  1183. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  1184. if (!pdata)
  1185. return NULL;
  1186. static_cnt = of_property_count_strings(dev->of_node, static_prop_name);
  1187. if (static_cnt < 0) {
  1188. dev_err(dev, "%s: Failed to get static supplies %d\n", __func__,
  1189. static_cnt);
  1190. ret = -EINVAL;
  1191. goto err;
  1192. }
  1193. /* On-demand supply list is an optional property */
  1194. ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name);
  1195. if (ond_cnt < 0)
  1196. ond_cnt = 0;
  1197. WARN_ON(static_cnt <= 0 || ond_cnt < 0);
  1198. if ((static_cnt + ond_cnt) > ARRAY_SIZE(pdata->regulator)) {
  1199. dev_err(dev, "%s: Num of supplies %u > max supported %zd\n",
  1200. __func__, (static_cnt + ond_cnt),
  1201. ARRAY_SIZE(pdata->regulator));
  1202. ret = -EINVAL;
  1203. goto err;
  1204. }
  1205. for (idx = 0; idx < static_cnt; idx++) {
  1206. ret = of_property_read_string_index(dev->of_node,
  1207. static_prop_name, idx,
  1208. &name);
  1209. if (ret) {
  1210. dev_err(dev, "%s: of read string %s idx %d error %d\n",
  1211. __func__, static_prop_name, idx, ret);
  1212. goto err;
  1213. }
  1214. dev_dbg(dev, "%s: Found static cdc supply %s\n", __func__,
  1215. name);
  1216. ret = msm_anlg_cdc_dt_parse_vreg_info(dev,
  1217. &pdata->regulator[idx],
  1218. name, false);
  1219. if (ret) {
  1220. dev_err(dev, "%s:err parsing vreg for %s idx %d\n",
  1221. __func__, name, idx);
  1222. goto err;
  1223. }
  1224. }
  1225. for (i = 0; i < ond_cnt; i++, idx++) {
  1226. ret = of_property_read_string_index(dev->of_node, ond_prop_name,
  1227. i, &name);
  1228. if (ret) {
  1229. dev_err(dev, "%s: err parsing on_demand for %s idx %d\n",
  1230. __func__, ond_prop_name, i);
  1231. goto err;
  1232. }
  1233. dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__,
  1234. name);
  1235. ret = msm_anlg_cdc_dt_parse_vreg_info(dev,
  1236. &pdata->regulator[idx],
  1237. name, true);
  1238. if (ret) {
  1239. dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n",
  1240. __func__, name, idx);
  1241. goto err;
  1242. }
  1243. }
  1244. msm_anlg_cdc_dt_parse_micbias_info(dev, &pdata->micbias);
  1245. return pdata;
  1246. err:
  1247. devm_kfree(dev, pdata);
  1248. dev_err(dev, "%s: Failed to populate DT data ret = %d\n",
  1249. __func__, ret);
  1250. return NULL;
  1251. }
  1252. static int msm_anlg_cdc_codec_enable_on_demand_supply(
  1253. struct snd_soc_dapm_widget *w,
  1254. struct snd_kcontrol *kcontrol, int event)
  1255. {
  1256. int ret = 0;
  1257. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1258. struct sdm660_cdc_priv *sdm660_cdc =
  1259. snd_soc_codec_get_drvdata(codec);
  1260. struct on_demand_supply *supply;
  1261. if (w->shift >= ON_DEMAND_SUPPLIES_MAX) {
  1262. dev_err(codec->dev, "%s: error index > MAX Demand supplies",
  1263. __func__);
  1264. ret = -EINVAL;
  1265. goto out;
  1266. }
  1267. dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n",
  1268. __func__, on_demand_supply_name[w->shift], event,
  1269. atomic_read(&sdm660_cdc->on_demand_list[w->shift].ref));
  1270. supply = &sdm660_cdc->on_demand_list[w->shift];
  1271. WARN_ONCE(!supply->supply, "%s isn't defined\n",
  1272. on_demand_supply_name[w->shift]);
  1273. if (!supply->supply) {
  1274. dev_err(codec->dev, "%s: err supply not present ond for %d",
  1275. __func__, w->shift);
  1276. goto out;
  1277. }
  1278. switch (event) {
  1279. case SND_SOC_DAPM_PRE_PMU:
  1280. if (atomic_inc_return(&supply->ref) == 1) {
  1281. ret = regulator_set_voltage(supply->supply,
  1282. supply->min_uv,
  1283. supply->max_uv);
  1284. if (ret) {
  1285. dev_err(codec->dev,
  1286. "Setting regulator voltage(en) for micbias with err = %d\n",
  1287. ret);
  1288. goto out;
  1289. }
  1290. ret = regulator_set_load(supply->supply,
  1291. supply->optimum_ua);
  1292. if (ret < 0) {
  1293. dev_err(codec->dev,
  1294. "Setting regulator optimum mode(en) failed for micbias with err = %d\n",
  1295. ret);
  1296. goto out;
  1297. }
  1298. ret = regulator_enable(supply->supply);
  1299. }
  1300. if (ret)
  1301. dev_err(codec->dev, "%s: Failed to enable %s\n",
  1302. __func__,
  1303. on_demand_supply_name[w->shift]);
  1304. break;
  1305. case SND_SOC_DAPM_POST_PMD:
  1306. if (atomic_read(&supply->ref) == 0) {
  1307. dev_dbg(codec->dev, "%s: %s supply has been disabled.\n",
  1308. __func__, on_demand_supply_name[w->shift]);
  1309. goto out;
  1310. }
  1311. if (atomic_dec_return(&supply->ref) == 0) {
  1312. ret = regulator_disable(supply->supply);
  1313. if (ret)
  1314. dev_err(codec->dev, "%s: Failed to disable %s\n",
  1315. __func__,
  1316. on_demand_supply_name[w->shift]);
  1317. ret = regulator_set_voltage(supply->supply,
  1318. 0,
  1319. supply->max_uv);
  1320. if (ret) {
  1321. dev_err(codec->dev,
  1322. "Setting regulator voltage(dis) failed for micbias with err = %d\n",
  1323. ret);
  1324. goto out;
  1325. }
  1326. ret = regulator_set_load(supply->supply, 0);
  1327. if (ret < 0)
  1328. dev_err(codec->dev,
  1329. "Setting regulator optimum mode(dis) failed for micbias with err = %d\n",
  1330. ret);
  1331. }
  1332. break;
  1333. default:
  1334. break;
  1335. }
  1336. out:
  1337. return ret;
  1338. }
  1339. static int msm_anlg_cdc_codec_enable_clock_block(struct snd_soc_codec *codec,
  1340. int enable)
  1341. {
  1342. struct msm_asoc_mach_data *pdata = NULL;
  1343. pdata = snd_soc_card_get_drvdata(codec->component.card);
  1344. if (enable) {
  1345. snd_soc_update_bits(codec,
  1346. MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
  1347. msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_ON);
  1348. snd_soc_update_bits(codec,
  1349. MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
  1350. snd_soc_update_bits(codec,
  1351. MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
  1352. } else {
  1353. snd_soc_update_bits(codec,
  1354. MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
  1355. }
  1356. return 0;
  1357. }
  1358. static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
  1359. struct snd_kcontrol *kcontrol,
  1360. int event)
  1361. {
  1362. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1363. struct sdm660_cdc_priv *sdm660_cdc =
  1364. snd_soc_codec_get_drvdata(codec);
  1365. dev_dbg(codec->dev, "%s: event = %d\n", __func__, event);
  1366. switch (event) {
  1367. case SND_SOC_DAPM_PRE_PMU:
  1368. msm_anlg_cdc_codec_enable_clock_block(codec, 1);
  1369. if (!(strcmp(w->name, "EAR CP"))) {
  1370. snd_soc_update_bits(codec,
  1371. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1372. 0x80, 0x80);
  1373. msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMU);
  1374. } else if (get_codec_version(sdm660_cdc) >= DIANGU) {
  1375. snd_soc_update_bits(codec,
  1376. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1377. 0x80, 0x80);
  1378. } else {
  1379. snd_soc_update_bits(codec,
  1380. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1381. 0xC0, 0xC0);
  1382. }
  1383. break;
  1384. case SND_SOC_DAPM_POST_PMU:
  1385. /* Wait for 1ms post powerup of chargepump */
  1386. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  1387. break;
  1388. case SND_SOC_DAPM_POST_PMD:
  1389. /* Wait for 1ms post powerdown of chargepump */
  1390. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  1391. if (!(strcmp(w->name, "EAR CP"))) {
  1392. snd_soc_update_bits(codec,
  1393. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1394. 0x80, 0x00);
  1395. if (sdm660_cdc->boost_option != BOOST_ALWAYS) {
  1396. dev_dbg(codec->dev,
  1397. "%s: boost_option:%d, tear down ear\n",
  1398. __func__, sdm660_cdc->boost_option);
  1399. msm_anlg_cdc_boost_mode_sequence(codec,
  1400. EAR_PMD);
  1401. }
  1402. /*
  1403. * Reset pa select bit from ear to hph after ear pa
  1404. * is disabled and HPH DAC disable to reduce ear
  1405. * turn off pop and avoid HPH pop in concurrency
  1406. */
  1407. snd_soc_update_bits(codec,
  1408. MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x00);
  1409. } else {
  1410. if (get_codec_version(sdm660_cdc) < DIANGU)
  1411. snd_soc_update_bits(codec,
  1412. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1413. 0x40, 0x00);
  1414. if (sdm660_cdc->rx_bias_count == 0)
  1415. snd_soc_update_bits(codec,
  1416. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1417. 0x80, 0x00);
  1418. dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
  1419. __func__, sdm660_cdc->rx_bias_count);
  1420. }
  1421. break;
  1422. }
  1423. return 0;
  1424. }
  1425. static int msm_anlg_cdc_ear_pa_boost_get(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1429. struct sdm660_cdc_priv *sdm660_cdc =
  1430. snd_soc_codec_get_drvdata(codec);
  1431. ucontrol->value.integer.value[0] =
  1432. (sdm660_cdc->ear_pa_boost_set ? 1 : 0);
  1433. dev_dbg(codec->dev, "%s: sdm660_cdc->ear_pa_boost_set = %d\n",
  1434. __func__, sdm660_cdc->ear_pa_boost_set);
  1435. return 0;
  1436. }
  1437. static int msm_anlg_cdc_ear_pa_boost_set(struct snd_kcontrol *kcontrol,
  1438. struct snd_ctl_elem_value *ucontrol)
  1439. {
  1440. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1441. struct sdm660_cdc_priv *sdm660_cdc =
  1442. snd_soc_codec_get_drvdata(codec);
  1443. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1444. __func__, ucontrol->value.integer.value[0]);
  1445. sdm660_cdc->ear_pa_boost_set =
  1446. (ucontrol->value.integer.value[0] ? true : false);
  1447. return 0;
  1448. }
  1449. static int msm_anlg_cdc_pa_gain_get(struct snd_kcontrol *kcontrol,
  1450. struct snd_ctl_elem_value *ucontrol)
  1451. {
  1452. u8 ear_pa_gain;
  1453. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1454. struct sdm660_cdc_priv *sdm660_cdc =
  1455. snd_soc_codec_get_drvdata(codec);
  1456. if (get_codec_version(sdm660_cdc) >= DIANGU) {
  1457. ear_pa_gain = snd_soc_read(codec,
  1458. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC);
  1459. ear_pa_gain = (ear_pa_gain >> 1) & 0x3;
  1460. if (ear_pa_gain == 0x00) {
  1461. ucontrol->value.integer.value[0] = 3;
  1462. } else if (ear_pa_gain == 0x01) {
  1463. ucontrol->value.integer.value[1] = 2;
  1464. } else if (ear_pa_gain == 0x02) {
  1465. ucontrol->value.integer.value[2] = 1;
  1466. } else if (ear_pa_gain == 0x03) {
  1467. ucontrol->value.integer.value[3] = 0;
  1468. } else {
  1469. dev_err(codec->dev,
  1470. "%s: ERROR: Unsupported Ear Gain = 0x%x\n",
  1471. __func__, ear_pa_gain);
  1472. return -EINVAL;
  1473. }
  1474. } else {
  1475. ear_pa_gain = snd_soc_read(codec,
  1476. MSM89XX_PMIC_ANALOG_RX_EAR_CTL);
  1477. ear_pa_gain = (ear_pa_gain >> 5) & 0x1;
  1478. if (ear_pa_gain == 0x00) {
  1479. ucontrol->value.integer.value[0] = 0;
  1480. } else if (ear_pa_gain == 0x01) {
  1481. ucontrol->value.integer.value[0] = 3;
  1482. } else {
  1483. dev_err(codec->dev,
  1484. "%s: ERROR: Unsupported Ear Gain = 0x%x\n",
  1485. __func__, ear_pa_gain);
  1486. return -EINVAL;
  1487. }
  1488. }
  1489. ucontrol->value.integer.value[0] = ear_pa_gain;
  1490. dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
  1491. return 0;
  1492. }
  1493. static int msm_anlg_cdc_pa_gain_put(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. u8 ear_pa_gain;
  1497. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1498. struct sdm660_cdc_priv *sdm660_cdc =
  1499. snd_soc_codec_get_drvdata(codec);
  1500. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1501. __func__, ucontrol->value.integer.value[0]);
  1502. if (get_codec_version(sdm660_cdc) >= DIANGU) {
  1503. switch (ucontrol->value.integer.value[0]) {
  1504. case 0:
  1505. ear_pa_gain = 0x06;
  1506. break;
  1507. case 1:
  1508. ear_pa_gain = 0x04;
  1509. break;
  1510. case 2:
  1511. ear_pa_gain = 0x02;
  1512. break;
  1513. case 3:
  1514. ear_pa_gain = 0x00;
  1515. break;
  1516. default:
  1517. return -EINVAL;
  1518. }
  1519. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  1520. 0x06, ear_pa_gain);
  1521. } else {
  1522. switch (ucontrol->value.integer.value[0]) {
  1523. case 0:
  1524. ear_pa_gain = 0x00;
  1525. break;
  1526. case 3:
  1527. ear_pa_gain = 0x20;
  1528. break;
  1529. case 1:
  1530. case 2:
  1531. default:
  1532. return -EINVAL;
  1533. }
  1534. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  1535. 0x20, ear_pa_gain);
  1536. }
  1537. return 0;
  1538. }
  1539. static int msm_anlg_cdc_hph_mode_get(struct snd_kcontrol *kcontrol,
  1540. struct snd_ctl_elem_value *ucontrol)
  1541. {
  1542. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1543. struct sdm660_cdc_priv *sdm660_cdc =
  1544. snd_soc_codec_get_drvdata(codec);
  1545. if (sdm660_cdc->hph_mode == NORMAL_MODE) {
  1546. ucontrol->value.integer.value[0] = 0;
  1547. } else if (sdm660_cdc->hph_mode == HD2_MODE) {
  1548. ucontrol->value.integer.value[0] = 1;
  1549. } else {
  1550. dev_err(codec->dev, "%s: ERROR: Default HPH Mode= %d\n",
  1551. __func__, sdm660_cdc->hph_mode);
  1552. }
  1553. dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode = %d\n", __func__,
  1554. sdm660_cdc->hph_mode);
  1555. return 0;
  1556. }
  1557. static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol,
  1558. struct snd_ctl_elem_value *ucontrol)
  1559. {
  1560. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1561. struct sdm660_cdc_priv *sdm660_cdc =
  1562. snd_soc_codec_get_drvdata(codec);
  1563. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1564. __func__, ucontrol->value.integer.value[0]);
  1565. switch (ucontrol->value.integer.value[0]) {
  1566. case 0:
  1567. sdm660_cdc->hph_mode = NORMAL_MODE;
  1568. break;
  1569. case 1:
  1570. if (get_codec_version(sdm660_cdc) >= DIANGU)
  1571. sdm660_cdc->hph_mode = HD2_MODE;
  1572. break;
  1573. default:
  1574. sdm660_cdc->hph_mode = NORMAL_MODE;
  1575. break;
  1576. }
  1577. dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode_set = %d\n",
  1578. __func__, sdm660_cdc->hph_mode);
  1579. return 0;
  1580. }
  1581. static int msm_anlg_cdc_boost_option_get(struct snd_kcontrol *kcontrol,
  1582. struct snd_ctl_elem_value *ucontrol)
  1583. {
  1584. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1585. struct sdm660_cdc_priv *sdm660_cdc =
  1586. snd_soc_codec_get_drvdata(codec);
  1587. if (sdm660_cdc->boost_option == BOOST_SWITCH) {
  1588. ucontrol->value.integer.value[0] = 0;
  1589. } else if (sdm660_cdc->boost_option == BOOST_ALWAYS) {
  1590. ucontrol->value.integer.value[0] = 1;
  1591. } else if (sdm660_cdc->boost_option == BYPASS_ALWAYS) {
  1592. ucontrol->value.integer.value[0] = 2;
  1593. } else if (sdm660_cdc->boost_option == BOOST_ON_FOREVER) {
  1594. ucontrol->value.integer.value[0] = 3;
  1595. } else {
  1596. dev_err(codec->dev, "%s: ERROR: Unsupported Boost option= %d\n",
  1597. __func__, sdm660_cdc->boost_option);
  1598. return -EINVAL;
  1599. }
  1600. dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option = %d\n", __func__,
  1601. sdm660_cdc->boost_option);
  1602. return 0;
  1603. }
  1604. static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol,
  1605. struct snd_ctl_elem_value *ucontrol)
  1606. {
  1607. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1608. struct sdm660_cdc_priv *sdm660_cdc =
  1609. snd_soc_codec_get_drvdata(codec);
  1610. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1611. __func__, ucontrol->value.integer.value[0]);
  1612. switch (ucontrol->value.integer.value[0]) {
  1613. case 0:
  1614. sdm660_cdc->boost_option = BOOST_SWITCH;
  1615. break;
  1616. case 1:
  1617. sdm660_cdc->boost_option = BOOST_ALWAYS;
  1618. break;
  1619. case 2:
  1620. sdm660_cdc->boost_option = BYPASS_ALWAYS;
  1621. msm_anlg_cdc_bypass_on(codec);
  1622. break;
  1623. case 3:
  1624. sdm660_cdc->boost_option = BOOST_ON_FOREVER;
  1625. msm_anlg_cdc_boost_on(codec);
  1626. break;
  1627. default:
  1628. pr_err("%s: invalid boost option: %d\n", __func__,
  1629. sdm660_cdc->boost_option);
  1630. return -EINVAL;
  1631. }
  1632. dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option_set = %d\n",
  1633. __func__, sdm660_cdc->boost_option);
  1634. return 0;
  1635. }
  1636. static int msm_anlg_cdc_spk_boost_get(struct snd_kcontrol *kcontrol,
  1637. struct snd_ctl_elem_value *ucontrol)
  1638. {
  1639. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1640. struct sdm660_cdc_priv *sdm660_cdc =
  1641. snd_soc_codec_get_drvdata(codec);
  1642. if (sdm660_cdc->spk_boost_set == false) {
  1643. ucontrol->value.integer.value[0] = 0;
  1644. } else if (sdm660_cdc->spk_boost_set == true) {
  1645. ucontrol->value.integer.value[0] = 1;
  1646. } else {
  1647. dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
  1648. __func__, sdm660_cdc->spk_boost_set);
  1649. return -EINVAL;
  1650. }
  1651. dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", __func__,
  1652. sdm660_cdc->spk_boost_set);
  1653. return 0;
  1654. }
  1655. static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol,
  1656. struct snd_ctl_elem_value *ucontrol)
  1657. {
  1658. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1659. struct sdm660_cdc_priv *sdm660_cdc =
  1660. snd_soc_codec_get_drvdata(codec);
  1661. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1662. __func__, ucontrol->value.integer.value[0]);
  1663. switch (ucontrol->value.integer.value[0]) {
  1664. case 0:
  1665. sdm660_cdc->spk_boost_set = false;
  1666. break;
  1667. case 1:
  1668. sdm660_cdc->spk_boost_set = true;
  1669. break;
  1670. default:
  1671. return -EINVAL;
  1672. }
  1673. dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n",
  1674. __func__, sdm660_cdc->spk_boost_set);
  1675. return 0;
  1676. }
  1677. static int msm_anlg_cdc_ext_spk_boost_get(struct snd_kcontrol *kcontrol,
  1678. struct snd_ctl_elem_value *ucontrol)
  1679. {
  1680. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1681. struct sdm660_cdc_priv *sdm660_cdc =
  1682. snd_soc_codec_get_drvdata(codec);
  1683. if (sdm660_cdc->ext_spk_boost_set == false)
  1684. ucontrol->value.integer.value[0] = 0;
  1685. else
  1686. ucontrol->value.integer.value[0] = 1;
  1687. dev_dbg(codec->dev, "%s: sdm660_cdc->ext_spk_boost_set = %d\n",
  1688. __func__, sdm660_cdc->ext_spk_boost_set);
  1689. return 0;
  1690. }
  1691. static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol,
  1692. struct snd_ctl_elem_value *ucontrol)
  1693. {
  1694. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1695. struct sdm660_cdc_priv *sdm660_cdc =
  1696. snd_soc_codec_get_drvdata(codec);
  1697. dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1698. __func__, ucontrol->value.integer.value[0]);
  1699. switch (ucontrol->value.integer.value[0]) {
  1700. case 0:
  1701. sdm660_cdc->ext_spk_boost_set = false;
  1702. break;
  1703. case 1:
  1704. sdm660_cdc->ext_spk_boost_set = true;
  1705. break;
  1706. default:
  1707. return -EINVAL;
  1708. }
  1709. dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n",
  1710. __func__, sdm660_cdc->spk_boost_set);
  1711. return 0;
  1712. }
  1713. static const char * const msm_anlg_cdc_ear_pa_boost_ctrl_text[] = {
  1714. "DISABLE", "ENABLE"};
  1715. static const struct soc_enum msm_anlg_cdc_ear_pa_boost_ctl_enum[] = {
  1716. SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ear_pa_boost_ctrl_text),
  1717. };
  1718. static const char * const msm_anlg_cdc_ear_pa_gain_text[] = {
  1719. "POS_1P5_DB", "POS_3_DB", "POS_4P5_DB", "POS_6_DB"};
  1720. static const struct soc_enum msm_anlg_cdc_ear_pa_gain_enum[] = {
  1721. SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_ear_pa_gain_text),
  1722. };
  1723. static const char * const msm_anlg_cdc_boost_option_ctrl_text[] = {
  1724. "BOOST_SWITCH", "BOOST_ALWAYS", "BYPASS_ALWAYS",
  1725. "BOOST_ON_FOREVER"};
  1726. static const struct soc_enum msm_anlg_cdc_boost_option_ctl_enum[] = {
  1727. SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_boost_option_ctrl_text),
  1728. };
  1729. static const char * const msm_anlg_cdc_spk_boost_ctrl_text[] = {
  1730. "DISABLE", "ENABLE"};
  1731. static const struct soc_enum msm_anlg_cdc_spk_boost_ctl_enum[] = {
  1732. SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_spk_boost_ctrl_text),
  1733. };
  1734. static const char * const msm_anlg_cdc_ext_spk_boost_ctrl_text[] = {
  1735. "DISABLE", "ENABLE"};
  1736. static const struct soc_enum msm_anlg_cdc_ext_spk_boost_ctl_enum[] = {
  1737. SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ext_spk_boost_ctrl_text),
  1738. };
  1739. static const char * const msm_anlg_cdc_hph_mode_ctrl_text[] = {
  1740. "NORMAL", "HD2"};
  1741. static const struct soc_enum msm_anlg_cdc_hph_mode_ctl_enum[] = {
  1742. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(msm_anlg_cdc_hph_mode_ctrl_text),
  1743. msm_anlg_cdc_hph_mode_ctrl_text),
  1744. };
  1745. /*cut of frequency for high pass filter*/
  1746. static const char * const cf_text[] = {
  1747. "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
  1748. };
  1749. static const struct snd_kcontrol_new msm_anlg_cdc_snd_controls[] = {
  1750. SOC_ENUM_EXT("RX HPH Mode", msm_anlg_cdc_hph_mode_ctl_enum[0],
  1751. msm_anlg_cdc_hph_mode_get, msm_anlg_cdc_hph_mode_set),
  1752. SOC_ENUM_EXT("Boost Option", msm_anlg_cdc_boost_option_ctl_enum[0],
  1753. msm_anlg_cdc_boost_option_get, msm_anlg_cdc_boost_option_set),
  1754. SOC_ENUM_EXT("EAR PA Boost", msm_anlg_cdc_ear_pa_boost_ctl_enum[0],
  1755. msm_anlg_cdc_ear_pa_boost_get, msm_anlg_cdc_ear_pa_boost_set),
  1756. SOC_ENUM_EXT("EAR PA Gain", msm_anlg_cdc_ear_pa_gain_enum[0],
  1757. msm_anlg_cdc_pa_gain_get, msm_anlg_cdc_pa_gain_put),
  1758. SOC_ENUM_EXT("Speaker Boost", msm_anlg_cdc_spk_boost_ctl_enum[0],
  1759. msm_anlg_cdc_spk_boost_get, msm_anlg_cdc_spk_boost_set),
  1760. SOC_ENUM_EXT("Ext Spk Boost", msm_anlg_cdc_ext_spk_boost_ctl_enum[0],
  1761. msm_anlg_cdc_ext_spk_boost_get, msm_anlg_cdc_ext_spk_boost_set),
  1762. SOC_SINGLE_TLV("ADC1 Volume", MSM89XX_PMIC_ANALOG_TX_1_EN, 3,
  1763. 8, 0, analog_gain),
  1764. SOC_SINGLE_TLV("ADC2 Volume", MSM89XX_PMIC_ANALOG_TX_2_EN, 3,
  1765. 8, 0, analog_gain),
  1766. SOC_SINGLE_TLV("ADC3 Volume", MSM89XX_PMIC_ANALOG_TX_3_EN, 3,
  1767. 8, 0, analog_gain),
  1768. };
  1769. static int tombak_hph_impedance_get(struct snd_kcontrol *kcontrol,
  1770. struct snd_ctl_elem_value *ucontrol)
  1771. {
  1772. int ret;
  1773. uint32_t zl, zr;
  1774. bool hphr;
  1775. struct soc_multi_mixer_control *mc;
  1776. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1777. struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
  1778. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1779. hphr = mc->shift;
  1780. ret = wcd_mbhc_get_impedance(&priv->mbhc, &zl, &zr);
  1781. if (ret)
  1782. dev_dbg(codec->dev, "%s: Failed to get mbhc imped", __func__);
  1783. dev_dbg(codec->dev, "%s: zl %u, zr %u\n", __func__, zl, zr);
  1784. ucontrol->value.integer.value[0] = hphr ? zr : zl;
  1785. return 0;
  1786. }
  1787. static const struct snd_kcontrol_new impedance_detect_controls[] = {
  1788. SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
  1789. tombak_hph_impedance_get, NULL),
  1790. SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
  1791. tombak_hph_impedance_get, NULL),
  1792. };
  1793. static int tombak_get_hph_type(struct snd_kcontrol *kcontrol,
  1794. struct snd_ctl_elem_value *ucontrol)
  1795. {
  1796. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1797. struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
  1798. struct wcd_mbhc *mbhc;
  1799. if (!priv) {
  1800. dev_err(codec->dev,
  1801. "%s: sdm660_cdc-wcd private data is NULL\n",
  1802. __func__);
  1803. return -EINVAL;
  1804. }
  1805. mbhc = &priv->mbhc;
  1806. if (!mbhc) {
  1807. dev_err(codec->dev, "%s: mbhc not initialized\n", __func__);
  1808. return -EINVAL;
  1809. }
  1810. ucontrol->value.integer.value[0] = (u32) mbhc->hph_type;
  1811. dev_dbg(codec->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type);
  1812. return 0;
  1813. }
  1814. static const struct snd_kcontrol_new hph_type_detect_controls[] = {
  1815. SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
  1816. tombak_get_hph_type, NULL),
  1817. };
  1818. static const char * const rdac2_mux_text[] = {
  1819. "ZERO", "RX2", "RX1"
  1820. };
  1821. static const struct snd_kcontrol_new adc1_switch =
  1822. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
  1823. static const struct soc_enum rdac2_mux_enum =
  1824. SOC_ENUM_SINGLE(MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL,
  1825. 0, 3, rdac2_mux_text);
  1826. static const char * const adc2_mux_text[] = {
  1827. "ZERO", "INP2", "INP3"
  1828. };
  1829. static const char * const ext_spk_text[] = {
  1830. "Off", "On"
  1831. };
  1832. static const char * const wsa_spk_text[] = {
  1833. "ZERO", "WSA"
  1834. };
  1835. static const struct soc_enum adc2_enum =
  1836. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1837. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1838. static const struct soc_enum ext_spk_enum =
  1839. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1840. ARRAY_SIZE(ext_spk_text), ext_spk_text);
  1841. static const struct soc_enum wsa_spk_enum =
  1842. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1843. ARRAY_SIZE(wsa_spk_text), wsa_spk_text);
  1844. static const struct snd_kcontrol_new ext_spk_mux =
  1845. SOC_DAPM_ENUM("Ext Spk Switch Mux", ext_spk_enum);
  1846. static const struct snd_kcontrol_new tx_adc2_mux =
  1847. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1848. static const struct snd_kcontrol_new rdac2_mux =
  1849. SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum);
  1850. static const char * const ear_text[] = {
  1851. "ZERO", "Switch",
  1852. };
  1853. static const struct soc_enum ear_enum =
  1854. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(ear_text), ear_text);
  1855. static const struct snd_kcontrol_new ear_pa_mux[] = {
  1856. SOC_DAPM_ENUM("EAR_S", ear_enum)
  1857. };
  1858. static const struct snd_kcontrol_new wsa_spk_mux[] = {
  1859. SOC_DAPM_ENUM("WSA Spk Switch", wsa_spk_enum)
  1860. };
  1861. static const char * const hph_text[] = {
  1862. "ZERO", "Switch",
  1863. };
  1864. static const struct soc_enum hph_enum =
  1865. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text);
  1866. static const struct snd_kcontrol_new hphl_mux[] = {
  1867. SOC_DAPM_ENUM("HPHL", hph_enum)
  1868. };
  1869. static const struct snd_kcontrol_new hphr_mux[] = {
  1870. SOC_DAPM_ENUM("HPHR", hph_enum)
  1871. };
  1872. static const struct snd_kcontrol_new spkr_mux[] = {
  1873. SOC_DAPM_ENUM("SPK", hph_enum)
  1874. };
  1875. static const char * const lo_text[] = {
  1876. "ZERO", "Switch",
  1877. };
  1878. static const struct soc_enum lo_enum =
  1879. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text);
  1880. static const struct snd_kcontrol_new lo_mux[] = {
  1881. SOC_DAPM_ENUM("LINE_OUT", lo_enum)
  1882. };
  1883. static void msm_anlg_cdc_codec_enable_adc_block(struct snd_soc_codec *codec,
  1884. int enable)
  1885. {
  1886. struct sdm660_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec);
  1887. dev_dbg(codec->dev, "%s %d\n", __func__, enable);
  1888. if (enable) {
  1889. wcd8x16->adc_count++;
  1890. snd_soc_update_bits(codec,
  1891. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL,
  1892. 0x20, 0x20);
  1893. snd_soc_update_bits(codec,
  1894. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1895. 0x10, 0x10);
  1896. } else {
  1897. wcd8x16->adc_count--;
  1898. if (!wcd8x16->adc_count) {
  1899. snd_soc_update_bits(codec,
  1900. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  1901. 0x10, 0x00);
  1902. snd_soc_update_bits(codec,
  1903. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL,
  1904. 0x20, 0x0);
  1905. }
  1906. }
  1907. }
  1908. static int msm_anlg_cdc_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1909. struct snd_kcontrol *kcontrol,
  1910. int event)
  1911. {
  1912. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1913. u16 adc_reg;
  1914. u8 init_bit_shift;
  1915. dev_dbg(codec->dev, "%s %d\n", __func__, event);
  1916. adc_reg = MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2;
  1917. if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN)
  1918. init_bit_shift = 5;
  1919. else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) ||
  1920. (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN))
  1921. init_bit_shift = 4;
  1922. else {
  1923. dev_err(codec->dev, "%s: Error, invalid adc register\n",
  1924. __func__);
  1925. return -EINVAL;
  1926. }
  1927. switch (event) {
  1928. case SND_SOC_DAPM_PRE_PMU:
  1929. msm_anlg_cdc_codec_enable_adc_block(codec, 1);
  1930. if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN)
  1931. snd_soc_update_bits(codec,
  1932. MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x02);
  1933. /*
  1934. * Add delay of 10 ms to give sufficient time for the voltage
  1935. * to shoot up and settle so that the txfe init does not
  1936. * happen when the input voltage is changing too much.
  1937. */
  1938. usleep_range(10000, 10010);
  1939. snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
  1940. 1 << init_bit_shift);
  1941. if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN)
  1942. snd_soc_update_bits(codec,
  1943. MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL,
  1944. 0x03, 0x00);
  1945. else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) ||
  1946. (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN))
  1947. snd_soc_update_bits(codec,
  1948. MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL,
  1949. 0x03, 0x00);
  1950. /* Wait for 1ms to allow txfe settling time */
  1951. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  1952. break;
  1953. case SND_SOC_DAPM_POST_PMU:
  1954. /*
  1955. * Add delay of 12 ms before deasserting the init
  1956. * to reduce the tx pop
  1957. */
  1958. usleep_range(12000, 12010);
  1959. snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
  1960. /* Wait for 1ms to allow txfe settling time post powerup */
  1961. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  1962. break;
  1963. case SND_SOC_DAPM_POST_PMD:
  1964. msm_anlg_cdc_codec_enable_adc_block(codec, 0);
  1965. if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN)
  1966. snd_soc_update_bits(codec,
  1967. MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x00);
  1968. if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN)
  1969. snd_soc_update_bits(codec,
  1970. MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL,
  1971. 0x03, 0x02);
  1972. else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) ||
  1973. (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN))
  1974. snd_soc_update_bits(codec,
  1975. MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL,
  1976. 0x03, 0x02);
  1977. break;
  1978. }
  1979. return 0;
  1980. }
  1981. static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
  1982. struct snd_kcontrol *kcontrol,
  1983. int event)
  1984. {
  1985. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1986. struct sdm660_cdc_priv *sdm660_cdc =
  1987. snd_soc_codec_get_drvdata(codec);
  1988. dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
  1989. switch (event) {
  1990. case SND_SOC_DAPM_PRE_PMU:
  1991. snd_soc_update_bits(codec,
  1992. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1993. snd_soc_update_bits(codec,
  1994. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
  1995. switch (sdm660_cdc->boost_option) {
  1996. case BOOST_SWITCH:
  1997. if (!sdm660_cdc->spk_boost_set)
  1998. snd_soc_update_bits(codec,
  1999. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
  2000. 0x10, 0x10);
  2001. break;
  2002. case BOOST_ALWAYS:
  2003. case BOOST_ON_FOREVER:
  2004. break;
  2005. case BYPASS_ALWAYS:
  2006. snd_soc_update_bits(codec,
  2007. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
  2008. 0x10, 0x10);
  2009. break;
  2010. default:
  2011. dev_err(codec->dev,
  2012. "%s: invalid boost option: %d\n", __func__,
  2013. sdm660_cdc->boost_option);
  2014. break;
  2015. }
  2016. /* Wait for 1ms after SPK_DAC CTL setting */
  2017. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  2018. snd_soc_update_bits(codec,
  2019. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
  2020. if (get_codec_version(sdm660_cdc) != TOMBAK_1_0)
  2021. snd_soc_update_bits(codec,
  2022. MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x01);
  2023. break;
  2024. case SND_SOC_DAPM_POST_PMU:
  2025. /* Wait for 1ms after SPK_VBAT_LDO Enable */
  2026. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  2027. switch (sdm660_cdc->boost_option) {
  2028. case BOOST_SWITCH:
  2029. if (sdm660_cdc->spk_boost_set)
  2030. snd_soc_update_bits(codec,
  2031. MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  2032. 0xEF, 0xEF);
  2033. else
  2034. snd_soc_update_bits(codec,
  2035. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
  2036. 0x10, 0x00);
  2037. break;
  2038. case BOOST_ALWAYS:
  2039. case BOOST_ON_FOREVER:
  2040. snd_soc_update_bits(codec,
  2041. MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  2042. 0xEF, 0xEF);
  2043. break;
  2044. case BYPASS_ALWAYS:
  2045. snd_soc_update_bits(codec,
  2046. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
  2047. break;
  2048. default:
  2049. dev_err(codec->dev,
  2050. "%s: invalid boost option: %d\n", __func__,
  2051. sdm660_cdc->boost_option);
  2052. break;
  2053. }
  2054. msm_anlg_cdc_dig_notifier_call(codec,
  2055. DIG_CDC_EVENT_RX3_MUTE_OFF);
  2056. snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
  2057. break;
  2058. case SND_SOC_DAPM_PRE_PMD:
  2059. msm_anlg_cdc_dig_notifier_call(codec,
  2060. DIG_CDC_EVENT_RX3_MUTE_ON);
  2061. /*
  2062. * Add 1 ms sleep for the mute to take effect
  2063. */
  2064. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  2065. snd_soc_update_bits(codec,
  2066. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
  2067. if (get_codec_version(sdm660_cdc) < CAJON_2_0)
  2068. msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD);
  2069. snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
  2070. switch (sdm660_cdc->boost_option) {
  2071. case BOOST_SWITCH:
  2072. if (sdm660_cdc->spk_boost_set)
  2073. snd_soc_update_bits(codec,
  2074. MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  2075. 0xEF, 0x69);
  2076. break;
  2077. case BOOST_ALWAYS:
  2078. case BOOST_ON_FOREVER:
  2079. snd_soc_update_bits(codec,
  2080. MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  2081. 0xEF, 0x69);
  2082. break;
  2083. case BYPASS_ALWAYS:
  2084. break;
  2085. default:
  2086. dev_err(codec->dev,
  2087. "%s: invalid boost option: %d\n", __func__,
  2088. sdm660_cdc->boost_option);
  2089. break;
  2090. }
  2091. break;
  2092. case SND_SOC_DAPM_POST_PMD:
  2093. snd_soc_update_bits(codec,
  2094. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00);
  2095. /* Wait for 1ms to allow setting time for spkr path disable */
  2096. usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
  2097. snd_soc_update_bits(codec,
  2098. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
  2099. snd_soc_update_bits(codec,
  2100. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
  2101. if (get_codec_version(sdm660_cdc) != TOMBAK_1_0)
  2102. snd_soc_update_bits(codec,
  2103. MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x00);
  2104. snd_soc_update_bits(codec,
  2105. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  2106. if (get_codec_version(sdm660_cdc) >= CAJON_2_0)
  2107. msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD);
  2108. break;
  2109. }
  2110. return 0;
  2111. }
  2112. static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
  2113. struct snd_kcontrol *kcontrol,
  2114. int event)
  2115. {
  2116. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2117. struct sdm660_cdc_priv *sdm660_cdc =
  2118. snd_soc_codec_get_drvdata(codec);
  2119. struct msm_asoc_mach_data *pdata = NULL;
  2120. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2121. dev_dbg(codec->dev, "%s event %d w->name %s\n", __func__,
  2122. event, w->name);
  2123. switch (event) {
  2124. case SND_SOC_DAPM_PRE_PMU:
  2125. msm_anlg_cdc_codec_enable_clock_block(codec, 1);
  2126. snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
  2127. msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMU);
  2128. break;
  2129. case SND_SOC_DAPM_POST_PMD:
  2130. if (sdm660_cdc->rx_bias_count == 0)
  2131. snd_soc_update_bits(codec,
  2132. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  2133. 0x80, 0x00);
  2134. }
  2135. return 0;
  2136. }
  2137. static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec)
  2138. {
  2139. struct sdm660_cdc_priv *sdm660_cdc =
  2140. snd_soc_codec_get_drvdata(codec);
  2141. if (get_codec_version(sdm660_cdc) < CAJON)
  2142. return true;
  2143. else
  2144. return false;
  2145. }
  2146. static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec,
  2147. bool enable)
  2148. {
  2149. struct sdm660_cdc_priv *sdm660_cdc =
  2150. snd_soc_codec_get_drvdata(codec);
  2151. if (get_codec_version(sdm660_cdc) < CONGA) {
  2152. if (enable)
  2153. /*
  2154. * Set autozeroing for special headset detection and
  2155. * buttons to work.
  2156. */
  2157. snd_soc_update_bits(codec,
  2158. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  2159. 0x18, 0x10);
  2160. else
  2161. snd_soc_update_bits(codec,
  2162. MSM89XX_PMIC_ANALOG_MICB_2_EN,
  2163. 0x18, 0x00);
  2164. } else {
  2165. dev_dbg(codec->dev,
  2166. "%s: Auto Zeroing is not required from CONGA\n",
  2167. __func__);
  2168. }
  2169. }
  2170. static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec)
  2171. {
  2172. struct sdm660_cdc_priv *sdm660_cdc =
  2173. snd_soc_codec_get_drvdata(codec);
  2174. if (get_codec_version(sdm660_cdc) == TOMBAK_1_0) {
  2175. pr_debug("%s: This device needs to be trimmed\n", __func__);
  2176. /*
  2177. * Calculate the trim value for each device used
  2178. * till is comes in production by hardware team
  2179. */
  2180. snd_soc_update_bits(codec,
  2181. MSM89XX_PMIC_ANALOG_SEC_ACCESS,
  2182. 0xA5, 0xA5);
  2183. snd_soc_update_bits(codec,
  2184. MSM89XX_PMIC_ANALOG_TRIM_CTRL2,
  2185. 0xFF, 0x30);
  2186. } else {
  2187. dev_dbg(codec->dev, "%s: This device is trimmed at ATE\n",
  2188. __func__);
  2189. }
  2190. }
  2191. static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc,
  2192. bool turn_on)
  2193. {
  2194. int ret = 0;
  2195. static int count;
  2196. struct snd_soc_codec *codec = wcd_mbhc->codec;
  2197. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  2198. dev_dbg(codec->dev, "%s turn_on: %d count: %d\n", __func__, turn_on,
  2199. count);
  2200. if (turn_on) {
  2201. if (!count) {
  2202. ret = snd_soc_dapm_force_enable_pin(dapm,
  2203. "MICBIAS_REGULATOR");
  2204. snd_soc_dapm_sync(dapm);
  2205. }
  2206. count++;
  2207. } else {
  2208. if (count > 0)
  2209. count--;
  2210. if (!count) {
  2211. ret = snd_soc_dapm_disable_pin(dapm,
  2212. "MICBIAS_REGULATOR");
  2213. snd_soc_dapm_sync(dapm);
  2214. }
  2215. }
  2216. if (ret)
  2217. dev_err(codec->dev, "%s: Failed to %s external micbias source\n",
  2218. __func__, turn_on ? "enable" : "disabled");
  2219. else
  2220. dev_dbg(codec->dev, "%s: %s external micbias source\n",
  2221. __func__, turn_on ? "Enabled" : "Disabled");
  2222. return ret;
  2223. }
  2224. static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2225. struct snd_kcontrol *kcontrol,
  2226. int event)
  2227. {
  2228. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2229. struct sdm660_cdc_priv *sdm660_cdc =
  2230. snd_soc_codec_get_drvdata(codec);
  2231. u16 micb_int_reg;
  2232. char *internal1_text = "Internal1";
  2233. char *internal2_text = "Internal2";
  2234. char *internal3_text = "Internal3";
  2235. char *external2_text = "External2";
  2236. char *external_text = "External";
  2237. bool micbias2;
  2238. dev_dbg(codec->dev, "%s %d\n", __func__, event);
  2239. switch (w->reg) {
  2240. case MSM89XX_PMIC_ANALOG_MICB_1_EN:
  2241. case MSM89XX_PMIC_ANALOG_MICB_2_EN:
  2242. micb_int_reg = MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS;
  2243. break;
  2244. default:
  2245. dev_err(codec->dev,
  2246. "%s: Error, invalid micbias register 0x%x\n",
  2247. __func__, w->reg);
  2248. return -EINVAL;
  2249. }
  2250. micbias2 = (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN) & 0x80);
  2251. switch (event) {
  2252. case SND_SOC_DAPM_PRE_PMU:
  2253. if (strnstr(w->name, internal1_text, strlen(w->name))) {
  2254. if (get_codec_version(sdm660_cdc) >= CAJON)
  2255. snd_soc_update_bits(codec,
  2256. MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2,
  2257. 0x02, 0x02);
  2258. snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x80);
  2259. } else if (strnstr(w->name, internal2_text, strlen(w->name))) {
  2260. snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x10);
  2261. snd_soc_update_bits(codec, w->reg, 0x60, 0x00);
  2262. } else if (strnstr(w->name, internal3_text, strlen(w->name))) {
  2263. snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x2);
  2264. /*
  2265. * update MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2
  2266. * for external bias only, not for external2.
  2267. */
  2268. } else if (!strnstr(w->name, external2_text, strlen(w->name)) &&
  2269. strnstr(w->name, external_text,
  2270. strlen(w->name))) {
  2271. snd_soc_update_bits(codec,
  2272. MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2,
  2273. 0x02, 0x02);
  2274. }
  2275. if (!strnstr(w->name, external_text, strlen(w->name)))
  2276. snd_soc_update_bits(codec,
  2277. MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x05, 0x04);
  2278. if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN)
  2279. msm_anlg_cdc_configure_cap(codec, true, micbias2);
  2280. break;
  2281. case SND_SOC_DAPM_POST_PMU:
  2282. if (get_codec_version(sdm660_cdc) <= TOMBAK_2_0)
  2283. /*
  2284. * Wait for 20ms post micbias enable
  2285. * for version < tombak 2.0.
  2286. */
  2287. usleep_range(20000, 20100);
  2288. if (strnstr(w->name, internal1_text, strlen(w->name))) {
  2289. snd_soc_update_bits(codec, micb_int_reg, 0x40, 0x40);
  2290. } else if (strnstr(w->name, internal2_text, strlen(w->name))) {
  2291. snd_soc_update_bits(codec, micb_int_reg, 0x08, 0x08);
  2292. msm_anlg_cdc_notifier_call(codec,
  2293. WCD_EVENT_POST_MICBIAS_2_ON);
  2294. } else if (strnstr(w->name, internal3_text, 30)) {
  2295. snd_soc_update_bits(codec, micb_int_reg, 0x01, 0x01);
  2296. } else if (strnstr(w->name, external2_text, strlen(w->name))) {
  2297. msm_anlg_cdc_notifier_call(codec,
  2298. WCD_EVENT_POST_MICBIAS_2_ON);
  2299. }
  2300. break;
  2301. case SND_SOC_DAPM_POST_PMD:
  2302. if (strnstr(w->name, internal1_text, strlen(w->name))) {
  2303. snd_soc_update_bits(codec, micb_int_reg, 0xC0, 0x40);
  2304. } else if (strnstr(w->name, internal2_text, strlen(w->name))) {
  2305. msm_anlg_cdc_notifier_call(codec,
  2306. WCD_EVENT_POST_MICBIAS_2_OFF);
  2307. } else if (strnstr(w->name, internal3_text, 30)) {
  2308. snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
  2309. } else if (strnstr(w->name, external2_text, strlen(w->name))) {
  2310. /*
  2311. * send micbias turn off event to mbhc driver and then
  2312. * break, as no need to set MICB_1_EN register.
  2313. */
  2314. msm_anlg_cdc_notifier_call(codec,
  2315. WCD_EVENT_POST_MICBIAS_2_OFF);
  2316. break;
  2317. }
  2318. if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN)
  2319. msm_anlg_cdc_configure_cap(codec, false, micbias2);
  2320. break;
  2321. }
  2322. return 0;
  2323. }
  2324. static void set_compander_mode(void *handle, int val)
  2325. {
  2326. struct sdm660_cdc_priv *handle_cdc = handle;
  2327. struct snd_soc_codec *codec = handle_cdc->codec;
  2328. if (get_codec_version(handle_cdc) >= DIANGU) {
  2329. snd_soc_update_bits(codec,
  2330. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  2331. 0x08, val);
  2332. };
  2333. }
  2334. static void update_clkdiv(void *handle, int val)
  2335. {
  2336. struct sdm660_cdc_priv *handle_cdc = handle;
  2337. struct snd_soc_codec *codec = handle_cdc->codec;
  2338. snd_soc_update_bits(codec,
  2339. MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV,
  2340. 0xFF, val);
  2341. }
  2342. static int get_cdc_version(void *handle)
  2343. {
  2344. struct sdm660_cdc_priv *sdm660_cdc = handle;
  2345. return get_codec_version(sdm660_cdc);
  2346. }
  2347. static int sdm660_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
  2348. struct snd_kcontrol *kcontrol,
  2349. int event)
  2350. {
  2351. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2352. struct sdm660_cdc_priv *sdm660_cdc =
  2353. snd_soc_codec_get_drvdata(codec);
  2354. int ret = 0;
  2355. if (!sdm660_cdc->ext_spk_boost_set) {
  2356. dev_dbg(codec->dev, "%s: ext_boost not supported/disabled\n",
  2357. __func__);
  2358. return 0;
  2359. }
  2360. dev_dbg(codec->dev, "%s: %s %d\n", __func__, w->name, event);
  2361. switch (event) {
  2362. case SND_SOC_DAPM_PRE_PMU:
  2363. if (sdm660_cdc->spkdrv_reg) {
  2364. ret = regulator_enable(sdm660_cdc->spkdrv_reg);
  2365. if (ret)
  2366. dev_err(codec->dev,
  2367. "%s Failed to enable spkdrv reg %s\n",
  2368. __func__, MSM89XX_VDD_SPKDRV_NAME);
  2369. }
  2370. break;
  2371. case SND_SOC_DAPM_POST_PMD:
  2372. if (sdm660_cdc->spkdrv_reg) {
  2373. ret = regulator_disable(sdm660_cdc->spkdrv_reg);
  2374. if (ret)
  2375. dev_err(codec->dev,
  2376. "%s: Failed to disable spkdrv_reg %s\n",
  2377. __func__, MSM89XX_VDD_SPKDRV_NAME);
  2378. }
  2379. break;
  2380. }
  2381. return 0;
  2382. }
  2383. /* The register address is the same as other codec so it can use resmgr */
  2384. static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
  2385. struct snd_kcontrol *kcontrol,
  2386. int event)
  2387. {
  2388. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2389. struct sdm660_cdc_priv *sdm660_cdc =
  2390. snd_soc_codec_get_drvdata(codec);
  2391. dev_dbg(codec->dev, "%s %d\n", __func__, event);
  2392. switch (event) {
  2393. case SND_SOC_DAPM_PRE_PMU:
  2394. sdm660_cdc->rx_bias_count++;
  2395. if (sdm660_cdc->rx_bias_count == 1) {
  2396. snd_soc_update_bits(codec,
  2397. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  2398. 0x80, 0x80);
  2399. snd_soc_update_bits(codec,
  2400. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  2401. 0x01, 0x01);
  2402. }
  2403. break;
  2404. case SND_SOC_DAPM_POST_PMD:
  2405. sdm660_cdc->rx_bias_count--;
  2406. if (sdm660_cdc->rx_bias_count == 0) {
  2407. snd_soc_update_bits(codec,
  2408. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  2409. 0x01, 0x00);
  2410. snd_soc_update_bits(codec,
  2411. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  2412. 0x80, 0x00);
  2413. }
  2414. break;
  2415. }
  2416. dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
  2417. __func__, sdm660_cdc->rx_bias_count);
  2418. return 0;
  2419. }
  2420. static uint32_t wcd_get_impedance_value(uint32_t imped)
  2421. {
  2422. int i;
  2423. for (i = 0; i < ARRAY_SIZE(wcd_imped_val) - 1; i++) {
  2424. if (imped >= wcd_imped_val[i] &&
  2425. imped < wcd_imped_val[i + 1])
  2426. break;
  2427. }
  2428. pr_debug("%s: selected impedance value = %d\n",
  2429. __func__, wcd_imped_val[i]);
  2430. return wcd_imped_val[i];
  2431. }
  2432. static void wcd_imped_config(struct snd_soc_codec *codec,
  2433. uint32_t imped, bool set_gain)
  2434. {
  2435. uint32_t value;
  2436. int codec_version;
  2437. struct sdm660_cdc_priv *sdm660_cdc =
  2438. snd_soc_codec_get_drvdata(codec);
  2439. value = wcd_get_impedance_value(imped);
  2440. if (value < wcd_imped_val[0]) {
  2441. dev_dbg(codec->dev,
  2442. "%s, detected impedance is less than 4 Ohm\n",
  2443. __func__);
  2444. return;
  2445. }
  2446. codec_version = get_codec_version(sdm660_cdc);
  2447. if (set_gain) {
  2448. switch (codec_version) {
  2449. case TOMBAK_1_0:
  2450. case TOMBAK_2_0:
  2451. case CONGA:
  2452. /*
  2453. * For 32Ohm load and higher loads, Set 0x19E
  2454. * bit 5 to 1 (POS_0_DB_DI). For loads lower
  2455. * than 32Ohm (such as 16Ohm load), Set 0x19E
  2456. * bit 5 to 0 (POS_M4P5_DB_DI)
  2457. */
  2458. if (value >= 32)
  2459. snd_soc_update_bits(codec,
  2460. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2461. 0x20, 0x20);
  2462. else
  2463. snd_soc_update_bits(codec,
  2464. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2465. 0x20, 0x00);
  2466. break;
  2467. case CAJON:
  2468. case CAJON_2_0:
  2469. case DIANGU:
  2470. case DRAX_CDC:
  2471. if (value >= 13) {
  2472. snd_soc_update_bits(codec,
  2473. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2474. 0x20, 0x20);
  2475. snd_soc_update_bits(codec,
  2476. MSM89XX_PMIC_ANALOG_NCP_VCTRL,
  2477. 0x07, 0x07);
  2478. } else {
  2479. snd_soc_update_bits(codec,
  2480. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2481. 0x20, 0x00);
  2482. snd_soc_update_bits(codec,
  2483. MSM89XX_PMIC_ANALOG_NCP_VCTRL,
  2484. 0x07, 0x04);
  2485. }
  2486. break;
  2487. }
  2488. } else {
  2489. snd_soc_update_bits(codec,
  2490. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2491. 0x20, 0x00);
  2492. snd_soc_update_bits(codec,
  2493. MSM89XX_PMIC_ANALOG_NCP_VCTRL,
  2494. 0x07, 0x04);
  2495. }
  2496. dev_dbg(codec->dev, "%s: Exit\n", __func__);
  2497. }
  2498. static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w,
  2499. struct snd_kcontrol *kcontrol,
  2500. int event)
  2501. {
  2502. uint32_t impedl, impedr;
  2503. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2504. struct sdm660_cdc_priv *sdm660_cdc =
  2505. snd_soc_codec_get_drvdata(codec);
  2506. int ret;
  2507. dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
  2508. ret = wcd_mbhc_get_impedance(&sdm660_cdc->mbhc,
  2509. &impedl, &impedr);
  2510. switch (event) {
  2511. case SND_SOC_DAPM_PRE_PMU:
  2512. if (get_codec_version(sdm660_cdc) > CAJON)
  2513. snd_soc_update_bits(codec,
  2514. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
  2515. 0x08, 0x08);
  2516. if (get_codec_version(sdm660_cdc) == CAJON ||
  2517. get_codec_version(sdm660_cdc) == CAJON_2_0) {
  2518. snd_soc_update_bits(codec,
  2519. MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST,
  2520. 0x80, 0x80);
  2521. snd_soc_update_bits(codec,
  2522. MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST,
  2523. 0x80, 0x80);
  2524. }
  2525. if (get_codec_version(sdm660_cdc) > CAJON)
  2526. snd_soc_update_bits(codec,
  2527. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
  2528. 0x08, 0x00);
  2529. if (sdm660_cdc->hph_mode == HD2_MODE)
  2530. msm_anlg_cdc_dig_notifier_call(codec,
  2531. DIG_CDC_EVENT_PRE_RX1_INT_ON);
  2532. snd_soc_update_bits(codec,
  2533. MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
  2534. snd_soc_update_bits(codec,
  2535. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  2536. snd_soc_update_bits(codec,
  2537. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  2538. if (!ret)
  2539. wcd_imped_config(codec, impedl, true);
  2540. else
  2541. dev_dbg(codec->dev, "Failed to get mbhc impedance %d\n",
  2542. ret);
  2543. break;
  2544. case SND_SOC_DAPM_POST_PMU:
  2545. snd_soc_update_bits(codec,
  2546. MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00);
  2547. break;
  2548. case SND_SOC_DAPM_POST_PMD:
  2549. wcd_imped_config(codec, impedl, false);
  2550. snd_soc_update_bits(codec,
  2551. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  2552. snd_soc_update_bits(codec,
  2553. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  2554. if (sdm660_cdc->hph_mode == HD2_MODE)
  2555. msm_anlg_cdc_dig_notifier_call(codec,
  2556. DIG_CDC_EVENT_POST_RX1_INT_OFF);
  2557. break;
  2558. }
  2559. return 0;
  2560. }
  2561. static int msm_anlg_cdc_lo_dac_event(struct snd_soc_dapm_widget *w,
  2562. struct snd_kcontrol *kcontrol,
  2563. int event)
  2564. {
  2565. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2566. dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
  2567. switch (event) {
  2568. case SND_SOC_DAPM_PRE_PMU:
  2569. snd_soc_update_bits(codec,
  2570. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2571. snd_soc_update_bits(codec,
  2572. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x20);
  2573. snd_soc_update_bits(codec,
  2574. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x80);
  2575. snd_soc_update_bits(codec,
  2576. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x08);
  2577. snd_soc_update_bits(codec,
  2578. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x40);
  2579. break;
  2580. case SND_SOC_DAPM_POST_PMU:
  2581. snd_soc_update_bits(codec,
  2582. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x80);
  2583. snd_soc_update_bits(codec,
  2584. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00);
  2585. snd_soc_update_bits(codec,
  2586. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x40);
  2587. break;
  2588. case SND_SOC_DAPM_POST_PMD:
  2589. /* Wait for 20ms before powerdown of lineout_dac */
  2590. usleep_range(20000, 20100);
  2591. snd_soc_update_bits(codec,
  2592. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x00);
  2593. snd_soc_update_bits(codec,
  2594. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x00);
  2595. snd_soc_update_bits(codec,
  2596. MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00);
  2597. snd_soc_update_bits(codec,
  2598. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x00);
  2599. snd_soc_update_bits(codec,
  2600. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x00);
  2601. snd_soc_update_bits(codec,
  2602. MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x00);
  2603. snd_soc_update_bits(codec,
  2604. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  2605. break;
  2606. }
  2607. return 0;
  2608. }
  2609. static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w,
  2610. struct snd_kcontrol *kcontrol,
  2611. int event)
  2612. {
  2613. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2614. struct sdm660_cdc_priv *sdm660_cdc =
  2615. snd_soc_codec_get_drvdata(codec);
  2616. dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
  2617. switch (event) {
  2618. case SND_SOC_DAPM_PRE_PMU:
  2619. if (sdm660_cdc->hph_mode == HD2_MODE)
  2620. msm_anlg_cdc_dig_notifier_call(codec,
  2621. DIG_CDC_EVENT_PRE_RX2_INT_ON);
  2622. snd_soc_update_bits(codec,
  2623. MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
  2624. snd_soc_update_bits(codec,
  2625. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  2626. snd_soc_update_bits(codec,
  2627. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  2628. break;
  2629. case SND_SOC_DAPM_POST_PMU:
  2630. snd_soc_update_bits(codec,
  2631. MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00);
  2632. break;
  2633. case SND_SOC_DAPM_POST_PMD:
  2634. snd_soc_update_bits(codec,
  2635. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  2636. snd_soc_update_bits(codec,
  2637. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
  2638. if (sdm660_cdc->hph_mode == HD2_MODE)
  2639. msm_anlg_cdc_dig_notifier_call(codec,
  2640. DIG_CDC_EVENT_POST_RX2_INT_OFF);
  2641. break;
  2642. }
  2643. return 0;
  2644. }
  2645. static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w,
  2646. struct snd_kcontrol *kcontrol,
  2647. int event)
  2648. {
  2649. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2650. struct sdm660_cdc_priv *sdm660_cdc =
  2651. snd_soc_codec_get_drvdata(codec);
  2652. dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
  2653. switch (event) {
  2654. case SND_SOC_DAPM_PRE_PMU:
  2655. if (w->shift == 5)
  2656. msm_anlg_cdc_notifier_call(codec,
  2657. WCD_EVENT_PRE_HPHL_PA_ON);
  2658. else if (w->shift == 4)
  2659. msm_anlg_cdc_notifier_call(codec,
  2660. WCD_EVENT_PRE_HPHR_PA_ON);
  2661. snd_soc_update_bits(codec,
  2662. MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x20, 0x20);
  2663. break;
  2664. case SND_SOC_DAPM_POST_PMU:
  2665. /* Wait for 7ms to allow setting time for HPH_PA Enable */
  2666. usleep_range(7000, 7100);
  2667. if (w->shift == 5) {
  2668. snd_soc_update_bits(codec,
  2669. MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
  2670. msm_anlg_cdc_dig_notifier_call(codec,
  2671. DIG_CDC_EVENT_RX1_MUTE_OFF);
  2672. } else if (w->shift == 4) {
  2673. snd_soc_update_bits(codec,
  2674. MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
  2675. msm_anlg_cdc_dig_notifier_call(codec,
  2676. DIG_CDC_EVENT_RX2_MUTE_OFF);
  2677. }
  2678. break;
  2679. case SND_SOC_DAPM_PRE_PMD:
  2680. if (w->shift == 5) {
  2681. msm_anlg_cdc_dig_notifier_call(codec,
  2682. DIG_CDC_EVENT_RX1_MUTE_ON);
  2683. /* Wait for 20ms after HPHL RX digital mute */
  2684. msleep(20);
  2685. snd_soc_update_bits(codec,
  2686. MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x00);
  2687. msm_anlg_cdc_notifier_call(codec,
  2688. WCD_EVENT_PRE_HPHL_PA_OFF);
  2689. } else if (w->shift == 4) {
  2690. msm_anlg_cdc_dig_notifier_call(codec,
  2691. DIG_CDC_EVENT_RX2_MUTE_ON);
  2692. /* Wait for 20ms after HPHR RX digital mute */
  2693. msleep(20);
  2694. snd_soc_update_bits(codec,
  2695. MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x00);
  2696. msm_anlg_cdc_notifier_call(codec,
  2697. WCD_EVENT_PRE_HPHR_PA_OFF);
  2698. }
  2699. if (get_codec_version(sdm660_cdc) >= CAJON) {
  2700. snd_soc_update_bits(codec,
  2701. MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP,
  2702. 0xF0, 0x30);
  2703. }
  2704. break;
  2705. case SND_SOC_DAPM_POST_PMD:
  2706. if (w->shift == 5) {
  2707. clear_bit(WCD_MBHC_HPHL_PA_OFF_ACK,
  2708. &sdm660_cdc->mbhc.hph_pa_dac_state);
  2709. msm_anlg_cdc_notifier_call(codec,
  2710. WCD_EVENT_POST_HPHL_PA_OFF);
  2711. } else if (w->shift == 4) {
  2712. clear_bit(WCD_MBHC_HPHR_PA_OFF_ACK,
  2713. &sdm660_cdc->mbhc.hph_pa_dac_state);
  2714. msm_anlg_cdc_notifier_call(codec,
  2715. WCD_EVENT_POST_HPHR_PA_OFF);
  2716. }
  2717. /* Wait for 15ms after HPH RX teardown */
  2718. usleep_range(15000, 15100);
  2719. break;
  2720. }
  2721. return 0;
  2722. }
  2723. static const struct snd_soc_dapm_route audio_map[] = {
  2724. /* RDAC Connections */
  2725. {"HPHR DAC", NULL, "RDAC2 MUX"},
  2726. {"RDAC2 MUX", "RX1", "PDM_IN_RX1"},
  2727. {"RDAC2 MUX", "RX2", "PDM_IN_RX2"},
  2728. /* WSA */
  2729. {"WSA_SPK OUT", NULL, "WSA Spk Switch"},
  2730. {"WSA Spk Switch", "WSA", "EAR PA"},
  2731. /* Earpiece (RX MIX1) */
  2732. {"EAR", NULL, "EAR_S"},
  2733. {"EAR_S", "Switch", "EAR PA"},
  2734. {"EAR PA", NULL, "RX_BIAS"},
  2735. {"EAR PA", NULL, "HPHL DAC"},
  2736. {"EAR PA", NULL, "HPHR DAC"},
  2737. {"EAR PA", NULL, "EAR CP"},
  2738. /* Headset (RX MIX1 and RX MIX2) */
  2739. {"HEADPHONE", NULL, "HPHL PA"},
  2740. {"HEADPHONE", NULL, "HPHR PA"},
  2741. {"Ext Spk", NULL, "Ext Spk Switch"},
  2742. {"Ext Spk Switch", "On", "HPHL PA"},
  2743. {"Ext Spk Switch", "On", "HPHR PA"},
  2744. {"HPHL PA", NULL, "HPHL"},
  2745. {"HPHR PA", NULL, "HPHR"},
  2746. {"HPHL", "Switch", "HPHL DAC"},
  2747. {"HPHR", "Switch", "HPHR DAC"},
  2748. {"HPHL PA", NULL, "CP"},
  2749. {"HPHL PA", NULL, "RX_BIAS"},
  2750. {"HPHR PA", NULL, "CP"},
  2751. {"HPHR PA", NULL, "RX_BIAS"},
  2752. {"HPHL DAC", NULL, "PDM_IN_RX1"},
  2753. {"SPK_OUT", NULL, "SPK PA"},
  2754. {"SPK PA", NULL, "SPK_RX_BIAS"},
  2755. {"SPK PA", NULL, "SPK"},
  2756. {"SPK", "Switch", "SPK DAC"},
  2757. {"SPK DAC", NULL, "PDM_IN_RX3"},
  2758. {"SPK DAC", NULL, "VDD_SPKDRV"},
  2759. /* lineout */
  2760. {"LINEOUT", NULL, "LINEOUT PA"},
  2761. {"LINEOUT PA", NULL, "SPK_RX_BIAS"},
  2762. {"LINEOUT PA", NULL, "LINE_OUT"},
  2763. {"LINE_OUT", "Switch", "LINEOUT DAC"},
  2764. {"LINEOUT DAC", NULL, "PDM_IN_RX3"},
  2765. /* lineout to WSA */
  2766. {"WSA_SPK OUT", NULL, "LINEOUT PA"},
  2767. {"PDM_IN_RX1", NULL, "RX1 CLK"},
  2768. {"PDM_IN_RX2", NULL, "RX2 CLK"},
  2769. {"PDM_IN_RX3", NULL, "RX3 CLK"},
  2770. {"ADC1_OUT", NULL, "ADC1"},
  2771. {"ADC2_OUT", NULL, "ADC2"},
  2772. {"ADC3_OUT", NULL, "ADC3"},
  2773. /* ADC Connections */
  2774. {"ADC2", NULL, "ADC2 MUX"},
  2775. {"ADC3", NULL, "ADC2 MUX"},
  2776. {"ADC2 MUX", "INP2", "ADC2_INP2"},
  2777. {"ADC2 MUX", "INP3", "ADC2_INP3"},
  2778. {"ADC1", NULL, "ADC1_INP1"},
  2779. {"ADC1_INP1", "Switch", "AMIC1"},
  2780. {"ADC2_INP2", NULL, "AMIC2"},
  2781. {"ADC2_INP3", NULL, "AMIC3"},
  2782. {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
  2783. {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
  2784. {"MIC BIAS External", NULL, "INT_LDO_H"},
  2785. {"MIC BIAS External2", NULL, "INT_LDO_H"},
  2786. {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"},
  2787. {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"},
  2788. {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"},
  2789. {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"},
  2790. };
  2791. static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream,
  2792. struct snd_soc_dai *dai)
  2793. {
  2794. struct sdm660_cdc_priv *sdm660_cdc =
  2795. snd_soc_codec_get_drvdata(dai->codec);
  2796. dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
  2797. __func__,
  2798. substream->name, substream->stream);
  2799. /*
  2800. * If status_mask is BUS_DOWN it means SSR is not complete.
  2801. * So return error.
  2802. */
  2803. if (test_bit(BUS_DOWN, &sdm660_cdc->status_mask)) {
  2804. dev_err(dai->codec->dev, "Error, Device is not up post SSR\n");
  2805. return -EINVAL;
  2806. }
  2807. return 0;
  2808. }
  2809. static void msm_anlg_cdc_shutdown(struct snd_pcm_substream *substream,
  2810. struct snd_soc_dai *dai)
  2811. {
  2812. dev_dbg(dai->codec->dev,
  2813. "%s(): substream = %s stream = %d\n", __func__,
  2814. substream->name, substream->stream);
  2815. }
  2816. int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
  2817. int mclk_enable, bool dapm)
  2818. {
  2819. struct sdm660_cdc_priv *sdm660_cdc =
  2820. snd_soc_codec_get_drvdata(codec);
  2821. dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n",
  2822. __func__, mclk_enable, dapm);
  2823. if (mclk_enable) {
  2824. sdm660_cdc->int_mclk0_enabled = true;
  2825. msm_anlg_cdc_codec_enable_clock_block(codec, 1);
  2826. } else {
  2827. if (!sdm660_cdc->int_mclk0_enabled) {
  2828. dev_err(codec->dev, "Error, MCLK already diabled\n");
  2829. return -EINVAL;
  2830. }
  2831. sdm660_cdc->int_mclk0_enabled = false;
  2832. msm_anlg_cdc_codec_enable_clock_block(codec, 0);
  2833. }
  2834. return 0;
  2835. }
  2836. EXPORT_SYMBOL(msm_anlg_cdc_mclk_enable);
  2837. static int msm_anlg_cdc_set_dai_sysclk(struct snd_soc_dai *dai,
  2838. int clk_id, unsigned int freq, int dir)
  2839. {
  2840. dev_dbg(dai->codec->dev, "%s\n", __func__);
  2841. return 0;
  2842. }
  2843. static int msm_anlg_cdc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2844. {
  2845. dev_dbg(dai->codec->dev, "%s\n", __func__);
  2846. return 0;
  2847. }
  2848. static int msm_anlg_cdc_set_channel_map(struct snd_soc_dai *dai,
  2849. unsigned int tx_num, unsigned int *tx_slot,
  2850. unsigned int rx_num, unsigned int *rx_slot)
  2851. {
  2852. dev_dbg(dai->codec->dev, "%s\n", __func__);
  2853. return 0;
  2854. }
  2855. static int msm_anlg_cdc_get_channel_map(struct snd_soc_dai *dai,
  2856. unsigned int *tx_num, unsigned int *tx_slot,
  2857. unsigned int *rx_num, unsigned int *rx_slot)
  2858. {
  2859. dev_dbg(dai->codec->dev, "%s\n", __func__);
  2860. return 0;
  2861. }
  2862. static struct snd_soc_dai_ops msm_anlg_cdc_dai_ops = {
  2863. .startup = msm_anlg_cdc_startup,
  2864. .shutdown = msm_anlg_cdc_shutdown,
  2865. .set_sysclk = msm_anlg_cdc_set_dai_sysclk,
  2866. .set_fmt = msm_anlg_cdc_set_dai_fmt,
  2867. .set_channel_map = msm_anlg_cdc_set_channel_map,
  2868. .get_channel_map = msm_anlg_cdc_get_channel_map,
  2869. };
  2870. static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = {
  2871. {
  2872. .name = "msm_anlg_cdc_i2s_rx1",
  2873. .id = AIF1_PB,
  2874. .playback = {
  2875. .stream_name = "PDM Playback",
  2876. .rates = SDM660_CDC_RATES,
  2877. .formats = SDM660_CDC_FORMATS,
  2878. .rate_max = 192000,
  2879. .rate_min = 8000,
  2880. .channels_min = 1,
  2881. .channels_max = 3,
  2882. },
  2883. .ops = &msm_anlg_cdc_dai_ops,
  2884. },
  2885. {
  2886. .name = "msm_anlg_cdc_i2s_tx1",
  2887. .id = AIF1_CAP,
  2888. .capture = {
  2889. .stream_name = "PDM Capture",
  2890. .rates = SDM660_CDC_RATES,
  2891. .formats = SDM660_CDC_FORMATS,
  2892. .rate_max = 48000,
  2893. .rate_min = 8000,
  2894. .channels_min = 1,
  2895. .channels_max = 4,
  2896. },
  2897. .ops = &msm_anlg_cdc_dai_ops,
  2898. },
  2899. {
  2900. .name = "msm_anlg_cdc_i2s_tx2",
  2901. .id = AIF3_SVA,
  2902. .capture = {
  2903. .stream_name = "RecordSVA",
  2904. .rates = SDM660_CDC_RATES,
  2905. .formats = SDM660_CDC_FORMATS,
  2906. .rate_max = 48000,
  2907. .rate_min = 8000,
  2908. .channels_min = 1,
  2909. .channels_max = 2,
  2910. },
  2911. .ops = &msm_anlg_cdc_dai_ops,
  2912. },
  2913. {
  2914. .name = "msm_anlg_vifeedback",
  2915. .id = AIF2_VIFEED,
  2916. .capture = {
  2917. .stream_name = "VIfeed",
  2918. .rates = SDM660_CDC_RATES,
  2919. .formats = SDM660_CDC_FORMATS,
  2920. .rate_max = 48000,
  2921. .rate_min = 48000,
  2922. .channels_min = 2,
  2923. .channels_max = 2,
  2924. },
  2925. .ops = &msm_anlg_cdc_dai_ops,
  2926. },
  2927. };
  2928. static int msm_anlg_cdc_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
  2929. struct snd_kcontrol *kcontrol,
  2930. int event)
  2931. {
  2932. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2933. dev_dbg(codec->dev, "%s: %d %s\n", __func__, event, w->name);
  2934. switch (event) {
  2935. case SND_SOC_DAPM_POST_PMU:
  2936. msm_anlg_cdc_dig_notifier_call(codec,
  2937. DIG_CDC_EVENT_RX3_MUTE_OFF);
  2938. break;
  2939. case SND_SOC_DAPM_POST_PMD:
  2940. msm_anlg_cdc_dig_notifier_call(codec,
  2941. DIG_CDC_EVENT_RX3_MUTE_ON);
  2942. break;
  2943. }
  2944. return 0;
  2945. }
  2946. static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w,
  2947. struct snd_kcontrol *kcontrol,
  2948. int event)
  2949. {
  2950. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2951. struct sdm660_cdc_priv *sdm660_cdc =
  2952. snd_soc_codec_get_drvdata(codec);
  2953. dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
  2954. switch (event) {
  2955. case SND_SOC_DAPM_POST_PMU:
  2956. dev_dbg(codec->dev,
  2957. "%s: enable external speaker PA\n", __func__);
  2958. if (sdm660_cdc->codec_spk_ext_pa_cb)
  2959. sdm660_cdc->codec_spk_ext_pa_cb(codec, 1);
  2960. break;
  2961. case SND_SOC_DAPM_PRE_PMD:
  2962. dev_dbg(codec->dev,
  2963. "%s: enable external speaker PA\n", __func__);
  2964. if (sdm660_cdc->codec_spk_ext_pa_cb)
  2965. sdm660_cdc->codec_spk_ext_pa_cb(codec, 0);
  2966. break;
  2967. }
  2968. return 0;
  2969. }
  2970. static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  2971. struct snd_kcontrol *kcontrol,
  2972. int event)
  2973. {
  2974. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2975. struct sdm660_cdc_priv *sdm660_cdc =
  2976. snd_soc_codec_get_drvdata(codec);
  2977. switch (event) {
  2978. case SND_SOC_DAPM_PRE_PMU:
  2979. dev_dbg(codec->dev,
  2980. "%s: Sleeping 20ms after select EAR PA\n",
  2981. __func__);
  2982. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  2983. 0x80, 0x80);
  2984. if (get_codec_version(sdm660_cdc) < CONGA)
  2985. snd_soc_update_bits(codec,
  2986. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x2A);
  2987. if (get_codec_version(sdm660_cdc) >= DIANGU) {
  2988. snd_soc_update_bits(codec,
  2989. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x00);
  2990. snd_soc_update_bits(codec,
  2991. MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
  2992. snd_soc_update_bits(codec,
  2993. MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
  2994. }
  2995. break;
  2996. case SND_SOC_DAPM_POST_PMU:
  2997. dev_dbg(codec->dev,
  2998. "%s: Sleeping 20ms after enabling EAR PA\n",
  2999. __func__);
  3000. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  3001. 0x40, 0x40);
  3002. /* Wait for 7ms after EAR PA enable */
  3003. usleep_range(7000, 7100);
  3004. msm_anlg_cdc_dig_notifier_call(codec,
  3005. DIG_CDC_EVENT_RX1_MUTE_OFF);
  3006. break;
  3007. case SND_SOC_DAPM_PRE_PMD:
  3008. msm_anlg_cdc_dig_notifier_call(codec,
  3009. DIG_CDC_EVENT_RX1_MUTE_ON);
  3010. /* Wait for 20ms for RX digital mute to take effect */
  3011. msleep(20);
  3012. if (sdm660_cdc->boost_option == BOOST_ALWAYS) {
  3013. dev_dbg(codec->dev,
  3014. "%s: boost_option:%d, tear down ear\n",
  3015. __func__, sdm660_cdc->boost_option);
  3016. msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD);
  3017. }
  3018. if (get_codec_version(sdm660_cdc) >= DIANGU) {
  3019. snd_soc_update_bits(codec,
  3020. MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x0);
  3021. snd_soc_update_bits(codec,
  3022. MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x0);
  3023. }
  3024. break;
  3025. case SND_SOC_DAPM_POST_PMD:
  3026. dev_dbg(codec->dev,
  3027. "%s: Sleeping 7ms after disabling EAR PA\n",
  3028. __func__);
  3029. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  3030. 0x40, 0x00);
  3031. /* Wait for 7ms after EAR PA teardown */
  3032. usleep_range(7000, 7100);
  3033. if (get_codec_version(sdm660_cdc) < CONGA)
  3034. snd_soc_update_bits(codec,
  3035. MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x16);
  3036. if (get_codec_version(sdm660_cdc) >= DIANGU)
  3037. snd_soc_update_bits(codec,
  3038. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x08);
  3039. break;
  3040. }
  3041. return 0;
  3042. }
  3043. static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = {
  3044. SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
  3045. 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_ear_pa,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3047. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_PGA_E("HPHL PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
  3049. 5, 0, NULL, 0,
  3050. msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
  3051. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
  3052. SND_SOC_DAPM_POST_PMD),
  3053. SND_SOC_DAPM_PGA_E("HPHR PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
  3054. 4, 0, NULL, 0,
  3055. msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
  3056. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
  3057. SND_SOC_DAPM_POST_PMD),
  3058. SND_SOC_DAPM_PGA_E("SPK PA", SND_SOC_NOPM,
  3059. 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_spk_pa,
  3060. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3061. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3062. SND_SOC_DAPM_PGA_E("LINEOUT PA", MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL,
  3063. 5, 0, NULL, 0, msm_anlg_cdc_codec_enable_lo_pa,
  3064. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3065. SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, ear_pa_mux),
  3066. SND_SOC_DAPM_MUX("SPK", SND_SOC_NOPM, 0, 0, spkr_mux),
  3067. SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux),
  3068. SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux),
  3069. SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
  3070. SND_SOC_DAPM_MUX("WSA Spk Switch", SND_SOC_NOPM, 0, 0, wsa_spk_mux),
  3071. SND_SOC_DAPM_MUX("Ext Spk Switch", SND_SOC_NOPM, 0, 0, &ext_spk_mux),
  3072. SND_SOC_DAPM_MUX("LINE_OUT", SND_SOC_NOPM, 0, 0, lo_mux),
  3073. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
  3074. SND_SOC_DAPM_MIXER_E("HPHL DAC",
  3075. MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
  3076. 0, msm_anlg_cdc_hphl_dac_event,
  3077. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3078. SND_SOC_DAPM_POST_PMD),
  3079. SND_SOC_DAPM_MIXER_E("HPHR DAC",
  3080. MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
  3081. 0, msm_anlg_cdc_hphr_dac_event,
  3082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3083. SND_SOC_DAPM_POST_PMD),
  3084. SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3085. SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3086. SND_SOC_DAPM_DAC("SPK DAC", NULL, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
  3087. 7, 0),
  3088. SND_SOC_DAPM_DAC_E("LINEOUT DAC", NULL,
  3089. SND_SOC_NOPM, 0, 0, msm_anlg_cdc_lo_dac_event,
  3090. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3091. SND_SOC_DAPM_POST_PMD),
  3092. SND_SOC_DAPM_SPK("Ext Spk", msm_anlg_cdc_codec_enable_spk_ext_pa),
  3093. SND_SOC_DAPM_SWITCH("ADC1_INP1", SND_SOC_NOPM, 0, 0,
  3094. &adc1_switch),
  3095. SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  3096. 0, 0, NULL, 0),
  3097. SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  3098. 1, 0, NULL, 0),
  3099. SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  3100. 2, 0, msm_anlg_cdc_codec_enable_dig_clk,
  3101. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3102. SND_SOC_DAPM_SUPPLY("CP", MSM89XX_PMIC_ANALOG_NCP_EN, 0, 0,
  3103. msm_anlg_cdc_codec_enable_charge_pump,
  3104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3105. SND_SOC_DAPM_POST_PMD),
  3106. SND_SOC_DAPM_SUPPLY("EAR CP", MSM89XX_PMIC_ANALOG_NCP_EN, 4, 0,
  3107. msm_anlg_cdc_codec_enable_charge_pump,
  3108. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3109. SND_SOC_DAPM_POST_PMD),
  3110. SND_SOC_DAPM_SUPPLY_S("RX_BIAS", 1, SND_SOC_NOPM,
  3111. 0, 0, msm_anlg_cdc_codec_enable_rx_bias,
  3112. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3113. SND_SOC_DAPM_SUPPLY_S("SPK_RX_BIAS", 1, SND_SOC_NOPM, 0, 0,
  3114. msm_anlg_cdc_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
  3115. SND_SOC_DAPM_POST_PMD),
  3116. SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0,
  3117. sdm660_wcd_codec_enable_vdd_spkr,
  3118. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3119. SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
  3120. SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM,
  3121. ON_DEMAND_MICBIAS, 0,
  3122. msm_anlg_cdc_codec_enable_on_demand_supply,
  3123. SND_SOC_DAPM_PRE_PMU |
  3124. SND_SOC_DAPM_POST_PMD),
  3125. SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal1",
  3126. MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0,
  3127. msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  3128. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3129. SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal2",
  3130. MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0,
  3131. msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  3132. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3133. SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal3",
  3134. MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0,
  3135. msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  3136. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3137. SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM89XX_PMIC_ANALOG_TX_1_EN, 7, 0,
  3138. msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  3139. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3140. SND_SOC_DAPM_ADC_E("ADC2_INP2",
  3141. NULL, MSM89XX_PMIC_ANALOG_TX_2_EN, 7, 0,
  3142. msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  3143. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3144. SND_SOC_DAPM_ADC_E("ADC2_INP3",
  3145. NULL, MSM89XX_PMIC_ANALOG_TX_3_EN, 7, 0,
  3146. msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  3147. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3148. SND_SOC_DAPM_MICBIAS_E("MIC BIAS External",
  3149. MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0,
  3150. msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  3151. SND_SOC_DAPM_POST_PMD),
  3152. SND_SOC_DAPM_MICBIAS_E("MIC BIAS External2",
  3153. MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0,
  3154. msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_POST_PMU |
  3155. SND_SOC_DAPM_POST_PMD),
  3156. SND_SOC_DAPM_INPUT("AMIC1"),
  3157. SND_SOC_DAPM_INPUT("AMIC2"),
  3158. SND_SOC_DAPM_INPUT("AMIC3"),
  3159. SND_SOC_DAPM_AIF_IN("PDM_IN_RX1", "PDM Playback",
  3160. 0, SND_SOC_NOPM, 0, 0),
  3161. SND_SOC_DAPM_AIF_IN("PDM_IN_RX2", "PDM Playback",
  3162. 0, SND_SOC_NOPM, 0, 0),
  3163. SND_SOC_DAPM_AIF_IN("PDM_IN_RX3", "PDM Playback",
  3164. 0, SND_SOC_NOPM, 0, 0),
  3165. SND_SOC_DAPM_OUTPUT("EAR"),
  3166. SND_SOC_DAPM_OUTPUT("WSA_SPK OUT"),
  3167. SND_SOC_DAPM_OUTPUT("HEADPHONE"),
  3168. SND_SOC_DAPM_OUTPUT("SPK_OUT"),
  3169. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  3170. SND_SOC_DAPM_AIF_OUT("ADC1_OUT", "PDM Capture",
  3171. 0, SND_SOC_NOPM, 0, 0),
  3172. SND_SOC_DAPM_AIF_OUT("ADC2_OUT", "PDM Capture",
  3173. 0, SND_SOC_NOPM, 0, 0),
  3174. SND_SOC_DAPM_AIF_OUT("ADC3_OUT", "PDM Capture",
  3175. 0, SND_SOC_NOPM, 0, 0),
  3176. };
  3177. static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = {
  3178. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
  3179. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82),
  3180. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
  3181. };
  3182. static const struct sdm660_cdc_reg_mask_val
  3183. msm_anlg_cdc_reg_defaults_2_0[] = {
  3184. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
  3185. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
  3186. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4F),
  3187. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28),
  3188. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69),
  3189. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01),
  3190. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x5F),
  3191. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x88),
  3192. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
  3193. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F),
  3194. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82),
  3195. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
  3196. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
  3197. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
  3198. };
  3199. static const struct sdm660_cdc_reg_mask_val conga_wcd_reg_defaults[] = {
  3200. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
  3201. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
  3202. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
  3203. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F),
  3204. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C),
  3205. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28),
  3206. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69),
  3207. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01),
  3208. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x0A),
  3209. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
  3210. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
  3211. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
  3212. };
  3213. static const struct sdm660_cdc_reg_mask_val cajon_wcd_reg_defaults[] = {
  3214. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
  3215. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
  3216. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
  3217. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F),
  3218. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C),
  3219. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82),
  3220. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8),
  3221. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4),
  3222. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41),
  3223. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69),
  3224. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01),
  3225. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
  3226. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
  3227. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA),
  3228. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
  3229. };
  3230. static const struct sdm660_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
  3231. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
  3232. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
  3233. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
  3234. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F),
  3235. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C),
  3236. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2),
  3237. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8),
  3238. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4),
  3239. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41),
  3240. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69),
  3241. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01),
  3242. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
  3243. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
  3244. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x10),
  3245. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x18),
  3246. MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA),
  3247. MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
  3248. };
  3249. static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec)
  3250. {
  3251. u32 i, version;
  3252. struct sdm660_cdc_priv *sdm660_cdc =
  3253. snd_soc_codec_get_drvdata(codec);
  3254. version = get_codec_version(sdm660_cdc);
  3255. if (version == TOMBAK_1_0) {
  3256. for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults); i++)
  3257. snd_soc_write(codec, msm_anlg_cdc_reg_defaults[i].reg,
  3258. msm_anlg_cdc_reg_defaults[i].val);
  3259. } else if (version == TOMBAK_2_0) {
  3260. for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults_2_0); i++)
  3261. snd_soc_write(codec,
  3262. msm_anlg_cdc_reg_defaults_2_0[i].reg,
  3263. msm_anlg_cdc_reg_defaults_2_0[i].val);
  3264. } else if (version == CONGA) {
  3265. for (i = 0; i < ARRAY_SIZE(conga_wcd_reg_defaults); i++)
  3266. snd_soc_write(codec,
  3267. conga_wcd_reg_defaults[i].reg,
  3268. conga_wcd_reg_defaults[i].val);
  3269. } else if (version == CAJON) {
  3270. for (i = 0; i < ARRAY_SIZE(cajon_wcd_reg_defaults); i++)
  3271. snd_soc_write(codec,
  3272. cajon_wcd_reg_defaults[i].reg,
  3273. cajon_wcd_reg_defaults[i].val);
  3274. } else if (version == CAJON_2_0 || version == DIANGU
  3275. || version == DRAX_CDC) {
  3276. for (i = 0; i < ARRAY_SIZE(cajon2p0_wcd_reg_defaults); i++)
  3277. snd_soc_write(codec,
  3278. cajon2p0_wcd_reg_defaults[i].reg,
  3279. cajon2p0_wcd_reg_defaults[i].val);
  3280. }
  3281. }
  3282. static const struct sdm660_cdc_reg_mask_val
  3283. msm_anlg_cdc_codec_reg_init_val[] = {
  3284. /* Initialize current threshold to 350MA
  3285. * number of wait and run cycles to 4096
  3286. */
  3287. {MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xFF, 0x12},
  3288. {MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF},
  3289. };
  3290. static void msm_anlg_cdc_codec_init_cache(struct snd_soc_codec *codec)
  3291. {
  3292. u32 i;
  3293. regcache_cache_only(codec->component.regmap, true);
  3294. /* update cache with POR values */
  3295. for (i = 0; i < ARRAY_SIZE(msm89xx_pmic_cdc_defaults); i++)
  3296. snd_soc_write(codec, msm89xx_pmic_cdc_defaults[i].reg,
  3297. msm89xx_pmic_cdc_defaults[i].def);
  3298. regcache_cache_only(codec->component.regmap, false);
  3299. }
  3300. static void msm_anlg_cdc_codec_init_reg(struct snd_soc_codec *codec)
  3301. {
  3302. u32 i;
  3303. for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_codec_reg_init_val); i++)
  3304. snd_soc_update_bits(codec,
  3305. msm_anlg_cdc_codec_reg_init_val[i].reg,
  3306. msm_anlg_cdc_codec_reg_init_val[i].mask,
  3307. msm_anlg_cdc_codec_reg_init_val[i].val);
  3308. }
  3309. static int msm_anlg_cdc_bringup(struct snd_soc_codec *codec)
  3310. {
  3311. snd_soc_write(codec,
  3312. MSM89XX_PMIC_DIGITAL_SEC_ACCESS,
  3313. 0xA5);
  3314. snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x01);
  3315. snd_soc_write(codec,
  3316. MSM89XX_PMIC_ANALOG_SEC_ACCESS,
  3317. 0xA5);
  3318. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x01);
  3319. snd_soc_write(codec,
  3320. MSM89XX_PMIC_DIGITAL_SEC_ACCESS,
  3321. 0xA5);
  3322. snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00);
  3323. snd_soc_write(codec,
  3324. MSM89XX_PMIC_ANALOG_SEC_ACCESS,
  3325. 0xA5);
  3326. snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00);
  3327. return 0;
  3328. }
  3329. static struct regulator *msm_anlg_cdc_find_regulator(
  3330. const struct sdm660_cdc_priv *sdm660_cdc,
  3331. const char *name)
  3332. {
  3333. int i;
  3334. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3335. if (sdm660_cdc->supplies[i].supply &&
  3336. !strcmp(sdm660_cdc->supplies[i].supply, name))
  3337. return sdm660_cdc->supplies[i].consumer;
  3338. }
  3339. dev_err(sdm660_cdc->dev, "Error: regulator not found:%s\n"
  3340. , name);
  3341. return NULL;
  3342. }
  3343. static void msm_anlg_cdc_update_micbias_regulator(
  3344. const struct sdm660_cdc_priv *sdm660_cdc,
  3345. const char *name,
  3346. struct on_demand_supply *micbias_supply)
  3347. {
  3348. int i;
  3349. struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data;
  3350. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3351. if (sdm660_cdc->supplies[i].supply &&
  3352. !strcmp(sdm660_cdc->supplies[i].supply, name)) {
  3353. micbias_supply->supply =
  3354. sdm660_cdc->supplies[i].consumer;
  3355. micbias_supply->min_uv = pdata->regulator[i].min_uv;
  3356. micbias_supply->max_uv = pdata->regulator[i].max_uv;
  3357. micbias_supply->optimum_ua =
  3358. pdata->regulator[i].optimum_ua;
  3359. return;
  3360. }
  3361. }
  3362. dev_err(sdm660_cdc->dev, "Error: regulator not found:%s\n", name);
  3363. }
  3364. static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec)
  3365. {
  3366. struct msm_asoc_mach_data *pdata = NULL;
  3367. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3368. snd_soc_codec_get_drvdata(codec);
  3369. unsigned int tx_1_en;
  3370. unsigned int tx_2_en;
  3371. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3372. dev_dbg(codec->dev, "%s: device down!\n", __func__);
  3373. tx_1_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_1_EN);
  3374. tx_2_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_2_EN);
  3375. tx_1_en = tx_1_en & 0x7f;
  3376. tx_2_en = tx_2_en & 0x7f;
  3377. snd_soc_write(codec,
  3378. MSM89XX_PMIC_ANALOG_TX_1_EN, tx_1_en);
  3379. snd_soc_write(codec,
  3380. MSM89XX_PMIC_ANALOG_TX_2_EN, tx_2_en);
  3381. if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) {
  3382. if ((snd_soc_read(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL)
  3383. & 0x80) == 0) {
  3384. msm_anlg_cdc_dig_notifier_call(codec,
  3385. DIG_CDC_EVENT_CLK_ON);
  3386. snd_soc_write(codec,
  3387. MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30);
  3388. snd_soc_update_bits(codec,
  3389. MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
  3390. snd_soc_update_bits(codec,
  3391. MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL,
  3392. 0x0C, 0x0C);
  3393. snd_soc_update_bits(codec,
  3394. MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
  3395. 0x84, 0x84);
  3396. snd_soc_update_bits(codec,
  3397. MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL,
  3398. 0x10, 0x10);
  3399. snd_soc_update_bits(codec,
  3400. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL,
  3401. 0x1F, 0x1F);
  3402. snd_soc_update_bits(codec,
  3403. MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
  3404. 0x90, 0x90);
  3405. snd_soc_update_bits(codec,
  3406. MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
  3407. 0xFF, 0xFF);
  3408. /* Wait for 20us for boost settings to take effect */
  3409. usleep_range(20, 21);
  3410. snd_soc_update_bits(codec,
  3411. MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL,
  3412. 0xFF, 0xFF);
  3413. snd_soc_update_bits(codec,
  3414. MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  3415. 0xE9, 0xE9);
  3416. }
  3417. }
  3418. msm_anlg_cdc_boost_off(codec);
  3419. sdm660_cdc_priv->hph_mode = NORMAL_MODE;
  3420. /* 40ms to allow boost to discharge */
  3421. msleep(40);
  3422. /* Disable PA to avoid pop during codec bring up */
  3423. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
  3424. 0x30, 0x00);
  3425. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
  3426. 0x80, 0x00);
  3427. snd_soc_write(codec,
  3428. MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20);
  3429. snd_soc_write(codec,
  3430. MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20);
  3431. snd_soc_write(codec,
  3432. MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12);
  3433. snd_soc_write(codec,
  3434. MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x93);
  3435. msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_DOWN);
  3436. atomic_set(&pdata->int_mclk0_enabled, false);
  3437. set_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask);
  3438. snd_soc_card_change_online_state(codec->component.card, 0);
  3439. return 0;
  3440. }
  3441. static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec)
  3442. {
  3443. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3444. snd_soc_codec_get_drvdata(codec);
  3445. dev_dbg(codec->dev, "%s: device up!\n", __func__);
  3446. msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_UP);
  3447. clear_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask);
  3448. snd_soc_card_change_online_state(codec->component.card, 1);
  3449. /* delay is required to make sure sound card state updated */
  3450. usleep_range(5000, 5100);
  3451. snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_SET,
  3452. MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR);
  3453. snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_CLR,
  3454. MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR);
  3455. msm_anlg_cdc_set_boost_v(codec);
  3456. msm_anlg_cdc_set_micb_v(codec);
  3457. if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER)
  3458. msm_anlg_cdc_boost_on(codec);
  3459. else if (sdm660_cdc_priv->boost_option == BYPASS_ALWAYS)
  3460. msm_anlg_cdc_bypass_on(codec);
  3461. return 0;
  3462. }
  3463. static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb,
  3464. unsigned long opcode, void *ptr)
  3465. {
  3466. struct snd_soc_codec *codec;
  3467. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3468. container_of(nb, struct sdm660_cdc_priv,
  3469. audio_ssr_nb);
  3470. bool adsp_ready = false;
  3471. bool timedout;
  3472. unsigned long timeout;
  3473. static bool initial_boot = true;
  3474. codec = sdm660_cdc_priv->codec;
  3475. dev_dbg(codec->dev, "%s: Service opcode 0x%lx\n", __func__, opcode);
  3476. switch (opcode) {
  3477. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3478. if (initial_boot) {
  3479. initial_boot = false;
  3480. break;
  3481. }
  3482. dev_dbg(codec->dev,
  3483. "ADSP is about to power down. teardown/reset codec\n");
  3484. msm_anlg_cdc_device_down(codec);
  3485. break;
  3486. case AUDIO_NOTIFIER_SERVICE_UP:
  3487. if (initial_boot)
  3488. initial_boot = false;
  3489. dev_dbg(codec->dev,
  3490. "ADSP is about to power up. bring up codec\n");
  3491. if (!q6core_is_adsp_ready()) {
  3492. dev_dbg(codec->dev,
  3493. "ADSP isn't ready\n");
  3494. timeout = jiffies +
  3495. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3496. while (!(timedout = time_after(jiffies, timeout))) {
  3497. if (!q6core_is_adsp_ready()) {
  3498. dev_dbg(codec->dev,
  3499. "ADSP isn't ready\n");
  3500. } else {
  3501. dev_dbg(codec->dev,
  3502. "ADSP is ready\n");
  3503. adsp_ready = true;
  3504. goto powerup;
  3505. }
  3506. }
  3507. } else {
  3508. adsp_ready = true;
  3509. dev_dbg(codec->dev, "%s: DSP is ready\n", __func__);
  3510. }
  3511. powerup:
  3512. if (adsp_ready)
  3513. msm_anlg_cdc_device_up(codec);
  3514. break;
  3515. default:
  3516. break;
  3517. }
  3518. return NOTIFY_OK;
  3519. }
  3520. int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
  3521. struct wcd_mbhc_config *mbhc_cfg)
  3522. {
  3523. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3524. snd_soc_codec_get_drvdata(codec);
  3525. return wcd_mbhc_start(&sdm660_cdc_priv->mbhc, mbhc_cfg);
  3526. }
  3527. EXPORT_SYMBOL(msm_anlg_cdc_hs_detect);
  3528. void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec)
  3529. {
  3530. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3531. snd_soc_codec_get_drvdata(codec);
  3532. wcd_mbhc_stop(&sdm660_cdc_priv->mbhc);
  3533. }
  3534. EXPORT_SYMBOL(msm_anlg_cdc_hs_detect_exit);
  3535. void msm_anlg_cdc_update_int_spk_boost(bool enable)
  3536. {
  3537. pr_debug("%s: enable = %d\n", __func__, enable);
  3538. spkr_boost_en = enable;
  3539. }
  3540. EXPORT_SYMBOL(msm_anlg_cdc_update_int_spk_boost);
  3541. static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec)
  3542. {
  3543. struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  3544. struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data;
  3545. u8 reg_val;
  3546. reg_val = VOLTAGE_CONVERTER(pdata->micbias.cfilt1_mv, MICBIAS_MIN_VAL,
  3547. MICBIAS_STEP_SIZE);
  3548. dev_dbg(codec->dev, "cfilt1_mv %d reg_val %x\n",
  3549. (u32)pdata->micbias.cfilt1_mv, reg_val);
  3550. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_VAL,
  3551. 0xF8, (reg_val << 3));
  3552. }
  3553. static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec)
  3554. {
  3555. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3556. snd_soc_codec_get_drvdata(codec);
  3557. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE,
  3558. 0x1F, sdm660_cdc_priv->boost_voltage);
  3559. }
  3560. static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec,
  3561. bool micbias1, bool micbias2)
  3562. {
  3563. struct msm_asoc_mach_data *pdata = NULL;
  3564. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3565. pr_debug("\n %s: micbias1 %x micbias2 = %d\n", __func__, micbias1,
  3566. micbias2);
  3567. if (micbias1 && micbias2) {
  3568. if ((pdata->micbias1_cap_mode
  3569. == MICBIAS_EXT_BYP_CAP) ||
  3570. (pdata->micbias2_cap_mode
  3571. == MICBIAS_EXT_BYP_CAP))
  3572. snd_soc_update_bits(codec,
  3573. MSM89XX_PMIC_ANALOG_MICB_1_EN,
  3574. 0x40, (MICBIAS_EXT_BYP_CAP << 6));
  3575. else
  3576. snd_soc_update_bits(codec,
  3577. MSM89XX_PMIC_ANALOG_MICB_1_EN,
  3578. 0x40, (MICBIAS_NO_EXT_BYP_CAP << 6));
  3579. } else if (micbias2) {
  3580. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN,
  3581. 0x40, (pdata->micbias2_cap_mode << 6));
  3582. } else if (micbias1) {
  3583. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN,
  3584. 0x40, (pdata->micbias1_cap_mode << 6));
  3585. } else {
  3586. snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN,
  3587. 0x40, 0x00);
  3588. }
  3589. }
  3590. static ssize_t msm_anlg_codec_version_read(struct snd_info_entry *entry,
  3591. void *file_private_data,
  3592. struct file *file,
  3593. char __user *buf, size_t count,
  3594. loff_t pos)
  3595. {
  3596. struct sdm660_cdc_priv *sdm660_cdc_priv;
  3597. char buffer[MSM_ANLG_CDC_VERSION_ENTRY_SIZE];
  3598. int len = 0;
  3599. sdm660_cdc_priv = (struct sdm660_cdc_priv *) entry->private_data;
  3600. if (!sdm660_cdc_priv) {
  3601. pr_err("%s: sdm660_cdc_priv is null\n", __func__);
  3602. return -EINVAL;
  3603. }
  3604. switch (get_codec_version(sdm660_cdc_priv)) {
  3605. case DRAX_CDC:
  3606. len = snprintf(buffer, sizeof(buffer), "DRAX-CDC_1_0\n");
  3607. break;
  3608. default:
  3609. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3610. }
  3611. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3612. }
  3613. static struct snd_info_entry_ops msm_anlg_codec_info_ops = {
  3614. .read = msm_anlg_codec_version_read,
  3615. };
  3616. /*
  3617. * msm_anlg_codec_info_create_codec_entry - creates pmic_analog module
  3618. * @codec_root: The parent directory
  3619. * @codec: Codec instance
  3620. *
  3621. * Creates pmic_analog module and version entry under the given
  3622. * parent directory.
  3623. *
  3624. * Return: 0 on success or negative error code on failure.
  3625. */
  3626. int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  3627. struct snd_soc_codec *codec)
  3628. {
  3629. struct snd_info_entry *version_entry;
  3630. struct sdm660_cdc_priv *sdm660_cdc_priv;
  3631. struct snd_soc_card *card;
  3632. int ret;
  3633. if (!codec_root || !codec)
  3634. return -EINVAL;
  3635. sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec);
  3636. card = codec->component.card;
  3637. sdm660_cdc_priv->entry = snd_info_create_subdir(codec_root->module,
  3638. "spmi0-03",
  3639. codec_root);
  3640. if (!sdm660_cdc_priv->entry) {
  3641. dev_dbg(codec->dev, "%s: failed to create pmic_analog entry\n",
  3642. __func__);
  3643. return -ENOMEM;
  3644. }
  3645. version_entry = snd_info_create_card_entry(card->snd_card,
  3646. "version",
  3647. sdm660_cdc_priv->entry);
  3648. if (!version_entry) {
  3649. dev_dbg(codec->dev, "%s: failed to create pmic_analog version entry\n",
  3650. __func__);
  3651. return -ENOMEM;
  3652. }
  3653. version_entry->private_data = sdm660_cdc_priv;
  3654. version_entry->size = MSM_ANLG_CDC_VERSION_ENTRY_SIZE;
  3655. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3656. version_entry->c.ops = &msm_anlg_codec_info_ops;
  3657. if (snd_info_register(version_entry) < 0) {
  3658. snd_info_free_entry(version_entry);
  3659. return -ENOMEM;
  3660. }
  3661. sdm660_cdc_priv->version_entry = version_entry;
  3662. sdm660_cdc_priv->audio_ssr_nb.notifier_call =
  3663. sdm660_cdc_notifier_service_cb;
  3664. ret = audio_notifier_register("pmic_analog_cdc",
  3665. AUDIO_NOTIFIER_ADSP_DOMAIN,
  3666. &sdm660_cdc_priv->audio_ssr_nb);
  3667. if (ret < 0) {
  3668. pr_err("%s: Audio notifier register failed ret = %d\n",
  3669. __func__, ret);
  3670. return ret;
  3671. }
  3672. return 0;
  3673. }
  3674. EXPORT_SYMBOL(msm_anlg_codec_info_create_codec_entry);
  3675. static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec)
  3676. {
  3677. struct sdm660_cdc_priv *sdm660_cdc;
  3678. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3679. int ret;
  3680. sdm660_cdc = dev_get_drvdata(codec->dev);
  3681. sdm660_cdc->codec = codec;
  3682. /* codec resmgr module init */
  3683. sdm660_cdc->spkdrv_reg =
  3684. msm_anlg_cdc_find_regulator(sdm660_cdc,
  3685. MSM89XX_VDD_SPKDRV_NAME);
  3686. sdm660_cdc->pmic_rev =
  3687. snd_soc_read(codec,
  3688. MSM89XX_PMIC_DIGITAL_REVISION1);
  3689. sdm660_cdc->codec_version =
  3690. snd_soc_read(codec,
  3691. MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE);
  3692. sdm660_cdc->analog_major_rev =
  3693. snd_soc_read(codec,
  3694. MSM89XX_PMIC_ANALOG_REVISION4);
  3695. if (sdm660_cdc->codec_version == CONGA) {
  3696. dev_dbg(codec->dev, "%s :Conga REV: %d\n", __func__,
  3697. sdm660_cdc->codec_version);
  3698. sdm660_cdc->ext_spk_boost_set = true;
  3699. } else {
  3700. dev_dbg(codec->dev, "%s :PMIC REV: %d\n", __func__,
  3701. sdm660_cdc->pmic_rev);
  3702. if (sdm660_cdc->pmic_rev == TOMBAK_1_0 &&
  3703. sdm660_cdc->codec_version == CAJON_2_0) {
  3704. if (sdm660_cdc->analog_major_rev == 0x02) {
  3705. sdm660_cdc->codec_version = DRAX_CDC;
  3706. dev_dbg(codec->dev,
  3707. "%s : Drax codec detected\n", __func__);
  3708. } else {
  3709. sdm660_cdc->codec_version = DIANGU;
  3710. dev_dbg(codec->dev, "%s : Diangu detected\n",
  3711. __func__);
  3712. }
  3713. } else if (sdm660_cdc->pmic_rev == TOMBAK_1_0 &&
  3714. (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL)
  3715. & 0x80)) {
  3716. sdm660_cdc->codec_version = CAJON;
  3717. dev_dbg(codec->dev, "%s : Cajon detected\n", __func__);
  3718. } else if (sdm660_cdc->pmic_rev == TOMBAK_2_0 &&
  3719. (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL)
  3720. & 0x80)) {
  3721. sdm660_cdc->codec_version = CAJON_2_0;
  3722. dev_dbg(codec->dev, "%s : Cajon 2.0 detected\n",
  3723. __func__);
  3724. }
  3725. }
  3726. /*
  3727. * set to default boost option BOOST_SWITCH, user mixer path can change
  3728. * it to BOOST_ALWAYS or BOOST_BYPASS based on solution chosen.
  3729. */
  3730. sdm660_cdc->boost_option = BOOST_SWITCH;
  3731. sdm660_cdc->hph_mode = NORMAL_MODE;
  3732. msm_anlg_cdc_dt_parse_boost_info(codec);
  3733. msm_anlg_cdc_set_boost_v(codec);
  3734. snd_soc_add_codec_controls(codec, impedance_detect_controls,
  3735. ARRAY_SIZE(impedance_detect_controls));
  3736. snd_soc_add_codec_controls(codec, hph_type_detect_controls,
  3737. ARRAY_SIZE(hph_type_detect_controls));
  3738. msm_anlg_cdc_bringup(codec);
  3739. msm_anlg_cdc_codec_init_cache(codec);
  3740. msm_anlg_cdc_codec_init_reg(codec);
  3741. msm_anlg_cdc_update_reg_defaults(codec);
  3742. wcd9xxx_spmi_set_codec(codec);
  3743. msm_anlg_cdc_update_micbias_regulator(
  3744. sdm660_cdc,
  3745. on_demand_supply_name[ON_DEMAND_MICBIAS],
  3746. &sdm660_cdc->on_demand_list[ON_DEMAND_MICBIAS]);
  3747. atomic_set(&sdm660_cdc->on_demand_list[ON_DEMAND_MICBIAS].ref,
  3748. 0);
  3749. sdm660_cdc->fw_data = devm_kzalloc(codec->dev,
  3750. sizeof(*(sdm660_cdc->fw_data)),
  3751. GFP_KERNEL);
  3752. if (!sdm660_cdc->fw_data)
  3753. return -ENOMEM;
  3754. set_bit(WCD9XXX_MBHC_CAL, sdm660_cdc->fw_data->cal_bit);
  3755. ret = wcd_cal_create_hwdep(sdm660_cdc->fw_data,
  3756. WCD9XXX_CODEC_HWDEP_NODE, codec);
  3757. if (ret < 0) {
  3758. dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret);
  3759. return ret;
  3760. }
  3761. wcd_mbhc_init(&sdm660_cdc->mbhc, codec, &mbhc_cb, &intr_ids,
  3762. wcd_mbhc_registers, true);
  3763. sdm660_cdc->int_mclk0_enabled = false;
  3764. /*Update speaker boost configuration*/
  3765. sdm660_cdc->spk_boost_set = spkr_boost_en;
  3766. pr_debug("%s: speaker boost configured = %d\n",
  3767. __func__, sdm660_cdc->spk_boost_set);
  3768. /* Set initial MICBIAS voltage level */
  3769. msm_anlg_cdc_set_micb_v(codec);
  3770. /* Set initial cap mode */
  3771. msm_anlg_cdc_configure_cap(codec, false, false);
  3772. snd_soc_dapm_ignore_suspend(dapm, "PDM Playback");
  3773. snd_soc_dapm_ignore_suspend(dapm, "PDM Capture");
  3774. snd_soc_dapm_sync(dapm);
  3775. return 0;
  3776. }
  3777. static int msm_anlg_cdc_soc_remove(struct snd_soc_codec *codec)
  3778. {
  3779. struct sdm660_cdc_priv *sdm660_cdc_priv =
  3780. dev_get_drvdata(codec->dev);
  3781. sdm660_cdc_priv->spkdrv_reg = NULL;
  3782. sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL;
  3783. atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref,
  3784. 0);
  3785. wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc);
  3786. return 0;
  3787. }
  3788. static int msm_anlg_cdc_enable_static_supplies_to_optimum(
  3789. struct sdm660_cdc_priv *sdm660_cdc,
  3790. struct sdm660_cdc_pdata *pdata)
  3791. {
  3792. int i;
  3793. int ret = 0;
  3794. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3795. if (pdata->regulator[i].ondemand)
  3796. continue;
  3797. if (regulator_count_voltages(
  3798. sdm660_cdc->supplies[i].consumer) <= 0)
  3799. continue;
  3800. ret = regulator_set_voltage(
  3801. sdm660_cdc->supplies[i].consumer,
  3802. pdata->regulator[i].min_uv,
  3803. pdata->regulator[i].max_uv);
  3804. if (ret) {
  3805. dev_err(sdm660_cdc->dev,
  3806. "Setting volt failed for regulator %s err %d\n",
  3807. sdm660_cdc->supplies[i].supply, ret);
  3808. }
  3809. ret = regulator_set_load(sdm660_cdc->supplies[i].consumer,
  3810. pdata->regulator[i].optimum_ua);
  3811. dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n",
  3812. sdm660_cdc->supplies[i].supply);
  3813. }
  3814. return ret;
  3815. }
  3816. static int msm_anlg_cdc_disable_static_supplies_to_optimum(
  3817. struct sdm660_cdc_priv *sdm660_cdc,
  3818. struct sdm660_cdc_pdata *pdata)
  3819. {
  3820. int i;
  3821. int ret = 0;
  3822. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3823. if (pdata->regulator[i].ondemand)
  3824. continue;
  3825. if (regulator_count_voltages(
  3826. sdm660_cdc->supplies[i].consumer) <= 0)
  3827. continue;
  3828. regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0,
  3829. pdata->regulator[i].max_uv);
  3830. regulator_set_load(sdm660_cdc->supplies[i].consumer, 0);
  3831. dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n",
  3832. sdm660_cdc->supplies[i].supply);
  3833. }
  3834. return ret;
  3835. }
  3836. static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec)
  3837. {
  3838. struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  3839. struct sdm660_cdc_pdata *sdm660_cdc_pdata =
  3840. sdm660_cdc->dev->platform_data;
  3841. msm_anlg_cdc_disable_static_supplies_to_optimum(sdm660_cdc,
  3842. sdm660_cdc_pdata);
  3843. return 0;
  3844. }
  3845. static int msm_anlg_cdc_resume(struct snd_soc_codec *codec)
  3846. {
  3847. struct msm_asoc_mach_data *pdata = NULL;
  3848. struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec);
  3849. struct sdm660_cdc_pdata *sdm660_cdc_pdata =
  3850. sdm660_cdc->dev->platform_data;
  3851. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3852. msm_anlg_cdc_enable_static_supplies_to_optimum(sdm660_cdc,
  3853. sdm660_cdc_pdata);
  3854. return 0;
  3855. }
  3856. static struct regmap *msm_anlg_get_regmap(struct device *dev)
  3857. {
  3858. return dev_get_regmap(dev->parent, NULL);
  3859. }
  3860. static struct snd_soc_codec_driver soc_codec_dev_sdm660_cdc = {
  3861. .probe = msm_anlg_cdc_soc_probe,
  3862. .remove = msm_anlg_cdc_soc_remove,
  3863. .suspend = msm_anlg_cdc_suspend,
  3864. .resume = msm_anlg_cdc_resume,
  3865. .reg_word_size = 1,
  3866. .get_regmap = msm_anlg_get_regmap,
  3867. .component_driver = {
  3868. .controls = msm_anlg_cdc_snd_controls,
  3869. .num_controls = ARRAY_SIZE(msm_anlg_cdc_snd_controls),
  3870. .dapm_widgets = msm_anlg_cdc_dapm_widgets,
  3871. .num_dapm_widgets = ARRAY_SIZE(msm_anlg_cdc_dapm_widgets),
  3872. .dapm_routes = audio_map,
  3873. .num_dapm_routes = ARRAY_SIZE(audio_map),
  3874. },
  3875. };
  3876. static int msm_anlg_cdc_init_supplies(struct sdm660_cdc_priv *sdm660_cdc,
  3877. struct sdm660_cdc_pdata *pdata)
  3878. {
  3879. int ret;
  3880. int i;
  3881. sdm660_cdc->supplies = devm_kzalloc(sdm660_cdc->dev,
  3882. sizeof(struct regulator_bulk_data) *
  3883. ARRAY_SIZE(pdata->regulator),
  3884. GFP_KERNEL);
  3885. if (!sdm660_cdc->supplies) {
  3886. ret = -ENOMEM;
  3887. goto err;
  3888. }
  3889. sdm660_cdc->num_of_supplies = 0;
  3890. if (ARRAY_SIZE(pdata->regulator) > MAX_REGULATOR) {
  3891. dev_err(sdm660_cdc->dev, "%s: Array Size out of bound\n",
  3892. __func__);
  3893. ret = -EINVAL;
  3894. goto err;
  3895. }
  3896. for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) {
  3897. if (pdata->regulator[i].name) {
  3898. sdm660_cdc->supplies[i].supply =
  3899. pdata->regulator[i].name;
  3900. sdm660_cdc->num_of_supplies++;
  3901. }
  3902. }
  3903. ret = devm_regulator_bulk_get(sdm660_cdc->dev,
  3904. sdm660_cdc->num_of_supplies,
  3905. sdm660_cdc->supplies);
  3906. if (ret != 0) {
  3907. dev_err(sdm660_cdc->dev,
  3908. "Failed to get supplies: err = %d\n",
  3909. ret);
  3910. goto err_supplies;
  3911. }
  3912. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3913. if (regulator_count_voltages(
  3914. sdm660_cdc->supplies[i].consumer) <= 0)
  3915. continue;
  3916. if (pdata->regulator[i].ondemand) {
  3917. ret = regulator_set_voltage(
  3918. sdm660_cdc->supplies[i].consumer,
  3919. 0, pdata->regulator[i].max_uv);
  3920. if (ret) {
  3921. dev_err(sdm660_cdc->dev,
  3922. "Setting regulator voltage failed for regulator %s err = %d\n",
  3923. sdm660_cdc->supplies[i].supply, ret);
  3924. goto err_supplies;
  3925. }
  3926. ret = regulator_set_load(
  3927. sdm660_cdc->supplies[i].consumer, 0);
  3928. if (ret < 0) {
  3929. dev_err(sdm660_cdc->dev,
  3930. "Setting regulator optimum mode failed for regulator %s err = %d\n",
  3931. sdm660_cdc->supplies[i].supply, ret);
  3932. goto err_supplies;
  3933. } else {
  3934. ret = 0;
  3935. continue;
  3936. }
  3937. }
  3938. ret = regulator_set_voltage(sdm660_cdc->supplies[i].consumer,
  3939. pdata->regulator[i].min_uv,
  3940. pdata->regulator[i].max_uv);
  3941. if (ret) {
  3942. dev_err(sdm660_cdc->dev,
  3943. "Setting regulator voltage failed for regulator %s err = %d\n",
  3944. sdm660_cdc->supplies[i].supply, ret);
  3945. goto err_supplies;
  3946. }
  3947. ret = regulator_set_load(sdm660_cdc->supplies[i].consumer,
  3948. pdata->regulator[i].optimum_ua);
  3949. if (ret < 0) {
  3950. dev_err(sdm660_cdc->dev,
  3951. "Setting regulator optimum mode failed for regulator %s err = %d\n",
  3952. sdm660_cdc->supplies[i].supply, ret);
  3953. goto err_supplies;
  3954. } else {
  3955. ret = 0;
  3956. }
  3957. }
  3958. return ret;
  3959. err_supplies:
  3960. kfree(sdm660_cdc->supplies);
  3961. err:
  3962. return ret;
  3963. }
  3964. static int msm_anlg_cdc_enable_static_supplies(
  3965. struct sdm660_cdc_priv *sdm660_cdc,
  3966. struct sdm660_cdc_pdata *pdata)
  3967. {
  3968. int i;
  3969. int ret = 0;
  3970. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3971. if (pdata->regulator[i].ondemand)
  3972. continue;
  3973. ret = regulator_enable(sdm660_cdc->supplies[i].consumer);
  3974. if (ret) {
  3975. dev_err(sdm660_cdc->dev, "Failed to enable %s\n",
  3976. sdm660_cdc->supplies[i].supply);
  3977. break;
  3978. }
  3979. dev_dbg(sdm660_cdc->dev, "Enabled regulator %s\n",
  3980. sdm660_cdc->supplies[i].supply);
  3981. }
  3982. while (ret && --i)
  3983. if (!pdata->regulator[i].ondemand)
  3984. regulator_disable(sdm660_cdc->supplies[i].consumer);
  3985. return ret;
  3986. }
  3987. static void msm_anlg_cdc_disable_supplies(struct sdm660_cdc_priv *sdm660_cdc,
  3988. struct sdm660_cdc_pdata *pdata)
  3989. {
  3990. int i;
  3991. regulator_bulk_disable(sdm660_cdc->num_of_supplies,
  3992. sdm660_cdc->supplies);
  3993. for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
  3994. if (regulator_count_voltages(
  3995. sdm660_cdc->supplies[i].consumer) <= 0)
  3996. continue;
  3997. regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0,
  3998. pdata->regulator[i].max_uv);
  3999. regulator_set_load(sdm660_cdc->supplies[i].consumer, 0);
  4000. }
  4001. regulator_bulk_free(sdm660_cdc->num_of_supplies,
  4002. sdm660_cdc->supplies);
  4003. kfree(sdm660_cdc->supplies);
  4004. }
  4005. static const struct of_device_id sdm660_codec_of_match[] = {
  4006. { .compatible = "qcom,pmic-analog-codec", },
  4007. {},
  4008. };
  4009. static void msm_anlg_add_child_devices(struct work_struct *work)
  4010. {
  4011. struct sdm660_cdc_priv *pdata;
  4012. struct platform_device *pdev;
  4013. struct device_node *node;
  4014. struct msm_dig_ctrl_data *dig_ctrl_data = NULL, *temp;
  4015. int ret, ctrl_num = 0;
  4016. struct msm_dig_ctrl_platform_data *platdata;
  4017. char plat_dev_name[MSM_DIG_CDC_STRING_LEN];
  4018. pdata = container_of(work, struct sdm660_cdc_priv,
  4019. msm_anlg_add_child_devices_work);
  4020. if (!pdata) {
  4021. pr_err("%s: Memory for pdata does not exist\n",
  4022. __func__);
  4023. return;
  4024. }
  4025. if (!pdata->dev->of_node) {
  4026. dev_err(pdata->dev,
  4027. "%s: DT node for pdata does not exist\n", __func__);
  4028. return;
  4029. }
  4030. platdata = &pdata->dig_plat_data;
  4031. for_each_child_of_node(pdata->dev->of_node, node) {
  4032. if (!strcmp(node->name, "msm-dig-codec"))
  4033. strlcpy(plat_dev_name, "msm_digital_codec",
  4034. (MSM_DIG_CDC_STRING_LEN - 1));
  4035. else
  4036. continue;
  4037. pdev = platform_device_alloc(plat_dev_name, -1);
  4038. if (!pdev) {
  4039. dev_err(pdata->dev, "%s: pdev memory alloc failed\n",
  4040. __func__);
  4041. ret = -ENOMEM;
  4042. goto err;
  4043. }
  4044. pdev->dev.parent = pdata->dev;
  4045. pdev->dev.of_node = node;
  4046. if (!strcmp(node->name, "msm-dig-codec")) {
  4047. ret = platform_device_add_data(pdev, platdata,
  4048. sizeof(*platdata));
  4049. if (ret) {
  4050. dev_err(&pdev->dev,
  4051. "%s: cannot add plat data ctrl:%d\n",
  4052. __func__, ctrl_num);
  4053. goto fail_pdev_add;
  4054. }
  4055. }
  4056. ret = platform_device_add(pdev);
  4057. if (ret) {
  4058. dev_err(&pdev->dev,
  4059. "%s: Cannot add platform device\n",
  4060. __func__);
  4061. goto fail_pdev_add;
  4062. }
  4063. if (!strcmp(node->name, "msm-dig-codec")) {
  4064. temp = krealloc(dig_ctrl_data,
  4065. (ctrl_num + 1) * sizeof(
  4066. struct msm_dig_ctrl_data),
  4067. GFP_KERNEL);
  4068. if (!temp) {
  4069. dev_err(&pdev->dev, "out of memory\n");
  4070. ret = -ENOMEM;
  4071. goto err;
  4072. }
  4073. dig_ctrl_data = temp;
  4074. dig_ctrl_data[ctrl_num].dig_pdev = pdev;
  4075. ctrl_num++;
  4076. dev_dbg(&pdev->dev,
  4077. "%s: Added digital codec device(s)\n",
  4078. __func__);
  4079. pdata->dig_ctrl_data = dig_ctrl_data;
  4080. }
  4081. }
  4082. return;
  4083. fail_pdev_add:
  4084. platform_device_put(pdev);
  4085. err:
  4086. return;
  4087. }
  4088. static int msm_anlg_cdc_probe(struct platform_device *pdev)
  4089. {
  4090. int ret = 0;
  4091. struct sdm660_cdc_priv *sdm660_cdc = NULL;
  4092. struct sdm660_cdc_pdata *pdata;
  4093. int adsp_state;
  4094. adsp_state = apr_get_subsys_state();
  4095. if (adsp_state != APR_SUBSYS_LOADED) {
  4096. dev_err(&pdev->dev, "Adsp is not loaded yet %d\n",
  4097. adsp_state);
  4098. return -EPROBE_DEFER;
  4099. }
  4100. device_init_wakeup(&pdev->dev, true);
  4101. if (pdev->dev.of_node) {
  4102. dev_dbg(&pdev->dev, "%s:Platform data from device tree\n",
  4103. __func__);
  4104. pdata = msm_anlg_cdc_populate_dt_pdata(&pdev->dev);
  4105. pdev->dev.platform_data = pdata;
  4106. } else {
  4107. dev_dbg(&pdev->dev, "%s:Platform data from board file\n",
  4108. __func__);
  4109. pdata = pdev->dev.platform_data;
  4110. }
  4111. if (pdata == NULL) {
  4112. dev_err(&pdev->dev, "%s:Platform data failed to populate\n",
  4113. __func__);
  4114. goto rtn;
  4115. }
  4116. sdm660_cdc = devm_kzalloc(&pdev->dev, sizeof(struct sdm660_cdc_priv),
  4117. GFP_KERNEL);
  4118. if (sdm660_cdc == NULL) {
  4119. ret = -ENOMEM;
  4120. goto rtn;
  4121. }
  4122. sdm660_cdc->dev = &pdev->dev;
  4123. ret = msm_anlg_cdc_init_supplies(sdm660_cdc, pdata);
  4124. if (ret) {
  4125. dev_err(&pdev->dev, "%s: Fail to enable Codec supplies\n",
  4126. __func__);
  4127. goto rtn;
  4128. }
  4129. ret = msm_anlg_cdc_enable_static_supplies(sdm660_cdc, pdata);
  4130. if (ret) {
  4131. dev_err(&pdev->dev,
  4132. "%s: Fail to enable Codec pre-reset supplies\n",
  4133. __func__);
  4134. goto rtn;
  4135. }
  4136. /* Allow supplies to be ready */
  4137. usleep_range(5, 6);
  4138. wcd9xxx_spmi_set_dev(pdev, 0);
  4139. wcd9xxx_spmi_set_dev(pdev, 1);
  4140. if (wcd9xxx_spmi_irq_init()) {
  4141. dev_err(&pdev->dev,
  4142. "%s: irq initialization failed\n", __func__);
  4143. } else {
  4144. dev_dbg(&pdev->dev,
  4145. "%s: irq initialization passed\n", __func__);
  4146. }
  4147. dev_set_drvdata(&pdev->dev, sdm660_cdc);
  4148. ret = snd_soc_register_codec(&pdev->dev,
  4149. &soc_codec_dev_sdm660_cdc,
  4150. msm_anlg_cdc_i2s_dai,
  4151. ARRAY_SIZE(msm_anlg_cdc_i2s_dai));
  4152. if (ret) {
  4153. dev_err(&pdev->dev,
  4154. "%s:snd_soc_register_codec failed with error %d\n",
  4155. __func__, ret);
  4156. goto err_supplies;
  4157. }
  4158. BLOCKING_INIT_NOTIFIER_HEAD(&sdm660_cdc->notifier);
  4159. BLOCKING_INIT_NOTIFIER_HEAD(&sdm660_cdc->notifier_mbhc);
  4160. sdm660_cdc->dig_plat_data.handle = (void *) sdm660_cdc;
  4161. sdm660_cdc->dig_plat_data.set_compander_mode = set_compander_mode;
  4162. sdm660_cdc->dig_plat_data.update_clkdiv = update_clkdiv;
  4163. sdm660_cdc->dig_plat_data.get_cdc_version = get_cdc_version;
  4164. sdm660_cdc->dig_plat_data.register_notifier =
  4165. msm_anlg_cdc_dig_register_notifier;
  4166. INIT_WORK(&sdm660_cdc->msm_anlg_add_child_devices_work,
  4167. msm_anlg_add_child_devices);
  4168. schedule_work(&sdm660_cdc->msm_anlg_add_child_devices_work);
  4169. return ret;
  4170. err_supplies:
  4171. msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata);
  4172. rtn:
  4173. return ret;
  4174. }
  4175. static int msm_anlg_cdc_remove(struct platform_device *pdev)
  4176. {
  4177. struct sdm660_cdc_priv *sdm660_cdc = dev_get_drvdata(&pdev->dev);
  4178. struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data;
  4179. snd_soc_unregister_codec(&pdev->dev);
  4180. msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata);
  4181. return 0;
  4182. }
  4183. static struct platform_driver msm_anlg_codec_driver = {
  4184. .driver = {
  4185. .owner = THIS_MODULE,
  4186. .name = DRV_NAME,
  4187. .of_match_table = of_match_ptr(sdm660_codec_of_match)
  4188. },
  4189. .probe = msm_anlg_cdc_probe,
  4190. .remove = msm_anlg_cdc_remove,
  4191. };
  4192. module_platform_driver(msm_anlg_codec_driver);
  4193. MODULE_DESCRIPTION("MSM Audio Analog codec driver");
  4194. MODULE_LICENSE("GPL v2");