f49df07dae
Add support to clear/reset the consumed HW descriptors to zero. Change-Id: Idccb120afa448c4f958a3177f27cab9b1197ac3e CRs-Fixed: 2978850
285 rader
8.8 KiB
C
285 rader
8.8 KiB
C
/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "cdp_txrx_cmn_struct.h"
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#include "dp_types.h"
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#include "dp_tx.h"
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#include "dp_li_tx.h"
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#include "dp_tx_desc.h"
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#include <dp_internal.h>
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#include <dp_htt.h>
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#include <hal_li_api.h>
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#include <hal_li_tx.h>
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/*mapping between hal encrypt type and cdp_sec_type*/
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#define MAX_CDP_SEC_TYPE 12
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uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
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HAL_TX_ENCRYPT_TYPE_WEP_128,
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HAL_TX_ENCRYPT_TYPE_WEP_104,
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HAL_TX_ENCRYPT_TYPE_WEP_40,
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HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
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HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
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HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
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HAL_TX_ENCRYPT_TYPE_WAPI,
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HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
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HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
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HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
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HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
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void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
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void *tx_comp_hal_desc,
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struct dp_tx_desc_s **r_tx_desc)
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{
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uint8_t pool_id;
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uint32_t tx_desc_id;
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tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
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pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
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DP_TX_DESC_ID_POOL_OS;
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/* Find Tx descriptor */
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*r_tx_desc = dp_tx_desc_find(soc, pool_id,
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(tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
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DP_TX_DESC_ID_PAGE_OS,
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(tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
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DP_TX_DESC_ID_OFFSET_OS);
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/* Pool id is not matching. Error */
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if ((*r_tx_desc)->pool_id != pool_id) {
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dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
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pool_id, (*r_tx_desc)->pool_id);
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qdf_assert_always(0);
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}
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}
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#ifdef QCA_OL_TX_MULTIQ_SUPPORT
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/*
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* dp_tx_get_rbm_id()- Get the RBM ID for data transmission completion.
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* @dp_soc - DP soc structure pointer
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* @ring_id - Transmit Queue/ring_id to be used when XPS is enabled
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*
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* Return - HAL ring handle
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*/
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
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HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
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}
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#else
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return (ring_id + soc->wbm_sw0_bm_id);
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}
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#endif
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#if defined(CLEAR_SW2TCL_CONSUMED_DESC)
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/**
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* dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
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*
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* @soc: DP soc handle
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* @hal_ring_hdl: Source ring pointer
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*
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* Return: void
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*/
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static inline
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void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
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hal_ring_handle_t hal_ring_hdl)
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{
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void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
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while (desc) {
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hal_tx_desc_clear(desc);
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desc = hal_srng_src_get_next_consumed(soc->hal_soc,
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hal_ring_hdl);
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}
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}
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#else
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static inline
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void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
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hal_ring_handle_t hal_ring_hdl)
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{
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}
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#endif /* CLEAR_SW2TCL_CONSUMED_DESC */
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QDF_STATUS
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dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
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struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
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struct cdp_tx_exception_metadata *tx_exc_metadata,
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struct dp_tx_msdu_info_s *msdu_info)
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{
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void *hal_tx_desc;
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uint32_t *hal_tx_desc_cached;
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int coalesce = 0;
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struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
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uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
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uint8_t tid = msdu_info->tid;
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/*
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* Setting it initialization statically here to avoid
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* a memset call jump with qdf_mem_set call
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*/
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uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
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enum cdp_sec_type sec_type = ((tx_exc_metadata &&
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tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
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tx_exc_metadata->sec_type : vdev->sec_type);
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/* Return Buffer Manager ID */
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uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
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hal_ring_handle_t hal_ring_hdl = NULL;
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QDF_STATUS status = QDF_STATUS_E_RESOURCES;
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if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
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dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
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return QDF_STATUS_E_RESOURCES;
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}
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hal_tx_desc_cached = (void *)cached_desc;
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hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
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tx_desc->dma_addr, bm_id, tx_desc->id,
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(tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
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hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
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vdev->lmac_id);
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hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
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vdev->search_type);
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hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
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vdev->bss_ast_idx);
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hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
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vdev->dscp_tid_map_id);
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hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
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sec_type_map[sec_type]);
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hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
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(vdev->bss_ast_hash & 0xF));
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hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
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hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
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hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
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hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
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hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
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vdev->hal_desc_addr_search_flags);
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if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
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hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
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/* verify checksum offload configuration*/
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if (vdev->csum_enabled &&
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((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
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QDF_NBUF_TX_CKSUM_TCP_UDP) ||
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qdf_nbuf_is_tso(tx_desc->nbuf))) {
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hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
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hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
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}
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if (tid != HTT_TX_EXT_TID_INVALID)
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hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
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if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
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hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
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if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
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qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
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tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
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dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
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tx_desc->length,
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(tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
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(uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
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tx_desc->id);
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hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
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if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
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QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
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"%s %d : HAL RING Access Failed -- %pK",
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__func__, __LINE__, hal_ring_hdl);
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DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
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DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
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return status;
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}
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dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
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/* Sync cached descriptor with HW */
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hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
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if (qdf_unlikely(!hal_tx_desc)) {
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dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
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DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
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DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
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goto ring_access_fail;
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}
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tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
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dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
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hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
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coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
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DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
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dp_tx_update_stats(soc, tx_desc->nbuf);
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status = QDF_STATUS_SUCCESS;
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dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
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hal_ring_hdl, soc);
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ring_access_fail:
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dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
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return status;
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}
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QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
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uint16_t num_elem,
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uint8_t pool_id)
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{
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uint32_t id, count, page_id, offset, pool_id_32;
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struct dp_tx_desc_s *tx_desc;
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struct dp_tx_desc_pool_s *tx_desc_pool;
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uint16_t num_desc_per_page;
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tx_desc_pool = &soc->tx_desc[pool_id];
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tx_desc = tx_desc_pool->freelist;
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count = 0;
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pool_id_32 = (uint32_t)pool_id;
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num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
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while (tx_desc) {
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page_id = count / num_desc_per_page;
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offset = count % num_desc_per_page;
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id = ((pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
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(page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
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tx_desc->id = id;
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tx_desc->pool_id = pool_id;
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tx_desc = tx_desc->next;
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count++;
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}
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return QDF_STATUS_SUCCESS;
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}
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void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
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struct dp_tx_desc_pool_s *tx_desc_pool,
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uint8_t pool_id)
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{
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}
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