ubwcp_main.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/dma-buf.h>
  8. #include <linux/slab.h>
  9. #include <linux/cdev.h>
  10. #include <linux/hashtable.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/types.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/of.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/genalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/numa.h>
  21. #include <linux/memory_hotplug.h>
  22. #include <asm/page.h>
  23. #include <linux/delay.h>
  24. #include <linux/ubwcp_dma_heap.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/clk.h>
  27. #include <linux/iommu.h>
  28. #include <linux/set_memory.h>
  29. #include <linux/range.h>
  30. MODULE_IMPORT_NS(DMA_BUF);
  31. #include "include/kernel/ubwcp.h"
  32. #include "ubwcp_hw.h"
  33. #include "include/uapi/ubwcp_ioctl.h"
  34. #define CREATE_TRACE_POINTS
  35. #include "ubwcp_trace.h"
  36. #define UBWCP_NUM_DEVICES 1
  37. #define UBWCP_DEVICE_NAME "ubwcp"
  38. #define UBWCP_BUFFER_DESC_OFFSET 64
  39. #define UBWCP_BUFFER_DESC_COUNT 256
  40. #define CACHE_ADDR(x) ((x) >> 6)
  41. #define PAGE_ADDR(x) ((x) >> 12)
  42. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  43. #define DBG_BUF_ATTR(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  44. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  45. } while (0)
  46. #define DBG(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  47. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  48. } while (0)
  49. #define ERR(fmt, args...) pr_err("ubwcp: %d: %s(): ~~~ERROR~~~: " fmt "\n", __LINE__, __func__, ##args)
  50. #define ERR_RATE_LIMIT(fmt, args...) pr_err_ratelimited("ubwcp: %s(): ~~~ERROR~~~: " fmt "\n",\
  51. __func__, ##args)
  52. #define FENTRY() DBG("")
  53. #define META_DATA_PITCH_ALIGN 64
  54. #define META_DATA_HEIGHT_ALIGN 16
  55. #define META_DATA_SIZE_ALIGN 4096
  56. #define PIXEL_DATA_SIZE_ALIGN 4096
  57. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  58. /* Max values for attributes */
  59. #define MAX_ATTR_WIDTH (10*1024)
  60. #define MAX_ATTR_HEIGHT (10*1024)
  61. #define MAX_ATTR_STRIDE (64*1024)
  62. #define MAX_ATTR_PLANAR_PAD 4096
  63. #define MAX_ATTR_SCANLN_HT_DELTA (32*1024)
  64. enum ula_remove_mem_status {
  65. ULA_REMOVE_MEM_SUCCESS = 0,
  66. ULA_REMOVE_MEM_ABORTED = 1
  67. };
  68. struct ubwcp_desc {
  69. int idx;
  70. void *ptr;
  71. };
  72. struct tile_dimension {
  73. u16 width;
  74. u16 height;
  75. };
  76. struct ubwcp_plane_info {
  77. u16 pixel_bytes;
  78. u16 per_pixel;
  79. struct tile_dimension tilesize_p; /* pixels */
  80. struct tile_dimension macrotilesize_p; /* pixels */
  81. };
  82. struct ubwcp_image_format_info {
  83. u16 planes;
  84. struct ubwcp_plane_info p_info[2];
  85. };
  86. enum ubwcp_std_image_format {
  87. RGBA = 0,
  88. NV12 = 1,
  89. NV124R = 2,
  90. P010 = 3,
  91. TP10 = 4,
  92. P016 = 5,
  93. INFO_FORMAT_LIST_SIZE,
  94. STD_IMAGE_FORMAT_INVALID = 0xFF
  95. };
  96. enum ubwcp_state {
  97. UBWCP_STATE_READY = 0,
  98. UBWCP_STATE_INVALID = -1,
  99. UBWCP_STATE_FAULT = -2,
  100. };
  101. struct ubwcp_driver {
  102. /* cdev related */
  103. dev_t devt;
  104. struct class *dev_class; //sysfs dev class
  105. struct device *dev_sys; //sysfs dev
  106. struct cdev cdev; //char dev
  107. /* debugfs */
  108. struct dentry *debugfs_root;
  109. bool read_err_irq_en;
  110. bool write_err_irq_en;
  111. bool decode_err_irq_en;
  112. bool encode_err_irq_en;
  113. /* ubwcp devices */
  114. struct device *dev; //ubwcp device
  115. struct device *dev_desc_cb; //smmu dev for descriptors
  116. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  117. void __iomem *base; //ubwcp base address
  118. struct regulator *vdd;
  119. struct clk **clocks;
  120. int num_clocks;
  121. /* interrupts */
  122. int irq_range_ck_rd;
  123. int irq_range_ck_wr;
  124. int irq_encode;
  125. int irq_decode;
  126. /* ula address pool */
  127. u64 ula_pool_base;
  128. u64 ula_pool_size;
  129. struct gen_pool *ula_pool;
  130. configure_mmap mmap_config_fptr;
  131. /* HW version */
  132. u32 hw_ver_major;
  133. u32 hw_ver_minor;
  134. /* keep track of all potential buffers.
  135. * hash table index'ed using dma_buf ptr.
  136. * 2**13 = 8192 hash values
  137. */
  138. DECLARE_HASHTABLE(buf_table, 13);
  139. /* buffer descriptor */
  140. void *buffer_desc_base; /* CPU address */
  141. dma_addr_t buffer_desc_dma_handle; /* dma address */
  142. size_t buffer_desc_size;
  143. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  144. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  145. /* driver state */
  146. enum ubwcp_state state;
  147. atomic_t num_non_lin_buffers;
  148. bool mem_online;
  149. struct mutex desc_lock; /* allocate/free descriptors */
  150. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  151. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  152. struct mutex ula_lock; /* allocate/free ula */
  153. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  154. struct mutex hw_range_ck_lock; /* range ck */
  155. struct list_head err_handler_list; /* error handler list */
  156. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  157. struct dev_pagemap pgmap;
  158. };
  159. struct ubwcp_buf {
  160. struct hlist_node hnode;
  161. struct ubwcp_driver *ubwcp;
  162. struct ubwcp_buffer_attrs buf_attr;
  163. bool perm;
  164. struct ubwcp_desc *desc;
  165. bool buf_attr_set;
  166. enum dma_data_direction dma_dir;
  167. int lock_count;
  168. /* dma_buf info */
  169. struct dma_buf *dma_buf;
  170. struct dma_buf_attachment *attachment;
  171. struct sg_table *sgt;
  172. /* ula info */
  173. phys_addr_t ula_pa;
  174. size_t ula_size;
  175. /* meta metadata */
  176. struct ubwcp_hw_meta_metadata mmdata;
  177. struct mutex lock;
  178. };
  179. static struct ubwcp_driver *me;
  180. static u32 ubwcp_debug_trace_enable;
  181. static struct ubwcp_driver *ubwcp_get_driver(void)
  182. {
  183. if (!me)
  184. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  185. return me;
  186. }
  187. static void image_format_init(struct ubwcp_driver *ubwcp)
  188. { /* planes, bytes/p, Tp , MTp */
  189. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  190. {1, {{4, 1, {16, 4}, {64, 16}}}};
  191. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  192. {2, {{1, 1, {32, 8}, {128, 32}},
  193. {2, 1, {16, 8}, { 64, 32}}}};
  194. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  195. {2, {{1, 1, {64, 4}, {256, 16}},
  196. {2, 1, {32, 4}, {128, 16}}}};
  197. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  198. {2, {{2, 1, {32, 4}, {128, 16}},
  199. {4, 1, {16, 4}, { 64, 16}}}};
  200. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  201. {2, {{4, 3, {48, 4}, {192, 16}},
  202. {8, 3, {24, 4}, { 96, 16}}}};
  203. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  204. {2, {{2, 1, {32, 4}, {128, 16}},
  205. {4, 1, {16, 4}, { 64, 16}}}};
  206. }
  207. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  208. {
  209. int idx;
  210. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  211. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  212. desc_list[idx].idx = -1;
  213. desc_list[idx].ptr = NULL;
  214. }
  215. }
  216. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  217. {
  218. const char *cname;
  219. struct property *prop;
  220. int i;
  221. ubwcp->num_clocks =
  222. of_property_count_strings(dev->of_node, "clock-names");
  223. if (ubwcp->num_clocks < 1) {
  224. ubwcp->num_clocks = 0;
  225. return 0;
  226. }
  227. ubwcp->clocks = devm_kzalloc(dev,
  228. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  229. if (!ubwcp->clocks)
  230. return -ENOMEM;
  231. i = 0;
  232. of_property_for_each_string(dev->of_node, "clock-names",
  233. prop, cname) {
  234. struct clk *c = devm_clk_get(dev, cname);
  235. if (IS_ERR(c)) {
  236. ERR("Couldn't get clock: %s\n", cname);
  237. return PTR_ERR(c);
  238. }
  239. ubwcp->clocks[i] = c;
  240. ++i;
  241. }
  242. return 0;
  243. }
  244. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  245. {
  246. int i, ret = 0;
  247. for (i = 0; i < ubwcp->num_clocks; ++i) {
  248. ret = clk_prepare_enable(ubwcp->clocks[i]);
  249. if (ret) {
  250. ERR("Couldn't enable clock #%d\n", i);
  251. while (i--)
  252. clk_disable_unprepare(ubwcp->clocks[i]);
  253. break;
  254. }
  255. }
  256. return ret;
  257. }
  258. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  259. {
  260. int i;
  261. for (i = ubwcp->num_clocks; i; --i)
  262. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  263. }
  264. /* UBWCP Power control */
  265. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  266. {
  267. int ret = 0;
  268. if (enable)
  269. ret = regulator_enable(ubwcp->vdd);
  270. else
  271. ret = regulator_disable(ubwcp->vdd);
  272. if (ret) {
  273. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  274. return ret;
  275. }
  276. if (enable) {
  277. ret = ubwcp_enable_clocks(ubwcp);
  278. if (ret) {
  279. ERR("enable clocks failed: %d", ret);
  280. regulator_disable(ubwcp->vdd);
  281. return ret;
  282. }
  283. } else {
  284. ubwcp_disable_clocks(ubwcp);
  285. }
  286. return ret;
  287. }
  288. /* get ubwcp_buf corresponding to the given dma_buf */
  289. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  290. {
  291. struct ubwcp_buf *buf = NULL;
  292. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  293. unsigned long flags;
  294. if (!dmabuf || !ubwcp)
  295. return NULL;
  296. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  297. /* look up ubwcp_buf corresponding to this dma_buf */
  298. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  299. if (buf->dma_buf == dmabuf)
  300. break;
  301. }
  302. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  303. return buf;
  304. }
  305. /* return ubwcp hardware version */
  306. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  307. {
  308. struct ubwcp_driver *ubwcp;
  309. FENTRY();
  310. if (!ver) {
  311. ERR("invalid version ptr");
  312. return -EINVAL;
  313. }
  314. ubwcp = ubwcp_get_driver();
  315. if (!ubwcp)
  316. return -1;
  317. if (ubwcp->state != UBWCP_STATE_FAULT)
  318. return -EPERM;
  319. ver->major = ubwcp->hw_ver_major;
  320. ver->minor = ubwcp->hw_ver_minor;
  321. return 0;
  322. }
  323. EXPORT_SYMBOL(ubwcp_get_hw_version);
  324. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  325. {
  326. int ret = 0;
  327. int nid;
  328. void *ptr;
  329. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  330. DBG("calling memremap_pages()...");
  331. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  332. ubwcp->pgmap.nr_range = 1;
  333. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  334. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  335. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  336. ptr = memremap_pages(&ubwcp->pgmap, nid);
  337. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  338. if (IS_ERR(ptr)) {
  339. ret = IS_ERR(ptr);
  340. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  341. ubwcp->ula_pool_base,
  342. ubwcp->ula_pool_size,
  343. ret);
  344. } else {
  345. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  346. ubwcp->ula_pool_base,
  347. ubwcp->ula_pool_size,
  348. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  349. }
  350. return ret;
  351. }
  352. static int ula_map_uncached(u64 base, u64 size)
  353. {
  354. int ret;
  355. trace_ubwcp_set_direct_map_range_uncached_start(size);
  356. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  357. trace_ubwcp_set_direct_map_range_uncached_end(size);
  358. if (ret)
  359. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  360. base, size >> PAGE_SHIFT, ret);
  361. return ret;
  362. }
  363. static void ula_unmap(struct ubwcp_driver *ubwcp)
  364. {
  365. DBG("Calling memunmap_pages() for ULA PA pool");
  366. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  367. memunmap_pages(&ubwcp->pgmap);
  368. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  369. }
  370. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  371. {
  372. trace_ubwcp_dma_sync_single_for_cpu_start(size);
  373. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  374. trace_ubwcp_dma_sync_single_for_cpu_end(size);
  375. }
  376. /** Remove ula memory in chunks
  377. * Abort if new buffer addition is detected
  378. * If remove succeeds or aborted, return success
  379. * status value indicates if mem was removed or aborted (not removed)
  380. * Otherwise return failure
  381. */
  382. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  383. {
  384. int ret = 0;
  385. unsigned long sync_remain = ubwcp->ula_pool_size;
  386. unsigned long sync_offset = 0;
  387. unsigned long sync_size = 0;
  388. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  389. if (ret)
  390. return ret;
  391. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  392. while (sync_remain > 0) {
  393. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  394. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  395. ula_unmap(ubwcp);
  396. if (ula_add_mem(ubwcp)) {
  397. ERR("remove mem: failed to add back during abort");
  398. return -1;
  399. }
  400. *status = ULA_REMOVE_MEM_ABORTED;
  401. return 0;
  402. }
  403. if (UBWCP_SYNC_GRANULE > sync_remain) {
  404. sync_size = sync_remain;
  405. sync_remain = 0;
  406. } else {
  407. sync_size = UBWCP_SYNC_GRANULE;
  408. sync_remain -= UBWCP_SYNC_GRANULE;
  409. }
  410. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  411. sync_offset += sync_size;
  412. }
  413. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  414. ula_unmap(ubwcp);
  415. *status = ULA_REMOVE_MEM_SUCCESS;
  416. return 0;
  417. }
  418. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  419. {
  420. atomic_inc(&ubwcp->num_non_lin_buffers);
  421. mutex_lock(&ubwcp->mem_hotplug_lock);
  422. if (!ubwcp->mem_online) {
  423. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  424. ERR("Bad state: num_non_lin_buffers should not be 0");
  425. goto err;
  426. }
  427. if (ubwcp_power(ubwcp, true))
  428. goto err;
  429. if (ula_add_mem(ubwcp))
  430. goto err_add_memory;
  431. ubwcp->mem_online = true;
  432. }
  433. mutex_unlock(&ubwcp->mem_hotplug_lock);
  434. return 0;
  435. err_add_memory:
  436. ubwcp_power(ubwcp, false);
  437. err:
  438. atomic_dec(&ubwcp->num_non_lin_buffers);
  439. mutex_unlock(&ubwcp->mem_hotplug_lock);
  440. ubwcp->state = UBWCP_STATE_FAULT;
  441. return -1;
  442. }
  443. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  444. {
  445. int ret;
  446. enum ula_remove_mem_status remove_status;
  447. atomic_dec(&ubwcp->num_non_lin_buffers);
  448. mutex_lock(&ubwcp->mem_hotplug_lock);
  449. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  450. DBG("last buffer: ~~~~~~~~~~~");
  451. if (!ubwcp->mem_online) {
  452. ERR("Bad state: mem_online should not be false");
  453. goto err;
  454. }
  455. ret = ula_remove_mem(ubwcp, &remove_status);
  456. if (ret)
  457. goto err;
  458. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  459. ubwcp->mem_online = false;
  460. if (ubwcp_power(ubwcp, false))
  461. goto err;
  462. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  463. DBG("ula memory offline aborted");
  464. } else {
  465. ERR("unexpected ula remove status: %d", remove_status);
  466. goto err;
  467. }
  468. }
  469. mutex_unlock(&ubwcp->mem_hotplug_lock);
  470. return 0;
  471. err:
  472. atomic_inc(&ubwcp->num_non_lin_buffers);
  473. mutex_unlock(&ubwcp->mem_hotplug_lock);
  474. ubwcp->state = UBWCP_STATE_FAULT;
  475. return -1;
  476. }
  477. /**
  478. *
  479. * Initialize ubwcp buffer for the given dma_buf. This
  480. * initializes ubwcp internal data structures and possibly hw to
  481. * use ubwcp for this buffer.
  482. *
  483. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  484. *
  485. * @return int : 0 on success, otherwise error code
  486. */
  487. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  488. {
  489. struct ubwcp_buf *buf;
  490. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  491. unsigned long flags;
  492. FENTRY();
  493. trace_ubwcp_init_buffer_start(dmabuf);
  494. if (!ubwcp) {
  495. trace_ubwcp_init_buffer_end(dmabuf);
  496. return -1;
  497. }
  498. if (ubwcp->state != UBWCP_STATE_READY) {
  499. ERR("driver in invalid state: %d", ubwcp->state);
  500. trace_ubwcp_init_buffer_end(dmabuf);
  501. return -EPERM;
  502. }
  503. if (!dmabuf) {
  504. ERR("NULL dmabuf input ptr");
  505. trace_ubwcp_init_buffer_end(dmabuf);
  506. return -EINVAL;
  507. }
  508. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  509. ERR("dma_buf already initialized for ubwcp");
  510. trace_ubwcp_init_buffer_end(dmabuf);
  511. return -EEXIST;
  512. }
  513. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  514. if (!buf) {
  515. ERR("failed to alloc for new ubwcp_buf");
  516. trace_ubwcp_init_buffer_end(dmabuf);
  517. return -ENOMEM;
  518. }
  519. mutex_init(&buf->lock);
  520. buf->dma_buf = dmabuf;
  521. buf->ubwcp = ubwcp;
  522. buf->buf_attr.image_format = UBWCP_LINEAR;
  523. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  524. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  525. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  526. trace_ubwcp_init_buffer_end(dmabuf);
  527. return 0;
  528. }
  529. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  530. {
  531. DBG_BUF_ATTR("");
  532. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  533. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  534. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  535. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  536. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  537. DBG_BUF_ATTR("width: %d", attr->width);
  538. DBG_BUF_ATTR("height: %d", attr->height);
  539. DBG_BUF_ATTR("stride: %d", attr->stride);
  540. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  541. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  542. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  543. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  544. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  545. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  546. DBG_BUF_ATTR("");
  547. }
  548. static enum ubwcp_std_image_format to_std_format(u16 ioctl_image_format)
  549. {
  550. switch (ioctl_image_format) {
  551. case UBWCP_RGBA8888:
  552. return RGBA;
  553. case UBWCP_NV12:
  554. case UBWCP_NV12_Y:
  555. case UBWCP_NV12_UV:
  556. return NV12;
  557. case UBWCP_NV124R:
  558. case UBWCP_NV124R_Y:
  559. case UBWCP_NV124R_UV:
  560. return NV124R;
  561. case UBWCP_TP10:
  562. case UBWCP_TP10_Y:
  563. case UBWCP_TP10_UV:
  564. return TP10;
  565. case UBWCP_P010:
  566. case UBWCP_P010_Y:
  567. case UBWCP_P010_UV:
  568. return P010;
  569. case UBWCP_P016:
  570. case UBWCP_P016_Y:
  571. case UBWCP_P016_UV:
  572. return P016;
  573. default:
  574. WARN(1, "Fix this!!!");
  575. return STD_IMAGE_FORMAT_INVALID;
  576. }
  577. }
  578. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  579. {
  580. switch (format) {
  581. case TP10:
  582. *align = 64;
  583. return 0;
  584. case NV12:
  585. *align = 128;
  586. return 0;
  587. case RGBA:
  588. case NV124R:
  589. case P010:
  590. case P016:
  591. *align = 256;
  592. return 0;
  593. default:
  594. return -1;
  595. }
  596. }
  597. /* returns stride of compressed image */
  598. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  599. enum ubwcp_std_image_format format, u32 width)
  600. {
  601. struct ubwcp_plane_info p_info;
  602. u16 macro_tile_width_p;
  603. u16 pixel_bytes;
  604. u16 per_pixel;
  605. p_info = ubwcp->format_info[format].p_info[0];
  606. macro_tile_width_p = p_info.macrotilesize_p.width;
  607. pixel_bytes = p_info.pixel_bytes;
  608. per_pixel = p_info.per_pixel;
  609. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  610. }
  611. static void
  612. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  613. enum ubwcp_std_image_format format,
  614. u32 width_p, u32 height_p,
  615. u32 *width_b, u32 *height_b)
  616. {
  617. u16 pixel_bytes;
  618. u16 per_pixel;
  619. struct ubwcp_image_format_info f_info;
  620. struct ubwcp_plane_info p_info;
  621. f_info = ubwcp->format_info[format];
  622. p_info = f_info.p_info[0];
  623. pixel_bytes = p_info.pixel_bytes;
  624. per_pixel = p_info.per_pixel;
  625. *width_b = (width_p*pixel_bytes)/per_pixel;
  626. *height_b = (height_p*pixel_bytes)/per_pixel;
  627. }
  628. /* check if linear stride conforms to hw limitations
  629. * always returns false for linear image
  630. */
  631. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  632. u16 ioctl_img_fmt, u32 width, u32 lin_stride)
  633. {
  634. u32 compressed_stride;
  635. u32 width_b;
  636. u32 height_b;
  637. enum ubwcp_std_image_format format = to_std_format(ioctl_img_fmt);
  638. if (format == STD_IMAGE_FORMAT_INVALID)
  639. return false;
  640. ubwcp_pixel_to_bytes(ubwcp, format, width, 0, &width_b, &height_b);
  641. if ((lin_stride < width_b) || (lin_stride > MAX_ATTR_STRIDE)) {
  642. ERR("Invalid stride: %u width: %u width_b: %u", lin_stride, width, width_b);
  643. return false;
  644. }
  645. if (format == TP10) {
  646. if(!IS_ALIGNED(lin_stride, 64)) {
  647. ERR("stride must be aligned to 64: %d", lin_stride);
  648. return false;
  649. }
  650. } else {
  651. compressed_stride = get_compressed_stride(ubwcp, format, width);
  652. if (lin_stride != compressed_stride) {
  653. ERR("linear stride: %d must be same as compressed stride: %d",
  654. lin_stride, compressed_stride);
  655. return false;
  656. }
  657. }
  658. return true;
  659. }
  660. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  661. {
  662. switch (ioctl_image_format) {
  663. case UBWCP_LINEAR:
  664. case UBWCP_RGBA8888:
  665. case UBWCP_NV12:
  666. case UBWCP_NV12_Y:
  667. case UBWCP_NV12_UV:
  668. case UBWCP_NV124R:
  669. case UBWCP_NV124R_Y:
  670. case UBWCP_NV124R_UV:
  671. case UBWCP_TP10:
  672. case UBWCP_TP10_Y:
  673. case UBWCP_TP10_UV:
  674. case UBWCP_P010:
  675. case UBWCP_P010_Y:
  676. case UBWCP_P010_UV:
  677. case UBWCP_P016:
  678. case UBWCP_P016_Y:
  679. case UBWCP_P016_UV:
  680. return true;
  681. default:
  682. return false;
  683. }
  684. }
  685. /* validate buffer attributes */
  686. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  687. {
  688. if (!ioctl_format_is_valid(attr->image_format)) {
  689. ERR("invalid image format: %d", attr->image_format);
  690. goto err;
  691. }
  692. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  693. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  694. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  695. goto err;
  696. }
  697. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  698. ERR("compression_type is not valid: %d",
  699. attr->compression_type);
  700. goto err;
  701. }
  702. if (attr->lossy_params != 0) {
  703. ERR("lossy_params is not valid: %d", attr->lossy_params);
  704. goto err;
  705. }
  706. if (attr->width > MAX_ATTR_WIDTH) {
  707. ERR("width is invalid (above upper limit): %d", attr->width);
  708. goto err;
  709. }
  710. if (attr->height > MAX_ATTR_HEIGHT) {
  711. ERR("height is invalid (above upper limit): %d", attr->height);
  712. goto err;
  713. }
  714. if (attr->image_format != UBWCP_LINEAR)
  715. if(!stride_is_valid(ubwcp, attr->image_format, attr->width, attr->stride)) {
  716. ERR("stride is invalid: %d", attr->stride);
  717. goto err;
  718. }
  719. if ((attr->scanlines < attr->height) ||
  720. (attr->scanlines > attr->height + MAX_ATTR_SCANLN_HT_DELTA)) {
  721. ERR("scanlines is not valid - height: %d scanlines: %d",
  722. attr->height, attr->scanlines);
  723. goto err;
  724. }
  725. if (attr->planar_padding > MAX_ATTR_PLANAR_PAD) {
  726. ERR("planar_padding is not valid: %d", attr->planar_padding);
  727. goto err;
  728. }
  729. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  730. ERR("subsample is not valid: %d", attr->subsample);
  731. goto err;
  732. }
  733. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  734. ERR("sub_system_target other that CPU is not supported: %d",
  735. attr->sub_system_target);
  736. goto err;
  737. }
  738. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  739. ERR("sub_system_target is not set to CPU: %d",
  740. attr->sub_system_target);
  741. goto err;
  742. }
  743. if (attr->y_offset != 0) {
  744. ERR("y_offset is not valid: %d", attr->y_offset);
  745. goto err;
  746. }
  747. if (attr->batch_size != 1) {
  748. ERR("batch_size is not valid: %d", attr->batch_size);
  749. goto err;
  750. }
  751. dump_attributes(attr);
  752. return true;
  753. err:
  754. dump_attributes(attr);
  755. return false;
  756. }
  757. /* calculate and return metadata buffer size for a given plane
  758. * and buffer attributes
  759. * NOTE: in this function, we will only pass in NV12 format.
  760. * NOT NV12_Y or NV12_UV etc.
  761. * the Y or UV information is in the "plane"
  762. * "format" here purely means "encoding format" and no information
  763. * if some plane data is missing.
  764. */
  765. static size_t metadata_buf_sz(struct ubwcp_driver *ubwcp,
  766. enum ubwcp_std_image_format format,
  767. u32 width, u32 height, u8 plane)
  768. {
  769. size_t size;
  770. u64 pitch;
  771. u64 lines;
  772. u64 tile_width;
  773. u32 tile_height;
  774. struct ubwcp_image_format_info f_info;
  775. struct ubwcp_plane_info p_info;
  776. f_info = ubwcp->format_info[format];
  777. DBG_BUF_ATTR("");
  778. DBG_BUF_ATTR("");
  779. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  780. if (plane >= f_info.planes) {
  781. ERR("Format does not have requested plane info: format: %d, plane: %d",
  782. format, plane);
  783. WARN(1, "Fix this!!!!!");
  784. return 0;
  785. }
  786. p_info = f_info.p_info[plane];
  787. /* UV plane */
  788. if (plane == 1) {
  789. width = width/2;
  790. height = height/2;
  791. }
  792. tile_width = p_info.tilesize_p.width;
  793. tile_height = p_info.tilesize_p.height;
  794. /* pitch: # of tiles in a row
  795. * lines: # of tile rows
  796. */
  797. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  798. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  799. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  800. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  801. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  802. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  803. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  804. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  805. size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  806. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  807. return size;
  808. }
  809. /* calculate and return size of pixel data buffer for a given plane
  810. * and buffer attributes
  811. */
  812. static size_t pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  813. u16 format, u32 width,
  814. u32 height, u8 plane)
  815. {
  816. size_t size;
  817. u64 pitch;
  818. u64 lines;
  819. u16 pixel_bytes;
  820. u16 per_pixel;
  821. u64 macro_tile_width_p;
  822. u64 macro_tile_height_p;
  823. struct ubwcp_image_format_info f_info;
  824. struct ubwcp_plane_info p_info;
  825. f_info = ubwcp->format_info[format];
  826. DBG_BUF_ATTR("");
  827. DBG_BUF_ATTR("");
  828. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  829. if (plane >= f_info.planes) {
  830. ERR("Format does not have requested plane info: format: %d, plane: %d",
  831. format, plane);
  832. WARN(1, "Fix this!!!!!");
  833. return 0;
  834. }
  835. p_info = f_info.p_info[plane];
  836. pixel_bytes = p_info.pixel_bytes;
  837. per_pixel = p_info.per_pixel;
  838. /* UV plane */
  839. if (plane == 1) {
  840. width = width/2;
  841. height = height/2;
  842. }
  843. macro_tile_width_p = p_info.macrotilesize_p.width;
  844. macro_tile_height_p = p_info.macrotilesize_p.height;
  845. /* align pixel width and height macro tile width and height */
  846. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  847. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  848. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  849. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  850. macro_tile_height_p);
  851. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  852. DBG_BUF_ATTR("pitch : %d", pitch);
  853. DBG_BUF_ATTR("lines : %d", lines);
  854. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  855. size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  856. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  857. return size;
  858. }
  859. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  860. u8 plane)
  861. {
  862. struct ubwcp_image_format_info f_info;
  863. struct ubwcp_plane_info p_info;
  864. f_info = ubwcp->format_info[format];
  865. p_info = f_info.p_info[plane];
  866. return p_info.tilesize_p.height;
  867. }
  868. /*
  869. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  870. */
  871. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  872. u32 stride_b, u32 scanlines, u8 plane,
  873. bool add_tile_pad)
  874. {
  875. size_t size;
  876. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  877. /* UV plane */
  878. if (plane == 1)
  879. scanlines = scanlines/2;
  880. if (add_tile_pad) {
  881. int tile_height = get_tile_height(ubwcp, format, plane);
  882. /* Align plane size to plane tile height */
  883. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  884. }
  885. size = stride_b*scanlines;
  886. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  887. plane, stride_b, scanlines, size, size);
  888. return size;
  889. }
  890. static int missing_plane_from_format(u16 ioctl_image_format)
  891. {
  892. int missing_plane;
  893. switch (ioctl_image_format) {
  894. case UBWCP_NV12_Y:
  895. missing_plane = 2;
  896. break;
  897. case UBWCP_NV12_UV:
  898. missing_plane = 1;
  899. break;
  900. case UBWCP_NV124R_Y:
  901. missing_plane = 2;
  902. break;
  903. case UBWCP_NV124R_UV:
  904. missing_plane = 1;
  905. break;
  906. case UBWCP_TP10_Y:
  907. missing_plane = 2;
  908. break;
  909. case UBWCP_TP10_UV:
  910. missing_plane = 1;
  911. break;
  912. case UBWCP_P010_Y:
  913. missing_plane = 2;
  914. break;
  915. case UBWCP_P010_UV:
  916. missing_plane = 1;
  917. break;
  918. case UBWCP_P016_Y:
  919. missing_plane = 2;
  920. break;
  921. case UBWCP_P016_UV:
  922. missing_plane = 1;
  923. break;
  924. default:
  925. missing_plane = 0;
  926. }
  927. return missing_plane;
  928. }
  929. static int planes_in_format(enum ubwcp_std_image_format format)
  930. {
  931. if (format == RGBA)
  932. return 1;
  933. else
  934. return 2;
  935. }
  936. static unsigned int ubwcp_get_hw_image_format_value(u16 ioctl_image_format)
  937. {
  938. enum ubwcp_std_image_format format;
  939. format = to_std_format(ioctl_image_format);
  940. switch (format) {
  941. case RGBA:
  942. return HW_BUFFER_FORMAT_RGBA;
  943. case NV12:
  944. return HW_BUFFER_FORMAT_NV12;
  945. case NV124R:
  946. return HW_BUFFER_FORMAT_NV124R;
  947. case P010:
  948. return HW_BUFFER_FORMAT_P010;
  949. case TP10:
  950. return HW_BUFFER_FORMAT_TP10;
  951. case P016:
  952. return HW_BUFFER_FORMAT_P016;
  953. default:
  954. WARN(1, "Fix this!!!!!");
  955. return 0;
  956. }
  957. }
  958. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  959. struct ubwcp_buffer_attrs *attr,
  960. size_t ula_y_plane_size,
  961. size_t uv_start_offset)
  962. {
  963. int ret = 0;
  964. size_t ula_y_plane_size_align;
  965. size_t y_tile_align_bytes;
  966. int y_tile_height;
  967. int planes;
  968. /* Only validate UV align if there is both a Y and UV plane */
  969. planes = planes_in_format(to_std_format(attr->image_format));
  970. if (planes != 2)
  971. return 0;
  972. /* Check it is cache line size aligned */
  973. if ((uv_start_offset % 64) != 0) {
  974. ret = -EINVAL;
  975. ERR("uv_start_offset %zu not cache line aligned",
  976. uv_start_offset);
  977. goto err;
  978. }
  979. /*
  980. * Check that UV plane does not overlap with any of the Y plane’s tiles
  981. */
  982. y_tile_height = get_tile_height(ubwcp, to_std_format(attr->image_format), 0);
  983. y_tile_align_bytes = y_tile_height * attr->stride;
  984. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  985. y_tile_align_bytes) * y_tile_align_bytes;
  986. if (uv_start_offset < ula_y_plane_size_align) {
  987. ret = -EINVAL;
  988. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  989. uv_start_offset, ula_y_plane_size_align,
  990. ula_y_plane_size);
  991. goto err;
  992. }
  993. return 0;
  994. err:
  995. return ret;
  996. }
  997. /* calculate ULA buffer parms */
  998. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  999. struct ubwcp_buffer_attrs *attr,
  1000. size_t *ula_size,
  1001. size_t *ula_y_plane_size,
  1002. size_t *uv_start_offset)
  1003. {
  1004. size_t size;
  1005. enum ubwcp_std_image_format format;
  1006. int planes;
  1007. int missing_plane;
  1008. u32 stride;
  1009. u32 scanlines;
  1010. u32 planar_padding;
  1011. stride = attr->stride;
  1012. scanlines = attr->scanlines;
  1013. planar_padding = attr->planar_padding;
  1014. /* convert ioctl image format to standard image format */
  1015. format = to_std_format(attr->image_format);
  1016. /* Number of "expected" planes in "the standard defined" image format */
  1017. planes = planes_in_format(format);
  1018. /* any plane missing?
  1019. * valid missing_plane values:
  1020. * 0 == no plane missing
  1021. * 1 == 1st plane missing
  1022. * 2 == 2nd plane missing
  1023. */
  1024. missing_plane = missing_plane_from_format(attr->image_format);
  1025. DBG_BUF_ATTR("ula params -->");
  1026. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1027. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1028. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1029. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1030. if (planes == 1) {
  1031. /* uv_start beyond ULA range */
  1032. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1033. *uv_start_offset = size;
  1034. *ula_y_plane_size = size;
  1035. } else {
  1036. if (!missing_plane) {
  1037. /* size for both planes and padding */
  1038. /* Don't pad out Y plane as client would not expect this padding */
  1039. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1040. *ula_y_plane_size = size;
  1041. size += planar_padding;
  1042. *uv_start_offset = size;
  1043. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1044. } else {
  1045. if (missing_plane == 2) {
  1046. /* Y-only image, set uv_start beyond ULA range */
  1047. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1048. *uv_start_offset = size;
  1049. *ula_y_plane_size = size;
  1050. } else {
  1051. /* first plane data is not there */
  1052. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1053. *uv_start_offset = 0; /* uv data is at the beginning */
  1054. *ula_y_plane_size = 0;
  1055. }
  1056. }
  1057. }
  1058. *ula_size = UBWCP_ALIGN(size, 4096);
  1059. DBG_BUF_ATTR("ULA_Size: %zu (0x%x) (before 4K align: %zu)", *ula_size, *ula_size, size);
  1060. return 0;
  1061. }
  1062. /* calculate UBWCP buffer parms */
  1063. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1064. struct ubwcp_buffer_attrs *attr,
  1065. size_t *md_p0, size_t *pd_p0,
  1066. size_t *md_p1, size_t *pd_p1,
  1067. size_t *stride_tp10_b)
  1068. {
  1069. int planes;
  1070. int missing_plane;
  1071. enum ubwcp_std_image_format format;
  1072. size_t stride_tp10_p;
  1073. FENTRY();
  1074. /* convert ioctl image format to standard image format */
  1075. format = to_std_format(attr->image_format);
  1076. missing_plane = missing_plane_from_format(attr->image_format);
  1077. planes = planes_in_format(format);
  1078. DBG_BUF_ATTR("ubwcp params -->");
  1079. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1080. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1081. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1082. *md_p0 = 0;
  1083. *pd_p0 = 0;
  1084. *md_p1 = 0;
  1085. *pd_p1 = 0;
  1086. *stride_tp10_b = 0;
  1087. if (!missing_plane) {
  1088. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1089. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1090. if (planes == 2) {
  1091. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1092. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1093. }
  1094. } else {
  1095. if (missing_plane == 1) {
  1096. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1097. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1098. } else {
  1099. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1100. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1101. }
  1102. }
  1103. if (format == TP10) {
  1104. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1105. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1106. }
  1107. return 0;
  1108. }
  1109. /* reserve ULA address space of the given size */
  1110. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1111. {
  1112. phys_addr_t pa;
  1113. mutex_lock(&ubwcp->ula_lock);
  1114. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1115. mutex_unlock(&ubwcp->ula_lock);
  1116. return pa;
  1117. }
  1118. /* free ULA address space of the given address and size */
  1119. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1120. {
  1121. mutex_lock(&ubwcp->ula_lock);
  1122. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1123. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1124. goto err;
  1125. }
  1126. DBG("addr: %p, size: %zx", pa, size);
  1127. gen_pool_free(ubwcp->ula_pool, pa, size);
  1128. mutex_unlock(&ubwcp->ula_lock);
  1129. return;
  1130. err:
  1131. mutex_unlock(&ubwcp->ula_lock);
  1132. }
  1133. /* free up or expand current_pa and return the new pa */
  1134. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1135. phys_addr_t pa,
  1136. size_t size,
  1137. size_t new_size)
  1138. {
  1139. if (size == new_size)
  1140. return pa;
  1141. if (pa)
  1142. ubwcp_ula_free(ubwcp, pa, size);
  1143. return ubwcp_ula_alloc(ubwcp, new_size);
  1144. }
  1145. /* unmap dma buf */
  1146. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1147. {
  1148. FENTRY();
  1149. if (buf->dma_buf && buf->attachment) {
  1150. DBG("Calling dma_buf_unmap_attachment()");
  1151. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1152. buf->sgt = NULL;
  1153. dma_buf_detach(buf->dma_buf, buf->attachment);
  1154. buf->attachment = NULL;
  1155. }
  1156. }
  1157. static bool verify_dma_buf_size(struct ubwcp_buf *buf, size_t min_size)
  1158. {
  1159. size_t dma_len;
  1160. dma_len = sg_dma_len(buf->sgt->sgl);
  1161. if (dma_len < min_size) {
  1162. ERR("dma len: %zu is less than min ubwcp buffer size: %zu", dma_len, min_size);
  1163. return false;
  1164. } else
  1165. return true;
  1166. }
  1167. /* dma map ubwcp buffer */
  1168. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1169. struct device *dev,
  1170. dma_addr_t *iova)
  1171. {
  1172. int ret = 0;
  1173. struct dma_buf *dma_buf = buf->dma_buf;
  1174. struct dma_buf_attachment *attachment;
  1175. struct sg_table *sgt;
  1176. /* Map buffer to SMMU and get IOVA */
  1177. attachment = dma_buf_attach(dma_buf, dev);
  1178. if (IS_ERR(attachment)) {
  1179. ret = PTR_ERR(attachment);
  1180. ERR("dma_buf_attach() failed: %d", ret);
  1181. goto err;
  1182. }
  1183. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1184. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1185. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1186. if (IS_ERR_OR_NULL(sgt)) {
  1187. ret = PTR_ERR(sgt);
  1188. ERR("dma_buf_map_attachment() failed: %d", ret);
  1189. goto err_detach;
  1190. }
  1191. if (sgt->nents != 1) {
  1192. ERR("nents = %d", sgt->nents);
  1193. goto err_unmap;
  1194. }
  1195. *iova = sg_dma_address(sgt->sgl);
  1196. buf->attachment = attachment;
  1197. buf->sgt = sgt;
  1198. return ret;
  1199. err_unmap:
  1200. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1201. err_detach:
  1202. dma_buf_detach(dma_buf, attachment);
  1203. err:
  1204. if (!ret)
  1205. ret = -1;
  1206. return ret;
  1207. }
  1208. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1209. {
  1210. struct ubwcp_hw_meta_metadata *mmdata;
  1211. struct ubwcp_driver *ubwcp;
  1212. ubwcp = buf->ubwcp;
  1213. mmdata = &buf->mmdata;
  1214. ubwcp_dma_unmap(buf);
  1215. /* reset ula params */
  1216. if (buf->ula_size) {
  1217. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1218. buf->ula_size = 0;
  1219. buf->ula_pa = 0;
  1220. }
  1221. /* reset ubwcp params */
  1222. memset(mmdata, 0, sizeof(*mmdata));
  1223. buf->buf_attr_set = false;
  1224. buf->buf_attr.image_format = UBWCP_LINEAR;
  1225. }
  1226. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1227. {
  1228. DBG_BUF_ATTR("");
  1229. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1230. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1231. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1232. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1233. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1234. mmdata->stride, mmdata->stride << 6);
  1235. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1236. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1237. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1238. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1239. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1240. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1241. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1242. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1243. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1244. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1245. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1246. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1247. DBG_BUF_ATTR("");
  1248. }
  1249. /* set buffer attributes:
  1250. * Failure:
  1251. * This call may fail for multiple reasons and it will leave the buffer in an undefined state.
  1252. * In some situations it may leave the buffer in linear mapped state, and in other situations it
  1253. * may leave the buffer in previously set attributes state.
  1254. */
  1255. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1256. {
  1257. int ret = 0;
  1258. size_t ula_size = 0;
  1259. size_t uv_start_offset = 0;
  1260. size_t ula_y_plane_size = 0;
  1261. phys_addr_t ula_pa = 0x0;
  1262. struct ubwcp_buf *buf;
  1263. struct ubwcp_driver *ubwcp;
  1264. size_t metadata_p0;
  1265. size_t pixeldata_p0;
  1266. size_t metadata_p1;
  1267. size_t pixeldata_p1;
  1268. size_t iova_min_size;
  1269. size_t stride_tp10_b;
  1270. dma_addr_t iova_base;
  1271. struct ubwcp_hw_meta_metadata *mmdata;
  1272. u64 uv_start;
  1273. u32 stride_b;
  1274. u32 width_b;
  1275. u32 height_b;
  1276. enum ubwcp_std_image_format std_image_format;
  1277. bool is_non_lin_buf;
  1278. FENTRY();
  1279. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1280. if (!dmabuf) {
  1281. ERR("NULL dmabuf input ptr");
  1282. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1283. return -EINVAL;
  1284. }
  1285. if (!attr) {
  1286. ERR("NULL attr ptr");
  1287. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1288. return -EINVAL;
  1289. }
  1290. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1291. if (!buf) {
  1292. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1293. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1294. return -EINVAL;
  1295. }
  1296. ubwcp = buf->ubwcp;
  1297. if (ubwcp->state != UBWCP_STATE_READY)
  1298. return -EPERM;
  1299. mutex_lock(&buf->lock);
  1300. if (buf->lock_count) {
  1301. ERR("Cannot set attr when buffer is locked");
  1302. ret = -EBUSY;
  1303. goto unlock;
  1304. }
  1305. mmdata = &buf->mmdata;
  1306. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1307. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1308. ERR("Invalid buf attrs");
  1309. goto unlock;
  1310. }
  1311. /* note: this also checks if buf is mmap'ed */
  1312. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1313. if (ret) {
  1314. ERR("dma_buf_mmap_config(0,0) failed: %d", ret);
  1315. goto unlock;
  1316. }
  1317. if (attr->image_format == UBWCP_LINEAR) {
  1318. DBG_BUF_ATTR("Linear format requested");
  1319. if (buf->buf_attr_set)
  1320. reset_buf_attrs(buf);
  1321. if (is_non_lin_buf) {
  1322. /*
  1323. * Changing buffer from ubwc to linear so decrement
  1324. * number of ubwc buffers
  1325. */
  1326. ret = dec_num_non_lin_buffers(ubwcp);
  1327. }
  1328. mutex_unlock(&buf->lock);
  1329. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1330. return ret;
  1331. }
  1332. std_image_format = to_std_format(attr->image_format);
  1333. if (std_image_format == STD_IMAGE_FORMAT_INVALID) {
  1334. ERR("Unable to map ioctl image format to std image format");
  1335. goto unlock;
  1336. }
  1337. /* Calculate uncompressed-buffer size. */
  1338. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1339. if (ret) {
  1340. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1341. goto unlock;
  1342. }
  1343. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1344. if (ret) {
  1345. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1346. goto unlock;
  1347. }
  1348. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr, &metadata_p0, &pixeldata_p0, &metadata_p1,
  1349. &pixeldata_p1, &stride_tp10_b);
  1350. if (ret) {
  1351. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1352. goto unlock;
  1353. }
  1354. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1355. DBG_BUF_ATTR("");
  1356. DBG_BUF_ATTR("");
  1357. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1358. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1359. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1360. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1361. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1362. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1363. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1364. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1365. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1366. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1367. DBG_BUF_ATTR("");
  1368. /* assign ULA PA with uncompressed-size range */
  1369. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1370. if (!ula_pa) {
  1371. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1372. goto err;
  1373. }
  1374. buf->ula_size = ula_size;
  1375. buf->ula_pa = ula_pa;
  1376. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1377. DBG_BUF_ATTR("");
  1378. /* dma map only the first time attribute is set */
  1379. if (!buf->buf_attr_set) {
  1380. /* linear -> ubwcp. map ubwcp buffer */
  1381. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, &iova_base);
  1382. if (ret) {
  1383. ERR("ubwcp_dma_map() failed: %d", ret);
  1384. goto err;
  1385. }
  1386. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1387. iova_base, iova_min_size, iova_base + iova_min_size);
  1388. }
  1389. if(!verify_dma_buf_size(buf, iova_min_size))
  1390. goto err;
  1391. uv_start = ula_pa + uv_start_offset;
  1392. if (!IS_ALIGNED(uv_start, 64)) {
  1393. ERR("ERROR: uv_start is NOT aligned to cache line");
  1394. goto err;
  1395. }
  1396. /* Convert height and width to bytes for writing to mmdata */
  1397. if (std_image_format != TP10) {
  1398. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1399. attr->height, &width_b, &height_b);
  1400. } else {
  1401. /* for tp10 image compression, we need to program p010 width/height */
  1402. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1403. attr->height, &width_b, &height_b);
  1404. }
  1405. stride_b = attr->stride;
  1406. /* create the mmdata descriptor */
  1407. memset(mmdata, 0, sizeof(*mmdata));
  1408. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1409. mmdata->format = ubwcp_get_hw_image_format_value(attr->image_format);
  1410. if (std_image_format != TP10) {
  1411. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1412. } else {
  1413. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1414. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1415. }
  1416. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1417. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1418. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1419. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1420. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1421. * For other versions, width in bytes & height in pixels.
  1422. */
  1423. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1424. mmdata->width_height = width_b << 16 | height_b;
  1425. else
  1426. mmdata->width_height = width_b << 16 | attr->height;
  1427. print_mmdata_desc(mmdata);
  1428. if (!is_non_lin_buf) {
  1429. /*
  1430. * Changing buffer from linear to ubwc so increment
  1431. * number of ubwc buffers
  1432. */
  1433. ret = inc_num_non_lin_buffers(ubwcp);
  1434. }
  1435. if (ret) {
  1436. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1437. goto err;
  1438. }
  1439. /* inform ULA-PA to dma-heap */
  1440. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1441. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa, buf->ula_size);
  1442. if (ret) {
  1443. ERR("dma_buf_mmap_config() failed: %d", ret);
  1444. if (!is_non_lin_buf)
  1445. dec_num_non_lin_buffers(ubwcp);
  1446. goto err;
  1447. }
  1448. buf->buf_attr = *attr;
  1449. buf->buf_attr_set = true;
  1450. mutex_unlock(&buf->lock);
  1451. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1452. return 0;
  1453. err:
  1454. reset_buf_attrs(buf);
  1455. if (is_non_lin_buf) {
  1456. /*
  1457. * Changing buffer from ubwc to linear so decrement
  1458. * number of ubwc buffers
  1459. */
  1460. dec_num_non_lin_buffers(ubwcp);
  1461. }
  1462. unlock:
  1463. mutex_unlock(&buf->lock);
  1464. if (!ret)
  1465. ret = -1;
  1466. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1467. return ret;
  1468. }
  1469. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1470. /* Set buffer attributes ioctl */
  1471. static int ubwcp_set_buf_attrs_ioctl(struct ubwcp_ioctl_buffer_attrs *attr_ioctl)
  1472. {
  1473. int ret;
  1474. struct dma_buf *dmabuf;
  1475. dmabuf = dma_buf_get(attr_ioctl->fd);
  1476. if (IS_ERR(dmabuf)) {
  1477. ERR("dmabuf ptr not found for dma_buf_fd = %d", dma_buf_fd);
  1478. return PTR_ERR(dmabuf);
  1479. }
  1480. ret = ubwcp_set_buf_attrs(dmabuf, &attr_ioctl->attr);
  1481. dma_buf_put(dmabuf);
  1482. return ret;
  1483. }
  1484. /* Free up the buffer descriptor */
  1485. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1486. {
  1487. int idx = desc->idx;
  1488. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1489. mutex_lock(&ubwcp->desc_lock);
  1490. desc_list[idx].idx = -1;
  1491. desc_list[idx].ptr = NULL;
  1492. DBG("freed descriptor_id: %d", idx);
  1493. mutex_unlock(&ubwcp->desc_lock);
  1494. }
  1495. /* Allocate next available buffer descriptor. */
  1496. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1497. {
  1498. int idx;
  1499. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1500. mutex_lock(&ubwcp->desc_lock);
  1501. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1502. if (desc_list[idx].idx == -1) {
  1503. desc_list[idx].idx = idx;
  1504. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1505. idx*UBWCP_BUFFER_DESC_OFFSET;
  1506. DBG("allocated descriptor_id: %d", idx);
  1507. mutex_unlock(&ubwcp->desc_lock);
  1508. return &desc_list[idx];
  1509. }
  1510. }
  1511. mutex_unlock(&ubwcp->desc_lock);
  1512. return NULL;
  1513. }
  1514. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1515. {
  1516. int ret = 0;
  1517. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1518. trace_ubwcp_hw_flush_start(0);
  1519. ret = ubwcp_hw_flush(ubwcp->base);
  1520. trace_ubwcp_hw_flush_end(0);
  1521. if (ret)
  1522. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1523. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1524. return ret;
  1525. }
  1526. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1527. {
  1528. int ret;
  1529. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1530. mutex_lock(&ubwcp->hw_range_ck_lock);
  1531. trace_ubwcp_hw_flush_start(0);
  1532. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1533. trace_ubwcp_hw_flush_end(0);
  1534. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1535. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1536. return ret;
  1537. }
  1538. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1539. {
  1540. mutex_lock(&ubwcp->hw_range_ck_lock);
  1541. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1542. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1543. }
  1544. /**
  1545. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1546. * CPU access to the compressed buffer. It will perform
  1547. * necessary address translation configuration and cache maintenance ops
  1548. * so that CPU can safely access ubwcp buffer, if this call is
  1549. * successful.
  1550. * Allocate descriptor if not already,
  1551. * perform CMO and then enable range check
  1552. *
  1553. * @param dmabuf : ptr to the dma buf
  1554. * @param direction : direction of access
  1555. *
  1556. * @return int : 0 on success, otherwise error code
  1557. */
  1558. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1559. {
  1560. int ret = 0;
  1561. struct ubwcp_buf *buf;
  1562. struct ubwcp_driver *ubwcp;
  1563. FENTRY();
  1564. trace_ubwcp_lock_start(dmabuf);
  1565. if (!dmabuf) {
  1566. ERR("NULL dmabuf input ptr");
  1567. trace_ubwcp_lock_end(dmabuf);
  1568. return -EINVAL;
  1569. }
  1570. if (!valid_dma_direction(dir)) {
  1571. ERR("invalid direction: %d", dir);
  1572. trace_ubwcp_lock_end(dmabuf);
  1573. return -EINVAL;
  1574. }
  1575. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1576. if (!buf) {
  1577. ERR("ubwcp_buf ptr not found");
  1578. trace_ubwcp_lock_end(dmabuf);
  1579. return -1;
  1580. }
  1581. ubwcp = buf->ubwcp;
  1582. if (ubwcp->state != UBWCP_STATE_READY) {
  1583. ERR("driver in invalid state: %d", ubwcp->state);
  1584. trace_ubwcp_lock_end(dmabuf);
  1585. return -EPERM;
  1586. }
  1587. mutex_lock(&buf->lock);
  1588. if (!buf->buf_attr_set) {
  1589. ERR("lock() called on buffer, but attr not set");
  1590. goto err;
  1591. }
  1592. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1593. ERR("lock() called on linear buffer");
  1594. goto err;
  1595. }
  1596. if (!buf->lock_count) {
  1597. DBG("first lock on buffer");
  1598. /* buf->desc could already be allocated because of perm range xlation */
  1599. if (!buf->desc) {
  1600. /* allocate a buffer descriptor */
  1601. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1602. if (!buf->desc) {
  1603. ERR("ubwcp_allocate_buf_desc() failed");
  1604. goto err;
  1605. }
  1606. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1607. /* Flushing of updated mmdata:
  1608. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1609. * *as long as* it has not cached that itself during previous
  1610. * access to the same descriptor.
  1611. *
  1612. * During unlock of previous use of this descriptor,
  1613. * we do hw flush, which will get rid of this mmdata from
  1614. * ubwcp cache.
  1615. *
  1616. * In addition, we also do a hw flush after enable_range_ck().
  1617. * That will also get rid of any speculative fetch of mmdata
  1618. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1619. * will cache mmdata only for active descriptor. But if ubwcp
  1620. * is speculatively fetching mmdata for all descriptors
  1621. * (irrespetive of enabled or not), the flush during lock
  1622. * will be necessary to make sure ubwcp sees updated mmdata
  1623. * that we just updated
  1624. */
  1625. /* program ULA range for this buffer */
  1626. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1627. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1628. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1629. buf->ula_size);
  1630. }
  1631. /* enable range check */
  1632. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1633. range_check_enable(ubwcp, buf->desc->idx);
  1634. /* Flush/invalidate UBWCP caches */
  1635. /* Why: cpu could have done a speculative fetch before
  1636. * enable_range_ck() and ubwcp in process of returning "default" data
  1637. * we don't want that stashing of default data pending.
  1638. * we force completion of that and then we also cpu invalidate which
  1639. * will get rid of that line.
  1640. */
  1641. ret = ubwcp_flush(ubwcp);
  1642. if (ret) {
  1643. ubwcp->state = UBWCP_STATE_FAULT;
  1644. ERR("ubwcp_flush() failed: %d, driver state set to FAULT", ret);
  1645. goto err_flush_failed;
  1646. }
  1647. /* Flush/invalidate ULA PA from CPU caches
  1648. * Always invalidate cache, even when writing.
  1649. * Upgrade direction to force invalidate.
  1650. */
  1651. if (dir == DMA_TO_DEVICE)
  1652. dir = DMA_BIDIRECTIONAL;
  1653. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size);
  1654. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1655. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size);
  1656. buf->dma_dir = dir;
  1657. } else {
  1658. DBG("buf already locked");
  1659. /* For write locks, always upgrade direction to bi_directional.
  1660. * A previous read lock will now become write lock.
  1661. * This will ensure a flush when the last unlock comes in.
  1662. */
  1663. if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
  1664. buf->dma_dir = DMA_BIDIRECTIONAL;
  1665. }
  1666. buf->lock_count++;
  1667. DBG("new lock_count: %d", buf->lock_count);
  1668. mutex_unlock(&buf->lock);
  1669. trace_ubwcp_lock_end(dmabuf);
  1670. return ret;
  1671. err_flush_failed:
  1672. range_check_disable(ubwcp, buf->desc->idx);
  1673. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1674. buf->desc = NULL;
  1675. err:
  1676. mutex_unlock(&buf->lock);
  1677. if (!ret)
  1678. ret = -1;
  1679. trace_ubwcp_lock_end(dmabuf);
  1680. return ret;
  1681. }
  1682. /* This can be called as a result of external unlock() call or
  1683. * internally if free() is called without unlock().
  1684. */
  1685. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1686. {
  1687. int ret = 0;
  1688. struct ubwcp_driver *ubwcp;
  1689. DBG("current lock_count: %d", buf->lock_count);
  1690. if (free_buffer) {
  1691. buf->lock_count = 0;
  1692. DBG("Forced lock_count: %d", buf->lock_count);
  1693. } else {
  1694. /* for write unlocks, remember the direction so we flush on last unlock */
  1695. if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
  1696. buf->dma_dir = DMA_BIDIRECTIONAL;
  1697. buf->lock_count--;
  1698. DBG("new lock_count: %d", buf->lock_count);
  1699. if (buf->lock_count) {
  1700. DBG("more than 1 lock on buffer. waiting until last unlock");
  1701. return 0;
  1702. }
  1703. }
  1704. ubwcp = buf->ubwcp;
  1705. /* Flush/invalidate ULA PA from CPU caches */
  1706. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size);
  1707. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, buf->dma_dir);
  1708. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size);
  1709. /* disable range check */
  1710. DBG("disabling range check");
  1711. ret = range_check_disable(ubwcp, buf->desc->idx);
  1712. if (ret) {
  1713. ubwcp->state = UBWCP_STATE_FAULT;
  1714. ERR("disable_range_check_with_flush() failed: %d, driver state set to FAULT", ret);
  1715. }
  1716. /* release descriptor if perm range xlation is not set */
  1717. if (!buf->perm) {
  1718. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1719. buf->desc = NULL;
  1720. }
  1721. return ret;
  1722. }
  1723. /**
  1724. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1725. * safely allow for device access to the compressed buffer including any
  1726. * necessary cache maintenance ops. It may also free up certain ubwcp
  1727. * resources that could result in error when accessed by CPU in
  1728. * unlocked state.
  1729. *
  1730. * @param dmabuf : ptr to the dma buf
  1731. * @param direction : direction of access
  1732. *
  1733. * @return int : 0 on success, otherwise error code
  1734. */
  1735. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1736. {
  1737. struct ubwcp_buf *buf;
  1738. int ret;
  1739. FENTRY();
  1740. trace_ubwcp_unlock_start(dmabuf);
  1741. if (!dmabuf) {
  1742. ERR("NULL dmabuf input ptr");
  1743. trace_ubwcp_unlock_end(dmabuf);
  1744. return -EINVAL;
  1745. }
  1746. if (!valid_dma_direction(dir)) {
  1747. ERR("invalid direction: %d", dir);
  1748. trace_ubwcp_unlock_end(dmabuf);
  1749. return -EINVAL;
  1750. }
  1751. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1752. if (!buf) {
  1753. ERR("ubwcp_buf not found");
  1754. trace_ubwcp_unlock_end(dmabuf);
  1755. return -1;
  1756. }
  1757. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1758. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1759. trace_ubwcp_unlock_end(dmabuf);
  1760. return -EPERM;
  1761. }
  1762. mutex_lock(&buf->lock);
  1763. if (!buf->lock_count) {
  1764. ERR("unlock() called on buffer which not in locked state");
  1765. trace_ubwcp_unlock_end(dmabuf);
  1766. mutex_unlock(&buf->lock);
  1767. return -1;
  1768. }
  1769. ret = unlock_internal(buf, dir, false);
  1770. mutex_unlock(&buf->lock);
  1771. trace_ubwcp_unlock_end(dmabuf);
  1772. return ret;
  1773. }
  1774. /* Return buffer attributes for the given buffer */
  1775. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1776. {
  1777. int ret = 0;
  1778. struct ubwcp_buf *buf;
  1779. FENTRY();
  1780. if (!dmabuf) {
  1781. ERR("NULL dmabuf input ptr");
  1782. return -EINVAL;
  1783. }
  1784. if (!attr) {
  1785. ERR("NULL attr ptr");
  1786. return -EINVAL;
  1787. }
  1788. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1789. if (!buf) {
  1790. ERR("ubwcp_buf ptr not found");
  1791. return -1;
  1792. }
  1793. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1794. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1795. return -EPERM;
  1796. }
  1797. mutex_lock(&buf->lock);
  1798. if (!buf->buf_attr_set) {
  1799. ERR("buffer attributes not set");
  1800. mutex_unlock(&buf->lock);
  1801. return -1;
  1802. }
  1803. *attr = buf->buf_attr;
  1804. mutex_unlock(&buf->lock);
  1805. return ret;
  1806. }
  1807. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1808. /* Set permanent range translation.
  1809. * enable: Descriptor will be reserved for this buffer until disabled,
  1810. * making lock/unlock quicker.
  1811. * disable: Descriptor will not be reserved for this buffer. Instead,
  1812. * descriptor will be allocated and released for each lock/unlock.
  1813. * If currently allocated but not being used, descriptor will be
  1814. * released.
  1815. */
  1816. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1817. {
  1818. int ret = 0;
  1819. struct ubwcp_buf *buf;
  1820. FENTRY();
  1821. if (!dmabuf) {
  1822. ERR("NULL dmabuf input ptr");
  1823. return -EINVAL;
  1824. }
  1825. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1826. if (!buf) {
  1827. ERR("ubwcp_buf not found");
  1828. return -1;
  1829. }
  1830. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1831. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1832. return -EPERM;
  1833. }
  1834. /* not implemented */
  1835. if (1) {
  1836. ERR("API not implemented yet");
  1837. return -1;
  1838. }
  1839. /* TBD: make sure we acquire buf lock while setting this so there is
  1840. * no race condition with attr_set/lock/unlock
  1841. */
  1842. buf->perm = enable;
  1843. /* if "disable" and we have allocated a desc and it is not being
  1844. * used currently, release it
  1845. */
  1846. if (!enable && buf->desc && !buf->lock_count) {
  1847. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1848. buf->desc = NULL;
  1849. /* Flush/invalidate UBWCP caches */
  1850. //TBD: need to do anything?
  1851. }
  1852. return ret;
  1853. }
  1854. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1855. /**
  1856. * Free up ubwcp resources for this buffer.
  1857. *
  1858. * @param dmabuf : ptr to the dma buf
  1859. *
  1860. * @return int : 0 on success, otherwise error code
  1861. */
  1862. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1863. {
  1864. int ret = 0;
  1865. struct ubwcp_buf *buf;
  1866. struct ubwcp_driver *ubwcp;
  1867. unsigned long flags;
  1868. bool is_non_lin_buf;
  1869. FENTRY();
  1870. trace_ubwcp_free_buffer_start(dmabuf);
  1871. if (!dmabuf) {
  1872. ERR("NULL dmabuf input ptr");
  1873. trace_ubwcp_free_buffer_end(dmabuf);
  1874. return -EINVAL;
  1875. }
  1876. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1877. if (!buf) {
  1878. ERR("ubwcp_buf ptr not found");
  1879. trace_ubwcp_free_buffer_end(dmabuf);
  1880. return -1;
  1881. }
  1882. ubwcp = buf->ubwcp;
  1883. if (ubwcp->state != UBWCP_STATE_READY) {
  1884. ERR("driver in invalid state: %d", ubwcp->state);
  1885. trace_ubwcp_free_buffer_end(dmabuf);
  1886. return -EPERM;
  1887. }
  1888. mutex_lock(&buf->lock);
  1889. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1890. if (buf->lock_count) {
  1891. DBG("free before unlock (lock_count: %d). unlock()'ing first", buf->lock_count);
  1892. ret = unlock_internal(buf, buf->dma_dir, true);
  1893. if (ret)
  1894. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1895. }
  1896. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1897. if (buf->desc) {
  1898. if (!buf->perm) {
  1899. ubwcp->state = UBWCP_STATE_FAULT;
  1900. WARN_ON(true);
  1901. }
  1902. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1903. buf->desc = NULL;
  1904. }
  1905. if (buf->buf_attr_set)
  1906. reset_buf_attrs(buf);
  1907. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1908. hash_del(&buf->hnode);
  1909. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1910. mutex_unlock(&buf->lock);
  1911. kfree(buf);
  1912. if (is_non_lin_buf)
  1913. dec_num_non_lin_buffers(ubwcp);
  1914. trace_ubwcp_free_buffer_end(dmabuf);
  1915. return ret;
  1916. }
  1917. /* file open: TBD: increment ref count? */
  1918. static int ubwcp_open(struct inode *i, struct file *f)
  1919. {
  1920. return 0;
  1921. }
  1922. /* file open: TBD: decrement ref count? */
  1923. static int ubwcp_close(struct inode *i, struct file *f)
  1924. {
  1925. return 0;
  1926. }
  1927. /* handle IOCTLs */
  1928. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  1929. {
  1930. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  1931. struct ubwcp_ioctl_hw_version hw_ver;
  1932. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  1933. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  1934. enum ubwcp_std_image_format format;
  1935. struct ubwcp_driver *ubwcp;
  1936. ubwcp = ubwcp_get_driver();
  1937. if (!ubwcp)
  1938. return -EINVAL;
  1939. if (ubwcp->state != UBWCP_STATE_READY) {
  1940. ERR("driver in invalid state: %d", ubwcp->state);
  1941. return -EPERM;
  1942. }
  1943. switch (ioctl_num) {
  1944. case UBWCP_IOCTL_SET_BUF_ATTR:
  1945. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  1946. sizeof(buf_attr_ioctl))) {
  1947. ERR("ERROR: copy_from_user() failed");
  1948. return -EFAULT;
  1949. }
  1950. DBG("IOCTL : SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  1951. if (buf_attr_ioctl.attr.unused1 || buf_attr_ioctl.attr.unused2
  1952. || buf_attr_ioctl.attr.unused3 || buf_attr_ioctl.attr.unused4
  1953. || buf_attr_ioctl.attr.unused5 || buf_attr_ioctl.attr.unused6
  1954. || buf_attr_ioctl.attr.unused7 || buf_attr_ioctl.attr.unused8
  1955. || buf_attr_ioctl.attr.unused9) {
  1956. ERR("ERROR: buf attr unused values must be set to 0");
  1957. return -EINVAL;
  1958. }
  1959. return ubwcp_set_buf_attrs_ioctl(&buf_attr_ioctl);
  1960. case UBWCP_IOCTL_GET_HW_VER:
  1961. DBG("IOCTL : GET_HW_VER");
  1962. if (ubwcp_get_hw_version(&hw_ver))
  1963. return -EINVAL;
  1964. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  1965. ERR("ERROR: copy_to_user() failed");
  1966. return -EFAULT;
  1967. }
  1968. break;
  1969. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  1970. DBG("IOCTL : GET_STRIDE_ALIGN");
  1971. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  1972. sizeof(stride_align_ioctl))) {
  1973. ERR("ERROR: copy_from_user() failed");
  1974. return -EFAULT;
  1975. }
  1976. format = to_std_format(stride_align_ioctl.image_format);
  1977. if (format == STD_IMAGE_FORMAT_INVALID)
  1978. return -EINVAL;
  1979. if (stride_align_ioctl.unused != 0)
  1980. return -EINVAL;
  1981. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  1982. ERR("ERROR: copy_to_user() failed");
  1983. return -EFAULT;
  1984. }
  1985. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  1986. sizeof(stride_align_ioctl))) {
  1987. ERR("ERROR: copy_to_user() failed");
  1988. return -EFAULT;
  1989. }
  1990. break;
  1991. case UBWCP_IOCTL_VALIDATE_STRIDE:
  1992. DBG("IOCTL : VALIDATE_STRIDE");
  1993. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  1994. sizeof(validate_stride_ioctl))) {
  1995. ERR("ERROR: copy_from_user() failed");
  1996. return -EFAULT;
  1997. }
  1998. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  1999. ERR("ERROR: unused values must be set to 0");
  2000. return -EINVAL;
  2001. }
  2002. format = to_std_format(validate_stride_ioctl.image_format);
  2003. if (format == STD_IMAGE_FORMAT_INVALID) {
  2004. ERR("ERROR: invalid format: %d", validate_stride_ioctl.image_format);
  2005. return -EINVAL;
  2006. }
  2007. validate_stride_ioctl.valid = stride_is_valid(ubwcp,
  2008. validate_stride_ioctl.image_format,
  2009. validate_stride_ioctl.width,
  2010. validate_stride_ioctl.stride);
  2011. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2012. sizeof(validate_stride_ioctl))) {
  2013. ERR("ERROR: copy_to_user() failed");
  2014. return -EFAULT;
  2015. }
  2016. break;
  2017. default:
  2018. ERR("Invalid ioctl_num = %d", ioctl_num);
  2019. return -EINVAL;
  2020. }
  2021. return 0;
  2022. }
  2023. static const struct file_operations ubwcp_fops = {
  2024. .owner = THIS_MODULE,
  2025. .open = ubwcp_open,
  2026. .release = ubwcp_close,
  2027. .unlocked_ioctl = ubwcp_ioctl,
  2028. };
  2029. static int read_err_r_op(void *data, u64 *value)
  2030. {
  2031. struct ubwcp_driver *ubwcp = data;
  2032. *value = ubwcp->read_err_irq_en;
  2033. return 0;
  2034. }
  2035. static int read_err_w_op(void *data, u64 value)
  2036. {
  2037. struct ubwcp_driver *ubwcp = data;
  2038. if (ubwcp->state != UBWCP_STATE_READY)
  2039. return -EPERM;
  2040. if (ubwcp_power(ubwcp, true))
  2041. goto err;
  2042. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2043. ubwcp->read_err_irq_en = value;
  2044. if (ubwcp_power(ubwcp, false))
  2045. goto err;
  2046. return 0;
  2047. err:
  2048. ubwcp->state = UBWCP_STATE_FAULT;
  2049. return -1;
  2050. }
  2051. static int write_err_r_op(void *data, u64 *value)
  2052. {
  2053. struct ubwcp_driver *ubwcp = data;
  2054. if (ubwcp->state != UBWCP_STATE_READY)
  2055. return -EPERM;
  2056. *value = ubwcp->write_err_irq_en;
  2057. return 0;
  2058. }
  2059. static int write_err_w_op(void *data, u64 value)
  2060. {
  2061. struct ubwcp_driver *ubwcp = data;
  2062. if (ubwcp->state != UBWCP_STATE_READY)
  2063. return -EPERM;
  2064. if (ubwcp_power(ubwcp, true))
  2065. goto err;
  2066. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2067. ubwcp->write_err_irq_en = value;
  2068. if (ubwcp_power(ubwcp, false))
  2069. goto err;
  2070. return 0;
  2071. err:
  2072. ubwcp->state = UBWCP_STATE_FAULT;
  2073. return -1;
  2074. }
  2075. static int decode_err_r_op(void *data, u64 *value)
  2076. {
  2077. struct ubwcp_driver *ubwcp = data;
  2078. if (ubwcp->state != UBWCP_STATE_READY)
  2079. return -EPERM;
  2080. *value = ubwcp->decode_err_irq_en;
  2081. return 0;
  2082. }
  2083. static int decode_err_w_op(void *data, u64 value)
  2084. {
  2085. struct ubwcp_driver *ubwcp = data;
  2086. if (ubwcp->state != UBWCP_STATE_READY)
  2087. return -EPERM;
  2088. if (ubwcp_power(ubwcp, true))
  2089. goto err;
  2090. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2091. ubwcp->decode_err_irq_en = value;
  2092. if (ubwcp_power(ubwcp, false))
  2093. goto err;
  2094. return 0;
  2095. err:
  2096. ubwcp->state = UBWCP_STATE_FAULT;
  2097. return -1;
  2098. }
  2099. static int encode_err_r_op(void *data, u64 *value)
  2100. {
  2101. struct ubwcp_driver *ubwcp = data;
  2102. if (ubwcp->state != UBWCP_STATE_READY)
  2103. return -EPERM;
  2104. *value = ubwcp->encode_err_irq_en;
  2105. return 0;
  2106. }
  2107. static int encode_err_w_op(void *data, u64 value)
  2108. {
  2109. struct ubwcp_driver *ubwcp = data;
  2110. if (ubwcp->state != UBWCP_STATE_READY)
  2111. return -EPERM;
  2112. if (ubwcp_power(ubwcp, true))
  2113. goto err;
  2114. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2115. ubwcp->encode_err_irq_en = value;
  2116. if (ubwcp_power(ubwcp, false))
  2117. goto err;
  2118. return 0;
  2119. err:
  2120. ubwcp->state = UBWCP_STATE_FAULT;
  2121. return -1;
  2122. }
  2123. static int reg_rw_trace_w_op(void *data, u64 value)
  2124. {
  2125. struct ubwcp_driver *ubwcp = data;
  2126. if (ubwcp->state != UBWCP_STATE_READY)
  2127. return -EPERM;
  2128. ubwcp_hw_trace_set(value);
  2129. return 0;
  2130. }
  2131. static int reg_rw_trace_r_op(void *data, u64 *value)
  2132. {
  2133. struct ubwcp_driver *ubwcp = data;
  2134. bool trace_status;
  2135. if (ubwcp->state != UBWCP_STATE_READY)
  2136. return -EPERM;
  2137. ubwcp_hw_trace_get(&trace_status);
  2138. *value = trace_status;
  2139. return 0;
  2140. }
  2141. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2142. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2143. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2144. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2145. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2146. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2147. {
  2148. struct dentry *debugfs_root;
  2149. struct dentry *dfile;
  2150. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2151. if (IS_ERR_OR_NULL(debugfs_root)) {
  2152. ERR("Failed to create debugfs for ubwcp\n");
  2153. return;
  2154. }
  2155. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2156. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2157. if (IS_ERR_OR_NULL(dfile)) {
  2158. ERR("failed to create reg_rw_trace_en debugfs file");
  2159. goto err;
  2160. }
  2161. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2162. if (IS_ERR_OR_NULL(dfile)) {
  2163. ERR("failed to create read_err_irq debugfs file");
  2164. goto err;
  2165. }
  2166. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2167. if (IS_ERR_OR_NULL(dfile)) {
  2168. ERR("failed to create write_err_irq debugfs file");
  2169. goto err;
  2170. }
  2171. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2172. &decode_err_fops);
  2173. if (IS_ERR_OR_NULL(dfile)) {
  2174. ERR("failed to create decode_err_irq debugfs file");
  2175. goto err;
  2176. }
  2177. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2178. &encode_err_fops);
  2179. if (IS_ERR_OR_NULL(dfile)) {
  2180. ERR("failed to create encode_err_irq debugfs file");
  2181. goto err;
  2182. }
  2183. ubwcp->debugfs_root = debugfs_root;
  2184. return;
  2185. err:
  2186. debugfs_remove_recursive(ubwcp->debugfs_root);
  2187. ubwcp->debugfs_root = NULL;
  2188. }
  2189. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2190. {
  2191. debugfs_remove_recursive(ubwcp->debugfs_root);
  2192. }
  2193. /* ubwcp char device initialization */
  2194. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2195. {
  2196. int ret;
  2197. dev_t devt;
  2198. struct class *dev_class;
  2199. struct device *dev_sys;
  2200. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2201. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2202. if (ret) {
  2203. ERR("alloc_chrdev_region() failed: %d", ret);
  2204. return ret;
  2205. }
  2206. /* create device class (/sys/class/ubwcp_class) */
  2207. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2208. if (IS_ERR(dev_class)) {
  2209. ret = PTR_ERR(dev_class);
  2210. ERR("class_create() failed, ret: %d", ret);
  2211. goto err;
  2212. }
  2213. /* Create device and register with sysfs
  2214. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2215. */
  2216. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2217. UBWCP_DEVICE_NAME);
  2218. if (IS_ERR(dev_sys)) {
  2219. ret = PTR_ERR(dev_sys);
  2220. ERR("device_create() failed, ret: %d", ret);
  2221. goto err_device_create;
  2222. }
  2223. /* register file operations and get cdev */
  2224. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2225. /* associate cdev and device major/minor with file system
  2226. * can do file ops on /dev/ubwcp after this
  2227. */
  2228. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2229. if (ret) {
  2230. ERR("cdev_add() failed, ret: %d", ret);
  2231. goto err_cdev_add;
  2232. }
  2233. ubwcp->devt = devt;
  2234. ubwcp->dev_class = dev_class;
  2235. ubwcp->dev_sys = dev_sys;
  2236. return 0;
  2237. err_cdev_add:
  2238. device_destroy(dev_class, devt);
  2239. err_device_create:
  2240. class_destroy(dev_class);
  2241. err:
  2242. unregister_chrdev_region(devt, UBWCP_NUM_DEVICES);
  2243. return ret;
  2244. }
  2245. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2246. {
  2247. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2248. class_destroy(ubwcp->dev_class);
  2249. cdev_del(&ubwcp->cdev);
  2250. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2251. }
  2252. struct handler_node {
  2253. struct list_head list;
  2254. u32 client_id;
  2255. ubwcp_error_handler_t handler;
  2256. void *data;
  2257. };
  2258. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2259. void *data)
  2260. {
  2261. struct handler_node *node;
  2262. unsigned long flags;
  2263. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2264. if (!ubwcp)
  2265. return -EINVAL;
  2266. if (client_id != -1)
  2267. return -EINVAL;
  2268. if (!handler)
  2269. return -EINVAL;
  2270. if (ubwcp->state != UBWCP_STATE_READY)
  2271. return -EPERM;
  2272. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2273. if (!node)
  2274. return -ENOMEM;
  2275. node->client_id = client_id;
  2276. node->handler = handler;
  2277. node->data = data;
  2278. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2279. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2280. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2281. return 0;
  2282. }
  2283. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2284. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2285. {
  2286. struct handler_node *node;
  2287. unsigned long flags;
  2288. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2289. if (!ubwcp)
  2290. return;
  2291. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2292. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2293. node->handler(err, node->data);
  2294. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2295. }
  2296. int ubwcp_unregister_error_handler(u32 client_id)
  2297. {
  2298. int ret = -EINVAL;
  2299. struct handler_node *node;
  2300. unsigned long flags;
  2301. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2302. if (!ubwcp)
  2303. return -EINVAL;
  2304. if (ubwcp->state != UBWCP_STATE_INVALID)
  2305. return -EPERM;
  2306. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2307. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2308. if (node->client_id == client_id) {
  2309. list_del(&node->list);
  2310. kfree(node);
  2311. ret = 0;
  2312. break;
  2313. }
  2314. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2315. return ret;
  2316. }
  2317. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2318. /* get ubwcp_buf corresponding to the ULA PA*/
  2319. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2320. {
  2321. struct ubwcp_buf *buf = NULL;
  2322. struct dma_buf *ret_buf = NULL;
  2323. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2324. unsigned long flags;
  2325. u32 i;
  2326. if (!ubwcp)
  2327. return NULL;
  2328. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2329. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2330. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2331. ret_buf = buf->dma_buf;
  2332. break;
  2333. }
  2334. }
  2335. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2336. return ret_buf;
  2337. }
  2338. /* get ubwcp_buf corresponding to the IOVA*/
  2339. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2340. {
  2341. struct ubwcp_buf *buf = NULL;
  2342. struct dma_buf *ret_buf = NULL;
  2343. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2344. unsigned long flags;
  2345. u32 i;
  2346. if (!ubwcp)
  2347. return NULL;
  2348. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2349. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2350. unsigned long iova_base;
  2351. unsigned int iova_size;
  2352. if (!buf->sgt)
  2353. continue;
  2354. iova_base = sg_dma_address(buf->sgt->sgl);
  2355. iova_size = sg_dma_len(buf->sgt->sgl);
  2356. if (iova_base <= addr && addr < iova_base + iova_size) {
  2357. ret_buf = buf->dma_buf;
  2358. break;
  2359. }
  2360. }
  2361. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2362. return ret_buf;
  2363. }
  2364. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2365. unsigned long iova, int flags, void *data)
  2366. {
  2367. int ret = 0;
  2368. struct ubwcp_err_info err;
  2369. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2370. struct device *cb_dev = (struct device *)data;
  2371. if (!ubwcp) {
  2372. ret = -EINVAL;
  2373. goto err;
  2374. }
  2375. err.err_code = UBWCP_SMMU_FAULT;
  2376. if (cb_dev == ubwcp->dev_desc_cb)
  2377. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2378. else if (cb_dev == ubwcp->dev_buf_cb)
  2379. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2380. else
  2381. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2382. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2383. err.smmu_err.iova = iova;
  2384. err.smmu_err.iommu_fault_flags = flags;
  2385. ERR_RATE_LIMIT("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2386. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2387. err.smmu_err.iommu_fault_flags);
  2388. ubwcp_notify_error_handlers(&err);
  2389. err:
  2390. return ret;
  2391. }
  2392. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2393. {
  2394. struct ubwcp_driver *ubwcp;
  2395. void __iomem *base;
  2396. phys_addr_t addr;
  2397. struct ubwcp_err_info err;
  2398. ubwcp = (struct ubwcp_driver *) ptr;
  2399. base = ubwcp->base;
  2400. if (irq == ubwcp->irq_range_ck_rd) {
  2401. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2402. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2403. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2404. err.translation_err.ula_pa = addr;
  2405. err.translation_err.read = true;
  2406. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2407. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2408. ubwcp_notify_error_handlers(&err);
  2409. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2410. } else if (irq == ubwcp->irq_range_ck_wr) {
  2411. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2412. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2413. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2414. err.translation_err.ula_pa = addr;
  2415. err.translation_err.read = false;
  2416. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2417. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2418. ubwcp_notify_error_handlers(&err);
  2419. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2420. } else if (irq == ubwcp->irq_encode) {
  2421. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2422. err.err_code = UBWCP_ENCODE_ERROR;
  2423. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2424. err.enc_err.ula_pa = addr;
  2425. ERR_RATE_LIMIT("ubwcp_err: err code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2426. err.err_code, err.enc_err.dmabuf, addr);
  2427. ubwcp_notify_error_handlers(&err);
  2428. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2429. } else if (irq == ubwcp->irq_decode) {
  2430. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2431. err.err_code = UBWCP_DECODE_ERROR;
  2432. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2433. err.dec_err.ula_pa = addr;
  2434. ERR_RATE_LIMIT("ubwcp_err: err code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2435. err.err_code, err.enc_err.dmabuf, addr);
  2436. ubwcp_notify_error_handlers(&err);
  2437. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2438. } else {
  2439. ERR("unknown irq: %d", irq);
  2440. return IRQ_NONE;
  2441. }
  2442. return IRQ_HANDLED;
  2443. }
  2444. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2445. {
  2446. int ret = 0;
  2447. struct device *dev = &pdev->dev;
  2448. FENTRY();
  2449. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2450. if (ubwcp->irq_range_ck_rd < 0)
  2451. return ubwcp->irq_range_ck_rd;
  2452. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2453. if (ubwcp->irq_range_ck_wr < 0)
  2454. return ubwcp->irq_range_ck_wr;
  2455. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2456. if (ubwcp->irq_encode < 0)
  2457. return ubwcp->irq_encode;
  2458. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2459. if (ubwcp->irq_decode < 0)
  2460. return ubwcp->irq_decode;
  2461. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2462. ubwcp->irq_range_ck_wr,
  2463. ubwcp->irq_encode,
  2464. ubwcp->irq_decode);
  2465. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2466. if (ret) {
  2467. ERR("request_irq() failed. irq: %d ret: %d",
  2468. ubwcp->irq_range_ck_rd, ret);
  2469. return ret;
  2470. }
  2471. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2472. if (ret) {
  2473. ERR("request_irq() failed. irq: %d ret: %d",
  2474. ubwcp->irq_range_ck_wr, ret);
  2475. return ret;
  2476. }
  2477. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2478. if (ret) {
  2479. ERR("request_irq() failed. irq: %d ret: %d",
  2480. ubwcp->irq_encode, ret);
  2481. return ret;
  2482. }
  2483. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2484. if (ret) {
  2485. ERR("request_irq() failed. irq: %d ret: %d",
  2486. ubwcp->irq_decode, ret);
  2487. return ret;
  2488. }
  2489. return ret;
  2490. }
  2491. /* ubwcp device probe */
  2492. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2493. {
  2494. int ret = 0;
  2495. struct ubwcp_driver *ubwcp;
  2496. struct device *ubwcp_dev = &pdev->dev;
  2497. FENTRY();
  2498. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2499. if (!ubwcp) {
  2500. ERR("devm_kzalloc() failed");
  2501. return -ENOMEM;
  2502. }
  2503. ubwcp->dev = &pdev->dev;
  2504. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2505. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2506. if (IS_ERR(ubwcp->base)) {
  2507. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2508. return PTR_ERR(ubwcp->base);
  2509. }
  2510. DBG("ubwcp->base: %p", ubwcp->base);
  2511. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2512. if (ret) {
  2513. ERR("failed reading ula_range (base): %d", ret);
  2514. return ret;
  2515. }
  2516. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2517. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2518. if (ret) {
  2519. ERR("failed reading ula_range (size): %d", ret);
  2520. return ret;
  2521. }
  2522. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2523. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2524. /* driver initial state */
  2525. ubwcp->state = UBWCP_STATE_INVALID;
  2526. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2527. ubwcp->mem_online = false;
  2528. mutex_init(&ubwcp->desc_lock);
  2529. spin_lock_init(&ubwcp->buf_table_lock);
  2530. mutex_init(&ubwcp->mem_hotplug_lock);
  2531. mutex_init(&ubwcp->ula_lock);
  2532. mutex_init(&ubwcp->ubwcp_flush_lock);
  2533. mutex_init(&ubwcp->hw_range_ck_lock);
  2534. spin_lock_init(&ubwcp->err_handler_list_lock);
  2535. /* Regulator */
  2536. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2537. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2538. ret = PTR_ERR(ubwcp->vdd);
  2539. ERR("devm_regulator_get() failed: %d", ret);
  2540. return ret;
  2541. }
  2542. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2543. if (ret) {
  2544. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2545. return ret;
  2546. }
  2547. if (ubwcp_power(ubwcp, true))
  2548. return -1;
  2549. if (ubwcp_cdev_init(ubwcp))
  2550. return -1;
  2551. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2552. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2553. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2554. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2555. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2556. if (ubwcp_interrupt_register(pdev, ubwcp))
  2557. return -1;
  2558. ubwcp_debugfs_init(ubwcp);
  2559. /* create ULA pool */
  2560. ubwcp->ula_pool = gen_pool_create(PAGE_SHIFT, -1);
  2561. if (!ubwcp->ula_pool) {
  2562. ERR("failed gen_pool_create()");
  2563. ret = -1;
  2564. goto err_pool_create;
  2565. }
  2566. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2567. if (ret) {
  2568. ERR("failed gen_pool_add(): %d", ret);
  2569. ret = -1;
  2570. goto err_pool_add;
  2571. }
  2572. /* register the default config mmap function. */
  2573. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2574. hash_init(ubwcp->buf_table);
  2575. ubwcp_buf_desc_list_init(ubwcp);
  2576. image_format_init(ubwcp);
  2577. /* one time hw init */
  2578. ubwcp_hw_one_time_init(ubwcp->base);
  2579. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2580. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2581. if (ubwcp->hw_ver_major == 0) {
  2582. ERR("Failed to read HW version");
  2583. ret = -1;
  2584. goto err_pool_add;
  2585. }
  2586. /* set pdev->dev->driver_data = ubwcp */
  2587. platform_set_drvdata(pdev, ubwcp);
  2588. /* enable interrupts */
  2589. if (ubwcp->read_err_irq_en)
  2590. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2591. if (ubwcp->write_err_irq_en)
  2592. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2593. if (ubwcp->decode_err_irq_en)
  2594. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2595. if (ubwcp->encode_err_irq_en)
  2596. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2597. /* Turn OFF until buffers are allocated */
  2598. if (ubwcp_power(ubwcp, false)) {
  2599. ret = -1;
  2600. goto err_power_off;
  2601. }
  2602. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2603. if (ret) {
  2604. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2605. goto err_power_off;
  2606. } else {
  2607. DBG("msm_ubwcp_set_ops(): success"); }
  2608. me = ubwcp;
  2609. return ret;
  2610. err_power_off:
  2611. if (!ubwcp_power(ubwcp, true)) {
  2612. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2613. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2614. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2615. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2616. ubwcp_power(ubwcp, false);
  2617. }
  2618. err_pool_add:
  2619. gen_pool_destroy(ubwcp->ula_pool);
  2620. err_pool_create:
  2621. ubwcp_debugfs_deinit(ubwcp);
  2622. ubwcp_cdev_deinit(ubwcp);
  2623. return ret;
  2624. }
  2625. /* buffer context bank device probe */
  2626. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2627. {
  2628. struct ubwcp_driver *ubwcp;
  2629. struct iommu_domain *domain = NULL;
  2630. FENTRY();
  2631. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2632. if (!ubwcp) {
  2633. ERR("failed to get ubwcp ptr");
  2634. return -EINVAL;
  2635. }
  2636. ubwcp->dev_buf_cb = &pdev->dev;
  2637. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2638. if (domain)
  2639. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2640. if (ubwcp->dev_desc_cb)
  2641. ubwcp->state = UBWCP_STATE_READY;
  2642. return 0;
  2643. }
  2644. /* descriptor context bank device probe */
  2645. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2646. {
  2647. int ret = 0;
  2648. struct ubwcp_driver *ubwcp;
  2649. struct iommu_domain *domain = NULL;
  2650. FENTRY();
  2651. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2652. if (!ubwcp) {
  2653. ERR("failed to get ubwcp ptr");
  2654. return -EINVAL;
  2655. }
  2656. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2657. UBWCP_BUFFER_DESC_COUNT;
  2658. ubwcp->dev_desc_cb = &pdev->dev;
  2659. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2660. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2661. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2662. * Thus we don't need to flush after updates to buffer descriptors.
  2663. */
  2664. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2665. ubwcp->buffer_desc_size,
  2666. &ubwcp->buffer_desc_dma_handle,
  2667. GFP_KERNEL);
  2668. if (!ubwcp->buffer_desc_base) {
  2669. ERR("failed to allocate desc buffer");
  2670. return -ENOMEM;
  2671. }
  2672. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2673. ubwcp->buffer_desc_size);
  2674. ret = ubwcp_power(ubwcp, true);
  2675. if (ret) {
  2676. ERR("failed to power on");
  2677. goto err;
  2678. }
  2679. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2680. UBWCP_BUFFER_DESC_OFFSET);
  2681. ret = ubwcp_power(ubwcp, false);
  2682. if (ret) {
  2683. ERR("failed to power off");
  2684. goto err;
  2685. }
  2686. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2687. if (domain)
  2688. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2689. if (ubwcp->dev_buf_cb)
  2690. ubwcp->state = UBWCP_STATE_READY;
  2691. return ret;
  2692. err:
  2693. dma_free_coherent(ubwcp->dev_desc_cb,
  2694. ubwcp->buffer_desc_size,
  2695. ubwcp->buffer_desc_base,
  2696. ubwcp->buffer_desc_dma_handle);
  2697. ubwcp->buffer_desc_base = NULL;
  2698. ubwcp->buffer_desc_dma_handle = 0;
  2699. ubwcp->dev_desc_cb = NULL;
  2700. return -1;
  2701. }
  2702. /* buffer context bank device remove */
  2703. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2704. {
  2705. struct ubwcp_driver *ubwcp;
  2706. FENTRY();
  2707. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2708. if (!ubwcp) {
  2709. ERR("failed to get ubwcp ptr");
  2710. return -EINVAL;
  2711. }
  2712. ubwcp->state = UBWCP_STATE_INVALID;
  2713. ubwcp->dev_buf_cb = NULL;
  2714. return 0;
  2715. }
  2716. /* descriptor context bank device remove */
  2717. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2718. {
  2719. struct ubwcp_driver *ubwcp;
  2720. FENTRY();
  2721. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2722. if (!ubwcp) {
  2723. ERR("failed to get ubwcp ptr");
  2724. return -EINVAL;
  2725. }
  2726. if (!ubwcp->dev_desc_cb) {
  2727. ERR("ubwcp->dev_desc_cb == NULL");
  2728. return -1;
  2729. }
  2730. if (!ubwcp_power(ubwcp, true)) {
  2731. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2732. ubwcp_power(ubwcp, false);
  2733. }
  2734. ubwcp->state = UBWCP_STATE_INVALID;
  2735. dma_free_coherent(ubwcp->dev_desc_cb,
  2736. ubwcp->buffer_desc_size,
  2737. ubwcp->buffer_desc_base,
  2738. ubwcp->buffer_desc_dma_handle);
  2739. ubwcp->buffer_desc_base = NULL;
  2740. ubwcp->buffer_desc_dma_handle = 0;
  2741. return 0;
  2742. }
  2743. /* ubwcp device remove */
  2744. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2745. {
  2746. size_t avail;
  2747. size_t psize;
  2748. struct ubwcp_driver *ubwcp;
  2749. FENTRY();
  2750. /* get pdev->dev->driver_data = ubwcp */
  2751. ubwcp = platform_get_drvdata(pdev);
  2752. if (!ubwcp) {
  2753. ERR("ubwcp == NULL");
  2754. return -1;
  2755. }
  2756. if (!ubwcp_power(ubwcp, true)) {
  2757. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2758. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2759. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2760. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2761. ubwcp_power(ubwcp, false);
  2762. }
  2763. ubwcp->state = UBWCP_STATE_INVALID;
  2764. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics. */
  2765. avail = gen_pool_avail(ubwcp->ula_pool);
  2766. psize = gen_pool_size(ubwcp->ula_pool);
  2767. if (psize != avail) {
  2768. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2769. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2770. WARN(1, "Fix this!");
  2771. } else {
  2772. gen_pool_destroy(ubwcp->ula_pool);
  2773. }
  2774. ubwcp_debugfs_deinit(ubwcp);
  2775. ubwcp_cdev_deinit(ubwcp);
  2776. return 0;
  2777. }
  2778. /* top level ubwcp device probe function */
  2779. static int ubwcp_probe(struct platform_device *pdev)
  2780. {
  2781. const char *compatible = "";
  2782. FENTRY();
  2783. trace_ubwcp_probe(pdev);
  2784. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2785. return qcom_ubwcp_probe(pdev);
  2786. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2787. return ubwcp_probe_cb_desc(pdev);
  2788. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2789. return ubwcp_probe_cb_buf(pdev);
  2790. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2791. ERR("unknown device: %s", compatible);
  2792. WARN_ON(1);
  2793. return -EINVAL;
  2794. }
  2795. /* top level ubwcp device remove function */
  2796. static int ubwcp_remove(struct platform_device *pdev)
  2797. {
  2798. const char *compatible = "";
  2799. FENTRY();
  2800. trace_ubwcp_remove(pdev);
  2801. /* TBD: what if buffers are still allocated? locked? etc.
  2802. * also should turn off power?
  2803. */
  2804. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2805. return qcom_ubwcp_remove(pdev);
  2806. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2807. return ubwcp_remove_cb_desc(pdev);
  2808. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2809. return ubwcp_remove_cb_buf(pdev);
  2810. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2811. ERR("unknown device: %s", compatible);
  2812. WARN_ON(1);
  2813. return -EINVAL;
  2814. }
  2815. static const struct of_device_id ubwcp_dt_match[] = {
  2816. {.compatible = "qcom,ubwcp"},
  2817. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2818. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2819. {}
  2820. };
  2821. struct platform_driver ubwcp_platform_driver = {
  2822. .probe = ubwcp_probe,
  2823. .remove = ubwcp_remove,
  2824. .driver = {
  2825. .name = "qcom,ubwcp",
  2826. .of_match_table = ubwcp_dt_match,
  2827. },
  2828. };
  2829. int ubwcp_init(void)
  2830. {
  2831. int ret = 0;
  2832. DBG("+++++++++++");
  2833. ret = platform_driver_register(&ubwcp_platform_driver);
  2834. if (ret)
  2835. ERR("platform_driver_register() failed: %d", ret);
  2836. return ret;
  2837. }
  2838. void ubwcp_exit(void)
  2839. {
  2840. platform_driver_unregister(&ubwcp_platform_driver);
  2841. DBG("-----------");
  2842. }
  2843. module_init(ubwcp_init);
  2844. module_exit(ubwcp_exit);
  2845. MODULE_LICENSE("GPL");