dp_power.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/pm_runtime.h>
  8. #include "dp_power.h"
  9. #include "dp_catalog.h"
  10. #include "dp_debug.h"
  11. #include "dp_pll.h"
  12. #if defined(CONFIG_SECDP)
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/delay.h>
  15. #include "secdp.h"
  16. #if IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)// && IS_ENABLED(CONFIG_IF_CB_MANAGER)
  17. #include <linux/usb/typec/manager/if_cb_manager.h>
  18. #endif
  19. #if IS_ENABLED(CONFIG_COMBO_REDRIVER_PTN36502)
  20. #include <linux/combo_redriver/ptn36502.h>
  21. #elif IS_ENABLED(CONFIG_COMBO_REDRIVER_PS5169)
  22. #include <linux/combo_redriver/ps5169.h>
  23. #endif
  24. #define DP_LINK_BW_RBR 0x06
  25. #define DP_LINK_BW_HBR 0x0a
  26. #define DP_LINK_BW_HBR2 0x14 /* 1.2 */
  27. #define DP_LINK_BW_HBR3 0x1e /* 1.4 */
  28. #endif/*CONFIG_SECDP*/
  29. #define DP_CLIENT_NAME_SIZE 20
  30. #define XO_CLK_KHZ 19200
  31. struct dp_power_private {
  32. struct dp_parser *parser;
  33. struct dp_pll *pll;
  34. struct platform_device *pdev;
  35. struct clk *pixel_clk_rcg;
  36. struct clk *pixel_parent;
  37. struct clk *pixel1_clk_rcg;
  38. struct clk *xo_clk;
  39. struct clk *link_clk_rcg;
  40. struct clk *link_parent;
  41. struct dp_power dp_power;
  42. bool core_clks_on;
  43. bool link_clks_on;
  44. bool strm0_clks_on;
  45. bool strm1_clks_on;
  46. bool strm0_clks_parked;
  47. bool strm1_clks_parked;
  48. bool link_clks_parked;
  49. #if defined(CONFIG_SECDP)
  50. bool aux_pullup_on;
  51. struct mutex dp_clk_lock;
  52. #if IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)
  53. enum sbu_switch_status sbu_status;
  54. #endif
  55. void (*redrv_onoff)(struct dp_power_private *power,
  56. bool enable, int lane);
  57. void (*redrv_aux_ctrl)(struct dp_power_private *power, int cross);
  58. void (*redrv_notify_linkinfo)(struct dp_power_private *power,
  59. u32 bw_code, u8 v_level, u8 p_level);
  60. #endif
  61. };
  62. #if defined(CONFIG_SECDP)
  63. #define DP_ENUM_STR(x) #x
  64. enum redriver_switch_t {
  65. REDRIVER_SWITCH_UNKNOWN = -1,
  66. REDRIVER_SWITCH_RESET = 0,
  67. REDRIVER_SWITCH_CROSS,
  68. REDRIVER_SWITCH_THROU,
  69. };
  70. #endif
  71. static int dp_power_regulator_init(struct dp_power_private *power)
  72. {
  73. int rc = 0, i = 0, j = 0;
  74. struct platform_device *pdev;
  75. struct dp_parser *parser;
  76. parser = power->parser;
  77. pdev = power->pdev;
  78. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  79. rc = msm_dss_get_vreg(&pdev->dev,
  80. parser->mp[i].vreg_config,
  81. parser->mp[i].num_vreg, 1);
  82. if (rc) {
  83. DP_ERR("failed to init vregs for %s\n",
  84. dp_parser_pm_name(i));
  85. for (j = i - 1; j >= DP_CORE_PM; j--) {
  86. msm_dss_get_vreg(&pdev->dev,
  87. parser->mp[j].vreg_config,
  88. parser->mp[j].num_vreg, 0);
  89. }
  90. goto error;
  91. }
  92. }
  93. error:
  94. return rc;
  95. }
  96. static void dp_power_regulator_deinit(struct dp_power_private *power)
  97. {
  98. int rc = 0, i = 0;
  99. struct platform_device *pdev;
  100. struct dp_parser *parser;
  101. parser = power->parser;
  102. pdev = power->pdev;
  103. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  104. rc = msm_dss_get_vreg(&pdev->dev,
  105. parser->mp[i].vreg_config,
  106. parser->mp[i].num_vreg, 0);
  107. if (rc)
  108. DP_ERR("failed to deinit vregs for %s\n",
  109. dp_parser_pm_name(i));
  110. }
  111. }
  112. #if defined(CONFIG_SECDP)
  113. /* factory use only
  114. * ref: qusb_phy_enable_power()
  115. */
  116. static int secdp_aux_pullup_vreg_enable(struct dp_power_private *power, bool on)
  117. {
  118. struct regulator *aux_pu_vreg;
  119. int rc = 0;
  120. if (!power || !power->parser) {
  121. DP_ERR("error! power is null\n");
  122. goto exit;
  123. }
  124. aux_pu_vreg = power->parser->aux_pullup_vreg;
  125. if (!aux_pu_vreg) {
  126. DP_ERR("error! vdda33 is null\n");
  127. goto exit;
  128. }
  129. DP_ENTER("on:%d\n", on);
  130. #define QUSB2PHY_3P3_VOL_MIN 3104000 /* uV */
  131. #define QUSB2PHY_3P3_VOL_MAX 3105000 /* uV */
  132. #define QUSB2PHY_3P3_HPM_LOAD 30000 /* uA */
  133. if (on) {
  134. if (power->aux_pullup_on) {
  135. DP_INFO("already on\n");
  136. goto exit;
  137. }
  138. rc = regulator_set_load(aux_pu_vreg, QUSB2PHY_3P3_HPM_LOAD);
  139. if (rc < 0) {
  140. DP_ERR("Unable to set HPM of vdda33:%d\n", rc);
  141. goto exit;
  142. }
  143. rc = regulator_set_voltage(aux_pu_vreg, QUSB2PHY_3P3_VOL_MIN,
  144. QUSB2PHY_3P3_VOL_MAX);
  145. if (rc) {
  146. DP_ERR("Unable to set voltage for vdda33:%d\n", rc);
  147. goto put_vdda33_lpm;
  148. }
  149. rc = regulator_enable(aux_pu_vreg);
  150. if (rc) {
  151. DP_ERR("Unable to enable vdda33:%d\n", rc);
  152. goto unset_vdd33;
  153. }
  154. DP_INFO("[AUX_PU] on success\n");
  155. power->aux_pullup_on = true;
  156. } else {
  157. rc = regulator_disable(aux_pu_vreg);
  158. if (rc)
  159. DP_ERR("Unable to disable vdda33:%d\n", rc);
  160. unset_vdd33:
  161. rc = regulator_set_voltage(aux_pu_vreg, 0,
  162. QUSB2PHY_3P3_VOL_MAX);
  163. if (rc)
  164. DP_ERR("Unable to set 0 voltage for vdda33:%d\n", rc);
  165. put_vdda33_lpm:
  166. rc = regulator_set_load(aux_pu_vreg, 0);
  167. if (!rc)
  168. DP_INFO("[AUX_PU] off success\n");
  169. else
  170. DP_ERR("Unable to set 0 HPM of vdda33:%d\n", rc);
  171. power->aux_pullup_on = false;
  172. }
  173. exit:
  174. return rc;
  175. }
  176. #endif
  177. static void dp_power_phy_gdsc(struct dp_power *dp_power, bool on)
  178. {
  179. int rc = 0;
  180. if (IS_ERR_OR_NULL(dp_power->dp_phy_gdsc))
  181. return;
  182. if (on)
  183. rc = regulator_enable(dp_power->dp_phy_gdsc);
  184. else
  185. rc = regulator_disable(dp_power->dp_phy_gdsc);
  186. if (rc)
  187. DP_ERR("Fail to %s dp_phy_gdsc regulator ret =%d\n",
  188. on ? "enable" : "disable", rc);
  189. }
  190. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  191. {
  192. int rc = 0, i = 0, j = 0;
  193. struct dp_parser *parser;
  194. parser = power->parser;
  195. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  196. /*
  197. * The DP_PLL_PM regulator is controlled by dp_display based
  198. * on the link configuration.
  199. */
  200. if (i == DP_PLL_PM) {
  201. /* DP GDSC vote is needed for new chipsets, define gdsc phandle if needed */
  202. dp_power_phy_gdsc(&power->dp_power, enable);
  203. DP_DEBUG("skipping: '%s' vregs for %s\n",
  204. enable ? "enable" : "disable",
  205. dp_parser_pm_name(i));
  206. continue;
  207. }
  208. rc = msm_dss_enable_vreg(
  209. parser->mp[i].vreg_config,
  210. parser->mp[i].num_vreg, enable);
  211. if (rc) {
  212. DP_ERR("failed to '%s' vregs for %s\n",
  213. enable ? "enable" : "disable",
  214. dp_parser_pm_name(i));
  215. if (enable) {
  216. for (j = i-1; j >= DP_CORE_PM; j--) {
  217. msm_dss_enable_vreg(
  218. parser->mp[j].vreg_config,
  219. parser->mp[j].num_vreg, 0);
  220. }
  221. }
  222. goto error;
  223. }
  224. }
  225. #if defined(CONFIG_SECDP)
  226. secdp_aux_pullup_vreg_enable(power, enable);
  227. #endif
  228. error:
  229. return rc;
  230. }
  231. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  232. {
  233. int rc = -EFAULT;
  234. struct pinctrl_state *pin_state;
  235. struct dp_parser *parser;
  236. #if IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)
  237. return 0;
  238. #endif
  239. parser = power->parser;
  240. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  241. return 0;
  242. pin_state = active ? parser->pinctrl.state_active
  243. : parser->pinctrl.state_suspend;
  244. if (!IS_ERR_OR_NULL(pin_state)) {
  245. rc = pinctrl_select_state(parser->pinctrl.pin,
  246. pin_state);
  247. if (rc)
  248. DP_ERR("can not set %s pins\n",
  249. active ? "dp_active"
  250. : "dp_sleep");
  251. } else {
  252. DP_ERR("invalid '%s' pinstate\n",
  253. active ? "dp_active"
  254. : "dp_sleep");
  255. }
  256. return rc;
  257. }
  258. static void dp_power_clk_put(struct dp_power_private *power)
  259. {
  260. enum dp_pm_type module;
  261. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  262. struct dss_module_power *pm = &power->parser->mp[module];
  263. if (!pm->num_clk)
  264. continue;
  265. msm_dss_mmrm_deregister(&power->pdev->dev, pm);
  266. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  267. }
  268. }
  269. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  270. {
  271. int rc = 0;
  272. struct device *dev;
  273. enum dp_pm_type module;
  274. dev = &power->pdev->dev;
  275. if (enable) {
  276. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  277. struct dss_module_power *pm =
  278. &power->parser->mp[module];
  279. if (!pm->num_clk)
  280. continue;
  281. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  282. if (rc) {
  283. DP_ERR("failed to get %s clk. err=%d\n",
  284. dp_parser_pm_name(module), rc);
  285. goto exit;
  286. }
  287. }
  288. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  289. if (IS_ERR(power->pixel_clk_rcg)) {
  290. DP_ERR("Unable to get DP pixel clk RCG: %ld\n",
  291. PTR_ERR(power->pixel_clk_rcg));
  292. rc = PTR_ERR(power->pixel_clk_rcg);
  293. power->pixel_clk_rcg = NULL;
  294. goto err_pixel_clk_rcg;
  295. }
  296. power->pixel_parent = clk_get(dev, "pixel_parent");
  297. if (IS_ERR(power->pixel_parent)) {
  298. DP_ERR("Unable to get DP pixel RCG parent: %d\n",
  299. PTR_ERR(power->pixel_parent));
  300. rc = PTR_ERR(power->pixel_parent);
  301. power->pixel_parent = NULL;
  302. goto err_pixel_parent;
  303. }
  304. power->xo_clk = clk_get(dev, "rpmh_cxo_clk");
  305. if (IS_ERR(power->xo_clk)) {
  306. DP_ERR("Unable to get XO clk: %d\n", PTR_ERR(power->xo_clk));
  307. rc = PTR_ERR(power->xo_clk);
  308. power->xo_clk = NULL;
  309. goto err_xo_clk;
  310. }
  311. if (power->parser->has_mst) {
  312. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  313. if (IS_ERR(power->pixel1_clk_rcg)) {
  314. DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",
  315. PTR_ERR(power->pixel1_clk_rcg));
  316. rc = PTR_ERR(power->pixel1_clk_rcg);
  317. power->pixel1_clk_rcg = NULL;
  318. goto err_pixel1_clk_rcg;
  319. }
  320. }
  321. power->link_clk_rcg = clk_get(dev, "link_clk_src");
  322. if (IS_ERR(power->link_clk_rcg)) {
  323. DP_ERR("Unable to get DP link clk RCG: %ld\n",
  324. PTR_ERR(power->link_clk_rcg));
  325. rc = PTR_ERR(power->link_clk_rcg);
  326. power->link_clk_rcg = NULL;
  327. goto err_link_clk_rcg;
  328. }
  329. /* If link_parent node is available, convert clk rates to HZ for byte2 ops */
  330. power->pll->clk_factor = 1000;
  331. power->link_parent = clk_get(dev, "link_parent");
  332. if (IS_ERR(power->link_parent)) {
  333. DP_WARN("Unable to get DP link parent: %ld\n",
  334. PTR_ERR(power->link_parent));
  335. power->link_parent = NULL;
  336. power->pll->clk_factor = 1;
  337. }
  338. } else {
  339. if (power->pixel1_clk_rcg)
  340. clk_put(power->pixel1_clk_rcg);
  341. if (power->pixel_parent)
  342. clk_put(power->pixel_parent);
  343. if (power->pixel_clk_rcg)
  344. clk_put(power->pixel_clk_rcg);
  345. if (power->link_parent)
  346. clk_put(power->link_parent);
  347. if (power->link_clk_rcg)
  348. clk_put(power->link_clk_rcg);
  349. dp_power_clk_put(power);
  350. }
  351. return rc;
  352. err_link_clk_rcg:
  353. if (power->pixel1_clk_rcg)
  354. clk_put(power->pixel1_clk_rcg);
  355. err_pixel1_clk_rcg:
  356. clk_put(power->xo_clk);
  357. err_xo_clk:
  358. clk_put(power->pixel_parent);
  359. err_pixel_parent:
  360. clk_put(power->pixel_clk_rcg);
  361. err_pixel_clk_rcg:
  362. dp_power_clk_put(power);
  363. exit:
  364. return rc;
  365. }
  366. static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type module)
  367. {
  368. struct dss_module_power *mp;
  369. struct clk *clk = NULL;
  370. int rc = 0;
  371. bool *parked;
  372. mp = &power->parser->mp[module];
  373. if (module == DP_STREAM0_PM) {
  374. clk = power->pixel_clk_rcg;
  375. parked = &power->strm0_clks_parked;
  376. } else if (module == DP_STREAM1_PM) {
  377. clk = power->pixel1_clk_rcg;
  378. parked = &power->strm1_clks_parked;
  379. } else if (module == DP_LINK_PM) {
  380. clk = power->link_clk_rcg;
  381. parked = &power->link_clks_parked;
  382. } else {
  383. goto exit;
  384. }
  385. if (!clk) {
  386. DP_WARN("clk type %d not supported\n", module);
  387. rc = -EINVAL;
  388. goto exit;
  389. }
  390. if (!power->xo_clk) {
  391. rc = -EINVAL;
  392. goto exit;
  393. }
  394. if (*parked)
  395. goto exit;
  396. rc = clk_set_parent(clk, power->xo_clk);
  397. if (rc) {
  398. DP_ERR("unable to set xo parent on clk %d\n", module);
  399. goto exit;
  400. }
  401. mp->clk_config->rate = XO_CLK_KHZ * 1000;
  402. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  403. if (rc) {
  404. DP_ERR("failed to set clk rate.\n");
  405. goto exit;
  406. }
  407. *parked = true;
  408. exit:
  409. return rc;
  410. }
  411. static int dp_power_clk_set_rate(struct dp_power_private *power,
  412. enum dp_pm_type module, bool enable)
  413. {
  414. int rc = 0;
  415. struct dss_module_power *mp;
  416. #if defined(CONFIG_SECDP)
  417. static bool prev[DP_MAX_PM];
  418. mutex_lock(&power->dp_clk_lock);
  419. #endif
  420. if (!power) {
  421. DP_ERR("invalid power data\n");
  422. rc = -EINVAL;
  423. goto exit;
  424. }
  425. mp = &power->parser->mp[module];
  426. #if defined(CONFIG_SECDP)
  427. if (prev[module] == enable) {
  428. DP_DEBUG("%d clk already %s\n", module, enable ? "enabled" : "disabled");
  429. goto exit;
  430. }
  431. #endif
  432. if (enable) {
  433. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  434. if (rc) {
  435. DP_ERR("failed to set clks rate.\n");
  436. goto exit;
  437. }
  438. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  439. if (rc) {
  440. DP_ERR("failed to enable clks\n");
  441. goto exit;
  442. }
  443. } else {
  444. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  445. if (rc) {
  446. DP_ERR("failed to disable clks\n");
  447. goto exit;
  448. }
  449. dp_power_park_module(power, module);
  450. }
  451. #if defined(CONFIG_SECDP)
  452. prev[module] = enable;
  453. #endif
  454. exit:
  455. #if defined(CONFIG_SECDP)
  456. mutex_unlock(&power->dp_clk_lock);
  457. #endif
  458. return rc;
  459. }
  460. static bool dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
  461. {
  462. struct dp_power_private *power;
  463. if (!dp_power) {
  464. DP_ERR("invalid power data\n");
  465. return false;
  466. }
  467. power = container_of(dp_power, struct dp_power_private, dp_power);
  468. if (pm_type == DP_LINK_PM)
  469. return power->link_clks_on;
  470. else if (pm_type == DP_CORE_PM)
  471. return power->core_clks_on;
  472. else if (pm_type == DP_STREAM0_PM)
  473. return power->strm0_clks_on;
  474. else if (pm_type == DP_STREAM1_PM)
  475. return power->strm1_clks_on;
  476. else
  477. return false;
  478. }
  479. static int dp_power_clk_enable(struct dp_power *dp_power,
  480. enum dp_pm_type pm_type, bool enable)
  481. {
  482. int rc = 0;
  483. struct dss_module_power *mp;
  484. struct dp_power_private *power;
  485. if (!dp_power) {
  486. DP_ERR("invalid power data\n");
  487. rc = -EINVAL;
  488. goto error;
  489. }
  490. power = container_of(dp_power, struct dp_power_private, dp_power);
  491. mp = &power->parser->mp[pm_type];
  492. if (pm_type >= DP_MAX_PM) {
  493. DP_ERR("unsupported power module: %s\n",
  494. dp_parser_pm_name(pm_type));
  495. return -EINVAL;
  496. }
  497. if (enable) {
  498. if (dp_power_clk_status(dp_power, pm_type)) {
  499. DP_DEBUG("%s clks already enabled\n", dp_parser_pm_name(pm_type));
  500. return 0;
  501. }
  502. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  503. DP_DEBUG("Need to enable core clks before link clks\n");
  504. rc = dp_power_clk_set_rate(power, pm_type, enable);
  505. if (rc) {
  506. DP_ERR("failed to enable clks: %s. err=%d\n",
  507. dp_parser_pm_name(DP_CORE_PM), rc);
  508. goto error;
  509. } else {
  510. power->core_clks_on = true;
  511. }
  512. }
  513. if (pm_type == DP_LINK_PM && power->link_parent) {
  514. rc = clk_set_parent(power->link_clk_rcg, power->link_parent);
  515. if (rc) {
  516. DP_ERR("failed to set link parent\n");
  517. goto error;
  518. }
  519. }
  520. if (((pm_type == DP_STREAM0_PM) || (pm_type == DP_STREAM1_PM))
  521. && (!power->link_clks_on)) {
  522. DP_ERR("Need to enable link clk before stream clks\n");
  523. goto error;
  524. }
  525. }
  526. rc = dp_power_clk_set_rate(power, pm_type, enable);
  527. if (rc) {
  528. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  529. enable ? "enable" : "disable",
  530. dp_parser_pm_name(pm_type), rc);
  531. goto error;
  532. }
  533. if (pm_type == DP_CORE_PM)
  534. power->core_clks_on = enable;
  535. else if (pm_type == DP_STREAM0_PM)
  536. power->strm0_clks_on = enable;
  537. else if (pm_type == DP_STREAM1_PM)
  538. power->strm1_clks_on = enable;
  539. else if (pm_type == DP_LINK_PM)
  540. power->link_clks_on = enable;
  541. if (pm_type == DP_STREAM0_PM)
  542. power->strm0_clks_parked = false;
  543. if (pm_type == DP_STREAM1_PM)
  544. power->strm1_clks_parked = false;
  545. if (pm_type == DP_LINK_PM)
  546. power->link_clks_parked = false;
  547. /*
  548. * This log is printed only when user connects or disconnects
  549. * a DP cable. As this is a user-action and not a frequent
  550. * usecase, it is not going to flood the kernel logs. Also,
  551. * helpful in debugging the NOC issues.
  552. */
  553. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  554. power->core_clks_on ? "on" : "off",
  555. power->link_clks_on ? "on" : "off",
  556. power->strm0_clks_on ? "on" : "off",
  557. power->strm1_clks_on ? "on" : "off");
  558. error:
  559. return rc;
  560. }
  561. static int dp_power_request_gpios(struct dp_power_private *power)
  562. {
  563. int rc = 0, i;
  564. struct device *dev;
  565. struct dss_module_power *mp;
  566. static const char * const gpio_names[] = {
  567. "aux_enable", "aux_sel", "usbplug_cc",
  568. };
  569. if (!power) {
  570. DP_ERR("invalid power data\n");
  571. return -EINVAL;
  572. }
  573. dev = &power->pdev->dev;
  574. mp = &power->parser->mp[DP_CORE_PM];
  575. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  576. unsigned int gpio = mp->gpio_config[i].gpio;
  577. if (gpio_is_valid(gpio)) {
  578. rc = gpio_request(gpio, gpio_names[i]);
  579. if (rc) {
  580. DP_ERR("request %s gpio failed, rc=%d\n",
  581. gpio_names[i], rc);
  582. goto error;
  583. }
  584. }
  585. }
  586. return 0;
  587. error:
  588. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  589. unsigned int gpio = mp->gpio_config[i].gpio;
  590. if (gpio_is_valid(gpio))
  591. gpio_free(gpio);
  592. }
  593. return rc;
  594. }
  595. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  596. {
  597. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  598. }
  599. #if !defined(CONFIG_SECDP)
  600. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  601. {
  602. int i;
  603. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  604. struct dss_gpio *config = mp->gpio_config;
  605. for (i = 0; i < mp->num_gpio; i++) {
  606. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  607. config->value = flip;
  608. if (gpio_is_valid(config->gpio)) {
  609. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  610. config->value);
  611. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  612. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  613. gpio_direction_output(config->gpio,
  614. config->value);
  615. else
  616. gpio_set_value(config->gpio, config->value);
  617. }
  618. config++;
  619. }
  620. }
  621. #else
  622. int secdp_power_request_gpios(struct dp_power *dp_power)
  623. {
  624. int rc;
  625. struct dp_power_private *power;
  626. if (!dp_power) {
  627. DP_ERR("invalid power data\n");
  628. rc = -EINVAL;
  629. goto exit;
  630. }
  631. power = container_of(dp_power, struct dp_power_private, dp_power);
  632. rc = dp_power_request_gpios(power);
  633. exit:
  634. return rc;
  635. }
  636. #if IS_ENABLED(CONFIG_COMBO_REDRIVER_PTN36502) || IS_ENABLED(CONFIG_COMBO_REDRIVER_PS5169)
  637. static inline char *secdp_redriver_switch_to_string(int event)
  638. {
  639. switch (event) {
  640. case REDRIVER_SWITCH_UNKNOWN:
  641. return DP_ENUM_STR(REDRIVER_SWITCH_UNKNOWN);
  642. case REDRIVER_SWITCH_RESET:
  643. return DP_ENUM_STR(REDRIVER_SWITCH_RESET);
  644. case REDRIVER_SWITCH_CROSS:
  645. return DP_ENUM_STR(REDRIVER_SWITCH_CROSS);
  646. case REDRIVER_SWITCH_THROU:
  647. return DP_ENUM_STR(REDRIVER_SWITCH_THROU);
  648. default:
  649. return "unknown";
  650. }
  651. }
  652. #endif
  653. #if IS_ENABLED(CONFIG_COMBO_REDRIVER_PTN36502)
  654. static void secdp_ptn36502_aux_ctrl(struct dp_power_private *power, int cross)
  655. {
  656. DP_DEBUG("cross:%s\n", secdp_redriver_switch_to_string(cross));
  657. switch (cross) {
  658. case REDRIVER_SWITCH_CROSS:
  659. ptn36502_config(AUX_CROSS_MODE, 0);
  660. break;
  661. case REDRIVER_SWITCH_THROU:
  662. ptn36502_config(AUX_THRU_MODE, 0);
  663. break;
  664. case REDRIVER_SWITCH_RESET:
  665. ptn36502_config(SAFE_STATE, 0);
  666. break;
  667. default:
  668. DP_INFO("unknown: %d\n", cross);
  669. break;
  670. }
  671. }
  672. static void secdp_ptn36502_onoff(struct dp_power_private *power, bool enable, int lane)
  673. {
  674. DP_DEBUG("en:%d, lane:%d\n", enable, lane);
  675. if (enable) {
  676. int val = -1;
  677. if (lane == 2)
  678. ptn36502_config(DP2_LANE_USB3_MODE, 1);
  679. else if (lane == 4)
  680. ptn36502_config(DP4_LANE_MODE, 1);
  681. else {
  682. DP_ERR("error! unknown lane: %d\n", lane);
  683. goto exit;
  684. }
  685. val = ptn36502_i2c_read(Chip_ID);
  686. DP_INFO("Chip_ID: 0x%x\n", val);
  687. val = ptn36502_i2c_read(Chip_Rev);
  688. DP_INFO("Chip_Rev: 0x%x\n", val);
  689. } else {
  690. ptn36502_config(SAFE_STATE, 0);
  691. }
  692. exit:
  693. return;
  694. }
  695. static void secdp_ptn36502_notify_linkinfo(struct dp_power_private *power, u32 bw_code, u8 v_level, u8 p_level)
  696. {
  697. DP_ENTER("0x%x,%d,%d, do nothing!\n", bw_code, v_level, p_level);
  698. //.TODO:
  699. }
  700. #elif IS_ENABLED(CONFIG_COMBO_REDRIVER_PS5169)
  701. static void secdp_ps5169_aux_ctrl(struct dp_power_private *power, int cross)
  702. {
  703. /*
  704. * ps5169 does not support AUX switching function.
  705. * It needs to be done by AUX switch IC
  706. */
  707. DP_ENTER("cross: %s, do nothing!\n",
  708. secdp_redriver_switch_to_string(cross));
  709. }
  710. static void secdp_ps5169_onoff(struct dp_power_private *power, bool enable, int lane)
  711. {
  712. DP_DEBUG("en:%d, lane:%d\n", enable, lane);
  713. if (enable) {
  714. if (lane == 2)
  715. ps5169_config(DP2_LANE_USB_MODE, 1);
  716. else if (lane == 4)
  717. ps5169_config(DP_ONLY_MODE, 1);
  718. else {
  719. DP_ERR("error! unknown lane: %d\n", lane);
  720. goto exit;
  721. }
  722. DP_INFO("Chip_ID1: 0x%x, Chip_Rev1: 0x%x\n",
  723. ps5169_i2c_read(Chip_ID1), ps5169_i2c_read(Chip_Rev1));
  724. DP_INFO("Chip_ID2: 0x%x, Chip_Rev2: 0x%x\n",
  725. ps5169_i2c_read(Chip_ID2), ps5169_i2c_read(Chip_Rev2));
  726. } else {
  727. ps5169_config(CLEAR_STATE, 0);
  728. }
  729. exit:
  730. return;
  731. }
  732. static void secdp_ps5169_notify_linkinfo(struct dp_power_private *power,
  733. u32 bw_code, u8 v_level, u8 p_level)
  734. {
  735. struct dp_parser *parser = power->parser;
  736. u8 eq0, eq1;
  737. switch (bw_code) {
  738. case DP_LINK_BW_RBR:
  739. eq0 = parser->ps5169_rbr_eq0[v_level][p_level];
  740. eq1 = parser->ps5169_rbr_eq1[v_level][p_level];
  741. break;
  742. case DP_LINK_BW_HBR:
  743. eq0 = parser->ps5169_hbr_eq0[v_level][p_level];
  744. eq1 = parser->ps5169_hbr_eq1[v_level][p_level];
  745. break;
  746. case DP_LINK_BW_HBR2:
  747. eq0 = parser->ps5169_hbr2_eq0[v_level][p_level];
  748. eq1 = parser->ps5169_hbr2_eq1[v_level][p_level];
  749. break;
  750. case DP_LINK_BW_HBR3:
  751. default:
  752. eq0 = parser->ps5169_hbr3_eq0[v_level][p_level];
  753. eq1 = parser->ps5169_hbr3_eq1[v_level][p_level];
  754. break;
  755. }
  756. DP_DEBUG("bw:0x%x, v:%d, p:%d, eq0:0x%x, eq1:0x%x\n",
  757. bw_code, v_level, p_level, eq0, eq1);
  758. ps5169_notify_dplink(eq0, eq1);
  759. }
  760. #endif
  761. void secdp_redriver_onoff(struct dp_power *dp_power,
  762. bool enable, int lane)
  763. {
  764. struct dp_power_private *power;
  765. power = container_of(dp_power, struct dp_power_private, dp_power);
  766. if (power && power->redrv_onoff)
  767. power->redrv_onoff(power, enable, lane);
  768. }
  769. void secdp_redriver_linkinfo(struct dp_power *dp_power,
  770. u32 rate, u8 v_level, u8 p_level)
  771. {
  772. struct dp_power_private *power;
  773. power = container_of(dp_power, struct dp_power_private, dp_power);
  774. if (power && power->redrv_notify_linkinfo)
  775. power->redrv_notify_linkinfo(power, rate, v_level, p_level);
  776. }
  777. static void secdp_redriver_register(struct dp_power_private *power)
  778. {
  779. int use_redrv;
  780. if (!power || !power->parser) {
  781. DP_ERR("invalid power!\n");
  782. goto end;
  783. }
  784. use_redrv = power->parser->use_redrv;
  785. DP_DEBUG("++ use_redrv(%d)\n", use_redrv);
  786. if (!use_redrv) {
  787. DP_INFO("nothing registered!\n");
  788. goto end;
  789. }
  790. #if IS_ENABLED(CONFIG_COMBO_REDRIVER_PTN36502)
  791. power->redrv_onoff = secdp_ptn36502_onoff;
  792. power->redrv_aux_ctrl = secdp_ptn36502_aux_ctrl;
  793. power->redrv_notify_linkinfo = secdp_ptn36502_notify_linkinfo;
  794. DP_INFO("ptn36502 API registered!\n");
  795. #elif IS_ENABLED(CONFIG_COMBO_REDRIVER_PS5169)
  796. power->redrv_onoff = secdp_ps5169_onoff;
  797. power->redrv_aux_ctrl = secdp_ps5169_aux_ctrl;
  798. power->redrv_notify_linkinfo = secdp_ps5169_notify_linkinfo;
  799. DP_INFO("ps5169 API registered!\n");
  800. #endif
  801. end:
  802. return;
  803. }
  804. #if !IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)
  805. /* turn on EDP_AUX switch
  806. * ===================================================
  807. * | usbplug-cc(dir) | orientation | flip | aux-sel |
  808. * ===================================================
  809. * | 0 | CC1 | false | 0 |
  810. * | 1 | CC2 | true | 1 |
  811. * ===================================================
  812. */
  813. static void _secdp_power_set_gpio(struct dp_power_private *power, bool flip)
  814. {
  815. int i, rc = 0;
  816. /*int dir = (flip == false) ? 0 : 1;*/
  817. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  818. struct dss_gpio *config = mp->gpio_config;
  819. struct dp_parser *parser = power->parser;
  820. bool sel_val = false;
  821. // DP_DEBUG("flip:%d, aux_inv:%d, redrv:%d\n",
  822. // flip, parser->aux_sel_inv, parser->use_redrv);
  823. if (parser->aux_sel_inv)
  824. sel_val = true;
  825. for (i = 0; i < mp->num_gpio; i++) {
  826. if (gpio_is_valid(config->gpio)) {
  827. if (dp_power_find_gpio(config->gpio_name, "aux-sel")) {
  828. if (parser->use_redrv == SECDP_REDRV_PTN36502) {
  829. rc = gpio_direction_output(config->gpio, 0);
  830. } else {
  831. /* SECDP_REDRV_PS5169 or SECDP_REDRV_NONE */
  832. bool val = (bool)gpio_get_value(config->gpio);
  833. if ((!flip && (val == sel_val)) ||
  834. (flip && (val == !sel_val))) {
  835. DP_DEBUG("%s: already %d %d, skip\n",
  836. config->gpio_name, flip, val);
  837. break;
  838. }
  839. rc = gpio_direction_output(config->gpio,
  840. (!flip ? sel_val : !sel_val));
  841. }
  842. usleep_range(100, 120);
  843. DP_INFO("[aux-sel] set %d (f:%d,i:%d,r:%d) %d\n",
  844. gpio_get_value(config->gpio),
  845. flip, parser->aux_sel_inv, parser->use_redrv, rc);
  846. break;
  847. }
  848. }
  849. config++;
  850. }
  851. usleep_range(100, 120);
  852. config = mp->gpio_config;
  853. for (i = 0; i < mp->num_gpio; i++) {
  854. if (gpio_is_valid(config->gpio)) {
  855. if (dp_power_find_gpio(config->gpio_name, "aux-en")) {
  856. if (!gpio_get_value(config->gpio)) {
  857. DP_DEBUG("%s: already enabled, skip\n",
  858. config->gpio_name);
  859. break;
  860. }
  861. rc = gpio_direction_output(config->gpio, 0);
  862. usleep_range(100, 120);
  863. DP_INFO("[aux-en] set %d (f:%d,i:%d,r:%d) %d\n",
  864. gpio_get_value(config->gpio),
  865. flip, parser->aux_sel_inv, parser->use_redrv, rc);
  866. break;
  867. }
  868. }
  869. config++;
  870. }
  871. }
  872. /* turn off EDP_AUX switch */
  873. static void _secdp_power_unset_gpio(struct dp_power_private *power)
  874. {
  875. int i, rc = 0;
  876. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  877. struct dss_gpio *config = mp->gpio_config;
  878. DP_ENTER("\n");
  879. for (i = 0; i < mp->num_gpio; i++) {
  880. if (gpio_is_valid(config->gpio)) {
  881. if (dp_power_find_gpio(config->gpio_name, "aux-en")) {
  882. if (gpio_get_value(config->gpio)) {
  883. DP_DEBUG("%s: already disabled, skip\n",
  884. config->gpio_name);
  885. break;
  886. }
  887. rc = gpio_direction_output(config->gpio, 1);
  888. usleep_range(100, 120);
  889. DP_INFO("[aux-en] set %d, %d\n",
  890. gpio_get_value(config->gpio), rc);
  891. break;
  892. }
  893. }
  894. config++;
  895. }
  896. config = mp->gpio_config;
  897. for (i = 0; i < mp->num_gpio; i++) {
  898. if (gpio_is_valid(config->gpio)) {
  899. if (dp_power_find_gpio(config->gpio_name, "aux-sel")) {
  900. if (!gpio_get_value(config->gpio)) {
  901. DP_DEBUG("%s: already 0, skip\n",
  902. config->gpio_name);
  903. break;
  904. }
  905. rc = gpio_direction_output(config->gpio, 0);
  906. usleep_range(100, 120);
  907. DP_INFO("[aux-sel] set %d, %d\n",
  908. gpio_get_value(config->gpio), rc);
  909. break;
  910. }
  911. }
  912. config++;
  913. }
  914. }
  915. #else/*CONFIG_SBU_SWITCH_CONTROL*/
  916. static void _secdp_sbu_switch_on(struct dp_power_private *power, bool flip)
  917. {
  918. int cc_sbu = !flip ? CLOSE_SBU_CC1_ACTIVE : CLOSE_SBU_CC2_ACTIVE;
  919. if (power->sbu_status == cc_sbu)
  920. return;
  921. usbpd_sbu_switch_control(cc_sbu);
  922. power->sbu_status = cc_sbu;
  923. }
  924. static void _secdp_sbu_switch_off(struct dp_power_private *power)
  925. {
  926. if (power->sbu_status == OPEN_SBU)
  927. return;
  928. usbpd_sbu_switch_control(OPEN_SBU);
  929. power->sbu_status = OPEN_SBU;
  930. }
  931. #endif
  932. void secdp_power_set_gpio(struct dp_power *dp_power, bool flip)
  933. {
  934. struct dp_power_private *power;
  935. power = container_of(dp_power, struct dp_power_private, dp_power);
  936. #if !IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)
  937. _secdp_power_set_gpio(power, flip);
  938. #else
  939. _secdp_sbu_switch_on(power, flip);
  940. #endif
  941. }
  942. void secdp_power_unset_gpio(struct dp_power *dp_power)
  943. {
  944. struct dp_power_private *power;
  945. power = container_of(dp_power, struct dp_power_private, dp_power);
  946. #if !IS_ENABLED(CONFIG_SBU_SWITCH_CONTROL)
  947. _secdp_power_unset_gpio(power);
  948. #else
  949. _secdp_sbu_switch_off(power);
  950. #endif
  951. }
  952. #if defined(CONFIG_SECDP_FACTORY_DPSWITCH_TEST)
  953. static void secdp_redriver_aux_ctrl(struct dp_power_private *power,
  954. int cross)
  955. {
  956. if (power && power->redrv_aux_ctrl)
  957. power->redrv_aux_ctrl(power, cross);
  958. }
  959. /*
  960. * @aux_sel : 1 or 0
  961. */
  962. void secdp_config_gpios_factory(struct dp_power *dp_power, int aux_sel, bool on)
  963. {
  964. struct dp_power_private *power;
  965. power = container_of(dp_power, struct dp_power_private, dp_power);
  966. DP_DEBUG("sel:%d, on:%d\n", aux_sel, on);
  967. if (on) {
  968. secdp_aux_pullup_vreg_enable(power, true);
  969. secdp_power_set_gpio(dp_power, aux_sel);
  970. if (aux_sel == 1)
  971. secdp_redriver_aux_ctrl(power, REDRIVER_SWITCH_CROSS);
  972. else if (aux_sel == 0)
  973. secdp_redriver_aux_ctrl(power, REDRIVER_SWITCH_THROU);
  974. else
  975. DP_ERR("unknown <%d>\n", aux_sel);
  976. } else {
  977. secdp_redriver_aux_ctrl(power, REDRIVER_SWITCH_RESET);
  978. secdp_power_unset_gpio(dp_power);
  979. secdp_aux_pullup_vreg_enable(power, false);
  980. }
  981. }
  982. #endif
  983. enum dp_hpd_plug_orientation secdp_get_plug_orientation(struct dp_power *dp_power)
  984. {
  985. struct dp_power_private *power;
  986. struct dp_parser *parser;
  987. struct dss_module_power *mp;
  988. struct dss_gpio *config;
  989. int i, dir;
  990. power = container_of(dp_power, struct dp_power_private, dp_power);
  991. parser = power->parser;
  992. mp = &power->parser->mp[DP_CORE_PM];
  993. config = mp->gpio_config;
  994. for (i = 0; i < mp->num_gpio; i++) {
  995. if (gpio_is_valid(config->gpio)) {
  996. if (dp_power_find_gpio(config->gpio_name,
  997. "usbplug-cc")) {
  998. dir = gpio_get_value(config->gpio);
  999. if (parser->cc_dir_inv)
  1000. dir = !dir;
  1001. DP_INFO("cc_dir_inv:%d, orientation:%s\n",
  1002. parser->cc_dir_inv, !dir ? "CC1" : "CC2");
  1003. if (dir == 0)
  1004. return ORIENTATION_CC1;
  1005. else /* if (dir == 1) */
  1006. return ORIENTATION_CC2;
  1007. }
  1008. }
  1009. config++;
  1010. }
  1011. /*cannot be here*/
  1012. return ORIENTATION_NONE;
  1013. }
  1014. #endif
  1015. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  1016. bool enable)
  1017. {
  1018. #if !defined(CONFIG_SECDP)
  1019. int rc = 0, i;
  1020. struct dss_module_power *mp;
  1021. struct dss_gpio *config;
  1022. mp = &power->parser->mp[DP_CORE_PM];
  1023. config = mp->gpio_config;
  1024. if (enable) {
  1025. rc = dp_power_request_gpios(power);
  1026. if (rc) {
  1027. DP_ERR("gpio request failed\n");
  1028. return rc;
  1029. }
  1030. dp_power_set_gpio(power, flip);
  1031. } else {
  1032. for (i = 0; i < mp->num_gpio; i++) {
  1033. if (gpio_is_valid(config[i].gpio)) {
  1034. gpio_set_value(config[i].gpio, 0);
  1035. gpio_free(config[i].gpio);
  1036. }
  1037. }
  1038. }
  1039. #else
  1040. struct dp_power *dp_power = &power->dp_power;
  1041. if (enable)
  1042. secdp_power_set_gpio(dp_power, flip);
  1043. else
  1044. secdp_power_unset_gpio(dp_power);
  1045. #endif
  1046. return 0;
  1047. }
  1048. static int dp_power_mmrm_init(struct dp_power *dp_power, struct sde_power_handle *phandle, void *dp,
  1049. int (*dp_display_mmrm_callback)(struct mmrm_client_notifier_data *notifier_data))
  1050. {
  1051. int rc = 0;
  1052. enum dp_pm_type module;
  1053. struct dp_power_private *power = container_of(dp_power, struct dp_power_private, dp_power);
  1054. struct device *dev = &power->pdev->dev;
  1055. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  1056. struct dss_module_power *pm = &power->parser->mp[module];
  1057. if (!pm->num_clk)
  1058. continue;
  1059. rc = msm_dss_mmrm_register(dev, pm, dp_display_mmrm_callback,
  1060. dp, &phandle->mmrm_enable);
  1061. if (rc)
  1062. DP_ERR("mmrm register failed rc=%d\n", rc);
  1063. }
  1064. return rc;
  1065. }
  1066. static int dp_power_client_init(struct dp_power *dp_power,
  1067. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  1068. {
  1069. int rc = 0;
  1070. struct dp_power_private *power;
  1071. if (!drm_dev) {
  1072. DP_ERR("invalid drm_dev\n");
  1073. return -EINVAL;
  1074. }
  1075. power = container_of(dp_power, struct dp_power_private, dp_power);
  1076. rc = dp_power_regulator_init(power);
  1077. if (rc) {
  1078. DP_ERR("failed to init regulators\n");
  1079. goto error_power;
  1080. }
  1081. rc = dp_power_clk_init(power, true);
  1082. if (rc) {
  1083. DP_ERR("failed to init clocks\n");
  1084. goto error_clk;
  1085. }
  1086. dp_power->phandle = phandle;
  1087. dp_power->drm_dev = drm_dev;
  1088. #if defined(CONFIG_SECDP)
  1089. rc = dp_power_pinctrl_set(power, false);
  1090. if (rc) {
  1091. DP_ERR("failed to set pinctrl state\n");
  1092. goto error_client;
  1093. }
  1094. #endif
  1095. return 0;
  1096. #if defined(CONFIG_SECDP)
  1097. error_client:
  1098. dp_power_clk_init(power, false);
  1099. #endif
  1100. error_clk:
  1101. dp_power_regulator_deinit(power);
  1102. error_power:
  1103. return rc;
  1104. }
  1105. static void dp_power_client_deinit(struct dp_power *dp_power)
  1106. {
  1107. struct dp_power_private *power;
  1108. if (!dp_power) {
  1109. DP_ERR("invalid power data\n");
  1110. return;
  1111. }
  1112. power = container_of(dp_power, struct dp_power_private, dp_power);
  1113. dp_power_clk_init(power, false);
  1114. dp_power_regulator_deinit(power);
  1115. }
  1116. static int dp_power_park_clocks(struct dp_power *dp_power)
  1117. {
  1118. int rc = 0;
  1119. struct dp_power_private *power;
  1120. if (!dp_power) {
  1121. DP_ERR("invalid power data\n");
  1122. return -EINVAL;
  1123. }
  1124. power = container_of(dp_power, struct dp_power_private, dp_power);
  1125. rc = dp_power_park_module(power, DP_STREAM0_PM);
  1126. if (rc) {
  1127. DP_ERR("failed to park stream 0. err=%d\n", rc);
  1128. goto error;
  1129. }
  1130. rc = dp_power_park_module(power, DP_STREAM1_PM);
  1131. if (rc) {
  1132. DP_ERR("failed to park stream 1. err=%d\n", rc);
  1133. goto error;
  1134. }
  1135. rc = dp_power_park_module(power, DP_LINK_PM);
  1136. if (rc) {
  1137. DP_ERR("failed to park link clock. err=%d\n", rc);
  1138. goto error;
  1139. }
  1140. error:
  1141. return rc;
  1142. }
  1143. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  1144. {
  1145. int rc = 0;
  1146. struct dp_power_private *power;
  1147. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  1148. DP_ERR("invalid power data. stream %d\n", strm_id);
  1149. rc = -EINVAL;
  1150. goto exit;
  1151. }
  1152. power = container_of(dp_power, struct dp_power_private, dp_power);
  1153. if (strm_id == DP_STREAM_0) {
  1154. if (power->pixel_clk_rcg && power->pixel_parent)
  1155. rc = clk_set_parent(power->pixel_clk_rcg,
  1156. power->pixel_parent);
  1157. else
  1158. DP_WARN("skipped for strm_id=%d\n", strm_id);
  1159. } else if (strm_id == DP_STREAM_1) {
  1160. if (power->pixel1_clk_rcg && power->pixel_parent)
  1161. rc = clk_set_parent(power->pixel1_clk_rcg,
  1162. power->pixel_parent);
  1163. else
  1164. DP_WARN("skipped for strm_id=%d\n", strm_id);
  1165. }
  1166. if (rc)
  1167. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  1168. exit:
  1169. return rc;
  1170. }
  1171. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  1172. {
  1173. size_t i;
  1174. enum dp_pm_type j;
  1175. struct dss_module_power *mp;
  1176. struct dp_power_private *power;
  1177. bool clk_found = false;
  1178. u64 rate = 0;
  1179. if (!clk_name) {
  1180. DP_ERR("invalid pointer for clk_name\n");
  1181. return 0;
  1182. }
  1183. power = container_of(dp_power, struct dp_power_private, dp_power);
  1184. mp = &dp_power->phandle->mp;
  1185. for (i = 0; i < mp->num_clk; i++) {
  1186. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  1187. rate = clk_get_rate(mp->clk_config[i].clk);
  1188. clk_found = true;
  1189. break;
  1190. }
  1191. }
  1192. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  1193. mp = &power->parser->mp[j];
  1194. for (i = 0; i < mp->num_clk; i++) {
  1195. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  1196. rate = clk_get_rate(mp->clk_config[i].clk);
  1197. clk_found = true;
  1198. break;
  1199. }
  1200. }
  1201. }
  1202. return rate;
  1203. }
  1204. static int dp_power_init(struct dp_power *dp_power, bool flip)
  1205. {
  1206. int rc = 0;
  1207. struct dp_power_private *power;
  1208. if (!dp_power) {
  1209. DP_ERR("invalid power data\n");
  1210. rc = -EINVAL;
  1211. goto exit;
  1212. }
  1213. power = container_of(dp_power, struct dp_power_private, dp_power);
  1214. rc = dp_power_regulator_ctrl(power, true);
  1215. if (rc) {
  1216. DP_ERR("failed to enable regulators\n");
  1217. goto exit;
  1218. }
  1219. rc = dp_power_pinctrl_set(power, true);
  1220. if (rc) {
  1221. DP_ERR("failed to set pinctrl state\n");
  1222. goto err_pinctrl;
  1223. }
  1224. rc = dp_power_config_gpios(power, flip, true);
  1225. if (rc) {
  1226. DP_ERR("failed to enable gpios\n");
  1227. goto err_gpio;
  1228. }
  1229. rc = pm_runtime_resume_and_get(dp_power->drm_dev->dev);
  1230. if (rc < 0) {
  1231. DP_ERR("failed to enable power resource %d\n", rc);
  1232. goto err_sde_power;
  1233. }
  1234. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  1235. if (rc) {
  1236. DP_ERR("failed to enable DP core clocks\n");
  1237. goto err_clk;
  1238. }
  1239. return 0;
  1240. err_clk:
  1241. pm_runtime_put_sync(dp_power->drm_dev->dev);
  1242. err_sde_power:
  1243. dp_power_config_gpios(power, flip, false);
  1244. err_gpio:
  1245. dp_power_pinctrl_set(power, false);
  1246. err_pinctrl:
  1247. dp_power_regulator_ctrl(power, false);
  1248. exit:
  1249. return rc;
  1250. }
  1251. static int dp_power_deinit(struct dp_power *dp_power)
  1252. {
  1253. int rc = 0;
  1254. struct dp_power_private *power;
  1255. if (!dp_power) {
  1256. DP_ERR("invalid power data\n");
  1257. rc = -EINVAL;
  1258. goto exit;
  1259. }
  1260. power = container_of(dp_power, struct dp_power_private, dp_power);
  1261. if (power->link_clks_on)
  1262. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  1263. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  1264. pm_runtime_put_sync(dp_power->drm_dev->dev);
  1265. dp_power_config_gpios(power, false, false);
  1266. dp_power_pinctrl_set(power, false);
  1267. dp_power_regulator_ctrl(power, false);
  1268. exit:
  1269. return rc;
  1270. }
  1271. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  1272. {
  1273. int rc = 0;
  1274. struct dp_power_private *power;
  1275. struct dp_power *dp_power;
  1276. struct device *dev;
  1277. if (!parser || !pll) {
  1278. DP_ERR("invalid input\n");
  1279. rc = -EINVAL;
  1280. goto error;
  1281. }
  1282. power = kzalloc(sizeof(*power), GFP_KERNEL);
  1283. if (!power) {
  1284. rc = -ENOMEM;
  1285. goto error;
  1286. }
  1287. power->parser = parser;
  1288. power->pll = pll;
  1289. power->pdev = parser->pdev;
  1290. dp_power = &power->dp_power;
  1291. dev = &power->pdev->dev;
  1292. dp_power->init = dp_power_init;
  1293. dp_power->deinit = dp_power_deinit;
  1294. dp_power->clk_enable = dp_power_clk_enable;
  1295. dp_power->clk_status = dp_power_clk_status;
  1296. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  1297. dp_power->park_clocks = dp_power_park_clocks;
  1298. dp_power->clk_get_rate = dp_power_clk_get_rate;
  1299. dp_power->power_client_init = dp_power_client_init;
  1300. dp_power->power_client_deinit = dp_power_client_deinit;
  1301. dp_power->power_mmrm_init = dp_power_mmrm_init;
  1302. dp_power->dp_phy_gdsc = devm_regulator_get(dev, "dp_phy_gdsc");
  1303. if (IS_ERR(dp_power->dp_phy_gdsc)) {
  1304. dp_power->dp_phy_gdsc = NULL;
  1305. DP_DEBUG("Optional GDSC regulator is missing\n");
  1306. }
  1307. #if defined(CONFIG_SECDP)
  1308. secdp_redriver_register(power);
  1309. mutex_init(&power->dp_clk_lock);
  1310. #endif
  1311. return dp_power;
  1312. error:
  1313. return ERR_PTR(rc);
  1314. }
  1315. void dp_power_put(struct dp_power *dp_power)
  1316. {
  1317. struct dp_power_private *power = NULL;
  1318. if (!dp_power)
  1319. return;
  1320. power = container_of(dp_power, struct dp_power_private, dp_power);
  1321. kfree(power);
  1322. }