cfg_mlme_he_caps.h 16 KB

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  1. /*
  2. * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. /**
  19. * DOC: This file contains centralized definitions of converged configuration.
  20. */
  21. #ifndef __CFG_MLME_HE_CAPS_H
  22. #define __CFG_MLME_HE_CAPS_H
  23. #define CFG_HE_CONTROL CFG_BOOL( \
  24. "he_control", \
  25. 0, \
  26. "HE Control")
  27. #define CFG_HE_TWT_REQUESTOR CFG_BOOL( \
  28. "he_twt_requestor", \
  29. 0, \
  30. "HE Twt Requestor")
  31. #define CFG_HE_TWT_RESPONDER CFG_BOOL( \
  32. "he_twt_responder", \
  33. 0, \
  34. "HE Twt Responder")
  35. #define CFG_HE_FRAGMENTATION CFG_UINT( \
  36. "he_fragmentation", \
  37. 0, \
  38. 3, \
  39. 0, \
  40. CFG_VALUE_OR_DEFAULT, \
  41. "HE Fragmentation")
  42. #define CFG_HE_MAX_FRAG_MSDU CFG_UINT( \
  43. "he_max_frag_msdu", \
  44. 0, \
  45. 7, \
  46. 0, \
  47. CFG_VALUE_OR_DEFAULT, \
  48. "HE Max Frag Msdu")
  49. #define CFG_HE_MIN_FRAG_SIZE CFG_UINT( \
  50. "he_min_frag_size", \
  51. 0, \
  52. 3, \
  53. 0, \
  54. CFG_VALUE_OR_DEFAULT, \
  55. "HE Min Frag Size")
  56. #define CFG_HE_TRIG_PAD CFG_UINT( \
  57. "he_trig_pad", \
  58. 0, \
  59. 2, \
  60. 0, \
  61. CFG_VALUE_OR_DEFAULT, \
  62. "HE Trig Pad")
  63. #define CFG_HE_MTID_AGGR_RX CFG_UINT( \
  64. "he_mtid_aggr_rx", \
  65. 0, \
  66. 7, \
  67. 0, \
  68. CFG_VALUE_OR_DEFAULT, \
  69. "HE Mtid Aggr")
  70. #define CFG_HE_LINK_ADAPTATION CFG_UINT( \
  71. "he_link_adaptation", \
  72. 0, \
  73. 3, \
  74. 0, \
  75. CFG_VALUE_OR_DEFAULT, \
  76. "HE Link Adaptation")
  77. #define CFG_HE_ALL_ACK CFG_BOOL( \
  78. "he_all_ack", \
  79. 0, \
  80. "HE All Ack")
  81. #define CFG_HE_TRIGD_RSP_SCHEDULING CFG_BOOL( \
  82. "he_trigd_rsp_scheduling", \
  83. 0, \
  84. "HE Trigd Rsp Scheduling")
  85. #define CFG_HE_BUFFER_STATUS_RPT CFG_BOOL( \
  86. "he_buffer_status_rpt", \
  87. 0, \
  88. "HE Buffer Status Rpt")
  89. #define CFG_HE_BCAST_TWT CFG_BOOL( \
  90. "he_bcast_twt", \
  91. 0, \
  92. "HE Bcast twt")
  93. #define CFG_HE_BA_32BIT CFG_BOOL( \
  94. "he_ba_32bit", \
  95. 0, \
  96. "HE BA 32Bit")
  97. #define CFG_HE_MU_CASCADING CFG_BOOL( \
  98. "he_mu_cascading", \
  99. 0, \
  100. "HE Mu Cascading")
  101. #define CFG_HE_MULTI_TID CFG_BOOL( \
  102. "he_multi_tid", \
  103. 0, \
  104. "HE Multi Tid")
  105. #define CFG_HE_OMI CFG_BOOL( \
  106. "he_omi", \
  107. 0, \
  108. "HE Omi")
  109. #define CFG_HE_OFDMA_RA CFG_BOOL( \
  110. "he_ofdma_ra", \
  111. 0, \
  112. "HE Ofdma Ra")
  113. #define CFG_HE_MAX_AMPDU_LEN CFG_UINT( \
  114. "he_max_ampdu_len", \
  115. 0, \
  116. 3, \
  117. 0, \
  118. CFG_VALUE_OR_DEFAULT, \
  119. "HE Max Ampdu Len")
  120. #define CFG_HE_AMSDU_FRAG CFG_BOOL( \
  121. "he_amspdu_frag", \
  122. 0, \
  123. "HE Amsdu Frag")
  124. #define CFG_HE_FLEX_TWT_SCHED CFG_BOOL( \
  125. "he_flex_twt_sched", \
  126. 0, \
  127. "HE Flex Twt Sched")
  128. #define CFG_HE_RX_CTRL CFG_BOOL( \
  129. "he_rx_ctrl", \
  130. 0, \
  131. "HE Rx Ctrl")
  132. #define CFG_HE_BSRP_AMPDU_AGGR CFG_BOOL( \
  133. "he_bsrp_ampdu_aggr", \
  134. 0, \
  135. "He Bspr Ampdu Aggr")
  136. #define CFG_HE_QTP CFG_BOOL( \
  137. "he_qtp", \
  138. 0, \
  139. "He Qtp")
  140. #define CFG_HE_A_BQR CFG_BOOL( \
  141. "he_a_bqr", \
  142. 0, \
  143. "He A Bqr")
  144. #define CFG_HE_SR_RESPONDER CFG_BOOL( \
  145. "he_sr_responder", \
  146. 0, \
  147. "He Sr Responder")
  148. #define CFG_HE_NDP_FEEDBACK_SUPP CFG_BOOL( \
  149. "he_ndp_feedback_supp", \
  150. 0, \
  151. "He Ndp Feedback Supp")
  152. #define CFG_HE_OPS_SUPP CFG_BOOL( \
  153. "he_ops_supp", \
  154. 0, \
  155. "He Ops Supp")
  156. #define CFG_HE_AMSDU_IN_AMPDU CFG_BOOL( \
  157. "he_amsdu_in_ampdu", \
  158. 0, \
  159. "He Amsdu In Ampdu")
  160. #define CFG_HE_MTID_AGGR_TX CFG_UINT( \
  161. "he_mtid_aggr_tx", \
  162. 0, \
  163. 0x7, \
  164. 0, \
  165. CFG_VALUE_OR_DEFAULT, \
  166. "He MTid Aggr Tx")
  167. #define CFG_HE_SUB_CH_SEL_TX CFG_BOOL( \
  168. "he_sub_ch_sel_tx", \
  169. 0, \
  170. "He Sub cg sel tx")
  171. #define CFG_HE_UL_2X996_RU CFG_BOOL( \
  172. "he_ul_2x996_ru", \
  173. 0, \
  174. "He Ul 2x996 Ru")
  175. #define CFG_HE_OM_CTRL_UL_MU_DIS_RX CFG_BOOL( \
  176. "he_om_ctrl_ul_mu_dis_rx", \
  177. 0, \
  178. "He Om Ctrl Ul My Dis Rx")
  179. #define CFG_HE_DYNAMIC_SMPS CFG_BOOL( \
  180. "he_dynamic_smps", \
  181. 0, \
  182. "He Dyanmic SMPS")
  183. #define CFG_HE_PUNCTURED_SOUNDING CFG_BOOL( \
  184. "he_punctured_sounding", \
  185. 0, \
  186. "He Punctured Sounding")
  187. #define CFG_HE_HT_VHT_TRG_FRM_RX CFG_BOOL( \
  188. "ht_vht_trg_frm_rx", \
  189. 0, \
  190. "HT VHT Trigger frame Rx")
  191. #define CFG_HE_CHAN_WIDTH CFG_UINT( \
  192. "he_chan_width", \
  193. 0, \
  194. 0x3F, \
  195. 0, \
  196. CFG_VALUE_OR_DEFAULT, \
  197. "He Chan Width")
  198. #define CFG_HE_RX_PREAM_PUNC CFG_UINT( \
  199. "he_rx_pream_punc", \
  200. 0, \
  201. 0xF, \
  202. 0, \
  203. CFG_VALUE_OR_DEFAULT, \
  204. "He Rx Pream Punc")
  205. #define CFG_HE_CLASS_OF_DEVICE CFG_BOOL( \
  206. "he_class_of_device", \
  207. 0, \
  208. "He Class Of Device")
  209. #define CFG_HE_LDPC CFG_BOOL( \
  210. "he_ldpc", \
  211. 0, \
  212. "He Ldpc")
  213. #define CFG_HE_LTF_PPDU CFG_UINT( \
  214. "he_ltf_ppdu", \
  215. 0, \
  216. 3, \
  217. 0, \
  218. CFG_VALUE_OR_DEFAULT, \
  219. "He Ltf Ppdu")
  220. #define CFG_HE_MIDAMBLE_RX_MAX_NSTS CFG_UINT( \
  221. "he_midamble_rx_max_nsts", \
  222. 0, \
  223. 3, \
  224. 0, \
  225. CFG_VALUE_OR_DEFAULT, \
  226. "He Midamble Rx Max Nsts")
  227. #define CFG_HE_LTF_NDP CFG_UINT( \
  228. "he_ltf_ndp", \
  229. 0, \
  230. 3, \
  231. 0, \
  232. CFG_VALUE_OR_DEFAULT, \
  233. "He Ltf Ndp")
  234. #define CFG_HE_TX_STBC_LT80 CFG_BOOL( \
  235. "he_tx_stbc_lt80_sta", \
  236. 0, \
  237. "He Tx Stbc Lt80")
  238. #define CFG_HE_RX_STBC_LT80 CFG_BOOL( \
  239. "he_rx_stbc_lt80", \
  240. 0, \
  241. "He Rx Stbc Lt80")
  242. #define CFG_HE_DOPPLER CFG_UINT( \
  243. "he_doppler", \
  244. 0, \
  245. 3, \
  246. 0, \
  247. CFG_VALUE_OR_DEFAULT, \
  248. "He Doppler")
  249. #define CFG_HE_DCM_TX CFG_UINT( \
  250. "he_dcm_tx", \
  251. 0, \
  252. 7, \
  253. 0, \
  254. CFG_VALUE_OR_DEFAULT, \
  255. "He Dcm Tx")
  256. #define CFG_HE_DCM_RX CFG_UINT( \
  257. "he_dcm_rx", \
  258. 0, \
  259. 7, \
  260. 0, \
  261. CFG_VALUE_OR_DEFAULT, \
  262. "He Dcm Rx")
  263. #define CFG_HE_MU_PPDU CFG_BOOL( \
  264. "he_mu_ppdu", \
  265. 0, \
  266. "He Mu Ppdu")
  267. #define CFG_HE_SU_BEAMFORMER CFG_BOOL( \
  268. "he_su_beamformer", \
  269. 0, \
  270. "He Su Beamformer")
  271. #define CFG_HE_SU_BEAMFORMEE CFG_BOOL( \
  272. "he_su_beamformee", \
  273. 0, \
  274. "He Su Beamformee")
  275. #define CFG_HE_MU_BEAMFORMER CFG_BOOL( \
  276. "he_mu_beamformer", \
  277. 0, \
  278. "He Mu Beamformer")
  279. #define CFG_HE_BFEE_STS_LT80 CFG_UINT( \
  280. "he_bfee_sts_lt80", \
  281. 0, \
  282. 7, \
  283. 0, \
  284. CFG_VALUE_OR_DEFAULT, \
  285. "He Mu Bfee Sts Lt80")
  286. #define CFG_HE_BFEE_STS_GT80 CFG_UINT( \
  287. "he_bfee_sts_lt80", \
  288. 0, \
  289. 7, \
  290. 0, \
  291. CFG_VALUE_OR_DEFAULT, \
  292. "He Mu Bfee Sts Gt80")
  293. #define CFG_HE_NUM_SOUND_LT80 CFG_UINT( \
  294. "he_num_sound_lt80", \
  295. 0, \
  296. 7, \
  297. 0, \
  298. CFG_VALUE_OR_DEFAULT, \
  299. "He Num Sound Lt80")
  300. #define CFG_HE_NUM_SOUND_GT80 CFG_UINT( \
  301. "he_num_sound_gt80", \
  302. 0, \
  303. 7, \
  304. 0, \
  305. CFG_VALUE_OR_DEFAULT, \
  306. "He Num Sound Gt80")
  307. #define CFG_HE_SU_FEED_TONE16 CFG_BOOL( \
  308. "he_su_feed_tone16", \
  309. 0, \
  310. "He Su Feed Tone16")
  311. #define CFG_HE_MU_FEED_TONE16 CFG_BOOL( \
  312. "he_mu_feed_tone16", \
  313. 0, \
  314. "He Mu Feed Tone16")
  315. #define CFG_HE_CODEBOOK_SU CFG_BOOL( \
  316. "he_codebook_su", \
  317. 0, \
  318. "He Codebook Su")
  319. #define CFG_HE_CODEBOOK_MU CFG_BOOL( \
  320. "he_codebook_mu", \
  321. 0, \
  322. "He Codebook Mu")
  323. #define CFG_HE_BFRM_FEED CFG_UINT( \
  324. "he_bfrm_feed", \
  325. 0, \
  326. 7, \
  327. 0, \
  328. CFG_VALUE_OR_DEFAULT, \
  329. "He Bfrm Feed")
  330. #define CFG_HE_ER_SU_PPDU CFG_BOOL( \
  331. "he_bfrm_feed", \
  332. 0, \
  333. "He Er Su Ppdu")
  334. #define CFG_HE_DL_PART_BW CFG_BOOL( \
  335. "he_dl_part_bw", \
  336. 0, \
  337. "He Dl Part Bw")
  338. #define CFG_HE_PPET_PRESENT CFG_BOOL( \
  339. "he_ppet_present", \
  340. 0, \
  341. "He Pper Present")
  342. #define CFG_HE_SRP CFG_BOOL( \
  343. "he_srp", \
  344. 0, \
  345. "He Srp")
  346. #define CFG_HE_POWER_BOOST CFG_BOOL( \
  347. "he_power_boost", \
  348. 0, \
  349. "He Power Boost")
  350. #define CFG_HE_4x_LTF_GI CFG_BOOL( \
  351. "he_4x_ltf_gi", \
  352. 0, \
  353. "He 4x Ltf Gi")
  354. #define CFG_HE_MAX_NC CFG_UINT( \
  355. "he_max_nc", \
  356. 0, \
  357. 7, \
  358. 0, \
  359. CFG_VALUE_OR_DEFAULT, \
  360. "He Max Nc")
  361. #define CFG_HE_RX_STBC_GT80 CFG_BOOL( \
  362. "he_rx_stbc_gt80", \
  363. 0, \
  364. "He Rx Stbc Gt80")
  365. #define CFG_HE_TX_STBC_GT80 CFG_BOOL( \
  366. "he_Tx_stbc_gt80", \
  367. 0, \
  368. "He Tx Stbc Gt80")
  369. #define CFG_HE_ER_4x_LTF_GI CFG_BOOL( \
  370. "he_er_4x_ltf_gi", \
  371. 0, \
  372. "He Er 4x Ltf Gi")
  373. #define CFG_HE_PPDU_20_IN_40MHZ_2G CFG_BOOL( \
  374. "he_ppdu_20_in_40mhz_2g", \
  375. 0, \
  376. "He Ppdu 20 In 40Mhz 2g")
  377. #define CFG_HE_PPDU_20_IN_160_80P80MHZ CFG_BOOL( \
  378. "he_ppdu_20_in_160_80p80mhz", \
  379. 0, \
  380. "He Ppdu 20 In 160 80p80mhz")
  381. #define CFG_HE_PPDU_80_IN_160_80P80MHZ CFG_BOOL( \
  382. "he_ppdu_80_in_160_80p80mhz", \
  383. 0, \
  384. "He Ppdu 80 In 160 80p80mhz")
  385. #define CFG_HE_ER_1X_HE_LTF_GI CFG_BOOL( \
  386. "he_er_1x_he_ltf_gi", \
  387. 0, \
  388. "He Er 1x He Ltf Gi")
  389. #define CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF CFG_BOOL( \
  390. "he_midamble_txrx_1x_he_ltf", \
  391. 0, \
  392. "He Midamble Tx Rx 1x He Ltf")
  393. #define CFG_HE_DCM_MAX_BW CFG_UINT( \
  394. "he_dcm_max_bw", \
  395. 0, \
  396. 3, \
  397. 0, \
  398. CFG_VALUE_OR_DEFAULT, \
  399. "He Dcm Max Bw")
  400. #define CFG_HE_LONGER_16_SIGB_OFDM_SYM CFG_BOOL( \
  401. "he_longer_16_sigb_ofdm_sys", \
  402. 0, \
  403. "He Longer 16 Sigb Ofdm Sys")
  404. #define CFG_HE_NON_TRIG_CQI_FEEDBACK CFG_BOOL( \
  405. "he_rx_mcs_map_lt_80", \
  406. 0, \
  407. "He Non Trig Cqi Feedback")
  408. #define CFG_HE_TX_1024_QAM_LT_242_RU CFG_BOOL( \
  409. "he_tx_1024_qam_lt_242_ru", \
  410. 0, \
  411. "He Tx 1024 Qam Lt 242 Ru")
  412. #define CFG_HE_RX_1024_QAM_LT_242_RU CFG_BOOL( \
  413. "he_rx_1024_qam_lt_242_ru", \
  414. 0, \
  415. "He Rx 1024 Qam Lt 242 Ru")
  416. #define CFG_HE_RX_FULL_BW_MU_CMPR_SIGB CFG_BOOL( \
  417. "he_rx_full_bw_cmpr_sigb", \
  418. 0, \
  419. "He Rx Full Bw Mu Cmpr Sigb")
  420. #define CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB CFG_BOOL( \
  421. "he_rx_full_bw_mu_non_cmpr_sigb", \
  422. 0, \
  423. "He Rx Full Bw Mu Non Cmpr Sigb")
  424. #define CFG_HE_RX_MCS_MAP_LT_80 CFG_UINT( \
  425. "he_rx_mcs_map_lt_80", \
  426. 0, \
  427. 0xFFFF, \
  428. 0xFFF0, \
  429. CFG_VALUE_OR_DEFAULT, \
  430. "He Rx Mcs Map Lt 80")
  431. #define CFG_HE_TX_MCS_MAP_LT_80 CFG_UINT( \
  432. "he_tx_mcs_map_lt_80", \
  433. 0, \
  434. 0xFFFF, \
  435. 0xFFF0, \
  436. CFG_VALUE_OR_DEFAULT, \
  437. "He Tx Mcs Map Lt 80")
  438. #define CFG_HE_RX_MCS_MAP_160 CFG_UINT( \
  439. "he_rx_mcs_map_160", \
  440. 0, \
  441. 0xFFFF, \
  442. 0xFFF0, \
  443. CFG_VALUE_OR_DEFAULT, \
  444. "He Rx Mcs Map 160")
  445. #define CFG_HE_TX_MCS_MAP_160 CFG_UINT( \
  446. "he_tx_mcs_map_160", \
  447. 0, \
  448. 0xFFFF, \
  449. 0xFFF0, \
  450. CFG_VALUE_OR_DEFAULT, \
  451. "He Tx Mcs Map 160")
  452. #define CFG_HE_RX_MCS_MAP_80_80 CFG_UINT( \
  453. "he_rx_mcs_map_80_80", \
  454. 0, \
  455. 0xFFFF, \
  456. 0xFFF0, \
  457. CFG_VALUE_OR_DEFAULT, \
  458. "He Rx Mcs Map 80 80")
  459. #define CFG_HE_TX_MCS_MAP_80_80 CFG_UINT( \
  460. "he_tx_mcs_map_80_80", \
  461. 0, \
  462. 0xFFFF, \
  463. 0xFFF0, \
  464. CFG_VALUE_OR_DEFAULT, \
  465. "He tx Mcs Map 80 80")
  466. #define CFG_HE_OPS_BASIC_MCS_NSS CFG_UINT( \
  467. "cfg_he_ops_basic_mcs_nss", \
  468. 0x0000, \
  469. 0xFFFF, \
  470. 0xFFFC, \
  471. CFG_VALUE_OR_DEFAULT, \
  472. "He Ops Basic Mcs NSS")
  473. /* 11AX related INI configuration */
  474. /*
  475. * <ini>
  476. * he_ul_mumimo - configure ul mu capabilities
  477. * @Min: 0
  478. * @Max: 3
  479. * @Default: 2
  480. *
  481. * This ini is used to configure capabilities of ul mu-mimo
  482. * 0-> no support
  483. * 1-> partial bandwidth support
  484. * 2-> full and partial bandwidth support
  485. *
  486. * Related: NA
  487. *
  488. * Supported Feature: 11AX
  489. *
  490. * Usage: Internal/External
  491. *
  492. * </ini>
  493. */
  494. #define CFG_HE_UL_MUMIMO CFG_INI_UINT( \
  495. "he_ul_mumimo", \
  496. 0, \
  497. 3, \
  498. 2, \
  499. CFG_VALUE_OR_DEFAULT, \
  500. "He Ul Mumimo")
  501. /* 11AX related INI configuration */
  502. /*
  503. * <ini>
  504. * he_dynamic_frag_support - configure dynamic fragmentation
  505. * @Min: 0
  506. * @Max: 3
  507. * @Default: 0
  508. *
  509. * This ini is used to configure dynamic fragmentation.
  510. *
  511. * Related: NA
  512. *
  513. * Supported Feature: 11AX
  514. *
  515. * Usage: Internal/External
  516. *
  517. * </ini>
  518. */
  519. #define CFG_HE_DYNAMIC_FRAGMENTATION CFG_INI_UINT( \
  520. "he_dynamic_frag_support", \
  521. 0, \
  522. 3, \
  523. 0, \
  524. CFG_VALUE_OR_DEFAULT, \
  525. "HE Dynamic Fragmentation")
  526. /*
  527. * <ini>
  528. * enable_ul_mimo- Enable UL MIMO.
  529. * @Min: 0
  530. * @Max: 1
  531. * @Default: 1
  532. *
  533. * This ini is used to enable or disable UL MIMO.
  534. *
  535. * Related: NA
  536. *
  537. * Supported Feature: 11AX
  538. *
  539. * Usage: External
  540. *
  541. * </ini>
  542. */
  543. #define CFG_ENABLE_UL_MIMO CFG_INI_BOOL( \
  544. "enable_ul_mimo", \
  545. 1, \
  546. "He Enble Ul Mimo Name")
  547. /*
  548. * <ini>
  549. * enable_ul_ofdma- Enable UL OFDMA.
  550. * @Min: 0
  551. * @Max: 1
  552. * @Default: 1
  553. *
  554. * This ini is used to enable or disable UL OFDMA.
  555. *
  556. * Related: NA
  557. *
  558. * Supported Feature: 11AX
  559. *
  560. * Usage: External
  561. *
  562. * </ini>
  563. */
  564. #define CFG_ENABLE_UL_OFDMA CFG_INI_BOOL( \
  565. "enable_ul_ofdma", \
  566. 1, \
  567. "He Enable Ul Ofdma Name")
  568. /*
  569. * <ini>
  570. * he_sta_obsspd- 11AX HE OBSS PD bit field
  571. * @Min: 0
  572. * @Max: uin32_t max
  573. * @Default: 0x15b8c2ae
  574. *
  575. * 4 Byte value with each byte representing a signed value for following params:
  576. * Param Bit position Default
  577. * OBSS_PD min (primary) 7:0 -82 (0xae)
  578. * OBSS_PD max (primary) 15:8 -62 (0xc2)
  579. * Secondary channel Ed 23:16 -72 (0xb8)
  580. * TX_PWR(ref) 31:24 21 (0x15)
  581. * This bit field value is directly applied to FW
  582. *
  583. * Related: NA
  584. *
  585. * Supported Feature: 11AX
  586. *
  587. * Usage: External
  588. *
  589. * </ini>
  590. */
  591. #define CFG_HE_STA_OBSSPD CFG_INI_UINT( \
  592. "he_sta_obsspd", \
  593. 0, \
  594. 0xFFFFFFFF, \
  595. 0x15b8c2ae, \
  596. CFG_VALUE_OR_DEFAULT, \
  597. "He Mu Bfee Sts Gt80")
  598. #define CFG_HE_CAPS_ALL \
  599. CFG(CFG_HE_CONTROL) \
  600. CFG(CFG_HE_TWT_REQUESTOR) \
  601. CFG(CFG_HE_TWT_RESPONDER) \
  602. CFG(CFG_HE_FRAGMENTATION) \
  603. CFG(CFG_HE_MAX_FRAG_MSDU) \
  604. CFG(CFG_HE_MIN_FRAG_SIZE) \
  605. CFG(CFG_HE_TRIG_PAD) \
  606. CFG(CFG_HE_MTID_AGGR_RX) \
  607. CFG(CFG_HE_LINK_ADAPTATION) \
  608. CFG(CFG_HE_ALL_ACK) \
  609. CFG(CFG_HE_TRIGD_RSP_SCHEDULING) \
  610. CFG(CFG_HE_BUFFER_STATUS_RPT) \
  611. CFG(CFG_HE_BCAST_TWT) \
  612. CFG(CFG_HE_BA_32BIT) \
  613. CFG(CFG_HE_MU_CASCADING) \
  614. CFG(CFG_HE_MULTI_TID) \
  615. CFG(CFG_HE_OMI) \
  616. CFG(CFG_HE_OFDMA_RA) \
  617. CFG(CFG_HE_MAX_AMPDU_LEN) \
  618. CFG(CFG_HE_AMSDU_FRAG) \
  619. CFG(CFG_HE_FLEX_TWT_SCHED) \
  620. CFG(CFG_HE_RX_CTRL) \
  621. CFG(CFG_HE_BSRP_AMPDU_AGGR) \
  622. CFG(CFG_HE_QTP) \
  623. CFG(CFG_HE_A_BQR) \
  624. CFG(CFG_HE_SR_RESPONDER) \
  625. CFG(CFG_HE_NDP_FEEDBACK_SUPP) \
  626. CFG(CFG_HE_OPS_SUPP) \
  627. CFG(CFG_HE_AMSDU_IN_AMPDU) \
  628. CFG(CFG_HE_CHAN_WIDTH) \
  629. CFG(CFG_HE_MTID_AGGR_TX) \
  630. CFG(CFG_HE_SUB_CH_SEL_TX) \
  631. CFG(CFG_HE_UL_2X996_RU) \
  632. CFG(CFG_HE_OM_CTRL_UL_MU_DIS_RX) \
  633. CFG(CFG_HE_RX_PREAM_PUNC) \
  634. CFG(CFG_HE_CLASS_OF_DEVICE) \
  635. CFG(CFG_HE_LDPC) \
  636. CFG(CFG_HE_LTF_PPDU) \
  637. CFG(CFG_HE_MIDAMBLE_RX_MAX_NSTS) \
  638. CFG(CFG_HE_LTF_NDP) \
  639. CFG(CFG_HE_TX_STBC_LT80) \
  640. CFG(CFG_HE_RX_STBC_LT80) \
  641. CFG(CFG_HE_DOPPLER) \
  642. CFG(CFG_HE_UL_MUMIMO) \
  643. CFG(CFG_HE_DCM_TX) \
  644. CFG(CFG_HE_DCM_RX) \
  645. CFG(CFG_HE_MU_PPDU) \
  646. CFG(CFG_HE_SU_BEAMFORMER) \
  647. CFG(CFG_HE_SU_BEAMFORMEE) \
  648. CFG(CFG_HE_MU_BEAMFORMER) \
  649. CFG(CFG_HE_BFEE_STS_LT80) \
  650. CFG(CFG_HE_BFEE_STS_GT80) \
  651. CFG(CFG_HE_NUM_SOUND_LT80) \
  652. CFG(CFG_HE_NUM_SOUND_GT80) \
  653. CFG(CFG_HE_SU_FEED_TONE16) \
  654. CFG(CFG_HE_MU_FEED_TONE16) \
  655. CFG(CFG_HE_CODEBOOK_SU) \
  656. CFG(CFG_HE_CODEBOOK_MU) \
  657. CFG(CFG_HE_BFRM_FEED) \
  658. CFG(CFG_HE_ER_SU_PPDU) \
  659. CFG(CFG_HE_DL_PART_BW) \
  660. CFG(CFG_HE_PPET_PRESENT) \
  661. CFG(CFG_HE_SRP) \
  662. CFG(CFG_HE_POWER_BOOST) \
  663. CFG(CFG_HE_4x_LTF_GI) \
  664. CFG(CFG_HE_MAX_NC) \
  665. CFG(CFG_HE_RX_STBC_GT80) \
  666. CFG(CFG_HE_TX_STBC_GT80) \
  667. CFG(CFG_HE_ER_4x_LTF_GI) \
  668. CFG(CFG_HE_PPDU_20_IN_40MHZ_2G) \
  669. CFG(CFG_HE_PPDU_20_IN_160_80P80MHZ) \
  670. CFG(CFG_HE_PPDU_80_IN_160_80P80MHZ) \
  671. CFG(CFG_HE_ER_1X_HE_LTF_GI) \
  672. CFG(CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF) \
  673. CFG(CFG_HE_DCM_MAX_BW) \
  674. CFG(CFG_HE_LONGER_16_SIGB_OFDM_SYM) \
  675. CFG(CFG_HE_NON_TRIG_CQI_FEEDBACK) \
  676. CFG(CFG_HE_TX_1024_QAM_LT_242_RU) \
  677. CFG(CFG_HE_RX_1024_QAM_LT_242_RU) \
  678. CFG(CFG_HE_RX_FULL_BW_MU_CMPR_SIGB) \
  679. CFG(CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB) \
  680. CFG(CFG_HE_RX_MCS_MAP_LT_80) \
  681. CFG(CFG_HE_TX_MCS_MAP_LT_80) \
  682. CFG(CFG_HE_RX_MCS_MAP_160) \
  683. CFG(CFG_HE_TX_MCS_MAP_160) \
  684. CFG(CFG_HE_RX_MCS_MAP_80_80) \
  685. CFG(CFG_HE_TX_MCS_MAP_80_80) \
  686. CFG(CFG_HE_OPS_BASIC_MCS_NSS) \
  687. CFG(CFG_HE_DYNAMIC_FRAGMENTATION) \
  688. CFG(CFG_ENABLE_UL_MIMO) \
  689. CFG(CFG_ENABLE_UL_OFDMA) \
  690. CFG(CFG_HE_STA_OBSSPD)
  691. #endif /* __CFG_MLME_HE_CAPS_H */