rx_msdu_end.h 65 KB

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  1. /*
  2. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _RX_MSDU_END_H_
  19. #define _RX_MSDU_END_H_
  20. #if !defined(__ASSEMBLER__)
  21. #endif
  22. #define NUM_OF_DWORDS_RX_MSDU_END 32
  23. #define NUM_OF_QWORDS_RX_MSDU_END 16
  24. struct rx_msdu_end {
  25. uint32_t rxpcu_mpdu_filter_in_category : 2,
  26. sw_frame_group_id : 7,
  27. reserved_0 : 7,
  28. phy_ppdu_id : 16;
  29. uint32_t ip_hdr_chksum : 16,
  30. reported_mpdu_length : 14,
  31. reserved_1a : 2;
  32. uint32_t key_id_octet : 8,
  33. cce_super_rule : 6,
  34. cce_classify_not_done_truncate : 1,
  35. cce_classify_not_done_cce_dis : 1,
  36. cumulative_l3_checksum : 16;
  37. uint32_t rule_indication_31_0 : 32;
  38. uint32_t rule_indication_63_32 : 32;
  39. uint32_t da_offset : 6,
  40. sa_offset : 6,
  41. da_offset_valid : 1,
  42. sa_offset_valid : 1,
  43. reserved_5a : 2,
  44. l3_type : 16;
  45. uint32_t ipv6_options_crc : 32;
  46. uint32_t tcp_seq_number : 32;
  47. uint32_t tcp_ack_number : 32;
  48. uint32_t tcp_flag : 9,
  49. lro_eligible : 1,
  50. reserved_9a : 6,
  51. window_size : 16;
  52. uint32_t tcp_udp_chksum : 16,
  53. sa_idx_timeout : 1,
  54. da_idx_timeout : 1,
  55. msdu_limit_error : 1,
  56. flow_idx_timeout : 1,
  57. flow_idx_invalid : 1,
  58. wifi_parser_error : 1,
  59. amsdu_parser_error : 1,
  60. sa_is_valid : 1,
  61. da_is_valid : 1,
  62. da_is_mcbc : 1,
  63. l3_header_padding : 2,
  64. first_msdu : 1,
  65. last_msdu : 1,
  66. tcp_udp_chksum_fail_copy : 1,
  67. ip_chksum_fail_copy : 1;
  68. uint32_t sa_idx : 16,
  69. da_idx_or_sw_peer_id : 16;
  70. uint32_t msdu_drop : 1,
  71. reo_destination_indication : 5,
  72. flow_idx : 20,
  73. use_ppe : 1,
  74. reserved_12a : 5;
  75. uint32_t fse_metadata : 32;
  76. uint32_t cce_metadata : 16,
  77. sa_sw_peer_id : 16;
  78. uint32_t aggregation_count : 8,
  79. flow_aggregation_continuation : 1,
  80. fisa_timeout : 1,
  81. reserved_15a : 22;
  82. uint32_t cumulative_l4_checksum : 16,
  83. cumulative_ip_length : 16;
  84. uint32_t reserved_17a : 6,
  85. service_code : 9,
  86. priority_valid : 1,
  87. intra_bss : 1,
  88. dest_chip_id : 2,
  89. multicast_echo : 1,
  90. wds_learning_event : 1,
  91. wds_roaming_event : 1,
  92. wds_keep_alive_event : 1,
  93. reserved_17b : 9;
  94. uint32_t msdu_length : 14,
  95. stbc : 1,
  96. ipsec_esp : 1,
  97. l3_offset : 7,
  98. ipsec_ah : 1,
  99. l4_offset : 8;
  100. uint32_t msdu_number : 8,
  101. decap_format : 2,
  102. ipv4_proto : 1,
  103. ipv6_proto : 1,
  104. tcp_proto : 1,
  105. udp_proto : 1,
  106. ip_frag : 1,
  107. tcp_only_ack : 1,
  108. da_is_bcast_mcast : 1,
  109. toeplitz_hash_sel : 2,
  110. ip_fixed_header_valid : 1,
  111. ip_extn_header_valid : 1,
  112. tcp_udp_header_valid : 1,
  113. mesh_control_present : 1,
  114. ldpc : 1,
  115. ip4_protocol_ip6_next_header : 8;
  116. uint32_t toeplitz_hash_2_or_4 : 32;
  117. uint32_t flow_id_toeplitz : 32;
  118. uint32_t user_rssi : 8,
  119. pkt_type : 4,
  120. sgi : 2,
  121. rate_mcs : 4,
  122. receive_bandwidth : 3,
  123. reception_type : 3,
  124. mimo_ss_bitmap : 8;
  125. uint32_t ppdu_start_timestamp_31_0 : 32;
  126. uint32_t ppdu_start_timestamp_63_32 : 32;
  127. uint32_t sw_phy_meta_data : 32;
  128. uint32_t vlan_ctag_ci : 16,
  129. vlan_stag_ci : 16;
  130. uint32_t reserved_27a : 32;
  131. uint32_t reserved_28a : 32;
  132. uint32_t reserved_29a : 32;
  133. uint32_t first_mpdu : 1,
  134. reserved_30a : 1,
  135. mcast_bcast : 1,
  136. ast_index_not_found : 1,
  137. ast_index_timeout : 1,
  138. power_mgmt : 1,
  139. non_qos : 1,
  140. null_data : 1,
  141. mgmt_type : 1,
  142. ctrl_type : 1,
  143. more_data : 1,
  144. eosp : 1,
  145. a_msdu_error : 1,
  146. fragment_flag : 1,
  147. order : 1,
  148. cce_match : 1,
  149. overflow_err : 1,
  150. msdu_length_err : 1,
  151. tcp_udp_chksum_fail : 1,
  152. ip_chksum_fail : 1,
  153. sa_idx_invalid : 1,
  154. da_idx_invalid : 1,
  155. reserved_30b : 1,
  156. rx_in_tx_decrypt_byp : 1,
  157. encrypt_required : 1,
  158. directed : 1,
  159. buffer_fragment : 1,
  160. mpdu_length_err : 1,
  161. tkip_mic_err : 1,
  162. decrypt_err : 1,
  163. unencrypted_frame_err : 1,
  164. fcs_err : 1;
  165. uint32_t reserved_31a : 10,
  166. decrypt_status_code : 3,
  167. rx_bitmap_not_updated : 1,
  168. reserved_31b : 17,
  169. msdu_done : 1;
  170. };
  171. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
  172. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  173. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
  174. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
  175. #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
  176. #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2
  177. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8
  178. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
  179. #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000
  180. #define RX_MSDU_END_RESERVED_0_LSB 9
  181. #define RX_MSDU_END_RESERVED_0_MSB 15
  182. #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00
  183. #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
  184. #define RX_MSDU_END_PHY_PPDU_ID_LSB 16
  185. #define RX_MSDU_END_PHY_PPDU_ID_MSB 31
  186. #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
  187. #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000
  188. #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32
  189. #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47
  190. #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000
  191. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000
  192. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48
  193. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61
  194. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000
  195. #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000
  196. #define RX_MSDU_END_RESERVED_1A_LSB 62
  197. #define RX_MSDU_END_RESERVED_1A_MSB 63
  198. #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000
  199. #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000008
  200. #define RX_MSDU_END_KEY_ID_OCTET_LSB 0
  201. #define RX_MSDU_END_KEY_ID_OCTET_MSB 7
  202. #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff
  203. #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008
  204. #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8
  205. #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13
  206. #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00
  207. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008
  208. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
  209. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14
  210. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000
  211. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008
  212. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
  213. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15
  214. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000
  215. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008
  216. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16
  217. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31
  218. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000
  219. #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008
  220. #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32
  221. #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63
  222. #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000
  223. #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000010
  224. #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0
  225. #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31
  226. #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff
  227. #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010
  228. #define RX_MSDU_END_DA_OFFSET_LSB 32
  229. #define RX_MSDU_END_DA_OFFSET_MSB 37
  230. #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000
  231. #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010
  232. #define RX_MSDU_END_SA_OFFSET_LSB 38
  233. #define RX_MSDU_END_SA_OFFSET_MSB 43
  234. #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000
  235. #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010
  236. #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44
  237. #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44
  238. #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000
  239. #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010
  240. #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45
  241. #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45
  242. #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000
  243. #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010
  244. #define RX_MSDU_END_RESERVED_5A_LSB 46
  245. #define RX_MSDU_END_RESERVED_5A_MSB 47
  246. #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000
  247. #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010
  248. #define RX_MSDU_END_L3_TYPE_LSB 48
  249. #define RX_MSDU_END_L3_TYPE_MSB 63
  250. #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000
  251. #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000018
  252. #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0
  253. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31
  254. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff
  255. #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018
  256. #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32
  257. #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63
  258. #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000
  259. #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020
  260. #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0
  261. #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31
  262. #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff
  263. #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020
  264. #define RX_MSDU_END_TCP_FLAG_LSB 32
  265. #define RX_MSDU_END_TCP_FLAG_MSB 40
  266. #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000
  267. #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020
  268. #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41
  269. #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41
  270. #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000
  271. #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020
  272. #define RX_MSDU_END_RESERVED_9A_LSB 42
  273. #define RX_MSDU_END_RESERVED_9A_MSB 47
  274. #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000
  275. #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020
  276. #define RX_MSDU_END_WINDOW_SIZE_LSB 48
  277. #define RX_MSDU_END_WINDOW_SIZE_MSB 63
  278. #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000
  279. #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000028
  280. #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 0
  281. #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 15
  282. #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x000000000000ffff
  283. #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  284. #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16
  285. #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16
  286. #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000
  287. #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  288. #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17
  289. #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17
  290. #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000
  291. #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000028
  292. #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 18
  293. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 18
  294. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000000000040000
  295. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000028
  296. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 19
  297. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 19
  298. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000000000080000
  299. #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000028
  300. #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 20
  301. #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 20
  302. #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000000000100000
  303. #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000028
  304. #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 21
  305. #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 21
  306. #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000200000
  307. #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000028
  308. #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 22
  309. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 22
  310. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000000000400000
  311. #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028
  312. #define RX_MSDU_END_SA_IS_VALID_LSB 23
  313. #define RX_MSDU_END_SA_IS_VALID_MSB 23
  314. #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000
  315. #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028
  316. #define RX_MSDU_END_DA_IS_VALID_LSB 24
  317. #define RX_MSDU_END_DA_IS_VALID_MSB 24
  318. #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000
  319. #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028
  320. #define RX_MSDU_END_DA_IS_MCBC_LSB 25
  321. #define RX_MSDU_END_DA_IS_MCBC_MSB 25
  322. #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000
  323. #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028
  324. #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26
  325. #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27
  326. #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000
  327. #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028
  328. #define RX_MSDU_END_FIRST_MSDU_LSB 28
  329. #define RX_MSDU_END_FIRST_MSDU_MSB 28
  330. #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000
  331. #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028
  332. #define RX_MSDU_END_LAST_MSDU_LSB 29
  333. #define RX_MSDU_END_LAST_MSDU_MSB 29
  334. #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000
  335. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028
  336. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 30
  337. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 30
  338. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000000040000000
  339. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028
  340. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31
  341. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31
  342. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000
  343. #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028
  344. #define RX_MSDU_END_SA_IDX_LSB 32
  345. #define RX_MSDU_END_SA_IDX_MSB 47
  346. #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000
  347. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028
  348. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48
  349. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63
  350. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000
  351. #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030
  352. #define RX_MSDU_END_MSDU_DROP_LSB 0
  353. #define RX_MSDU_END_MSDU_DROP_MSB 0
  354. #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001
  355. #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030
  356. #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1
  357. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5
  358. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e
  359. #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030
  360. #define RX_MSDU_END_FLOW_IDX_LSB 6
  361. #define RX_MSDU_END_FLOW_IDX_MSB 25
  362. #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0
  363. #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030
  364. #define RX_MSDU_END_USE_PPE_LSB 26
  365. #define RX_MSDU_END_USE_PPE_MSB 26
  366. #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000
  367. #define RX_MSDU_END_RESERVED_12A_OFFSET 0x0000000000000030
  368. #define RX_MSDU_END_RESERVED_12A_LSB 27
  369. #define RX_MSDU_END_RESERVED_12A_MSB 31
  370. #define RX_MSDU_END_RESERVED_12A_MASK 0x00000000f8000000
  371. #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030
  372. #define RX_MSDU_END_FSE_METADATA_LSB 32
  373. #define RX_MSDU_END_FSE_METADATA_MSB 63
  374. #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000
  375. #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038
  376. #define RX_MSDU_END_CCE_METADATA_LSB 0
  377. #define RX_MSDU_END_CCE_METADATA_MSB 15
  378. #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff
  379. #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000038
  380. #define RX_MSDU_END_SA_SW_PEER_ID_LSB 16
  381. #define RX_MSDU_END_SA_SW_PEER_ID_MSB 31
  382. #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x00000000ffff0000
  383. #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038
  384. #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32
  385. #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39
  386. #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000
  387. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038
  388. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40
  389. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40
  390. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000
  391. #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038
  392. #define RX_MSDU_END_FISA_TIMEOUT_LSB 41
  393. #define RX_MSDU_END_FISA_TIMEOUT_MSB 41
  394. #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000
  395. #define RX_MSDU_END_RESERVED_15A_OFFSET 0x0000000000000038
  396. #define RX_MSDU_END_RESERVED_15A_LSB 42
  397. #define RX_MSDU_END_RESERVED_15A_MSB 63
  398. #define RX_MSDU_END_RESERVED_15A_MASK 0xfffffc0000000000
  399. #define RX_MSDU_END_CUMULATIVE_L4_CHECKSUM_OFFSET 0x0000000000000040
  400. #define RX_MSDU_END_CUMULATIVE_L4_CHECKSUM_LSB 0
  401. #define RX_MSDU_END_CUMULATIVE_L4_CHECKSUM_MSB 15
  402. #define RX_MSDU_END_CUMULATIVE_L4_CHECKSUM_MASK 0x000000000000ffff
  403. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000040
  404. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16
  405. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31
  406. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0x00000000ffff0000
  407. #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040
  408. #define RX_MSDU_END_RESERVED_17A_LSB 32
  409. #define RX_MSDU_END_RESERVED_17A_MSB 37
  410. #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000
  411. #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040
  412. #define RX_MSDU_END_SERVICE_CODE_LSB 38
  413. #define RX_MSDU_END_SERVICE_CODE_MSB 46
  414. #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000
  415. #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040
  416. #define RX_MSDU_END_PRIORITY_VALID_LSB 47
  417. #define RX_MSDU_END_PRIORITY_VALID_MSB 47
  418. #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000
  419. #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040
  420. #define RX_MSDU_END_INTRA_BSS_LSB 48
  421. #define RX_MSDU_END_INTRA_BSS_MSB 48
  422. #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000
  423. #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040
  424. #define RX_MSDU_END_DEST_CHIP_ID_LSB 49
  425. #define RX_MSDU_END_DEST_CHIP_ID_MSB 50
  426. #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000
  427. #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040
  428. #define RX_MSDU_END_MULTICAST_ECHO_LSB 51
  429. #define RX_MSDU_END_MULTICAST_ECHO_MSB 51
  430. #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000
  431. #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040
  432. #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52
  433. #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52
  434. #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000
  435. #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040
  436. #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53
  437. #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53
  438. #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000
  439. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040
  440. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54
  441. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54
  442. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000
  443. #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040
  444. #define RX_MSDU_END_RESERVED_17B_LSB 55
  445. #define RX_MSDU_END_RESERVED_17B_MSB 63
  446. #define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000
  447. #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048
  448. #define RX_MSDU_END_MSDU_LENGTH_LSB 0
  449. #define RX_MSDU_END_MSDU_LENGTH_MSB 13
  450. #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff
  451. #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048
  452. #define RX_MSDU_END_STBC_LSB 14
  453. #define RX_MSDU_END_STBC_MSB 14
  454. #define RX_MSDU_END_STBC_MASK 0x0000000000004000
  455. #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048
  456. #define RX_MSDU_END_IPSEC_ESP_LSB 15
  457. #define RX_MSDU_END_IPSEC_ESP_MSB 15
  458. #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000
  459. #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048
  460. #define RX_MSDU_END_L3_OFFSET_LSB 16
  461. #define RX_MSDU_END_L3_OFFSET_MSB 22
  462. #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000
  463. #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048
  464. #define RX_MSDU_END_IPSEC_AH_LSB 23
  465. #define RX_MSDU_END_IPSEC_AH_MSB 23
  466. #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000
  467. #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048
  468. #define RX_MSDU_END_L4_OFFSET_LSB 24
  469. #define RX_MSDU_END_L4_OFFSET_MSB 31
  470. #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000
  471. #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048
  472. #define RX_MSDU_END_MSDU_NUMBER_LSB 32
  473. #define RX_MSDU_END_MSDU_NUMBER_MSB 39
  474. #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000
  475. #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048
  476. #define RX_MSDU_END_DECAP_FORMAT_LSB 40
  477. #define RX_MSDU_END_DECAP_FORMAT_MSB 41
  478. #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000
  479. #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048
  480. #define RX_MSDU_END_IPV4_PROTO_LSB 42
  481. #define RX_MSDU_END_IPV4_PROTO_MSB 42
  482. #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000
  483. #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048
  484. #define RX_MSDU_END_IPV6_PROTO_LSB 43
  485. #define RX_MSDU_END_IPV6_PROTO_MSB 43
  486. #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000
  487. #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048
  488. #define RX_MSDU_END_TCP_PROTO_LSB 44
  489. #define RX_MSDU_END_TCP_PROTO_MSB 44
  490. #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000
  491. #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048
  492. #define RX_MSDU_END_UDP_PROTO_LSB 45
  493. #define RX_MSDU_END_UDP_PROTO_MSB 45
  494. #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000
  495. #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048
  496. #define RX_MSDU_END_IP_FRAG_LSB 46
  497. #define RX_MSDU_END_IP_FRAG_MSB 46
  498. #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000
  499. #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048
  500. #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47
  501. #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47
  502. #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000
  503. #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048
  504. #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48
  505. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48
  506. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000
  507. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048
  508. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49
  509. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50
  510. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000
  511. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048
  512. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51
  513. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51
  514. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000
  515. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048
  516. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52
  517. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52
  518. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000
  519. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048
  520. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53
  521. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53
  522. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000
  523. #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048
  524. #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54
  525. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54
  526. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000
  527. #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048
  528. #define RX_MSDU_END_LDPC_LSB 55
  529. #define RX_MSDU_END_LDPC_MSB 55
  530. #define RX_MSDU_END_LDPC_MASK 0x0080000000000000
  531. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048
  532. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56
  533. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63
  534. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000
  535. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000050
  536. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0
  537. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31
  538. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0x00000000ffffffff
  539. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000050
  540. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32
  541. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63
  542. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000
  543. #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058
  544. #define RX_MSDU_END_USER_RSSI_LSB 0
  545. #define RX_MSDU_END_USER_RSSI_MSB 7
  546. #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff
  547. #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058
  548. #define RX_MSDU_END_PKT_TYPE_LSB 8
  549. #define RX_MSDU_END_PKT_TYPE_MSB 11
  550. #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00
  551. #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058
  552. #define RX_MSDU_END_SGI_LSB 12
  553. #define RX_MSDU_END_SGI_MSB 13
  554. #define RX_MSDU_END_SGI_MASK 0x0000000000003000
  555. #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058
  556. #define RX_MSDU_END_RATE_MCS_LSB 14
  557. #define RX_MSDU_END_RATE_MCS_MSB 17
  558. #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000
  559. #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058
  560. #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18
  561. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20
  562. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000
  563. #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058
  564. #define RX_MSDU_END_RECEPTION_TYPE_LSB 21
  565. #define RX_MSDU_END_RECEPTION_TYPE_MSB 23
  566. #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000
  567. #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058
  568. #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24
  569. #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 31
  570. #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x00000000ff000000
  571. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000058
  572. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 32
  573. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 63
  574. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000
  575. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060
  576. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0
  577. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31
  578. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff
  579. #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060
  580. #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32
  581. #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63
  582. #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000
  583. #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000068
  584. #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0
  585. #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15
  586. #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff
  587. #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000068
  588. #define RX_MSDU_END_VLAN_STAG_CI_LSB 16
  589. #define RX_MSDU_END_VLAN_STAG_CI_MSB 31
  590. #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000
  591. #define RX_MSDU_END_RESERVED_27A_OFFSET 0x0000000000000068
  592. #define RX_MSDU_END_RESERVED_27A_LSB 32
  593. #define RX_MSDU_END_RESERVED_27A_MSB 63
  594. #define RX_MSDU_END_RESERVED_27A_MASK 0xffffffff00000000
  595. #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070
  596. #define RX_MSDU_END_RESERVED_28A_LSB 0
  597. #define RX_MSDU_END_RESERVED_28A_MSB 31
  598. #define RX_MSDU_END_RESERVED_28A_MASK 0x00000000ffffffff
  599. #define RX_MSDU_END_RESERVED_29A_OFFSET 0x0000000000000070
  600. #define RX_MSDU_END_RESERVED_29A_LSB 32
  601. #define RX_MSDU_END_RESERVED_29A_MSB 63
  602. #define RX_MSDU_END_RESERVED_29A_MASK 0xffffffff00000000
  603. #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078
  604. #define RX_MSDU_END_FIRST_MPDU_LSB 0
  605. #define RX_MSDU_END_FIRST_MPDU_MSB 0
  606. #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001
  607. #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078
  608. #define RX_MSDU_END_RESERVED_30A_LSB 1
  609. #define RX_MSDU_END_RESERVED_30A_MSB 1
  610. #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002
  611. #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078
  612. #define RX_MSDU_END_MCAST_BCAST_LSB 2
  613. #define RX_MSDU_END_MCAST_BCAST_MSB 2
  614. #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004
  615. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078
  616. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3
  617. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3
  618. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008
  619. #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078
  620. #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4
  621. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4
  622. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010
  623. #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078
  624. #define RX_MSDU_END_POWER_MGMT_LSB 5
  625. #define RX_MSDU_END_POWER_MGMT_MSB 5
  626. #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020
  627. #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078
  628. #define RX_MSDU_END_NON_QOS_LSB 6
  629. #define RX_MSDU_END_NON_QOS_MSB 6
  630. #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040
  631. #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078
  632. #define RX_MSDU_END_NULL_DATA_LSB 7
  633. #define RX_MSDU_END_NULL_DATA_MSB 7
  634. #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080
  635. #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078
  636. #define RX_MSDU_END_MGMT_TYPE_LSB 8
  637. #define RX_MSDU_END_MGMT_TYPE_MSB 8
  638. #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100
  639. #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078
  640. #define RX_MSDU_END_CTRL_TYPE_LSB 9
  641. #define RX_MSDU_END_CTRL_TYPE_MSB 9
  642. #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200
  643. #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078
  644. #define RX_MSDU_END_MORE_DATA_LSB 10
  645. #define RX_MSDU_END_MORE_DATA_MSB 10
  646. #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400
  647. #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078
  648. #define RX_MSDU_END_EOSP_LSB 11
  649. #define RX_MSDU_END_EOSP_MSB 11
  650. #define RX_MSDU_END_EOSP_MASK 0x0000000000000800
  651. #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078
  652. #define RX_MSDU_END_A_MSDU_ERROR_LSB 12
  653. #define RX_MSDU_END_A_MSDU_ERROR_MSB 12
  654. #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000
  655. #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000078
  656. #define RX_MSDU_END_FRAGMENT_FLAG_LSB 13
  657. #define RX_MSDU_END_FRAGMENT_FLAG_MSB 13
  658. #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000000002000
  659. #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078
  660. #define RX_MSDU_END_ORDER_LSB 14
  661. #define RX_MSDU_END_ORDER_MSB 14
  662. #define RX_MSDU_END_ORDER_MASK 0x0000000000004000
  663. #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000078
  664. #define RX_MSDU_END_CCE_MATCH_LSB 15
  665. #define RX_MSDU_END_CCE_MATCH_MSB 15
  666. #define RX_MSDU_END_CCE_MATCH_MASK 0x0000000000008000
  667. #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078
  668. #define RX_MSDU_END_OVERFLOW_ERR_LSB 16
  669. #define RX_MSDU_END_OVERFLOW_ERR_MSB 16
  670. #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000
  671. #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078
  672. #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17
  673. #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17
  674. #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000
  675. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  676. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18
  677. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18
  678. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000
  679. #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  680. #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19
  681. #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19
  682. #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000
  683. #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078
  684. #define RX_MSDU_END_SA_IDX_INVALID_LSB 20
  685. #define RX_MSDU_END_SA_IDX_INVALID_MSB 20
  686. #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000
  687. #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078
  688. #define RX_MSDU_END_DA_IDX_INVALID_LSB 21
  689. #define RX_MSDU_END_DA_IDX_INVALID_MSB 21
  690. #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000
  691. #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078
  692. #define RX_MSDU_END_RESERVED_30B_LSB 22
  693. #define RX_MSDU_END_RESERVED_30B_MSB 22
  694. #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000400000
  695. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078
  696. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23
  697. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23
  698. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000
  699. #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078
  700. #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24
  701. #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24
  702. #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000
  703. #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078
  704. #define RX_MSDU_END_DIRECTED_LSB 25
  705. #define RX_MSDU_END_DIRECTED_MSB 25
  706. #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000
  707. #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078
  708. #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26
  709. #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26
  710. #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000
  711. #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078
  712. #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27
  713. #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27
  714. #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000
  715. #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078
  716. #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28
  717. #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28
  718. #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000
  719. #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078
  720. #define RX_MSDU_END_DECRYPT_ERR_LSB 29
  721. #define RX_MSDU_END_DECRYPT_ERR_MSB 29
  722. #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000
  723. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078
  724. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30
  725. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30
  726. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000
  727. #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078
  728. #define RX_MSDU_END_FCS_ERR_LSB 31
  729. #define RX_MSDU_END_FCS_ERR_MSB 31
  730. #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000
  731. #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078
  732. #define RX_MSDU_END_RESERVED_31A_LSB 32
  733. #define RX_MSDU_END_RESERVED_31A_MSB 41
  734. #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000
  735. #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078
  736. #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42
  737. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44
  738. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000
  739. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078
  740. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45
  741. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45
  742. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000
  743. #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078
  744. #define RX_MSDU_END_RESERVED_31B_LSB 46
  745. #define RX_MSDU_END_RESERVED_31B_MSB 62
  746. #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000
  747. #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078
  748. #define RX_MSDU_END_MSDU_DONE_LSB 63
  749. #define RX_MSDU_END_MSDU_DONE_MSB 63
  750. #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000
  751. #endif