a855ce2006
Bring in E3.R38 HW header files for kiwi, as the final set of header files from emulation drop. In addition cleanup header files w.r.t comments, add appropriate copyright header. Change-Id: I3cee05e506c4171f8641193a0f12456f5cfaf890 CRs-Fixed: 2850521
282 sor
11 KiB
C
282 sor
11 KiB
C
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __MSMHWIOBASE_H__
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#define __MSMHWIOBASE_H__
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#define WCSS_WCSS_BASE 0x00000000
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#define WCSS_WCSS_BASE_SIZE 0x01000000
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#define WCSS_WCSS_BASE_PHYS 0x00000000
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#define QDSS_STM_SIZE_BASE 0x00100000
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#define QDSS_STM_SIZE_BASE_SIZE 0x100000000
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#define QDSS_STM_SIZE_BASE_PHYS 0x00100000
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#define BOOT_ROM_SIZE_BASE 0x00200000
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#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
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#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000
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#define SYSTEM_IRAM_SIZE_BASE 0x00400000
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#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
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#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
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#define BOOT_ROM_START_ADDRESS_BASE 0x01200000
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#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
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#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000
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#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff
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#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
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#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff
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#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
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#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
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#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
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#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
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#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
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#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
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#define QDSS_STM_BASE 0x01800000
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#define QDSS_STM_BASE_SIZE 0x100000000
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#define QDSS_STM_BASE_PHYS 0x01800000
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#define QDSS_STM_END_BASE 0x018fffff
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#define QDSS_STM_END_BASE_SIZE 0x100000000
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#define QDSS_STM_END_BASE_PHYS 0x018fffff
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#define TLMM_BASE 0x01900000
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#define TLMM_BASE_SIZE 0x00200000
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#define TLMM_BASE_PHYS 0x01900000
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#define CORE_TOP_CSR_BASE 0x01b00000
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#define CORE_TOP_CSR_BASE_SIZE 0x00040000
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#define CORE_TOP_CSR_BASE_PHYS 0x01b00000
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#define BLSP1_BLSP_BASE 0x01b40000
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#define BLSP1_BLSP_BASE_SIZE 0x00040000
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#define BLSP1_BLSP_BASE_PHYS 0x01b40000
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#define SOC_WFSS_CE_REG_BASE 0x01b80000
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#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
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#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
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#define WL_TLMM_BASE 0x01bc0000
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#define WL_TLMM_BASE_SIZE 0x00020000
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#define WL_TLMM_BASE_PHYS 0x01bc0000
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#define MEMSS_CSR_BASE 0x01be0000
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#define MEMSS_CSR_BASE_SIZE 0x0000001c
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#define MEMSS_CSR_BASE_PHYS 0x01be0000
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#define TSENS_SROT_BASE 0x01bf0000
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#define TSENS_SROT_BASE_SIZE 0x00001000
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#define TSENS_SROT_BASE_PHYS 0x01bf0000
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#define TSENS_TM_BASE 0x01bf1000
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#define TSENS_TM_BASE_SIZE 0x00001000
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#define TSENS_TM_BASE_PHYS 0x01bf1000
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#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
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#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
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#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
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#define QDSS_WRAPPER_TOP_BASE 0x01c80000
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#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
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#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000
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#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000
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#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000
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#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000
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#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
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#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
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#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
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#define SECURITY_CONTROL_WLAN_BASE 0x01e20000
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#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
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#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
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#define EDPD_CAL_ACC_BASE 0x01e28000
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#define EDPD_CAL_ACC_BASE_SIZE 0x00003000
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#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000
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#define CPR_CX_CPR3_BASE 0x01e30000
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#define CPR_CX_CPR3_BASE_SIZE 0x00004000
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#define CPR_CX_CPR3_BASE_PHYS 0x01e30000
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#define CPR_MX_CPR3_BASE 0x01e34000
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#define CPR_MX_CPR3_BASE_SIZE 0x00004000
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#define CPR_MX_CPR3_BASE_PHYS 0x01e34000
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#define GCC_GCC_BASE 0x01e40000
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#define GCC_GCC_BASE_SIZE 0x000003e8
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#define GCC_GCC_BASE_PHYS 0x01e40000
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#define PRNG_PRNG_TOP_BASE 0x01e50000
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#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
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#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
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#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
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#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
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#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
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#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
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#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
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#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
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#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
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#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
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#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
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#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
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#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
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#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
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#define RRI_PREFETCH_REG_BASE 0x01e70000
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#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000
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#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
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#define SYSTEM_NOC_BASE 0x01e80000
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#define SYSTEM_NOC_BASE_SIZE 0x0000a000
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#define SYSTEM_NOC_BASE_PHYS 0x01e80000
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#define PC_NOC_BASE 0x01f00000
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#define PC_NOC_BASE_SIZE 0x00003880
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#define PC_NOC_BASE_PHYS 0x01f00000
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#define WLAON_WL_AON_REG_BASE 0x01f80000
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#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8
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#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
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#define SYSPM_SYSPM_REG_BASE 0x01f82000
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#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
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#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
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#define PMU_WLAN_PMU_TOP_BASE 0x01f88000
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#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340
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#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
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#define PMU_NOC_BASE 0x01f8a000
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#define PMU_NOC_BASE_SIZE 0x00000080
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#define PMU_NOC_BASE_PHYS 0x01f8a000
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#define PCIE_ATU_REGION_BASE 0x04000000
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#define PCIE_ATU_REGION_BASE_SIZE 0x100000000
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#define PCIE_ATU_REGION_BASE_PHYS 0x04000000
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#define PCIE_ATU_REGION_SIZE_BASE 0x40000000
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#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
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#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
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#define PCIE_ATU_REGION_END_BASE 0x43ffffff
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#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
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#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
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#endif
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