qmi.c 108 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define CONN_ROAM_FILE_NAME "wlan-connection-roaming"
  28. #define INI_EXT ".ini"
  29. #define INI_FILE_NAME_LEN 100
  30. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  31. /*
  32. * Download QDSS config file based on build type. Add build type string to
  33. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  34. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  35. */
  36. #ifdef CONFIG_CNSS2_DEBUG
  37. #define QDSS_FILE_BUILD_STR "debug_"
  38. #else
  39. #define QDSS_FILE_BUILD_STR "perf_"
  40. #endif
  41. #define HW_V1_NUMBER "v1"
  42. #define HW_V2_NUMBER "v2"
  43. #define CE_MSI_NAME "CE"
  44. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  45. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  46. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  47. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  48. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  49. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  50. #define DMS_QMI_MAX_MSG_LEN SZ_256
  51. #define MAX_SHADOW_REG_RESERVED 2
  52. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  53. MAX_SHADOW_REG_RESERVED)
  54. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  55. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  173. wlfw_ind_register_resp_msg_v01_ei, resp);
  174. if (ret < 0) {
  175. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  176. ret);
  177. goto out;
  178. }
  179. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  180. QMI_WLFW_IND_REGISTER_REQ_V01,
  181. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  182. wlfw_ind_register_req_msg_v01_ei, req);
  183. if (ret < 0) {
  184. qmi_txn_cancel(&txn);
  185. cnss_pr_err("Failed to send indication register request, err: %d\n",
  186. ret);
  187. goto out;
  188. }
  189. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  190. if (ret < 0) {
  191. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  192. ret);
  193. goto out;
  194. }
  195. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  196. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  197. resp->resp.result, resp->resp.error);
  198. ret = -resp->resp.result;
  199. goto out;
  200. }
  201. if (resp->fw_status_valid) {
  202. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  203. ret = -EALREADY;
  204. goto qmi_registered;
  205. }
  206. }
  207. kfree(req);
  208. kfree(resp);
  209. return 0;
  210. out:
  211. CNSS_QMI_ASSERT();
  212. qmi_registered:
  213. kfree(req);
  214. kfree(resp);
  215. return ret;
  216. }
  217. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  218. struct wlfw_host_cap_req_msg_v01 *req)
  219. {
  220. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  221. plat_priv->device_id == MANGO_DEVICE_ID ||
  222. plat_priv->device_id == PEACH_DEVICE_ID) {
  223. req->mlo_capable_valid = 1;
  224. req->mlo_capable = 1;
  225. req->mlo_chip_id_valid = 1;
  226. req->mlo_chip_id = 0;
  227. req->mlo_group_id_valid = 1;
  228. req->mlo_group_id = 0;
  229. req->max_mlo_peer_valid = 1;
  230. /* Max peer number generally won't change for the same device
  231. * but needs to be synced with host driver.
  232. */
  233. req->max_mlo_peer = 32;
  234. req->mlo_num_chips_valid = 1;
  235. req->mlo_num_chips = 1;
  236. req->mlo_chip_info_valid = 1;
  237. req->mlo_chip_info[0].chip_id = 0;
  238. req->mlo_chip_info[0].num_local_links = 2;
  239. req->mlo_chip_info[0].hw_link_id[0] = 0;
  240. req->mlo_chip_info[0].hw_link_id[1] = 1;
  241. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  242. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  243. }
  244. }
  245. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  246. {
  247. struct wlfw_host_cap_req_msg_v01 *req;
  248. struct wlfw_host_cap_resp_msg_v01 *resp;
  249. struct qmi_txn txn;
  250. int ret = 0;
  251. u64 iova_start = 0, iova_size = 0,
  252. iova_ipa_start = 0, iova_ipa_size = 0;
  253. u64 feature_list = 0;
  254. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  255. plat_priv->driver_state);
  256. req = kzalloc(sizeof(*req), GFP_KERNEL);
  257. if (!req)
  258. return -ENOMEM;
  259. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  260. if (!resp) {
  261. kfree(req);
  262. return -ENOMEM;
  263. }
  264. req->num_clients_valid = 1;
  265. req->num_clients = 1;
  266. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  267. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  268. if (req->wake_msi) {
  269. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  270. req->wake_msi_valid = 1;
  271. }
  272. req->bdf_support_valid = 1;
  273. req->bdf_support = 1;
  274. req->m3_support_valid = 1;
  275. req->m3_support = 1;
  276. req->m3_cache_support_valid = 1;
  277. req->m3_cache_support = 1;
  278. req->cal_done_valid = 1;
  279. req->cal_done = plat_priv->cal_done;
  280. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  281. if (plat_priv->sleep_clk) {
  282. req->nm_modem_valid = 1;
  283. /* Notify firmware about the sleep clock selection,
  284. * nm_modem_bit[1] is used for this purpose.
  285. */
  286. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  287. }
  288. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  289. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  290. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  291. &iova_ipa_size)) {
  292. req->ddr_range_valid = 1;
  293. req->ddr_range[0].start = iova_start;
  294. req->ddr_range[0].size = iova_size + iova_ipa_size;
  295. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  296. req->ddr_range[0].start, req->ddr_range[0].size);
  297. }
  298. req->host_build_type_valid = 1;
  299. req->host_build_type = cnss_get_host_build_type();
  300. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  301. ret = cnss_get_feature_list(plat_priv, &feature_list);
  302. if (!ret) {
  303. req->feature_list_valid = 1;
  304. req->feature_list = feature_list;
  305. cnss_pr_dbg("Sending feature list 0x%llx\n",
  306. req->feature_list);
  307. }
  308. if (cnss_get_platform_name(plat_priv, req->platform_name,
  309. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  310. req->platform_name_valid = 1;
  311. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  312. wlfw_host_cap_resp_msg_v01_ei, resp);
  313. if (ret < 0) {
  314. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  315. ret);
  316. goto out;
  317. }
  318. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  319. QMI_WLFW_HOST_CAP_REQ_V01,
  320. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  321. wlfw_host_cap_req_msg_v01_ei, req);
  322. if (ret < 0) {
  323. qmi_txn_cancel(&txn);
  324. cnss_pr_err("Failed to send host capability request, err: %d\n",
  325. ret);
  326. goto out;
  327. }
  328. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  329. if (ret < 0) {
  330. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  331. ret);
  332. goto out;
  333. }
  334. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  335. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  336. resp->resp.result, resp->resp.error);
  337. ret = -resp->resp.result;
  338. goto out;
  339. }
  340. kfree(req);
  341. kfree(resp);
  342. return 0;
  343. out:
  344. CNSS_QMI_ASSERT();
  345. kfree(req);
  346. kfree(resp);
  347. return ret;
  348. }
  349. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  350. {
  351. struct wlfw_respond_mem_req_msg_v01 *req;
  352. struct wlfw_respond_mem_resp_msg_v01 *resp;
  353. struct qmi_txn txn;
  354. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  355. int ret = 0, i;
  356. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  357. plat_priv->driver_state);
  358. req = kzalloc(sizeof(*req), GFP_KERNEL);
  359. if (!req)
  360. return -ENOMEM;
  361. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  362. if (!resp) {
  363. kfree(req);
  364. return -ENOMEM;
  365. }
  366. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  367. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  368. ret = -EINVAL;
  369. goto out;
  370. }
  371. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  372. for (i = 0; i < req->mem_seg_len; i++) {
  373. if (!fw_mem[i].pa || !fw_mem[i].size) {
  374. if (fw_mem[i].type == 0) {
  375. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  376. i);
  377. ret = -EINVAL;
  378. goto out;
  379. }
  380. cnss_pr_err("Memory for FW is not available for type: %u\n",
  381. fw_mem[i].type);
  382. ret = -ENOMEM;
  383. goto out;
  384. }
  385. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  386. fw_mem[i].va, &fw_mem[i].pa,
  387. fw_mem[i].size, fw_mem[i].type);
  388. req->mem_seg[i].addr = fw_mem[i].pa;
  389. req->mem_seg[i].size = fw_mem[i].size;
  390. req->mem_seg[i].type = fw_mem[i].type;
  391. }
  392. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  393. wlfw_respond_mem_resp_msg_v01_ei, resp);
  394. if (ret < 0) {
  395. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  396. ret);
  397. goto out;
  398. }
  399. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  400. QMI_WLFW_RESPOND_MEM_REQ_V01,
  401. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  402. wlfw_respond_mem_req_msg_v01_ei, req);
  403. if (ret < 0) {
  404. qmi_txn_cancel(&txn);
  405. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  406. ret);
  407. goto out;
  408. }
  409. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  410. if (ret < 0) {
  411. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  412. ret);
  413. goto out;
  414. }
  415. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  416. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  417. resp->resp.result, resp->resp.error);
  418. ret = -resp->resp.result;
  419. goto out;
  420. }
  421. kfree(req);
  422. kfree(resp);
  423. return 0;
  424. out:
  425. CNSS_QMI_ASSERT();
  426. kfree(req);
  427. kfree(resp);
  428. return ret;
  429. }
  430. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  431. {
  432. struct wlfw_cap_req_msg_v01 *req;
  433. struct wlfw_cap_resp_msg_v01 *resp;
  434. struct qmi_txn txn;
  435. char *fw_build_timestamp;
  436. int ret = 0, i;
  437. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  438. plat_priv->driver_state);
  439. req = kzalloc(sizeof(*req), GFP_KERNEL);
  440. if (!req)
  441. return -ENOMEM;
  442. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  443. if (!resp) {
  444. kfree(req);
  445. return -ENOMEM;
  446. }
  447. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  448. wlfw_cap_resp_msg_v01_ei, resp);
  449. if (ret < 0) {
  450. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  451. ret);
  452. goto out;
  453. }
  454. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  455. QMI_WLFW_CAP_REQ_V01,
  456. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  457. wlfw_cap_req_msg_v01_ei, req);
  458. if (ret < 0) {
  459. qmi_txn_cancel(&txn);
  460. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  461. ret);
  462. goto out;
  463. }
  464. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  465. if (ret < 0) {
  466. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  467. ret);
  468. goto out;
  469. }
  470. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  471. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  472. resp->resp.result, resp->resp.error);
  473. ret = -resp->resp.result;
  474. goto out;
  475. }
  476. if (resp->chip_info_valid) {
  477. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  478. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  479. }
  480. if (resp->board_info_valid)
  481. plat_priv->board_info.board_id = resp->board_info.board_id;
  482. else
  483. plat_priv->board_info.board_id = 0xFF;
  484. if (resp->soc_info_valid)
  485. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  486. if (resp->fw_version_info_valid) {
  487. plat_priv->fw_version_info.fw_version =
  488. resp->fw_version_info.fw_version;
  489. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  490. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  491. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  492. resp->fw_version_info.fw_build_timestamp,
  493. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  494. }
  495. if (resp->fw_build_id_valid) {
  496. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  497. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  498. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  499. }
  500. /* FW will send aop retention volatage for qca6490 */
  501. if (resp->voltage_mv_valid) {
  502. plat_priv->cpr_info.voltage = resp->voltage_mv;
  503. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  504. plat_priv->cpr_info.voltage);
  505. cnss_update_cpr_info(plat_priv);
  506. }
  507. if (resp->time_freq_hz_valid) {
  508. plat_priv->device_freq_hz = resp->time_freq_hz;
  509. cnss_pr_dbg("Device frequency is %d HZ\n",
  510. plat_priv->device_freq_hz);
  511. }
  512. if (resp->otp_version_valid)
  513. plat_priv->otp_version = resp->otp_version;
  514. if (resp->dev_mem_info_valid) {
  515. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  516. plat_priv->dev_mem_info[i].start =
  517. resp->dev_mem_info[i].start;
  518. plat_priv->dev_mem_info[i].size =
  519. resp->dev_mem_info[i].size;
  520. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  521. i, plat_priv->dev_mem_info[i].start,
  522. plat_priv->dev_mem_info[i].size);
  523. }
  524. }
  525. if (resp->fw_caps_valid) {
  526. plat_priv->fw_pcie_gen_switch =
  527. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  528. plat_priv->fw_aux_uc_support =
  529. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  530. cnss_pr_dbg("FW aux uc support capability: %d\n",
  531. plat_priv->fw_aux_uc_support);
  532. plat_priv->fw_caps = resp->fw_caps;
  533. }
  534. if (resp->hang_data_length_valid &&
  535. resp->hang_data_length &&
  536. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  537. plat_priv->hang_event_data_len = resp->hang_data_length;
  538. else
  539. plat_priv->hang_event_data_len = 0;
  540. if (resp->hang_data_addr_offset_valid)
  541. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  542. else
  543. plat_priv->hang_data_addr_offset = 0;
  544. if (resp->hwid_bitmap_valid)
  545. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  546. if (resp->ol_cpr_cfg_valid)
  547. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  548. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  549. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  550. **/
  551. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  552. if (plat_priv->board_info.board_id ==
  553. plat_priv->on_chip_pmic_board_ids[i]) {
  554. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  555. plat_priv->board_info.board_id);
  556. ret = cnss_aop_send_msg(plat_priv,
  557. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  558. if (ret < 0)
  559. cnss_pr_dbg("Failed to Send AOP Msg");
  560. break;
  561. }
  562. }
  563. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  564. plat_priv->chip_info.chip_id,
  565. plat_priv->chip_info.chip_family,
  566. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  567. plat_priv->otp_version);
  568. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  569. plat_priv->fw_version_info.fw_version,
  570. plat_priv->fw_version_info.fw_build_timestamp,
  571. plat_priv->fw_build_id,
  572. plat_priv->hwid_bitmap);
  573. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  574. plat_priv->hang_event_data_len,
  575. plat_priv->hang_data_addr_offset);
  576. kfree(req);
  577. kfree(resp);
  578. return 0;
  579. out:
  580. CNSS_QMI_ASSERT();
  581. kfree(req);
  582. kfree(resp);
  583. return ret;
  584. }
  585. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  586. {
  587. switch (bdf_type) {
  588. case CNSS_BDF_BIN:
  589. case CNSS_BDF_ELF:
  590. return "BDF";
  591. case CNSS_BDF_REGDB:
  592. return "REGDB";
  593. case CNSS_BDF_HDS:
  594. return "HDS";
  595. default:
  596. return "UNKNOWN";
  597. }
  598. }
  599. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  600. u32 bdf_type, char *filename,
  601. u32 filename_len)
  602. {
  603. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  604. int ret = 0;
  605. switch (bdf_type) {
  606. case CNSS_BDF_ELF:
  607. /* Board ID will be equal or less than 0xFF in GF mask case */
  608. if (plat_priv->board_info.board_id == 0xFF) {
  609. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  610. snprintf(filename_tmp, filename_len,
  611. ELF_BDF_FILE_NAME_GF);
  612. else
  613. snprintf(filename_tmp, filename_len,
  614. ELF_BDF_FILE_NAME);
  615. } else if (plat_priv->board_info.board_id < 0xFF) {
  616. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  617. snprintf(filename_tmp, filename_len,
  618. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  619. plat_priv->board_info.board_id);
  620. else
  621. snprintf(filename_tmp, filename_len,
  622. ELF_BDF_FILE_NAME_PREFIX "%02x",
  623. plat_priv->board_info.board_id);
  624. } else {
  625. snprintf(filename_tmp, filename_len,
  626. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  627. plat_priv->board_info.board_id >> 8 & 0xFF,
  628. plat_priv->board_info.board_id & 0xFF);
  629. }
  630. break;
  631. case CNSS_BDF_BIN:
  632. if (plat_priv->board_info.board_id == 0xFF) {
  633. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  634. snprintf(filename_tmp, filename_len,
  635. BIN_BDF_FILE_NAME_GF);
  636. else
  637. snprintf(filename_tmp, filename_len,
  638. BIN_BDF_FILE_NAME);
  639. } else if (plat_priv->board_info.board_id < 0xFF) {
  640. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  641. snprintf(filename_tmp, filename_len,
  642. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  643. plat_priv->board_info.board_id);
  644. else
  645. snprintf(filename_tmp, filename_len,
  646. BIN_BDF_FILE_NAME_PREFIX "%02x",
  647. plat_priv->board_info.board_id);
  648. } else {
  649. snprintf(filename_tmp, filename_len,
  650. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  651. plat_priv->board_info.board_id >> 8 & 0xFF,
  652. plat_priv->board_info.board_id & 0xFF);
  653. }
  654. break;
  655. case CNSS_BDF_REGDB:
  656. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  657. break;
  658. case CNSS_BDF_HDS:
  659. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  660. break;
  661. default:
  662. cnss_pr_err("Invalid BDF type: %d\n",
  663. plat_priv->ctrl_params.bdf_type);
  664. ret = -EINVAL;
  665. break;
  666. }
  667. if (!ret)
  668. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  669. return ret;
  670. }
  671. int cnss_wlfw_ini_file_send_sync(struct cnss_plat_data *plat_priv,
  672. enum wlfw_ini_file_type_v01 file_type)
  673. {
  674. struct wlfw_ini_file_download_req_msg_v01 *req;
  675. struct wlfw_ini_file_download_resp_msg_v01 *resp;
  676. struct qmi_txn txn;
  677. int ret = 0;
  678. const struct firmware *fw;
  679. char filename[INI_FILE_NAME_LEN] = {0};
  680. char tmp_filename[INI_FILE_NAME_LEN] = {0};
  681. const u8 *temp;
  682. unsigned int remaining;
  683. bool backup_supported = false;
  684. req = kzalloc(sizeof(*req), GFP_KERNEL);
  685. if (!req)
  686. return -ENOMEM;
  687. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  688. if (!resp) {
  689. kfree(req);
  690. return -ENOMEM;
  691. }
  692. switch (file_type) {
  693. case WLFW_CONN_ROAM_INI_V01:
  694. snprintf(tmp_filename, sizeof(tmp_filename),
  695. CONN_ROAM_FILE_NAME);
  696. backup_supported = true;
  697. break;
  698. default:
  699. cnss_pr_err("Invalid file type: %u\n", file_type);
  700. ret = -EINVAL;
  701. goto err_req_fw;
  702. }
  703. snprintf(filename, sizeof(filename), "%s%s", tmp_filename, INI_EXT);
  704. /* Fetch the file */
  705. ret = firmware_request_nowarn(&fw, filename, &plat_priv->plat_dev->dev);
  706. if (ret) {
  707. if (!backup_supported)
  708. goto err_req_fw;
  709. snprintf(filename, sizeof(filename),
  710. "%s-%s%s", tmp_filename, "backup", INI_EXT);
  711. ret = firmware_request_nowarn(&fw, filename,
  712. &plat_priv->plat_dev->dev);
  713. if (ret)
  714. goto err_req_fw;
  715. }
  716. temp = fw->data;
  717. remaining = fw->size;
  718. cnss_pr_dbg("Downloading INI file: %s, size: %u\n", filename,
  719. remaining);
  720. while (remaining) {
  721. req->file_type_valid = 1;
  722. req->file_type = file_type;
  723. req->total_size_valid = 1;
  724. req->total_size = remaining;
  725. req->seg_id_valid = 1;
  726. req->data_valid = 1;
  727. req->end_valid = 1;
  728. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  729. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  730. } else {
  731. req->data_len = remaining;
  732. req->end = 1;
  733. }
  734. memcpy(req->data, temp, req->data_len);
  735. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  736. wlfw_ini_file_download_resp_msg_v01_ei,
  737. resp);
  738. if (ret < 0) {
  739. cnss_pr_err("Failed to initialize txn for INI file download request, err: %d\n",
  740. ret);
  741. goto err;
  742. }
  743. ret = qmi_send_request
  744. (&plat_priv->qmi_wlfw, NULL, &txn,
  745. QMI_WLFW_INI_FILE_DOWNLOAD_REQ_V01,
  746. WLFW_INI_FILE_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  747. wlfw_ini_file_download_req_msg_v01_ei, req);
  748. if (ret < 0) {
  749. qmi_txn_cancel(&txn);
  750. cnss_pr_err("Failed to send INI File download request, err: %d\n",
  751. ret);
  752. goto err;
  753. }
  754. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  755. if (ret < 0) {
  756. cnss_pr_err("Failed to wait for response of INI File download request, err: %d\n",
  757. ret);
  758. goto err;
  759. }
  760. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  761. cnss_pr_err("INI file download request failed, result: %d, err: %d\n",
  762. resp->resp.result, resp->resp.error);
  763. ret = -resp->resp.result;
  764. goto err;
  765. }
  766. remaining -= req->data_len;
  767. temp += req->data_len;
  768. req->seg_id++;
  769. }
  770. release_firmware(fw);
  771. kfree(req);
  772. kfree(resp);
  773. return 0;
  774. err:
  775. release_firmware(fw);
  776. err_req_fw:
  777. kfree(req);
  778. kfree(resp);
  779. return ret;
  780. }
  781. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  782. u32 bdf_type)
  783. {
  784. struct wlfw_bdf_download_req_msg_v01 *req;
  785. struct wlfw_bdf_download_resp_msg_v01 *resp;
  786. struct qmi_txn txn;
  787. char filename[MAX_FIRMWARE_NAME_LEN];
  788. const struct firmware *fw_entry = NULL;
  789. const u8 *temp;
  790. unsigned int remaining;
  791. int ret = 0;
  792. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  793. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  794. req = kzalloc(sizeof(*req), GFP_KERNEL);
  795. if (!req)
  796. return -ENOMEM;
  797. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  798. if (!resp) {
  799. kfree(req);
  800. return -ENOMEM;
  801. }
  802. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  803. filename, sizeof(filename));
  804. if (ret)
  805. goto err_req_fw;
  806. if (bdf_type == CNSS_BDF_REGDB)
  807. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  808. filename);
  809. else
  810. ret = firmware_request_nowarn(&fw_entry, filename,
  811. &plat_priv->plat_dev->dev);
  812. if (ret) {
  813. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  814. cnss_bdf_type_to_str(bdf_type), filename, ret);
  815. goto err_req_fw;
  816. }
  817. temp = fw_entry->data;
  818. remaining = fw_entry->size;
  819. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  820. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  821. while (remaining) {
  822. req->valid = 1;
  823. req->file_id_valid = 1;
  824. req->file_id = plat_priv->board_info.board_id;
  825. req->total_size_valid = 1;
  826. req->total_size = remaining;
  827. req->seg_id_valid = 1;
  828. req->data_valid = 1;
  829. req->end_valid = 1;
  830. req->bdf_type_valid = 1;
  831. req->bdf_type = bdf_type;
  832. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  833. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  834. } else {
  835. req->data_len = remaining;
  836. req->end = 1;
  837. }
  838. memcpy(req->data, temp, req->data_len);
  839. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  840. wlfw_bdf_download_resp_msg_v01_ei, resp);
  841. if (ret < 0) {
  842. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  843. cnss_bdf_type_to_str(bdf_type), ret);
  844. goto err_send;
  845. }
  846. ret = qmi_send_request
  847. (&plat_priv->qmi_wlfw, NULL, &txn,
  848. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  849. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  850. wlfw_bdf_download_req_msg_v01_ei, req);
  851. if (ret < 0) {
  852. qmi_txn_cancel(&txn);
  853. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  854. cnss_bdf_type_to_str(bdf_type), ret);
  855. goto err_send;
  856. }
  857. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  858. if (ret < 0) {
  859. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  860. cnss_bdf_type_to_str(bdf_type), ret);
  861. goto err_send;
  862. }
  863. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  864. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  865. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  866. resp->resp.error);
  867. ret = -resp->resp.result;
  868. goto err_send;
  869. }
  870. remaining -= req->data_len;
  871. temp += req->data_len;
  872. req->seg_id++;
  873. }
  874. release_firmware(fw_entry);
  875. if (resp->host_bdf_data_valid) {
  876. /* QCA6490 enable S3E regulator for IPA configuration only */
  877. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  878. cnss_enable_int_pow_amp_vreg(plat_priv);
  879. plat_priv->cbc_file_download =
  880. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  881. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  882. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  883. plat_priv->cbc_file_download);
  884. }
  885. kfree(req);
  886. kfree(resp);
  887. return 0;
  888. err_send:
  889. release_firmware(fw_entry);
  890. err_req_fw:
  891. if (!(bdf_type == CNSS_BDF_REGDB ||
  892. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  893. ret == -EAGAIN))
  894. CNSS_QMI_ASSERT();
  895. kfree(req);
  896. kfree(resp);
  897. return ret;
  898. }
  899. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  900. enum wlfw_tme_lite_file_type_v01 file)
  901. {
  902. struct wlfw_tme_lite_info_req_msg_v01 *req;
  903. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  904. struct qmi_txn txn;
  905. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  906. int ret = 0;
  907. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  908. plat_priv->driver_state);
  909. if (plat_priv->device_id != PEACH_DEVICE_ID)
  910. return 0;
  911. req = kzalloc(sizeof(*req), GFP_KERNEL);
  912. if (!req)
  913. return -ENOMEM;
  914. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  915. if (!resp) {
  916. kfree(req);
  917. return -ENOMEM;
  918. }
  919. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  920. cnss_pr_err("Memory for TME patch is not available\n");
  921. ret = -ENOMEM;
  922. goto out;
  923. }
  924. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  925. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  926. req->tme_file = file;
  927. req->addr = plat_priv->tme_lite_mem.pa;
  928. req->size = plat_priv->tme_lite_mem.size;
  929. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  930. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  931. if (ret < 0) {
  932. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  933. ret);
  934. goto out;
  935. }
  936. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  937. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  938. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  939. wlfw_tme_lite_info_req_msg_v01_ei, req);
  940. if (ret < 0) {
  941. qmi_txn_cancel(&txn);
  942. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  943. ret);
  944. goto out;
  945. }
  946. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  947. if (ret < 0) {
  948. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  949. ret);
  950. goto out;
  951. }
  952. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  953. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  954. resp->resp.result, resp->resp.error);
  955. ret = -resp->resp.result;
  956. goto out;
  957. }
  958. kfree(req);
  959. kfree(resp);
  960. return 0;
  961. out:
  962. kfree(req);
  963. kfree(resp);
  964. return ret;
  965. }
  966. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  967. {
  968. struct wlfw_m3_info_req_msg_v01 *req;
  969. struct wlfw_m3_info_resp_msg_v01 *resp;
  970. struct qmi_txn txn;
  971. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  972. int ret = 0;
  973. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  974. plat_priv->driver_state);
  975. req = kzalloc(sizeof(*req), GFP_KERNEL);
  976. if (!req)
  977. return -ENOMEM;
  978. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  979. if (!resp) {
  980. kfree(req);
  981. return -ENOMEM;
  982. }
  983. if (!m3_mem->pa || !m3_mem->size) {
  984. cnss_pr_err("Memory for M3 is not available\n");
  985. ret = -ENOMEM;
  986. goto out;
  987. }
  988. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  989. m3_mem->va, &m3_mem->pa, m3_mem->size);
  990. req->addr = plat_priv->m3_mem.pa;
  991. req->size = plat_priv->m3_mem.size;
  992. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  993. wlfw_m3_info_resp_msg_v01_ei, resp);
  994. if (ret < 0) {
  995. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  996. ret);
  997. goto out;
  998. }
  999. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1000. QMI_WLFW_M3_INFO_REQ_V01,
  1001. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1002. wlfw_m3_info_req_msg_v01_ei, req);
  1003. if (ret < 0) {
  1004. qmi_txn_cancel(&txn);
  1005. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  1006. ret);
  1007. goto out;
  1008. }
  1009. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1010. if (ret < 0) {
  1011. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  1012. ret);
  1013. goto out;
  1014. }
  1015. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1016. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1017. resp->resp.result, resp->resp.error);
  1018. ret = -resp->resp.result;
  1019. goto out;
  1020. }
  1021. kfree(req);
  1022. kfree(resp);
  1023. return 0;
  1024. out:
  1025. CNSS_QMI_ASSERT();
  1026. kfree(req);
  1027. kfree(resp);
  1028. return ret;
  1029. }
  1030. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1031. {
  1032. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1033. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1034. struct qmi_txn txn;
  1035. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1036. int ret = 0;
  1037. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1038. plat_priv->driver_state);
  1039. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1040. if (!req)
  1041. return -ENOMEM;
  1042. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1043. if (!resp) {
  1044. kfree(req);
  1045. return -ENOMEM;
  1046. }
  1047. if (!aux_mem->pa || !aux_mem->size) {
  1048. cnss_pr_err("Memory for AUX is not available\n");
  1049. ret = -ENOMEM;
  1050. goto out;
  1051. }
  1052. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1053. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1054. req->addr = plat_priv->aux_mem.pa;
  1055. req->size = plat_priv->aux_mem.size;
  1056. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1057. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1058. if (ret < 0) {
  1059. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1060. ret);
  1061. goto out;
  1062. }
  1063. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1064. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1065. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1066. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1067. if (ret < 0) {
  1068. qmi_txn_cancel(&txn);
  1069. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1070. ret);
  1071. goto out;
  1072. }
  1073. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1074. if (ret < 0) {
  1075. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1076. ret);
  1077. goto out;
  1078. }
  1079. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1080. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1081. resp->resp.result, resp->resp.error);
  1082. ret = -resp->resp.result;
  1083. goto out;
  1084. }
  1085. kfree(req);
  1086. kfree(resp);
  1087. return 0;
  1088. out:
  1089. CNSS_QMI_ASSERT();
  1090. kfree(req);
  1091. kfree(resp);
  1092. return ret;
  1093. }
  1094. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1095. u8 *mac, u32 mac_len)
  1096. {
  1097. struct wlfw_mac_addr_req_msg_v01 req;
  1098. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1099. struct qmi_txn txn;
  1100. int ret;
  1101. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1102. return -EINVAL;
  1103. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1104. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1105. if (ret < 0) {
  1106. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1107. ret);
  1108. ret = -EIO;
  1109. goto out;
  1110. }
  1111. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1112. mac, plat_priv->driver_state);
  1113. memcpy(req.mac_addr, mac, mac_len);
  1114. req.mac_addr_valid = 1;
  1115. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1116. QMI_WLFW_MAC_ADDR_REQ_V01,
  1117. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1118. wlfw_mac_addr_req_msg_v01_ei, &req);
  1119. if (ret < 0) {
  1120. qmi_txn_cancel(&txn);
  1121. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1122. ret = -EIO;
  1123. goto out;
  1124. }
  1125. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1126. if (ret < 0) {
  1127. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1128. ret);
  1129. ret = -EIO;
  1130. goto out;
  1131. }
  1132. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1133. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1134. resp.resp.result);
  1135. ret = -resp.resp.result;
  1136. }
  1137. out:
  1138. return ret;
  1139. }
  1140. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1141. u32 total_size)
  1142. {
  1143. int ret = 0;
  1144. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1145. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1146. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1147. unsigned int remaining;
  1148. struct qmi_txn txn;
  1149. cnss_pr_dbg("%s\n", __func__);
  1150. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1151. if (!req)
  1152. return -ENOMEM;
  1153. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1154. if (!resp) {
  1155. kfree(req);
  1156. return -ENOMEM;
  1157. }
  1158. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1159. if (!p_qdss_trace_data) {
  1160. ret = ENOMEM;
  1161. goto end;
  1162. }
  1163. remaining = total_size;
  1164. p_qdss_trace_data_temp = p_qdss_trace_data;
  1165. while (remaining && resp->end == 0) {
  1166. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1167. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1168. if (ret < 0) {
  1169. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1170. ret);
  1171. goto fail;
  1172. }
  1173. ret = qmi_send_request
  1174. (&plat_priv->qmi_wlfw, NULL, &txn,
  1175. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1176. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1177. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1178. if (ret < 0) {
  1179. qmi_txn_cancel(&txn);
  1180. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1181. ret);
  1182. goto fail;
  1183. }
  1184. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1185. if (ret < 0) {
  1186. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1187. ret);
  1188. goto fail;
  1189. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1190. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1191. resp->resp.result, resp->resp.error);
  1192. ret = -resp->resp.result;
  1193. goto fail;
  1194. } else {
  1195. ret = 0;
  1196. }
  1197. cnss_pr_dbg("%s: response total size %d data len %d",
  1198. __func__, resp->total_size, resp->data_len);
  1199. if ((resp->total_size_valid == 1 &&
  1200. resp->total_size == total_size) &&
  1201. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1202. (resp->data_valid == 1 &&
  1203. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1204. resp->data_len <= remaining) {
  1205. memcpy(p_qdss_trace_data_temp,
  1206. resp->data, resp->data_len);
  1207. } else {
  1208. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1209. __func__,
  1210. total_size, req->seg_id,
  1211. resp->total_size_valid,
  1212. resp->total_size,
  1213. resp->seg_id_valid,
  1214. resp->seg_id,
  1215. resp->data_valid,
  1216. resp->data_len);
  1217. ret = -1;
  1218. goto fail;
  1219. }
  1220. remaining -= resp->data_len;
  1221. p_qdss_trace_data_temp += resp->data_len;
  1222. req->seg_id++;
  1223. }
  1224. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1225. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1226. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1227. total_size);
  1228. if (ret < 0) {
  1229. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1230. ret);
  1231. ret = -1;
  1232. goto fail;
  1233. }
  1234. } else {
  1235. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1236. __func__,
  1237. remaining, resp->end_valid, resp->end);
  1238. ret = -1;
  1239. goto fail;
  1240. }
  1241. fail:
  1242. kfree(p_qdss_trace_data);
  1243. end:
  1244. kfree(req);
  1245. kfree(resp);
  1246. return ret;
  1247. }
  1248. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1249. char *filename, u32 filename_len,
  1250. bool fallback_file)
  1251. {
  1252. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1253. char *build_str = QDSS_FILE_BUILD_STR;
  1254. if (fallback_file)
  1255. build_str = "";
  1256. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1257. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1258. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1259. else
  1260. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1261. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1262. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1263. }
  1264. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1265. {
  1266. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1267. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1268. struct qmi_txn txn;
  1269. const struct firmware *fw_entry = NULL;
  1270. const u8 *temp;
  1271. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1272. unsigned int remaining;
  1273. int ret = 0;
  1274. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1275. plat_priv->driver_state);
  1276. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1277. if (!req)
  1278. return -ENOMEM;
  1279. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1280. if (!resp) {
  1281. kfree(req);
  1282. return -ENOMEM;
  1283. }
  1284. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1285. sizeof(qdss_cfg_filename), false);
  1286. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1287. qdss_cfg_filename);
  1288. if (ret) {
  1289. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1290. qdss_cfg_filename, ret);
  1291. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1292. sizeof(qdss_cfg_filename),
  1293. true);
  1294. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1295. qdss_cfg_filename);
  1296. if (ret) {
  1297. cnss_pr_err("Unable to load %s ret %d\n",
  1298. qdss_cfg_filename, ret);
  1299. goto err_req_fw;
  1300. }
  1301. }
  1302. temp = fw_entry->data;
  1303. remaining = fw_entry->size;
  1304. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1305. qdss_cfg_filename, remaining);
  1306. while (remaining) {
  1307. req->total_size_valid = 1;
  1308. req->total_size = remaining;
  1309. req->seg_id_valid = 1;
  1310. req->data_valid = 1;
  1311. req->end_valid = 1;
  1312. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1313. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1314. } else {
  1315. req->data_len = remaining;
  1316. req->end = 1;
  1317. }
  1318. memcpy(req->data, temp, req->data_len);
  1319. ret = qmi_txn_init
  1320. (&plat_priv->qmi_wlfw, &txn,
  1321. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1322. resp);
  1323. if (ret < 0) {
  1324. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1325. ret);
  1326. goto err_send;
  1327. }
  1328. ret = qmi_send_request
  1329. (&plat_priv->qmi_wlfw, NULL, &txn,
  1330. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1331. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1332. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1333. if (ret < 0) {
  1334. qmi_txn_cancel(&txn);
  1335. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1336. ret);
  1337. goto err_send;
  1338. }
  1339. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1340. if (ret < 0) {
  1341. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1342. ret);
  1343. goto err_send;
  1344. }
  1345. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1346. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1347. resp->resp.result, resp->resp.error);
  1348. ret = -resp->resp.result;
  1349. goto err_send;
  1350. }
  1351. remaining -= req->data_len;
  1352. temp += req->data_len;
  1353. req->seg_id++;
  1354. }
  1355. release_firmware(fw_entry);
  1356. kfree(req);
  1357. kfree(resp);
  1358. return 0;
  1359. err_send:
  1360. release_firmware(fw_entry);
  1361. err_req_fw:
  1362. kfree(req);
  1363. kfree(resp);
  1364. return ret;
  1365. }
  1366. static int wlfw_send_qdss_trace_mode_req
  1367. (struct cnss_plat_data *plat_priv,
  1368. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1369. unsigned long long option)
  1370. {
  1371. int rc = 0;
  1372. int tmp = 0;
  1373. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1374. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1375. struct qmi_txn txn;
  1376. if (!plat_priv)
  1377. return -ENODEV;
  1378. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1379. if (!req)
  1380. return -ENOMEM;
  1381. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1382. if (!resp) {
  1383. kfree(req);
  1384. return -ENOMEM;
  1385. }
  1386. req->mode_valid = 1;
  1387. req->mode = mode;
  1388. req->option_valid = 1;
  1389. req->option = option;
  1390. tmp = plat_priv->hw_trc_override;
  1391. req->hw_trc_disable_override_valid = 1;
  1392. req->hw_trc_disable_override =
  1393. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1394. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1395. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1396. __func__, mode, option, req->hw_trc_disable_override);
  1397. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1398. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1399. if (rc < 0) {
  1400. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1401. rc);
  1402. goto out;
  1403. }
  1404. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1405. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1406. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1407. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1408. if (rc < 0) {
  1409. qmi_txn_cancel(&txn);
  1410. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1411. goto out;
  1412. }
  1413. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1414. if (rc < 0) {
  1415. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1416. rc);
  1417. goto out;
  1418. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1419. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1420. resp->resp.result, resp->resp.error);
  1421. rc = -resp->resp.result;
  1422. goto out;
  1423. }
  1424. kfree(resp);
  1425. kfree(req);
  1426. return rc;
  1427. out:
  1428. kfree(resp);
  1429. kfree(req);
  1430. CNSS_QMI_ASSERT();
  1431. return rc;
  1432. }
  1433. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1434. {
  1435. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1436. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1437. }
  1438. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1439. {
  1440. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1441. option);
  1442. }
  1443. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1444. enum cnss_driver_mode mode)
  1445. {
  1446. struct wlfw_wlan_mode_req_msg_v01 *req;
  1447. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1448. struct qmi_txn txn;
  1449. int ret = 0;
  1450. if (!plat_priv)
  1451. return -ENODEV;
  1452. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1453. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1454. if (mode == CNSS_OFF &&
  1455. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1456. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1457. return 0;
  1458. }
  1459. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1460. if (!req)
  1461. return -ENOMEM;
  1462. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1463. if (!resp) {
  1464. kfree(req);
  1465. return -ENOMEM;
  1466. }
  1467. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1468. req->hw_debug_valid = 1;
  1469. req->hw_debug = 0;
  1470. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1471. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1472. if (ret < 0) {
  1473. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1474. cnss_qmi_mode_to_str(mode), mode, ret);
  1475. goto out;
  1476. }
  1477. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1478. QMI_WLFW_WLAN_MODE_REQ_V01,
  1479. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1480. wlfw_wlan_mode_req_msg_v01_ei, req);
  1481. if (ret < 0) {
  1482. qmi_txn_cancel(&txn);
  1483. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1484. cnss_qmi_mode_to_str(mode), mode, ret);
  1485. goto out;
  1486. }
  1487. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1488. if (ret < 0) {
  1489. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1490. cnss_qmi_mode_to_str(mode), mode, ret);
  1491. goto out;
  1492. }
  1493. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1494. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1495. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1496. resp->resp.error);
  1497. ret = -resp->resp.result;
  1498. goto out;
  1499. }
  1500. kfree(req);
  1501. kfree(resp);
  1502. return 0;
  1503. out:
  1504. if (mode == CNSS_OFF) {
  1505. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1506. ret = 0;
  1507. } else {
  1508. CNSS_QMI_ASSERT();
  1509. }
  1510. kfree(req);
  1511. kfree(resp);
  1512. return ret;
  1513. }
  1514. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1515. struct cnss_wlan_enable_cfg *config,
  1516. const char *host_version)
  1517. {
  1518. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1519. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1520. struct qmi_txn txn;
  1521. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1522. int ret = 0;
  1523. if (!plat_priv)
  1524. return -ENODEV;
  1525. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1526. plat_priv->driver_state);
  1527. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1528. if (!req)
  1529. return -ENOMEM;
  1530. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1531. if (!resp) {
  1532. kfree(req);
  1533. return -ENOMEM;
  1534. }
  1535. req->host_version_valid = 1;
  1536. strlcpy(req->host_version, host_version,
  1537. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1538. req->tgt_cfg_valid = 1;
  1539. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1540. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1541. else
  1542. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1543. for (i = 0; i < req->tgt_cfg_len; i++) {
  1544. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1545. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1546. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1547. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1548. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1549. }
  1550. req->svc_cfg_valid = 1;
  1551. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1552. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1553. else
  1554. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1555. for (i = 0; i < req->svc_cfg_len; i++) {
  1556. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1557. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1558. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1559. }
  1560. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1561. plat_priv->device_id != MANGO_DEVICE_ID &&
  1562. plat_priv->device_id != PEACH_DEVICE_ID) {
  1563. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1564. config->num_shadow_reg_cfg) {
  1565. req->shadow_reg_valid = 1;
  1566. if (config->num_shadow_reg_cfg >
  1567. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1568. req->shadow_reg_len =
  1569. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1570. else
  1571. req->shadow_reg_len =
  1572. config->num_shadow_reg_cfg;
  1573. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1574. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1575. req->shadow_reg_len);
  1576. } else {
  1577. req->shadow_reg_v2_valid = 1;
  1578. if (config->num_shadow_reg_v2_cfg >
  1579. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1580. req->shadow_reg_v2_len =
  1581. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1582. else
  1583. req->shadow_reg_v2_len =
  1584. config->num_shadow_reg_v2_cfg;
  1585. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1586. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1587. req->shadow_reg_v2_len);
  1588. }
  1589. } else {
  1590. req->shadow_reg_v3_valid = 1;
  1591. if (config->num_shadow_reg_v3_cfg >
  1592. MAX_NUM_SHADOW_REG_V3)
  1593. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1594. else
  1595. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1596. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1597. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1598. plat_priv->num_shadow_regs_v3);
  1599. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1600. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1601. req->shadow_reg_v3_len);
  1602. }
  1603. if (config->rri_over_ddr_cfg_valid) {
  1604. req->rri_over_ddr_cfg_valid = 1;
  1605. req->rri_over_ddr_cfg.base_addr_low =
  1606. config->rri_over_ddr_cfg.base_addr_low;
  1607. req->rri_over_ddr_cfg.base_addr_high =
  1608. config->rri_over_ddr_cfg.base_addr_high;
  1609. }
  1610. if (config->send_msi_ce) {
  1611. ret = cnss_bus_get_msi_assignment(plat_priv,
  1612. CE_MSI_NAME,
  1613. &num_vectors,
  1614. &user_base_data,
  1615. &base_vector);
  1616. if (!ret) {
  1617. req->msi_cfg_valid = 1;
  1618. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1619. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1620. ce_id++) {
  1621. req->msi_cfg[ce_id].ce_id = ce_id;
  1622. req->msi_cfg[ce_id].msi_vector =
  1623. (ce_id % num_vectors) + base_vector;
  1624. }
  1625. }
  1626. }
  1627. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1628. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1629. if (ret < 0) {
  1630. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1631. ret);
  1632. goto out;
  1633. }
  1634. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1635. QMI_WLFW_WLAN_CFG_REQ_V01,
  1636. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1637. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1638. if (ret < 0) {
  1639. qmi_txn_cancel(&txn);
  1640. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1641. ret);
  1642. goto out;
  1643. }
  1644. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1645. if (ret < 0) {
  1646. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1647. ret);
  1648. goto out;
  1649. }
  1650. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1651. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1652. resp->resp.result, resp->resp.error);
  1653. ret = -resp->resp.result;
  1654. goto out;
  1655. }
  1656. kfree(req);
  1657. kfree(resp);
  1658. return 0;
  1659. out:
  1660. CNSS_QMI_ASSERT();
  1661. kfree(req);
  1662. kfree(resp);
  1663. return ret;
  1664. }
  1665. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1666. u32 offset, u32 mem_type,
  1667. u32 data_len, u8 *data)
  1668. {
  1669. struct wlfw_athdiag_read_req_msg_v01 *req;
  1670. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1671. struct qmi_txn txn;
  1672. int ret = 0;
  1673. if (!plat_priv)
  1674. return -ENODEV;
  1675. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1676. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1677. data, data_len);
  1678. return -EINVAL;
  1679. }
  1680. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1681. plat_priv->driver_state, offset, mem_type, data_len);
  1682. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1683. if (!req)
  1684. return -ENOMEM;
  1685. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1686. if (!resp) {
  1687. kfree(req);
  1688. return -ENOMEM;
  1689. }
  1690. req->offset = offset;
  1691. req->mem_type = mem_type;
  1692. req->data_len = data_len;
  1693. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1694. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1695. if (ret < 0) {
  1696. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1697. ret);
  1698. goto out;
  1699. }
  1700. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1701. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1702. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1703. wlfw_athdiag_read_req_msg_v01_ei, req);
  1704. if (ret < 0) {
  1705. qmi_txn_cancel(&txn);
  1706. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1707. ret);
  1708. goto out;
  1709. }
  1710. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1711. if (ret < 0) {
  1712. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1713. ret);
  1714. goto out;
  1715. }
  1716. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1717. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1718. resp->resp.result, resp->resp.error);
  1719. ret = -resp->resp.result;
  1720. goto out;
  1721. }
  1722. if (!resp->data_valid || resp->data_len != data_len) {
  1723. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1724. resp->data_valid, resp->data_len);
  1725. ret = -EINVAL;
  1726. goto out;
  1727. }
  1728. memcpy(data, resp->data, resp->data_len);
  1729. kfree(req);
  1730. kfree(resp);
  1731. return 0;
  1732. out:
  1733. kfree(req);
  1734. kfree(resp);
  1735. return ret;
  1736. }
  1737. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1738. u32 offset, u32 mem_type,
  1739. u32 data_len, u8 *data)
  1740. {
  1741. struct wlfw_athdiag_write_req_msg_v01 *req;
  1742. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1743. struct qmi_txn txn;
  1744. int ret = 0;
  1745. if (!plat_priv)
  1746. return -ENODEV;
  1747. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1748. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1749. data, data_len);
  1750. return -EINVAL;
  1751. }
  1752. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1753. plat_priv->driver_state, offset, mem_type, data_len, data);
  1754. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1755. if (!req)
  1756. return -ENOMEM;
  1757. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1758. if (!resp) {
  1759. kfree(req);
  1760. return -ENOMEM;
  1761. }
  1762. req->offset = offset;
  1763. req->mem_type = mem_type;
  1764. req->data_len = data_len;
  1765. memcpy(req->data, data, data_len);
  1766. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1767. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1768. if (ret < 0) {
  1769. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1770. ret);
  1771. goto out;
  1772. }
  1773. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1774. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1775. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1776. wlfw_athdiag_write_req_msg_v01_ei, req);
  1777. if (ret < 0) {
  1778. qmi_txn_cancel(&txn);
  1779. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1780. ret);
  1781. goto out;
  1782. }
  1783. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1784. if (ret < 0) {
  1785. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1786. ret);
  1787. goto out;
  1788. }
  1789. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1790. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1791. resp->resp.result, resp->resp.error);
  1792. ret = -resp->resp.result;
  1793. goto out;
  1794. }
  1795. kfree(req);
  1796. kfree(resp);
  1797. return 0;
  1798. out:
  1799. kfree(req);
  1800. kfree(resp);
  1801. return ret;
  1802. }
  1803. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1804. u8 fw_log_mode)
  1805. {
  1806. struct wlfw_ini_req_msg_v01 *req;
  1807. struct wlfw_ini_resp_msg_v01 *resp;
  1808. struct qmi_txn txn;
  1809. int ret = 0;
  1810. if (!plat_priv)
  1811. return -ENODEV;
  1812. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1813. plat_priv->driver_state, fw_log_mode);
  1814. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1815. if (!req)
  1816. return -ENOMEM;
  1817. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1818. if (!resp) {
  1819. kfree(req);
  1820. return -ENOMEM;
  1821. }
  1822. req->enablefwlog_valid = 1;
  1823. req->enablefwlog = fw_log_mode;
  1824. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1825. wlfw_ini_resp_msg_v01_ei, resp);
  1826. if (ret < 0) {
  1827. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1828. fw_log_mode, ret);
  1829. goto out;
  1830. }
  1831. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1832. QMI_WLFW_INI_REQ_V01,
  1833. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1834. wlfw_ini_req_msg_v01_ei, req);
  1835. if (ret < 0) {
  1836. qmi_txn_cancel(&txn);
  1837. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1838. fw_log_mode, ret);
  1839. goto out;
  1840. }
  1841. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1842. if (ret < 0) {
  1843. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1844. fw_log_mode, ret);
  1845. goto out;
  1846. }
  1847. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1848. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1849. fw_log_mode, resp->resp.result, resp->resp.error);
  1850. ret = -resp->resp.result;
  1851. goto out;
  1852. }
  1853. kfree(req);
  1854. kfree(resp);
  1855. return 0;
  1856. out:
  1857. kfree(req);
  1858. kfree(resp);
  1859. return ret;
  1860. }
  1861. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1862. {
  1863. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1864. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1865. struct qmi_txn txn;
  1866. int ret = 0;
  1867. if (!plat_priv)
  1868. return -ENODEV;
  1869. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1870. !plat_priv->fw_pcie_gen_switch) {
  1871. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1872. return 0;
  1873. }
  1874. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1875. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1876. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1877. plat_priv->pcie_gen_speed;
  1878. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1879. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1880. if (ret < 0) {
  1881. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1882. ret);
  1883. goto out;
  1884. }
  1885. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1886. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1887. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1888. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1889. if (ret < 0) {
  1890. qmi_txn_cancel(&txn);
  1891. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1892. goto out;
  1893. }
  1894. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1895. if (ret < 0) {
  1896. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1897. ret);
  1898. goto out;
  1899. }
  1900. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1901. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1902. plat_priv->pcie_gen_speed, resp.resp.result,
  1903. resp.resp.error);
  1904. ret = -resp.resp.result;
  1905. }
  1906. out:
  1907. /* Reset PCIE Gen speed after one time use */
  1908. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1909. return ret;
  1910. }
  1911. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1912. {
  1913. struct wlfw_antenna_switch_req_msg_v01 *req;
  1914. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1915. struct qmi_txn txn;
  1916. int ret = 0;
  1917. if (!plat_priv)
  1918. return -ENODEV;
  1919. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1920. plat_priv->driver_state);
  1921. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1922. if (!req)
  1923. return -ENOMEM;
  1924. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1925. if (!resp) {
  1926. kfree(req);
  1927. return -ENOMEM;
  1928. }
  1929. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1930. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1931. if (ret < 0) {
  1932. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1933. ret);
  1934. goto out;
  1935. }
  1936. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1937. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1938. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1939. wlfw_antenna_switch_req_msg_v01_ei, req);
  1940. if (ret < 0) {
  1941. qmi_txn_cancel(&txn);
  1942. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1943. ret);
  1944. goto out;
  1945. }
  1946. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1947. if (ret < 0) {
  1948. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1949. ret);
  1950. goto out;
  1951. }
  1952. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1953. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1954. resp->resp.result, resp->resp.error);
  1955. ret = -resp->resp.result;
  1956. goto out;
  1957. }
  1958. if (resp->antenna_valid)
  1959. plat_priv->antenna = resp->antenna;
  1960. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1961. resp->antenna_valid, resp->antenna);
  1962. kfree(req);
  1963. kfree(resp);
  1964. return 0;
  1965. out:
  1966. kfree(req);
  1967. kfree(resp);
  1968. return ret;
  1969. }
  1970. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1971. {
  1972. struct wlfw_antenna_grant_req_msg_v01 *req;
  1973. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1974. struct qmi_txn txn;
  1975. int ret = 0;
  1976. if (!plat_priv)
  1977. return -ENODEV;
  1978. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1979. plat_priv->driver_state, plat_priv->grant);
  1980. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1981. if (!req)
  1982. return -ENOMEM;
  1983. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1984. if (!resp) {
  1985. kfree(req);
  1986. return -ENOMEM;
  1987. }
  1988. req->grant_valid = 1;
  1989. req->grant = plat_priv->grant;
  1990. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1991. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1992. if (ret < 0) {
  1993. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1994. ret);
  1995. goto out;
  1996. }
  1997. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1998. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1999. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  2000. wlfw_antenna_grant_req_msg_v01_ei, req);
  2001. if (ret < 0) {
  2002. qmi_txn_cancel(&txn);
  2003. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  2004. ret);
  2005. goto out;
  2006. }
  2007. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2008. if (ret < 0) {
  2009. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  2010. ret);
  2011. goto out;
  2012. }
  2013. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2014. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2015. resp->resp.result, resp->resp.error);
  2016. ret = -resp->resp.result;
  2017. goto out;
  2018. }
  2019. kfree(req);
  2020. kfree(resp);
  2021. return 0;
  2022. out:
  2023. kfree(req);
  2024. kfree(resp);
  2025. return ret;
  2026. }
  2027. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2028. {
  2029. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2030. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2031. struct qmi_txn txn;
  2032. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2033. int ret = 0;
  2034. int i;
  2035. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2036. plat_priv->driver_state);
  2037. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2038. if (!req)
  2039. return -ENOMEM;
  2040. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2041. if (!resp) {
  2042. kfree(req);
  2043. return -ENOMEM;
  2044. }
  2045. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2046. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2047. ret = -EINVAL;
  2048. goto out;
  2049. }
  2050. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2051. for (i = 0; i < req->mem_seg_len; i++) {
  2052. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2053. qdss_mem[i].va, &qdss_mem[i].pa,
  2054. qdss_mem[i].size, qdss_mem[i].type);
  2055. req->mem_seg[i].addr = qdss_mem[i].pa;
  2056. req->mem_seg[i].size = qdss_mem[i].size;
  2057. req->mem_seg[i].type = qdss_mem[i].type;
  2058. }
  2059. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2060. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2061. if (ret < 0) {
  2062. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2063. ret);
  2064. goto out;
  2065. }
  2066. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2067. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2068. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2069. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2070. if (ret < 0) {
  2071. qmi_txn_cancel(&txn);
  2072. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2073. ret);
  2074. goto out;
  2075. }
  2076. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2077. if (ret < 0) {
  2078. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2079. ret);
  2080. goto out;
  2081. }
  2082. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2083. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2084. resp->resp.result, resp->resp.error);
  2085. ret = -resp->resp.result;
  2086. goto out;
  2087. }
  2088. kfree(req);
  2089. kfree(resp);
  2090. return 0;
  2091. out:
  2092. kfree(req);
  2093. kfree(resp);
  2094. return ret;
  2095. }
  2096. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2097. struct cnss_wfc_cfg cfg)
  2098. {
  2099. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2100. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2101. struct qmi_txn txn;
  2102. int ret = 0;
  2103. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2104. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2105. return -EINVAL;
  2106. }
  2107. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2108. if (!req)
  2109. return -ENOMEM;
  2110. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2111. if (!resp) {
  2112. kfree(req);
  2113. return -ENOMEM;
  2114. }
  2115. req->wfc_call_active_valid = 1;
  2116. req->wfc_call_active = cfg.mode;
  2117. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2118. plat_priv->driver_state);
  2119. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2120. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2121. if (ret < 0) {
  2122. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2123. ret);
  2124. goto out;
  2125. }
  2126. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2127. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2128. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2129. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2130. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2131. if (ret < 0) {
  2132. qmi_txn_cancel(&txn);
  2133. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2134. ret);
  2135. goto out;
  2136. }
  2137. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2138. if (ret < 0) {
  2139. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2140. ret);
  2141. goto out;
  2142. }
  2143. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2144. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2145. resp->resp.result, resp->resp.error);
  2146. ret = -EINVAL;
  2147. goto out;
  2148. }
  2149. ret = 0;
  2150. out:
  2151. kfree(req);
  2152. kfree(resp);
  2153. return ret;
  2154. }
  2155. static int cnss_wlfw_wfc_call_status_send_sync
  2156. (struct cnss_plat_data *plat_priv,
  2157. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2158. {
  2159. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2160. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2161. struct qmi_txn txn;
  2162. int ret = 0;
  2163. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2164. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2165. return -EINVAL;
  2166. }
  2167. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2168. if (!req)
  2169. return -ENOMEM;
  2170. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2171. if (!resp) {
  2172. kfree(req);
  2173. return -ENOMEM;
  2174. }
  2175. /**
  2176. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2177. * But in r2 update QMI structure is expanded and as an effect qmi
  2178. * decoded structures have padding. Thus we cannot use buffer design.
  2179. * For backward compatibility for r1 design copy only wfc_call_active
  2180. * value in hex buffer.
  2181. */
  2182. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2183. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2184. /* wfc_call_active is mandatory in IMS indication */
  2185. req->wfc_call_active_valid = 1;
  2186. req->wfc_call_active = ind_msg->wfc_call_active;
  2187. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2188. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2189. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2190. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2191. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2192. req->twt_ims_start = ind_msg->twt_ims_start;
  2193. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2194. req->twt_ims_int = ind_msg->twt_ims_int;
  2195. req->media_quality_valid = ind_msg->media_quality_valid;
  2196. req->media_quality =
  2197. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2198. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2199. plat_priv->driver_state);
  2200. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2201. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2202. if (ret < 0) {
  2203. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2204. ret);
  2205. goto out;
  2206. }
  2207. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2208. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2209. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2210. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2211. if (ret < 0) {
  2212. qmi_txn_cancel(&txn);
  2213. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2214. ret);
  2215. goto out;
  2216. }
  2217. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2218. if (ret < 0) {
  2219. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2220. ret);
  2221. goto out;
  2222. }
  2223. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2224. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2225. resp->resp.result, resp->resp.error);
  2226. ret = -resp->resp.result;
  2227. goto out;
  2228. }
  2229. ret = 0;
  2230. out:
  2231. kfree(req);
  2232. kfree(resp);
  2233. return ret;
  2234. }
  2235. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2236. {
  2237. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2238. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2239. struct qmi_txn txn;
  2240. int ret = 0;
  2241. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2242. plat_priv->dynamic_feature,
  2243. plat_priv->driver_state);
  2244. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2245. if (!req)
  2246. return -ENOMEM;
  2247. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2248. if (!resp) {
  2249. kfree(req);
  2250. return -ENOMEM;
  2251. }
  2252. req->mask_valid = 1;
  2253. req->mask = plat_priv->dynamic_feature;
  2254. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2255. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2256. if (ret < 0) {
  2257. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2258. ret);
  2259. goto out;
  2260. }
  2261. ret = qmi_send_request
  2262. (&plat_priv->qmi_wlfw, NULL, &txn,
  2263. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2264. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2265. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2266. if (ret < 0) {
  2267. qmi_txn_cancel(&txn);
  2268. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2269. ret);
  2270. goto out;
  2271. }
  2272. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2273. if (ret < 0) {
  2274. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2275. ret);
  2276. goto out;
  2277. }
  2278. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2279. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2280. resp->resp.result, resp->resp.error);
  2281. ret = -resp->resp.result;
  2282. goto out;
  2283. }
  2284. out:
  2285. kfree(req);
  2286. kfree(resp);
  2287. return ret;
  2288. }
  2289. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2290. void *cmd, int cmd_len)
  2291. {
  2292. struct wlfw_get_info_req_msg_v01 *req;
  2293. struct wlfw_get_info_resp_msg_v01 *resp;
  2294. struct qmi_txn txn;
  2295. int ret = 0;
  2296. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2297. type, cmd_len, plat_priv->driver_state);
  2298. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2299. return -EINVAL;
  2300. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2301. if (!req)
  2302. return -ENOMEM;
  2303. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2304. if (!resp) {
  2305. kfree(req);
  2306. return -ENOMEM;
  2307. }
  2308. req->type = type;
  2309. req->data_len = cmd_len;
  2310. memcpy(req->data, cmd, req->data_len);
  2311. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2312. wlfw_get_info_resp_msg_v01_ei, resp);
  2313. if (ret < 0) {
  2314. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2315. ret);
  2316. goto out;
  2317. }
  2318. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2319. QMI_WLFW_GET_INFO_REQ_V01,
  2320. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2321. wlfw_get_info_req_msg_v01_ei, req);
  2322. if (ret < 0) {
  2323. qmi_txn_cancel(&txn);
  2324. cnss_pr_err("Failed to send get info request, err: %d\n",
  2325. ret);
  2326. goto out;
  2327. }
  2328. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2329. if (ret < 0) {
  2330. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2331. ret);
  2332. goto out;
  2333. }
  2334. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2335. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2336. resp->resp.result, resp->resp.error);
  2337. ret = -resp->resp.result;
  2338. goto out;
  2339. }
  2340. kfree(req);
  2341. kfree(resp);
  2342. return 0;
  2343. out:
  2344. kfree(req);
  2345. kfree(resp);
  2346. return ret;
  2347. }
  2348. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2349. {
  2350. return QMI_WLFW_TIMEOUT_MS;
  2351. }
  2352. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2353. struct sockaddr_qrtr *sq,
  2354. struct qmi_txn *txn, const void *data)
  2355. {
  2356. struct cnss_plat_data *plat_priv =
  2357. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2358. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2359. int i;
  2360. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2361. if (!txn) {
  2362. cnss_pr_err("Spurious indication\n");
  2363. return;
  2364. }
  2365. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2366. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2367. return;
  2368. }
  2369. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2370. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2371. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2372. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2373. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2374. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2375. if (!plat_priv->fw_mem[i].va &&
  2376. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2377. plat_priv->fw_mem[i].attrs |=
  2378. DMA_ATTR_FORCE_CONTIGUOUS;
  2379. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2380. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2381. }
  2382. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2383. 0, NULL);
  2384. }
  2385. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2386. struct sockaddr_qrtr *sq,
  2387. struct qmi_txn *txn, const void *data)
  2388. {
  2389. struct cnss_plat_data *plat_priv =
  2390. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2391. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2392. if (!txn) {
  2393. cnss_pr_err("Spurious indication\n");
  2394. return;
  2395. }
  2396. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2397. 0, NULL);
  2398. }
  2399. /**
  2400. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2401. *
  2402. * This event is not required for HST/ HSP as FW calibration done is
  2403. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2404. */
  2405. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2406. struct sockaddr_qrtr *sq,
  2407. struct qmi_txn *txn, const void *data)
  2408. {
  2409. struct cnss_plat_data *plat_priv =
  2410. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2411. struct cnss_cal_info *cal_info;
  2412. if (!txn) {
  2413. cnss_pr_err("Spurious indication\n");
  2414. return;
  2415. }
  2416. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2417. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2418. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2419. return;
  2420. }
  2421. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2422. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2423. if (!cal_info)
  2424. return;
  2425. cal_info->cal_status = CNSS_CAL_DONE;
  2426. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2427. 0, cal_info);
  2428. }
  2429. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2430. struct sockaddr_qrtr *sq,
  2431. struct qmi_txn *txn, const void *data)
  2432. {
  2433. struct cnss_plat_data *plat_priv =
  2434. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2435. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2436. if (!txn) {
  2437. cnss_pr_err("Spurious indication\n");
  2438. return;
  2439. }
  2440. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2441. }
  2442. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2443. struct sockaddr_qrtr *sq,
  2444. struct qmi_txn *txn, const void *data)
  2445. {
  2446. struct cnss_plat_data *plat_priv =
  2447. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2448. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2449. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2450. if (!txn) {
  2451. cnss_pr_err("Spurious indication\n");
  2452. return;
  2453. }
  2454. if (ind_msg->pwr_pin_result_valid)
  2455. plat_priv->pin_result.fw_pwr_pin_result =
  2456. ind_msg->pwr_pin_result;
  2457. if (ind_msg->phy_io_pin_result_valid)
  2458. plat_priv->pin_result.fw_phy_io_pin_result =
  2459. ind_msg->phy_io_pin_result;
  2460. if (ind_msg->rf_pin_result_valid)
  2461. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2462. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2463. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2464. ind_msg->rf_pin_result);
  2465. }
  2466. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2467. u32 cal_file_download_size)
  2468. {
  2469. struct wlfw_cal_report_req_msg_v01 req = {0};
  2470. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2471. struct qmi_txn txn;
  2472. int ret = 0;
  2473. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2474. cal_file_download_size, plat_priv->driver_state);
  2475. req.cal_file_download_size_valid = 1;
  2476. req.cal_file_download_size = cal_file_download_size;
  2477. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2478. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2479. if (ret < 0) {
  2480. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2481. ret);
  2482. goto out;
  2483. }
  2484. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2485. QMI_WLFW_CAL_REPORT_REQ_V01,
  2486. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2487. wlfw_cal_report_req_msg_v01_ei, &req);
  2488. if (ret < 0) {
  2489. qmi_txn_cancel(&txn);
  2490. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2491. ret);
  2492. goto out;
  2493. }
  2494. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2495. if (ret < 0) {
  2496. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2497. ret);
  2498. goto out;
  2499. }
  2500. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2501. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2502. resp.resp.result, resp.resp.error);
  2503. ret = -resp.resp.result;
  2504. goto out;
  2505. }
  2506. out:
  2507. return ret;
  2508. }
  2509. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2510. struct sockaddr_qrtr *sq,
  2511. struct qmi_txn *txn, const void *data)
  2512. {
  2513. struct cnss_plat_data *plat_priv =
  2514. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2515. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2516. struct cnss_cal_info *cal_info;
  2517. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2518. ind->cal_file_upload_size);
  2519. cnss_pr_info("Calibration took %d ms\n",
  2520. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2521. if (!txn) {
  2522. cnss_pr_err("Spurious indication\n");
  2523. return;
  2524. }
  2525. if (ind->cal_file_upload_size_valid)
  2526. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2527. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2528. if (!cal_info)
  2529. return;
  2530. cal_info->cal_status = CNSS_CAL_DONE;
  2531. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2532. 0, cal_info);
  2533. }
  2534. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2535. struct sockaddr_qrtr *sq,
  2536. struct qmi_txn *txn,
  2537. const void *data)
  2538. {
  2539. struct cnss_plat_data *plat_priv =
  2540. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2541. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2542. int i;
  2543. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2544. if (!txn) {
  2545. cnss_pr_err("Spurious indication\n");
  2546. return;
  2547. }
  2548. if (plat_priv->qdss_mem_seg_len) {
  2549. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2550. plat_priv->qdss_mem_seg_len);
  2551. return;
  2552. }
  2553. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2554. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2555. return;
  2556. }
  2557. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2558. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2559. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2560. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2561. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2562. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2563. }
  2564. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2565. 0, NULL);
  2566. }
  2567. /**
  2568. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2569. *
  2570. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2571. * fw memory segment for dumping to file system. Only one type of mem can be
  2572. * saved per indication and is provided in mem seg index 0.
  2573. *
  2574. * Return: None
  2575. */
  2576. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2577. struct sockaddr_qrtr *sq,
  2578. struct qmi_txn *txn,
  2579. const void *data)
  2580. {
  2581. struct cnss_plat_data *plat_priv =
  2582. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2583. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2584. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2585. int i = 0;
  2586. if (!txn || !data) {
  2587. cnss_pr_err("Spurious indication\n");
  2588. return;
  2589. }
  2590. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2591. ind_msg->source, ind_msg->mem_seg_valid,
  2592. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2593. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2594. if (!event_data)
  2595. return;
  2596. event_data->mem_type = ind_msg->mem_seg[0].type;
  2597. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2598. event_data->total_size = ind_msg->total_size;
  2599. if (ind_msg->mem_seg_valid) {
  2600. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2601. cnss_pr_err("Invalid seg len indication\n");
  2602. goto free_event_data;
  2603. }
  2604. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2605. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2606. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2607. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2608. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2609. goto free_event_data;
  2610. }
  2611. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2612. i, ind_msg->mem_seg[i].addr,
  2613. ind_msg->mem_seg[i].size);
  2614. }
  2615. }
  2616. if (ind_msg->file_name_valid)
  2617. strlcpy(event_data->file_name, ind_msg->file_name,
  2618. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2619. if (ind_msg->source == 1) {
  2620. if (!ind_msg->file_name_valid)
  2621. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2622. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2623. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2624. 0, event_data);
  2625. } else {
  2626. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2627. if (!ind_msg->file_name_valid)
  2628. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2629. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2630. } else {
  2631. if (!ind_msg->file_name_valid)
  2632. strlcpy(event_data->file_name, "fw_mem_dump",
  2633. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2634. }
  2635. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2636. 0, event_data);
  2637. }
  2638. return;
  2639. free_event_data:
  2640. kfree(event_data);
  2641. }
  2642. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2643. struct sockaddr_qrtr *sq,
  2644. struct qmi_txn *txn,
  2645. const void *data)
  2646. {
  2647. struct cnss_plat_data *plat_priv =
  2648. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2649. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2650. 0, NULL);
  2651. }
  2652. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2653. struct sockaddr_qrtr *sq,
  2654. struct qmi_txn *txn,
  2655. const void *data)
  2656. {
  2657. struct cnss_plat_data *plat_priv =
  2658. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2659. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2660. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2661. if (!txn) {
  2662. cnss_pr_err("Spurious indication\n");
  2663. return;
  2664. }
  2665. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2666. ind_msg->data_len, ind_msg->type,
  2667. ind_msg->is_last, ind_msg->seq_no);
  2668. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2669. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2670. (void *)ind_msg->data,
  2671. ind_msg->data_len);
  2672. }
  2673. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2674. (struct cnss_plat_data *plat_priv,
  2675. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2676. {
  2677. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2678. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2679. struct qmi_txn txn;
  2680. int ret = 0;
  2681. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2682. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2683. return -EINVAL;
  2684. }
  2685. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2686. if (!req)
  2687. return -ENOMEM;
  2688. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2689. if (!resp) {
  2690. kfree(req);
  2691. return -ENOMEM;
  2692. }
  2693. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2694. req->twt_sta_start = ind_msg->twt_sta_start;
  2695. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2696. req->twt_sta_int = ind_msg->twt_sta_int;
  2697. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2698. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2699. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2700. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2701. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2702. req->twt_sta_dl = req->twt_sta_dl;
  2703. req->twt_sta_config_changed_valid =
  2704. ind_msg->twt_sta_config_changed_valid;
  2705. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2706. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2707. plat_priv->driver_state);
  2708. ret =
  2709. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2710. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2711. resp);
  2712. if (ret < 0) {
  2713. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2714. ret);
  2715. goto out;
  2716. }
  2717. ret =
  2718. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2719. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2720. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2721. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2722. if (ret < 0) {
  2723. qmi_txn_cancel(&txn);
  2724. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2725. goto out;
  2726. }
  2727. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2728. if (ret < 0) {
  2729. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2730. goto out;
  2731. }
  2732. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2733. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2734. resp->resp.result, resp->resp.error);
  2735. ret = -resp->resp.result;
  2736. goto out;
  2737. }
  2738. ret = 0;
  2739. out:
  2740. kfree(req);
  2741. kfree(resp);
  2742. return ret;
  2743. }
  2744. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2745. void *data)
  2746. {
  2747. int ret;
  2748. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2749. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2750. kfree(data);
  2751. return ret;
  2752. }
  2753. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2754. struct sockaddr_qrtr *sq,
  2755. struct qmi_txn *txn,
  2756. const void *data)
  2757. {
  2758. struct cnss_plat_data *plat_priv =
  2759. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2760. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2761. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2762. if (!txn) {
  2763. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2764. return;
  2765. }
  2766. if (!ind_msg) {
  2767. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2768. return;
  2769. }
  2770. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2771. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2772. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2773. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2774. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2775. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2776. ind_msg->twt_sta_config_changed_valid,
  2777. ind_msg->twt_sta_config_changed);
  2778. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2779. if (!event_data)
  2780. return;
  2781. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2782. event_data);
  2783. }
  2784. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2785. {
  2786. .type = QMI_INDICATION,
  2787. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2788. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2789. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2790. .fn = cnss_wlfw_request_mem_ind_cb
  2791. },
  2792. {
  2793. .type = QMI_INDICATION,
  2794. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2795. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2796. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2797. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2798. },
  2799. {
  2800. .type = QMI_INDICATION,
  2801. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2802. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2803. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2804. .fn = cnss_wlfw_fw_ready_ind_cb
  2805. },
  2806. {
  2807. .type = QMI_INDICATION,
  2808. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2809. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2810. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2811. .fn = cnss_wlfw_fw_init_done_ind_cb
  2812. },
  2813. {
  2814. .type = QMI_INDICATION,
  2815. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2816. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2817. .decoded_size =
  2818. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2819. .fn = cnss_wlfw_pin_result_ind_cb
  2820. },
  2821. {
  2822. .type = QMI_INDICATION,
  2823. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2824. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2825. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2826. .fn = cnss_wlfw_cal_done_ind_cb
  2827. },
  2828. {
  2829. .type = QMI_INDICATION,
  2830. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2831. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2832. .decoded_size =
  2833. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2834. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2835. },
  2836. {
  2837. .type = QMI_INDICATION,
  2838. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2839. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2840. .decoded_size =
  2841. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2842. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2843. },
  2844. {
  2845. .type = QMI_INDICATION,
  2846. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2847. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2848. .decoded_size =
  2849. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2850. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2851. },
  2852. {
  2853. .type = QMI_INDICATION,
  2854. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2855. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2856. .decoded_size =
  2857. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2858. .fn = cnss_wlfw_respond_get_info_ind_cb
  2859. },
  2860. {
  2861. .type = QMI_INDICATION,
  2862. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2863. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2864. .decoded_size =
  2865. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2866. .fn = cnss_wlfw_process_twt_cfg_ind
  2867. },
  2868. {}
  2869. };
  2870. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2871. void *data)
  2872. {
  2873. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2874. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2875. struct sockaddr_qrtr sq = { 0 };
  2876. int ret = 0;
  2877. if (!event_data)
  2878. return -EINVAL;
  2879. sq.sq_family = AF_QIPCRTR;
  2880. sq.sq_node = event_data->node;
  2881. sq.sq_port = event_data->port;
  2882. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2883. sizeof(sq), 0);
  2884. if (ret < 0) {
  2885. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2886. goto out;
  2887. }
  2888. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2889. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2890. plat_priv->driver_state);
  2891. kfree(data);
  2892. return 0;
  2893. out:
  2894. CNSS_QMI_ASSERT();
  2895. kfree(data);
  2896. return ret;
  2897. }
  2898. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2899. {
  2900. int ret = 0;
  2901. if (!plat_priv)
  2902. return -ENODEV;
  2903. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2904. cnss_pr_err("Unexpected WLFW server arrive\n");
  2905. CNSS_ASSERT(0);
  2906. return -EINVAL;
  2907. }
  2908. cnss_ignore_qmi_failure(false);
  2909. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2910. if (ret < 0)
  2911. goto out;
  2912. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2913. if (ret < 0) {
  2914. if (ret == -EALREADY)
  2915. ret = 0;
  2916. goto out;
  2917. }
  2918. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2919. if (ret < 0)
  2920. goto out;
  2921. return 0;
  2922. out:
  2923. return ret;
  2924. }
  2925. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2926. {
  2927. int ret;
  2928. if (!plat_priv)
  2929. return -ENODEV;
  2930. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2931. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2932. plat_priv->driver_state);
  2933. cnss_qmi_deinit(plat_priv);
  2934. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2935. ret = cnss_qmi_init(plat_priv);
  2936. if (ret < 0) {
  2937. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2938. CNSS_ASSERT(0);
  2939. }
  2940. return 0;
  2941. }
  2942. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2943. struct qmi_service *service)
  2944. {
  2945. struct cnss_plat_data *plat_priv =
  2946. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2947. struct cnss_qmi_event_server_arrive_data *event_data;
  2948. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2949. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2950. plat_priv->driver_state);
  2951. return 0;
  2952. }
  2953. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2954. service->node, service->port);
  2955. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2956. if (!event_data)
  2957. return -ENOMEM;
  2958. event_data->node = service->node;
  2959. event_data->port = service->port;
  2960. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2961. 0, event_data);
  2962. return 0;
  2963. }
  2964. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2965. struct qmi_service *service)
  2966. {
  2967. struct cnss_plat_data *plat_priv =
  2968. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2969. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2970. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2971. plat_priv->driver_state);
  2972. return;
  2973. }
  2974. cnss_pr_dbg("WLFW server exiting\n");
  2975. if (plat_priv) {
  2976. cnss_ignore_qmi_failure(true);
  2977. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2978. }
  2979. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2980. 0, NULL);
  2981. }
  2982. static struct qmi_ops qmi_wlfw_ops = {
  2983. .new_server = wlfw_new_server,
  2984. .del_server = wlfw_del_server,
  2985. };
  2986. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2987. {
  2988. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2989. /* In order to support dual wlan card attach case,
  2990. * need separate qmi service instance id for each dev
  2991. */
  2992. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  2993. plat_priv->wlfw_service_instance_id != 0)
  2994. id = plat_priv->wlfw_service_instance_id;
  2995. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2996. WLFW_SERVICE_VERS_V01, id);
  2997. }
  2998. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2999. {
  3000. int ret = 0;
  3001. cnss_get_qrtr_info(plat_priv);
  3002. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  3003. QMI_WLFW_MAX_RECV_BUF_SIZE,
  3004. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  3005. if (ret < 0) {
  3006. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  3007. ret);
  3008. goto out;
  3009. }
  3010. ret = cnss_qmi_add_lookup(plat_priv);
  3011. if (ret < 0)
  3012. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3013. out:
  3014. return ret;
  3015. }
  3016. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3017. {
  3018. qmi_handle_release(&plat_priv->qmi_wlfw);
  3019. }
  3020. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3021. {
  3022. struct dms_get_mac_address_req_msg_v01 req;
  3023. struct dms_get_mac_address_resp_msg_v01 resp;
  3024. struct qmi_txn txn;
  3025. int ret = 0;
  3026. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3027. cnss_pr_err("DMS QMI connection not established\n");
  3028. return -EINVAL;
  3029. }
  3030. cnss_pr_dbg("Requesting DMS MAC address");
  3031. memset(&resp, 0, sizeof(resp));
  3032. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3033. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3034. if (ret < 0) {
  3035. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3036. ret);
  3037. goto out;
  3038. }
  3039. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3040. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3041. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3042. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3043. dms_get_mac_address_req_msg_v01_ei, &req);
  3044. if (ret < 0) {
  3045. qmi_txn_cancel(&txn);
  3046. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3047. ret);
  3048. goto out;
  3049. }
  3050. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3051. if (ret < 0) {
  3052. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3053. ret);
  3054. goto out;
  3055. }
  3056. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3057. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3058. resp.resp.result, resp.resp.error);
  3059. ret = -resp.resp.result;
  3060. goto out;
  3061. }
  3062. if (!resp.mac_address_valid ||
  3063. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3064. cnss_pr_err("Invalid MAC address received from DMS\n");
  3065. plat_priv->dms.mac_valid = false;
  3066. goto out;
  3067. }
  3068. plat_priv->dms.mac_valid = true;
  3069. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3070. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3071. out:
  3072. return ret;
  3073. }
  3074. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3075. unsigned int node, unsigned int port)
  3076. {
  3077. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3078. struct sockaddr_qrtr sq = {0};
  3079. int ret = 0;
  3080. sq.sq_family = AF_QIPCRTR;
  3081. sq.sq_node = node;
  3082. sq.sq_port = port;
  3083. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3084. sizeof(sq), 0);
  3085. if (ret < 0) {
  3086. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3087. node, port);
  3088. goto out;
  3089. }
  3090. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3091. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3092. plat_priv->driver_state);
  3093. out:
  3094. return ret;
  3095. }
  3096. static int dms_new_server(struct qmi_handle *qmi_dms,
  3097. struct qmi_service *service)
  3098. {
  3099. struct cnss_plat_data *plat_priv =
  3100. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3101. if (!service)
  3102. return -EINVAL;
  3103. return cnss_dms_connect_to_server(plat_priv, service->node,
  3104. service->port);
  3105. }
  3106. static void cnss_dms_server_exit_work(struct work_struct *work)
  3107. {
  3108. int ret;
  3109. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3110. cnss_dms_deinit(plat_priv);
  3111. cnss_pr_info("QMI DMS Server Exit");
  3112. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3113. ret = cnss_dms_init(plat_priv);
  3114. if (ret < 0)
  3115. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3116. }
  3117. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3118. static void dms_del_server(struct qmi_handle *qmi_dms,
  3119. struct qmi_service *service)
  3120. {
  3121. struct cnss_plat_data *plat_priv =
  3122. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3123. if (!plat_priv)
  3124. return;
  3125. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3126. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3127. plat_priv->driver_state);
  3128. return;
  3129. }
  3130. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3131. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3132. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3133. plat_priv->driver_state);
  3134. schedule_work(&cnss_dms_del_work);
  3135. }
  3136. void cnss_cancel_dms_work(void)
  3137. {
  3138. cancel_work_sync(&cnss_dms_del_work);
  3139. }
  3140. static struct qmi_ops qmi_dms_ops = {
  3141. .new_server = dms_new_server,
  3142. .del_server = dms_del_server,
  3143. };
  3144. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3145. {
  3146. int ret = 0;
  3147. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3148. &qmi_dms_ops, NULL);
  3149. if (ret < 0) {
  3150. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3151. goto out;
  3152. }
  3153. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3154. DMS_SERVICE_VERS_V01, 0);
  3155. if (ret < 0)
  3156. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3157. out:
  3158. return ret;
  3159. }
  3160. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3161. {
  3162. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3163. qmi_handle_release(&plat_priv->qmi_dms);
  3164. }
  3165. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3166. {
  3167. int ret;
  3168. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3169. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3170. struct qmi_txn txn;
  3171. if (!plat_priv)
  3172. return -ENODEV;
  3173. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3174. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3175. if (!req)
  3176. return -ENOMEM;
  3177. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3178. if (!resp) {
  3179. kfree(req);
  3180. return -ENOMEM;
  3181. }
  3182. req->antenna = plat_priv->antenna;
  3183. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3184. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3185. if (ret < 0) {
  3186. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3187. ret);
  3188. goto out;
  3189. }
  3190. ret = qmi_send_request
  3191. (&plat_priv->coex_qmi, NULL, &txn,
  3192. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3193. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3194. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3195. if (ret < 0) {
  3196. qmi_txn_cancel(&txn);
  3197. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3198. ret);
  3199. goto out;
  3200. }
  3201. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3202. if (ret < 0) {
  3203. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3204. ret);
  3205. goto out;
  3206. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3207. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3208. resp->resp.result, resp->resp.error);
  3209. ret = -resp->resp.result;
  3210. goto out;
  3211. }
  3212. if (resp->grant_valid)
  3213. plat_priv->grant = resp->grant;
  3214. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3215. kfree(resp);
  3216. kfree(req);
  3217. return 0;
  3218. out:
  3219. kfree(resp);
  3220. kfree(req);
  3221. return ret;
  3222. }
  3223. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3224. {
  3225. int ret;
  3226. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3227. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3228. struct qmi_txn txn;
  3229. if (!plat_priv)
  3230. return -ENODEV;
  3231. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3232. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3233. if (!req)
  3234. return -ENOMEM;
  3235. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3236. if (!resp) {
  3237. kfree(req);
  3238. return -ENOMEM;
  3239. }
  3240. req->antenna = plat_priv->antenna;
  3241. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3242. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3243. if (ret < 0) {
  3244. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3245. ret);
  3246. goto out;
  3247. }
  3248. ret = qmi_send_request
  3249. (&plat_priv->coex_qmi, NULL, &txn,
  3250. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3251. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3252. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3253. if (ret < 0) {
  3254. qmi_txn_cancel(&txn);
  3255. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3256. ret);
  3257. goto out;
  3258. }
  3259. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3260. if (ret < 0) {
  3261. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3262. ret);
  3263. goto out;
  3264. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3265. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3266. resp->resp.result, resp->resp.error);
  3267. ret = -resp->resp.result;
  3268. goto out;
  3269. }
  3270. kfree(resp);
  3271. kfree(req);
  3272. return 0;
  3273. out:
  3274. kfree(resp);
  3275. kfree(req);
  3276. return ret;
  3277. }
  3278. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3279. {
  3280. int ret;
  3281. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3282. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3283. u8 pcss_enabled;
  3284. if (!plat_priv)
  3285. return -ENODEV;
  3286. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3287. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3288. return 0;
  3289. }
  3290. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3291. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3292. req.restart_level_type_valid = 1;
  3293. req.restart_level_type = pcss_enabled;
  3294. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3295. wlfw_subsys_restart_level_req_msg_v01_ei,
  3296. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3297. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3298. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3299. QMI_WLFW_TIMEOUT_JF);
  3300. if (ret < 0)
  3301. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3302. return ret;
  3303. }
  3304. static int coex_new_server(struct qmi_handle *qmi,
  3305. struct qmi_service *service)
  3306. {
  3307. struct cnss_plat_data *plat_priv =
  3308. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3309. struct sockaddr_qrtr sq = { 0 };
  3310. int ret = 0;
  3311. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3312. service->node, service->port);
  3313. sq.sq_family = AF_QIPCRTR;
  3314. sq.sq_node = service->node;
  3315. sq.sq_port = service->port;
  3316. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3317. if (ret < 0) {
  3318. cnss_pr_err("Fail to connect to remote service port\n");
  3319. return ret;
  3320. }
  3321. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3322. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3323. plat_priv->driver_state);
  3324. return 0;
  3325. }
  3326. static void coex_del_server(struct qmi_handle *qmi,
  3327. struct qmi_service *service)
  3328. {
  3329. struct cnss_plat_data *plat_priv =
  3330. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3331. cnss_pr_dbg("COEX server exit\n");
  3332. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3333. }
  3334. static struct qmi_ops coex_qmi_ops = {
  3335. .new_server = coex_new_server,
  3336. .del_server = coex_del_server,
  3337. };
  3338. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3339. { int ret;
  3340. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3341. COEX_SERVICE_MAX_MSG_LEN,
  3342. &coex_qmi_ops, NULL);
  3343. if (ret < 0)
  3344. return ret;
  3345. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3346. COEX_SERVICE_VERS_V01, 0);
  3347. return ret;
  3348. }
  3349. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3350. {
  3351. qmi_handle_release(&plat_priv->coex_qmi);
  3352. }
  3353. /* IMS Service */
  3354. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3355. {
  3356. int ret;
  3357. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3358. struct qmi_txn *txn;
  3359. if (!plat_priv)
  3360. return -ENODEV;
  3361. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3362. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3363. if (!req)
  3364. return -ENOMEM;
  3365. req->wfc_call_status_valid = 1;
  3366. req->wfc_call_status = 1;
  3367. txn = &plat_priv->txn;
  3368. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3369. if (ret < 0) {
  3370. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3371. ret);
  3372. goto out;
  3373. }
  3374. ret = qmi_send_request
  3375. (&plat_priv->ims_qmi, NULL, txn,
  3376. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3377. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3378. ims_private_service_subscribe_for_indications_req_msg_v01_ei, req);
  3379. if (ret < 0) {
  3380. qmi_txn_cancel(txn);
  3381. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3382. ret);
  3383. goto out;
  3384. }
  3385. kfree(req);
  3386. return 0;
  3387. out:
  3388. kfree(req);
  3389. return ret;
  3390. }
  3391. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3392. struct sockaddr_qrtr *sq,
  3393. struct qmi_txn *txn,
  3394. const void *data)
  3395. {
  3396. const
  3397. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3398. data;
  3399. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3400. if (!txn) {
  3401. cnss_pr_err("spurious response\n");
  3402. return;
  3403. }
  3404. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3405. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3406. resp->resp.result, resp->resp.error);
  3407. txn->result = -resp->resp.result;
  3408. }
  3409. }
  3410. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3411. void *data)
  3412. {
  3413. int ret;
  3414. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3415. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3416. kfree(data);
  3417. return ret;
  3418. }
  3419. static void
  3420. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3421. struct sockaddr_qrtr *sq,
  3422. struct qmi_txn *txn, const void *data)
  3423. {
  3424. struct cnss_plat_data *plat_priv =
  3425. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3426. const
  3427. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3428. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3429. if (!txn) {
  3430. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3431. return;
  3432. }
  3433. if (!ind_msg) {
  3434. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3435. return;
  3436. }
  3437. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3438. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3439. ind_msg->all_wfc_calls_held,
  3440. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3441. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3442. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3443. ind_msg->media_quality_valid, ind_msg->media_quality);
  3444. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3445. if (!event_data)
  3446. return;
  3447. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3448. 0, event_data);
  3449. }
  3450. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3451. {
  3452. .type = QMI_RESPONSE,
  3453. .msg_id =
  3454. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3455. .ei =
  3456. ims_private_service_subscribe_for_indications_rsp_msg_v01_ei,
  3457. .decoded_size = sizeof(struct
  3458. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3459. .fn = ims_subscribe_for_indication_resp_cb
  3460. },
  3461. {
  3462. .type = QMI_INDICATION,
  3463. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3464. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3465. .decoded_size =
  3466. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3467. .fn = cnss_ims_process_wfc_call_ind_cb
  3468. },
  3469. {}
  3470. };
  3471. static int ims_new_server(struct qmi_handle *qmi,
  3472. struct qmi_service *service)
  3473. {
  3474. struct cnss_plat_data *plat_priv =
  3475. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3476. struct sockaddr_qrtr sq = { 0 };
  3477. int ret = 0;
  3478. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3479. service->node, service->port);
  3480. sq.sq_family = AF_QIPCRTR;
  3481. sq.sq_node = service->node;
  3482. sq.sq_port = service->port;
  3483. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3484. if (ret < 0) {
  3485. cnss_pr_err("Fail to connect to remote service port\n");
  3486. return ret;
  3487. }
  3488. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3489. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3490. plat_priv->driver_state);
  3491. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3492. return ret;
  3493. }
  3494. static void ims_del_server(struct qmi_handle *qmi,
  3495. struct qmi_service *service)
  3496. {
  3497. struct cnss_plat_data *plat_priv =
  3498. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3499. cnss_pr_dbg("IMS server exit\n");
  3500. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3501. }
  3502. static struct qmi_ops ims_qmi_ops = {
  3503. .new_server = ims_new_server,
  3504. .del_server = ims_del_server,
  3505. };
  3506. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3507. { int ret;
  3508. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3509. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3510. &ims_qmi_ops, qmi_ims_msg_handlers);
  3511. if (ret < 0)
  3512. return ret;
  3513. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3514. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3515. return ret;
  3516. }
  3517. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3518. {
  3519. qmi_handle_release(&plat_priv->ims_qmi);
  3520. }