sde_power_handle.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d]: " fmt, __func__, __LINE__
  6. #include <linux/clk.h>
  7. #include <linux/kernel.h>
  8. #include <linux/of.h>
  9. #include <linux/string.h>
  10. #include <linux/of_address.h>
  11. #include <linux/slab.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/sde_io_util.h>
  15. #include <linux/sde_rsc.h>
  16. #include "sde_power_handle.h"
  17. #include "sde_trace.h"
  18. #include "sde_dbg.h"
  19. #define KBPS2BPS(x) ((x) * 1000ULL)
  20. /* wait for at most 2 vsync for lowest refresh rate (1hz) */
  21. #define SDE_MMRM_CB_TIMEOUT_MS 2000
  22. #define SDE_MMRM_CB_TIMEOUT_JIFFIES msecs_to_jiffies( \
  23. SDE_MMRM_CB_TIMEOUT_MS)
  24. static const char *data_bus_name[SDE_POWER_HANDLE_DBUS_ID_MAX] = {
  25. [SDE_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,sde-data-bus",
  26. [SDE_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,sde-llcc-bus",
  27. [SDE_POWER_HANDLE_DBUS_ID_EBI] = "qcom,sde-ebi-bus",
  28. };
  29. const char *sde_power_handle_get_dbus_name(u32 bus_id)
  30. {
  31. if (bus_id < SDE_POWER_HANDLE_DBUS_ID_MAX)
  32. return data_bus_name[bus_id];
  33. return NULL;
  34. }
  35. static int sde_power_event_trigger_locked(struct sde_power_handle *phandle,
  36. u32 event_type)
  37. {
  38. struct sde_power_event *event;
  39. int ret = -EPERM;
  40. phandle->last_event_handled = event_type;
  41. list_for_each_entry(event, &phandle->event_list, list) {
  42. if (event->event_type & event_type) {
  43. event->cb_fnc(event_type, event->usr);
  44. ret = 0;
  45. }
  46. }
  47. return ret;
  48. }
  49. static inline void sde_power_rsc_client_init(struct sde_power_handle *phandle)
  50. {
  51. /* creates the rsc client */
  52. if (!phandle->rsc_client_init) {
  53. phandle->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX,
  54. "sde_power_handle", SDE_RSC_CLK_CLIENT, 0);
  55. if (IS_ERR_OR_NULL(phandle->rsc_client)) {
  56. pr_debug("sde rsc client create failed :%ld\n",
  57. PTR_ERR(phandle->rsc_client));
  58. phandle->rsc_client = NULL;
  59. }
  60. phandle->rsc_client_init = true;
  61. }
  62. }
  63. static int sde_power_rsc_update(struct sde_power_handle *phandle, bool enable)
  64. {
  65. u32 rsc_state;
  66. int ret = 0;
  67. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  68. if (phandle->rsc_client)
  69. ret = sde_rsc_client_state_update(phandle->rsc_client,
  70. rsc_state, NULL, SDE_RSC_INVALID_CRTC_ID, NULL);
  71. return ret;
  72. }
  73. static int sde_power_parse_dt_supply(struct platform_device *pdev,
  74. struct dss_module_power *mp)
  75. {
  76. int i = 0, rc = 0;
  77. u32 tmp = 0;
  78. struct device_node *of_node = NULL, *supply_root_node = NULL;
  79. struct device_node *supply_node = NULL;
  80. if (!pdev || !mp) {
  81. pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
  82. return -EINVAL;
  83. }
  84. of_node = pdev->dev.of_node;
  85. mp->num_vreg = 0;
  86. supply_root_node = of_get_child_by_name(of_node,
  87. "qcom,platform-supply-entries");
  88. if (!supply_root_node) {
  89. pr_debug("no supply entry present\n");
  90. return rc;
  91. }
  92. for_each_child_of_node(supply_root_node, supply_node)
  93. mp->num_vreg++;
  94. if (mp->num_vreg == 0) {
  95. pr_debug("no vreg\n");
  96. return rc;
  97. }
  98. pr_debug("vreg found. count=%d\n", mp->num_vreg);
  99. mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
  100. mp->num_vreg, GFP_KERNEL);
  101. if (!mp->vreg_config) {
  102. rc = -ENOMEM;
  103. return rc;
  104. }
  105. for_each_child_of_node(supply_root_node, supply_node) {
  106. const char *st = NULL;
  107. rc = of_property_read_string(supply_node,
  108. "qcom,supply-name", &st);
  109. if (rc) {
  110. pr_err("error reading name. rc=%d\n", rc);
  111. goto error;
  112. }
  113. strlcpy(mp->vreg_config[i].vreg_name, st,
  114. sizeof(mp->vreg_config[i].vreg_name));
  115. rc = of_property_read_u32(supply_node,
  116. "qcom,supply-min-voltage", &tmp);
  117. if (rc) {
  118. pr_err("error reading min volt. rc=%d\n", rc);
  119. goto error;
  120. }
  121. mp->vreg_config[i].min_voltage = tmp;
  122. rc = of_property_read_u32(supply_node,
  123. "qcom,supply-max-voltage", &tmp);
  124. if (rc) {
  125. pr_err("error reading max volt. rc=%d\n", rc);
  126. goto error;
  127. }
  128. mp->vreg_config[i].max_voltage = tmp;
  129. rc = of_property_read_u32(supply_node,
  130. "qcom,supply-enable-load", &tmp);
  131. if (rc) {
  132. pr_err("error reading enable load. rc=%d\n", rc);
  133. goto error;
  134. }
  135. mp->vreg_config[i].enable_load = tmp;
  136. rc = of_property_read_u32(supply_node,
  137. "qcom,supply-disable-load", &tmp);
  138. if (rc) {
  139. pr_err("error reading disable load. rc=%d\n", rc);
  140. goto error;
  141. }
  142. mp->vreg_config[i].disable_load = tmp;
  143. rc = of_property_read_u32(supply_node,
  144. "qcom,supply-pre-on-sleep", &tmp);
  145. if (rc)
  146. pr_debug("error reading supply pre sleep value. rc=%d\n",
  147. rc);
  148. mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
  149. rc = of_property_read_u32(supply_node,
  150. "qcom,supply-pre-off-sleep", &tmp);
  151. if (rc)
  152. pr_debug("error reading supply pre sleep value. rc=%d\n",
  153. rc);
  154. mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
  155. rc = of_property_read_u32(supply_node,
  156. "qcom,supply-post-on-sleep", &tmp);
  157. if (rc)
  158. pr_debug("error reading supply post sleep value. rc=%d\n",
  159. rc);
  160. mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
  161. rc = of_property_read_u32(supply_node,
  162. "qcom,supply-post-off-sleep", &tmp);
  163. if (rc)
  164. pr_debug("error reading supply post sleep value. rc=%d\n",
  165. rc);
  166. mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
  167. pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
  168. mp->vreg_config[i].vreg_name,
  169. mp->vreg_config[i].min_voltage,
  170. mp->vreg_config[i].max_voltage,
  171. mp->vreg_config[i].enable_load,
  172. mp->vreg_config[i].disable_load,
  173. mp->vreg_config[i].pre_on_sleep,
  174. mp->vreg_config[i].post_on_sleep,
  175. mp->vreg_config[i].pre_off_sleep,
  176. mp->vreg_config[i].post_off_sleep);
  177. ++i;
  178. rc = 0;
  179. }
  180. return rc;
  181. error:
  182. if (mp->vreg_config) {
  183. devm_kfree(&pdev->dev, mp->vreg_config);
  184. mp->vreg_config = NULL;
  185. mp->num_vreg = 0;
  186. }
  187. return rc;
  188. }
  189. static int sde_power_parse_dt_clock(struct platform_device *pdev,
  190. struct dss_module_power *mp)
  191. {
  192. u32 i = 0, rc = 0;
  193. const char *clock_name;
  194. u32 clock_rate = 0;
  195. u32 clock_mmrm = 0;
  196. u32 clock_max_rate = 0;
  197. int num_clk = 0;
  198. if (!pdev || !mp) {
  199. pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
  200. return -EINVAL;
  201. }
  202. mp->num_clk = 0;
  203. num_clk = of_property_count_strings(pdev->dev.of_node,
  204. "clock-names");
  205. if (num_clk <= 0) {
  206. pr_debug("clocks are not defined\n");
  207. goto clk_err;
  208. }
  209. mp->num_clk = num_clk;
  210. mp->clk_config = devm_kzalloc(&pdev->dev,
  211. sizeof(struct dss_clk) * num_clk, GFP_KERNEL);
  212. if (!mp->clk_config) {
  213. rc = -ENOMEM;
  214. mp->num_clk = 0;
  215. goto clk_err;
  216. }
  217. for (i = 0; i < num_clk; i++) {
  218. of_property_read_string_index(pdev->dev.of_node, "clock-names",
  219. i, &clock_name);
  220. strlcpy(mp->clk_config[i].clk_name, clock_name,
  221. sizeof(mp->clk_config[i].clk_name));
  222. of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
  223. i, &clock_rate);
  224. mp->clk_config[i].rate = clock_rate;
  225. if (!clock_rate)
  226. mp->clk_config[i].type = DSS_CLK_AHB;
  227. else
  228. mp->clk_config[i].type = DSS_CLK_PCLK;
  229. clock_mmrm = 0;
  230. of_property_read_u32_index(pdev->dev.of_node, "clock-mmrm",
  231. i, &clock_mmrm);
  232. if (clock_mmrm) {
  233. mp->clk_config[i].type = DSS_CLK_MMRM;
  234. mp->clk_config[i].mmrm.clk_id = clock_mmrm;
  235. }
  236. pr_debug("clk[%d]:%d mmrm:%d rate:%d name:%s dev:%s\n",
  237. i, clock_mmrm, clock_rate, clock_name,
  238. pdev->name ? pdev->name : "<unknown>");
  239. clock_max_rate = 0;
  240. of_property_read_u32_index(pdev->dev.of_node, "clock-max-rate",
  241. i, &clock_max_rate);
  242. mp->clk_config[i].max_rate = clock_max_rate;
  243. }
  244. clk_err:
  245. return rc;
  246. }
  247. #define MAX_AXI_PORT_COUNT 3
  248. static int _sde_power_data_bus_set_quota(
  249. struct sde_power_data_bus_handle *pdbus,
  250. u64 in_ab_quota, u64 in_ib_quota)
  251. {
  252. int rc = 0, i = 0;
  253. u32 paths = pdbus->data_paths_cnt;
  254. if (!paths || paths > DATA_BUS_PATH_MAX) {
  255. pr_err("invalid data bus handle, paths %d\n", paths);
  256. return -EINVAL;
  257. }
  258. in_ab_quota = div_u64(in_ab_quota, paths);
  259. SDE_ATRACE_BEGIN("msm_bus_scale_req");
  260. for (i = 0; i < paths; i++) {
  261. if (pdbus->data_bus_hdl[i]) {
  262. rc = icc_set_bw(pdbus->data_bus_hdl[i],
  263. Bps_to_icc(in_ab_quota),
  264. Bps_to_icc(in_ib_quota));
  265. if (rc)
  266. goto err;
  267. }
  268. }
  269. pdbus->curr_val.ab = in_ab_quota;
  270. pdbus->curr_val.ib = in_ib_quota;
  271. SDE_ATRACE_END("msm_bus_scale_req");
  272. return rc;
  273. err:
  274. for (; i >= 0; --i)
  275. if (pdbus->data_bus_hdl[i])
  276. icc_set_bw(pdbus->data_bus_hdl[i],
  277. Bps_to_icc(pdbus->curr_val.ab),
  278. Bps_to_icc(pdbus->curr_val.ib));
  279. SDE_ATRACE_END("msm_bus_scale_req");
  280. pr_err("failed to set data bus vote ab=%llu ib=%llu rc=%d\n",
  281. in_ab_quota, in_ib_quota, rc);
  282. return rc;
  283. }
  284. int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
  285. u32 bus_id, u64 ab_quota, u64 ib_quota)
  286. {
  287. int rc = 0;
  288. u32 paths;
  289. if (!phandle || bus_id >= SDE_POWER_HANDLE_DBUS_ID_MAX) {
  290. pr_err("invalid parameters\n");
  291. return -EINVAL;
  292. }
  293. paths = phandle->data_bus_handle[bus_id].data_paths_cnt;
  294. if (!paths)
  295. goto skip_vote;
  296. trace_sde_perf_update_bus(bus_id, ab_quota, ib_quota, paths);
  297. mutex_lock(&phandle->phandle_lock);
  298. rc = _sde_power_data_bus_set_quota(&phandle->data_bus_handle[bus_id],
  299. ab_quota, ib_quota);
  300. mutex_unlock(&phandle->phandle_lock);
  301. skip_vote:
  302. pr_debug("bus=%d, ab=%llu, ib=%llu, paths=%d\n", bus_id, ab_quota,
  303. ib_quota, paths);
  304. return rc;
  305. }
  306. /**
  307. * sde_power_icc_get - get the interconnect path for the given bus_name
  308. * @pdev - platform device
  309. * @bus_name - bus name for the corresponding interconnect
  310. * @path - the icc_path object we want to obtain for this @bus_name (output)
  311. * @count - if given, incremented only if the path was successfully retrieved
  312. **/
  313. static int sde_power_icc_get(struct platform_device *pdev,
  314. const char *bus_name, struct icc_path **path, u32 *count)
  315. {
  316. int rc = of_property_match_string(pdev->dev.of_node,
  317. "interconnect-names", bus_name);
  318. /* bus_names are optional for any given device node, skip if missing */
  319. if (rc < 0)
  320. goto end;
  321. *path = of_icc_get(&pdev->dev, bus_name);
  322. if (IS_ERR_OR_NULL(*path)) {
  323. rc = PTR_ERR(*path);
  324. pr_err("bus %s parsing failed, rc:%d\n", bus_name, rc);
  325. *path = NULL;
  326. return rc;
  327. }
  328. if (count)
  329. (*count)++;
  330. end:
  331. pr_debug("bus %s dt node %s(%d), icc_path is %s, count:%d\n",
  332. bus_name, rc < 0 ? "missing" : "found", rc,
  333. *path ? "valid" : "NULL", count ? *count : -1);
  334. return 0;
  335. }
  336. static int sde_power_reg_bus_parse(struct platform_device *pdev,
  337. struct sde_power_reg_bus_handle *reg_bus)
  338. {
  339. const char *bus_name = "qcom,sde-reg-bus";
  340. const u32 *vec_arr = NULL;
  341. int rc, len, i, vec_idx = 0;
  342. u32 paths = 0;
  343. rc = sde_power_icc_get(pdev, bus_name, &reg_bus->reg_bus_hdl, &paths);
  344. if (rc)
  345. return rc;
  346. if (!paths) {
  347. pr_debug("%s not defined for pdev %s\n", bus_name, pdev->name ?
  348. pdev->name : "<unknown>");
  349. return 0;
  350. }
  351. vec_arr = of_get_property(pdev->dev.of_node,
  352. "qcom,sde-reg-bus,vectors-KBps", &len);
  353. if (!vec_arr) {
  354. pr_err("%s scale table property not found\n", bus_name);
  355. return -EINVAL;
  356. }
  357. if (len / sizeof(*vec_arr) != VOTE_INDEX_MAX * 2) {
  358. pr_err("wrong size for %s vector table\n", bus_name);
  359. return -EINVAL;
  360. }
  361. for (i = 0; i < VOTE_INDEX_MAX; ++i) {
  362. reg_bus->scale_table[i].ab = (u64)KBPS2BPS(be32_to_cpu(
  363. vec_arr[vec_idx++]));
  364. reg_bus->scale_table[i].ib = (u64)KBPS2BPS(be32_to_cpu(
  365. vec_arr[vec_idx++]));
  366. }
  367. return rc;
  368. }
  369. static int sde_power_mnoc_bus_parse(struct platform_device *pdev,
  370. struct sde_power_data_bus_handle *pdbus, const char *name)
  371. {
  372. int i, rc = 0;
  373. char bus_name[32];
  374. for (i = 0; i < DATA_BUS_PATH_MAX; ++i) {
  375. snprintf(bus_name, sizeof(bus_name), "%s%d", name, i);
  376. rc = sde_power_icc_get(pdev, bus_name, &pdbus->data_bus_hdl[i],
  377. &pdbus->data_paths_cnt);
  378. if (rc)
  379. break;
  380. }
  381. /* at least one databus path is required */
  382. if (!pdbus->data_paths_cnt) {
  383. pr_info("mnoc interconnect path(s) not defined, rc: %d\n", rc);
  384. } else if (rc) {
  385. pr_info("ignoring error %d for non-primary data path\n", rc);
  386. rc = 0;
  387. }
  388. return rc;
  389. }
  390. static int sde_power_bus_parse(struct platform_device *pdev,
  391. struct sde_power_handle *phandle)
  392. {
  393. int i, j, ib_quota_count, rc = 0;
  394. bool active_only = false;
  395. struct sde_power_data_bus_handle *pdbus = phandle->data_bus_handle;
  396. u32 ib_quota[SDE_POWER_HANDLE_DBUS_ID_MAX];
  397. ib_quota_count = of_property_count_u32_elems(pdev->dev.of_node, "qcom,sde-ib-bw-vote");
  398. if (ib_quota_count > 0) {
  399. if (ib_quota_count != SDE_POWER_HANDLE_DBUS_ID_MAX) {
  400. pr_err("wrong size for qcom,sde-ib-bw-vote\n");
  401. return -EINVAL;
  402. }
  403. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; ++i) {
  404. of_property_read_u32_index(pdev->dev.of_node,
  405. "qcom,sde-ib-bw-vote", i, &ib_quota[i]);
  406. phandle->ib_quota[i] = ib_quota[i]*1000;
  407. }
  408. }
  409. /* reg bus */
  410. rc = sde_power_reg_bus_parse(pdev, &phandle->reg_bus_handle);
  411. if (rc)
  412. return rc;
  413. /* data buses */
  414. if (of_find_property(pdev->dev.of_node,
  415. "qcom,msm-bus,active-only", NULL))
  416. active_only = true;
  417. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  418. i < SDE_POWER_HANDLE_DBUS_ID_MAX; ++i) {
  419. if (i == SDE_POWER_HANDLE_DBUS_ID_MNOC)
  420. rc = sde_power_mnoc_bus_parse(pdev, &pdbus[i],
  421. data_bus_name[i]);
  422. else
  423. rc = sde_power_icc_get(pdev, data_bus_name[i],
  424. &pdbus[i].data_bus_hdl[0],
  425. &pdbus[i].data_paths_cnt);
  426. if (rc)
  427. break;
  428. if (active_only) {
  429. pdbus[i].bus_active_only = true;
  430. for (j = 0; j < pdbus[i].data_paths_cnt; ++j)
  431. icc_set_tag(pdbus[i].data_bus_hdl[j],
  432. QCOM_ICC_TAG_ACTIVE_ONLY);
  433. }
  434. pr_debug("found %d paths for %s\n", pdbus[i].data_paths_cnt,
  435. data_bus_name[i]);
  436. }
  437. return rc;
  438. }
  439. static void sde_power_bus_unregister(struct sde_power_handle *phandle)
  440. {
  441. int i, j;
  442. struct sde_power_reg_bus_handle *reg_bus = &phandle->reg_bus_handle;
  443. struct sde_power_data_bus_handle *pdbus = phandle->data_bus_handle;
  444. icc_put(reg_bus->reg_bus_hdl);
  445. reg_bus->reg_bus_hdl = NULL;
  446. for (i = SDE_POWER_HANDLE_DBUS_ID_MAX - 1;
  447. i >= SDE_POWER_HANDLE_DBUS_ID_MNOC; i--) {
  448. for (j = 0; j < pdbus[i].data_paths_cnt; j++) {
  449. if (pdbus[i].data_bus_hdl[j]) {
  450. icc_put(pdbus[i].data_bus_hdl[j]);
  451. pdbus[i].data_bus_hdl[j] = NULL;
  452. }
  453. }
  454. }
  455. }
  456. static int sde_power_reg_bus_update(struct sde_power_reg_bus_handle *reg_bus,
  457. u32 usecase_ndx)
  458. {
  459. int rc = 0;
  460. u64 ab_quota, ib_quota;
  461. ab_quota = reg_bus->scale_table[usecase_ndx].ab;
  462. ib_quota = reg_bus->scale_table[usecase_ndx].ib;
  463. if (reg_bus->reg_bus_hdl) {
  464. SDE_ATRACE_BEGIN("msm_bus_scale_req");
  465. rc = icc_set_bw(reg_bus->reg_bus_hdl, Bps_to_icc(ab_quota),
  466. Bps_to_icc(ib_quota));
  467. SDE_ATRACE_END("msm_bus_scale_req");
  468. }
  469. if (rc)
  470. pr_err("failed to set reg bus vote to index %d, rc=%d\n",
  471. usecase_ndx, rc);
  472. else {
  473. reg_bus->curr_idx = usecase_ndx;
  474. pr_debug("reg-bus vote set to index=%d, ab=%llu, ib=%llu\n",
  475. usecase_ndx, ab_quota, ib_quota);
  476. }
  477. return rc;
  478. }
  479. int sde_power_mmrm_set_clk_limit(struct dss_clk *clk,
  480. struct sde_power_handle *phandle, unsigned long requested_clk)
  481. {
  482. int ret;
  483. clk->mmrm.mmrm_requested_clk = requested_clk;
  484. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_ENTRY,
  485. clk->mmrm.mmrm_requested_clk);
  486. ret = sde_power_event_trigger_locked(phandle,
  487. SDE_POWER_EVENT_MMRM_CALLBACK);
  488. if (ret) {
  489. /* no crtc's present, we cannot process the cb */
  490. pr_err("error cannot process mmrm cb\n");
  491. goto exit;
  492. }
  493. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_CASE1,
  494. clk->mmrm.mmrm_requested_clk);
  495. /* wait for the request to reduce the clk */
  496. ret = wait_event_timeout(clk->mmrm.mmrm_cb_wq,
  497. clk->mmrm.mmrm_requested_clk == 0,
  498. SDE_MMRM_CB_TIMEOUT_JIFFIES);
  499. if (!ret) {
  500. /* requested clk was not reduced, fail cb */
  501. ret = -EPERM;
  502. /* Clear the request */
  503. clk->mmrm.mmrm_requested_clk = 0;
  504. pr_err("error cannot process mmrm cb clk request\n");
  505. } else {
  506. ret = 0; // Succeed, clk was reduced
  507. }
  508. exit:
  509. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, ret);
  510. return ret;
  511. }
  512. int sde_power_mmrm_callback(
  513. struct mmrm_client_notifier_data *notifier_data)
  514. {
  515. struct dss_clk_mmrm_cb *mmrm_cb_data =
  516. (struct dss_clk_mmrm_cb *)notifier_data->pvt_data;
  517. struct sde_power_handle *phandle =
  518. (struct sde_power_handle *)mmrm_cb_data->phandle;
  519. struct dss_clk *clk = mmrm_cb_data->clk;
  520. int ret = -EPERM;
  521. if (notifier_data->cb_type == MMRM_CLIENT_RESOURCE_VALUE_CHANGE) {
  522. unsigned long requested_clk =
  523. notifier_data->cb_data.val_chng.new_val;
  524. ret = sde_power_mmrm_set_clk_limit(clk, phandle, requested_clk);
  525. if (ret)
  526. pr_err("mmrm callback error reducing clk:%lu ret:%d\n",
  527. requested_clk, ret);
  528. }
  529. return ret;
  530. }
  531. u64 sde_power_mmrm_get_requested_clk(struct sde_power_handle *phandle,
  532. char *clock_name)
  533. {
  534. struct dss_module_power *mp;
  535. u64 rate = -EINVAL;
  536. int i;
  537. if (!phandle) {
  538. pr_err("invalid input power handle\n");
  539. return -EINVAL;
  540. }
  541. mp = &phandle->mp;
  542. for (i = 0; i < mp->num_clk; i++) {
  543. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  544. rate = mp->clk_config[i].mmrm.mmrm_requested_clk;
  545. break;
  546. }
  547. }
  548. return rate;
  549. }
  550. int sde_power_resource_init(struct platform_device *pdev,
  551. struct sde_power_handle *phandle)
  552. {
  553. int rc = 0;
  554. struct dss_module_power *mp;
  555. if (!phandle || !pdev) {
  556. pr_err("invalid input param\n");
  557. rc = -EINVAL;
  558. goto end;
  559. }
  560. mp = &phandle->mp;
  561. phandle->dev = &pdev->dev;
  562. /* event init must happen before mmrm register */
  563. INIT_LIST_HEAD(&phandle->event_list);
  564. rc = sde_power_parse_dt_clock(pdev, mp);
  565. if (rc) {
  566. pr_err("device clock parsing failed\n");
  567. goto end;
  568. }
  569. rc = sde_power_parse_dt_supply(pdev, mp);
  570. if (rc) {
  571. pr_err("device vreg supply parsing failed\n");
  572. goto parse_vreg_err;
  573. }
  574. rc = msm_dss_get_vreg(&pdev->dev,
  575. mp->vreg_config, mp->num_vreg, 1);
  576. if (rc) {
  577. pr_err("get config failed rc=%d\n", rc);
  578. goto vreg_err;
  579. }
  580. rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
  581. if (rc) {
  582. pr_err("clock get failed rc=%d\n", rc);
  583. goto clkget_err;
  584. }
  585. rc = msm_dss_mmrm_register(&pdev->dev, mp,
  586. sde_power_mmrm_callback, (void *)phandle,
  587. &phandle->mmrm_enable);
  588. if (rc) {
  589. pr_err("mmrm register failed rc=%d\n", rc);
  590. goto clkmmrm_err;
  591. }
  592. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  593. if (rc) {
  594. pr_err("clock set rate failed rc=%d\n", rc);
  595. goto clkset_err;
  596. }
  597. rc = sde_power_bus_parse(pdev, phandle);
  598. if (rc) {
  599. pr_err("bus parse failed rc=%d\n", rc);
  600. goto bus_err;
  601. }
  602. phandle->rsc_client = NULL;
  603. phandle->rsc_client_init = false;
  604. mutex_init(&phandle->phandle_lock);
  605. return rc;
  606. bus_err:
  607. sde_power_bus_unregister(phandle);
  608. clkset_err:
  609. msm_dss_mmrm_deregister(&pdev->dev, mp);
  610. clkmmrm_err:
  611. msm_dss_put_clk(mp->clk_config, mp->num_clk);
  612. clkget_err:
  613. msm_dss_get_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  614. vreg_err:
  615. if (mp->vreg_config)
  616. devm_kfree(&pdev->dev, mp->vreg_config);
  617. mp->num_vreg = 0;
  618. parse_vreg_err:
  619. if (mp->clk_config)
  620. devm_kfree(&pdev->dev, mp->clk_config);
  621. mp->num_clk = 0;
  622. end:
  623. return rc;
  624. }
  625. void sde_power_resource_deinit(struct platform_device *pdev,
  626. struct sde_power_handle *phandle)
  627. {
  628. struct dss_module_power *mp;
  629. struct sde_power_event *curr_event, *next_event;
  630. if (!phandle || !pdev) {
  631. pr_err("invalid input param\n");
  632. return;
  633. }
  634. mp = &phandle->mp;
  635. mutex_lock(&phandle->phandle_lock);
  636. list_for_each_entry_safe(curr_event, next_event,
  637. &phandle->event_list, list) {
  638. pr_err("event:%d, client:%s still registered\n",
  639. curr_event->event_type,
  640. curr_event->client_name);
  641. curr_event->active = false;
  642. list_del(&curr_event->list);
  643. }
  644. mutex_unlock(&phandle->phandle_lock);
  645. sde_power_bus_unregister(phandle);
  646. msm_dss_mmrm_deregister(&pdev->dev, mp);
  647. msm_dss_put_clk(mp->clk_config, mp->num_clk);
  648. msm_dss_get_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  649. if (mp->clk_config)
  650. devm_kfree(&pdev->dev, mp->clk_config);
  651. if (mp->vreg_config)
  652. devm_kfree(&pdev->dev, mp->vreg_config);
  653. mp->num_vreg = 0;
  654. mp->num_clk = 0;
  655. if (phandle->rsc_client)
  656. sde_rsc_client_destroy(phandle->rsc_client);
  657. }
  658. int sde_power_scale_reg_bus(struct sde_power_handle *phandle,
  659. u32 usecase_ndx, bool skip_lock)
  660. {
  661. int rc = 0;
  662. if (!phandle->reg_bus_handle.reg_bus_hdl)
  663. return 0;
  664. if (!skip_lock)
  665. mutex_lock(&phandle->phandle_lock);
  666. pr_debug("%pS: requested:%d\n",
  667. __builtin_return_address(0), usecase_ndx);
  668. rc = sde_power_reg_bus_update(&phandle->reg_bus_handle,
  669. usecase_ndx);
  670. if (!skip_lock)
  671. mutex_unlock(&phandle->phandle_lock);
  672. return rc;
  673. }
  674. int sde_power_resource_enable(struct sde_power_handle *phandle, bool enable)
  675. {
  676. int rc = 0, i = 0;
  677. struct dss_module_power *mp;
  678. if (!phandle) {
  679. pr_err("invalid input argument\n");
  680. return -EINVAL;
  681. }
  682. mp = &phandle->mp;
  683. mutex_lock(&phandle->phandle_lock);
  684. pr_debug("enable:%d\n", enable);
  685. SDE_ATRACE_BEGIN("sde_power_resource_enable");
  686. /* RSC client init */
  687. sde_power_rsc_client_init(phandle);
  688. if (enable) {
  689. sde_power_event_trigger_locked(phandle,
  690. SDE_POWER_EVENT_PRE_ENABLE);
  691. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  692. if (phandle->data_bus_handle[i].data_paths_cnt > 0) {
  693. rc = _sde_power_data_bus_set_quota(
  694. &phandle->data_bus_handle[i],
  695. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  696. phandle->ib_quota[i]);
  697. if (rc) {
  698. pr_err("failed to set data bus vote id=%d rc=%d\n",
  699. i, rc);
  700. goto vreg_err;
  701. }
  702. }
  703. }
  704. rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,
  705. enable);
  706. if (rc) {
  707. pr_err("failed to enable vregs rc=%d\n", rc);
  708. goto vreg_err;
  709. }
  710. rc = sde_power_scale_reg_bus(phandle, VOTE_INDEX_LOW, true);
  711. if (rc) {
  712. pr_err("failed to set reg bus vote rc=%d\n", rc);
  713. goto reg_bus_hdl_err;
  714. }
  715. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE1);
  716. rc = sde_power_rsc_update(phandle, true);
  717. if (rc) {
  718. pr_err("failed to update rsc\n");
  719. goto rsc_err;
  720. }
  721. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
  722. if (rc) {
  723. pr_err("clock enable failed rc:%d\n", rc);
  724. goto clk_err;
  725. }
  726. sde_power_event_trigger_locked(phandle,
  727. SDE_POWER_EVENT_POST_ENABLE);
  728. } else {
  729. sde_power_event_trigger_locked(phandle,
  730. SDE_POWER_EVENT_PRE_DISABLE);
  731. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE2);
  732. sde_power_rsc_update(phandle, false);
  733. msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
  734. sde_power_scale_reg_bus(phandle, VOTE_INDEX_DISABLE, true);
  735. msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
  736. for (i = SDE_POWER_HANDLE_DBUS_ID_MAX - 1; i >= 0; i--)
  737. if (phandle->data_bus_handle[i].data_paths_cnt > 0)
  738. _sde_power_data_bus_set_quota(
  739. &phandle->data_bus_handle[i],
  740. SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,
  741. SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  742. sde_power_event_trigger_locked(phandle,
  743. SDE_POWER_EVENT_POST_DISABLE);
  744. }
  745. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_EXIT);
  746. SDE_ATRACE_END("sde_power_resource_enable");
  747. mutex_unlock(&phandle->phandle_lock);
  748. return rc;
  749. clk_err:
  750. sde_power_rsc_update(phandle, false);
  751. rsc_err:
  752. sde_power_scale_reg_bus(phandle, VOTE_INDEX_DISABLE, true);
  753. reg_bus_hdl_err:
  754. msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
  755. vreg_err:
  756. for (i-- ; i >= 0 && phandle->data_bus_handle[i].data_paths_cnt > 0; i--)
  757. _sde_power_data_bus_set_quota(
  758. &phandle->data_bus_handle[i],
  759. SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,
  760. SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  761. SDE_ATRACE_END("sde_power_resource_enable");
  762. mutex_unlock(&phandle->phandle_lock);
  763. return rc;
  764. }
  765. int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name,
  766. u64 rate, u32 flags)
  767. {
  768. int i, rc = -EINVAL;
  769. struct dss_module_power *mp;
  770. if (!phandle) {
  771. pr_err("invalid input power handle\n");
  772. return -EINVAL;
  773. }
  774. /*
  775. * Return early if mmrm is disabled and the flags to reserve the mmrm
  776. * mmrm clock are set.
  777. */
  778. if (flags && !phandle->mmrm_enable) {
  779. pr_debug("mmrm disabled, return early for reserve flags\n");
  780. return 0;
  781. }
  782. mutex_lock(&phandle->phandle_lock);
  783. if (phandle->last_event_handled & SDE_POWER_EVENT_POST_DISABLE &&
  784. !flags) {
  785. pr_debug("invalid power state %u\n",
  786. phandle->last_event_handled);
  787. SDE_EVT32(phandle->last_event_handled, SDE_EVTLOG_ERROR);
  788. mutex_unlock(&phandle->phandle_lock);
  789. return -EINVAL;
  790. }
  791. mp = &phandle->mp;
  792. for (i = 0; i < mp->num_clk; i++) {
  793. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  794. if (mp->clk_config[i].max_rate &&
  795. (rate > mp->clk_config[i].max_rate))
  796. rate = mp->clk_config[i].max_rate;
  797. mp->clk_config[i].rate = rate;
  798. mp->clk_config[i].mmrm.flags = flags;
  799. pr_debug("set rate clk:%s rate:%lu flags:0x%x\n",
  800. clock_name, rate, flags);
  801. SDE_ATRACE_BEGIN("sde_clk_set_rate");
  802. rc = msm_dss_single_clk_set_rate(&mp->clk_config[i]);
  803. SDE_ATRACE_END("sde_clk_set_rate");
  804. break;
  805. }
  806. }
  807. mutex_unlock(&phandle->phandle_lock);
  808. return rc;
  809. }
  810. u64 sde_power_clk_get_rate(struct sde_power_handle *phandle, char *clock_name)
  811. {
  812. int i;
  813. struct dss_module_power *mp;
  814. u64 rate = -EINVAL;
  815. if (!phandle) {
  816. pr_err("invalid input power handle\n");
  817. return -EINVAL;
  818. }
  819. mp = &phandle->mp;
  820. for (i = 0; i < mp->num_clk; i++) {
  821. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  822. rate = clk_get_rate(mp->clk_config[i].clk);
  823. break;
  824. }
  825. }
  826. return rate;
  827. }
  828. u64 sde_power_clk_get_max_rate(struct sde_power_handle *phandle,
  829. char *clock_name)
  830. {
  831. int i;
  832. struct dss_module_power *mp;
  833. u64 rate = 0;
  834. if (!phandle) {
  835. pr_err("invalid input power handle\n");
  836. return 0;
  837. }
  838. mp = &phandle->mp;
  839. for (i = 0; i < mp->num_clk; i++) {
  840. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  841. rate = mp->clk_config[i].max_rate;
  842. break;
  843. }
  844. }
  845. return rate;
  846. }
  847. struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
  848. char *clock_name)
  849. {
  850. int i;
  851. struct dss_module_power *mp;
  852. struct clk *clk = NULL;
  853. if (!phandle) {
  854. pr_err("invalid input power handle\n");
  855. return 0;
  856. }
  857. mp = &phandle->mp;
  858. for (i = 0; i < mp->num_clk; i++) {
  859. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  860. clk = mp->clk_config[i].clk;
  861. break;
  862. }
  863. }
  864. return clk;
  865. }
  866. struct sde_power_event *sde_power_handle_register_event(
  867. struct sde_power_handle *phandle,
  868. u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  869. void *usr, char *client_name)
  870. {
  871. struct sde_power_event *event;
  872. if (!phandle) {
  873. pr_err("invalid power handle\n");
  874. return ERR_PTR(-EINVAL);
  875. } else if (!cb_fnc || !event_type) {
  876. pr_err("no callback fnc or event type\n");
  877. return ERR_PTR(-EINVAL);
  878. }
  879. event = kzalloc(sizeof(struct sde_power_event), GFP_KERNEL);
  880. if (!event)
  881. return ERR_PTR(-ENOMEM);
  882. event->event_type = event_type;
  883. event->cb_fnc = cb_fnc;
  884. event->usr = usr;
  885. strlcpy(event->client_name, client_name, MAX_CLIENT_NAME_LEN);
  886. event->active = true;
  887. mutex_lock(&phandle->phandle_lock);
  888. list_add(&event->list, &phandle->event_list);
  889. mutex_unlock(&phandle->phandle_lock);
  890. return event;
  891. }
  892. void sde_power_handle_unregister_event(
  893. struct sde_power_handle *phandle,
  894. struct sde_power_event *event)
  895. {
  896. if (!phandle || !event) {
  897. pr_err("invalid phandle or event\n");
  898. } else if (!event->active) {
  899. pr_err("power handle deinit already done\n");
  900. kfree(event);
  901. } else {
  902. mutex_lock(&phandle->phandle_lock);
  903. list_del_init(&event->list);
  904. mutex_unlock(&phandle->phandle_lock);
  905. kfree(event);
  906. }
  907. }