sde_rm.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s] " fmt, __func__
  6. #include "sde_kms.h"
  7. #include "sde_hw_lm.h"
  8. #include "sde_hw_ctl.h"
  9. #include "sde_hw_cdm.h"
  10. #include "sde_hw_dspp.h"
  11. #include "sde_hw_ds.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_intf.h"
  14. #include "sde_hw_wb.h"
  15. #include "sde_encoder.h"
  16. #include "sde_connector.h"
  17. #include "sde_hw_dsc.h"
  18. #include "sde_hw_vdc.h"
  19. #include "sde_crtc.h"
  20. #include "sde_hw_qdss.h"
  21. #define RESERVED_BY_OTHER(h, r) \
  22. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  23. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  24. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  25. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  26. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  27. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  28. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  29. #define RM_RQ_DCWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DCWB))
  30. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  31. (t).num_comp_enc == (r).num_enc && \
  32. (t).num_intf == (r).num_intf && \
  33. (t).comp_type == (r).comp_type)
  34. #define IS_COMPATIBLE_PP_DSC(p, d) (p % 2 == d % 2)
  35. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  36. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 16600
  37. /**
  38. * toplogy information to be used when ctl path version does not
  39. * support driving more than one interface per ctl_path
  40. */
  41. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  42. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  43. MSM_DISPLAY_COMPRESSION_NONE },
  44. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  45. MSM_DISPLAY_COMPRESSION_NONE },
  46. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  47. MSM_DISPLAY_COMPRESSION_DSC },
  48. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  49. MSM_DISPLAY_COMPRESSION_NONE },
  50. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  51. MSM_DISPLAY_COMPRESSION_DSC },
  52. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  53. MSM_DISPLAY_COMPRESSION_NONE },
  54. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  55. MSM_DISPLAY_COMPRESSION_DSC },
  56. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  57. MSM_DISPLAY_COMPRESSION_DSC },
  58. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  59. MSM_DISPLAY_COMPRESSION_NONE },
  60. };
  61. /**
  62. * topology information to be used when the ctl path version
  63. * is SDE_CTL_CFG_VERSION_1_0_0
  64. */
  65. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  66. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  67. MSM_DISPLAY_COMPRESSION_NONE },
  68. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  69. MSM_DISPLAY_COMPRESSION_NONE },
  70. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  71. MSM_DISPLAY_COMPRESSION_DSC },
  72. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  73. MSM_DISPLAY_COMPRESSION_VDC },
  74. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, false,
  75. MSM_DISPLAY_COMPRESSION_NONE },
  76. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, false,
  77. MSM_DISPLAY_COMPRESSION_DSC },
  78. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  79. MSM_DISPLAY_COMPRESSION_NONE },
  80. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  81. MSM_DISPLAY_COMPRESSION_DSC },
  82. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  83. MSM_DISPLAY_COMPRESSION_VDC },
  84. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  85. MSM_DISPLAY_COMPRESSION_DSC },
  86. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, false,
  87. MSM_DISPLAY_COMPRESSION_NONE },
  88. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  89. MSM_DISPLAY_COMPRESSION_NONE },
  90. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  91. MSM_DISPLAY_COMPRESSION_DSC },
  92. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  93. MSM_DISPLAY_COMPRESSION_DSC },
  94. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  95. MSM_DISPLAY_COMPRESSION_DSC },
  96. };
  97. /**
  98. * struct sde_rm_requirements - Reservation requirements parameter bundle
  99. * @top_ctrl: topology control preference from kernel client
  100. * @top: selected topology for the display
  101. * @hw_res: Hardware resources required as reported by the encoders
  102. */
  103. struct sde_rm_requirements {
  104. uint64_t top_ctrl;
  105. const struct sde_rm_topology_def *topology;
  106. struct sde_encoder_hw_resources hw_res;
  107. };
  108. /**
  109. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  110. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  111. * By using as a tag, rather than lists of pointers to HW blocks used
  112. * we can avoid some list management since we don't know how many blocks
  113. * of each type a given use case may require.
  114. * @list: List head for list of all reservations
  115. * @seq: Global RSVP sequence number for debugging, especially for
  116. * differentiating differenct allocations for same encoder.
  117. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  118. * CRTCs may be connected to multiple Encoders.
  119. * An encoder or connector id identifies the display path.
  120. * @topology DRM<->HW topology use case
  121. */
  122. struct sde_rm_rsvp {
  123. struct list_head list;
  124. uint32_t seq;
  125. uint32_t enc_id;
  126. enum sde_rm_topology_name topology;
  127. };
  128. /**
  129. * struct sde_rm_hw_blk - hardware block tracking list member
  130. * @list: List head for list of all hardware blocks tracking items
  131. * @rsvp: Pointer to use case reservation if reserved by a client
  132. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  133. * request. Will be swapped into rsvp if proposal is accepted
  134. * @type: Type of hardware block this structure tracks
  135. * @id: Hardware ID number, within it's own space, ie. LM_X
  136. * @catalog: Pointer to the hardware catalog entry for this block
  137. * @hw: Pointer to the hardware register access object for this block
  138. */
  139. struct sde_rm_hw_blk {
  140. struct list_head list;
  141. struct sde_rm_rsvp *rsvp;
  142. struct sde_rm_rsvp *rsvp_nxt;
  143. enum sde_hw_blk_type type;
  144. uint32_t id;
  145. struct sde_hw_blk *hw;
  146. };
  147. /**
  148. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  149. */
  150. enum sde_rm_dbg_rsvp_stage {
  151. SDE_RM_STAGE_BEGIN,
  152. SDE_RM_STAGE_AFTER_CLEAR,
  153. SDE_RM_STAGE_AFTER_RSVPNEXT,
  154. SDE_RM_STAGE_FINAL
  155. };
  156. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  157. struct msm_resource_caps_info *avail_res,
  158. struct sde_rm_hw_blk *blk)
  159. {
  160. struct sde_rm_hw_blk *blk2;
  161. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  162. avail_res->num_lm++;
  163. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  164. /* Check for 3d muxes by comparing paired lms */
  165. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  166. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  167. /*
  168. * If lm2 is free, or
  169. * lm1 & lm2 reserved by same enc, check mask
  170. */
  171. if ((!blk2->rsvp || (blk->rsvp &&
  172. blk2->rsvp->enc_id == blk->rsvp->enc_id
  173. && lm_cfg->id > lm_cfg2->id)) &&
  174. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  175. avail_res->num_3dmux++;
  176. }
  177. }
  178. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  179. struct msm_resource_caps_info *avail_res,
  180. struct sde_rm_hw_blk *blk)
  181. {
  182. struct sde_rm_hw_blk *blk2;
  183. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  184. avail_res->num_lm--;
  185. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  186. /* Check for 3d muxes by comparing paired lms */
  187. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  188. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  189. /* If lm2 is free and lm1 is now being reserved */
  190. if (!blk2->rsvp &&
  191. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  192. avail_res->num_3dmux--;
  193. }
  194. }
  195. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  196. struct msm_resource_caps_info *avail_res,
  197. struct sde_rm_hw_blk *blk)
  198. {
  199. enum sde_hw_blk_type type = blk->type;
  200. if (type == SDE_HW_BLK_LM)
  201. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  202. else if (type == SDE_HW_BLK_CTL)
  203. avail_res->num_ctl++;
  204. else if (type == SDE_HW_BLK_DSC)
  205. avail_res->num_dsc++;
  206. else if (type == SDE_HW_BLK_VDC)
  207. avail_res->num_vdc++;
  208. }
  209. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  210. struct msm_resource_caps_info *avail_res,
  211. struct sde_rm_hw_blk *blk)
  212. {
  213. enum sde_hw_blk_type type = blk->type;
  214. if (type == SDE_HW_BLK_LM)
  215. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  216. else if (type == SDE_HW_BLK_CTL)
  217. avail_res->num_ctl--;
  218. else if (type == SDE_HW_BLK_DSC)
  219. avail_res->num_dsc--;
  220. else if (type == SDE_HW_BLK_VDC)
  221. avail_res->num_vdc--;
  222. }
  223. void sde_rm_get_resource_info(struct sde_rm *rm,
  224. struct drm_encoder *drm_enc,
  225. struct msm_resource_caps_info *avail_res)
  226. {
  227. struct sde_rm_hw_blk *blk;
  228. enum sde_hw_blk_type type;
  229. struct sde_rm_rsvp rsvp;
  230. memcpy(avail_res, &rm->avail_res,
  231. sizeof(rm->avail_res));
  232. if (!drm_enc)
  233. return;
  234. rsvp.enc_id = drm_enc->base.id;
  235. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  236. list_for_each_entry(blk, &rm->hw_blks[type], list)
  237. if (blk->rsvp && blk->rsvp->enc_id == rsvp.enc_id)
  238. _sde_rm_inc_resource_info(rm, avail_res, blk);
  239. }
  240. static void _sde_rm_print_rsvps(
  241. struct sde_rm *rm,
  242. enum sde_rm_dbg_rsvp_stage stage)
  243. {
  244. struct sde_rm_rsvp *rsvp;
  245. struct sde_rm_hw_blk *blk;
  246. enum sde_hw_blk_type type;
  247. SDE_DEBUG("%d\n", stage);
  248. list_for_each_entry(rsvp, &rm->rsvps, list) {
  249. SDE_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
  250. rsvp->enc_id, rsvp->topology);
  251. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
  252. }
  253. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  254. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  255. if (!blk->rsvp && !blk->rsvp_nxt)
  256. continue;
  257. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  258. (blk->rsvp) ? blk->rsvp->seq : 0,
  259. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  260. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  261. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  262. blk->type, blk->id);
  263. SDE_EVT32(stage,
  264. (blk->rsvp) ? blk->rsvp->seq : 0,
  265. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  266. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  267. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  268. blk->type, blk->id);
  269. }
  270. }
  271. }
  272. static void _sde_rm_print_rsvps_by_type(
  273. struct sde_rm *rm,
  274. enum sde_hw_blk_type type)
  275. {
  276. struct sde_rm_hw_blk *blk;
  277. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  278. if (!blk->rsvp && !blk->rsvp_nxt)
  279. continue;
  280. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  281. (blk->rsvp) ? blk->rsvp->seq : 0,
  282. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  283. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  284. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  285. blk->type, blk->id);
  286. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  287. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  288. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  289. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  290. blk->type, blk->id);
  291. }
  292. }
  293. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  294. {
  295. return rm->hw_mdp;
  296. }
  297. void sde_rm_init_hw_iter(
  298. struct sde_rm_hw_iter *iter,
  299. uint32_t enc_id,
  300. enum sde_hw_blk_type type)
  301. {
  302. memset(iter, 0, sizeof(*iter));
  303. iter->enc_id = enc_id;
  304. iter->type = type;
  305. }
  306. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  307. struct msm_display_topology topology)
  308. {
  309. int i;
  310. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  311. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  312. topology))
  313. return rm->topology_tbl[i].top_name;
  314. return SDE_RM_TOPOLOGY_NONE;
  315. }
  316. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  317. {
  318. struct list_head *blk_list;
  319. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  320. SDE_ERROR("invalid rm\n");
  321. return false;
  322. }
  323. i->hw = NULL;
  324. blk_list = &rm->hw_blks[i->type];
  325. if (i->blk && (&i->blk->list == blk_list)) {
  326. SDE_DEBUG("attempt resume iteration past last\n");
  327. return false;
  328. }
  329. i->blk = list_prepare_entry(i->blk, blk_list, list);
  330. list_for_each_entry_continue(i->blk, blk_list, list) {
  331. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  332. if (i->blk->type != i->type) {
  333. SDE_ERROR("found incorrect block type %d on %d list\n",
  334. i->blk->type, i->type);
  335. return false;
  336. }
  337. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  338. i->hw = i->blk->hw;
  339. SDE_DEBUG("found type %d id %d for enc %d\n",
  340. i->type, i->blk->id, i->enc_id);
  341. return true;
  342. }
  343. }
  344. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  345. return false;
  346. }
  347. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  348. struct sde_rm_hw_request *hw_blk_info)
  349. {
  350. struct list_head *blk_list;
  351. struct sde_rm_hw_blk *blk = NULL;
  352. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  353. SDE_ERROR("invalid rm\n");
  354. return false;
  355. }
  356. hw_blk_info->hw = NULL;
  357. blk_list = &rm->hw_blks[hw_blk_info->type];
  358. blk = list_prepare_entry(blk, blk_list, list);
  359. list_for_each_entry_continue(blk, blk_list, list) {
  360. if (blk->type != hw_blk_info->type) {
  361. SDE_ERROR("found incorrect block type %d on %d list\n",
  362. blk->type, hw_blk_info->type);
  363. return false;
  364. }
  365. if (blk->hw->id == hw_blk_info->id) {
  366. hw_blk_info->hw = blk->hw;
  367. SDE_DEBUG("found type %d id %d\n",
  368. blk->type, blk->id);
  369. return true;
  370. }
  371. }
  372. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  373. hw_blk_info->id);
  374. return false;
  375. }
  376. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  377. {
  378. bool ret;
  379. mutex_lock(&rm->rm_lock);
  380. ret = _sde_rm_get_hw_locked(rm, i);
  381. mutex_unlock(&rm->rm_lock);
  382. return ret;
  383. }
  384. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  385. {
  386. bool ret;
  387. mutex_lock(&rm->rm_lock);
  388. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  389. mutex_unlock(&rm->rm_lock);
  390. return ret;
  391. }
  392. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, void *hw)
  393. {
  394. switch (type) {
  395. case SDE_HW_BLK_LM:
  396. sde_hw_lm_destroy(hw);
  397. break;
  398. case SDE_HW_BLK_DSPP:
  399. sde_hw_dspp_destroy(hw);
  400. break;
  401. case SDE_HW_BLK_DS:
  402. sde_hw_ds_destroy(hw);
  403. break;
  404. case SDE_HW_BLK_CTL:
  405. sde_hw_ctl_destroy(hw);
  406. break;
  407. case SDE_HW_BLK_CDM:
  408. sde_hw_cdm_destroy(hw);
  409. break;
  410. case SDE_HW_BLK_PINGPONG:
  411. sde_hw_pingpong_destroy(hw);
  412. break;
  413. case SDE_HW_BLK_INTF:
  414. sde_hw_intf_destroy(hw);
  415. break;
  416. case SDE_HW_BLK_WB:
  417. sde_hw_wb_destroy(hw);
  418. break;
  419. case SDE_HW_BLK_DSC:
  420. sde_hw_dsc_destroy(hw);
  421. break;
  422. case SDE_HW_BLK_VDC:
  423. sde_hw_vdc_destroy(hw);
  424. break;
  425. case SDE_HW_BLK_QDSS:
  426. sde_hw_qdss_destroy(hw);
  427. break;
  428. case SDE_HW_BLK_SSPP:
  429. /* SSPPs are not managed by the resource manager */
  430. case SDE_HW_BLK_TOP:
  431. /* Top is a singleton, not managed in hw_blks list */
  432. case SDE_HW_BLK_MAX:
  433. default:
  434. SDE_ERROR("unsupported block type %d\n", type);
  435. break;
  436. }
  437. }
  438. int sde_rm_destroy(struct sde_rm *rm)
  439. {
  440. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  441. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  442. enum sde_hw_blk_type type;
  443. if (!rm) {
  444. SDE_ERROR("invalid rm\n");
  445. return -EINVAL;
  446. }
  447. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  448. list_del(&rsvp_cur->list);
  449. kfree(rsvp_cur);
  450. }
  451. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  452. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  453. list) {
  454. list_del(&hw_cur->list);
  455. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  456. kfree(hw_cur);
  457. }
  458. }
  459. sde_hw_mdp_destroy(rm->hw_mdp);
  460. rm->hw_mdp = NULL;
  461. mutex_destroy(&rm->rm_lock);
  462. return 0;
  463. }
  464. static int _sde_rm_hw_blk_create(
  465. struct sde_rm *rm,
  466. struct sde_mdss_cfg *cat,
  467. void __iomem *mmio,
  468. enum sde_hw_blk_type type,
  469. uint32_t id,
  470. void *hw_catalog_info)
  471. {
  472. struct sde_rm_hw_blk *blk;
  473. struct sde_hw_mdp *hw_mdp;
  474. void *hw;
  475. hw_mdp = rm->hw_mdp;
  476. switch (type) {
  477. case SDE_HW_BLK_LM:
  478. hw = sde_hw_lm_init(id, mmio, cat);
  479. break;
  480. case SDE_HW_BLK_DSPP:
  481. hw = sde_hw_dspp_init(id, mmio, cat);
  482. break;
  483. case SDE_HW_BLK_DS:
  484. hw = sde_hw_ds_init(id, mmio, cat);
  485. break;
  486. case SDE_HW_BLK_CTL:
  487. hw = sde_hw_ctl_init(id, mmio, cat);
  488. break;
  489. case SDE_HW_BLK_CDM:
  490. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  491. break;
  492. case SDE_HW_BLK_PINGPONG:
  493. hw = sde_hw_pingpong_init(id, mmio, cat);
  494. break;
  495. case SDE_HW_BLK_INTF:
  496. hw = sde_hw_intf_init(id, mmio, cat);
  497. break;
  498. case SDE_HW_BLK_WB:
  499. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp);
  500. break;
  501. case SDE_HW_BLK_DSC:
  502. hw = sde_hw_dsc_init(id, mmio, cat);
  503. break;
  504. case SDE_HW_BLK_VDC:
  505. hw = sde_hw_vdc_init(id, mmio, cat);
  506. break;
  507. case SDE_HW_BLK_QDSS:
  508. hw = sde_hw_qdss_init(id, mmio, cat);
  509. break;
  510. case SDE_HW_BLK_SSPP:
  511. /* SSPPs are not managed by the resource manager */
  512. case SDE_HW_BLK_TOP:
  513. /* Top is a singleton, not managed in hw_blks list */
  514. case SDE_HW_BLK_MAX:
  515. default:
  516. SDE_ERROR("unsupported block type %d\n", type);
  517. return -EINVAL;
  518. }
  519. if (IS_ERR_OR_NULL(hw)) {
  520. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  521. type, PTR_ERR(hw));
  522. return -EFAULT;
  523. }
  524. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  525. if (!blk) {
  526. _sde_rm_hw_destroy(type, hw);
  527. return -ENOMEM;
  528. }
  529. blk->type = type;
  530. blk->id = id;
  531. blk->hw = hw;
  532. list_add_tail(&blk->list, &rm->hw_blks[type]);
  533. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  534. return 0;
  535. }
  536. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  537. struct sde_mdss_cfg *cat,
  538. void __iomem *mmio)
  539. {
  540. int i, rc = 0;
  541. for (i = 0; i < cat->dspp_count; i++) {
  542. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  543. cat->dspp[i].id, &cat->dspp[i]);
  544. if (rc) {
  545. SDE_ERROR("failed: dspp hw not available\n");
  546. goto fail;
  547. }
  548. }
  549. if (cat->mdp[0].has_dest_scaler) {
  550. for (i = 0; i < cat->ds_count; i++) {
  551. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  552. cat->ds[i].id, &cat->ds[i]);
  553. if (rc) {
  554. SDE_ERROR("failed: ds hw not available\n");
  555. goto fail;
  556. }
  557. }
  558. }
  559. for (i = 0; i < cat->pingpong_count; i++) {
  560. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  561. cat->pingpong[i].id, &cat->pingpong[i]);
  562. if (rc) {
  563. SDE_ERROR("failed: pp hw not available\n");
  564. goto fail;
  565. }
  566. }
  567. for (i = 0; i < cat->dsc_count; i++) {
  568. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  569. cat->dsc[i].id, &cat->dsc[i]);
  570. if (rc) {
  571. SDE_ERROR("failed: dsc hw not available\n");
  572. goto fail;
  573. }
  574. }
  575. for (i = 0; i < cat->vdc_count; i++) {
  576. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  577. cat->vdc[i].id, &cat->vdc[i]);
  578. if (rc) {
  579. SDE_ERROR("failed: vdc hw not available\n");
  580. goto fail;
  581. }
  582. }
  583. for (i = 0; i < cat->intf_count; i++) {
  584. if (cat->intf[i].type == INTF_NONE) {
  585. SDE_DEBUG("skip intf %d with type none\n", i);
  586. continue;
  587. }
  588. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  589. cat->intf[i].id, &cat->intf[i]);
  590. if (rc) {
  591. SDE_ERROR("failed: intf hw not available\n");
  592. goto fail;
  593. }
  594. }
  595. for (i = 0; i < cat->wb_count; i++) {
  596. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  597. cat->wb[i].id, &cat->wb[i]);
  598. if (rc) {
  599. SDE_ERROR("failed: wb hw not available\n");
  600. goto fail;
  601. }
  602. }
  603. for (i = 0; i < cat->ctl_count; i++) {
  604. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  605. cat->ctl[i].id, &cat->ctl[i]);
  606. if (rc) {
  607. SDE_ERROR("failed: ctl hw not available\n");
  608. goto fail;
  609. }
  610. }
  611. for (i = 0; i < cat->cdm_count; i++) {
  612. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  613. cat->cdm[i].id, &cat->cdm[i]);
  614. if (rc) {
  615. SDE_ERROR("failed: cdm hw not available\n");
  616. goto fail;
  617. }
  618. }
  619. for (i = 0; i < cat->qdss_count; i++) {
  620. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  621. cat->qdss[i].id, &cat->qdss[i]);
  622. if (rc) {
  623. SDE_ERROR("failed: qdss hw not available\n");
  624. goto fail;
  625. }
  626. }
  627. fail:
  628. return rc;
  629. }
  630. int sde_rm_init(struct sde_rm *rm,
  631. struct sde_mdss_cfg *cat,
  632. void __iomem *mmio,
  633. struct drm_device *dev)
  634. {
  635. int i, rc = 0;
  636. enum sde_hw_blk_type type;
  637. if (!rm || !cat || !mmio || !dev) {
  638. SDE_ERROR("invalid input params\n");
  639. return -EINVAL;
  640. }
  641. /* Clear, setup lists */
  642. memset(rm, 0, sizeof(*rm));
  643. mutex_init(&rm->rm_lock);
  644. INIT_LIST_HEAD(&rm->rsvps);
  645. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  646. INIT_LIST_HEAD(&rm->hw_blks[type]);
  647. rm->dev = dev;
  648. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  649. rm->topology_tbl = g_top_table_v1;
  650. else
  651. rm->topology_tbl = g_top_table;
  652. /* Some of the sub-blocks require an mdptop to be created */
  653. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  654. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  655. rc = PTR_ERR(rm->hw_mdp);
  656. rm->hw_mdp = NULL;
  657. SDE_ERROR("failed: mdp hw not available\n");
  658. goto fail;
  659. }
  660. /* Interrogate HW catalog and create tracking items for hw blocks */
  661. for (i = 0; i < cat->mixer_count; i++) {
  662. struct sde_lm_cfg *lm = &cat->mixer[i];
  663. if (lm->pingpong == PINGPONG_MAX) {
  664. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  665. goto fail;
  666. }
  667. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  668. cat->mixer[i].id, &cat->mixer[i]);
  669. if (rc) {
  670. SDE_ERROR("failed: lm hw not available\n");
  671. goto fail;
  672. }
  673. if (!rm->lm_max_width) {
  674. rm->lm_max_width = lm->sblk->maxwidth;
  675. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  676. /*
  677. * Don't expect to have hw where lm max widths differ.
  678. * If found, take the min.
  679. */
  680. SDE_ERROR("unsupported: lm maxwidth differs\n");
  681. if (rm->lm_max_width > lm->sblk->maxwidth)
  682. rm->lm_max_width = lm->sblk->maxwidth;
  683. }
  684. }
  685. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  686. if (!rc)
  687. return 0;
  688. fail:
  689. sde_rm_destroy(rm);
  690. return rc;
  691. }
  692. static bool _sde_rm_check_lm(
  693. struct sde_rm *rm,
  694. struct sde_rm_rsvp *rsvp,
  695. struct sde_rm_requirements *reqs,
  696. const struct sde_lm_cfg *lm_cfg,
  697. struct sde_rm_hw_blk *lm,
  698. struct sde_rm_hw_blk **dspp,
  699. struct sde_rm_hw_blk **ds,
  700. struct sde_rm_hw_blk **pp)
  701. {
  702. bool is_valid_dspp, is_valid_ds, ret = true;
  703. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  704. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  705. /**
  706. * RM_RQ_X: specification of which LMs to choose
  707. * is_valid_X: indicates whether LM is tied with block X
  708. * ret: true if given LM matches the user requirement,
  709. * false otherwise
  710. */
  711. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  712. ret = (is_valid_dspp && is_valid_ds);
  713. else if (RM_RQ_DSPP(reqs))
  714. ret = is_valid_dspp;
  715. else if (RM_RQ_DS(reqs))
  716. ret = is_valid_ds;
  717. if (!ret) {
  718. SDE_DEBUG(
  719. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  720. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  721. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  722. lm_cfg->ds);
  723. return ret;
  724. }
  725. return true;
  726. }
  727. static bool _sde_rm_reserve_dspp(
  728. struct sde_rm *rm,
  729. struct sde_rm_rsvp *rsvp,
  730. const struct sde_lm_cfg *lm_cfg,
  731. struct sde_rm_hw_blk *lm,
  732. struct sde_rm_hw_blk **dspp)
  733. {
  734. struct sde_rm_hw_iter iter;
  735. if (lm_cfg->dspp != DSPP_MAX) {
  736. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  737. while (_sde_rm_get_hw_locked(rm, &iter)) {
  738. if (iter.blk->id == lm_cfg->dspp) {
  739. *dspp = iter.blk;
  740. break;
  741. }
  742. }
  743. if (!*dspp) {
  744. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  745. lm_cfg->dspp);
  746. return false;
  747. }
  748. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  749. SDE_DEBUG("lm %d dspp %d already reserved\n",
  750. lm->id, (*dspp)->id);
  751. return false;
  752. }
  753. }
  754. return true;
  755. }
  756. static bool _sde_rm_reserve_ds(
  757. struct sde_rm *rm,
  758. struct sde_rm_rsvp *rsvp,
  759. const struct sde_lm_cfg *lm_cfg,
  760. struct sde_rm_hw_blk *lm,
  761. struct sde_rm_hw_blk **ds)
  762. {
  763. struct sde_rm_hw_iter iter;
  764. if (lm_cfg->ds != DS_MAX) {
  765. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  766. while (_sde_rm_get_hw_locked(rm, &iter)) {
  767. if (iter.blk->id == lm_cfg->ds) {
  768. *ds = iter.blk;
  769. break;
  770. }
  771. }
  772. if (!*ds) {
  773. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  774. lm_cfg->ds);
  775. return false;
  776. }
  777. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  778. SDE_DEBUG("lm %d ds %d already reserved\n",
  779. lm->id, (*ds)->id);
  780. return false;
  781. }
  782. }
  783. return true;
  784. }
  785. static bool _sde_rm_reserve_pp(
  786. struct sde_rm *rm,
  787. struct sde_rm_rsvp *rsvp,
  788. struct sde_rm_requirements *reqs,
  789. const struct sde_lm_cfg *lm_cfg,
  790. const struct sde_pingpong_cfg *pp_cfg,
  791. struct sde_rm_hw_blk *lm,
  792. struct sde_rm_hw_blk **dspp,
  793. struct sde_rm_hw_blk **ds,
  794. struct sde_rm_hw_blk **pp)
  795. {
  796. struct sde_rm_hw_iter iter;
  797. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  798. while (_sde_rm_get_hw_locked(rm, &iter)) {
  799. if (iter.blk->id == lm_cfg->pingpong) {
  800. *pp = iter.blk;
  801. break;
  802. }
  803. }
  804. if (!*pp) {
  805. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  806. return false;
  807. }
  808. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  809. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  810. (*pp)->id);
  811. *dspp = NULL;
  812. *ds = NULL;
  813. return false;
  814. }
  815. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  816. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  817. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  818. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  819. *dspp = NULL;
  820. *ds = NULL;
  821. return false;
  822. }
  823. return true;
  824. }
  825. /**
  826. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  827. * proposed use case requirements, incl. hardwired dependent blocks like
  828. * pingpong, and dspp.
  829. * @rm: sde resource manager handle
  830. * @rsvp: reservation currently being created
  831. * @reqs: proposed use case requirements
  832. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  833. * blocks connected to the lm (pp, dspp) are available and appropriate
  834. * @dspp: output parameter, dspp block attached to the layer mixer.
  835. * NULL if dspp was not available, or not matching requirements.
  836. * @pp: output parameter, pingpong block attached to the layer mixer.
  837. * NULL if dspp was not available, or not matching requirements.
  838. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  839. * as well as satisfying all other requirements
  840. * @Return: true if lm matches all requirements, false otherwise
  841. */
  842. static bool _sde_rm_check_lm_and_get_connected_blks(
  843. struct sde_rm *rm,
  844. struct sde_rm_rsvp *rsvp,
  845. struct sde_rm_requirements *reqs,
  846. struct sde_rm_hw_blk *lm,
  847. struct sde_rm_hw_blk **dspp,
  848. struct sde_rm_hw_blk **ds,
  849. struct sde_rm_hw_blk **pp,
  850. struct sde_rm_hw_blk *primary_lm)
  851. {
  852. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  853. const struct sde_pingpong_cfg *pp_cfg;
  854. bool ret, is_conn_primary, is_conn_secondary;
  855. u32 lm_primary_pref, lm_secondary_pref, cwb_pref, dcwb_pref;
  856. *dspp = NULL;
  857. *ds = NULL;
  858. *pp = NULL;
  859. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  860. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  861. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  862. dcwb_pref = lm_cfg->features & BIT(SDE_DISP_DCWB_PREF);
  863. is_conn_primary = (reqs->hw_res.display_type ==
  864. SDE_CONNECTOR_PRIMARY) ? true : false;
  865. is_conn_secondary = (reqs->hw_res.display_type ==
  866. SDE_CONNECTOR_SECONDARY) ? true : false;
  867. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %ld disp type %d\n",
  868. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  869. lm_cfg->features, (int)reqs->hw_res.display_type);
  870. /* Check if this layer mixer is a peer of the proposed primary LM */
  871. if (primary_lm) {
  872. const struct sde_lm_cfg *prim_lm_cfg =
  873. to_sde_hw_mixer(primary_lm->hw)->cap;
  874. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  875. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  876. prim_lm_cfg->id);
  877. return false;
  878. }
  879. }
  880. /* bypass rest of the checks if LM for primary display is found */
  881. if (!lm_primary_pref && !lm_secondary_pref) {
  882. /* Check lm for valid requirements */
  883. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  884. dspp, ds, pp);
  885. if (!ret)
  886. return ret;
  887. /**
  888. * If CWB is enabled and LM is not CWB supported
  889. * then return false.
  890. */
  891. if ((RM_RQ_CWB(reqs) && !cwb_pref) ||
  892. (RM_RQ_DCWB(reqs) && !dcwb_pref)) {
  893. SDE_DEBUG("fail: cwb/dcwb supported lm not allocated\n");
  894. return false;
  895. }
  896. } else if ((!is_conn_primary && lm_primary_pref) ||
  897. (!is_conn_secondary && lm_secondary_pref)) {
  898. SDE_DEBUG(
  899. "display preference is not met. display_type: %d lm_features: %lx\n",
  900. (int)reqs->hw_res.display_type, lm_cfg->features);
  901. return false;
  902. }
  903. /* Already reserved? */
  904. if (RESERVED_BY_OTHER(lm, rsvp)) {
  905. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  906. return false;
  907. }
  908. /* Reserve dspp */
  909. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  910. if (!ret)
  911. return ret;
  912. /* Reserve ds */
  913. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  914. if (!ret)
  915. return ret;
  916. /* Reserve pp */
  917. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  918. dspp, ds, pp);
  919. if (!ret)
  920. return ret;
  921. return true;
  922. }
  923. static int _sde_rm_reserve_lms(
  924. struct sde_rm *rm,
  925. struct sde_rm_rsvp *rsvp,
  926. struct sde_rm_requirements *reqs,
  927. u8 *_lm_ids)
  928. {
  929. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  930. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  931. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  932. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  933. struct sde_rm_hw_iter iter_i, iter_j;
  934. u32 lm_mask = 0;
  935. int lm_count = 0;
  936. int i, rc = 0;
  937. if (!reqs->topology->num_lm) {
  938. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  939. return 0;
  940. }
  941. /* Find a primary mixer */
  942. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  943. while (lm_count != reqs->topology->num_lm &&
  944. _sde_rm_get_hw_locked(rm, &iter_i)) {
  945. if (lm_mask & (1 << iter_i.blk->id))
  946. continue;
  947. lm[lm_count] = iter_i.blk;
  948. dspp[lm_count] = NULL;
  949. ds[lm_count] = NULL;
  950. pp[lm_count] = NULL;
  951. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  952. iter_i.blk->id,
  953. lm_count,
  954. _lm_ids ? _lm_ids[lm_count] : -1);
  955. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  956. continue;
  957. if (!_sde_rm_check_lm_and_get_connected_blks(
  958. rm, rsvp, reqs, lm[lm_count],
  959. &dspp[lm_count], &ds[lm_count],
  960. &pp[lm_count], NULL))
  961. continue;
  962. lm_mask |= (1 << iter_i.blk->id);
  963. ++lm_count;
  964. /* Return if peer is not needed */
  965. if (lm_count == reqs->topology->num_lm)
  966. break;
  967. /* Valid primary mixer found, find matching peers */
  968. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  969. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  970. if (lm_mask & (1 << iter_j.blk->id))
  971. continue;
  972. lm[lm_count] = iter_j.blk;
  973. dspp[lm_count] = NULL;
  974. ds[lm_count] = NULL;
  975. pp[lm_count] = NULL;
  976. if (!_sde_rm_check_lm_and_get_connected_blks(
  977. rm, rsvp, reqs, iter_j.blk,
  978. &dspp[lm_count], &ds[lm_count],
  979. &pp[lm_count], iter_i.blk))
  980. continue;
  981. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  982. iter_j.blk->id,
  983. lm_count,
  984. _lm_ids ? _lm_ids[lm_count] : -1);
  985. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  986. continue;
  987. lm_mask |= (1 << iter_j.blk->id);
  988. ++lm_count;
  989. break;
  990. }
  991. /* Rollback primary LM if peer is not found */
  992. if (!iter_j.hw) {
  993. lm_mask &= ~(1 << iter_i.blk->id);
  994. --lm_count;
  995. }
  996. }
  997. if (lm_count != reqs->topology->num_lm) {
  998. SDE_DEBUG("unable to find appropriate mixers\n");
  999. return -ENAVAIL;
  1000. }
  1001. for (i = 0; i < lm_count; i++) {
  1002. lm[i]->rsvp_nxt = rsvp;
  1003. pp[i]->rsvp_nxt = rsvp;
  1004. if (dspp[i])
  1005. dspp[i]->rsvp_nxt = rsvp;
  1006. if (ds[i])
  1007. ds[i]->rsvp_nxt = rsvp;
  1008. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1009. dspp[i] ? dspp[i]->id : 0,
  1010. ds[i] ? ds[i]->id : 0);
  1011. }
  1012. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1013. /* reserve a free PINGPONG_SLAVE block */
  1014. rc = -ENAVAIL;
  1015. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1016. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1017. const struct sde_hw_pingpong *pp =
  1018. to_sde_hw_pingpong(iter_i.blk->hw);
  1019. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1020. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1021. continue;
  1022. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1023. continue;
  1024. iter_i.blk->rsvp_nxt = rsvp;
  1025. rc = 0;
  1026. break;
  1027. }
  1028. }
  1029. return rc;
  1030. }
  1031. static int _sde_rm_reserve_ctls(
  1032. struct sde_rm *rm,
  1033. struct sde_rm_rsvp *rsvp,
  1034. struct sde_rm_requirements *reqs,
  1035. const struct sde_rm_topology_def *top,
  1036. u8 *_ctl_ids)
  1037. {
  1038. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1039. struct sde_rm_hw_iter iter;
  1040. int i = 0;
  1041. if (!top->num_ctl) {
  1042. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1043. return 0;
  1044. }
  1045. memset(&ctls, 0, sizeof(ctls));
  1046. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1047. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1048. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1049. unsigned long features = ctl->caps->features;
  1050. bool has_split_display, has_ppsplit, primary_pref;
  1051. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1052. continue;
  1053. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1054. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1055. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1056. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1057. /*
  1058. * bypass rest feature checks on finding CTL preferred
  1059. * for primary displays.
  1060. */
  1061. if (!primary_pref && !_ctl_ids) {
  1062. if (top->needs_split_display != has_split_display)
  1063. continue;
  1064. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1065. !has_ppsplit)
  1066. continue;
  1067. } else if (!(reqs->hw_res.display_type ==
  1068. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1069. SDE_DEBUG(
  1070. "display pref not met. display_type: %d primary_pref: %d\n",
  1071. reqs->hw_res.display_type, primary_pref);
  1072. continue;
  1073. }
  1074. ctls[i] = iter.blk;
  1075. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1076. iter.blk->id, i,
  1077. _ctl_ids ? _ctl_ids[i] : -1);
  1078. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1079. continue;
  1080. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1081. if (++i == top->num_ctl)
  1082. break;
  1083. }
  1084. if (i != top->num_ctl)
  1085. return -ENAVAIL;
  1086. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1087. ctls[i]->rsvp_nxt = rsvp;
  1088. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1089. }
  1090. return 0;
  1091. }
  1092. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1093. struct sde_rm_rsvp *rsvp,
  1094. struct sde_rm_hw_blk *dsc,
  1095. struct sde_rm_hw_blk *paired_dsc,
  1096. struct sde_rm_hw_blk *pp_blk)
  1097. {
  1098. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1099. /* Already reserved? */
  1100. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1101. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1102. return false;
  1103. }
  1104. /**
  1105. * This check is required for routing even numbered DSC
  1106. * blks to any of the even numbered PP blks and odd numbered
  1107. * DSC blks to any of the odd numbered PP blks.
  1108. */
  1109. if (!pp_blk || !IS_COMPATIBLE_PP_DSC(pp_blk->id, dsc->id))
  1110. return false;
  1111. /* Check if this dsc is a peer of the proposed paired DSC */
  1112. if (paired_dsc) {
  1113. const struct sde_dsc_cfg *paired_dsc_cfg =
  1114. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1115. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1116. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1117. paired_dsc_cfg->id);
  1118. return false;
  1119. }
  1120. }
  1121. return true;
  1122. }
  1123. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1124. struct sde_rm_rsvp *rsvp,
  1125. struct sde_rm_hw_blk *vdc)
  1126. {
  1127. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1128. /* Already reserved? */
  1129. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1130. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1131. return false;
  1132. }
  1133. return true;
  1134. }
  1135. static void sde_rm_get_rsvp_nxt_hw_blks(
  1136. struct sde_rm *rm,
  1137. struct sde_rm_rsvp *rsvp,
  1138. int type,
  1139. struct sde_rm_hw_blk **blk_arr)
  1140. {
  1141. struct sde_rm_hw_blk *blk;
  1142. int i = 0;
  1143. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1144. if (blk->rsvp_nxt && blk->rsvp_nxt->seq ==
  1145. rsvp->seq)
  1146. blk_arr[i++] = blk;
  1147. }
  1148. }
  1149. static int _sde_rm_reserve_dsc(
  1150. struct sde_rm *rm,
  1151. struct sde_rm_rsvp *rsvp,
  1152. struct sde_rm_requirements *reqs,
  1153. u8 *_dsc_ids)
  1154. {
  1155. struct sde_rm_hw_iter iter_i, iter_j;
  1156. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1157. u32 reserve_mask = 0;
  1158. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1159. int alloc_count = 0;
  1160. int num_dsc_enc;
  1161. struct msm_display_dsc_info *dsc_info;
  1162. int i;
  1163. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1164. SDE_DEBUG("compression blk dsc not required\n");
  1165. return 0;
  1166. }
  1167. num_dsc_enc = reqs->topology->num_comp_enc;
  1168. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1169. if ((!num_dsc_enc) || !dsc_info) {
  1170. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1171. num_dsc_enc, !(dsc_info == NULL));
  1172. return 0;
  1173. }
  1174. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1175. sde_rm_get_rsvp_nxt_hw_blks(rm, rsvp, SDE_HW_BLK_PINGPONG, pp);
  1176. /* Find a first DSC */
  1177. while (alloc_count != num_dsc_enc &&
  1178. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1179. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1180. iter_i.blk->hw);
  1181. unsigned long features = hw_dsc->caps->features;
  1182. bool has_422_420_support =
  1183. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1184. if (reserve_mask & (1 << iter_i.blk->id))
  1185. continue;
  1186. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1187. continue;
  1188. /* if this hw block does not support required feature */
  1189. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1190. dsc_info->config.native_420) && !has_422_420_support)
  1191. continue;
  1192. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL,
  1193. pp[alloc_count]))
  1194. continue;
  1195. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1196. iter_i.blk->id,
  1197. alloc_count,
  1198. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1199. reserve_mask |= (1 << iter_i.blk->id);
  1200. dsc[alloc_count++] = iter_i.blk;
  1201. /* Return if peer is not needed */
  1202. if (alloc_count == num_dsc_enc)
  1203. break;
  1204. /* Valid first dsc found, find matching peers */
  1205. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1206. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1207. if (reserve_mask & (1 << iter_j.blk->id))
  1208. continue;
  1209. if (_dsc_ids && (iter_j.blk->id !=
  1210. _dsc_ids[alloc_count]))
  1211. continue;
  1212. if (!_sde_rm_check_dsc(rm, rsvp, iter_j.blk,
  1213. iter_i.blk, pp[alloc_count]))
  1214. continue;
  1215. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1216. iter_j.blk->id,
  1217. alloc_count,
  1218. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1219. reserve_mask |= (1 << iter_j.blk->id);
  1220. dsc[alloc_count++] = iter_j.blk;
  1221. break;
  1222. }
  1223. /* Rollback primary DSC if peer is not found */
  1224. if (!iter_j.hw) {
  1225. reserve_mask &= ~(1 << iter_i.blk->id);
  1226. --alloc_count;
  1227. }
  1228. }
  1229. if (alloc_count != num_dsc_enc) {
  1230. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1231. num_dsc_enc, rsvp->enc_id);
  1232. return -EINVAL;
  1233. }
  1234. for (i = 0; i < alloc_count; i++) {
  1235. if (!dsc[i])
  1236. break;
  1237. dsc[i]->rsvp_nxt = rsvp;
  1238. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1239. }
  1240. return 0;
  1241. }
  1242. static int _sde_rm_reserve_vdc(
  1243. struct sde_rm *rm,
  1244. struct sde_rm_rsvp *rsvp,
  1245. struct sde_rm_requirements *reqs,
  1246. const struct sde_rm_topology_def *top,
  1247. u8 *_vdc_ids)
  1248. {
  1249. struct sde_rm_hw_iter iter_i;
  1250. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1251. int alloc_count = 0;
  1252. int num_vdc_enc = top->num_comp_enc;
  1253. int i;
  1254. if (!top->num_comp_enc)
  1255. return 0;
  1256. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1257. return 0;
  1258. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1259. /* Find a VDC */
  1260. while (alloc_count != num_vdc_enc &&
  1261. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1262. memset(&vdc, 0, sizeof(vdc));
  1263. alloc_count = 0;
  1264. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1265. continue;
  1266. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1267. continue;
  1268. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1269. iter_i.blk->id,
  1270. alloc_count,
  1271. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1272. vdc[alloc_count++] = iter_i.blk;
  1273. }
  1274. if (alloc_count != num_vdc_enc) {
  1275. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1276. num_vdc_enc, rsvp->enc_id);
  1277. return -EINVAL;
  1278. }
  1279. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1280. if (!vdc[i])
  1281. break;
  1282. vdc[i]->rsvp_nxt = rsvp;
  1283. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1284. }
  1285. return 0;
  1286. }
  1287. static int _sde_rm_reserve_qdss(
  1288. struct sde_rm *rm,
  1289. struct sde_rm_rsvp *rsvp,
  1290. const struct sde_rm_topology_def *top,
  1291. u8 *_qdss_ids)
  1292. {
  1293. struct sde_rm_hw_iter iter;
  1294. struct msm_drm_private *priv = rm->dev->dev_private;
  1295. struct sde_kms *sde_kms;
  1296. if (!priv->kms) {
  1297. SDE_ERROR("invalid kms\n");
  1298. return -EINVAL;
  1299. }
  1300. sde_kms = to_sde_kms(priv->kms);
  1301. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1302. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1303. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1304. continue;
  1305. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1306. iter.blk->rsvp_nxt = rsvp;
  1307. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1308. return 0;
  1309. }
  1310. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1311. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1312. SDE_HW_BLK_QDSS, iter.blk->id);
  1313. return -ENAVAIL;
  1314. }
  1315. return 0;
  1316. }
  1317. static int _sde_rm_reserve_cdm(
  1318. struct sde_rm *rm,
  1319. struct sde_rm_rsvp *rsvp,
  1320. uint32_t id,
  1321. enum sde_hw_blk_type type)
  1322. {
  1323. struct sde_rm_hw_iter iter;
  1324. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1325. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1326. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1327. const struct sde_cdm_cfg *caps = cdm->caps;
  1328. bool match = false;
  1329. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1330. continue;
  1331. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1332. match = test_bit(id, &caps->intf_connect);
  1333. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1334. match = test_bit(id, &caps->wb_connect);
  1335. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1336. type, id, caps->intf_connect, caps->wb_connect,
  1337. match);
  1338. if (!match)
  1339. continue;
  1340. iter.blk->rsvp_nxt = rsvp;
  1341. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1342. break;
  1343. }
  1344. if (!iter.hw) {
  1345. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1346. return -ENAVAIL;
  1347. }
  1348. return 0;
  1349. }
  1350. static int _sde_rm_reserve_intf_or_wb(
  1351. struct sde_rm *rm,
  1352. struct sde_rm_rsvp *rsvp,
  1353. uint32_t id,
  1354. enum sde_hw_blk_type type,
  1355. bool needs_cdm)
  1356. {
  1357. struct sde_rm_hw_iter iter;
  1358. int ret = 0;
  1359. /* Find the block entry in the rm, and note the reservation */
  1360. sde_rm_init_hw_iter(&iter, 0, type);
  1361. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1362. if (iter.blk->id != id)
  1363. continue;
  1364. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1365. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1366. return -ENAVAIL;
  1367. }
  1368. iter.blk->rsvp_nxt = rsvp;
  1369. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1370. break;
  1371. }
  1372. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1373. if (!iter.hw) {
  1374. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1375. return -EINVAL;
  1376. }
  1377. /* Expected only one intf or wb will request cdm */
  1378. if (needs_cdm)
  1379. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1380. return ret;
  1381. }
  1382. static int _sde_rm_reserve_intf_related_hw(
  1383. struct sde_rm *rm,
  1384. struct sde_rm_rsvp *rsvp,
  1385. struct sde_encoder_hw_resources *hw_res)
  1386. {
  1387. int i, ret = 0;
  1388. u32 id;
  1389. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1390. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1391. continue;
  1392. id = i + INTF_0;
  1393. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1394. SDE_HW_BLK_INTF, hw_res->needs_cdm);
  1395. if (ret)
  1396. return ret;
  1397. }
  1398. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1399. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1400. continue;
  1401. id = i + WB_0;
  1402. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1403. SDE_HW_BLK_WB, hw_res->needs_cdm);
  1404. if (ret)
  1405. return ret;
  1406. }
  1407. return ret;
  1408. }
  1409. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1410. struct drm_encoder *enc)
  1411. {
  1412. int i;
  1413. struct sde_splash_display *splash_dpy;
  1414. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1415. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1416. if (splash_dpy->encoder == enc)
  1417. return splash_dpy->cont_splash_enabled;
  1418. }
  1419. return false;
  1420. }
  1421. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1422. struct sde_rm_requirements *reqs,
  1423. struct sde_splash_display *splash_display)
  1424. {
  1425. int ret, i;
  1426. u8 *hw_ids = NULL;
  1427. /* Check if splash data provided lm_ids */
  1428. if (splash_display) {
  1429. hw_ids = splash_display->lm_ids;
  1430. for (i = 0; i < splash_display->lm_cnt; i++)
  1431. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1432. i, splash_display->lm_ids[i]);
  1433. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1434. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1435. }
  1436. /*
  1437. * Assign LMs and blocks whose usage is tied to them:
  1438. * DSPP & Pingpong.
  1439. */
  1440. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1441. return ret;
  1442. }
  1443. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1444. struct sde_rm_requirements *reqs,
  1445. struct sde_splash_display *splash_display)
  1446. {
  1447. int ret, i;
  1448. u8 *hw_ids = NULL;
  1449. struct sde_rm_topology_def topology;
  1450. /* Check if splash data provided ctl_ids */
  1451. if (splash_display) {
  1452. hw_ids = splash_display->ctl_ids;
  1453. for (i = 0; i < splash_display->ctl_cnt; i++)
  1454. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1455. i, splash_display->ctl_ids[i]);
  1456. }
  1457. /*
  1458. * Do assignment preferring to give away low-resource CTLs first:
  1459. * - Check mixers without Split Display
  1460. * - Only then allow to grab from CTLs with split display capability
  1461. */
  1462. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1463. if (ret && !reqs->topology->needs_split_display &&
  1464. reqs->topology->num_ctl > SINGLE_CTL) {
  1465. memcpy(&topology, reqs->topology, sizeof(topology));
  1466. topology.needs_split_display = true;
  1467. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1468. }
  1469. return ret;
  1470. }
  1471. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1472. struct sde_rm_requirements *reqs,
  1473. struct sde_splash_display *splash_display)
  1474. {
  1475. int i;
  1476. u8 *hw_ids = NULL;
  1477. /* Check if splash data provided dsc_ids */
  1478. if (splash_display) {
  1479. hw_ids = splash_display->dsc_ids;
  1480. if (splash_display->dsc_cnt)
  1481. reqs->hw_res.comp_info->comp_type =
  1482. MSM_DISPLAY_COMPRESSION_DSC;
  1483. for (i = 0; i < splash_display->dsc_cnt; i++)
  1484. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1485. i, splash_display->dsc_ids[i]);
  1486. }
  1487. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1488. }
  1489. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1490. struct sde_rm_requirements *reqs,
  1491. struct sde_splash_display *splash_display)
  1492. {
  1493. int ret, i;
  1494. u8 *hw_ids = NULL;
  1495. /* Check if splash data provided vdc_ids */
  1496. if (splash_display) {
  1497. hw_ids = splash_display->vdc_ids;
  1498. for (i = 0; i < splash_display->vdc_cnt; i++)
  1499. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1500. i, splash_display->vdc_ids[i]);
  1501. }
  1502. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1503. return ret;
  1504. }
  1505. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1506. struct drm_crtc_state *crtc_state,
  1507. struct drm_connector_state *conn_state,
  1508. struct sde_rm_rsvp *rsvp,
  1509. struct sde_rm_requirements *reqs)
  1510. {
  1511. struct msm_drm_private *priv;
  1512. struct sde_kms *sde_kms;
  1513. struct sde_splash_display *splash_display = NULL;
  1514. struct sde_splash_data *splash_data;
  1515. int i, ret;
  1516. priv = enc->dev->dev_private;
  1517. sde_kms = to_sde_kms(priv->kms);
  1518. splash_data = &sde_kms->splash_data;
  1519. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1520. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1521. if (enc == splash_data->splash_display[i].encoder)
  1522. splash_display =
  1523. &splash_data->splash_display[i];
  1524. }
  1525. if (!splash_display) {
  1526. SDE_ERROR("rm is in cont_splash but data not found\n");
  1527. return -EINVAL;
  1528. }
  1529. }
  1530. /* Create reservation info, tag reserved blocks with it as we go */
  1531. rsvp->seq = ++rm->rsvp_next_seq;
  1532. rsvp->enc_id = enc->base.id;
  1533. rsvp->topology = reqs->topology->top_name;
  1534. list_add_tail(&rsvp->list, &rm->rsvps);
  1535. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1536. if (ret) {
  1537. SDE_ERROR("unable to find appropriate mixers\n");
  1538. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1539. return ret;
  1540. }
  1541. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1542. if (ret) {
  1543. SDE_ERROR("unable to find appropriate CTL\n");
  1544. return ret;
  1545. }
  1546. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1547. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
  1548. if (ret)
  1549. return ret;
  1550. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1551. if (ret)
  1552. return ret;
  1553. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1554. if (ret)
  1555. return ret;
  1556. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1557. if (ret)
  1558. return ret;
  1559. return ret;
  1560. }
  1561. static int _sde_rm_update_pipe_cnt_from_active(
  1562. struct sde_splash_display *splash_display,
  1563. u32 active_pipes_mask)
  1564. {
  1565. int i;
  1566. u32 sspp_present = 0, space_remain = 0;
  1567. if (!active_pipes_mask) {
  1568. return 0;
  1569. } else if (!splash_display) {
  1570. SDE_ERROR("invalid splash display provided\n");
  1571. return -EINVAL;
  1572. } else if (splash_display->pipe_cnt >=
  1573. ARRAY_SIZE(splash_display->pipes)) {
  1574. SDE_ERROR("no room to add active pipes to pipe array\n");
  1575. return -EINVAL;
  1576. }
  1577. for (i = 0; i < splash_display->pipe_cnt; i++)
  1578. sspp_present |= BIT(splash_display->pipes[i].sspp);
  1579. space_remain = ARRAY_SIZE(splash_display->pipes)
  1580. - splash_display->pipe_cnt;
  1581. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  1582. /* Skip planes already present in the array */
  1583. if (!(active_pipes_mask & BIT(i)) ||
  1584. (sspp_present & BIT(i)))
  1585. continue;
  1586. if (space_remain < R_MAX) {
  1587. SDE_ERROR("not enough room to add active pipe %d", i);
  1588. return -EINVAL;
  1589. }
  1590. /*
  1591. * A plane in active but not sspp_present indicates a non-pixel
  1592. * plane. Register both rectangles as we can't differentiate
  1593. */
  1594. splash_display->pipes[splash_display->pipe_cnt].sspp = i;
  1595. splash_display->pipes[splash_display->pipe_cnt].is_virtual =
  1596. false;
  1597. splash_display->pipe_cnt++;
  1598. space_remain--;
  1599. splash_display->pipes[splash_display->pipe_cnt].sspp = i;
  1600. splash_display->pipes[splash_display->pipe_cnt].is_virtual =
  1601. true;
  1602. splash_display->pipe_cnt++;
  1603. space_remain--;
  1604. }
  1605. return 0;
  1606. }
  1607. /**
  1608. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1609. * and populate the connected HW blk ids in sde_splash_display
  1610. * @rm: Pointer to resource manager structure
  1611. * @ctl: Pointer to CTL hardware block
  1612. * @splash_display: Pointer to struct sde_splash_display
  1613. * return: number of active LM blocks for this CTL block
  1614. */
  1615. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1616. struct sde_hw_ctl *ctl,
  1617. struct sde_splash_display *splash_display)
  1618. {
  1619. u32 lm_reg, max_cnt, active_pipes_mask = 0;
  1620. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1621. struct sde_kms *sde_kms;
  1622. size_t start_count;
  1623. if (!rm || !ctl || !splash_display) {
  1624. SDE_ERROR("invalid input parameters\n");
  1625. return 0;
  1626. }
  1627. sde_kms = container_of(rm, struct sde_kms, rm);
  1628. max_cnt = ARRAY_SIZE(splash_display->pipes);
  1629. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1630. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1631. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1632. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1633. break;
  1634. lm_reg = ctl->ops.read_ctl_layers(ctl, iter_lm.blk->id);
  1635. if (!lm_reg)
  1636. continue;
  1637. splash_display->lm_ids[splash_display->lm_cnt++] =
  1638. iter_lm.blk->id;
  1639. SDE_DEBUG("lm_cnt=%d lm_reg[%d]=0x%x\n", splash_display->lm_cnt,
  1640. iter_lm.blk->id - LM_0, lm_reg);
  1641. start_count = splash_display->pipe_cnt;
  1642. if (ctl->ops.get_staged_sspp) {
  1643. struct sde_sspp_index_info *start =
  1644. &splash_display->pipes[
  1645. splash_display->pipe_cnt];
  1646. splash_display->pipe_cnt += ctl->ops.get_staged_sspp(
  1647. ctl, iter_lm.blk->id, start,
  1648. max_cnt - splash_display->pipe_cnt);
  1649. }
  1650. if (sde_kms->splash_data.type == SDE_VM_HANDOFF) {
  1651. /* Allow VM handoff without any pipes, as it is a
  1652. * valid case to have NULL commit before the
  1653. * transition.
  1654. */
  1655. SDE_DEBUG("VM handoff with no pipes staged\n");
  1656. } else if (start_count == splash_display->pipe_cnt) {
  1657. SDE_ERROR("no pipes detected on LM-%d\n",
  1658. iter_lm.blk->id - LM_0);
  1659. return 0;
  1660. } else if (splash_display->pipe_cnt > max_cnt) {
  1661. SDE_ERROR("found %d pipes exceed max of %d\n",
  1662. splash_display->pipe_cnt, max_cnt);
  1663. return 0;
  1664. }
  1665. }
  1666. if (ctl->ops.get_active_pipes)
  1667. active_pipes_mask = ctl->ops.get_active_pipes(ctl);
  1668. if (_sde_rm_update_pipe_cnt_from_active(splash_display,
  1669. active_pipes_mask))
  1670. return 0;
  1671. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1672. if (ctl->ops.read_active_status &&
  1673. !(ctl->ops.read_active_status(ctl,
  1674. SDE_HW_BLK_DSC,
  1675. iter_dsc.blk->id)))
  1676. continue;
  1677. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1678. iter_dsc.blk->id;
  1679. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1680. ctl->idx,
  1681. iter_dsc.blk->id - DSC_0);
  1682. }
  1683. return splash_display->lm_cnt;
  1684. }
  1685. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1686. struct sde_rm *rm,
  1687. struct sde_splash_data *splash_data,
  1688. struct sde_mdss_cfg *cat)
  1689. {
  1690. struct sde_rm_hw_iter iter_c;
  1691. int index = 0, ctl_top_cnt;
  1692. struct sde_kms *sde_kms = NULL;
  1693. struct sde_hw_mdp *hw_mdp;
  1694. struct sde_splash_display *splash_display;
  1695. u8 intf_sel;
  1696. if (!priv || !rm || !cat || !splash_data) {
  1697. SDE_ERROR("invalid input parameters\n");
  1698. return -EINVAL;
  1699. }
  1700. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1701. cat->mixer_count,
  1702. cat->ctl_count,
  1703. cat->dsc_count);
  1704. ctl_top_cnt = cat->ctl_count;
  1705. if (!priv->kms) {
  1706. SDE_ERROR("invalid kms\n");
  1707. return -EINVAL;
  1708. }
  1709. sde_kms = to_sde_kms(priv->kms);
  1710. hw_mdp = sde_rm_get_mdp(rm);
  1711. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1712. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1713. && (index < splash_data->num_splash_displays)) {
  1714. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1715. if (!ctl->ops.get_ctl_intf) {
  1716. SDE_ERROR("get_ctl_intf not initialized\n");
  1717. return -EINVAL;
  1718. }
  1719. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1720. if (intf_sel) {
  1721. splash_display = &splash_data->splash_display[index];
  1722. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1723. index, iter_c.blk->id - CTL_0);
  1724. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1725. ctl, splash_display);
  1726. splash_display->cont_splash_enabled = true;
  1727. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1728. iter_c.blk->id;
  1729. }
  1730. index++;
  1731. }
  1732. return 0;
  1733. }
  1734. static int _sde_rm_populate_requirements(
  1735. struct sde_rm *rm,
  1736. struct drm_encoder *enc,
  1737. struct drm_crtc_state *crtc_state,
  1738. struct drm_connector_state *conn_state,
  1739. struct sde_mdss_cfg *cfg,
  1740. struct sde_rm_requirements *reqs)
  1741. {
  1742. const struct drm_display_mode *mode = &crtc_state->mode;
  1743. int i, num_lm;
  1744. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1745. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1746. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1747. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1748. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1749. reqs->hw_res.topology)) {
  1750. reqs->topology = &rm->topology_tbl[i];
  1751. break;
  1752. }
  1753. }
  1754. if (!reqs->topology) {
  1755. SDE_ERROR("invalid topology for the display\n");
  1756. return -EINVAL;
  1757. }
  1758. /*
  1759. * select dspp HW block for all dsi displays and ds for only
  1760. * primary dsi display.
  1761. */
  1762. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1763. if (!RM_RQ_DSPP(reqs))
  1764. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1765. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1766. sde_encoder_is_primary_display(enc))
  1767. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1768. }
  1769. /**
  1770. * Set the requirement for LM which has CWB support if CWB is
  1771. * found enabled.
  1772. */
  1773. if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
  1774. && sde_encoder_in_clone_mode(enc)) {
  1775. if (cfg->has_dedicated_cwb_support)
  1776. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
  1777. else
  1778. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1779. /*
  1780. * topology selection based on conn mode is not valid for CWB
  1781. * as WB conn populates modes based on max_mixer_width check
  1782. * but primary can be using dual LMs. This topology override for
  1783. * CWB is to check number of datapath active in primary and
  1784. * allocate same number of LM/PP blocks reserved for CWB
  1785. */
  1786. reqs->topology =
  1787. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  1788. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  1789. conn_state->connector);
  1790. if (num_lm == 1)
  1791. reqs->topology =
  1792. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  1793. else if (num_lm == 0)
  1794. SDE_ERROR("Primary layer mixer is not set\n");
  1795. SDE_EVT32(num_lm, reqs->topology->num_lm,
  1796. reqs->topology->top_name, reqs->topology->num_ctl);
  1797. }
  1798. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  1799. reqs->hw_res.display_num_of_h_tiles);
  1800. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
  1801. reqs->topology->num_lm, reqs->topology->num_ctl,
  1802. reqs->topology->top_name,
  1803. reqs->topology->needs_split_display);
  1804. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  1805. reqs->top_ctrl, reqs->topology->top_name,
  1806. reqs->topology->num_ctl);
  1807. return 0;
  1808. }
  1809. static struct sde_rm_rsvp *_sde_rm_get_rsvp(
  1810. struct sde_rm *rm,
  1811. struct drm_encoder *enc)
  1812. {
  1813. struct sde_rm_rsvp *i;
  1814. if (!rm || !enc) {
  1815. SDE_ERROR("invalid params\n");
  1816. return NULL;
  1817. }
  1818. if (list_empty(&rm->rsvps))
  1819. return NULL;
  1820. list_for_each_entry(i, &rm->rsvps, list)
  1821. if (i->enc_id == enc->base.id)
  1822. return i;
  1823. return NULL;
  1824. }
  1825. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(
  1826. struct sde_rm *rm,
  1827. struct drm_encoder *enc)
  1828. {
  1829. struct sde_rm_rsvp *i;
  1830. if (list_empty(&rm->rsvps))
  1831. return NULL;
  1832. list_for_each_entry(i, &rm->rsvps, list)
  1833. if (i->enc_id == enc->base.id)
  1834. break;
  1835. list_for_each_entry_continue(i, &rm->rsvps, list)
  1836. if (i->enc_id == enc->base.id)
  1837. return i;
  1838. return NULL;
  1839. }
  1840. static struct drm_connector *_sde_rm_get_connector(
  1841. struct drm_encoder *enc)
  1842. {
  1843. struct drm_connector *conn = NULL, *conn_search;
  1844. struct sde_connector *c_conn = NULL;
  1845. struct drm_connector_list_iter conn_iter;
  1846. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1847. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1848. c_conn = to_sde_connector(conn_search);
  1849. if (c_conn->encoder == enc) {
  1850. conn = conn_search;
  1851. break;
  1852. }
  1853. }
  1854. drm_connector_list_iter_end(&conn_iter);
  1855. return conn;
  1856. }
  1857. int sde_rm_update_topology(struct sde_rm *rm,
  1858. struct drm_connector_state *conn_state,
  1859. struct msm_display_topology *topology)
  1860. {
  1861. int i, ret = 0;
  1862. struct msm_display_topology top;
  1863. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  1864. if (!conn_state)
  1865. return -EINVAL;
  1866. if (topology) {
  1867. top = *topology;
  1868. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  1869. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  1870. top_name = rm->topology_tbl[i].top_name;
  1871. break;
  1872. }
  1873. }
  1874. ret = msm_property_set_property(
  1875. sde_connector_get_propinfo(conn_state->connector),
  1876. sde_connector_get_property_state(conn_state),
  1877. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  1878. return ret;
  1879. }
  1880. bool sde_rm_topology_is_group(struct sde_rm *rm,
  1881. struct drm_crtc_state *state,
  1882. enum sde_rm_topology_group group)
  1883. {
  1884. int i, ret = 0;
  1885. struct sde_crtc_state *cstate;
  1886. struct drm_connector *conn;
  1887. struct drm_connector_state *conn_state;
  1888. struct msm_display_topology topology;
  1889. enum sde_rm_topology_name name;
  1890. if ((!rm) || (!state) || (!state->state)) {
  1891. pr_err("invalid arguments: rm:%d state:%d atomic state:%d\n",
  1892. !rm, !state, state ? (!state->state) : 0);
  1893. return false;
  1894. }
  1895. cstate = to_sde_crtc_state(state);
  1896. for (i = 0; i < cstate->num_connectors; i++) {
  1897. conn = cstate->connectors[i];
  1898. if (!conn) {
  1899. SDE_DEBUG("invalid connector\n");
  1900. continue;
  1901. }
  1902. conn_state = drm_atomic_get_new_connector_state(state->state,
  1903. conn);
  1904. if (!conn_state) {
  1905. SDE_DEBUG("%s invalid connector state\n", conn->name);
  1906. continue;
  1907. }
  1908. ret = sde_connector_state_get_topology(conn_state, &topology);
  1909. if (ret) {
  1910. SDE_DEBUG("%s invalid topology\n", conn->name);
  1911. continue;
  1912. }
  1913. name = sde_rm_get_topology_name(rm, topology);
  1914. switch (group) {
  1915. case SDE_RM_TOPOLOGY_GROUP_SINGLEPIPE:
  1916. if (TOPOLOGY_SINGLEPIPE_MODE(name))
  1917. return true;
  1918. break;
  1919. case SDE_RM_TOPOLOGY_GROUP_DUALPIPE:
  1920. if (TOPOLOGY_DUALPIPE_MODE(name))
  1921. return true;
  1922. break;
  1923. case SDE_RM_TOPOLOGY_GROUP_QUADPIPE:
  1924. if (TOPOLOGY_QUADPIPE_MODE(name))
  1925. return true;
  1926. break;
  1927. case SDE_RM_TOPOLOGY_GROUP_3DMERGE:
  1928. if (topology.num_lm > topology.num_intf &&
  1929. !topology.num_enc)
  1930. return true;
  1931. break;
  1932. case SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC:
  1933. if (topology.num_lm > topology.num_enc &&
  1934. topology.num_enc)
  1935. return true;
  1936. break;
  1937. case SDE_RM_TOPOLOGY_GROUP_DSCMERGE:
  1938. if (topology.num_lm == topology.num_enc &&
  1939. topology.num_enc)
  1940. return true;
  1941. break;
  1942. default:
  1943. SDE_ERROR("invalid topology group\n");
  1944. return false;
  1945. }
  1946. }
  1947. return false;
  1948. }
  1949. /**
  1950. * _sde_rm_release_rsvp - release resources and release a reservation
  1951. * @rm: KMS handle
  1952. * @rsvp: RSVP pointer to release and release resources for
  1953. */
  1954. static void _sde_rm_release_rsvp(
  1955. struct sde_rm *rm,
  1956. struct sde_rm_rsvp *rsvp,
  1957. struct drm_connector *conn)
  1958. {
  1959. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  1960. struct sde_rm_hw_blk *blk;
  1961. enum sde_hw_blk_type type;
  1962. if (!rsvp)
  1963. return;
  1964. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  1965. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  1966. if (rsvp == rsvp_c) {
  1967. list_del(&rsvp_c->list);
  1968. break;
  1969. }
  1970. }
  1971. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1972. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1973. if (blk->rsvp == rsvp) {
  1974. blk->rsvp = NULL;
  1975. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  1976. rsvp->seq, rsvp->enc_id,
  1977. blk->type, blk->id);
  1978. _sde_rm_inc_resource_info(rm,
  1979. &rm->avail_res, blk);
  1980. }
  1981. if (blk->rsvp_nxt == rsvp) {
  1982. blk->rsvp_nxt = NULL;
  1983. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  1984. rsvp->seq, rsvp->enc_id,
  1985. blk->type, blk->id);
  1986. }
  1987. }
  1988. }
  1989. kfree(rsvp);
  1990. }
  1991. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  1992. {
  1993. struct sde_rm_rsvp *rsvp;
  1994. struct drm_connector *conn = NULL;
  1995. struct msm_drm_private *priv;
  1996. struct sde_kms *sde_kms;
  1997. uint64_t top_ctrl = 0;
  1998. if (!rm || !enc) {
  1999. SDE_ERROR("invalid params\n");
  2000. return;
  2001. }
  2002. priv = enc->dev->dev_private;
  2003. if (!priv->kms) {
  2004. SDE_ERROR("invalid kms\n");
  2005. return;
  2006. }
  2007. sde_kms = to_sde_kms(priv->kms);
  2008. mutex_lock(&rm->rm_lock);
  2009. if (nxt)
  2010. rsvp = _sde_rm_get_rsvp_nxt(rm, enc);
  2011. else
  2012. rsvp = _sde_rm_get_rsvp(rm, enc);
  2013. if (!rsvp) {
  2014. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  2015. enc->base.id, nxt);
  2016. goto end;
  2017. }
  2018. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  2019. _sde_rm_release_rsvp(rm, rsvp, conn);
  2020. goto end;
  2021. }
  2022. conn = _sde_rm_get_connector(enc);
  2023. if (!conn) {
  2024. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  2025. _sde_rm_release_rsvp(rm, rsvp, conn);
  2026. SDE_DEBUG("failed to get conn for enc %d nxt %d\n",
  2027. enc->base.id, nxt);
  2028. goto end;
  2029. }
  2030. top_ctrl = sde_connector_get_property(conn->state,
  2031. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  2032. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  2033. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  2034. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  2035. rsvp->seq, rsvp->enc_id);
  2036. } else {
  2037. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  2038. rsvp->enc_id);
  2039. _sde_rm_release_rsvp(rm, rsvp, conn);
  2040. }
  2041. end:
  2042. mutex_unlock(&rm->rm_lock);
  2043. }
  2044. static int _sde_rm_commit_rsvp(
  2045. struct sde_rm *rm,
  2046. struct sde_rm_rsvp *rsvp,
  2047. struct drm_connector_state *conn_state)
  2048. {
  2049. struct sde_rm_hw_blk *blk;
  2050. enum sde_hw_blk_type type;
  2051. int ret = 0;
  2052. /* Swap next rsvp to be the active */
  2053. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2054. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2055. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  2056. == blk->rsvp_nxt->enc_id) {
  2057. blk->rsvp = blk->rsvp_nxt;
  2058. blk->rsvp_nxt = NULL;
  2059. _sde_rm_dec_resource_info(rm,
  2060. &rm->avail_res, blk);
  2061. }
  2062. }
  2063. }
  2064. if (!ret) {
  2065. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
  2066. rsvp->topology);
  2067. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  2068. }
  2069. return ret;
  2070. }
  2071. /* call this only after rm_mutex held */
  2072. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  2073. struct drm_encoder *enc)
  2074. {
  2075. int i;
  2076. u32 loop_count = 20;
  2077. struct sde_rm_rsvp *rsvp_nxt = NULL;
  2078. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  2079. for (i = 0; i < loop_count; i++) {
  2080. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2081. if (!rsvp_nxt)
  2082. return rsvp_nxt;
  2083. mutex_unlock(&rm->rm_lock);
  2084. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  2085. i, sleep, sleep * 2);
  2086. usleep_range(sleep, sleep * 2);
  2087. mutex_lock(&rm->rm_lock);
  2088. }
  2089. /* make sure to get latest rsvp_next to avoid use after free issues */
  2090. return _sde_rm_get_rsvp_nxt(rm, enc);
  2091. }
  2092. int sde_rm_reserve(
  2093. struct sde_rm *rm,
  2094. struct drm_encoder *enc,
  2095. struct drm_crtc_state *crtc_state,
  2096. struct drm_connector_state *conn_state,
  2097. bool test_only)
  2098. {
  2099. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  2100. struct sde_rm_requirements reqs = {0,};
  2101. struct msm_drm_private *priv;
  2102. struct sde_kms *sde_kms;
  2103. struct msm_compression_info *comp_info;
  2104. int ret;
  2105. if (!rm || !enc || !crtc_state || !conn_state) {
  2106. SDE_ERROR("invalid arguments\n");
  2107. return -EINVAL;
  2108. }
  2109. if (!enc->dev || !enc->dev->dev_private) {
  2110. SDE_ERROR("drm device invalid\n");
  2111. return -EINVAL;
  2112. }
  2113. priv = enc->dev->dev_private;
  2114. if (!priv->kms) {
  2115. SDE_ERROR("invalid kms\n");
  2116. return -EINVAL;
  2117. }
  2118. sde_kms = to_sde_kms(priv->kms);
  2119. /* Check if this is just a page-flip */
  2120. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2121. !msm_atomic_needs_modeset(crtc_state))
  2122. return 0;
  2123. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2124. if (!comp_info)
  2125. return -ENOMEM;
  2126. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2127. conn_state->connector->base.id, enc->base.id,
  2128. crtc_state->crtc->base.id, test_only);
  2129. SDE_EVT32(enc->base.id, conn_state->connector->base.id);
  2130. mutex_lock(&rm->rm_lock);
  2131. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2132. rsvp_cur = _sde_rm_get_rsvp(rm, enc);
  2133. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2134. /*
  2135. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2136. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2137. * check_only commit with modeset when its predecessor atomic
  2138. * commit is delayed / not committed the reservation yet.
  2139. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2140. * gets cleared and bailout if it does not get cleared before timeout.
  2141. */
  2142. if (test_only && rsvp_cur && rsvp_nxt) {
  2143. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2144. if (rsvp_nxt) {
  2145. SDE_ERROR("poll timeout cur %d nxt %d enc %d\n",
  2146. rsvp_cur->seq, rsvp_nxt->seq, enc->base.id);
  2147. ret = -EINVAL;
  2148. goto end;
  2149. }
  2150. }
  2151. if (!test_only && rsvp_nxt)
  2152. goto commit_rsvp;
  2153. reqs.hw_res.comp_info = comp_info;
  2154. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2155. conn_state, sde_kms->catalog, &reqs);
  2156. if (ret) {
  2157. SDE_ERROR("failed to populate hw requirements\n");
  2158. goto end;
  2159. }
  2160. /*
  2161. * We only support one active reservation per-hw-block. But to implement
  2162. * transactional semantics for test-only, and for allowing failure while
  2163. * modifying your existing reservation, over the course of this
  2164. * function we can have two reservations:
  2165. * Current: Existing reservation
  2166. * Next: Proposed reservation. The proposed reservation may fail, or may
  2167. * be discarded if in test-only mode.
  2168. * If reservation is successful, and we're not in test-only, then we
  2169. * replace the current with the next.
  2170. */
  2171. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2172. if (!rsvp_nxt) {
  2173. ret = -ENOMEM;
  2174. goto end;
  2175. }
  2176. /*
  2177. * User can request that we clear out any reservation during the
  2178. * atomic_check phase by using this CLEAR bit
  2179. */
  2180. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2181. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2182. rsvp_cur->seq, rsvp_cur->enc_id);
  2183. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2184. rsvp_cur = NULL;
  2185. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2186. }
  2187. /* Check the proposed reservation, store it in hw's "next" field */
  2188. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2189. rsvp_nxt, &reqs);
  2190. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2191. if (ret) {
  2192. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2193. ret, test_only);
  2194. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2195. goto end;
  2196. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2197. /*
  2198. * Normally, if test_only, test the reservation and then undo
  2199. * However, if the user requests LOCK, then keep the reservation
  2200. * made during the atomic_check phase.
  2201. */
  2202. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2203. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2204. goto end;
  2205. } else {
  2206. if (test_only && RM_RQ_LOCK(&reqs))
  2207. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2208. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2209. }
  2210. commit_rsvp:
  2211. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2212. ret = _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2213. end:
  2214. kfree(comp_info);
  2215. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2216. mutex_unlock(&rm->rm_lock);
  2217. return ret;
  2218. }
  2219. int sde_rm_ext_blk_create_reserve(struct sde_rm *rm,
  2220. struct sde_hw_blk *hw, struct drm_encoder *enc)
  2221. {
  2222. struct sde_rm_hw_blk *blk;
  2223. struct sde_rm_rsvp *rsvp;
  2224. int ret = 0;
  2225. if (!rm || !hw || !enc) {
  2226. SDE_ERROR("invalid parameters\n");
  2227. return -EINVAL;
  2228. }
  2229. if (hw->type >= SDE_HW_BLK_MAX) {
  2230. SDE_ERROR("invalid HW type\n");
  2231. return -EINVAL;
  2232. }
  2233. mutex_lock(&rm->rm_lock);
  2234. rsvp = _sde_rm_get_rsvp(rm, enc);
  2235. if (!rsvp) {
  2236. rsvp = kzalloc(sizeof(*rsvp), GFP_KERNEL);
  2237. if (!rsvp) {
  2238. ret = -ENOMEM;
  2239. goto end;
  2240. }
  2241. rsvp->seq = ++rm->rsvp_next_seq;
  2242. rsvp->enc_id = enc->base.id;
  2243. list_add_tail(&rsvp->list, &rm->rsvps);
  2244. SDE_DEBUG("create rsvp %d for enc %d\n",
  2245. rsvp->seq, rsvp->enc_id);
  2246. }
  2247. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  2248. if (!blk) {
  2249. ret = -ENOMEM;
  2250. goto end;
  2251. }
  2252. blk->type = hw->type;
  2253. blk->id = hw->id;
  2254. blk->hw = hw;
  2255. blk->rsvp = rsvp;
  2256. list_add_tail(&blk->list, &rm->hw_blks[hw->type]);
  2257. SDE_DEBUG("create blk %d %d for rsvp %d enc %d\n", blk->type, blk->id,
  2258. rsvp->seq, rsvp->enc_id);
  2259. end:
  2260. mutex_unlock(&rm->rm_lock);
  2261. return ret;
  2262. }
  2263. int sde_rm_ext_blk_destroy(struct sde_rm *rm,
  2264. struct drm_encoder *enc)
  2265. {
  2266. struct sde_rm_hw_blk *blk = NULL, *p;
  2267. struct sde_rm_rsvp *rsvp;
  2268. enum sde_hw_blk_type type;
  2269. int ret = 0;
  2270. if (!rm || !enc) {
  2271. SDE_ERROR("invalid parameters\n");
  2272. return -EINVAL;
  2273. }
  2274. mutex_lock(&rm->rm_lock);
  2275. rsvp = _sde_rm_get_rsvp(rm, enc);
  2276. if (!rsvp) {
  2277. ret = -ENOENT;
  2278. SDE_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
  2279. goto end;
  2280. }
  2281. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2282. list_for_each_entry_safe(blk, p, &rm->hw_blks[type], list) {
  2283. if (blk->rsvp == rsvp) {
  2284. list_del(&blk->list);
  2285. SDE_DEBUG("del blk %d %d from rsvp %d enc %d\n",
  2286. blk->type, blk->id,
  2287. rsvp->seq, rsvp->enc_id);
  2288. kfree(blk);
  2289. }
  2290. }
  2291. }
  2292. SDE_DEBUG("del rsvp %d\n", rsvp->seq);
  2293. list_del(&rsvp->list);
  2294. kfree(rsvp);
  2295. end:
  2296. mutex_unlock(&rm->rm_lock);
  2297. return ret;
  2298. }