hif_main.h 18 KB

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  1. /*
  2. * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. /*
  20. * NB: Inappropriate references to "HTC" are used in this (and other)
  21. * HIF implementations. HTC is typically the calling layer, but it
  22. * theoretically could be some alternative.
  23. */
  24. /*
  25. * This holds all state needed to process a pending send/recv interrupt.
  26. * The information is saved here as soon as the interrupt occurs (thus
  27. * allowing the underlying CE to re-use the ring descriptor). The
  28. * information here is eventually processed by a completion processing
  29. * thread.
  30. */
  31. #ifndef __HIF_MAIN_H__
  32. #define __HIF_MAIN_H__
  33. #include <qdf_atomic.h> /* qdf_atomic_read */
  34. #include "qdf_lock.h"
  35. #include "cepci.h"
  36. #include "hif.h"
  37. #include "multibus.h"
  38. #include "hif_unit_test_suspend_i.h"
  39. #ifdef HIF_CE_LOG_INFO
  40. #include "qdf_notifier.h"
  41. #endif
  42. #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50
  43. #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60
  44. #define HIF_MAX_BUDGET 0xFFFF
  45. #define HIF_STATS_INC(_handle, _field, _delta) \
  46. { \
  47. (_handle)->stats._field += _delta; \
  48. }
  49. /*
  50. * This macro implementation is exposed for efficiency only.
  51. * The implementation may change and callers should
  52. * consider the targid to be a completely opaque handle.
  53. */
  54. #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid)))
  55. #ifdef QCA_WIFI_3_0
  56. #define DISABLE_L1SS_STATES 1
  57. #endif
  58. #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES
  59. #ifdef QCA_WIFI_3_0_ADRASTEA
  60. #define ADRASTEA_BU 1
  61. #else
  62. #define ADRASTEA_BU 0
  63. #endif
  64. #ifdef QCA_WIFI_3_0
  65. #define HAS_FW_INDICATOR 0
  66. #else
  67. #define HAS_FW_INDICATOR 1
  68. #endif
  69. #define AR9888_DEVICE_ID (0x003c)
  70. #define AR6320_DEVICE_ID (0x003e)
  71. #define AR6320_FW_1_1 (0x11)
  72. #define AR6320_FW_1_3 (0x13)
  73. #define AR6320_FW_2_0 (0x20)
  74. #define AR6320_FW_3_0 (0x30)
  75. #define AR6320_FW_3_2 (0x32)
  76. #define QCA6290_EMULATION_DEVICE_ID (0xabcd)
  77. #define QCA6290_DEVICE_ID (0x1100)
  78. #define QCN9000_DEVICE_ID (0x1104)
  79. #define QCN9224_DEVICE_ID (0x1109)
  80. #define QCN6122_DEVICE_ID (0xFFFB)
  81. #define QCA6390_EMULATION_DEVICE_ID (0x0108)
  82. #define QCA6390_DEVICE_ID (0x1101)
  83. /* TODO: change IDs for HastingsPrime */
  84. #define QCA6490_EMULATION_DEVICE_ID (0x010a)
  85. #define QCA6490_DEVICE_ID (0x1103)
  86. #define MANGO_DEVICE_ID (0x110a)
  87. /* TODO: change IDs for Moselle */
  88. #define QCA6750_EMULATION_DEVICE_ID (0x010c)
  89. #define QCA6750_DEVICE_ID (0x1105)
  90. /* TODO: change IDs for Hamilton */
  91. #define KIWI_DEVICE_ID (0x1107)
  92. #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
  93. #define AR9887_DEVICE_ID (0x0050)
  94. #define AR900B_DEVICE_ID (0x0040)
  95. #define QCA9984_DEVICE_ID (0x0046)
  96. #define QCA9888_DEVICE_ID (0x0056)
  97. #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with
  98. actual number once available.
  99. currently defining this to 0xffff for
  100. emulation purpose */
  101. #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */
  102. #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */
  103. #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */
  104. #define QCA9574_DEVICE_ID (0xfffa)
  105. /* Genoa */
  106. #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/
  107. #define QCN7605_COMPOSITE (0x9901)
  108. #define QCN7605_STANDALONE (0x9900)
  109. #define QCN7605_STANDALONE_V2 (0x9902)
  110. #define QCN7605_COMPOSITE_V2 (0x9903)
  111. #define RUMIM2M_DEVICE_ID_NODE0 0xabc0
  112. #define RUMIM2M_DEVICE_ID_NODE1 0xabc1
  113. #define RUMIM2M_DEVICE_ID_NODE2 0xabc2
  114. #define RUMIM2M_DEVICE_ID_NODE3 0xabc3
  115. #define RUMIM2M_DEVICE_ID_NODE4 0xaa10
  116. #define RUMIM2M_DEVICE_ID_NODE5 0xaa11
  117. #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
  118. #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn)
  119. #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)
  120. #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn)
  121. #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn)
  122. #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn)
  123. #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn)
  124. #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn)
  125. #ifdef QCA_WIFI_QCN9224
  126. #define NUM_CE_AVAILABLE 16
  127. #else
  128. #define NUM_CE_AVAILABLE 12
  129. #endif
  130. /* Add 1 here to store default configuration in index 0 */
  131. #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1)
  132. #define CE_INTERRUPT_IDX(x) x
  133. struct ce_int_assignment {
  134. uint8_t msi_idx[NUM_CE_AVAILABLE];
  135. };
  136. struct hif_ce_stats {
  137. int hif_pipe_no_resrc_count;
  138. int ce_ring_delta_fail_count;
  139. };
  140. #ifdef HIF_DETECTION_LATENCY_ENABLE
  141. struct hif_latency_detect {
  142. qdf_timer_t detect_latency_timer;
  143. uint32_t detect_latency_timer_timeout;
  144. bool is_timer_started;
  145. bool enable_detection;
  146. /* threshold when stall happens */
  147. uint32_t detect_latency_threshold;
  148. int ce2_tasklet_sched_cpuid;
  149. qdf_time_t ce2_tasklet_sched_time;
  150. qdf_time_t ce2_tasklet_exec_time;
  151. qdf_time_t credit_request_time;
  152. qdf_time_t credit_report_time;
  153. };
  154. #endif
  155. /*
  156. * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked
  157. * for defined here
  158. */
  159. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  160. #define HIF_CE_MAX_LATEST_HIST 2
  161. struct latest_evt_history {
  162. uint64_t irq_entry_ts;
  163. uint64_t bh_entry_ts;
  164. uint64_t bh_resched_ts;
  165. uint64_t bh_exit_ts;
  166. uint64_t bh_work_ts;
  167. int cpu_id;
  168. uint32_t ring_hp;
  169. uint32_t ring_tp;
  170. };
  171. struct ce_desc_hist {
  172. qdf_atomic_t history_index[CE_COUNT_MAX];
  173. uint8_t ce_id_hist_map[CE_COUNT_MAX];
  174. bool enable[CE_COUNT_MAX];
  175. bool data_enable[CE_COUNT_MAX];
  176. qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX];
  177. uint32_t hist_index;
  178. uint32_t hist_id;
  179. void *hist_ev[CE_COUNT_MAX];
  180. struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST];
  181. };
  182. void hif_record_latest_evt(struct ce_desc_hist *ce_hist,
  183. uint8_t type,
  184. int ce_id, uint64_t time,
  185. uint32_t hp, uint32_t tp);
  186. #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/
  187. /**
  188. * struct hif_cfg() - store ini config parameters in hif layer
  189. * @ce_status_ring_timer_threshold: ce status ring timer threshold
  190. * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold
  191. */
  192. struct hif_cfg {
  193. uint16_t ce_status_ring_timer_threshold;
  194. uint8_t ce_status_ring_batch_count_threshold;
  195. };
  196. #ifdef DP_UMAC_HW_RESET_SUPPORT
  197. /**
  198. * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer
  199. * @intr_tq: Tasklet structure
  200. * @cb_handler: Callback handler
  201. * @cb_ctx: Argument to be passed to @cb_handler
  202. * @os_irq: Interrupt number for this IRQ
  203. * @irq_configured: Whether the IRQ has been configured
  204. */
  205. struct hif_umac_reset_ctx {
  206. struct tasklet_struct intr_tq;
  207. int (*cb_handler)(void *cb_ctx);
  208. void *cb_ctx;
  209. uint32_t os_irq;
  210. bool irq_configured;
  211. };
  212. #endif
  213. struct hif_softc {
  214. struct hif_opaque_softc osc;
  215. struct hif_config_info hif_config;
  216. struct hif_target_info target_info;
  217. void __iomem *mem;
  218. void __iomem *mem_ce;
  219. enum qdf_bus_type bus_type;
  220. struct hif_bus_ops bus_ops;
  221. void *ce_id_to_state[CE_COUNT_MAX];
  222. qdf_device_t qdf_dev;
  223. bool hif_init_done;
  224. bool request_irq_done;
  225. bool ext_grp_irq_configured;
  226. bool free_irq_done;
  227. uint8_t ce_latency_stats;
  228. /* Packet statistics */
  229. struct hif_ce_stats pkt_stats;
  230. enum hif_target_status target_status;
  231. uint64_t event_enable_mask;
  232. struct targetdef_s *targetdef;
  233. struct ce_reg_def *target_ce_def;
  234. struct hostdef_s *hostdef;
  235. struct host_shadow_regs_s *host_shadow_regs;
  236. bool recovery;
  237. bool notice_send;
  238. bool per_ce_irq;
  239. uint32_t ce_irq_summary;
  240. /* No of copy engines supported */
  241. unsigned int ce_count;
  242. struct ce_int_assignment *int_assignment;
  243. atomic_t active_tasklet_cnt;
  244. atomic_t active_grp_tasklet_cnt;
  245. atomic_t link_suspended;
  246. uint32_t *vaddr_rri_on_ddr;
  247. qdf_dma_addr_t paddr_rri_on_ddr;
  248. #ifdef CONFIG_BYPASS_QMI
  249. uint32_t *vaddr_qmi_bypass;
  250. qdf_dma_addr_t paddr_qmi_bypass;
  251. #endif
  252. int linkstate_vote;
  253. bool fastpath_mode_on;
  254. atomic_t tasklet_from_intr;
  255. int htc_htt_tx_endpoint;
  256. qdf_dma_addr_t mem_pa;
  257. bool athdiag_procfs_inited;
  258. #ifdef FEATURE_NAPI
  259. struct qca_napi_data napi_data;
  260. #endif /* FEATURE_NAPI */
  261. /* stores ce_service_max_yield_time in ns */
  262. unsigned long long ce_service_max_yield_time;
  263. uint8_t ce_service_max_rx_ind_flush;
  264. struct hif_driver_state_callbacks callbacks;
  265. uint32_t hif_con_param;
  266. #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT
  267. uint32_t nss_wifi_ol_mode;
  268. #endif
  269. void *hal_soc;
  270. struct hif_ut_suspend_context ut_suspend_ctx;
  271. uint32_t hif_attribute;
  272. int wake_irq;
  273. int disable_wake_irq;
  274. hif_pm_wake_irq_type wake_irq_type;
  275. void (*initial_wakeup_cb)(void *);
  276. void *initial_wakeup_priv;
  277. #ifdef REMOVE_PKT_LOG
  278. /* Handle to pktlog device */
  279. void *pktlog_dev;
  280. #endif
  281. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  282. /* Pointer to the srng event history */
  283. struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS];
  284. #endif
  285. /*
  286. * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked
  287. * for defined here
  288. */
  289. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  290. struct ce_desc_hist hif_ce_desc_hist;
  291. #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/
  292. #ifdef IPA_OFFLOAD
  293. qdf_shared_mem_t *ipa_ce_ring;
  294. #endif
  295. struct hif_cfg ini_cfg;
  296. #ifdef HIF_CE_LOG_INFO
  297. qdf_notif_block hif_recovery_notifier;
  298. #endif
  299. #ifdef HIF_CPU_PERF_AFFINE_MASK
  300. /* The CPU hotplug event registration handle */
  301. struct qdf_cpuhp_handler *cpuhp_event_handle;
  302. #endif
  303. uint32_t irq_unlazy_disable;
  304. /* Should the unlzay support for interrupt delivery be disabled */
  305. /* Flag to indicate whether bus is suspended */
  306. bool bus_suspended;
  307. bool pktlog_init;
  308. #ifdef FEATURE_RUNTIME_PM
  309. /* Variable to track the link state change in RTPM */
  310. qdf_atomic_t pm_link_state;
  311. #endif
  312. #ifdef HIF_DETECTION_LATENCY_ENABLE
  313. struct hif_latency_detect latency_detect;
  314. #endif
  315. #ifdef FEATURE_RUNTIME_PM
  316. qdf_runtime_lock_t prevent_linkdown_lock;
  317. #endif
  318. #ifdef SYSTEM_PM_CHECK
  319. qdf_atomic_t sys_pm_state;
  320. #endif
  321. #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE)
  322. qdf_atomic_t dp_ep_vote_access;
  323. qdf_atomic_t ep_vote_access;
  324. #endif
  325. /* CMEM address target reserved for host usage */
  326. uint64_t cmem_start;
  327. /* CMEM size target reserved */
  328. uint64_t cmem_size;
  329. #ifdef DP_UMAC_HW_RESET_SUPPORT
  330. struct hif_umac_reset_ctx umac_reset_ctx;
  331. #endif
  332. };
  333. static inline
  334. void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl)
  335. {
  336. struct hif_softc *sc = (struct hif_softc *)hif_hdl;
  337. if (!sc)
  338. return NULL;
  339. return sc->hal_soc;
  340. }
  341. /**
  342. * hif_get_cmem_info() - get CMEM address and size from HIF handle
  343. * @hif_hdl: HIF handle pointer
  344. * @cmem_start: pointer for CMEM address
  345. * @cmem_size: pointer for CMEM size
  346. *
  347. * Return: None.
  348. */
  349. static inline
  350. void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl,
  351. uint64_t *cmem_start,
  352. uint64_t *cmem_size)
  353. {
  354. struct hif_softc *sc = (struct hif_softc *)hif_hdl;
  355. *cmem_start = sc->cmem_start;
  356. *cmem_size = sc->cmem_size;
  357. }
  358. /**
  359. * hif_get_num_active_tasklets() - get the number of active
  360. * tasklets pending to be completed.
  361. * @scn: HIF context
  362. *
  363. * Returns: the number of tasklets which are active
  364. */
  365. static inline int hif_get_num_active_tasklets(struct hif_softc *scn)
  366. {
  367. return qdf_atomic_read(&scn->active_tasklet_cnt);
  368. }
  369. /**
  370. * Max waiting time during Runtime PM suspend to finish all
  371. * the tasks. This is in the multiple of 10ms.
  372. */
  373. #define HIF_TASK_DRAIN_WAIT_CNT 25
  374. /**
  375. * hif_try_complete_tasks() - Try to complete all the pending tasks
  376. * @scn: HIF context
  377. *
  378. * Try to complete all the pending datapath tasks, i.e. tasklets,
  379. * DP group tasklets and works which are queued, in a given time
  380. * slot.
  381. *
  382. * Returns: QDF_STATUS_SUCCESS if all the tasks were completed
  383. * QDF error code, if the time slot exhausted
  384. */
  385. QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn);
  386. #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT
  387. static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc)
  388. {
  389. return !!(sc->nss_wifi_ol_mode);
  390. }
  391. #else
  392. static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc)
  393. {
  394. return false;
  395. }
  396. #endif
  397. static inline uint8_t hif_is_attribute_set(struct hif_softc *sc,
  398. uint32_t hif_attrib)
  399. {
  400. return sc->hif_attribute == hif_attrib;
  401. }
  402. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  403. static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle)
  404. {
  405. struct hif_softc *scn = (struct hif_softc *)hif_handle;
  406. scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK;
  407. }
  408. #else
  409. static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle)
  410. {
  411. }
  412. #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */
  413. A_target_id_t hif_get_target_id(struct hif_softc *scn);
  414. void hif_dump_pipe_debug_count(struct hif_softc *scn);
  415. void hif_display_bus_stats(struct hif_opaque_softc *scn);
  416. void hif_clear_bus_stats(struct hif_opaque_softc *scn);
  417. bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count);
  418. void hif_shutdown_device(struct hif_opaque_softc *hif_ctx);
  419. int hif_bus_configure(struct hif_softc *scn);
  420. void hif_cancel_deferred_target_sleep(struct hif_softc *scn);
  421. int hif_config_ce(struct hif_softc *scn);
  422. int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx);
  423. int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num);
  424. void hif_unconfig_ce(struct hif_softc *scn);
  425. void hif_ce_prepare_config(struct hif_softc *scn);
  426. QDF_STATUS hif_ce_open(struct hif_softc *scn);
  427. void hif_ce_close(struct hif_softc *scn);
  428. int athdiag_procfs_init(void *scn);
  429. void athdiag_procfs_remove(void);
  430. /* routine to modify the initial buffer count to be allocated on an os
  431. * platform basis. Platform owner will need to modify this as needed
  432. */
  433. qdf_size_t init_buffer_count(qdf_size_t maxSize);
  434. irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
  435. int hif_get_device_type(uint32_t device_id,
  436. uint32_t revision_id,
  437. uint32_t *hif_type, uint32_t *target_type);
  438. /*These functions are exposed to HDD*/
  439. void hif_nointrs(struct hif_softc *scn);
  440. void hif_bus_close(struct hif_softc *ol_sc);
  441. QDF_STATUS hif_bus_open(struct hif_softc *ol_sc,
  442. enum qdf_bus_type bus_type);
  443. QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev,
  444. void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type);
  445. void hif_disable_bus(struct hif_softc *scn);
  446. void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag);
  447. int hif_bus_get_context_size(enum qdf_bus_type bus_type);
  448. void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value);
  449. uint32_t hif_get_conparam(struct hif_softc *scn);
  450. struct hif_driver_state_callbacks *hif_get_callbacks_handle(
  451. struct hif_softc *scn);
  452. bool hif_is_driver_unloading(struct hif_softc *scn);
  453. bool hif_is_load_or_unload_in_progress(struct hif_softc *scn);
  454. bool hif_is_recovery_in_progress(struct hif_softc *scn);
  455. bool hif_is_target_ready(struct hif_softc *scn);
  456. /**
  457. * hif_get_bandwidth_level() - API to get the current bandwidth level
  458. * @scn: HIF Context
  459. *
  460. * Return: PLD bandwidth level
  461. */
  462. int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle);
  463. void hif_wlan_disable(struct hif_softc *scn);
  464. int hif_target_sleep_state_adjust(struct hif_softc *scn,
  465. bool sleep_ok,
  466. bool wait_for_it);
  467. #ifdef DP_MEM_PRE_ALLOC
  468. void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn,
  469. qdf_size_t size,
  470. qdf_dma_addr_t *paddr,
  471. uint32_t ring_type,
  472. uint8_t *is_mem_prealloc);
  473. void hif_mem_free_consistent_unaligned(struct hif_softc *scn,
  474. qdf_size_t size,
  475. void *vaddr,
  476. qdf_dma_addr_t paddr,
  477. qdf_dma_context_t memctx,
  478. uint8_t is_mem_prealloc);
  479. #else
  480. static inline
  481. void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn,
  482. qdf_size_t size,
  483. qdf_dma_addr_t *paddr,
  484. uint32_t ring_type,
  485. uint8_t *is_mem_prealloc)
  486. {
  487. return qdf_mem_alloc_consistent(scn->qdf_dev,
  488. scn->qdf_dev->dev,
  489. size,
  490. paddr);
  491. }
  492. static inline
  493. void hif_mem_free_consistent_unaligned(struct hif_softc *scn,
  494. qdf_size_t size,
  495. void *vaddr,
  496. qdf_dma_addr_t paddr,
  497. qdf_dma_context_t memctx,
  498. uint8_t is_mem_prealloc)
  499. {
  500. return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev,
  501. size, vaddr, paddr, memctx);
  502. }
  503. #endif
  504. /**
  505. * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID
  506. * @ctx_id: Rx CE context ID
  507. * @hif_hdl: HIF Context
  508. *
  509. * Return: Rx instance ID
  510. */
  511. int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl);
  512. void hif_ramdump_handler(struct hif_opaque_softc *scn);
  513. #ifdef HIF_USB
  514. void hif_usb_get_hw_info(struct hif_softc *scn);
  515. void hif_usb_ramdump_handler(struct hif_opaque_softc *scn);
  516. #else
  517. static inline void hif_usb_get_hw_info(struct hif_softc *scn) {}
  518. static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {}
  519. #endif
  520. /**
  521. * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq
  522. * @irq: the irq number that fired
  523. * @context: the opaque pointer passed to request_irq()
  524. *
  525. * Return: an irq return type
  526. */
  527. irqreturn_t hif_wake_interrupt_handler(int irq, void *context);
  528. #ifdef HIF_SNOC
  529. bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc);
  530. #else
  531. static inline
  532. bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc)
  533. {
  534. return true;
  535. }
  536. #endif
  537. #ifdef ADRASTEA_RRI_ON_DDR
  538. void hif_uninit_rri_on_ddr(struct hif_softc *scn);
  539. #else
  540. static inline
  541. void hif_uninit_rri_on_ddr(struct hif_softc *scn) {}
  542. #endif
  543. void hif_cleanup_static_buf_to_target(struct hif_softc *scn);
  544. #ifdef FEATURE_RUNTIME_PM
  545. /**
  546. * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring
  547. * @scn: hif context
  548. * @is_get: prevent linkdown if true otherwise allow
  549. *
  550. * this api should only be called as part of bus prevent linkdown
  551. */
  552. void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get);
  553. #else
  554. static inline
  555. void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get)
  556. {
  557. }
  558. #endif
  559. #endif /* __HIF_MAIN_H__ */