sde_rotator_base.h 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef __SDE_ROTATOR_BASE_H__
  7. #define __SDE_ROTATOR_BASE_H__
  8. #include <linux/types.h>
  9. #include <linux/file.h>
  10. #include <linux/kref.h>
  11. #include <linux/kernel.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interconnect.h>
  16. #include "sde_rotator_hwio.h"
  17. #include "sde_rotator_io_util.h"
  18. #include "sde_rotator_smmu.h"
  19. #include "sde_rotator_formats.h"
  20. #include <linux/pm_qos.h>
  21. /* HW Revisions for different targets */
  22. #define SDE_GET_MAJOR_REV(rev) ((rev) >> 28)
  23. #define SDE_GET_MAJOR_MINOR(rev) ((rev) >> 16)
  24. #define IS_SDE_MAJOR_SAME(rev1, rev2) \
  25. (SDE_GET_MAJOR_REV((rev1)) == SDE_GET_MAJOR_REV((rev2)))
  26. #define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2) \
  27. (SDE_GET_MAJOR_MINOR(rev1) == SDE_GET_MAJOR_MINOR(rev2))
  28. #define SDE_MDP_REV(major, minor, step) \
  29. ((u32)(((major) & 0x000F) << 28) | \
  30. (((minor) & 0x0FFF) << 16) | \
  31. ((step) & 0xFFFF))
  32. #define SDE_MDP_HW_REV_107 SDE_MDP_REV(1, 0, 7) /* 8996 v1.0 */
  33. #define SDE_MDP_HW_REV_300 SDE_MDP_REV(3, 0, 0) /* 8998 v1.0 */
  34. #define SDE_MDP_HW_REV_301 SDE_MDP_REV(3, 0, 1) /* 8998 v1.1 */
  35. #define SDE_MDP_HW_REV_400 SDE_MDP_REV(4, 0, 0) /* sdm845 v1.0 */
  36. #define SDE_MDP_HW_REV_410 SDE_MDP_REV(4, 1, 0) /* sdm670 v1.0 */
  37. #define SDE_MDP_HW_REV_500 SDE_MDP_REV(5, 0, 0) /* sm8150 v1.0 */
  38. #define SDE_MDP_HW_REV_520 SDE_MDP_REV(5, 2, 0) /* sdmmagpie v1.0 */
  39. #define SDE_MDP_HW_REV_530 SDE_MDP_REV(5, 3, 0) /* sm6150 v1.0 */
  40. #define SDE_MDP_HW_REV_540 SDE_MDP_REV(5, 4, 0) /* sdmtrinket v1.0 */
  41. #define SDE_MDP_HW_REV_600 SDE_MDP_REV(6, 0, 0) /* msmnile+ v1.0 */
  42. #define SDE_MDP_HW_REV_630 SDE_MDP_REV(6, 3, 0) /* bengal v1.0 */
  43. #define SDE_MDP_HW_REV_660 SDE_MDP_REV(6, 6, 0) /* holi */
  44. #define SDE_MDP_HW_REV_690 SDE_MDP_REV(6, 9, 0) /* blair */
  45. #define SDE_MDP_HW_REV_870 SDE_MDP_REV(8, 7, 0) /* pitti */
  46. #define SDE_MDP_VBIF_4_LEVEL_REMAPPER 4
  47. #define SDE_MDP_VBIF_8_LEVEL_REMAPPER 8
  48. /* XIN mapping */
  49. #define XIN_SSPP 0
  50. #define XIN_WRITEBACK 1
  51. #define MAX_XIN 2
  52. struct sde_mult_factor {
  53. uint32_t numer;
  54. uint32_t denom;
  55. };
  56. struct sde_mdp_set_ot_params {
  57. u32 xin_id;
  58. u32 num;
  59. u32 width;
  60. u32 height;
  61. u32 fps;
  62. u32 fmt;
  63. u32 reg_off_vbif_lim_conf;
  64. u32 reg_off_mdp_clk_ctrl;
  65. u32 bit_off_mdp_clk_ctrl;
  66. char __iomem *rotsts_base;
  67. u32 rotsts_busy_mask;
  68. };
  69. /*
  70. * struct sde_mdp_vbif_halt_params: parameters for issue halt request to vbif
  71. * @xin_id: xin port number of vbif
  72. * @reg_off_mdp_clk_ctrl: reg offset for vbif clock control
  73. * @bit_off_mdp_clk_ctrl: bit offset for vbif clock control
  74. * @xin_timeout: bit position indicates timeout on corresponding xin id
  75. */
  76. struct sde_mdp_vbif_halt_params {
  77. u32 xin_id;
  78. u32 reg_off_mdp_clk_ctrl;
  79. u32 bit_off_mdp_clk_ctrl;
  80. u32 xin_timeout;
  81. };
  82. enum sde_bus_vote_type {
  83. VOTE_INDEX_DISABLE,
  84. VOTE_INDEX_76_MHZ,
  85. VOTE_INDEX_150_MHZ,
  86. VOTE_INDEX_300_MHZ,
  87. VOTE_INDEX_MAX,
  88. };
  89. #define MAX_CLIENT_NAME_LEN 64
  90. enum sde_qos_settings {
  91. SDE_QOS_PER_PIPE_IB,
  92. SDE_QOS_OVERHEAD_FACTOR,
  93. SDE_QOS_CDP,
  94. SDE_QOS_OTLIM,
  95. SDE_QOS_PER_PIPE_LUT,
  96. SDE_QOS_SIMPLIFIED_PREFILL,
  97. SDE_QOS_VBLANK_PANIC_CTRL,
  98. SDE_QOS_LUT,
  99. SDE_QOS_DANGER_LUT,
  100. SDE_QOS_SAFE_LUT,
  101. SDE_QOS_MAX,
  102. };
  103. enum sde_inline_qos_settings {
  104. SDE_INLINE_QOS_LUT,
  105. SDE_INLINE_QOS_DANGER_LUT,
  106. SDE_INLINE_QOS_SAFE_LUT,
  107. SDE_INLINE_QOS_MAX,
  108. };
  109. /**
  110. * enum sde_rot_type: SDE rotator HW version
  111. * @SDE_ROT_TYPE_V1_0: V1.0 HW version
  112. * @SDE_ROT_TYPE_V1_1: V1.1 HW version
  113. */
  114. enum sde_rot_type {
  115. SDE_ROT_TYPE_V1_0 = 0x10000000,
  116. SDE_ROT_TYPE_V1_1 = 0x10010000,
  117. SDE_ROT_TYPE_MAX,
  118. };
  119. /**
  120. * enum sde_caps_settings: SDE rotator capability definition
  121. * @SDE_CAPS_R1_WB: MDSS V1.x WB block
  122. * @SDE_CAPS_R3_WB: MDSS V3.x WB block
  123. * @SDE_CAPS_R3_1P5_DOWNSCALE: 1.5x downscale rotator support
  124. * @SDE_CAPS_SBUF_1: stream buffer support for inline rotation
  125. * @SDE_CAPS_UBWC_2: universal bandwidth compression version 2
  126. * @SDE_CAPS_PARTIALWR: partial write override
  127. * @SDE_CAPS_HW_TIMESTAMP: rotator has hw timestamp support
  128. * @SDE_CAPS_UBWC_3: universal bandwidth compression version 3
  129. * @SDE_CAPS_UBWC_4: universal bandwidth compression version 4
  130. */
  131. enum sde_caps_settings {
  132. SDE_CAPS_R1_WB,
  133. SDE_CAPS_R3_WB,
  134. SDE_CAPS_R3_1P5_DOWNSCALE,
  135. SDE_CAPS_SEC_ATTACH_DETACH_SMMU,
  136. SDE_CAPS_SBUF_1,
  137. SDE_CAPS_UBWC_2,
  138. SDE_CAPS_PARTIALWR,
  139. SDE_CAPS_HW_TIMESTAMP,
  140. SDE_CAPS_UBWC_3,
  141. SDE_CAPS_UBWC_4,
  142. SDE_CAPS_MAX,
  143. };
  144. enum sde_bus_clients {
  145. SDE_ROT_RT,
  146. SDE_ROT_NRT,
  147. SDE_MAX_BUS_CLIENTS
  148. };
  149. enum sde_rot_op {
  150. SDE_ROT_RD,
  151. SDE_ROT_WR,
  152. SDE_ROT_OP_MAX
  153. };
  154. enum sde_rot_regdump_access {
  155. SDE_ROT_REGDUMP_READ,
  156. SDE_ROT_REGDUMP_WRITE,
  157. SDE_ROT_REGDUMP_VBIF,
  158. SDE_ROT_REGDUMP_MAX
  159. };
  160. struct reg_bus_client {
  161. char name[MAX_CLIENT_NAME_LEN];
  162. short usecase_ndx;
  163. u32 id;
  164. struct list_head list;
  165. };
  166. struct sde_smmu_client {
  167. struct device *dev;
  168. struct iommu_domain *rot_domain;
  169. struct sde_module_power mp;
  170. struct reg_bus_client *reg_bus_clt;
  171. bool domain_attached;
  172. int domain;
  173. u32 sid;
  174. };
  175. /*
  176. * struct sde_rot_bus_data: struct for bus setting
  177. * @ab: average bandwidth in kilobytes per second
  178. * @ib: peak bandwidth in kilobytes per second
  179. */
  180. struct sde_rot_bus_data {
  181. uint64_t ab; /* Arbitrated bandwidth */
  182. uint64_t ib; /* Instantaneous bandwidth */
  183. };
  184. /*
  185. * struct sde_rot_debug_bus: rotator debugbus header structure
  186. * @wr_addr: write address for debugbus controller
  187. * @block_id: rotator debugbus block id
  188. * @test_id: rotator debugbus test id
  189. */
  190. struct sde_rot_debug_bus {
  191. u32 wr_addr;
  192. u32 block_id;
  193. u32 test_id;
  194. };
  195. struct sde_rot_vbif_debug_bus {
  196. u32 disable_bus_addr;
  197. u32 block_bus_addr;
  198. u32 bit_offset;
  199. u32 block_cnt;
  200. u32 test_pnt_cnt;
  201. };
  202. struct sde_rot_regdump {
  203. char *name;
  204. u32 offset;
  205. u32 len;
  206. enum sde_rot_regdump_access access;
  207. u32 value;
  208. };
  209. struct sde_rot_lut_cfg {
  210. u32 creq_lut_0;
  211. u32 creq_lut_1;
  212. u32 danger_lut;
  213. u32 safe_lut;
  214. };
  215. struct sde_rot_data_type {
  216. u32 mdss_version;
  217. struct platform_device *pdev;
  218. struct platform_device *parent_pdev;
  219. struct sde_io_data sde_io;
  220. struct sde_io_data vbif_nrt_io;
  221. char __iomem *mdp_base;
  222. struct sde_smmu_client sde_smmu[SDE_IOMMU_MAX_DOMAIN];
  223. /* bitmap to track qos applicable settings */
  224. DECLARE_BITMAP(sde_qos_map, SDE_QOS_MAX);
  225. DECLARE_BITMAP(sde_inline_qos_map, SDE_QOS_MAX);
  226. /* bitmap to track capability settings */
  227. DECLARE_BITMAP(sde_caps_map, SDE_CAPS_MAX);
  228. u32 default_ot_rd_limit;
  229. u32 default_ot_wr_limit;
  230. u32 highest_bank_bit;
  231. u32 rot_block_size;
  232. /* register bus (AHB) */
  233. struct icc_path *reg_bus_hdl;
  234. u32 reg_bus_usecase_ndx;
  235. struct list_head reg_bus_clist;
  236. struct mutex reg_bus_lock;
  237. u32 *vbif_rt_qos;
  238. u32 *vbif_nrt_qos;
  239. u32 npriority_lvl;
  240. u32 vbif_xin_id[MAX_XIN];
  241. struct pm_qos_request pm_qos_rot_cpu_req;
  242. u32 rot_pm_qos_cpu_count;
  243. u32 rot_pm_qos_cpu_mask;
  244. u32 rot_pm_qos_cpu_dma_latency;
  245. u32 vbif_memtype_count;
  246. u32 *vbif_memtype;
  247. int iommu_attached;
  248. int iommu_ref_cnt;
  249. struct sde_rot_vbif_debug_bus *nrt_vbif_dbg_bus;
  250. u32 nrt_vbif_dbg_bus_size;
  251. struct sde_rot_debug_bus *rot_dbg_bus;
  252. u32 rot_dbg_bus_size;
  253. struct sde_rot_regdump *regdump;
  254. u32 regdump_size;
  255. void *sde_rot_hw;
  256. int sec_cam_en;
  257. u32 enable_cdp[SDE_ROT_OP_MAX];
  258. struct sde_rot_lut_cfg lut_cfg[SDE_ROT_OP_MAX];
  259. struct sde_rot_lut_cfg inline_lut_cfg[SDE_ROT_OP_MAX];
  260. bool clk_always_on;
  261. };
  262. int sde_rotator_base_init(struct sde_rot_data_type **pmdata,
  263. struct platform_device *pdev,
  264. const void *drvdata);
  265. void sde_rotator_base_destroy(struct sde_rot_data_type *data);
  266. #if IS_ENABLED(CONFIG_MSM_SDE_ROTATOR)
  267. struct sde_rot_data_type *sde_rot_get_mdata(void);
  268. #else
  269. static inline struct sde_rot_data_type *sde_rot_get_mdata(void)
  270. {
  271. return NULL;
  272. }
  273. #endif /* CONFIG_MSM_SDE_ROTATOR */
  274. struct reg_bus_client *sde_reg_bus_vote_client_create(char *client_name);
  275. void sde_reg_bus_vote_client_destroy(struct reg_bus_client *client);
  276. int sde_update_reg_bus_vote(struct reg_bus_client *bus_client, u32 usecase_ndx);
  277. u32 sde_apply_comp_ratio_factor(u32 quota,
  278. struct sde_mdp_format_params *fmt,
  279. struct sde_mult_factor *factor);
  280. u32 sde_mdp_get_ot_limit(u32 width, u32 height, u32 pixfmt, u32 fps, u32 is_rd);
  281. void sde_mdp_set_ot_limit(struct sde_mdp_set_ot_params *params);
  282. void vbif_lock(struct platform_device *parent_pdev);
  283. void vbif_unlock(struct platform_device *parent_pdev);
  284. void sde_mdp_halt_vbif_xin(struct sde_mdp_vbif_halt_params *params);
  285. int sde_mdp_init_vbif(void);
  286. const struct sde_rot_bus_data *sde_get_rot_reg_bus_value(u32 usecase_ndx);
  287. #define SDE_VBIF_WRITE(mdata, offset, value) \
  288. (sde_reg_w(&mdata->vbif_nrt_io, offset, value, 0))
  289. #define SDE_VBIF_READ(mdata, offset) \
  290. (sde_reg_r(&mdata->vbif_nrt_io, offset, 0))
  291. #define SDE_REG_WRITE(mdata, offset, value) \
  292. sde_reg_w(&mdata->sde_io, offset, value, 0)
  293. #define SDE_REG_READ(mdata, offset) \
  294. sde_reg_r(&mdata->sde_io, offset, 0)
  295. #define ATRACE_END(name) trace_rot_mark_write(current->tgid, name, 0)
  296. #define ATRACE_BEGIN(name) trace_rot_mark_write(current->tgid, name, 1)
  297. #define ATRACE_INT(name, value) \
  298. trace_rot_trace_counter(current->tgid, name, value)
  299. #endif /* __SDE_ROTATOR_BASE__ */