dp_main.c 145 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_tx_desc.h"
  32. #include "dp_rx.h"
  33. #include <cdp_txrx_handle.h>
  34. #include <wlan_cfg.h>
  35. #include "cdp_txrx_cmn_struct.h"
  36. #include <qdf_util.h>
  37. #include "dp_peer.h"
  38. #include "dp_rx_mon.h"
  39. #include "htt_stats.h"
  40. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  41. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  42. #include "cdp_txrx_flow_ctrl_v2.h"
  43. #else
  44. static inline void
  45. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  46. {
  47. return;
  48. }
  49. #endif
  50. #include <ol_cfg.h>
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0x7
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. /**
  70. * default_dscp_tid_map - Default DSCP-TID mapping
  71. *
  72. * DSCP TID AC
  73. * 000000 0 WME_AC_BE
  74. * 001000 1 WME_AC_BK
  75. * 010000 1 WME_AC_BK
  76. * 011000 0 WME_AC_BE
  77. * 100000 5 WME_AC_VI
  78. * 101000 5 WME_AC_VI
  79. * 110000 6 WME_AC_VO
  80. * 111000 6 WME_AC_VO
  81. */
  82. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  83. 0, 0, 0, 0, 0, 0, 0, 0,
  84. 1, 1, 1, 1, 1, 1, 1, 1,
  85. 1, 1, 1, 1, 1, 1, 1, 1,
  86. 0, 0, 0, 0, 0, 0, 0, 0,
  87. 5, 5, 5, 5, 5, 5, 5, 5,
  88. 5, 5, 5, 5, 5, 5, 5, 5,
  89. 6, 6, 6, 6, 6, 6, 6, 6,
  90. 6, 6, 6, 6, 6, 6, 6, 6,
  91. };
  92. /*
  93. * struct dp_rate_debug
  94. *
  95. * @mcs_type: print string for a given mcs
  96. * @valid: valid mcs rate?
  97. */
  98. struct dp_rate_debug {
  99. char mcs_type[DP_MAX_MCS_STRING_LEN];
  100. uint8_t valid;
  101. };
  102. #define MCS_VALID 1
  103. #define MCS_INVALID 0
  104. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  105. {
  106. {"CCK 11 Mbps Long ", MCS_VALID},
  107. {"CCK 5.5 Mbps Long ", MCS_VALID},
  108. {"CCK 2 Mbps Long ", MCS_VALID},
  109. {"CCK 1 Mbps Long ", MCS_VALID},
  110. {"CCK 11 Mbps Short ", MCS_VALID},
  111. {"CCK 5.5 Mbps Short", MCS_VALID},
  112. {"CCK 2 Mbps Short ", MCS_VALID},
  113. {"INVALID ", MCS_INVALID},
  114. {"INVALID ", MCS_INVALID},
  115. {"INVALID ", MCS_INVALID},
  116. {"INVALID ", MCS_INVALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_VALID},
  119. },
  120. {
  121. {"OFDM 48 Mbps", MCS_VALID},
  122. {"OFDM 24 Mbps", MCS_VALID},
  123. {"OFDM 12 Mbps", MCS_VALID},
  124. {"OFDM 6 Mbps ", MCS_VALID},
  125. {"OFDM 54 Mbps", MCS_VALID},
  126. {"OFDM 36 Mbps", MCS_VALID},
  127. {"OFDM 18 Mbps", MCS_VALID},
  128. {"OFDM 9 Mbps ", MCS_VALID},
  129. {"INVALID ", MCS_INVALID},
  130. {"INVALID ", MCS_INVALID},
  131. {"INVALID ", MCS_INVALID},
  132. {"INVALID ", MCS_INVALID},
  133. {"INVALID ", MCS_VALID},
  134. },
  135. {
  136. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  137. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  138. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  139. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  140. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  141. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  142. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  143. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  144. {"INVALID ", MCS_INVALID},
  145. {"INVALID ", MCS_INVALID},
  146. {"INVALID ", MCS_INVALID},
  147. {"INVALID ", MCS_INVALID},
  148. {"INVALID ", MCS_VALID},
  149. },
  150. {
  151. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  152. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  153. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  154. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  155. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  156. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  157. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  158. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  159. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  161. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  162. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  163. {"INVALID ", MCS_VALID},
  164. },
  165. {
  166. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  167. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  168. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  169. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  170. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  171. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  172. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  173. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  174. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  176. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  177. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  178. {"INVALID ", MCS_VALID},
  179. }
  180. };
  181. /**
  182. * @brief Cpu ring map types
  183. */
  184. enum dp_cpu_ring_map_types {
  185. DP_DEFAULT_MAP,
  186. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  187. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  188. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  189. DP_CPU_RING_MAP_MAX
  190. };
  191. /**
  192. * @brief Cpu to tx ring map
  193. */
  194. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  195. {0x0, 0x1, 0x2, 0x0},
  196. {0x1, 0x2, 0x1, 0x2},
  197. {0x0, 0x2, 0x0, 0x2},
  198. {0x2, 0x2, 0x2, 0x2}
  199. };
  200. /**
  201. * @brief Select the type of statistics
  202. */
  203. enum dp_stats_type {
  204. STATS_FW = 0,
  205. STATS_HOST = 1,
  206. STATS_TYPE_MAX = 2,
  207. };
  208. /**
  209. * @brief General Firmware statistics options
  210. *
  211. */
  212. enum dp_fw_stats {
  213. TXRX_FW_STATS_INVALID = -1,
  214. };
  215. /**
  216. * dp_stats_mapping_table - Firmware and Host statistics
  217. * currently supported
  218. */
  219. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  220. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  221. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  222. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  223. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  224. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  231. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  239. /* Last ENUM for HTT FW STATS */
  240. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  241. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  242. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  243. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  244. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  245. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  246. };
  247. /**
  248. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  249. * @ring_num: ring num of the ring being queried
  250. * @grp_mask: the grp_mask array for the ring type in question.
  251. *
  252. * The grp_mask array is indexed by group number and the bit fields correspond
  253. * to ring numbers. We are finding which interrupt group a ring belongs to.
  254. *
  255. * Return: the index in the grp_mask array with the ring number.
  256. * -QDF_STATUS_E_NOENT if no entry is found
  257. */
  258. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  259. {
  260. int ext_group_num;
  261. int mask = 1 << ring_num;
  262. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  263. ext_group_num++) {
  264. if (mask & grp_mask[ext_group_num])
  265. return ext_group_num;
  266. }
  267. return -QDF_STATUS_E_NOENT;
  268. }
  269. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  270. enum hal_ring_type ring_type,
  271. int ring_num)
  272. {
  273. int *grp_mask;
  274. switch (ring_type) {
  275. case WBM2SW_RELEASE:
  276. /* dp_tx_comp_handler - soc->tx_comp_ring */
  277. if (ring_num < 3)
  278. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  279. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  280. else if (ring_num == 3) {
  281. /* sw treats this as a separate ring type */
  282. grp_mask = &soc->wlan_cfg_ctx->
  283. int_rx_wbm_rel_ring_mask[0];
  284. ring_num = 0;
  285. } else {
  286. qdf_assert(0);
  287. return -QDF_STATUS_E_NOENT;
  288. }
  289. break;
  290. case REO_EXCEPTION:
  291. /* dp_rx_err_process - &soc->reo_exception_ring */
  292. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  293. break;
  294. case REO_DST:
  295. /* dp_rx_process - soc->reo_dest_ring */
  296. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  297. break;
  298. case REO_STATUS:
  299. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  300. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  301. break;
  302. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  303. case RXDMA_MONITOR_STATUS:
  304. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  305. case RXDMA_MONITOR_DST:
  306. /* dp_mon_process */
  307. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  308. break;
  309. case RXDMA_MONITOR_BUF:
  310. case RXDMA_BUF:
  311. /* TODO: support low_thresh interrupt */
  312. return -QDF_STATUS_E_NOENT;
  313. break;
  314. case TCL_DATA:
  315. case TCL_CMD:
  316. case REO_CMD:
  317. case SW2WBM_RELEASE:
  318. case WBM_IDLE_LINK:
  319. /* normally empty SW_TO_HW rings */
  320. return -QDF_STATUS_E_NOENT;
  321. break;
  322. case TCL_STATUS:
  323. case REO_REINJECT:
  324. case RXDMA_DST:
  325. /* misc unused rings */
  326. return -QDF_STATUS_E_NOENT;
  327. break;
  328. case CE_SRC:
  329. case CE_DST:
  330. case CE_DST_STATUS:
  331. /* CE_rings - currently handled by hif */
  332. default:
  333. return -QDF_STATUS_E_NOENT;
  334. break;
  335. }
  336. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  337. }
  338. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  339. *ring_params, int ring_type, int ring_num)
  340. {
  341. int msi_group_number;
  342. int msi_data_count;
  343. int ret;
  344. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  345. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  346. &msi_data_count, &msi_data_start,
  347. &msi_irq_start);
  348. if (ret)
  349. return;
  350. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  351. ring_num);
  352. if (msi_group_number < 0) {
  353. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  354. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  355. ring_type, ring_num);
  356. ring_params->msi_addr = 0;
  357. ring_params->msi_data = 0;
  358. return;
  359. }
  360. if (msi_group_number > msi_data_count) {
  361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  362. FL("2 msi_groups will share an msi; msi_group_num %d"),
  363. msi_group_number);
  364. QDF_ASSERT(0);
  365. }
  366. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  367. ring_params->msi_addr = addr_low;
  368. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  369. ring_params->msi_data = (msi_group_number % msi_data_count)
  370. + msi_data_start;
  371. ring_params->flags |= HAL_SRNG_MSI_INTR;
  372. }
  373. /**
  374. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  375. */
  376. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  377. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  378. {
  379. void *hal_soc = soc->hal_soc;
  380. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  381. /* TODO: See if we should get align size from hal */
  382. uint32_t ring_base_align = 8;
  383. struct hal_srng_params ring_params;
  384. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  385. /* TODO: Currently hal layer takes care of endianness related settings.
  386. * See if these settings need to passed from DP layer
  387. */
  388. ring_params.flags = 0;
  389. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  390. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  391. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  392. srng->hal_srng = NULL;
  393. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  394. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  395. soc->osdev, soc->osdev->dev, srng->alloc_size,
  396. &(srng->base_paddr_unaligned));
  397. if (!srng->base_vaddr_unaligned) {
  398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  399. FL("alloc failed - ring_type: %d, ring_num %d"),
  400. ring_type, ring_num);
  401. return QDF_STATUS_E_NOMEM;
  402. }
  403. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  404. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  405. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  406. ((unsigned long)(ring_params.ring_base_vaddr) -
  407. (unsigned long)srng->base_vaddr_unaligned);
  408. ring_params.num_entries = num_entries;
  409. if (soc->intr_mode == DP_INTR_MSI) {
  410. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  411. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  412. FL("Using MSI for ring_type: %d, ring_num %d"),
  413. ring_type, ring_num);
  414. } else {
  415. ring_params.msi_data = 0;
  416. ring_params.msi_addr = 0;
  417. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  418. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  419. ring_type, ring_num);
  420. }
  421. /*
  422. * Setup interrupt timer and batch counter thresholds for
  423. * interrupt mitigation based on ring type
  424. */
  425. if (ring_type == REO_DST) {
  426. ring_params.intr_timer_thres_us =
  427. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  428. ring_params.intr_batch_cntr_thres_entries =
  429. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  430. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  431. ring_params.intr_timer_thres_us =
  432. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  433. ring_params.intr_batch_cntr_thres_entries =
  434. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  435. } else {
  436. ring_params.intr_timer_thres_us =
  437. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  438. ring_params.intr_batch_cntr_thres_entries =
  439. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  440. }
  441. /* Enable low threshold interrupts for rx buffer rings (regular and
  442. * monitor buffer rings.
  443. * TODO: See if this is required for any other ring
  444. */
  445. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  446. /* TODO: Setting low threshold to 1/8th of ring size
  447. * see if this needs to be configurable
  448. */
  449. ring_params.low_threshold = num_entries >> 3;
  450. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  451. ring_params.intr_timer_thres_us = 0x1000;
  452. }
  453. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  454. mac_id, &ring_params);
  455. return 0;
  456. }
  457. /**
  458. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  459. * Any buffers allocated and attached to ring entries are expected to be freed
  460. * before calling this function.
  461. */
  462. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  463. int ring_type, int ring_num)
  464. {
  465. if (!srng->hal_srng) {
  466. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  467. FL("Ring type: %d, num:%d not setup"),
  468. ring_type, ring_num);
  469. return;
  470. }
  471. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  472. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  473. srng->alloc_size,
  474. srng->base_vaddr_unaligned,
  475. srng->base_paddr_unaligned, 0);
  476. }
  477. #ifdef IPA_OFFLOAD
  478. /**
  479. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  480. * @soc: data path instance
  481. * @pdev: core txrx pdev context
  482. *
  483. * Free allocated TX buffers with WBM SRNG
  484. *
  485. * Return: none
  486. */
  487. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  488. {
  489. int idx;
  490. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  491. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  492. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  493. }
  494. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  495. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  496. }
  497. /**
  498. * dp_rx_ipa_uc_detach - free autonomy RX resources
  499. * @soc: data path instance
  500. * @pdev: core txrx pdev context
  501. *
  502. * This function will detach DP RX into main device context
  503. * will free DP Rx resources.
  504. *
  505. * Return: none
  506. */
  507. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  508. {
  509. }
  510. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  511. {
  512. /* TX resource detach */
  513. dp_tx_ipa_uc_detach(soc, pdev);
  514. /* RX resource detach */
  515. dp_rx_ipa_uc_detach(soc, pdev);
  516. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  517. return QDF_STATUS_SUCCESS; /* success */
  518. }
  519. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  520. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  521. /**
  522. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  523. * @soc: data path instance
  524. * @pdev: Physical device handle
  525. *
  526. * Allocate TX buffer from non-cacheable memory
  527. * Attache allocated TX buffers with WBM SRNG
  528. *
  529. * Return: int
  530. */
  531. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  532. {
  533. uint32_t tx_buffer_count;
  534. uint32_t ring_base_align = 8;
  535. void *buffer_vaddr_unaligned;
  536. void *buffer_vaddr;
  537. qdf_dma_addr_t buffer_paddr_unaligned;
  538. qdf_dma_addr_t buffer_paddr;
  539. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  540. uint32_t paddr_lo;
  541. uint32_t paddr_hi;
  542. void *ring_entry;
  543. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  544. int retval = QDF_STATUS_SUCCESS;
  545. /*
  546. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  547. * unsigned int uc_tx_buf_sz =
  548. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  549. */
  550. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  551. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  553. "requested %d buffers to be posted to wbm ring",
  554. ring_size);
  555. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  556. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  557. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  559. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  560. return -ENOMEM;
  561. }
  562. hal_srng_access_start(soc->hal_soc, wbm_srng);
  563. /* Allocate TX buffers as many as possible */
  564. for (tx_buffer_count = 0;
  565. tx_buffer_count < ring_size; tx_buffer_count++) {
  566. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  567. if (!ring_entry) {
  568. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  569. "Failed to get WBM ring entry\n");
  570. goto fail;
  571. }
  572. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  573. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  574. if (!buffer_vaddr_unaligned) {
  575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  576. "IPA WDI TX buffer alloc fail %d allocated\n",
  577. tx_buffer_count);
  578. break;
  579. }
  580. buffer_vaddr = buffer_vaddr_unaligned +
  581. ((unsigned long)buffer_vaddr_unaligned %
  582. ring_base_align);
  583. buffer_paddr = buffer_paddr_unaligned +
  584. ((unsigned long)(buffer_vaddr) -
  585. (unsigned long)buffer_vaddr_unaligned);
  586. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  587. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  588. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  589. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  590. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  591. buffer_vaddr;
  592. }
  593. hal_srng_access_end(soc->hal_soc, wbm_srng);
  594. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  595. return retval;
  596. fail:
  597. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  598. return retval;
  599. }
  600. /**
  601. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  602. * @soc: data path instance
  603. * @pdev: core txrx pdev context
  604. *
  605. * This function will attach a DP RX instance into the main
  606. * device (SOC) context.
  607. *
  608. * Return: QDF_STATUS_SUCCESS: success
  609. * QDF_STATUS_E_RESOURCES: Error return
  610. */
  611. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  612. {
  613. return QDF_STATUS_SUCCESS;
  614. }
  615. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  616. {
  617. int error;
  618. /* TX resource attach */
  619. error = dp_tx_ipa_uc_attach(soc, pdev);
  620. if (error) {
  621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  622. "DP IPA UC TX attach fail code %d\n", error);
  623. return error;
  624. }
  625. /* RX resource attach */
  626. error = dp_rx_ipa_uc_attach(soc, pdev);
  627. if (error) {
  628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  629. "DP IPA UC RX attach fail code %d\n", error);
  630. dp_tx_ipa_uc_detach(soc, pdev);
  631. return error;
  632. }
  633. return QDF_STATUS_SUCCESS; /* success */
  634. }
  635. #else
  636. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  637. {
  638. return QDF_STATUS_SUCCESS;
  639. }
  640. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  641. {
  642. return QDF_STATUS_SUCCESS;
  643. }
  644. #endif
  645. /* TODO: Need this interface from HIF */
  646. void *hif_get_hal_handle(void *hif_handle);
  647. /*
  648. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  649. * @dp_ctx: DP SOC handle
  650. * @budget: Number of frames/descriptors that can be processed in one shot
  651. *
  652. * Return: remaining budget/quota for the soc device
  653. */
  654. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  655. {
  656. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  657. struct dp_soc *soc = int_ctx->soc;
  658. int ring = 0;
  659. uint32_t work_done = 0;
  660. uint32_t budget = dp_budget;
  661. uint8_t tx_mask = int_ctx->tx_ring_mask;
  662. uint8_t rx_mask = int_ctx->rx_ring_mask;
  663. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  664. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  665. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  666. /* Process Tx completion interrupts first to return back buffers */
  667. if (tx_mask) {
  668. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  669. if (tx_mask & (1 << ring)) {
  670. work_done =
  671. dp_tx_comp_handler(soc, ring, budget);
  672. budget -= work_done;
  673. if (work_done)
  674. QDF_TRACE(QDF_MODULE_ID_DP,
  675. QDF_TRACE_LEVEL_INFO,
  676. "tx mask 0x%x ring %d,"
  677. "budget %d",
  678. tx_mask, ring, budget);
  679. if (budget <= 0)
  680. goto budget_done;
  681. }
  682. }
  683. }
  684. /* Process REO Exception ring interrupt */
  685. if (rx_err_mask) {
  686. work_done = dp_rx_err_process(soc,
  687. soc->reo_exception_ring.hal_srng, budget);
  688. budget -= work_done;
  689. if (work_done)
  690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  691. "REO Exception Ring: work_done %d budget %d",
  692. work_done, budget);
  693. if (budget <= 0) {
  694. goto budget_done;
  695. }
  696. }
  697. /* Process Rx WBM release ring interrupt */
  698. if (rx_wbm_rel_mask) {
  699. work_done = dp_rx_wbm_err_process(soc,
  700. soc->rx_rel_ring.hal_srng, budget);
  701. budget -= work_done;
  702. if (work_done)
  703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  704. "WBM Release Ring: work_done %d budget %d",
  705. work_done, budget);
  706. if (budget <= 0) {
  707. goto budget_done;
  708. }
  709. }
  710. /* Process Rx interrupts */
  711. if (rx_mask) {
  712. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  713. if (rx_mask & (1 << ring)) {
  714. work_done =
  715. dp_rx_process(int_ctx,
  716. soc->reo_dest_ring[ring].hal_srng,
  717. budget);
  718. budget -= work_done;
  719. if (work_done)
  720. QDF_TRACE(QDF_MODULE_ID_DP,
  721. QDF_TRACE_LEVEL_INFO,
  722. "rx mask 0x%x ring %d,"
  723. "budget %d",
  724. tx_mask, ring, budget);
  725. if (budget <= 0)
  726. goto budget_done;
  727. }
  728. }
  729. }
  730. if (reo_status_mask)
  731. dp_reo_status_ring_handler(soc);
  732. /* Process LMAC interrupts */
  733. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  734. if (soc->pdev_list[ring] == NULL)
  735. continue;
  736. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  737. work_done =
  738. dp_mon_process(soc, ring, budget);
  739. budget -= work_done;
  740. }
  741. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  742. work_done =
  743. dp_rxdma_err_process(soc, ring, budget);
  744. budget -= work_done;
  745. }
  746. }
  747. qdf_lro_flush(int_ctx->lro_ctx);
  748. budget_done:
  749. return dp_budget - budget;
  750. }
  751. #ifdef DP_INTR_POLL_BASED
  752. /* dp_interrupt_timer()- timer poll for interrupts
  753. *
  754. * @arg: SoC Handle
  755. *
  756. * Return:
  757. *
  758. */
  759. static void dp_interrupt_timer(void *arg)
  760. {
  761. struct dp_soc *soc = (struct dp_soc *) arg;
  762. int i;
  763. if (qdf_atomic_read(&soc->cmn_init_done)) {
  764. for (i = 0;
  765. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  766. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  767. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  768. }
  769. }
  770. /*
  771. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  772. * @txrx_soc: DP SOC handle
  773. *
  774. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  775. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  776. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  777. *
  778. * Return: 0 for success. nonzero for failure.
  779. */
  780. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  781. {
  782. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  783. int i;
  784. soc->intr_mode = DP_INTR_POLL;
  785. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  786. soc->intr_ctx[i].dp_intr_id = i;
  787. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  788. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  789. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  790. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  791. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  792. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  793. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  794. soc->intr_ctx[i].soc = soc;
  795. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  796. }
  797. qdf_timer_init(soc->osdev, &soc->int_timer,
  798. dp_interrupt_timer, (void *)soc,
  799. QDF_TIMER_TYPE_WAKE_APPS);
  800. return QDF_STATUS_SUCCESS;
  801. }
  802. #ifdef CONFIG_MCL
  803. extern int con_mode_monitor;
  804. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  805. /*
  806. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  807. * @txrx_soc: DP SOC handle
  808. *
  809. * Call the appropriate attach function based on the mode of operation.
  810. * This is a WAR for enabling monitor mode.
  811. *
  812. * Return: 0 for success. nonzero for failure.
  813. */
  814. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  815. {
  816. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  818. FL("Attach interrupts in Poll mode"));
  819. return dp_soc_interrupt_attach_poll(txrx_soc);
  820. } else {
  821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  822. FL("Attach interrupts in MSI mode"));
  823. return dp_soc_interrupt_attach(txrx_soc);
  824. }
  825. }
  826. #else
  827. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  828. {
  829. return dp_soc_interrupt_attach_poll(txrx_soc);
  830. }
  831. #endif
  832. #endif
  833. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  834. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  835. {
  836. int j;
  837. int num_irq = 0;
  838. int tx_mask =
  839. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  840. int rx_mask =
  841. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  842. int rx_mon_mask =
  843. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  844. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  845. soc->wlan_cfg_ctx, intr_ctx_num);
  846. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  847. soc->wlan_cfg_ctx, intr_ctx_num);
  848. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  849. soc->wlan_cfg_ctx, intr_ctx_num);
  850. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  851. if (tx_mask & (1 << j)) {
  852. irq_id_map[num_irq++] =
  853. (wbm2host_tx_completions_ring1 - j);
  854. }
  855. if (rx_mask & (1 << j)) {
  856. irq_id_map[num_irq++] =
  857. (reo2host_destination_ring1 - j);
  858. }
  859. if (rx_mon_mask & (1 << j)) {
  860. irq_id_map[num_irq++] =
  861. (ppdu_end_interrupts_mac1 - j);
  862. }
  863. if (rx_wbm_rel_ring_mask & (1 << j))
  864. irq_id_map[num_irq++] = wbm2host_rx_release;
  865. if (rx_err_ring_mask & (1 << j))
  866. irq_id_map[num_irq++] = reo2host_exception;
  867. if (reo_status_ring_mask & (1 << j))
  868. irq_id_map[num_irq++] = reo2host_status;
  869. }
  870. *num_irq_r = num_irq;
  871. }
  872. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  873. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  874. int msi_vector_count, int msi_vector_start)
  875. {
  876. int tx_mask = wlan_cfg_get_tx_ring_mask(
  877. soc->wlan_cfg_ctx, intr_ctx_num);
  878. int rx_mask = wlan_cfg_get_rx_ring_mask(
  879. soc->wlan_cfg_ctx, intr_ctx_num);
  880. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  881. soc->wlan_cfg_ctx, intr_ctx_num);
  882. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  883. soc->wlan_cfg_ctx, intr_ctx_num);
  884. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  885. soc->wlan_cfg_ctx, intr_ctx_num);
  886. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  887. soc->wlan_cfg_ctx, intr_ctx_num);
  888. unsigned int vector =
  889. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  890. int num_irq = 0;
  891. soc->intr_mode = DP_INTR_MSI;
  892. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  893. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  894. irq_id_map[num_irq++] =
  895. pld_get_msi_irq(soc->osdev->dev, vector);
  896. *num_irq_r = num_irq;
  897. }
  898. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  899. int *irq_id_map, int *num_irq)
  900. {
  901. int msi_vector_count, ret;
  902. uint32_t msi_base_data, msi_vector_start;
  903. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  904. &msi_vector_count,
  905. &msi_base_data,
  906. &msi_vector_start);
  907. if (ret)
  908. return dp_soc_interrupt_map_calculate_integrated(soc,
  909. intr_ctx_num, irq_id_map, num_irq);
  910. else
  911. dp_soc_interrupt_map_calculate_msi(soc,
  912. intr_ctx_num, irq_id_map, num_irq,
  913. msi_vector_count, msi_vector_start);
  914. }
  915. /*
  916. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  917. * @txrx_soc: DP SOC handle
  918. *
  919. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  920. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  921. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  922. *
  923. * Return: 0 for success. nonzero for failure.
  924. */
  925. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  926. {
  927. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  928. int i = 0;
  929. int num_irq = 0;
  930. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  931. int ret = 0;
  932. /* Map of IRQ ids registered with one interrupt context */
  933. int irq_id_map[HIF_MAX_GRP_IRQ];
  934. int tx_mask =
  935. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  936. int rx_mask =
  937. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  938. int rx_mon_mask =
  939. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  940. int rx_err_ring_mask =
  941. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  942. int rx_wbm_rel_ring_mask =
  943. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  944. int reo_status_ring_mask =
  945. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  946. int rxdma2host_ring_mask =
  947. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  948. soc->intr_ctx[i].dp_intr_id = i;
  949. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  950. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  951. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  952. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  953. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  954. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  955. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  956. soc->intr_ctx[i].soc = soc;
  957. num_irq = 0;
  958. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  959. &num_irq);
  960. ret = hif_register_ext_group(soc->hif_handle,
  961. num_irq, irq_id_map, dp_service_srngs,
  962. &soc->intr_ctx[i], "dp_intr",
  963. HIF_EXEC_NAPI_TYPE);
  964. if (ret) {
  965. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  966. FL("failed, ret = %d"), ret);
  967. return QDF_STATUS_E_FAILURE;
  968. }
  969. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  970. }
  971. hif_configure_ext_group_interrupts(soc->hif_handle);
  972. return QDF_STATUS_SUCCESS;
  973. }
  974. /*
  975. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  976. * @txrx_soc: DP SOC handle
  977. *
  978. * Return: void
  979. */
  980. static void dp_soc_interrupt_detach(void *txrx_soc)
  981. {
  982. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  983. int i;
  984. if (soc->intr_mode == DP_INTR_POLL) {
  985. qdf_timer_stop(&soc->int_timer);
  986. qdf_timer_free(&soc->int_timer);
  987. }
  988. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  989. soc->intr_ctx[i].tx_ring_mask = 0;
  990. soc->intr_ctx[i].rx_ring_mask = 0;
  991. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  992. soc->intr_ctx[i].rx_err_ring_mask = 0;
  993. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  994. soc->intr_ctx[i].reo_status_ring_mask = 0;
  995. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  996. }
  997. }
  998. #define AVG_MAX_MPDUS_PER_TID 128
  999. #define AVG_TIDS_PER_CLIENT 2
  1000. #define AVG_FLOWS_PER_TID 2
  1001. #define AVG_MSDUS_PER_FLOW 128
  1002. #define AVG_MSDUS_PER_MPDU 4
  1003. /*
  1004. * Allocate and setup link descriptor pool that will be used by HW for
  1005. * various link and queue descriptors and managed by WBM
  1006. */
  1007. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1008. {
  1009. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1010. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1011. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1012. uint32_t num_mpdus_per_link_desc =
  1013. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1014. uint32_t num_msdus_per_link_desc =
  1015. hal_num_msdus_per_link_desc(soc->hal_soc);
  1016. uint32_t num_mpdu_links_per_queue_desc =
  1017. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1018. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1019. uint32_t total_link_descs, total_mem_size;
  1020. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1021. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1022. uint32_t num_link_desc_banks;
  1023. uint32_t last_bank_size = 0;
  1024. uint32_t entry_size, num_entries;
  1025. int i;
  1026. uint32_t desc_id = 0;
  1027. /* Only Tx queue descriptors are allocated from common link descriptor
  1028. * pool Rx queue descriptors are not included in this because (REO queue
  1029. * extension descriptors) they are expected to be allocated contiguously
  1030. * with REO queue descriptors
  1031. */
  1032. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1033. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1034. num_mpdu_queue_descs = num_mpdu_link_descs /
  1035. num_mpdu_links_per_queue_desc;
  1036. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1037. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1038. num_msdus_per_link_desc;
  1039. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1040. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1041. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1042. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1043. /* Round up to power of 2 */
  1044. total_link_descs = 1;
  1045. while (total_link_descs < num_entries)
  1046. total_link_descs <<= 1;
  1047. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1048. FL("total_link_descs: %u, link_desc_size: %d"),
  1049. total_link_descs, link_desc_size);
  1050. total_mem_size = total_link_descs * link_desc_size;
  1051. total_mem_size += link_desc_align;
  1052. if (total_mem_size <= max_alloc_size) {
  1053. num_link_desc_banks = 0;
  1054. last_bank_size = total_mem_size;
  1055. } else {
  1056. num_link_desc_banks = (total_mem_size) /
  1057. (max_alloc_size - link_desc_align);
  1058. last_bank_size = total_mem_size %
  1059. (max_alloc_size - link_desc_align);
  1060. }
  1061. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1062. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1063. total_mem_size, num_link_desc_banks);
  1064. for (i = 0; i < num_link_desc_banks; i++) {
  1065. soc->link_desc_banks[i].base_vaddr_unaligned =
  1066. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1067. max_alloc_size,
  1068. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1069. soc->link_desc_banks[i].size = max_alloc_size;
  1070. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1071. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1072. ((unsigned long)(
  1073. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1074. link_desc_align));
  1075. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1076. soc->link_desc_banks[i].base_paddr_unaligned) +
  1077. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1078. (unsigned long)(
  1079. soc->link_desc_banks[i].base_vaddr_unaligned));
  1080. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1082. FL("Link descriptor memory alloc failed"));
  1083. goto fail;
  1084. }
  1085. }
  1086. if (last_bank_size) {
  1087. /* Allocate last bank in case total memory required is not exact
  1088. * multiple of max_alloc_size
  1089. */
  1090. soc->link_desc_banks[i].base_vaddr_unaligned =
  1091. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1092. last_bank_size,
  1093. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1094. soc->link_desc_banks[i].size = last_bank_size;
  1095. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1096. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1097. ((unsigned long)(
  1098. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1099. link_desc_align));
  1100. soc->link_desc_banks[i].base_paddr =
  1101. (unsigned long)(
  1102. soc->link_desc_banks[i].base_paddr_unaligned) +
  1103. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1104. (unsigned long)(
  1105. soc->link_desc_banks[i].base_vaddr_unaligned));
  1106. }
  1107. /* Allocate and setup link descriptor idle list for HW internal use */
  1108. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1109. total_mem_size = entry_size * total_link_descs;
  1110. if (total_mem_size <= max_alloc_size) {
  1111. void *desc;
  1112. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1113. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1114. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1115. FL("Link desc idle ring setup failed"));
  1116. goto fail;
  1117. }
  1118. hal_srng_access_start_unlocked(soc->hal_soc,
  1119. soc->wbm_idle_link_ring.hal_srng);
  1120. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1121. soc->link_desc_banks[i].base_paddr; i++) {
  1122. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1123. ((unsigned long)(
  1124. soc->link_desc_banks[i].base_vaddr) -
  1125. (unsigned long)(
  1126. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1127. / link_desc_size;
  1128. unsigned long paddr = (unsigned long)(
  1129. soc->link_desc_banks[i].base_paddr);
  1130. while (num_entries && (desc = hal_srng_src_get_next(
  1131. soc->hal_soc,
  1132. soc->wbm_idle_link_ring.hal_srng))) {
  1133. hal_set_link_desc_addr(desc,
  1134. LINK_DESC_COOKIE(desc_id, i), paddr);
  1135. num_entries--;
  1136. desc_id++;
  1137. paddr += link_desc_size;
  1138. }
  1139. }
  1140. hal_srng_access_end_unlocked(soc->hal_soc,
  1141. soc->wbm_idle_link_ring.hal_srng);
  1142. } else {
  1143. uint32_t num_scatter_bufs;
  1144. uint32_t num_entries_per_buf;
  1145. uint32_t rem_entries;
  1146. uint8_t *scatter_buf_ptr;
  1147. uint16_t scatter_buf_num;
  1148. soc->wbm_idle_scatter_buf_size =
  1149. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1150. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1151. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1152. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1153. soc->hal_soc, total_mem_size,
  1154. soc->wbm_idle_scatter_buf_size);
  1155. for (i = 0; i < num_scatter_bufs; i++) {
  1156. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1157. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1158. soc->wbm_idle_scatter_buf_size,
  1159. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1160. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1161. QDF_TRACE(QDF_MODULE_ID_DP,
  1162. QDF_TRACE_LEVEL_ERROR,
  1163. FL("Scatter list memory alloc failed"));
  1164. goto fail;
  1165. }
  1166. }
  1167. /* Populate idle list scatter buffers with link descriptor
  1168. * pointers
  1169. */
  1170. scatter_buf_num = 0;
  1171. scatter_buf_ptr = (uint8_t *)(
  1172. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1173. rem_entries = num_entries_per_buf;
  1174. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1175. soc->link_desc_banks[i].base_paddr; i++) {
  1176. uint32_t num_link_descs =
  1177. (soc->link_desc_banks[i].size -
  1178. ((unsigned long)(
  1179. soc->link_desc_banks[i].base_vaddr) -
  1180. (unsigned long)(
  1181. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1182. / link_desc_size;
  1183. unsigned long paddr = (unsigned long)(
  1184. soc->link_desc_banks[i].base_paddr);
  1185. while (num_link_descs) {
  1186. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1187. LINK_DESC_COOKIE(desc_id, i), paddr);
  1188. num_link_descs--;
  1189. desc_id++;
  1190. paddr += link_desc_size;
  1191. rem_entries--;
  1192. if (rem_entries) {
  1193. scatter_buf_ptr += entry_size;
  1194. } else {
  1195. rem_entries = num_entries_per_buf;
  1196. scatter_buf_num++;
  1197. if (scatter_buf_num >= num_scatter_bufs)
  1198. break;
  1199. scatter_buf_ptr = (uint8_t *)(
  1200. soc->wbm_idle_scatter_buf_base_vaddr[
  1201. scatter_buf_num]);
  1202. }
  1203. }
  1204. }
  1205. /* Setup link descriptor idle list in HW */
  1206. hal_setup_link_idle_list(soc->hal_soc,
  1207. soc->wbm_idle_scatter_buf_base_paddr,
  1208. soc->wbm_idle_scatter_buf_base_vaddr,
  1209. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1210. (uint32_t)(scatter_buf_ptr -
  1211. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1212. scatter_buf_num-1])), total_link_descs);
  1213. }
  1214. return 0;
  1215. fail:
  1216. if (soc->wbm_idle_link_ring.hal_srng) {
  1217. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1218. WBM_IDLE_LINK, 0);
  1219. }
  1220. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1221. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1222. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1223. soc->wbm_idle_scatter_buf_size,
  1224. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1225. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1226. }
  1227. }
  1228. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1229. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1230. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1231. soc->link_desc_banks[i].size,
  1232. soc->link_desc_banks[i].base_vaddr_unaligned,
  1233. soc->link_desc_banks[i].base_paddr_unaligned,
  1234. 0);
  1235. }
  1236. }
  1237. return QDF_STATUS_E_FAILURE;
  1238. }
  1239. #ifdef notused
  1240. /*
  1241. * Free link descriptor pool that was setup HW
  1242. */
  1243. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1244. {
  1245. int i;
  1246. if (soc->wbm_idle_link_ring.hal_srng) {
  1247. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1248. WBM_IDLE_LINK, 0);
  1249. }
  1250. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1251. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1252. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1253. soc->wbm_idle_scatter_buf_size,
  1254. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1255. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1256. }
  1257. }
  1258. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1259. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1260. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1261. soc->link_desc_banks[i].size,
  1262. soc->link_desc_banks[i].base_vaddr_unaligned,
  1263. soc->link_desc_banks[i].base_paddr_unaligned,
  1264. 0);
  1265. }
  1266. }
  1267. }
  1268. #endif /* notused */
  1269. /* TODO: Following should be configurable */
  1270. #define WBM_RELEASE_RING_SIZE 64
  1271. #define TCL_CMD_RING_SIZE 32
  1272. #define TCL_STATUS_RING_SIZE 32
  1273. #if defined(QCA_WIFI_QCA6290)
  1274. #define REO_DST_RING_SIZE 1024
  1275. #else
  1276. #define REO_DST_RING_SIZE 2048
  1277. #endif
  1278. #define REO_REINJECT_RING_SIZE 32
  1279. #define RX_RELEASE_RING_SIZE 1024
  1280. #define REO_EXCEPTION_RING_SIZE 128
  1281. #define REO_CMD_RING_SIZE 32
  1282. #define REO_STATUS_RING_SIZE 32
  1283. #define RXDMA_BUF_RING_SIZE 1024
  1284. #define RXDMA_REFILL_RING_SIZE 2048
  1285. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  1286. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  1287. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1288. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  1289. #define RXDMA_ERR_DST_RING_SIZE 1024
  1290. /*
  1291. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1292. * @soc: Datapath SOC handle
  1293. *
  1294. * This is a timer function used to age out stale WDS nodes from
  1295. * AST table
  1296. */
  1297. #ifdef FEATURE_WDS
  1298. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1299. {
  1300. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1301. struct dp_pdev *pdev;
  1302. struct dp_vdev *vdev;
  1303. struct dp_peer *peer;
  1304. struct dp_ast_entry *ase, *temp_ase;
  1305. int i;
  1306. qdf_spin_lock_bh(&soc->ast_lock);
  1307. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1308. pdev = soc->pdev_list[i];
  1309. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1310. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1311. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1312. /*
  1313. * Do not expire static ast entries
  1314. */
  1315. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1316. continue;
  1317. if (ase->is_active) {
  1318. ase->is_active = FALSE;
  1319. continue;
  1320. }
  1321. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1322. pdev->osif_pdev,
  1323. ase->mac_addr.raw);
  1324. dp_peer_del_ast(soc, ase);
  1325. }
  1326. }
  1327. }
  1328. }
  1329. qdf_spin_unlock_bh(&soc->ast_lock);
  1330. if (qdf_atomic_read(&soc->cmn_init_done))
  1331. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1332. }
  1333. /*
  1334. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1335. * @soc: Datapath SOC handle
  1336. *
  1337. * Return: None
  1338. */
  1339. static void dp_soc_wds_attach(struct dp_soc *soc)
  1340. {
  1341. qdf_spinlock_create(&soc->ast_lock);
  1342. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1343. dp_wds_aging_timer_fn, (void *)soc,
  1344. QDF_TIMER_TYPE_WAKE_APPS);
  1345. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1346. }
  1347. /*
  1348. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1349. * @txrx_soc: DP SOC handle
  1350. *
  1351. * Return: None
  1352. */
  1353. static void dp_soc_wds_detach(struct dp_soc *soc)
  1354. {
  1355. qdf_timer_stop(&soc->wds_aging_timer);
  1356. qdf_timer_free(&soc->wds_aging_timer);
  1357. qdf_spinlock_destroy(&soc->ast_lock);
  1358. }
  1359. #else
  1360. static void dp_soc_wds_attach(struct dp_soc *soc)
  1361. {
  1362. }
  1363. static void dp_soc_wds_detach(struct dp_soc *soc)
  1364. {
  1365. }
  1366. #endif
  1367. /*
  1368. * dp_soc_reset_ring_map() - Reset cpu ring map
  1369. * @soc: Datapath soc handler
  1370. *
  1371. * This api resets the default cpu ring map
  1372. */
  1373. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1374. {
  1375. uint8_t i;
  1376. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1377. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1378. if (nss_config == 1) {
  1379. /*
  1380. * Setting Tx ring map for one nss offloaded radio
  1381. */
  1382. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1383. } else if (nss_config == 2) {
  1384. /*
  1385. * Setting Tx ring for two nss offloaded radios
  1386. */
  1387. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1388. } else {
  1389. /*
  1390. * Setting Tx ring map for all nss offloaded radios
  1391. */
  1392. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1393. }
  1394. }
  1395. }
  1396. /*
  1397. * dp_soc_cmn_setup() - Common SoC level initializion
  1398. * @soc: Datapath SOC handle
  1399. *
  1400. * This is an internal function used to setup common SOC data structures,
  1401. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1402. */
  1403. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1404. {
  1405. int i;
  1406. struct hal_reo_params reo_params;
  1407. int tx_ring_size;
  1408. int tx_comp_ring_size;
  1409. if (qdf_atomic_read(&soc->cmn_init_done))
  1410. return 0;
  1411. if (dp_peer_find_attach(soc))
  1412. goto fail0;
  1413. if (dp_hw_link_desc_pool_setup(soc))
  1414. goto fail1;
  1415. /* Setup SRNG rings */
  1416. /* Common rings */
  1417. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1418. WBM_RELEASE_RING_SIZE)) {
  1419. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1420. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1421. goto fail1;
  1422. }
  1423. soc->num_tcl_data_rings = 0;
  1424. /* Tx data rings */
  1425. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1426. soc->num_tcl_data_rings =
  1427. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1428. tx_comp_ring_size =
  1429. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1430. tx_ring_size =
  1431. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1432. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1433. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1434. TCL_DATA, i, 0, tx_ring_size)) {
  1435. QDF_TRACE(QDF_MODULE_ID_DP,
  1436. QDF_TRACE_LEVEL_ERROR,
  1437. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1438. goto fail1;
  1439. }
  1440. /*
  1441. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1442. * count
  1443. */
  1444. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1445. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1446. QDF_TRACE(QDF_MODULE_ID_DP,
  1447. QDF_TRACE_LEVEL_ERROR,
  1448. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1449. goto fail1;
  1450. }
  1451. }
  1452. } else {
  1453. /* This will be incremented during per pdev ring setup */
  1454. soc->num_tcl_data_rings = 0;
  1455. }
  1456. if (dp_tx_soc_attach(soc)) {
  1457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1458. FL("dp_tx_soc_attach failed"));
  1459. goto fail1;
  1460. }
  1461. /* TCL command and status rings */
  1462. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1463. TCL_CMD_RING_SIZE)) {
  1464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1465. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1466. goto fail1;
  1467. }
  1468. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1469. TCL_STATUS_RING_SIZE)) {
  1470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1471. FL("dp_srng_setup failed for tcl_status_ring"));
  1472. goto fail1;
  1473. }
  1474. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1475. * descriptors
  1476. */
  1477. /* Rx data rings */
  1478. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1479. soc->num_reo_dest_rings =
  1480. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1481. QDF_TRACE(QDF_MODULE_ID_DP,
  1482. QDF_TRACE_LEVEL_ERROR,
  1483. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1484. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1485. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1486. i, 0, REO_DST_RING_SIZE)) {
  1487. QDF_TRACE(QDF_MODULE_ID_DP,
  1488. QDF_TRACE_LEVEL_ERROR,
  1489. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1490. goto fail1;
  1491. }
  1492. }
  1493. } else {
  1494. /* This will be incremented during per pdev ring setup */
  1495. soc->num_reo_dest_rings = 0;
  1496. }
  1497. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1498. /* REO reinjection ring */
  1499. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1500. REO_REINJECT_RING_SIZE)) {
  1501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1502. FL("dp_srng_setup failed for reo_reinject_ring"));
  1503. goto fail1;
  1504. }
  1505. /* Rx release ring */
  1506. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1507. RX_RELEASE_RING_SIZE)) {
  1508. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1509. FL("dp_srng_setup failed for rx_rel_ring"));
  1510. goto fail1;
  1511. }
  1512. /* Rx exception ring */
  1513. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1514. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1516. FL("dp_srng_setup failed for reo_exception_ring"));
  1517. goto fail1;
  1518. }
  1519. /* REO command and status rings */
  1520. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1521. REO_CMD_RING_SIZE)) {
  1522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1523. FL("dp_srng_setup failed for reo_cmd_ring"));
  1524. goto fail1;
  1525. }
  1526. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1527. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1528. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1529. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1530. REO_STATUS_RING_SIZE)) {
  1531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1532. FL("dp_srng_setup failed for reo_status_ring"));
  1533. goto fail1;
  1534. }
  1535. dp_soc_wds_attach(soc);
  1536. /* Reset the cpu ring map if radio is NSS offloaded */
  1537. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1538. dp_soc_reset_cpu_ring_map(soc);
  1539. }
  1540. /* Setup HW REO */
  1541. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1542. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx))
  1543. reo_params.rx_hash_enabled = true;
  1544. hal_reo_setup(soc->hal_soc, &reo_params);
  1545. qdf_atomic_set(&soc->cmn_init_done, 1);
  1546. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1547. return 0;
  1548. fail1:
  1549. /*
  1550. * Cleanup will be done as part of soc_detach, which will
  1551. * be called on pdev attach failure
  1552. */
  1553. fail0:
  1554. return QDF_STATUS_E_FAILURE;
  1555. }
  1556. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1557. static void dp_lro_hash_setup(struct dp_soc *soc)
  1558. {
  1559. struct cdp_lro_hash_config lro_hash;
  1560. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1561. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1562. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1563. FL("LRO disabled RX hash disabled"));
  1564. return;
  1565. }
  1566. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1567. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1568. lro_hash.lro_enable = 1;
  1569. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1570. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1571. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1572. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1573. }
  1574. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1575. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1576. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1577. LRO_IPV4_SEED_ARR_SZ));
  1578. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1579. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1580. LRO_IPV6_SEED_ARR_SZ));
  1581. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1582. "lro_hash: lro_enable: 0x%x"
  1583. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1584. lro_hash.lro_enable, lro_hash.tcp_flag,
  1585. lro_hash.tcp_flag_mask);
  1586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1587. FL("lro_hash: toeplitz_hash_ipv4:"));
  1588. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1589. QDF_TRACE_LEVEL_ERROR,
  1590. (void *)lro_hash.toeplitz_hash_ipv4,
  1591. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1592. LRO_IPV4_SEED_ARR_SZ));
  1593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1594. FL("lro_hash: toeplitz_hash_ipv6:"));
  1595. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1596. QDF_TRACE_LEVEL_ERROR,
  1597. (void *)lro_hash.toeplitz_hash_ipv6,
  1598. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1599. LRO_IPV6_SEED_ARR_SZ));
  1600. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1601. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1602. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1603. (soc->osif_soc, &lro_hash);
  1604. }
  1605. /*
  1606. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1607. * @soc: data path SoC handle
  1608. * @pdev: Physical device handle
  1609. *
  1610. * Return: 0 - success, > 0 - failure
  1611. */
  1612. #ifdef QCA_HOST2FW_RXBUF_RING
  1613. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1614. struct dp_pdev *pdev)
  1615. {
  1616. int max_mac_rings =
  1617. wlan_cfg_get_num_mac_rings
  1618. (pdev->wlan_cfg_ctx);
  1619. int i;
  1620. for (i = 0; i < max_mac_rings; i++) {
  1621. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1622. "%s: pdev_id %d mac_id %d\n",
  1623. __func__, pdev->pdev_id, i);
  1624. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1625. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1626. QDF_TRACE(QDF_MODULE_ID_DP,
  1627. QDF_TRACE_LEVEL_ERROR,
  1628. FL("failed rx mac ring setup"));
  1629. return QDF_STATUS_E_FAILURE;
  1630. }
  1631. }
  1632. return QDF_STATUS_SUCCESS;
  1633. }
  1634. #else
  1635. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1636. struct dp_pdev *pdev)
  1637. {
  1638. return QDF_STATUS_SUCCESS;
  1639. }
  1640. #endif
  1641. /**
  1642. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1643. * @pdev - DP_PDEV handle
  1644. *
  1645. * Return: void
  1646. */
  1647. static inline void
  1648. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1649. {
  1650. uint8_t map_id;
  1651. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1652. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1653. sizeof(default_dscp_tid_map));
  1654. }
  1655. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1656. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1657. pdev->dscp_tid_map[map_id],
  1658. map_id);
  1659. }
  1660. }
  1661. /*
  1662. * dp_reset_intr_mask() - reset interrupt mask
  1663. * @dp_soc - DP Soc handle
  1664. * @dp_pdev - DP pdev handle
  1665. *
  1666. * Return: Return void
  1667. */
  1668. static inline
  1669. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1670. {
  1671. /*
  1672. * We will set the interrupt mask to zero for NSS offloaded radio
  1673. */
  1674. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1675. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1676. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1677. }
  1678. /*
  1679. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1680. * @soc: data path SoC handle
  1681. *
  1682. * Return: none
  1683. */
  1684. #ifdef IPA_OFFLOAD
  1685. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1686. struct dp_pdev *pdev)
  1687. {
  1688. void *hal_srng;
  1689. struct hal_srng_params srng_params;
  1690. qdf_dma_addr_t hp_addr, tp_addr;
  1691. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1692. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1693. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1694. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1695. srng_params.ring_base_paddr;
  1696. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1697. srng_params.ring_base_vaddr;
  1698. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1699. srng_params.num_entries * srng_params.entry_size;
  1700. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1701. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1702. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1703. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1704. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1705. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1706. srng_params.ring_base_paddr;
  1707. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1708. srng_params.ring_base_vaddr;
  1709. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1710. srng_params.num_entries * srng_params.entry_size;
  1711. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1712. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1713. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1714. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1715. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1716. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1717. srng_params.ring_base_paddr;
  1718. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1719. srng_params.ring_base_vaddr;
  1720. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1721. srng_params.num_entries * srng_params.entry_size;
  1722. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1723. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1724. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1725. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1726. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1727. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1728. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1729. __func__);
  1730. return -EFAULT;
  1731. }
  1732. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1733. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1734. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1735. srng_params.ring_base_paddr;
  1736. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1737. srng_params.ring_base_vaddr;
  1738. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1739. srng_params.num_entries * srng_params.entry_size;
  1740. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1741. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1742. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1743. "%s: ring_base_paddr:%p, ring_base_vaddr:%p"
  1744. "_entries:%d, hp_addr:%p\n",
  1745. __func__,
  1746. (void *)srng_params.ring_base_paddr,
  1747. (void *)srng_params.ring_base_vaddr,
  1748. srng_params.num_entries,
  1749. (void *)hp_addr);
  1750. return 0;
  1751. }
  1752. #else
  1753. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1754. struct dp_pdev *pdev)
  1755. {
  1756. return 0;
  1757. }
  1758. #endif
  1759. /*
  1760. * dp_pdev_attach_wifi3() - attach txrx pdev
  1761. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1762. * @txrx_soc: Datapath SOC handle
  1763. * @htc_handle: HTC handle for host-target interface
  1764. * @qdf_osdev: QDF OS device
  1765. * @pdev_id: PDEV ID
  1766. *
  1767. * Return: DP PDEV handle on success, NULL on failure
  1768. */
  1769. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1770. struct cdp_cfg *ctrl_pdev,
  1771. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1772. {
  1773. int tx_ring_size;
  1774. int tx_comp_ring_size;
  1775. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1776. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1777. if (!pdev) {
  1778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1779. FL("DP PDEV memory allocation failed"));
  1780. goto fail0;
  1781. }
  1782. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1783. if (!pdev->wlan_cfg_ctx) {
  1784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1785. FL("pdev cfg_attach failed"));
  1786. qdf_mem_free(pdev);
  1787. goto fail0;
  1788. }
  1789. /*
  1790. * set nss pdev config based on soc config
  1791. */
  1792. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1793. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1794. pdev->soc = soc;
  1795. pdev->osif_pdev = ctrl_pdev;
  1796. pdev->pdev_id = pdev_id;
  1797. soc->pdev_list[pdev_id] = pdev;
  1798. soc->pdev_count++;
  1799. TAILQ_INIT(&pdev->vdev_list);
  1800. pdev->vdev_count = 0;
  1801. qdf_spinlock_create(&pdev->tx_mutex);
  1802. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1803. TAILQ_INIT(&pdev->neighbour_peers_list);
  1804. if (dp_soc_cmn_setup(soc)) {
  1805. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1806. FL("dp_soc_cmn_setup failed"));
  1807. goto fail1;
  1808. }
  1809. /* Setup per PDEV TCL rings if configured */
  1810. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1811. tx_ring_size =
  1812. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1813. tx_comp_ring_size =
  1814. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1815. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1816. pdev_id, pdev_id, tx_ring_size)) {
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1818. FL("dp_srng_setup failed for tcl_data_ring"));
  1819. goto fail1;
  1820. }
  1821. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1822. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1823. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1824. FL("dp_srng_setup failed for tx_comp_ring"));
  1825. goto fail1;
  1826. }
  1827. soc->num_tcl_data_rings++;
  1828. }
  1829. /* Tx specific init */
  1830. if (dp_tx_pdev_attach(pdev)) {
  1831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1832. FL("dp_tx_pdev_attach failed"));
  1833. goto fail1;
  1834. }
  1835. /* Setup per PDEV REO rings if configured */
  1836. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1837. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1838. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1839. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1840. FL("dp_srng_setup failed for reo_dest_ringn"));
  1841. goto fail1;
  1842. }
  1843. soc->num_reo_dest_rings++;
  1844. }
  1845. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1846. RXDMA_REFILL_RING_SIZE)) {
  1847. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1848. FL("dp_srng_setup failed rx refill ring"));
  1849. goto fail1;
  1850. }
  1851. if (dp_rxdma_ring_setup(soc, pdev)) {
  1852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1853. FL("RXDMA ring config failed"));
  1854. goto fail1;
  1855. }
  1856. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1857. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1859. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1860. goto fail1;
  1861. }
  1862. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1863. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1864. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1865. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1866. goto fail1;
  1867. }
  1868. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1869. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1870. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1871. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1872. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1873. goto fail1;
  1874. }
  1875. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1876. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1877. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1878. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1879. goto fail1;
  1880. }
  1881. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  1882. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1883. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1884. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1885. goto fail1;
  1886. }
  1887. if (dp_ipa_ring_resource_setup(soc, pdev))
  1888. goto fail1;
  1889. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1890. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1891. "%s: dp_ipa_uc_attach failed\n", __func__);
  1892. goto fail1;
  1893. }
  1894. /* Rx specific init */
  1895. if (dp_rx_pdev_attach(pdev)) {
  1896. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1897. FL("dp_rx_pdev_attach failed "));
  1898. goto fail0;
  1899. }
  1900. DP_STATS_INIT(pdev);
  1901. #ifndef CONFIG_WIN
  1902. /* MCL */
  1903. dp_local_peer_id_pool_init(pdev);
  1904. #endif
  1905. dp_dscp_tid_map_setup(pdev);
  1906. /* Rx monitor mode specific init */
  1907. if (dp_rx_pdev_mon_attach(pdev)) {
  1908. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1909. "dp_rx_pdev_attach failed\n");
  1910. goto fail1;
  1911. }
  1912. if (dp_wdi_event_attach(pdev)) {
  1913. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1914. "dp_wdi_evet_attach failed\n");
  1915. goto fail1;
  1916. }
  1917. /* set the reo destination during initialization */
  1918. pdev->reo_dest = pdev->pdev_id + 1;
  1919. /*
  1920. * reset the interrupt mask for offloaded radio
  1921. */
  1922. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  1923. dp_soc_reset_intr_mask(soc, pdev);
  1924. }
  1925. return (struct cdp_pdev *)pdev;
  1926. fail1:
  1927. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1928. fail0:
  1929. return NULL;
  1930. }
  1931. /*
  1932. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1933. * @soc: data path SoC handle
  1934. * @pdev: Physical device handle
  1935. *
  1936. * Return: void
  1937. */
  1938. #ifdef QCA_HOST2FW_RXBUF_RING
  1939. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1940. struct dp_pdev *pdev)
  1941. {
  1942. int max_mac_rings =
  1943. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1944. int i;
  1945. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1946. max_mac_rings : MAX_RX_MAC_RINGS;
  1947. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1948. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1949. RXDMA_BUF, 1);
  1950. }
  1951. #else
  1952. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1953. struct dp_pdev *pdev)
  1954. {
  1955. }
  1956. #endif
  1957. /*
  1958. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1959. * @pdev: device object
  1960. *
  1961. * Return: void
  1962. */
  1963. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1964. {
  1965. struct dp_neighbour_peer *peer = NULL;
  1966. struct dp_neighbour_peer *temp_peer = NULL;
  1967. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1968. neighbour_peer_list_elem, temp_peer) {
  1969. /* delete this peer from the list */
  1970. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1971. peer, neighbour_peer_list_elem);
  1972. qdf_mem_free(peer);
  1973. }
  1974. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  1975. }
  1976. /*
  1977. * dp_pdev_detach_wifi3() - detach txrx pdev
  1978. * @txrx_pdev: Datapath PDEV handle
  1979. * @force: Force detach
  1980. *
  1981. */
  1982. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  1983. {
  1984. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1985. struct dp_soc *soc = pdev->soc;
  1986. dp_wdi_event_detach(pdev);
  1987. dp_tx_pdev_detach(pdev);
  1988. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1989. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  1990. TCL_DATA, pdev->pdev_id);
  1991. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  1992. WBM2SW_RELEASE, pdev->pdev_id);
  1993. }
  1994. dp_rx_pdev_detach(pdev);
  1995. dp_rx_pdev_mon_detach(pdev);
  1996. dp_neighbour_peers_detach(pdev);
  1997. qdf_spinlock_destroy(&pdev->tx_mutex);
  1998. dp_ipa_uc_detach(soc, pdev);
  1999. /* Cleanup per PDEV REO rings if configured */
  2000. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2001. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2002. REO_DST, pdev->pdev_id);
  2003. }
  2004. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2005. dp_rxdma_ring_cleanup(soc, pdev);
  2006. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2007. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2008. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2009. RXDMA_MONITOR_STATUS, 0);
  2010. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2011. RXDMA_MONITOR_DESC, 0);
  2012. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2013. soc->pdev_list[pdev->pdev_id] = NULL;
  2014. soc->pdev_count--;
  2015. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2016. qdf_mem_free(pdev);
  2017. }
  2018. /*
  2019. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2020. * @soc: DP SOC handle
  2021. */
  2022. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2023. {
  2024. struct reo_desc_list_node *desc;
  2025. struct dp_rx_tid *rx_tid;
  2026. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2027. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2028. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2029. rx_tid = &desc->rx_tid;
  2030. qdf_mem_unmap_nbytes_single(soc->osdev,
  2031. rx_tid->hw_qdesc_paddr,
  2032. QDF_DMA_BIDIRECTIONAL,
  2033. rx_tid->hw_qdesc_alloc_size);
  2034. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2035. qdf_mem_free(desc);
  2036. }
  2037. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2038. qdf_list_destroy(&soc->reo_desc_freelist);
  2039. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2040. }
  2041. /*
  2042. * dp_soc_detach_wifi3() - Detach txrx SOC
  2043. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2044. */
  2045. static void dp_soc_detach_wifi3(void *txrx_soc)
  2046. {
  2047. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2048. int i;
  2049. qdf_atomic_set(&soc->cmn_init_done, 0);
  2050. qdf_flush_work(0, &soc->htt_stats.work);
  2051. qdf_disable_work(0, &soc->htt_stats.work);
  2052. /* Free pending htt stats messages */
  2053. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2054. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2055. if (soc->pdev_list[i])
  2056. dp_pdev_detach_wifi3(
  2057. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2058. }
  2059. dp_peer_find_detach(soc);
  2060. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2061. * SW descriptors
  2062. */
  2063. /* Free the ring memories */
  2064. /* Common rings */
  2065. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2066. dp_tx_soc_detach(soc);
  2067. /* Tx data rings */
  2068. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2069. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2070. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2071. TCL_DATA, i);
  2072. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2073. WBM2SW_RELEASE, i);
  2074. }
  2075. }
  2076. /* TCL command and status rings */
  2077. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2078. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2079. /* Rx data rings */
  2080. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2081. soc->num_reo_dest_rings =
  2082. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2083. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2084. /* TODO: Get number of rings and ring sizes
  2085. * from wlan_cfg
  2086. */
  2087. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2088. REO_DST, i);
  2089. }
  2090. }
  2091. /* REO reinjection ring */
  2092. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2093. /* Rx release ring */
  2094. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2095. /* Rx exception ring */
  2096. /* TODO: Better to store ring_type and ring_num in
  2097. * dp_srng during setup
  2098. */
  2099. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2100. /* REO command and status rings */
  2101. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2102. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2103. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2104. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2105. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2106. htt_soc_detach(soc->htt_handle);
  2107. dp_reo_cmdlist_destroy(soc);
  2108. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2109. dp_reo_desc_freelist_destroy(soc);
  2110. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2111. dp_soc_wds_detach(soc);
  2112. qdf_mem_free(soc);
  2113. }
  2114. /*
  2115. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2116. * @soc: data path SoC handle
  2117. * @pdev: physical device handle
  2118. *
  2119. * Return: void
  2120. */
  2121. #ifdef IPA_OFFLOAD
  2122. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2123. struct dp_pdev *pdev)
  2124. {
  2125. htt_srng_setup(soc->htt_handle, 0,
  2126. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2127. }
  2128. #else
  2129. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2130. struct dp_pdev *pdev)
  2131. {
  2132. }
  2133. #endif
  2134. /*
  2135. * dp_rxdma_ring_config() - configure the RX DMA rings
  2136. *
  2137. * This function is used to configure the MAC rings.
  2138. * On MCL host provides buffers in Host2FW ring
  2139. * FW refills (copies) buffers to the ring and updates
  2140. * ring_idx in register
  2141. *
  2142. * @soc: data path SoC handle
  2143. *
  2144. * Return: void
  2145. */
  2146. #ifdef QCA_HOST2FW_RXBUF_RING
  2147. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2148. {
  2149. int i;
  2150. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2151. struct dp_pdev *pdev = soc->pdev_list[i];
  2152. if (pdev) {
  2153. int mac_id = 0;
  2154. int j;
  2155. bool dbs_enable = 0;
  2156. int max_mac_rings =
  2157. wlan_cfg_get_num_mac_rings
  2158. (pdev->wlan_cfg_ctx);
  2159. htt_srng_setup(soc->htt_handle, 0,
  2160. pdev->rx_refill_buf_ring.hal_srng,
  2161. RXDMA_BUF);
  2162. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2163. if (soc->cdp_soc.ol_ops->
  2164. is_hw_dbs_2x2_capable) {
  2165. dbs_enable = soc->cdp_soc.ol_ops->
  2166. is_hw_dbs_2x2_capable(soc->psoc);
  2167. }
  2168. if (dbs_enable) {
  2169. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2170. QDF_TRACE_LEVEL_ERROR,
  2171. FL("DBS enabled max_mac_rings %d\n"),
  2172. max_mac_rings);
  2173. } else {
  2174. max_mac_rings = 1;
  2175. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2176. QDF_TRACE_LEVEL_ERROR,
  2177. FL("DBS disabled, max_mac_rings %d\n"),
  2178. max_mac_rings);
  2179. }
  2180. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2181. FL("pdev_id %d max_mac_rings %d\n"),
  2182. pdev->pdev_id, max_mac_rings);
  2183. for (j = 0; j < max_mac_rings; j++) {
  2184. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2185. QDF_TRACE_LEVEL_ERROR,
  2186. FL("mac_id %d\n"), mac_id);
  2187. htt_srng_setup(soc->htt_handle, mac_id,
  2188. pdev->rx_mac_buf_ring[j]
  2189. .hal_srng,
  2190. RXDMA_BUF);
  2191. mac_id++;
  2192. }
  2193. /* Configure monitor mode rings */
  2194. htt_srng_setup(soc->htt_handle, i,
  2195. pdev->rxdma_mon_buf_ring.hal_srng,
  2196. RXDMA_MONITOR_BUF);
  2197. htt_srng_setup(soc->htt_handle, i,
  2198. pdev->rxdma_mon_dst_ring.hal_srng,
  2199. RXDMA_MONITOR_DST);
  2200. htt_srng_setup(soc->htt_handle, i,
  2201. pdev->rxdma_mon_status_ring.hal_srng,
  2202. RXDMA_MONITOR_STATUS);
  2203. htt_srng_setup(soc->htt_handle, i,
  2204. pdev->rxdma_mon_desc_ring.hal_srng,
  2205. RXDMA_MONITOR_DESC);
  2206. htt_srng_setup(soc->htt_handle, i,
  2207. pdev->rxdma_err_dst_ring.hal_srng,
  2208. RXDMA_DST);
  2209. }
  2210. }
  2211. }
  2212. #else
  2213. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2214. {
  2215. int i;
  2216. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2217. struct dp_pdev *pdev = soc->pdev_list[i];
  2218. if (pdev) {
  2219. htt_srng_setup(soc->htt_handle, i,
  2220. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2221. htt_srng_setup(soc->htt_handle, i,
  2222. pdev->rxdma_mon_buf_ring.hal_srng,
  2223. RXDMA_MONITOR_BUF);
  2224. htt_srng_setup(soc->htt_handle, i,
  2225. pdev->rxdma_mon_dst_ring.hal_srng,
  2226. RXDMA_MONITOR_DST);
  2227. htt_srng_setup(soc->htt_handle, i,
  2228. pdev->rxdma_mon_status_ring.hal_srng,
  2229. RXDMA_MONITOR_STATUS);
  2230. htt_srng_setup(soc->htt_handle, i,
  2231. pdev->rxdma_mon_desc_ring.hal_srng,
  2232. RXDMA_MONITOR_DESC);
  2233. htt_srng_setup(soc->htt_handle, i,
  2234. pdev->rxdma_err_dst_ring.hal_srng,
  2235. RXDMA_DST);
  2236. }
  2237. }
  2238. }
  2239. #endif
  2240. /*
  2241. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2242. * @txrx_soc: Datapath SOC handle
  2243. */
  2244. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2245. {
  2246. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2247. htt_soc_attach_target(soc->htt_handle);
  2248. dp_rxdma_ring_config(soc);
  2249. DP_STATS_INIT(soc);
  2250. /* initialize work queue for stats processing */
  2251. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2252. return 0;
  2253. }
  2254. /*
  2255. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2256. * @txrx_soc: Datapath SOC handle
  2257. */
  2258. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2259. {
  2260. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2261. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2262. }
  2263. /*
  2264. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2265. * @txrx_soc: Datapath SOC handle
  2266. * @nss_cfg: nss config
  2267. */
  2268. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2269. {
  2270. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2271. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2273. FL("nss-wifi<0> nss config is enabled"));
  2274. }
  2275. /*
  2276. * dp_vdev_attach_wifi3() - attach txrx vdev
  2277. * @txrx_pdev: Datapath PDEV handle
  2278. * @vdev_mac_addr: MAC address of the virtual interface
  2279. * @vdev_id: VDEV Id
  2280. * @wlan_op_mode: VDEV operating mode
  2281. *
  2282. * Return: DP VDEV handle on success, NULL on failure
  2283. */
  2284. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2285. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2286. {
  2287. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2288. struct dp_soc *soc = pdev->soc;
  2289. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2290. int tx_ring_size;
  2291. if (!vdev) {
  2292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2293. FL("DP VDEV memory allocation failed"));
  2294. goto fail0;
  2295. }
  2296. vdev->pdev = pdev;
  2297. vdev->vdev_id = vdev_id;
  2298. vdev->opmode = op_mode;
  2299. vdev->osdev = soc->osdev;
  2300. vdev->osif_rx = NULL;
  2301. vdev->osif_rsim_rx_decap = NULL;
  2302. vdev->osif_get_key = NULL;
  2303. vdev->osif_rx_mon = NULL;
  2304. vdev->osif_tx_free_ext = NULL;
  2305. vdev->osif_vdev = NULL;
  2306. vdev->delete.pending = 0;
  2307. vdev->safemode = 0;
  2308. vdev->drop_unenc = 1;
  2309. #ifdef notyet
  2310. vdev->filters_num = 0;
  2311. #endif
  2312. qdf_mem_copy(
  2313. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2314. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2315. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2316. vdev->dscp_tid_map_id = 0;
  2317. vdev->mcast_enhancement_en = 0;
  2318. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2319. /* TODO: Initialize default HTT meta data that will be used in
  2320. * TCL descriptors for packets transmitted from this VDEV
  2321. */
  2322. TAILQ_INIT(&vdev->peer_list);
  2323. /* add this vdev into the pdev's list */
  2324. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2325. pdev->vdev_count++;
  2326. dp_tx_vdev_attach(vdev);
  2327. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2328. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2329. goto fail1;
  2330. if ((soc->intr_mode == DP_INTR_POLL) &&
  2331. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2332. if (pdev->vdev_count == 1)
  2333. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2334. }
  2335. dp_lro_hash_setup(soc);
  2336. /* LRO */
  2337. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2338. wlan_op_mode_sta == vdev->opmode)
  2339. vdev->lro_enable = true;
  2340. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2341. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2343. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  2344. DP_STATS_INIT(vdev);
  2345. return (struct cdp_vdev *)vdev;
  2346. fail1:
  2347. dp_tx_vdev_detach(vdev);
  2348. qdf_mem_free(vdev);
  2349. fail0:
  2350. return NULL;
  2351. }
  2352. /**
  2353. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2354. * @vdev: Datapath VDEV handle
  2355. * @osif_vdev: OSIF vdev handle
  2356. * @txrx_ops: Tx and Rx operations
  2357. *
  2358. * Return: DP VDEV handle on success, NULL on failure
  2359. */
  2360. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2361. void *osif_vdev,
  2362. struct ol_txrx_ops *txrx_ops)
  2363. {
  2364. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2365. vdev->osif_vdev = osif_vdev;
  2366. vdev->osif_rx = txrx_ops->rx.rx;
  2367. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2368. vdev->osif_get_key = txrx_ops->get_key;
  2369. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2370. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2371. #ifdef notyet
  2372. #if ATH_SUPPORT_WAPI
  2373. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2374. #endif
  2375. #endif
  2376. #ifdef UMAC_SUPPORT_PROXY_ARP
  2377. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2378. #endif
  2379. vdev->me_convert = txrx_ops->me_convert;
  2380. /* TODO: Enable the following once Tx code is integrated */
  2381. txrx_ops->tx.tx = dp_tx_send;
  2382. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2383. "DP Vdev Register success");
  2384. }
  2385. /*
  2386. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2387. * @txrx_vdev: Datapath VDEV handle
  2388. * @callback: Callback OL_IF on completion of detach
  2389. * @cb_context: Callback context
  2390. *
  2391. */
  2392. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2393. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2394. {
  2395. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2396. struct dp_pdev *pdev = vdev->pdev;
  2397. struct dp_soc *soc = pdev->soc;
  2398. /* preconditions */
  2399. qdf_assert(vdev);
  2400. /* remove the vdev from its parent pdev's list */
  2401. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2402. /*
  2403. * Use peer_ref_mutex while accessing peer_list, in case
  2404. * a peer is in the process of being removed from the list.
  2405. */
  2406. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2407. /* check that the vdev has no peers allocated */
  2408. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2409. /* debug print - will be removed later */
  2410. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2411. FL("not deleting vdev object %p (%pM)"
  2412. "until deletion finishes for all its peers"),
  2413. vdev, vdev->mac_addr.raw);
  2414. /* indicate that the vdev needs to be deleted */
  2415. vdev->delete.pending = 1;
  2416. vdev->delete.callback = callback;
  2417. vdev->delete.context = cb_context;
  2418. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2419. return;
  2420. }
  2421. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2422. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2423. vdev->vdev_id);
  2424. dp_tx_vdev_detach(vdev);
  2425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2426. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  2427. qdf_mem_free(vdev);
  2428. if (callback)
  2429. callback(cb_context);
  2430. }
  2431. /*
  2432. * dp_peer_create_wifi3() - attach txrx peer
  2433. * @txrx_vdev: Datapath VDEV handle
  2434. * @peer_mac_addr: Peer MAC address
  2435. *
  2436. * Return: DP peeer handle on success, NULL on failure
  2437. */
  2438. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2439. uint8_t *peer_mac_addr)
  2440. {
  2441. struct dp_peer *peer;
  2442. int i;
  2443. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2444. struct dp_pdev *pdev;
  2445. struct dp_soc *soc;
  2446. /* preconditions */
  2447. qdf_assert(vdev);
  2448. qdf_assert(peer_mac_addr);
  2449. pdev = vdev->pdev;
  2450. soc = pdev->soc;
  2451. #ifdef notyet
  2452. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2453. soc->mempool_ol_ath_peer);
  2454. #else
  2455. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2456. #endif
  2457. if (!peer)
  2458. return NULL; /* failure */
  2459. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2460. TAILQ_INIT(&peer->ast_entry_list);
  2461. /* store provided params */
  2462. peer->vdev = vdev;
  2463. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2464. qdf_spinlock_create(&peer->peer_info_lock);
  2465. qdf_mem_copy(
  2466. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2467. /* TODO: See of rx_opt_proc is really required */
  2468. peer->rx_opt_proc = soc->rx_opt_proc;
  2469. /* initialize the peer_id */
  2470. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2471. peer->peer_ids[i] = HTT_INVALID_PEER;
  2472. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2473. qdf_atomic_init(&peer->ref_cnt);
  2474. /* keep one reference for attach */
  2475. qdf_atomic_inc(&peer->ref_cnt);
  2476. /* add this peer into the vdev's list */
  2477. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2478. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2479. /* TODO: See if hash based search is required */
  2480. dp_peer_find_hash_add(soc, peer);
  2481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2482. "vdev %p created peer %p (%pM) ref_cnt: %d",
  2483. vdev, peer, peer->mac_addr.raw,
  2484. qdf_atomic_read(&peer->ref_cnt));
  2485. /*
  2486. * For every peer MAp message search and set if bss_peer
  2487. */
  2488. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2489. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2490. "vdev bss_peer!!!!");
  2491. peer->bss_peer = 1;
  2492. vdev->vap_bss_peer = peer;
  2493. }
  2494. #ifndef CONFIG_WIN
  2495. dp_local_peer_id_alloc(pdev, peer);
  2496. #endif
  2497. DP_STATS_INIT(peer);
  2498. return (void *)peer;
  2499. }
  2500. /*
  2501. * dp_peer_setup_wifi3() - initialize the peer
  2502. * @vdev_hdl: virtual device object
  2503. * @peer: Peer object
  2504. *
  2505. * Return: void
  2506. */
  2507. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2508. {
  2509. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2510. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2511. struct dp_pdev *pdev;
  2512. struct dp_soc *soc;
  2513. bool hash_based = 0;
  2514. enum cdp_host_reo_dest_ring reo_dest;
  2515. /* preconditions */
  2516. qdf_assert(vdev);
  2517. qdf_assert(peer);
  2518. pdev = vdev->pdev;
  2519. soc = pdev->soc;
  2520. dp_peer_rx_init(pdev, peer);
  2521. peer->last_assoc_rcvd = 0;
  2522. peer->last_disassoc_rcvd = 0;
  2523. peer->last_deauth_rcvd = 0;
  2524. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2526. FL("hash based steering %d\n"), hash_based);
  2527. if (!hash_based)
  2528. reo_dest = pdev->reo_dest;
  2529. else
  2530. reo_dest = 1;
  2531. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2532. /* TODO: Check the destination ring number to be passed to FW */
  2533. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2534. pdev->osif_pdev, peer->mac_addr.raw,
  2535. peer->vdev->vdev_id, hash_based, reo_dest);
  2536. }
  2537. return;
  2538. }
  2539. /*
  2540. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2541. * @vdev_handle: virtual device object
  2542. * @htt_pkt_type: type of pkt
  2543. *
  2544. * Return: void
  2545. */
  2546. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2547. enum htt_cmn_pkt_type val)
  2548. {
  2549. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2550. vdev->tx_encap_type = val;
  2551. }
  2552. /*
  2553. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2554. * @vdev_handle: virtual device object
  2555. * @htt_pkt_type: type of pkt
  2556. *
  2557. * Return: void
  2558. */
  2559. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2560. enum htt_cmn_pkt_type val)
  2561. {
  2562. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2563. vdev->rx_decap_type = val;
  2564. }
  2565. /*
  2566. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2567. * @pdev_handle: physical device object
  2568. * @val: reo destination ring index (1 - 4)
  2569. *
  2570. * Return: void
  2571. */
  2572. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2573. enum cdp_host_reo_dest_ring val)
  2574. {
  2575. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2576. if (pdev)
  2577. pdev->reo_dest = val;
  2578. }
  2579. /*
  2580. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2581. * @pdev_handle: physical device object
  2582. *
  2583. * Return: reo destination ring index
  2584. */
  2585. static enum cdp_host_reo_dest_ring
  2586. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2587. {
  2588. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2589. if (pdev)
  2590. return pdev->reo_dest;
  2591. else
  2592. return cdp_host_reo_dest_ring_unknown;
  2593. }
  2594. #ifdef QCA_SUPPORT_SON
  2595. static void dp_son_peer_authorize(struct dp_peer *peer)
  2596. {
  2597. struct dp_soc *soc;
  2598. soc = peer->vdev->pdev->soc;
  2599. peer->peer_bs_inact_flag = 0;
  2600. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2601. return;
  2602. }
  2603. #else
  2604. static void dp_son_peer_authorize(struct dp_peer *peer)
  2605. {
  2606. return;
  2607. }
  2608. #endif
  2609. /*
  2610. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2611. * @pdev_handle: device object
  2612. * @val: value to be set
  2613. *
  2614. * Return: void
  2615. */
  2616. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2617. uint32_t val)
  2618. {
  2619. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2620. /* Enable/Disable smart mesh filtering. This flag will be checked
  2621. * during rx processing to check if packets are from NAC clients.
  2622. */
  2623. pdev->filter_neighbour_peers = val;
  2624. return 0;
  2625. }
  2626. /*
  2627. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2628. * address for smart mesh filtering
  2629. * @pdev_handle: device object
  2630. * @cmd: Add/Del command
  2631. * @macaddr: nac client mac address
  2632. *
  2633. * Return: void
  2634. */
  2635. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2636. uint32_t cmd, uint8_t *macaddr)
  2637. {
  2638. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2639. struct dp_neighbour_peer *peer = NULL;
  2640. if (!macaddr)
  2641. goto fail0;
  2642. /* Store address of NAC (neighbour peer) which will be checked
  2643. * against TA of received packets.
  2644. */
  2645. if (cmd == DP_NAC_PARAM_ADD) {
  2646. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2647. sizeof(*peer));
  2648. if (!peer) {
  2649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2650. FL("DP neighbour peer node memory allocation failed"));
  2651. goto fail0;
  2652. }
  2653. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2654. macaddr, DP_MAC_ADDR_LEN);
  2655. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2656. /* add this neighbour peer into the list */
  2657. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2658. neighbour_peer_list_elem);
  2659. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2660. return 1;
  2661. } else if (cmd == DP_NAC_PARAM_DEL) {
  2662. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2663. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2664. neighbour_peer_list_elem) {
  2665. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2666. macaddr, DP_MAC_ADDR_LEN)) {
  2667. /* delete this peer from the list */
  2668. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2669. peer, neighbour_peer_list_elem);
  2670. qdf_mem_free(peer);
  2671. break;
  2672. }
  2673. }
  2674. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2675. return 1;
  2676. }
  2677. fail0:
  2678. return 0;
  2679. }
  2680. /*
  2681. * dp_get_sec_type() - Get the security type
  2682. * @peer: Datapath peer handle
  2683. * @sec_idx: Security id (mcast, ucast)
  2684. *
  2685. * return sec_type: Security type
  2686. */
  2687. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2688. {
  2689. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2690. return dpeer->security[sec_idx].sec_type;
  2691. }
  2692. /*
  2693. * dp_peer_authorize() - authorize txrx peer
  2694. * @peer_handle: Datapath peer handle
  2695. * @authorize
  2696. *
  2697. */
  2698. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2699. {
  2700. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2701. struct dp_soc *soc;
  2702. if (peer != NULL) {
  2703. soc = peer->vdev->pdev->soc;
  2704. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2705. dp_son_peer_authorize(peer);
  2706. peer->authorize = authorize ? 1 : 0;
  2707. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2708. }
  2709. }
  2710. /*
  2711. * dp_peer_unref_delete() - unref and delete peer
  2712. * @peer_handle: Datapath peer handle
  2713. *
  2714. */
  2715. void dp_peer_unref_delete(void *peer_handle)
  2716. {
  2717. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2718. struct dp_vdev *vdev = peer->vdev;
  2719. struct dp_pdev *pdev = vdev->pdev;
  2720. struct dp_soc *soc = pdev->soc;
  2721. struct dp_peer *tmppeer;
  2722. int found = 0;
  2723. uint16_t peer_id;
  2724. /*
  2725. * Hold the lock all the way from checking if the peer ref count
  2726. * is zero until the peer references are removed from the hash
  2727. * table and vdev list (if the peer ref count is zero).
  2728. * This protects against a new HL tx operation starting to use the
  2729. * peer object just after this function concludes it's done being used.
  2730. * Furthermore, the lock needs to be held while checking whether the
  2731. * vdev's list of peers is empty, to make sure that list is not modified
  2732. * concurrently with the empty check.
  2733. */
  2734. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2735. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2736. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2737. peer, qdf_atomic_read(&peer->ref_cnt));
  2738. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2739. peer_id = peer->peer_ids[0];
  2740. /*
  2741. * Make sure that the reference to the peer in
  2742. * peer object map is removed
  2743. */
  2744. if (peer_id != HTT_INVALID_PEER)
  2745. soc->peer_id_to_obj_map[peer_id] = NULL;
  2746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2747. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2748. /* remove the reference to the peer from the hash table */
  2749. dp_peer_find_hash_remove(soc, peer);
  2750. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2751. if (tmppeer == peer) {
  2752. found = 1;
  2753. break;
  2754. }
  2755. }
  2756. if (found) {
  2757. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2758. peer_list_elem);
  2759. } else {
  2760. /*Ignoring the remove operation as peer not found*/
  2761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2762. "peer %p not found in vdev (%p)->peer_list:%p",
  2763. peer, vdev, &peer->vdev->peer_list);
  2764. }
  2765. /* cleanup the peer data */
  2766. dp_peer_cleanup(vdev, peer);
  2767. /* check whether the parent vdev has no peers left */
  2768. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2769. /*
  2770. * Now that there are no references to the peer, we can
  2771. * release the peer reference lock.
  2772. */
  2773. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2774. /*
  2775. * Check if the parent vdev was waiting for its peers
  2776. * to be deleted, in order for it to be deleted too.
  2777. */
  2778. if (vdev->delete.pending) {
  2779. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2780. vdev->delete.callback;
  2781. void *vdev_delete_context =
  2782. vdev->delete.context;
  2783. QDF_TRACE(QDF_MODULE_ID_DP,
  2784. QDF_TRACE_LEVEL_INFO_HIGH,
  2785. FL("deleting vdev object %p (%pM)"
  2786. " - its last peer is done"),
  2787. vdev, vdev->mac_addr.raw);
  2788. /* all peers are gone, go ahead and delete it */
  2789. qdf_mem_free(vdev);
  2790. if (vdev_delete_cb)
  2791. vdev_delete_cb(vdev_delete_context);
  2792. }
  2793. } else {
  2794. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2795. }
  2796. #ifdef notyet
  2797. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2798. #else
  2799. qdf_mem_free(peer);
  2800. #endif
  2801. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2802. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2803. vdev->vdev_id, peer->mac_addr.raw);
  2804. }
  2805. } else {
  2806. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2807. }
  2808. }
  2809. /*
  2810. * dp_peer_detach_wifi3() – Detach txrx peer
  2811. * @peer_handle: Datapath peer handle
  2812. *
  2813. */
  2814. static void dp_peer_delete_wifi3(void *peer_handle)
  2815. {
  2816. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2817. /* redirect the peer's rx delivery function to point to a
  2818. * discard func
  2819. */
  2820. peer->rx_opt_proc = dp_rx_discard;
  2821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2822. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2823. #ifndef CONFIG_WIN
  2824. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2825. #endif
  2826. qdf_spinlock_destroy(&peer->peer_info_lock);
  2827. /*
  2828. * Remove the reference added during peer_attach.
  2829. * The peer will still be left allocated until the
  2830. * PEER_UNMAP message arrives to remove the other
  2831. * reference, added by the PEER_MAP message.
  2832. */
  2833. dp_peer_unref_delete(peer_handle);
  2834. }
  2835. /*
  2836. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2837. * @peer_handle: Datapath peer handle
  2838. *
  2839. */
  2840. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2841. {
  2842. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2843. return vdev->mac_addr.raw;
  2844. }
  2845. /*
  2846. * dp_vdev_set_wds() - Enable per packet stats
  2847. * @vdev_handle: DP VDEV handle
  2848. * @val: value
  2849. *
  2850. * Return: none
  2851. */
  2852. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2853. {
  2854. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2855. vdev->wds_enabled = val;
  2856. return 0;
  2857. }
  2858. /*
  2859. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2860. * @peer_handle: Datapath peer handle
  2861. *
  2862. */
  2863. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2864. uint8_t vdev_id)
  2865. {
  2866. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2867. struct dp_vdev *vdev = NULL;
  2868. if (qdf_unlikely(!pdev))
  2869. return NULL;
  2870. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2871. if (vdev->vdev_id == vdev_id)
  2872. break;
  2873. }
  2874. return (struct cdp_vdev *)vdev;
  2875. }
  2876. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2877. {
  2878. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2879. return vdev->opmode;
  2880. }
  2881. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2882. {
  2883. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2884. struct dp_pdev *pdev = vdev->pdev;
  2885. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2886. }
  2887. /**
  2888. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2889. * @vdev_handle: Datapath VDEV handle
  2890. * @smart_monitor: Flag to denote if its smart monitor mode
  2891. *
  2892. * Return: 0 on success, not 0 on failure
  2893. */
  2894. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2895. uint8_t smart_monitor)
  2896. {
  2897. /* Many monitor VAPs can exists in a system but only one can be up at
  2898. * anytime
  2899. */
  2900. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2901. struct dp_pdev *pdev;
  2902. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2903. struct dp_soc *soc;
  2904. uint8_t pdev_id;
  2905. qdf_assert(vdev);
  2906. pdev = vdev->pdev;
  2907. pdev_id = pdev->pdev_id;
  2908. soc = pdev->soc;
  2909. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2910. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  2911. pdev, pdev_id, soc, vdev);
  2912. /*Check if current pdev's monitor_vdev exists */
  2913. if (pdev->monitor_vdev) {
  2914. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2915. "vdev=%p\n", vdev);
  2916. qdf_assert(vdev);
  2917. }
  2918. pdev->monitor_vdev = vdev;
  2919. /* If smart monitor mode, do not configure monitor ring */
  2920. if (smart_monitor)
  2921. return QDF_STATUS_SUCCESS;
  2922. htt_tlv_filter.mpdu_start = 1;
  2923. htt_tlv_filter.msdu_start = 1;
  2924. htt_tlv_filter.packet = 1;
  2925. htt_tlv_filter.msdu_end = 1;
  2926. htt_tlv_filter.mpdu_end = 1;
  2927. htt_tlv_filter.packet_header = 1;
  2928. htt_tlv_filter.attention = 1;
  2929. htt_tlv_filter.ppdu_start = 0;
  2930. htt_tlv_filter.ppdu_end = 0;
  2931. htt_tlv_filter.ppdu_end_user_stats = 0;
  2932. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2933. htt_tlv_filter.ppdu_end_status_done = 0;
  2934. htt_tlv_filter.enable_fp = 1;
  2935. htt_tlv_filter.enable_md = 0;
  2936. htt_tlv_filter.enable_mo = 1;
  2937. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2938. pdev->rxdma_mon_buf_ring.hal_srng,
  2939. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2940. htt_tlv_filter.mpdu_start = 1;
  2941. htt_tlv_filter.msdu_start = 1;
  2942. htt_tlv_filter.packet = 0;
  2943. htt_tlv_filter.msdu_end = 1;
  2944. htt_tlv_filter.mpdu_end = 1;
  2945. htt_tlv_filter.packet_header = 1;
  2946. htt_tlv_filter.attention = 1;
  2947. htt_tlv_filter.ppdu_start = 1;
  2948. htt_tlv_filter.ppdu_end = 1;
  2949. htt_tlv_filter.ppdu_end_user_stats = 1;
  2950. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  2951. htt_tlv_filter.ppdu_end_status_done = 1;
  2952. htt_tlv_filter.enable_fp = 1;
  2953. htt_tlv_filter.enable_md = 0;
  2954. htt_tlv_filter.enable_mo = 1;
  2955. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2956. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2957. RX_BUFFER_SIZE, &htt_tlv_filter);
  2958. return QDF_STATUS_SUCCESS;
  2959. }
  2960. #ifdef MESH_MODE_SUPPORT
  2961. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  2962. {
  2963. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2964. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2965. FL("val %d"), val);
  2966. vdev->mesh_vdev = val;
  2967. }
  2968. /*
  2969. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  2970. * @vdev_hdl: virtual device object
  2971. * @val: value to be set
  2972. *
  2973. * Return: void
  2974. */
  2975. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  2976. {
  2977. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2979. FL("val %d"), val);
  2980. vdev->mesh_rx_filter = val;
  2981. }
  2982. #endif
  2983. /**
  2984. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  2985. * @vdev: DP VDEV handle
  2986. *
  2987. * return: void
  2988. */
  2989. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  2990. {
  2991. struct dp_peer *peer = NULL;
  2992. struct dp_soc *soc = vdev->pdev->soc;
  2993. int i;
  2994. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  2995. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  2996. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2997. if (!peer)
  2998. return;
  2999. for (i = 0; i < MAX_MCS; i++) {
  3000. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  3001. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  3002. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  3003. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  3004. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  3005. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  3006. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  3007. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  3008. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  3009. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  3010. }
  3011. for (i = 0; i < MAX_BW; i++) {
  3012. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3013. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3014. }
  3015. for (i = 0; i < SS_COUNT; i++)
  3016. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3017. for (i = 0; i < WME_AC_MAX; i++) {
  3018. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3019. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3020. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3021. }
  3022. for (i = 0; i < MAX_GI; i++) {
  3023. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3024. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3025. }
  3026. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3027. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3028. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3029. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3030. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3031. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3032. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3033. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3034. DP_STATS_AGGR(vdev, peer, tx.retries);
  3035. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3036. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3037. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3038. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3039. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3040. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3041. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3042. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3043. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3044. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3045. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3046. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3047. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3048. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3049. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3050. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3051. peer->stats.rx.multicast.num;
  3052. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3053. peer->stats.rx.multicast.bytes;
  3054. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3055. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3056. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3057. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3058. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3059. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3060. vdev->stats.tx.last_ack_rssi =
  3061. peer->stats.tx.last_ack_rssi;
  3062. }
  3063. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3064. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3065. }
  3066. /**
  3067. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3068. * @pdev: DP PDEV handle
  3069. *
  3070. * return: void
  3071. */
  3072. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3073. {
  3074. struct dp_vdev *vdev = NULL;
  3075. uint8_t i;
  3076. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3077. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3078. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3079. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3080. if (!vdev)
  3081. return;
  3082. dp_aggregate_vdev_stats(vdev);
  3083. for (i = 0; i < MAX_MCS; i++) {
  3084. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  3085. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  3086. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  3087. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  3088. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  3089. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  3090. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  3091. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  3092. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  3093. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  3094. }
  3095. for (i = 0; i < MAX_BW; i++) {
  3096. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3097. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3098. }
  3099. for (i = 0; i < SS_COUNT; i++)
  3100. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3101. for (i = 0; i < WME_AC_MAX; i++) {
  3102. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3103. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3104. DP_STATS_AGGR(pdev, vdev,
  3105. tx.excess_retries_ac[i]);
  3106. }
  3107. for (i = 0; i < MAX_GI; i++) {
  3108. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3109. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3110. }
  3111. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3112. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3113. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3114. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3115. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3116. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3117. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3118. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3119. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3120. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3121. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3122. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3123. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3124. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3125. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3126. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3127. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3128. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3129. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3130. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3131. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3132. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3133. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3134. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3135. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3136. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3137. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3138. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3139. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3140. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3141. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3142. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3143. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3144. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3145. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3146. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3147. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3148. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3149. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3150. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3151. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3152. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3153. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3154. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3155. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3156. DP_STATS_AGGR(pdev, vdev,
  3157. tx_i.mcast_en.dropped_map_error);
  3158. DP_STATS_AGGR(pdev, vdev,
  3159. tx_i.mcast_en.dropped_self_mac);
  3160. DP_STATS_AGGR(pdev, vdev,
  3161. tx_i.mcast_en.dropped_send_fail);
  3162. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3163. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3164. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3165. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3166. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3167. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3168. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3169. pdev->stats.tx_i.dropped.dma_error +
  3170. pdev->stats.tx_i.dropped.ring_full +
  3171. pdev->stats.tx_i.dropped.enqueue_fail +
  3172. pdev->stats.tx_i.dropped.desc_na +
  3173. pdev->stats.tx_i.dropped.res_full;
  3174. pdev->stats.tx.last_ack_rssi =
  3175. vdev->stats.tx.last_ack_rssi;
  3176. pdev->stats.tx_i.tso.num_seg =
  3177. vdev->stats.tx_i.tso.num_seg;
  3178. }
  3179. }
  3180. /**
  3181. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3182. * @pdev: DP_PDEV Handle
  3183. *
  3184. * Return:void
  3185. */
  3186. static inline void
  3187. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3188. {
  3189. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3190. DP_PRINT_STATS("Received From Stack:");
  3191. DP_PRINT_STATS(" Packets = %d",
  3192. pdev->stats.tx_i.rcvd.num);
  3193. DP_PRINT_STATS(" Bytes = %d",
  3194. pdev->stats.tx_i.rcvd.bytes);
  3195. DP_PRINT_STATS("Processed:");
  3196. DP_PRINT_STATS(" Packets = %d",
  3197. pdev->stats.tx_i.processed.num);
  3198. DP_PRINT_STATS(" Bytes = %d",
  3199. pdev->stats.tx_i.processed.bytes);
  3200. DP_PRINT_STATS("Completions:");
  3201. DP_PRINT_STATS(" Packets = %d",
  3202. pdev->stats.tx.comp_pkt.num);
  3203. DP_PRINT_STATS(" Bytes = %d",
  3204. pdev->stats.tx.comp_pkt.bytes);
  3205. DP_PRINT_STATS("Dropped:");
  3206. DP_PRINT_STATS(" Total = %d",
  3207. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3208. DP_PRINT_STATS(" Dma_map_error = %d",
  3209. pdev->stats.tx_i.dropped.dma_error);
  3210. DP_PRINT_STATS(" Ring Full = %d",
  3211. pdev->stats.tx_i.dropped.ring_full);
  3212. DP_PRINT_STATS(" Descriptor Not available = %d",
  3213. pdev->stats.tx_i.dropped.desc_na);
  3214. DP_PRINT_STATS(" HW enqueue failed= %d",
  3215. pdev->stats.tx_i.dropped.enqueue_fail);
  3216. DP_PRINT_STATS(" Resources Full = %d",
  3217. pdev->stats.tx_i.dropped.res_full);
  3218. DP_PRINT_STATS(" FW removed = %d",
  3219. pdev->stats.tx.dropped.fw_rem);
  3220. DP_PRINT_STATS(" FW removed transmitted = %d",
  3221. pdev->stats.tx.dropped.fw_rem_tx);
  3222. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3223. pdev->stats.tx.dropped.fw_rem_notx);
  3224. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3225. pdev->stats.tx.dropped.age_out);
  3226. DP_PRINT_STATS("Scatter Gather:");
  3227. DP_PRINT_STATS(" Packets = %d",
  3228. pdev->stats.tx_i.sg.sg_pkt.num);
  3229. DP_PRINT_STATS(" Bytes = %d",
  3230. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3231. DP_PRINT_STATS(" Dropped By Host = %d",
  3232. pdev->stats.tx_i.sg.dropped_host);
  3233. DP_PRINT_STATS(" Dropped By Target = %d",
  3234. pdev->stats.tx_i.sg.dropped_target);
  3235. DP_PRINT_STATS("TSO:");
  3236. DP_PRINT_STATS(" Number of Segments = %d",
  3237. pdev->stats.tx_i.tso.num_seg);
  3238. DP_PRINT_STATS(" Packets = %d",
  3239. pdev->stats.tx_i.tso.tso_pkt.num);
  3240. DP_PRINT_STATS(" Bytes = %d",
  3241. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3242. DP_PRINT_STATS(" Dropped By Host = %d",
  3243. pdev->stats.tx_i.tso.dropped_host);
  3244. DP_PRINT_STATS("Mcast Enhancement:");
  3245. DP_PRINT_STATS(" Packets = %d",
  3246. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3247. DP_PRINT_STATS(" Bytes = %d",
  3248. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3249. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3250. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3251. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3252. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3253. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3254. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3255. DP_PRINT_STATS(" Unicast sent = %d",
  3256. pdev->stats.tx_i.mcast_en.ucast);
  3257. DP_PRINT_STATS("Raw:");
  3258. DP_PRINT_STATS(" Packets = %d",
  3259. pdev->stats.tx_i.raw.raw_pkt.num);
  3260. DP_PRINT_STATS(" Bytes = %d",
  3261. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3262. DP_PRINT_STATS(" DMA map error = %d",
  3263. pdev->stats.tx_i.raw.dma_map_error);
  3264. DP_PRINT_STATS("Reinjected:");
  3265. DP_PRINT_STATS(" Packets = %d",
  3266. pdev->stats.tx_i.reinject_pkts.num);
  3267. DP_PRINT_STATS("Bytes = %d\n",
  3268. pdev->stats.tx_i.reinject_pkts.bytes);
  3269. DP_PRINT_STATS("Inspected:");
  3270. DP_PRINT_STATS(" Packets = %d",
  3271. pdev->stats.tx_i.inspect_pkts.num);
  3272. DP_PRINT_STATS(" Bytes = %d",
  3273. pdev->stats.tx_i.inspect_pkts.bytes);
  3274. }
  3275. /**
  3276. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3277. * @pdev: DP_PDEV Handle
  3278. *
  3279. * Return: void
  3280. */
  3281. static inline void
  3282. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3283. {
  3284. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3285. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3286. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3287. pdev->stats.rx.rcvd_reo[0].num,
  3288. pdev->stats.rx.rcvd_reo[1].num,
  3289. pdev->stats.rx.rcvd_reo[2].num,
  3290. pdev->stats.rx.rcvd_reo[3].num);
  3291. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3292. pdev->stats.rx.rcvd_reo[0].bytes,
  3293. pdev->stats.rx.rcvd_reo[1].bytes,
  3294. pdev->stats.rx.rcvd_reo[2].bytes,
  3295. pdev->stats.rx.rcvd_reo[3].bytes);
  3296. DP_PRINT_STATS("Replenished:");
  3297. DP_PRINT_STATS(" Packets = %d",
  3298. pdev->stats.replenish.pkts.num);
  3299. DP_PRINT_STATS(" Bytes = %d",
  3300. pdev->stats.replenish.pkts.bytes);
  3301. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3302. pdev->stats.buf_freelist);
  3303. DP_PRINT_STATS("Dropped:");
  3304. DP_PRINT_STATS(" msdu_not_done = %d",
  3305. pdev->stats.dropped.msdu_not_done);
  3306. DP_PRINT_STATS("Sent To Stack:");
  3307. DP_PRINT_STATS(" Packets = %d",
  3308. pdev->stats.rx.to_stack.num);
  3309. DP_PRINT_STATS(" Bytes = %d",
  3310. pdev->stats.rx.to_stack.bytes);
  3311. DP_PRINT_STATS("Multicast/Broadcast:");
  3312. DP_PRINT_STATS(" Packets = %d",
  3313. pdev->stats.rx.multicast.num);
  3314. DP_PRINT_STATS(" Bytes = %d",
  3315. pdev->stats.rx.multicast.bytes);
  3316. DP_PRINT_STATS("Errors:");
  3317. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3318. pdev->stats.replenish.rxdma_err);
  3319. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3320. pdev->stats.err.desc_alloc_fail);
  3321. }
  3322. /**
  3323. * dp_print_soc_tx_stats(): Print SOC level stats
  3324. * @soc DP_SOC Handle
  3325. *
  3326. * Return: void
  3327. */
  3328. static inline void
  3329. dp_print_soc_tx_stats(struct dp_soc *soc)
  3330. {
  3331. DP_PRINT_STATS("SOC Tx Stats:\n");
  3332. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3333. soc->stats.tx.desc_in_use);
  3334. DP_PRINT_STATS("Invalid peer:");
  3335. DP_PRINT_STATS(" Packets = %d",
  3336. soc->stats.tx.tx_invalid_peer.num);
  3337. DP_PRINT_STATS(" Bytes = %d",
  3338. soc->stats.tx.tx_invalid_peer.bytes);
  3339. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3340. soc->stats.tx.tcl_ring_full[0],
  3341. soc->stats.tx.tcl_ring_full[1],
  3342. soc->stats.tx.tcl_ring_full[2]);
  3343. }
  3344. /**
  3345. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3346. * @soc: DP_SOC Handle
  3347. *
  3348. * Return:void
  3349. */
  3350. static inline void
  3351. dp_print_soc_rx_stats(struct dp_soc *soc)
  3352. {
  3353. uint32_t i;
  3354. char reo_error[DP_REO_ERR_LENGTH];
  3355. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3356. uint8_t index = 0;
  3357. DP_PRINT_STATS("SOC Rx Stats:\n");
  3358. DP_PRINT_STATS("Errors:\n");
  3359. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3360. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3361. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3362. DP_PRINT_STATS("Invalid RBM = %d",
  3363. soc->stats.rx.err.invalid_rbm);
  3364. DP_PRINT_STATS("Invalid Vdev = %d",
  3365. soc->stats.rx.err.invalid_vdev);
  3366. DP_PRINT_STATS("Invalid Pdev = %d",
  3367. soc->stats.rx.err.invalid_pdev);
  3368. DP_PRINT_STATS("Invalid Peer = %d",
  3369. soc->stats.rx.err.rx_invalid_peer.num);
  3370. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3371. soc->stats.rx.err.hal_ring_access_fail);
  3372. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3373. index += qdf_snprint(&rxdma_error[index],
  3374. DP_RXDMA_ERR_LENGTH - index,
  3375. " %d", soc->stats.rx.err.rxdma_error[i]);
  3376. }
  3377. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3378. rxdma_error);
  3379. index = 0;
  3380. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3381. index += qdf_snprint(&reo_error[index],
  3382. DP_REO_ERR_LENGTH - index,
  3383. " %d", soc->stats.rx.err.reo_error[i]);
  3384. }
  3385. DP_PRINT_STATS("REO Error(0-14):%s",
  3386. reo_error);
  3387. }
  3388. /**
  3389. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3390. * @vdev: DP_VDEV handle
  3391. *
  3392. * Return:void
  3393. */
  3394. static inline void
  3395. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3396. {
  3397. struct dp_peer *peer = NULL;
  3398. DP_STATS_CLR(vdev->pdev);
  3399. DP_STATS_CLR(vdev->pdev->soc);
  3400. DP_STATS_CLR(vdev);
  3401. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3402. if (!peer)
  3403. return;
  3404. DP_STATS_CLR(peer);
  3405. }
  3406. }
  3407. /**
  3408. * dp_print_rx_rates(): Print Rx rate stats
  3409. * @vdev: DP_VDEV handle
  3410. *
  3411. * Return:void
  3412. */
  3413. static inline void
  3414. dp_print_rx_rates(struct dp_vdev *vdev)
  3415. {
  3416. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3417. uint8_t i, mcs, pkt_type;
  3418. uint8_t index = 0;
  3419. char nss[DP_NSS_LENGTH];
  3420. DP_PRINT_STATS("Rx Rate Info:\n");
  3421. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3422. index = 0;
  3423. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3424. if (!dp_rate_string[pkt_type][mcs].valid)
  3425. continue;
  3426. DP_PRINT_STATS(" %s = %d",
  3427. dp_rate_string[pkt_type][mcs].mcs_type,
  3428. pdev->stats.rx.pkt_type[pkt_type].
  3429. mcs_count[mcs]);
  3430. }
  3431. DP_PRINT_STATS("\n");
  3432. }
  3433. index = 0;
  3434. for (i = 0; i < SS_COUNT; i++) {
  3435. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3436. " %d", pdev->stats.rx.nss[i]);
  3437. }
  3438. DP_PRINT_STATS("NSS(0-7) = %s",
  3439. nss);
  3440. DP_PRINT_STATS("SGI ="
  3441. " 0.8us %d,"
  3442. " 0.4us %d,"
  3443. " 1.6us %d,"
  3444. " 3.2us %d,",
  3445. pdev->stats.rx.sgi_count[0],
  3446. pdev->stats.rx.sgi_count[1],
  3447. pdev->stats.rx.sgi_count[2],
  3448. pdev->stats.rx.sgi_count[3]);
  3449. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3450. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3451. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3452. DP_PRINT_STATS("Reception Type ="
  3453. " SU: %d,"
  3454. " MU_MIMO:%d,"
  3455. " MU_OFDMA:%d,"
  3456. " MU_OFDMA_MIMO:%d\n",
  3457. pdev->stats.rx.reception_type[0],
  3458. pdev->stats.rx.reception_type[1],
  3459. pdev->stats.rx.reception_type[2],
  3460. pdev->stats.rx.reception_type[3]);
  3461. DP_PRINT_STATS("Aggregation:\n");
  3462. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3463. pdev->stats.rx.ampdu_cnt);
  3464. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3465. pdev->stats.rx.non_ampdu_cnt);
  3466. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3467. pdev->stats.rx.amsdu_cnt);
  3468. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3469. pdev->stats.rx.non_amsdu_cnt);
  3470. }
  3471. /**
  3472. * dp_print_tx_rates(): Print tx rates
  3473. * @vdev: DP_VDEV handle
  3474. *
  3475. * Return:void
  3476. */
  3477. static inline void
  3478. dp_print_tx_rates(struct dp_vdev *vdev)
  3479. {
  3480. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3481. uint8_t mcs, pkt_type;
  3482. uint32_t index;
  3483. DP_PRINT_STATS("Tx Rate Info:\n");
  3484. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3485. index = 0;
  3486. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3487. if (!dp_rate_string[pkt_type][mcs].valid)
  3488. continue;
  3489. DP_PRINT_STATS(" %s = %d",
  3490. dp_rate_string[pkt_type][mcs].mcs_type,
  3491. pdev->stats.tx.pkt_type[pkt_type].
  3492. mcs_count[mcs]);
  3493. }
  3494. DP_PRINT_STATS("\n");
  3495. }
  3496. DP_PRINT_STATS("SGI ="
  3497. " 0.8us %d"
  3498. " 0.4us %d"
  3499. " 1.6us %d"
  3500. " 3.2us %d",
  3501. pdev->stats.tx.sgi_count[0],
  3502. pdev->stats.tx.sgi_count[1],
  3503. pdev->stats.tx.sgi_count[2],
  3504. pdev->stats.tx.sgi_count[3]);
  3505. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3506. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3507. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3508. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3509. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3510. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3511. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3512. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3513. DP_PRINT_STATS("Aggregation:\n");
  3514. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3515. pdev->stats.tx.amsdu_cnt);
  3516. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3517. pdev->stats.tx.non_amsdu_cnt);
  3518. }
  3519. /**
  3520. * dp_print_peer_stats():print peer stats
  3521. * @peer: DP_PEER handle
  3522. *
  3523. * return void
  3524. */
  3525. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3526. {
  3527. uint8_t i, mcs, pkt_type;
  3528. uint32_t index;
  3529. char nss[DP_NSS_LENGTH];
  3530. DP_PRINT_STATS("Node Tx Stats:\n");
  3531. DP_PRINT_STATS("Total Packet Completions = %d",
  3532. peer->stats.tx.comp_pkt.num);
  3533. DP_PRINT_STATS("Total Bytes Completions = %d",
  3534. peer->stats.tx.comp_pkt.bytes);
  3535. DP_PRINT_STATS("Success Packets = %d",
  3536. peer->stats.tx.tx_success.num);
  3537. DP_PRINT_STATS("Success Bytes = %d",
  3538. peer->stats.tx.tx_success.bytes);
  3539. DP_PRINT_STATS("Packets Failed = %d",
  3540. peer->stats.tx.tx_failed);
  3541. DP_PRINT_STATS("Packets In OFDMA = %d",
  3542. peer->stats.tx.ofdma);
  3543. DP_PRINT_STATS("Packets In STBC = %d",
  3544. peer->stats.tx.stbc);
  3545. DP_PRINT_STATS("Packets In LDPC = %d",
  3546. peer->stats.tx.ldpc);
  3547. DP_PRINT_STATS("Packet Retries = %d",
  3548. peer->stats.tx.retries);
  3549. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3550. peer->stats.tx.amsdu_cnt);
  3551. DP_PRINT_STATS("Last Packet RSSI = %d",
  3552. peer->stats.tx.last_ack_rssi);
  3553. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3554. peer->stats.tx.dropped.fw_rem);
  3555. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3556. peer->stats.tx.dropped.fw_rem_tx);
  3557. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3558. peer->stats.tx.dropped.fw_rem_notx);
  3559. DP_PRINT_STATS("Dropped : Age Out = %d",
  3560. peer->stats.tx.dropped.age_out);
  3561. DP_PRINT_STATS("Rate Info:");
  3562. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3563. index = 0;
  3564. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3565. if (!dp_rate_string[pkt_type][mcs].valid)
  3566. continue;
  3567. DP_PRINT_STATS(" %s = %d",
  3568. dp_rate_string[pkt_type][mcs].mcs_type,
  3569. peer->stats.tx.pkt_type[pkt_type].
  3570. mcs_count[mcs]);
  3571. }
  3572. DP_PRINT_STATS("\n");
  3573. }
  3574. DP_PRINT_STATS("SGI = "
  3575. " 0.8us %d"
  3576. " 0.4us %d"
  3577. " 1.6us %d"
  3578. " 3.2us %d",
  3579. peer->stats.tx.sgi_count[0],
  3580. peer->stats.tx.sgi_count[1],
  3581. peer->stats.tx.sgi_count[2],
  3582. peer->stats.tx.sgi_count[3]);
  3583. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3584. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3585. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3586. DP_PRINT_STATS("Aggregation:");
  3587. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3588. peer->stats.tx.amsdu_cnt);
  3589. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3590. peer->stats.tx.non_amsdu_cnt);
  3591. DP_PRINT_STATS("Node Rx Stats:");
  3592. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3593. peer->stats.rx.to_stack.num);
  3594. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3595. peer->stats.rx.to_stack.bytes);
  3596. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3597. DP_PRINT_STATS("Packets Received = %d",
  3598. peer->stats.rx.rcvd_reo[i].num);
  3599. DP_PRINT_STATS("Bytes Received = %d",
  3600. peer->stats.rx.rcvd_reo[i].bytes);
  3601. }
  3602. DP_PRINT_STATS("Multicast Packets Received = %d",
  3603. peer->stats.rx.multicast.num);
  3604. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3605. peer->stats.rx.multicast.bytes);
  3606. DP_PRINT_STATS("WDS Packets Received = %d",
  3607. peer->stats.rx.wds.num);
  3608. DP_PRINT_STATS("WDS Bytes Received = %d",
  3609. peer->stats.rx.wds.bytes);
  3610. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3611. peer->stats.rx.intra_bss.pkts.num);
  3612. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3613. peer->stats.rx.intra_bss.pkts.bytes);
  3614. DP_PRINT_STATS("Raw Packets Received = %d",
  3615. peer->stats.rx.raw.num);
  3616. DP_PRINT_STATS("Raw Bytes Received = %d",
  3617. peer->stats.rx.raw.bytes);
  3618. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3619. peer->stats.rx.err.mic_err);
  3620. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3621. peer->stats.rx.err.decrypt_err);
  3622. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3623. peer->stats.rx.non_ampdu_cnt);
  3624. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3625. peer->stats.rx.ampdu_cnt);
  3626. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3627. peer->stats.rx.non_amsdu_cnt);
  3628. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3629. peer->stats.rx.amsdu_cnt);
  3630. DP_PRINT_STATS("SGI ="
  3631. " 0.8us %d"
  3632. " 0.4us %d"
  3633. " 1.6us %d"
  3634. " 3.2us %d",
  3635. peer->stats.rx.sgi_count[0],
  3636. peer->stats.rx.sgi_count[1],
  3637. peer->stats.rx.sgi_count[2],
  3638. peer->stats.rx.sgi_count[3]);
  3639. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3640. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3641. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3642. DP_PRINT_STATS("Reception Type ="
  3643. " SU %d,"
  3644. " MU_MIMO %d,"
  3645. " MU_OFDMA %d,"
  3646. " MU_OFDMA_MIMO %d",
  3647. peer->stats.rx.reception_type[0],
  3648. peer->stats.rx.reception_type[1],
  3649. peer->stats.rx.reception_type[2],
  3650. peer->stats.rx.reception_type[3]);
  3651. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3652. index = 0;
  3653. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3654. if (!dp_rate_string[pkt_type][mcs].valid)
  3655. continue;
  3656. DP_PRINT_STATS(" %s = %d",
  3657. dp_rate_string[pkt_type][mcs].mcs_type,
  3658. peer->stats.rx.pkt_type[pkt_type].
  3659. mcs_count[mcs]);
  3660. }
  3661. DP_PRINT_STATS("\n");
  3662. }
  3663. index = 0;
  3664. for (i = 0; i < SS_COUNT; i++) {
  3665. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3666. " %d", peer->stats.rx.nss[i]);
  3667. }
  3668. DP_PRINT_STATS("NSS(0-7) = %s",
  3669. nss);
  3670. DP_PRINT_STATS("Aggregation:");
  3671. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3672. peer->stats.rx.ampdu_cnt);
  3673. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3674. peer->stats.rx.non_ampdu_cnt);
  3675. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3676. peer->stats.rx.amsdu_cnt);
  3677. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3678. peer->stats.rx.non_amsdu_cnt);
  3679. }
  3680. /**
  3681. * dp_print_host_stats()- Function to print the stats aggregated at host
  3682. * @vdev_handle: DP_VDEV handle
  3683. * @type: host stats type
  3684. *
  3685. * Available Stat types
  3686. * TXRX_CLEAR_STATS : Clear the stats
  3687. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3688. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3689. * TXRX_TX_HOST_STATS: Print Tx Stats
  3690. * TXRX_RX_HOST_STATS: Print Rx Stats
  3691. *
  3692. * Return: 0 on success, print error message in case of failure
  3693. */
  3694. static int
  3695. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3696. {
  3697. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3698. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3699. dp_aggregate_pdev_stats(pdev);
  3700. switch (type) {
  3701. case TXRX_CLEAR_STATS:
  3702. dp_txrx_host_stats_clr(vdev);
  3703. break;
  3704. case TXRX_RX_RATE_STATS:
  3705. dp_print_rx_rates(vdev);
  3706. break;
  3707. case TXRX_TX_RATE_STATS:
  3708. dp_print_tx_rates(vdev);
  3709. break;
  3710. case TXRX_TX_HOST_STATS:
  3711. dp_print_pdev_tx_stats(pdev);
  3712. dp_print_soc_tx_stats(pdev->soc);
  3713. break;
  3714. case TXRX_RX_HOST_STATS:
  3715. dp_print_pdev_rx_stats(pdev);
  3716. dp_print_soc_rx_stats(pdev->soc);
  3717. break;
  3718. default:
  3719. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3720. break;
  3721. }
  3722. return 0;
  3723. }
  3724. /*
  3725. * dp_get_host_peer_stats()- function to print peer stats
  3726. * @pdev_handle: DP_PDEV handle
  3727. * @mac_addr: mac address of the peer
  3728. *
  3729. * Return: void
  3730. */
  3731. static void
  3732. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3733. {
  3734. struct dp_peer *peer;
  3735. uint8_t local_id;
  3736. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3737. &local_id);
  3738. if (!peer) {
  3739. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3740. "%s: Invalid peer\n", __func__);
  3741. return;
  3742. }
  3743. dp_print_peer_stats(peer);
  3744. dp_peer_rxtid_stats(peer);
  3745. return;
  3746. }
  3747. /*
  3748. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3749. * @pdev_handle: DP_PDEV handle
  3750. *
  3751. * Return: void
  3752. */
  3753. static void
  3754. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3755. {
  3756. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3757. pdev->enhanced_stats_en = 1;
  3758. }
  3759. /*
  3760. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3761. * @pdev_handle: DP_PDEV handle
  3762. *
  3763. * Return: void
  3764. */
  3765. static void
  3766. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3767. {
  3768. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3769. pdev->enhanced_stats_en = 0;
  3770. }
  3771. /*
  3772. * dp_get_fw_peer_stats()- function to print peer stats
  3773. * @pdev_handle: DP_PDEV handle
  3774. * @mac_addr: mac address of the peer
  3775. * @cap: Type of htt stats requested
  3776. *
  3777. * Currently Supporting only MAC ID based requests Only
  3778. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3779. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3780. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3781. *
  3782. * Return: void
  3783. */
  3784. static void
  3785. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3786. uint32_t cap)
  3787. {
  3788. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3789. uint32_t config_param0 = 0;
  3790. uint32_t config_param1 = 0;
  3791. uint32_t config_param2 = 0;
  3792. uint32_t config_param3 = 0;
  3793. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3794. config_param0 |= (1 << (cap + 1));
  3795. config_param1 = 0x8f;
  3796. config_param2 |= (mac_addr[0] & 0x000000ff);
  3797. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3798. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3799. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3800. config_param3 |= (mac_addr[4] & 0x000000ff);
  3801. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3802. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3803. config_param0, config_param1, config_param2,
  3804. config_param3);
  3805. }
  3806. /*
  3807. * dp_set_vdev_param: function to set parameters in vdev
  3808. * @param: parameter type to be set
  3809. * @val: value of parameter to be set
  3810. *
  3811. * return: void
  3812. */
  3813. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3814. enum cdp_vdev_param_type param, uint32_t val)
  3815. {
  3816. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3817. switch (param) {
  3818. case CDP_ENABLE_WDS:
  3819. vdev->wds_enabled = val;
  3820. break;
  3821. case CDP_ENABLE_NAWDS:
  3822. vdev->nawds_enabled = val;
  3823. break;
  3824. case CDP_ENABLE_MCAST_EN:
  3825. vdev->mcast_enhancement_en = val;
  3826. break;
  3827. case CDP_ENABLE_PROXYSTA:
  3828. vdev->proxysta_vdev = val;
  3829. break;
  3830. case CDP_UPDATE_TDLS_FLAGS:
  3831. vdev->tdls_link_connected = val;
  3832. break;
  3833. case CDP_CFG_WDS_AGING_TIMER:
  3834. if (val == 0)
  3835. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  3836. else if (val != vdev->wds_aging_timer_val)
  3837. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  3838. vdev->wds_aging_timer_val = val;
  3839. break;
  3840. default:
  3841. break;
  3842. }
  3843. dp_tx_vdev_update_search_flags(vdev);
  3844. }
  3845. /**
  3846. * dp_peer_set_nawds: set nawds bit in peer
  3847. * @peer_handle: pointer to peer
  3848. * @value: enable/disable nawds
  3849. *
  3850. * return: void
  3851. */
  3852. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  3853. {
  3854. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3855. peer->nawds_enabled = value;
  3856. }
  3857. /*
  3858. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  3859. * @vdev_handle: DP_VDEV handle
  3860. * @map_id:ID of map that needs to be updated
  3861. *
  3862. * Return: void
  3863. */
  3864. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  3865. uint8_t map_id)
  3866. {
  3867. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3868. vdev->dscp_tid_map_id = map_id;
  3869. return;
  3870. }
  3871. /**
  3872. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  3873. * @pdev: DP_PDEV handle
  3874. * @map_id: ID of map that needs to be updated
  3875. * @tos: index value in map
  3876. * @tid: tid value passed by the user
  3877. *
  3878. * Return: void
  3879. */
  3880. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  3881. uint8_t map_id, uint8_t tos, uint8_t tid)
  3882. {
  3883. uint8_t dscp;
  3884. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  3885. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  3886. pdev->dscp_tid_map[map_id][dscp] = tid;
  3887. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  3888. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  3889. map_id, dscp);
  3890. return;
  3891. }
  3892. /**
  3893. * dp_fw_stats_process(): Process TxRX FW stats request
  3894. * @vdev_handle: DP VDEV handle
  3895. * @val: value passed by user
  3896. *
  3897. * return: int
  3898. */
  3899. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  3900. {
  3901. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3902. struct dp_pdev *pdev = NULL;
  3903. if (!vdev) {
  3904. DP_TRACE(NONE, "VDEV not found");
  3905. return 1;
  3906. }
  3907. pdev = vdev->pdev;
  3908. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  3909. }
  3910. /*
  3911. * dp_txrx_stats() - function to map to firmware and host stats
  3912. * @vdev: virtual handle
  3913. * @stats: type of statistics requested
  3914. *
  3915. * Return: integer
  3916. */
  3917. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  3918. {
  3919. int host_stats;
  3920. int fw_stats;
  3921. if (stats >= CDP_TXRX_MAX_STATS)
  3922. return 0;
  3923. /*
  3924. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  3925. * has to be updated if new FW HTT stats added
  3926. */
  3927. if (stats > CDP_TXRX_STATS_HTT_MAX)
  3928. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  3929. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  3930. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  3931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3932. "stats: %u fw_stats_type: %d host_stats_type: %d",
  3933. stats, fw_stats, host_stats);
  3934. if (fw_stats != TXRX_FW_STATS_INVALID)
  3935. return dp_fw_stats_process(vdev, fw_stats);
  3936. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  3937. (host_stats <= TXRX_HOST_STATS_MAX))
  3938. return dp_print_host_stats(vdev, host_stats);
  3939. else
  3940. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3941. "Wrong Input for TxRx Stats");
  3942. return 0;
  3943. }
  3944. /*
  3945. * dp_print_napi_stats(): NAPI stats
  3946. * @soc - soc handle
  3947. */
  3948. static void dp_print_napi_stats(struct dp_soc *soc)
  3949. {
  3950. hif_print_napi_stats(soc->hif_handle);
  3951. }
  3952. /*
  3953. * dp_print_per_ring_stats(): Packet count per ring
  3954. * @soc - soc handle
  3955. */
  3956. static void dp_print_per_ring_stats(struct dp_soc *soc)
  3957. {
  3958. uint8_t core, ring;
  3959. uint64_t total_packets;
  3960. DP_TRACE(FATAL, "Reo packets per ring:");
  3961. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  3962. total_packets = 0;
  3963. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  3964. for (core = 0; core < NR_CPUS; core++) {
  3965. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  3966. core, soc->stats.rx.ring_packets[core][ring]);
  3967. total_packets += soc->stats.rx.ring_packets[core][ring];
  3968. }
  3969. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  3970. ring, total_packets);
  3971. }
  3972. }
  3973. /*
  3974. * dp_txrx_path_stats() - Function to display dump stats
  3975. * @soc - soc handle
  3976. *
  3977. * return: none
  3978. */
  3979. static void dp_txrx_path_stats(struct dp_soc *soc)
  3980. {
  3981. uint8_t error_code;
  3982. uint8_t loop_pdev;
  3983. struct dp_pdev *pdev;
  3984. uint8_t i;
  3985. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  3986. pdev = soc->pdev_list[loop_pdev];
  3987. dp_aggregate_pdev_stats(pdev);
  3988. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3989. "Tx path Statistics:");
  3990. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  3991. pdev->stats.tx_i.rcvd.num,
  3992. pdev->stats.tx_i.rcvd.bytes);
  3993. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  3994. pdev->stats.tx_i.processed.num,
  3995. pdev->stats.tx_i.processed.bytes);
  3996. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  3997. pdev->stats.tx.tx_success.num,
  3998. pdev->stats.tx.tx_success.bytes);
  3999. DP_TRACE(FATAL, "Dropped in host:");
  4000. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4001. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4002. DP_TRACE(FATAL, "Descriptor not available: %u",
  4003. pdev->stats.tx_i.dropped.desc_na);
  4004. DP_TRACE(FATAL, "Ring full: %u",
  4005. pdev->stats.tx_i.dropped.ring_full);
  4006. DP_TRACE(FATAL, "Enqueue fail: %u",
  4007. pdev->stats.tx_i.dropped.enqueue_fail);
  4008. DP_TRACE(FATAL, "DMA Error: %u",
  4009. pdev->stats.tx_i.dropped.dma_error);
  4010. DP_TRACE(FATAL, "Dropped in hardware:");
  4011. DP_TRACE(FATAL, "total packets dropped: %u",
  4012. pdev->stats.tx.tx_failed);
  4013. DP_TRACE(FATAL, "mpdu age out: %u",
  4014. pdev->stats.tx.dropped.age_out);
  4015. DP_TRACE(FATAL, "firmware removed: %u",
  4016. pdev->stats.tx.dropped.fw_rem);
  4017. DP_TRACE(FATAL, "firmware removed tx: %u",
  4018. pdev->stats.tx.dropped.fw_rem_tx);
  4019. DP_TRACE(FATAL, "firmware removed notx %u",
  4020. pdev->stats.tx.dropped.fw_rem_notx);
  4021. DP_TRACE(FATAL, "peer_invalid: %u",
  4022. pdev->soc->stats.tx.tx_invalid_peer.num);
  4023. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4024. DP_TRACE(FATAL, "Single Packet: %u",
  4025. pdev->stats.tx_comp_histogram.pkts_1);
  4026. DP_TRACE(FATAL, "2-20 Packets: %u",
  4027. pdev->stats.tx_comp_histogram.pkts_2_20);
  4028. DP_TRACE(FATAL, "21-40 Packets: %u",
  4029. pdev->stats.tx_comp_histogram.pkts_21_40);
  4030. DP_TRACE(FATAL, "41-60 Packets: %u",
  4031. pdev->stats.tx_comp_histogram.pkts_41_60);
  4032. DP_TRACE(FATAL, "61-80 Packets: %u",
  4033. pdev->stats.tx_comp_histogram.pkts_61_80);
  4034. DP_TRACE(FATAL, "81-100 Packets: %u",
  4035. pdev->stats.tx_comp_histogram.pkts_81_100);
  4036. DP_TRACE(FATAL, "101-200 Packets: %u",
  4037. pdev->stats.tx_comp_histogram.pkts_101_200);
  4038. DP_TRACE(FATAL, " 201+ Packets: %u",
  4039. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4040. DP_TRACE(FATAL, "Rx path statistics");
  4041. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4042. pdev->stats.rx.to_stack.num,
  4043. pdev->stats.rx.to_stack.bytes);
  4044. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4045. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4046. i, pdev->stats.rx.rcvd_reo[i].num,
  4047. pdev->stats.rx.rcvd_reo[i].bytes);
  4048. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4049. pdev->stats.rx.intra_bss.pkts.num,
  4050. pdev->stats.rx.intra_bss.pkts.bytes);
  4051. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4052. pdev->stats.rx.raw.num,
  4053. pdev->stats.rx.raw.bytes);
  4054. DP_TRACE(FATAL, "dropped: error %u msdus",
  4055. pdev->stats.rx.err.mic_err);
  4056. DP_TRACE(FATAL, "peer invalid %u",
  4057. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4058. DP_TRACE(FATAL, "Reo Statistics");
  4059. DP_TRACE(FATAL, "rbm error: %u msdus",
  4060. pdev->soc->stats.rx.err.invalid_rbm);
  4061. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4062. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4063. DP_TRACE(FATAL, "Reo errors");
  4064. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4065. error_code++) {
  4066. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4067. error_code,
  4068. pdev->soc->stats.rx.err.reo_error[error_code]);
  4069. }
  4070. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4071. error_code++) {
  4072. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4073. error_code,
  4074. pdev->soc->stats.rx.err
  4075. .rxdma_error[error_code]);
  4076. }
  4077. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4078. DP_TRACE(FATAL, "Single Packet: %u",
  4079. pdev->stats.rx_ind_histogram.pkts_1);
  4080. DP_TRACE(FATAL, "2-20 Packets: %u",
  4081. pdev->stats.rx_ind_histogram.pkts_2_20);
  4082. DP_TRACE(FATAL, "21-40 Packets: %u",
  4083. pdev->stats.rx_ind_histogram.pkts_21_40);
  4084. DP_TRACE(FATAL, "41-60 Packets: %u",
  4085. pdev->stats.rx_ind_histogram.pkts_41_60);
  4086. DP_TRACE(FATAL, "61-80 Packets: %u",
  4087. pdev->stats.rx_ind_histogram.pkts_61_80);
  4088. DP_TRACE(FATAL, "81-100 Packets: %u",
  4089. pdev->stats.rx_ind_histogram.pkts_81_100);
  4090. DP_TRACE(FATAL, "101-200 Packets: %u",
  4091. pdev->stats.rx_ind_histogram.pkts_101_200);
  4092. DP_TRACE(FATAL, " 201+ Packets: %u",
  4093. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4094. }
  4095. }
  4096. /*
  4097. * dp_txrx_dump_stats() - Dump statistics
  4098. * @value - Statistics option
  4099. */
  4100. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4101. {
  4102. struct dp_soc *soc =
  4103. (struct dp_soc *)psoc;
  4104. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4105. if (!soc) {
  4106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4107. "%s: soc is NULL", __func__);
  4108. return QDF_STATUS_E_INVAL;
  4109. }
  4110. switch (value) {
  4111. case CDP_TXRX_PATH_STATS:
  4112. dp_txrx_path_stats(soc);
  4113. break;
  4114. case CDP_RX_RING_STATS:
  4115. dp_print_per_ring_stats(soc);
  4116. break;
  4117. case CDP_TXRX_TSO_STATS:
  4118. /* TODO: NOT IMPLEMENTED */
  4119. break;
  4120. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4121. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4122. break;
  4123. case CDP_DP_NAPI_STATS:
  4124. dp_print_napi_stats(soc);
  4125. break;
  4126. case CDP_TXRX_DESC_STATS:
  4127. /* TODO: NOT IMPLEMENTED */
  4128. break;
  4129. default:
  4130. status = QDF_STATUS_E_INVAL;
  4131. break;
  4132. }
  4133. return status;
  4134. }
  4135. static struct cdp_wds_ops dp_ops_wds = {
  4136. .vdev_set_wds = dp_vdev_set_wds,
  4137. };
  4138. /*
  4139. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4140. * @soc - datapath soc handle
  4141. * @peer - datapath peer handle
  4142. *
  4143. * Delete the AST entries belonging to a peer
  4144. */
  4145. #ifdef FEATURE_WDS
  4146. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4147. struct dp_peer *peer)
  4148. {
  4149. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4150. qdf_spin_lock_bh(&soc->ast_lock);
  4151. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4152. if (ast_entry->next_hop) {
  4153. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4154. peer->vdev->pdev->osif_pdev,
  4155. ast_entry->mac_addr.raw);
  4156. }
  4157. dp_peer_del_ast(soc, ast_entry);
  4158. }
  4159. qdf_spin_unlock_bh(&soc->ast_lock);
  4160. }
  4161. #else
  4162. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4163. struct dp_peer *peer)
  4164. {
  4165. }
  4166. #endif
  4167. #ifdef CONFIG_WIN
  4168. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4169. {
  4170. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4171. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4172. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4173. dp_peer_delete_ast_entries(soc, peer);
  4174. }
  4175. #endif
  4176. static struct cdp_cmn_ops dp_ops_cmn = {
  4177. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4178. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4179. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4180. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4181. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4182. .txrx_peer_create = dp_peer_create_wifi3,
  4183. .txrx_peer_setup = dp_peer_setup_wifi3,
  4184. #ifdef CONFIG_WIN
  4185. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4186. #else
  4187. .txrx_peer_teardown = NULL,
  4188. #endif
  4189. .txrx_peer_delete = dp_peer_delete_wifi3,
  4190. .txrx_vdev_register = dp_vdev_register_wifi3,
  4191. .txrx_soc_detach = dp_soc_detach_wifi3,
  4192. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4193. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4194. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4195. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4196. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4197. .delba_process = dp_delba_process_wifi3,
  4198. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4199. .flush_cache_rx_queue = NULL,
  4200. /* TODO: get API's for dscp-tid need to be added*/
  4201. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4202. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4203. .txrx_stats = dp_txrx_stats,
  4204. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4205. .display_stats = dp_txrx_dump_stats,
  4206. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4207. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4208. #ifdef DP_INTR_POLL_BASED
  4209. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4210. #else
  4211. .txrx_intr_attach = dp_soc_interrupt_attach,
  4212. #endif
  4213. .txrx_intr_detach = dp_soc_interrupt_detach,
  4214. .set_pn_check = dp_set_pn_check_wifi3,
  4215. /* TODO: Add other functions */
  4216. };
  4217. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4218. .txrx_peer_authorize = dp_peer_authorize,
  4219. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4220. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4221. #ifdef MESH_MODE_SUPPORT
  4222. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4223. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4224. #endif
  4225. .txrx_set_vdev_param = dp_set_vdev_param,
  4226. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4227. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4228. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4229. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4230. .txrx_update_filter_neighbour_peers =
  4231. dp_update_filter_neighbour_peers,
  4232. .txrx_get_sec_type = dp_get_sec_type,
  4233. /* TODO: Add other functions */
  4234. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4235. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4236. };
  4237. static struct cdp_me_ops dp_ops_me = {
  4238. #ifdef ATH_SUPPORT_IQUE
  4239. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4240. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4241. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4242. #endif
  4243. };
  4244. static struct cdp_mon_ops dp_ops_mon = {
  4245. .txrx_monitor_set_filter_ucast_data = NULL,
  4246. .txrx_monitor_set_filter_mcast_data = NULL,
  4247. .txrx_monitor_set_filter_non_data = NULL,
  4248. .txrx_monitor_get_filter_ucast_data = NULL,
  4249. .txrx_monitor_get_filter_mcast_data = NULL,
  4250. .txrx_monitor_get_filter_non_data = NULL,
  4251. .txrx_reset_monitor_mode = NULL,
  4252. };
  4253. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4254. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4255. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4256. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4257. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4258. /* TODO */
  4259. };
  4260. static struct cdp_raw_ops dp_ops_raw = {
  4261. /* TODO */
  4262. };
  4263. #ifdef CONFIG_WIN
  4264. static struct cdp_pflow_ops dp_ops_pflow = {
  4265. /* TODO */
  4266. };
  4267. #endif /* CONFIG_WIN */
  4268. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4269. {
  4270. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4271. struct dp_soc *soc = pdev->soc;
  4272. if (soc->intr_mode == DP_INTR_POLL)
  4273. qdf_timer_stop(&soc->int_timer);
  4274. return QDF_STATUS_SUCCESS;
  4275. }
  4276. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4277. {
  4278. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4279. struct dp_soc *soc = pdev->soc;
  4280. if (soc->intr_mode == DP_INTR_POLL)
  4281. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4282. return QDF_STATUS_SUCCESS;
  4283. }
  4284. #ifndef CONFIG_WIN
  4285. static struct cdp_misc_ops dp_ops_misc = {
  4286. .get_opmode = dp_get_opmode,
  4287. #ifdef FEATURE_RUNTIME_PM
  4288. .runtime_suspend = dp_bus_suspend,
  4289. .runtime_resume = dp_bus_resume,
  4290. #endif
  4291. };
  4292. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4293. /* WIFI 3.0 DP implement as required. */
  4294. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4295. .register_pause_cb = dp_txrx_register_pause_cb,
  4296. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4297. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4298. };
  4299. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4300. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4301. };
  4302. #ifdef IPA_OFFLOAD
  4303. static struct cdp_ipa_ops dp_ops_ipa = {
  4304. .ipa_get_resource = dp_ipa_get_resource,
  4305. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4306. .ipa_op_response = dp_ipa_op_response,
  4307. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4308. .ipa_get_stat = dp_ipa_get_stat,
  4309. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4310. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4311. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4312. .ipa_setup = dp_ipa_setup,
  4313. .ipa_cleanup = dp_ipa_cleanup,
  4314. .ipa_setup_iface = dp_ipa_setup_iface,
  4315. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4316. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4317. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4318. .ipa_set_perf_level = dp_ipa_set_perf_level
  4319. };
  4320. #endif
  4321. static struct cdp_bus_ops dp_ops_bus = {
  4322. .bus_suspend = dp_bus_suspend,
  4323. .bus_resume = dp_bus_resume
  4324. };
  4325. static struct cdp_ocb_ops dp_ops_ocb = {
  4326. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4327. };
  4328. static struct cdp_throttle_ops dp_ops_throttle = {
  4329. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4330. };
  4331. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4332. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4333. };
  4334. static struct cdp_cfg_ops dp_ops_cfg = {
  4335. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4336. };
  4337. static struct cdp_peer_ops dp_ops_peer = {
  4338. .register_peer = dp_register_peer,
  4339. .clear_peer = dp_clear_peer,
  4340. .find_peer_by_addr = dp_find_peer_by_addr,
  4341. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4342. .local_peer_id = dp_local_peer_id,
  4343. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4344. .peer_state_update = dp_peer_state_update,
  4345. .get_vdevid = dp_get_vdevid,
  4346. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4347. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4348. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4349. .get_peer_state = dp_get_peer_state,
  4350. .last_assoc_received = dp_get_last_assoc_received,
  4351. .last_disassoc_received = dp_get_last_disassoc_received,
  4352. .last_deauth_received = dp_get_last_deauth_received,
  4353. };
  4354. #endif
  4355. static struct cdp_ops dp_txrx_ops = {
  4356. .cmn_drv_ops = &dp_ops_cmn,
  4357. .ctrl_ops = &dp_ops_ctrl,
  4358. .me_ops = &dp_ops_me,
  4359. .mon_ops = &dp_ops_mon,
  4360. .host_stats_ops = &dp_ops_host_stats,
  4361. .wds_ops = &dp_ops_wds,
  4362. .raw_ops = &dp_ops_raw,
  4363. #ifdef CONFIG_WIN
  4364. .pflow_ops = &dp_ops_pflow,
  4365. #endif /* CONFIG_WIN */
  4366. #ifndef CONFIG_WIN
  4367. .misc_ops = &dp_ops_misc,
  4368. .cfg_ops = &dp_ops_cfg,
  4369. .flowctl_ops = &dp_ops_flowctl,
  4370. .l_flowctl_ops = &dp_ops_l_flowctl,
  4371. #ifdef IPA_OFFLOAD
  4372. .ipa_ops = &dp_ops_ipa,
  4373. #endif
  4374. .bus_ops = &dp_ops_bus,
  4375. .ocb_ops = &dp_ops_ocb,
  4376. .peer_ops = &dp_ops_peer,
  4377. .throttle_ops = &dp_ops_throttle,
  4378. .mob_stats_ops = &dp_ops_mob_stats,
  4379. #endif
  4380. };
  4381. /*
  4382. * dp_soc_set_txrx_ring_map()
  4383. * @dp_soc: DP handler for soc
  4384. *
  4385. * Return: Void
  4386. */
  4387. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4388. {
  4389. uint32_t i;
  4390. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4391. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4392. }
  4393. }
  4394. /*
  4395. * dp_soc_attach_wifi3() - Attach txrx SOC
  4396. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4397. * @htc_handle: Opaque HTC handle
  4398. * @hif_handle: Opaque HIF handle
  4399. * @qdf_osdev: QDF device
  4400. *
  4401. * Return: DP SOC handle on success, NULL on failure
  4402. */
  4403. /*
  4404. * Local prototype added to temporarily address warning caused by
  4405. * -Wmissing-prototypes. A more correct solution, namely to expose
  4406. * a prototype in an appropriate header file, will come later.
  4407. */
  4408. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4409. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4410. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4411. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4412. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4413. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4414. {
  4415. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4416. if (!soc) {
  4417. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4418. FL("DP SOC memory allocation failed"));
  4419. goto fail0;
  4420. }
  4421. soc->cdp_soc.ops = &dp_txrx_ops;
  4422. soc->cdp_soc.ol_ops = ol_ops;
  4423. soc->osif_soc = osif_soc;
  4424. soc->osdev = qdf_osdev;
  4425. soc->hif_handle = hif_handle;
  4426. soc->psoc = psoc;
  4427. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4428. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4429. soc->hal_soc, qdf_osdev);
  4430. if (!soc->htt_handle) {
  4431. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4432. FL("HTT attach failed"));
  4433. goto fail1;
  4434. }
  4435. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4436. if (!soc->wlan_cfg_ctx) {
  4437. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4438. FL("wlan_cfg_soc_attach failed"));
  4439. goto fail2;
  4440. }
  4441. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4442. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4443. CDP_CFG_MAX_PEER_ID);
  4444. if (ret != -EINVAL) {
  4445. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4446. }
  4447. }
  4448. qdf_spinlock_create(&soc->peer_ref_mutex);
  4449. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4450. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4451. /* fill the tx/rx cpu ring map*/
  4452. dp_soc_set_txrx_ring_map(soc);
  4453. qdf_spinlock_create(&soc->htt_stats.lock);
  4454. /* initialize work queue for stats processing */
  4455. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4456. return (void *)soc;
  4457. fail2:
  4458. htt_soc_detach(soc->htt_handle);
  4459. fail1:
  4460. qdf_mem_free(soc);
  4461. fail0:
  4462. return NULL;
  4463. }
  4464. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4465. /*
  4466. * dp_set_pktlog_wifi3() - attach txrx vdev
  4467. * @pdev: Datapath PDEV handle
  4468. * @event: which event's notifications are being subscribed to
  4469. * @enable: WDI event subscribe or not. (True or False)
  4470. *
  4471. * Return: Success, NULL on failure
  4472. */
  4473. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4474. bool enable)
  4475. {
  4476. struct dp_soc *soc = pdev->soc;
  4477. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4478. if (enable) {
  4479. switch (event) {
  4480. case WDI_EVENT_RX_DESC:
  4481. if (pdev->monitor_vdev) {
  4482. /* Nothing needs to be done if monitor mode is
  4483. * enabled
  4484. */
  4485. return 0;
  4486. }
  4487. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4488. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4489. htt_tlv_filter.mpdu_start = 1;
  4490. htt_tlv_filter.msdu_start = 1;
  4491. htt_tlv_filter.msdu_end = 1;
  4492. htt_tlv_filter.mpdu_end = 1;
  4493. htt_tlv_filter.packet_header = 1;
  4494. htt_tlv_filter.attention = 1;
  4495. htt_tlv_filter.ppdu_start = 1;
  4496. htt_tlv_filter.ppdu_end = 1;
  4497. htt_tlv_filter.ppdu_end_user_stats = 1;
  4498. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4499. htt_tlv_filter.ppdu_end_status_done = 1;
  4500. htt_tlv_filter.enable_fp = 1;
  4501. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4502. pdev->pdev_id,
  4503. pdev->rxdma_mon_status_ring.hal_srng,
  4504. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4505. &htt_tlv_filter);
  4506. }
  4507. break;
  4508. case WDI_EVENT_LITE_RX:
  4509. if (pdev->monitor_vdev) {
  4510. /* Nothing needs to be done if monitor mode is
  4511. * enabled
  4512. */
  4513. return 0;
  4514. }
  4515. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4516. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4517. htt_tlv_filter.ppdu_start = 1;
  4518. htt_tlv_filter.ppdu_end = 1;
  4519. htt_tlv_filter.ppdu_end_user_stats = 1;
  4520. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4521. htt_tlv_filter.ppdu_end_status_done = 1;
  4522. htt_tlv_filter.enable_fp = 1;
  4523. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4524. pdev->pdev_id,
  4525. pdev->rxdma_mon_status_ring.hal_srng,
  4526. RXDMA_MONITOR_STATUS,
  4527. RX_BUFFER_SIZE_PKTLOG_LITE,
  4528. &htt_tlv_filter);
  4529. }
  4530. break;
  4531. case WDI_EVENT_LITE_T2H:
  4532. if (pdev->monitor_vdev) {
  4533. /* Nothing needs to be done if monitor mode is
  4534. * enabled
  4535. */
  4536. return 0;
  4537. }
  4538. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4539. * passing value 0xffff. Once these macros will define in htt
  4540. * header file will use proper macros
  4541. */
  4542. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4543. break;
  4544. default:
  4545. /* Nothing needs to be done for other pktlog types */
  4546. break;
  4547. }
  4548. } else {
  4549. switch (event) {
  4550. case WDI_EVENT_RX_DESC:
  4551. case WDI_EVENT_LITE_RX:
  4552. if (pdev->monitor_vdev) {
  4553. /* Nothing needs to be done if monitor mode is
  4554. * enabled
  4555. */
  4556. return 0;
  4557. }
  4558. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4559. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4560. /* htt_tlv_filter is initialized to 0 */
  4561. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4562. pdev->pdev_id,
  4563. pdev->rxdma_mon_status_ring.hal_srng,
  4564. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4565. &htt_tlv_filter);
  4566. }
  4567. break;
  4568. case WDI_EVENT_LITE_T2H:
  4569. if (pdev->monitor_vdev) {
  4570. /* Nothing needs to be done if monitor mode is
  4571. * enabled
  4572. */
  4573. return 0;
  4574. }
  4575. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4576. * passing value 0. Once these macros will define in htt
  4577. * header file will use proper macros
  4578. */
  4579. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4580. break;
  4581. default:
  4582. /* Nothing needs to be done for other pktlog types */
  4583. break;
  4584. }
  4585. }
  4586. return 0;
  4587. }
  4588. #endif