lpass-cdc-tx-macro.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/clk.h>
  8. #include <linux/io.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/pm_runtime.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dapm.h>
  14. #include <sound/tlv.h>
  15. #include <asoc/msm-cdc-pinctrl.h>
  16. #include "lpass-cdc.h"
  17. #include "lpass-cdc-registers.h"
  18. #include "lpass-cdc-clk-rsc.h"
  19. #if IS_ENABLED(CONFIG_SND_SOC_SAMSUNG_AUDIO)
  20. #include <sound/samsung/snd_debug_proc.h>
  21. #endif
  22. #define AUTO_SUSPEND_DELAY 50 /* delay in msec */
  23. #define LPASS_CDC_TX_MACRO_MAX_OFFSET 0x1000
  24. #define NUM_DECIMATORS 8
  25. #define LPASS_CDC_TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  26. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  27. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  28. #define LPASS_CDC_TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  29. SNDRV_PCM_FMTBIT_S24_LE |\
  30. SNDRV_PCM_FMTBIT_S24_3LE)
  31. #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
  32. #define CF_MIN_3DB_4HZ 0x0
  33. #define CF_MIN_3DB_75HZ 0x1
  34. #define CF_MIN_3DB_150HZ 0x2
  35. #define LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0
  36. #define LPASS_CDC_TX_MACRO_MCLK_FREQ 9600000
  37. #define LPASS_CDC_TX_MACRO_TX_PATH_OFFSET \
  38. (LPASS_CDC_TX1_TX_PATH_CTL - LPASS_CDC_TX0_TX_PATH_CTL)
  39. #define LPASS_CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
  40. #define LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET 0x8
  41. #define LPASS_CDC_TX_MACRO_ADC_MODE_CFG0_SHIFT 1
  42. #define LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
  43. #define LPASS_CDC_TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
  44. #define LPASS_CDC_TX_MACRO_DMIC_HPF_DELAY_MS 300
  45. #define LPASS_CDC_TX_MACRO_AMIC_HPF_DELAY_MS 300
  46. static int tx_unmute_delay = LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS;
  47. module_param(tx_unmute_delay, int, 0664);
  48. MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path");
  49. static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
  50. static int lpass_cdc_tx_macro_hw_params(struct snd_pcm_substream *substream,
  51. struct snd_pcm_hw_params *params,
  52. struct snd_soc_dai *dai);
  53. static int lpass_cdc_tx_macro_get_channel_map(struct snd_soc_dai *dai,
  54. unsigned int *tx_num, unsigned int *tx_slot,
  55. unsigned int *rx_num, unsigned int *rx_slot);
  56. #define LPASS_CDC_TX_MACRO_SWR_STRING_LEN 80
  57. #define LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX 3
  58. enum {
  59. LPASS_CDC_TX_MACRO_AIF_INVALID = 0,
  60. LPASS_CDC_TX_MACRO_AIF1_CAP,
  61. LPASS_CDC_TX_MACRO_AIF2_CAP,
  62. LPASS_CDC_TX_MACRO_AIF3_CAP,
  63. LPASS_CDC_TX_MACRO_MAX_DAIS
  64. };
  65. enum {
  66. LPASS_CDC_TX_MACRO_DEC0,
  67. LPASS_CDC_TX_MACRO_DEC1,
  68. LPASS_CDC_TX_MACRO_DEC2,
  69. LPASS_CDC_TX_MACRO_DEC3,
  70. LPASS_CDC_TX_MACRO_DEC4,
  71. LPASS_CDC_TX_MACRO_DEC5,
  72. LPASS_CDC_TX_MACRO_DEC6,
  73. LPASS_CDC_TX_MACRO_DEC7,
  74. LPASS_CDC_TX_MACRO_DEC_MAX,
  75. };
  76. enum {
  77. LPASS_CDC_TX_MACRO_CLK_DIV_2,
  78. LPASS_CDC_TX_MACRO_CLK_DIV_3,
  79. LPASS_CDC_TX_MACRO_CLK_DIV_4,
  80. LPASS_CDC_TX_MACRO_CLK_DIV_6,
  81. LPASS_CDC_TX_MACRO_CLK_DIV_8,
  82. LPASS_CDC_TX_MACRO_CLK_DIV_16,
  83. };
  84. enum {
  85. MSM_DMIC,
  86. SWR_MIC,
  87. ANC_FB_TUNE1
  88. };
  89. enum {
  90. TX_MCLK,
  91. VA_MCLK,
  92. };
  93. /* Based on 9.6MHZ MCLK Freq */
  94. enum {
  95. CLK_DISABLED = 0,
  96. CLK_2P4MHZ,
  97. CLK_0P6MHZ,
  98. };
  99. static int dmic_clk_rate_div[] = {
  100. [CLK_DISABLED] = 0,
  101. [CLK_2P4MHZ] = LPASS_CDC_TX_MACRO_CLK_DIV_4,
  102. [CLK_0P6MHZ] = LPASS_CDC_TX_MACRO_CLK_DIV_16,
  103. };
  104. struct lpass_cdc_tx_macro_reg_mask_val {
  105. u16 reg;
  106. u8 mask;
  107. u8 val;
  108. };
  109. struct tx_mute_work {
  110. struct lpass_cdc_tx_macro_priv *tx_priv;
  111. u32 decimator;
  112. struct delayed_work dwork;
  113. };
  114. struct hpf_work {
  115. struct lpass_cdc_tx_macro_priv *tx_priv;
  116. u8 decimator;
  117. u8 hpf_cut_off_freq;
  118. struct delayed_work dwork;
  119. };
  120. struct lpass_cdc_tx_macro_priv {
  121. struct device *dev;
  122. bool dec_active[NUM_DECIMATORS];
  123. int tx_mclk_users;
  124. bool dapm_mclk_enable;
  125. struct mutex mclk_lock;
  126. struct mutex wlock;
  127. struct snd_soc_component *component;
  128. struct hpf_work tx_hpf_work[NUM_DECIMATORS];
  129. struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
  130. u16 dmic_clk_div;
  131. u32 version;
  132. unsigned long active_ch_mask[LPASS_CDC_TX_MACRO_MAX_DAIS];
  133. unsigned long active_ch_cnt[LPASS_CDC_TX_MACRO_MAX_DAIS];
  134. char __iomem *tx_io_base;
  135. struct platform_device *pdev_child_devices
  136. [LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX];
  137. int child_count;
  138. bool bcs_enable;
  139. int dec_mode[NUM_DECIMATORS];
  140. int bcs_ch;
  141. bool bcs_clk_en;
  142. bool hs_slow_insert_complete;
  143. int pcm_rate[NUM_DECIMATORS];
  144. bool swr_dmic_enable;
  145. int wlock_holders;
  146. u32 dmic_rate_override;
  147. };
  148. static const char* const dmic_rate_override_text[] = {
  149. "DISABLED", "CLK_2P4MHZ", "CLK_0P6MHZ"
  150. };
  151. static SOC_ENUM_SINGLE_EXT_DECL(dmic_rate_enum, dmic_rate_override_text);
  152. static int lpass_cdc_tx_macro_wake_enable(struct lpass_cdc_tx_macro_priv *tx_priv,
  153. bool wake_enable)
  154. {
  155. int ret = 0;
  156. mutex_lock(&tx_priv->wlock);
  157. if (wake_enable) {
  158. if (tx_priv->wlock_holders++ == 0) {
  159. dev_dbg(tx_priv->dev, "%s: pm wake\n", __func__);
  160. pm_stay_awake(tx_priv->dev);
  161. }
  162. } else {
  163. if (--tx_priv->wlock_holders == 0) {
  164. dev_dbg(tx_priv->dev, "%s: pm release\n", __func__);
  165. pm_relax(tx_priv->dev);
  166. }
  167. if (tx_priv->wlock_holders < 0)
  168. tx_priv->wlock_holders = 0;
  169. }
  170. mutex_unlock(&tx_priv->wlock);
  171. return ret;
  172. }
  173. static bool lpass_cdc_tx_macro_get_data(struct snd_soc_component *component,
  174. struct device **tx_dev,
  175. struct lpass_cdc_tx_macro_priv **tx_priv,
  176. const char *func_name)
  177. {
  178. *tx_dev = lpass_cdc_get_device_ptr(component->dev, TX_MACRO);
  179. if (!(*tx_dev)) {
  180. dev_err_ratelimited(component->dev,
  181. "%s: null device for macro!\n", func_name);
  182. return false;
  183. }
  184. *tx_priv = dev_get_drvdata((*tx_dev));
  185. if (!(*tx_priv)) {
  186. dev_err_ratelimited(component->dev,
  187. "%s: priv is null for macro!\n", func_name);
  188. return false;
  189. }
  190. if (!(*tx_priv)->component) {
  191. dev_err_ratelimited(component->dev,
  192. "%s: tx_priv->component not initialized!\n", func_name);
  193. return false;
  194. }
  195. return true;
  196. }
  197. static int lpass_cdc_dmic_rate_override_get(struct snd_kcontrol *kcontrol,
  198. struct snd_ctl_elem_value *ucontrol)
  199. {
  200. struct snd_soc_component *component =
  201. snd_soc_kcontrol_component(kcontrol);
  202. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  203. struct device *tx_dev = NULL;
  204. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  205. return -EINVAL;
  206. ucontrol->value.enumerated.item[0] = tx_priv->dmic_rate_override;
  207. dev_dbg(component->dev, "%s: dmic rate: %d\n",
  208. __func__, tx_priv->dmic_rate_override);
  209. return 0;
  210. }
  211. static int lpass_cdc_dmic_rate_override_put(struct snd_kcontrol *kcontrol,
  212. struct snd_ctl_elem_value *ucontrol)
  213. {
  214. struct snd_soc_component *component =
  215. snd_soc_kcontrol_component(kcontrol);
  216. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  217. struct device *tx_dev = NULL;
  218. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  219. return -EINVAL;
  220. tx_priv->dmic_rate_override = ucontrol->value.enumerated.item[0];
  221. dev_dbg(component->dev, "%s: dmic rate: %d\n",
  222. __func__, tx_priv->dmic_rate_override);
  223. return 0;
  224. }
  225. static int lpass_cdc_tx_macro_mclk_enable(
  226. struct lpass_cdc_tx_macro_priv *tx_priv,
  227. bool mclk_enable)
  228. {
  229. struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL);
  230. int ret = 0, rc = 0;
  231. if (regmap == NULL) {
  232. dev_err_ratelimited(tx_priv->dev, "%s: regmap is NULL\n", __func__);
  233. return -EINVAL;
  234. }
  235. dev_info(tx_priv->dev, "%s: mclk_enable = %u,clk_users= %d\n",
  236. __func__, mclk_enable, tx_priv->tx_mclk_users);
  237. mutex_lock(&tx_priv->mclk_lock);
  238. if (mclk_enable) {
  239. ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev,
  240. TX_CORE_CLK,
  241. TX_CORE_CLK,
  242. true);
  243. if (ret < 0) {
  244. dev_err_ratelimited(tx_priv->dev,
  245. "%s: request clock enable failed\n",
  246. __func__);
  247. goto exit;
  248. }
  249. lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev,
  250. true);
  251. regcache_mark_dirty(regmap);
  252. ret = regcache_sync_region(regmap,
  253. TX_START_OFFSET,
  254. TX_MAX_OFFSET);
  255. if (ret < 0) {
  256. dev_err_ratelimited(tx_priv->dev,
  257. "%s: regcache_sync_region failed\n",
  258. __func__);
  259. #if IS_ENABLED(CONFIG_SND_SOC_SAMSUNG_AUDIO)
  260. sdp_info_print("%s: regcache_sync_region failed\n",
  261. __func__);
  262. #endif
  263. lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev,
  264. false);
  265. lpass_cdc_clk_rsc_request_clock(tx_priv->dev,
  266. TX_CORE_CLK,
  267. TX_CORE_CLK,
  268. false);
  269. goto exit;
  270. }
  271. if (tx_priv->tx_mclk_users == 0) {
  272. rc = (rc | regmap_update_bits(regmap,
  273. LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
  274. 0x01, 0x01));
  275. rc = (rc | regmap_update_bits(regmap,
  276. LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
  277. 0x01, 0x01));
  278. }
  279. tx_priv->tx_mclk_users++;
  280. } else {
  281. if (tx_priv->tx_mclk_users <= 0) {
  282. dev_err_ratelimited(tx_priv->dev, "%s: clock already disabled\n",
  283. __func__);
  284. tx_priv->tx_mclk_users = 0;
  285. goto exit;
  286. }
  287. tx_priv->tx_mclk_users--;
  288. if (tx_priv->tx_mclk_users == 0) {
  289. rc = (rc | regmap_update_bits(regmap,
  290. LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
  291. 0x01, 0x00));
  292. rc = (rc | regmap_update_bits(regmap,
  293. LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
  294. 0x01, 0x00));
  295. }
  296. if (rc < 0) {
  297. dev_err_ratelimited(tx_priv->dev, "%s: register writes failed\n",
  298. __func__);
  299. #if IS_ENABLED(CONFIG_SND_SOC_SAMSUNG_AUDIO)
  300. sdp_info_print("%s: register writes failed\n",
  301. __func__);
  302. #endif
  303. }
  304. lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev,
  305. false);
  306. ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev,
  307. TX_CORE_CLK,
  308. TX_CORE_CLK,
  309. false);
  310. }
  311. exit:
  312. mutex_unlock(&tx_priv->mclk_lock);
  313. return ret;
  314. }
  315. static int __lpass_cdc_tx_macro_mclk_enable(struct snd_soc_component *component,
  316. bool enable)
  317. {
  318. struct device *tx_dev = NULL;
  319. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  320. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  321. return -EINVAL;
  322. return lpass_cdc_tx_macro_mclk_enable(tx_priv, enable);
  323. }
  324. static int lpass_cdc_tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
  325. struct snd_kcontrol *kcontrol, int event)
  326. {
  327. struct snd_soc_component *component =
  328. snd_soc_dapm_to_component(w->dapm);
  329. int ret = 0;
  330. struct device *tx_dev = NULL;
  331. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  332. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  333. return -EINVAL;
  334. dev_dbg(tx_dev, "%s: event = %d\n", __func__, event);
  335. switch (event) {
  336. case SND_SOC_DAPM_PRE_PMU:
  337. ret = lpass_cdc_tx_macro_mclk_enable(tx_priv, 1);
  338. if (ret)
  339. tx_priv->dapm_mclk_enable = false;
  340. else
  341. tx_priv->dapm_mclk_enable = true;
  342. break;
  343. case SND_SOC_DAPM_POST_PMD:
  344. if (tx_priv->dapm_mclk_enable)
  345. ret = lpass_cdc_tx_macro_mclk_enable(tx_priv, 0);
  346. break;
  347. default:
  348. dev_err_ratelimited(tx_priv->dev,
  349. "%s: invalid DAPM event %d\n", __func__, event);
  350. ret = -EINVAL;
  351. }
  352. return ret;
  353. }
  354. static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component,
  355. u16 event, u32 data)
  356. {
  357. struct device *tx_dev = NULL;
  358. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  359. int ret = 0;
  360. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  361. return -EINVAL;
  362. switch (event) {
  363. case LPASS_CDC_MACRO_EVT_SSR_DOWN:
  364. if ((!pm_runtime_enabled(tx_dev) ||
  365. !pm_runtime_suspended(tx_dev))) {
  366. ret = lpass_cdc_runtime_suspend(tx_dev);
  367. if (!ret) {
  368. pm_runtime_disable(tx_dev);
  369. pm_runtime_set_suspended(tx_dev);
  370. pm_runtime_enable(tx_dev);
  371. }
  372. }
  373. break;
  374. case LPASS_CDC_MACRO_EVT_SSR_UP:
  375. break;
  376. case LPASS_CDC_MACRO_EVT_CLK_RESET:
  377. lpass_cdc_rsc_clk_reset(tx_dev, TX_CORE_CLK);
  378. break;
  379. case LPASS_CDC_MACRO_EVT_BCS_CLK_OFF:
  380. if (tx_priv->bcs_clk_en)
  381. snd_soc_component_update_bits(component,
  382. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, data << 6);
  383. if (data)
  384. tx_priv->hs_slow_insert_complete = true;
  385. else
  386. tx_priv->hs_slow_insert_complete = false;
  387. break;
  388. default:
  389. pr_debug("%s Invalid Event\n", __func__);
  390. break;
  391. }
  392. return 0;
  393. }
  394. static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
  395. {
  396. u16 adc_mux_reg = 0;
  397. bool ret = false;
  398. struct device *tx_dev = NULL;
  399. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  400. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  401. return ret;
  402. adc_mux_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  403. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  404. if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
  405. if (!tx_priv->swr_dmic_enable)
  406. return true;
  407. }
  408. return ret;
  409. }
  410. static void lpass_cdc_tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
  411. {
  412. struct delayed_work *hpf_delayed_work = NULL;
  413. struct hpf_work *hpf_work = NULL;
  414. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  415. struct snd_soc_component *component = NULL;
  416. u16 dec_cfg_reg = 0, hpf_gate_reg = 0;
  417. u8 hpf_cut_off_freq = 0;
  418. u16 adc_reg = 0, adc_n = 0;
  419. hpf_delayed_work = to_delayed_work(work);
  420. hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
  421. tx_priv = hpf_work->tx_priv;
  422. component = tx_priv->component;
  423. hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
  424. dec_cfg_reg = LPASS_CDC_TX0_TX_PATH_CFG0 +
  425. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  426. hpf_gate_reg = LPASS_CDC_TX0_TX_PATH_SEC2 +
  427. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  428. dev_dbg(component->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",
  429. __func__, hpf_work->decimator, hpf_cut_off_freq);
  430. if (is_amic_enabled(component, hpf_work->decimator)) {
  431. adc_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  432. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * hpf_work->decimator;
  433. adc_n = snd_soc_component_read(component, adc_reg) &
  434. LPASS_CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
  435. /* analog mic clear TX hold */
  436. lpass_cdc_clear_amic_tx_hold(component->dev, adc_n);
  437. snd_soc_component_update_bits(component,
  438. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  439. hpf_cut_off_freq << 5);
  440. snd_soc_component_update_bits(component, hpf_gate_reg,
  441. 0x03, 0x02);
  442. /* Add delay between toggle hpf gate based on sample rate */
  443. switch (tx_priv->pcm_rate[hpf_work->decimator]) {
  444. case 0:
  445. usleep_range(125, 130);
  446. break;
  447. case 1:
  448. usleep_range(62, 65);
  449. break;
  450. case 3:
  451. usleep_range(31, 32);
  452. break;
  453. case 4:
  454. usleep_range(20, 21);
  455. break;
  456. case 5:
  457. usleep_range(10, 11);
  458. break;
  459. case 6:
  460. usleep_range(5, 6);
  461. break;
  462. default:
  463. usleep_range(125, 130);
  464. }
  465. snd_soc_component_update_bits(component, hpf_gate_reg,
  466. 0x03, 0x01);
  467. } else {
  468. snd_soc_component_update_bits(component,
  469. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  470. hpf_cut_off_freq << 5);
  471. snd_soc_component_update_bits(component, hpf_gate_reg,
  472. 0x02, 0x02);
  473. /* Minimum 1 clk cycle delay is required as per HW spec */
  474. usleep_range(1000, 1010);
  475. snd_soc_component_update_bits(component, hpf_gate_reg,
  476. 0x02, 0x00);
  477. }
  478. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  479. }
  480. static void lpass_cdc_tx_macro_mute_update_callback(struct work_struct *work)
  481. {
  482. struct tx_mute_work *tx_mute_dwork = NULL;
  483. struct snd_soc_component *component = NULL;
  484. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  485. struct delayed_work *delayed_work = NULL;
  486. u16 tx_vol_ctl_reg = 0;
  487. u8 decimator = 0;
  488. delayed_work = to_delayed_work(work);
  489. tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
  490. tx_priv = tx_mute_dwork->tx_priv;
  491. component = tx_priv->component;
  492. decimator = tx_mute_dwork->decimator;
  493. tx_vol_ctl_reg =
  494. LPASS_CDC_TX0_TX_PATH_CTL +
  495. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  496. snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x10, 0x00);
  497. dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n",
  498. __func__, decimator);
  499. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  500. }
  501. static int lpass_cdc_tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
  502. struct snd_ctl_elem_value *ucontrol)
  503. {
  504. struct snd_soc_dapm_widget *widget =
  505. snd_soc_dapm_kcontrol_widget(kcontrol);
  506. struct snd_soc_component *component =
  507. snd_soc_dapm_to_component(widget->dapm);
  508. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  509. unsigned int val = 0;
  510. u16 mic_sel_reg = 0;
  511. u16 dmic_clk_reg = 0;
  512. struct device *tx_dev = NULL;
  513. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  514. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  515. return -EINVAL;
  516. val = ucontrol->value.enumerated.item[0];
  517. if (val > e->items - 1)
  518. return -EINVAL;
  519. dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__,
  520. widget->name, val);
  521. switch (e->reg) {
  522. case LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0:
  523. mic_sel_reg = LPASS_CDC_TX0_TX_PATH_CFG0;
  524. break;
  525. case LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0:
  526. mic_sel_reg = LPASS_CDC_TX1_TX_PATH_CFG0;
  527. break;
  528. case LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0:
  529. mic_sel_reg = LPASS_CDC_TX2_TX_PATH_CFG0;
  530. break;
  531. case LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0:
  532. mic_sel_reg = LPASS_CDC_TX3_TX_PATH_CFG0;
  533. break;
  534. case LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
  535. mic_sel_reg = LPASS_CDC_TX4_TX_PATH_CFG0;
  536. break;
  537. case LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
  538. mic_sel_reg = LPASS_CDC_TX5_TX_PATH_CFG0;
  539. break;
  540. case LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
  541. mic_sel_reg = LPASS_CDC_TX6_TX_PATH_CFG0;
  542. break;
  543. case LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
  544. mic_sel_reg = LPASS_CDC_TX7_TX_PATH_CFG0;
  545. break;
  546. default:
  547. dev_err_ratelimited(component->dev, "%s: e->reg: 0x%x not expected\n",
  548. __func__, e->reg);
  549. return -EINVAL;
  550. }
  551. if (strnstr(widget->name, "SMIC", strlen(widget->name))) {
  552. if (val != 0) {
  553. if (!tx_priv->swr_dmic_enable) {
  554. snd_soc_component_update_bits(component,
  555. mic_sel_reg,
  556. 1 << 7, 0x0 << 7);
  557. } else {
  558. snd_soc_component_update_bits(component,
  559. mic_sel_reg,
  560. 1 << 7, 0x1 << 7);
  561. snd_soc_component_update_bits(component,
  562. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  563. 0x80, 0x00);
  564. dmic_clk_reg =
  565. LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL +
  566. ((val - 5)/2) * 4;
  567. snd_soc_component_update_bits(component,
  568. dmic_clk_reg,
  569. 0x0E, tx_priv->dmic_clk_div << 0x1);
  570. }
  571. }
  572. } else {
  573. /* DMIC selected */
  574. if (val != 0)
  575. snd_soc_component_update_bits(component, mic_sel_reg,
  576. 1 << 7, 1 << 7);
  577. }
  578. return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  579. }
  580. static int lpass_cdc_tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
  581. struct snd_ctl_elem_value *ucontrol)
  582. {
  583. struct snd_soc_dapm_widget *widget =
  584. snd_soc_dapm_kcontrol_widget(kcontrol);
  585. struct snd_soc_component *component =
  586. snd_soc_dapm_to_component(widget->dapm);
  587. struct soc_multi_mixer_control *mixer =
  588. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  589. u32 dai_id = widget->shift;
  590. u32 dec_id = mixer->shift;
  591. struct device *tx_dev = NULL;
  592. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  593. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  594. return -EINVAL;
  595. if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id]))
  596. ucontrol->value.integer.value[0] = 1;
  597. else
  598. ucontrol->value.integer.value[0] = 0;
  599. return 0;
  600. }
  601. static int lpass_cdc_tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
  602. struct snd_ctl_elem_value *ucontrol)
  603. {
  604. struct snd_soc_dapm_widget *widget =
  605. snd_soc_dapm_kcontrol_widget(kcontrol);
  606. struct snd_soc_component *component =
  607. snd_soc_dapm_to_component(widget->dapm);
  608. struct snd_soc_dapm_update *update = NULL;
  609. struct soc_multi_mixer_control *mixer =
  610. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  611. u32 dai_id = widget->shift;
  612. u32 dec_id = mixer->shift;
  613. u32 enable = ucontrol->value.integer.value[0];
  614. struct device *tx_dev = NULL;
  615. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  616. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  617. return -EINVAL;
  618. if (enable) {
  619. if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) {
  620. dev_err(component->dev, "%s: channel is already enabled, dec_id = %d, dai_id = %d\n",
  621. __func__, dec_id, dai_id);
  622. } else {
  623. set_bit(dec_id, &tx_priv->active_ch_mask[dai_id]);
  624. tx_priv->active_ch_cnt[dai_id]++;
  625. }
  626. } else {
  627. if (!test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) {
  628. dev_err(component->dev, "%s: channel is already disabled, dec_id = %d, dai_id = %d\n",
  629. __func__, dec_id, dai_id);
  630. } else {
  631. tx_priv->active_ch_cnt[dai_id]--;
  632. clear_bit(dec_id, &tx_priv->active_ch_mask[dai_id]);
  633. }
  634. }
  635. snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
  636. return 0;
  637. }
  638. static inline int lpass_cdc_tx_macro_path_get(const char *wname,
  639. unsigned int *path_num)
  640. {
  641. int ret = 0;
  642. char *widget_name = NULL;
  643. char *w_name = NULL;
  644. char *path_num_char = NULL;
  645. char *path_name = NULL;
  646. widget_name = kstrndup(wname, 10, GFP_KERNEL);
  647. if (!widget_name)
  648. return -EINVAL;
  649. w_name = widget_name;
  650. path_name = strsep(&widget_name, " ");
  651. if (!path_name) {
  652. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  653. __func__, widget_name);
  654. ret = -EINVAL;
  655. goto err;
  656. }
  657. path_num_char = strpbrk(path_name, "01234567");
  658. if (!path_num_char) {
  659. pr_err_ratelimited("%s: tx path index not found\n",
  660. __func__);
  661. ret = -EINVAL;
  662. goto err;
  663. }
  664. ret = kstrtouint(path_num_char, 10, path_num);
  665. if (ret < 0)
  666. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  667. __func__, w_name);
  668. err:
  669. kfree(w_name);
  670. return ret;
  671. }
  672. static int lpass_cdc_tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
  673. struct snd_ctl_elem_value *ucontrol)
  674. {
  675. struct snd_soc_component *component =
  676. snd_soc_kcontrol_component(kcontrol);
  677. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  678. struct device *tx_dev = NULL;
  679. int ret = 0;
  680. int path = 0;
  681. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  682. return -EINVAL;
  683. ret = lpass_cdc_tx_macro_path_get(kcontrol->id.name, &path);
  684. if (ret)
  685. return ret;
  686. ucontrol->value.integer.value[0] = tx_priv->dec_mode[path];
  687. return 0;
  688. }
  689. static int lpass_cdc_tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
  690. struct snd_ctl_elem_value *ucontrol)
  691. {
  692. struct snd_soc_component *component =
  693. snd_soc_kcontrol_component(kcontrol);
  694. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  695. struct device *tx_dev = NULL;
  696. int value = ucontrol->value.integer.value[0];
  697. int ret = 0;
  698. int path = 0;
  699. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  700. return -EINVAL;
  701. ret = lpass_cdc_tx_macro_path_get(kcontrol->id.name, &path);
  702. if (ret)
  703. return ret;
  704. tx_priv->dec_mode[path] = value;
  705. return 0;
  706. }
  707. static int lpass_cdc_tx_macro_bcs_ch_get(struct snd_kcontrol *kcontrol,
  708. struct snd_ctl_elem_value *ucontrol)
  709. {
  710. struct snd_soc_component *component =
  711. snd_soc_kcontrol_component(kcontrol);
  712. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  713. struct device *tx_dev = NULL;
  714. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  715. return -EINVAL;
  716. ucontrol->value.enumerated.item[0] = tx_priv->bcs_ch;
  717. return 0;
  718. }
  719. static int lpass_cdc_tx_macro_bcs_ch_put(struct snd_kcontrol *kcontrol,
  720. struct snd_ctl_elem_value *ucontrol)
  721. {
  722. struct snd_soc_component *component =
  723. snd_soc_kcontrol_component(kcontrol);
  724. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  725. struct device *tx_dev = NULL;
  726. int value = ucontrol->value.enumerated.item[0];
  727. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  728. return -EINVAL;
  729. tx_priv->bcs_ch = value;
  730. return 0;
  731. }
  732. static int lpass_cdc_tx_macro_swr_dmic_get(struct snd_kcontrol *kcontrol,
  733. struct snd_ctl_elem_value *ucontrol)
  734. {
  735. struct snd_soc_component *component =
  736. snd_soc_kcontrol_component(kcontrol);
  737. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  738. struct device *tx_dev = NULL;
  739. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  740. return -EINVAL;
  741. ucontrol->value.integer.value[0] = tx_priv->swr_dmic_enable;
  742. return 0;
  743. }
  744. static int lpass_cdc_tx_macro_swr_dmic_put(struct snd_kcontrol *kcontrol,
  745. struct snd_ctl_elem_value *ucontrol)
  746. {
  747. struct snd_soc_component *component =
  748. snd_soc_kcontrol_component(kcontrol);
  749. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  750. struct device *tx_dev = NULL;
  751. int value = ucontrol->value.integer.value[0];
  752. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  753. return -EINVAL;
  754. tx_priv->swr_dmic_enable = value;
  755. return 0;
  756. }
  757. static int lpass_cdc_tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
  758. struct snd_ctl_elem_value *ucontrol)
  759. {
  760. struct snd_soc_component *component =
  761. snd_soc_kcontrol_component(kcontrol);
  762. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  763. struct device *tx_dev = NULL;
  764. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  765. return -EINVAL;
  766. ucontrol->value.integer.value[0] = tx_priv->bcs_enable;
  767. return 0;
  768. }
  769. static int lpass_cdc_tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
  770. struct snd_ctl_elem_value *ucontrol)
  771. {
  772. struct snd_soc_component *component =
  773. snd_soc_kcontrol_component(kcontrol);
  774. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  775. struct device *tx_dev = NULL;
  776. int value = ucontrol->value.integer.value[0];
  777. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  778. return -EINVAL;
  779. tx_priv->bcs_enable = value;
  780. return 0;
  781. }
  782. static const char * const bcs_ch_sel_mux_text[] = {
  783. "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
  784. "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
  785. "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11",
  786. };
  787. static const struct soc_enum bcs_ch_sel_mux_enum =
  788. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(bcs_ch_sel_mux_text),
  789. bcs_ch_sel_mux_text);
  790. static int lpass_cdc_tx_macro_get_bcs_ch_sel(struct snd_kcontrol *kcontrol,
  791. struct snd_ctl_elem_value *ucontrol)
  792. {
  793. struct snd_soc_component *component =
  794. snd_soc_kcontrol_component(kcontrol);
  795. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  796. struct device *tx_dev = NULL;
  797. int value = 0;
  798. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  799. return -EINVAL;
  800. value = (snd_soc_component_read(component,
  801. LPASS_CDC_VA_TOP_CSR_SWR_CTRL)) & 0x0F;
  802. ucontrol->value.integer.value[0] = value;
  803. return 0;
  804. }
  805. static int lpass_cdc_tx_macro_put_bcs_ch_sel(struct snd_kcontrol *kcontrol,
  806. struct snd_ctl_elem_value *ucontrol)
  807. {
  808. struct snd_soc_component *component =
  809. snd_soc_kcontrol_component(kcontrol);
  810. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  811. struct device *tx_dev = NULL;
  812. int value;
  813. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  814. return -EINVAL;
  815. if (ucontrol->value.integer.value[0] < 0 ||
  816. ucontrol->value.integer.value[0] > ARRAY_SIZE(bcs_ch_sel_mux_text))
  817. return -EINVAL;
  818. value = ucontrol->value.integer.value[0];
  819. snd_soc_component_update_bits(component,
  820. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F, value);
  821. return 0;
  822. }
  823. static int lpass_cdc_tx_macro_enable_dmic(struct snd_soc_dapm_widget *w,
  824. struct snd_kcontrol *kcontrol, int event, u16 adc_mux0_cfg)
  825. {
  826. struct snd_soc_component *component =
  827. snd_soc_dapm_to_component(w->dapm);
  828. unsigned int dmic = 0;
  829. dmic = (snd_soc_component_read(component, adc_mux0_cfg) >> 4) - 1;
  830. dev_dbg(component->dev, "%s: event %d DMIC%d\n",
  831. __func__, event, dmic);
  832. switch (event) {
  833. case SND_SOC_DAPM_PRE_PMU:
  834. lpass_cdc_dmic_clk_enable(component, dmic, DMIC_TX, true);
  835. break;
  836. case SND_SOC_DAPM_POST_PMD:
  837. lpass_cdc_dmic_clk_enable(component, dmic, DMIC_TX, false);
  838. break;
  839. }
  840. return 0;
  841. }
  842. static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
  843. struct snd_kcontrol *kcontrol, int event)
  844. {
  845. struct snd_soc_component *component =
  846. snd_soc_dapm_to_component(w->dapm);
  847. unsigned int decimator = 0;
  848. u16 tx_vol_ctl_reg = 0;
  849. u16 dec_cfg_reg = 0;
  850. u16 hpf_gate_reg = 0;
  851. u16 tx_gain_ctl_reg = 0;
  852. u16 tx_fs_reg = 0;
  853. u8 hpf_cut_off_freq = 0;
  854. u16 adc_mux_reg = 0;
  855. u16 adc_mux0_reg = 0;
  856. int hpf_delay = LPASS_CDC_TX_MACRO_DMIC_HPF_DELAY_MS;
  857. int unmute_delay = LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS;
  858. struct device *tx_dev = NULL;
  859. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  860. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  861. return -EINVAL;
  862. decimator = w->shift;
  863. dev_dbg(component->dev, "%s(): widget = %s decimator = %u\n", __func__,
  864. w->name, decimator);
  865. tx_vol_ctl_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  866. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  867. hpf_gate_reg = LPASS_CDC_TX0_TX_PATH_SEC2 +
  868. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  869. dec_cfg_reg = LPASS_CDC_TX0_TX_PATH_CFG0 +
  870. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  871. tx_gain_ctl_reg = LPASS_CDC_TX0_TX_VOL_CTL +
  872. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  873. adc_mux_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  874. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  875. adc_mux0_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  876. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  877. tx_fs_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  878. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  879. tx_priv->pcm_rate[decimator] = (snd_soc_component_read(component,
  880. tx_fs_reg) & 0x0F);
  881. if(!is_amic_enabled(component, decimator))
  882. lpass_cdc_tx_macro_enable_dmic(w, kcontrol, event, adc_mux0_reg);
  883. switch (event) {
  884. case SND_SOC_DAPM_PRE_PMU:
  885. snd_soc_component_update_bits(component,
  886. dec_cfg_reg, 0x06, tx_priv->dec_mode[decimator] <<
  887. LPASS_CDC_TX_MACRO_ADC_MODE_CFG0_SHIFT);
  888. /* Enable TX PGA Mute */
  889. snd_soc_component_update_bits(component,
  890. tx_vol_ctl_reg, 0x10, 0x10);
  891. break;
  892. case SND_SOC_DAPM_POST_PMU:
  893. snd_soc_component_update_bits(component,
  894. tx_vol_ctl_reg, 0x20, 0x20);
  895. if (!is_amic_enabled(component, decimator)) {
  896. snd_soc_component_update_bits(component,
  897. hpf_gate_reg, 0x01, 0x00);
  898. /*
  899. * Minimum 1 clk cycle delay is required as per HW spec
  900. */
  901. usleep_range(1000, 1010);
  902. }
  903. hpf_cut_off_freq = (
  904. snd_soc_component_read(component, dec_cfg_reg) &
  905. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  906. tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq =
  907. hpf_cut_off_freq;
  908. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
  909. snd_soc_component_update_bits(component, dec_cfg_reg,
  910. TX_HPF_CUT_OFF_FREQ_MASK,
  911. CF_MIN_3DB_150HZ << 5);
  912. if (is_amic_enabled(component, decimator)) {
  913. hpf_delay = LPASS_CDC_TX_MACRO_AMIC_HPF_DELAY_MS;
  914. unmute_delay = LPASS_CDC_TX_MACRO_AMIC_UNMUTE_DELAY_MS;
  915. }
  916. if (tx_unmute_delay < unmute_delay)
  917. tx_unmute_delay = unmute_delay;
  918. lpass_cdc_tx_macro_wake_enable(tx_priv, 1);
  919. /* schedule work queue to Remove Mute */
  920. queue_delayed_work(system_freezable_wq,
  921. &tx_priv->tx_mute_dwork[decimator].dwork,
  922. msecs_to_jiffies(tx_unmute_delay));
  923. if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq !=
  924. CF_MIN_3DB_150HZ) {
  925. lpass_cdc_tx_macro_wake_enable(tx_priv, 1);
  926. queue_delayed_work(system_freezable_wq,
  927. &tx_priv->tx_hpf_work[decimator].dwork,
  928. msecs_to_jiffies(hpf_delay));
  929. snd_soc_component_update_bits(component,
  930. hpf_gate_reg, 0x03, 0x02);
  931. if (!is_amic_enabled(component, decimator))
  932. snd_soc_component_update_bits(component,
  933. hpf_gate_reg, 0x03, 0x00);
  934. snd_soc_component_update_bits(component,
  935. hpf_gate_reg, 0x03, 0x01);
  936. /*
  937. * 6ms delay is required as per HW spec
  938. */
  939. usleep_range(6000, 6010);
  940. }
  941. /* apply gain after decimator is enabled */
  942. snd_soc_component_write(component, tx_gain_ctl_reg,
  943. snd_soc_component_read(component,
  944. tx_gain_ctl_reg));
  945. if (tx_priv->bcs_enable) {
  946. snd_soc_component_update_bits(component,
  947. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F,
  948. tx_priv->bcs_ch);
  949. snd_soc_component_update_bits(component, dec_cfg_reg,
  950. 0x01, 0x01);
  951. tx_priv->bcs_clk_en = true;
  952. if (tx_priv->hs_slow_insert_complete)
  953. snd_soc_component_update_bits(component,
  954. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40,
  955. 0x40);
  956. }
  957. break;
  958. case SND_SOC_DAPM_PRE_PMD:
  959. hpf_cut_off_freq =
  960. tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq;
  961. snd_soc_component_update_bits(component,
  962. tx_vol_ctl_reg, 0x10, 0x10);
  963. if (cancel_delayed_work_sync(
  964. &tx_priv->tx_hpf_work[decimator].dwork)) {
  965. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
  966. snd_soc_component_update_bits(
  967. component, dec_cfg_reg,
  968. TX_HPF_CUT_OFF_FREQ_MASK,
  969. hpf_cut_off_freq << 5);
  970. if (is_amic_enabled(component, decimator))
  971. snd_soc_component_update_bits(component,
  972. hpf_gate_reg,
  973. 0x03, 0x02);
  974. else
  975. snd_soc_component_update_bits(component,
  976. hpf_gate_reg,
  977. 0x03, 0x03);
  978. /*
  979. * Minimum 1 clk cycle delay is required
  980. * as per HW spec
  981. */
  982. usleep_range(1000, 1010);
  983. snd_soc_component_update_bits(component,
  984. hpf_gate_reg,
  985. 0x03, 0x01);
  986. }
  987. }
  988. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  989. cancel_delayed_work_sync(
  990. &tx_priv->tx_mute_dwork[decimator].dwork);
  991. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  992. if (snd_soc_component_read(component, adc_mux_reg)
  993. & SWR_MIC)
  994. snd_soc_component_update_bits(component,
  995. LPASS_CDC_TX_TOP_CSR_SWR_CTRL,
  996. 0x01, 0x00);
  997. break;
  998. case SND_SOC_DAPM_POST_PMD:
  999. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1000. 0x20, 0x00);
  1001. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1002. 0x40, 0x40);
  1003. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1004. 0x40, 0x00);
  1005. snd_soc_component_update_bits(component,
  1006. dec_cfg_reg, 0x06, 0x00);
  1007. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1008. 0x10, 0x00);
  1009. snd_soc_component_update_bits(component, tx_fs_reg,
  1010. 0x0F, 0x04);
  1011. if (tx_priv->bcs_enable) {
  1012. snd_soc_component_update_bits(component, dec_cfg_reg,
  1013. 0x01, 0x00);
  1014. snd_soc_component_update_bits(component,
  1015. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, 0x00);
  1016. tx_priv->bcs_clk_en = false;
  1017. snd_soc_component_update_bits(component,
  1018. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F,
  1019. 0x00);
  1020. }
  1021. break;
  1022. }
  1023. return 0;
  1024. }
  1025. static int lpass_cdc_tx_macro_enable_micbias(struct snd_soc_dapm_widget *w,
  1026. struct snd_kcontrol *kcontrol, int event)
  1027. {
  1028. return 0;
  1029. }
  1030. /* Cutoff frequency for high pass filter */
  1031. static const char * const cf_text[] = {
  1032. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
  1033. };
  1034. static SOC_ENUM_SINGLE_DECL(cf_dec0_enum, LPASS_CDC_TX0_TX_PATH_CFG0, 5,
  1035. cf_text);
  1036. static SOC_ENUM_SINGLE_DECL(cf_dec1_enum, LPASS_CDC_TX1_TX_PATH_CFG0, 5,
  1037. cf_text);
  1038. static SOC_ENUM_SINGLE_DECL(cf_dec2_enum, LPASS_CDC_TX2_TX_PATH_CFG0, 5,
  1039. cf_text);
  1040. static SOC_ENUM_SINGLE_DECL(cf_dec3_enum, LPASS_CDC_TX3_TX_PATH_CFG0, 5,
  1041. cf_text);
  1042. static SOC_ENUM_SINGLE_DECL(cf_dec4_enum, LPASS_CDC_TX4_TX_PATH_CFG0, 5,
  1043. cf_text);
  1044. static SOC_ENUM_SINGLE_DECL(cf_dec5_enum, LPASS_CDC_TX5_TX_PATH_CFG0, 5,
  1045. cf_text);
  1046. static SOC_ENUM_SINGLE_DECL(cf_dec6_enum, LPASS_CDC_TX6_TX_PATH_CFG0, 5,
  1047. cf_text);
  1048. static SOC_ENUM_SINGLE_DECL(cf_dec7_enum, LPASS_CDC_TX7_TX_PATH_CFG0, 5,
  1049. cf_text);
  1050. static int lpass_cdc_tx_macro_hw_params(struct snd_pcm_substream *substream,
  1051. struct snd_pcm_hw_params *params,
  1052. struct snd_soc_dai *dai)
  1053. {
  1054. int tx_fs_rate = -EINVAL;
  1055. struct snd_soc_component *component = dai->component;
  1056. u32 decimator = 0;
  1057. u32 sample_rate = 0;
  1058. u16 tx_fs_reg = 0;
  1059. struct device *tx_dev = NULL;
  1060. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1061. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1062. return -EINVAL;
  1063. pr_info("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
  1064. dai->name, dai->id, params_rate(params),
  1065. params_channels(params));
  1066. sample_rate = params_rate(params);
  1067. switch (sample_rate) {
  1068. case 8000:
  1069. tx_fs_rate = 0;
  1070. break;
  1071. case 16000:
  1072. tx_fs_rate = 1;
  1073. break;
  1074. case 32000:
  1075. tx_fs_rate = 3;
  1076. break;
  1077. case 48000:
  1078. tx_fs_rate = 4;
  1079. break;
  1080. case 96000:
  1081. tx_fs_rate = 5;
  1082. break;
  1083. case 192000:
  1084. tx_fs_rate = 6;
  1085. break;
  1086. case 384000:
  1087. tx_fs_rate = 7;
  1088. break;
  1089. default:
  1090. dev_err_ratelimited(component->dev, "%s: Invalid TX sample rate: %d\n",
  1091. __func__, params_rate(params));
  1092. return -EINVAL;
  1093. }
  1094. for_each_set_bit(decimator, &tx_priv->active_ch_mask[dai->id],
  1095. LPASS_CDC_TX_MACRO_DEC_MAX) {
  1096. if (decimator >= 0) {
  1097. tx_fs_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  1098. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  1099. dev_dbg(component->dev, "%s: set DEC%u rate to %u\n",
  1100. __func__, decimator, sample_rate);
  1101. snd_soc_component_update_bits(component, tx_fs_reg,
  1102. 0x0F, tx_fs_rate);
  1103. } else {
  1104. dev_err_ratelimited(component->dev,
  1105. "%s: ERROR: Invalid decimator: %d\n",
  1106. __func__, decimator);
  1107. return -EINVAL;
  1108. }
  1109. }
  1110. return 0;
  1111. }
  1112. static int lpass_cdc_tx_macro_get_channel_map(struct snd_soc_dai *dai,
  1113. unsigned int *tx_num, unsigned int *tx_slot,
  1114. unsigned int *rx_num, unsigned int *rx_slot)
  1115. {
  1116. struct snd_soc_component *component = dai->component;
  1117. struct device *tx_dev = NULL;
  1118. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1119. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1120. return -EINVAL;
  1121. switch (dai->id) {
  1122. case LPASS_CDC_TX_MACRO_AIF1_CAP:
  1123. case LPASS_CDC_TX_MACRO_AIF2_CAP:
  1124. case LPASS_CDC_TX_MACRO_AIF3_CAP:
  1125. *tx_slot = tx_priv->active_ch_mask[dai->id];
  1126. *tx_num = tx_priv->active_ch_cnt[dai->id];
  1127. break;
  1128. default:
  1129. dev_err_ratelimited(tx_dev, "%s: Invalid AIF\n", __func__);
  1130. break;
  1131. }
  1132. return 0;
  1133. }
  1134. static struct snd_soc_dai_ops lpass_cdc_tx_macro_dai_ops = {
  1135. .hw_params = lpass_cdc_tx_macro_hw_params,
  1136. .get_channel_map = lpass_cdc_tx_macro_get_channel_map,
  1137. };
  1138. static struct snd_soc_dai_driver lpass_cdc_tx_macro_dai[] = {
  1139. {
  1140. .name = "tx_macro_tx1",
  1141. .id = LPASS_CDC_TX_MACRO_AIF1_CAP,
  1142. .capture = {
  1143. .stream_name = "TX_AIF1 Capture",
  1144. .rates = LPASS_CDC_TX_MACRO_RATES,
  1145. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1146. .rate_max = 192000,
  1147. .rate_min = 8000,
  1148. .channels_min = 1,
  1149. .channels_max = 8,
  1150. },
  1151. .ops = &lpass_cdc_tx_macro_dai_ops,
  1152. },
  1153. {
  1154. .name = "tx_macro_tx2",
  1155. .id = LPASS_CDC_TX_MACRO_AIF2_CAP,
  1156. .capture = {
  1157. .stream_name = "TX_AIF2 Capture",
  1158. .rates = LPASS_CDC_TX_MACRO_RATES,
  1159. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1160. .rate_max = 192000,
  1161. .rate_min = 8000,
  1162. .channels_min = 1,
  1163. .channels_max = 8,
  1164. },
  1165. .ops = &lpass_cdc_tx_macro_dai_ops,
  1166. },
  1167. {
  1168. .name = "tx_macro_tx3",
  1169. .id = LPASS_CDC_TX_MACRO_AIF3_CAP,
  1170. .capture = {
  1171. .stream_name = "TX_AIF3 Capture",
  1172. .rates = LPASS_CDC_TX_MACRO_RATES,
  1173. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1174. .rate_max = 192000,
  1175. .rate_min = 8000,
  1176. .channels_min = 1,
  1177. .channels_max = 8,
  1178. },
  1179. .ops = &lpass_cdc_tx_macro_dai_ops,
  1180. },
  1181. };
  1182. #define STRING(name) #name
  1183. #define LPASS_CDC_TX_MACRO_DAPM_ENUM(name, reg, offset, text) \
  1184. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1185. static const struct snd_kcontrol_new name##_mux = \
  1186. SOC_DAPM_ENUM(STRING(name), name##_enum)
  1187. #define LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
  1188. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1189. static const struct snd_kcontrol_new name##_mux = \
  1190. SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
  1191. #define LPASS_CDC_TX_MACRO_DAPM_MUX(name, shift, kctl) \
  1192. SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
  1193. static const char * const adc_mux_text[] = {
  1194. "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
  1195. };
  1196. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1,
  1197. 0, adc_mux_text);
  1198. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1,
  1199. 0, adc_mux_text);
  1200. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1,
  1201. 0, adc_mux_text);
  1202. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1,
  1203. 0, adc_mux_text);
  1204. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1,
  1205. 0, adc_mux_text);
  1206. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1,
  1207. 0, adc_mux_text);
  1208. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1,
  1209. 0, adc_mux_text);
  1210. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1,
  1211. 0, adc_mux_text);
  1212. static const char * const dmic_mux_text[] = {
  1213. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
  1214. "DMIC4", "DMIC5", "DMIC6", "DMIC7"
  1215. };
  1216. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0,
  1217. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1218. lpass_cdc_tx_macro_put_dec_enum);
  1219. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0,
  1220. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1221. lpass_cdc_tx_macro_put_dec_enum);
  1222. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0,
  1223. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1224. lpass_cdc_tx_macro_put_dec_enum);
  1225. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0,
  1226. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1227. lpass_cdc_tx_macro_put_dec_enum);
  1228. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0,
  1229. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1230. lpass_cdc_tx_macro_put_dec_enum);
  1231. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0,
  1232. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1233. lpass_cdc_tx_macro_put_dec_enum);
  1234. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0,
  1235. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1236. lpass_cdc_tx_macro_put_dec_enum);
  1237. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0,
  1238. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1239. lpass_cdc_tx_macro_put_dec_enum);
  1240. static const char * const smic_mux_text[] = {
  1241. "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
  1242. "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
  1243. "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11"
  1244. };
  1245. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0,
  1246. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1247. lpass_cdc_tx_macro_put_dec_enum);
  1248. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0,
  1249. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1250. lpass_cdc_tx_macro_put_dec_enum);
  1251. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0,
  1252. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1253. lpass_cdc_tx_macro_put_dec_enum);
  1254. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0,
  1255. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1256. lpass_cdc_tx_macro_put_dec_enum);
  1257. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0,
  1258. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1259. lpass_cdc_tx_macro_put_dec_enum);
  1260. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0,
  1261. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1262. lpass_cdc_tx_macro_put_dec_enum);
  1263. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0,
  1264. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1265. lpass_cdc_tx_macro_put_dec_enum);
  1266. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0,
  1267. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1268. lpass_cdc_tx_macro_put_dec_enum);
  1269. static const char * const dec_mode_mux_text[] = {
  1270. "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
  1271. };
  1272. static const struct soc_enum dec_mode_mux_enum =
  1273. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dec_mode_mux_text),
  1274. dec_mode_mux_text);
  1275. static const char * const bcs_ch_enum_text[] = {
  1276. "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", "CH8", "CH9",
  1277. "CH10", "CH11",
  1278. };
  1279. static const struct soc_enum bcs_ch_enum =
  1280. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(bcs_ch_enum_text),
  1281. bcs_ch_enum_text);
  1282. static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
  1283. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1284. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1285. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1286. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1287. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1288. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1289. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1290. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1291. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1292. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1293. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1294. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1295. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1296. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1297. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1298. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1299. };
  1300. static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
  1301. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1302. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1303. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1304. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1305. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1306. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1307. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1308. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1309. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1310. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1311. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1312. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1313. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1314. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1315. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1316. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1317. };
  1318. static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
  1319. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1320. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1321. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1322. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1323. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1324. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1325. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1326. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1327. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1328. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1329. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1330. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1331. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1332. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1333. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1334. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1335. };
  1336. static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets[] = {
  1337. SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
  1338. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF1_CAP, 0),
  1339. SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
  1340. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF2_CAP, 0),
  1341. SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
  1342. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF3_CAP, 0),
  1343. SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM,
  1344. LPASS_CDC_TX_MACRO_AIF1_CAP, 0,
  1345. tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
  1346. SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM,
  1347. LPASS_CDC_TX_MACRO_AIF2_CAP, 0,
  1348. tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
  1349. SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM,
  1350. LPASS_CDC_TX_MACRO_AIF3_CAP, 0,
  1351. tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
  1352. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0),
  1353. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1),
  1354. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2),
  1355. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3),
  1356. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4),
  1357. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5),
  1358. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6),
  1359. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7),
  1360. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0),
  1361. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1),
  1362. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2),
  1363. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3),
  1364. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4),
  1365. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5),
  1366. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6),
  1367. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7),
  1368. SND_SOC_DAPM_SUPPLY("TX MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1369. lpass_cdc_tx_macro_enable_micbias,
  1370. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1371. SND_SOC_DAPM_ADC("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0),
  1372. SND_SOC_DAPM_ADC("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0),
  1373. SND_SOC_DAPM_ADC("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0),
  1374. SND_SOC_DAPM_ADC("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0),
  1375. SND_SOC_DAPM_ADC("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0),
  1376. SND_SOC_DAPM_ADC("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0),
  1377. SND_SOC_DAPM_ADC("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0),
  1378. SND_SOC_DAPM_ADC("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0),
  1379. SND_SOC_DAPM_INPUT("TX SWR_INPUT"),
  1380. SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
  1381. LPASS_CDC_TX_MACRO_DEC0, 0,
  1382. &tx_dec0_mux, lpass_cdc_tx_macro_enable_dec,
  1383. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1384. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1385. SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
  1386. LPASS_CDC_TX_MACRO_DEC1, 0,
  1387. &tx_dec1_mux, lpass_cdc_tx_macro_enable_dec,
  1388. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1389. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1390. SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
  1391. LPASS_CDC_TX_MACRO_DEC2, 0,
  1392. &tx_dec2_mux, lpass_cdc_tx_macro_enable_dec,
  1393. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1394. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1395. SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
  1396. LPASS_CDC_TX_MACRO_DEC3, 0,
  1397. &tx_dec3_mux, lpass_cdc_tx_macro_enable_dec,
  1398. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1399. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1400. SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
  1401. LPASS_CDC_TX_MACRO_DEC4, 0,
  1402. &tx_dec4_mux, lpass_cdc_tx_macro_enable_dec,
  1403. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1404. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1405. SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
  1406. LPASS_CDC_TX_MACRO_DEC5, 0,
  1407. &tx_dec5_mux, lpass_cdc_tx_macro_enable_dec,
  1408. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1409. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1410. SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
  1411. LPASS_CDC_TX_MACRO_DEC6, 0,
  1412. &tx_dec6_mux, lpass_cdc_tx_macro_enable_dec,
  1413. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1414. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1415. SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
  1416. LPASS_CDC_TX_MACRO_DEC7, 0,
  1417. &tx_dec7_mux, lpass_cdc_tx_macro_enable_dec,
  1418. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1419. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1420. SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
  1421. lpass_cdc_tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1422. };
  1423. static const struct snd_soc_dapm_route tx_audio_map[] = {
  1424. {"TX_AIF1 CAP", NULL, "TX_MCLK"},
  1425. {"TX_AIF2 CAP", NULL, "TX_MCLK"},
  1426. {"TX_AIF3 CAP", NULL, "TX_MCLK"},
  1427. {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
  1428. {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
  1429. {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
  1430. {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1431. {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1432. {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1433. {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1434. {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1435. {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1436. {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1437. {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1438. {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1439. {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1440. {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1441. {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1442. {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1443. {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1444. {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1445. {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1446. {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1447. {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1448. {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1449. {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1450. {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1451. {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1452. {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1453. {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1454. {"TX DEC0 MUX", NULL, "TX_MCLK"},
  1455. {"TX DEC1 MUX", NULL, "TX_MCLK"},
  1456. {"TX DEC2 MUX", NULL, "TX_MCLK"},
  1457. {"TX DEC3 MUX", NULL, "TX_MCLK"},
  1458. {"TX DEC4 MUX", NULL, "TX_MCLK"},
  1459. {"TX DEC5 MUX", NULL, "TX_MCLK"},
  1460. {"TX DEC6 MUX", NULL, "TX_MCLK"},
  1461. {"TX DEC7 MUX", NULL, "TX_MCLK"},
  1462. {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
  1463. {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
  1464. {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
  1465. {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
  1466. {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
  1467. {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
  1468. {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
  1469. {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
  1470. {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
  1471. {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
  1472. {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT"},
  1473. {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT"},
  1474. {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT"},
  1475. {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT"},
  1476. {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT"},
  1477. {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT"},
  1478. {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT"},
  1479. {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT"},
  1480. {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT"},
  1481. {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT"},
  1482. {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT"},
  1483. {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT"},
  1484. {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
  1485. {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
  1486. {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
  1487. {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
  1488. {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
  1489. {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
  1490. {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
  1491. {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
  1492. {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
  1493. {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
  1494. {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT"},
  1495. {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT"},
  1496. {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT"},
  1497. {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT"},
  1498. {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT"},
  1499. {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT"},
  1500. {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT"},
  1501. {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT"},
  1502. {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT"},
  1503. {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT"},
  1504. {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT"},
  1505. {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT"},
  1506. {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
  1507. {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
  1508. {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
  1509. {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
  1510. {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
  1511. {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
  1512. {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
  1513. {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
  1514. {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
  1515. {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
  1516. {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT"},
  1517. {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT"},
  1518. {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT"},
  1519. {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT"},
  1520. {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT"},
  1521. {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT"},
  1522. {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT"},
  1523. {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT"},
  1524. {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT"},
  1525. {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT"},
  1526. {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT"},
  1527. {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT"},
  1528. {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
  1529. {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
  1530. {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
  1531. {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
  1532. {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
  1533. {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
  1534. {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
  1535. {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
  1536. {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
  1537. {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
  1538. {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT"},
  1539. {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT"},
  1540. {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT"},
  1541. {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT"},
  1542. {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT"},
  1543. {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT"},
  1544. {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT"},
  1545. {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT"},
  1546. {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT"},
  1547. {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT"},
  1548. {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT"},
  1549. {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT"},
  1550. {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
  1551. {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
  1552. {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
  1553. {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
  1554. {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
  1555. {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
  1556. {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
  1557. {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
  1558. {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
  1559. {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
  1560. {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT"},
  1561. {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT"},
  1562. {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT"},
  1563. {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT"},
  1564. {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT"},
  1565. {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT"},
  1566. {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT"},
  1567. {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT"},
  1568. {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT"},
  1569. {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT"},
  1570. {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT"},
  1571. {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT"},
  1572. {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
  1573. {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
  1574. {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
  1575. {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
  1576. {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
  1577. {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
  1578. {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
  1579. {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
  1580. {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
  1581. {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
  1582. {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT"},
  1583. {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT"},
  1584. {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT"},
  1585. {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT"},
  1586. {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT"},
  1587. {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT"},
  1588. {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT"},
  1589. {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT"},
  1590. {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT"},
  1591. {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT"},
  1592. {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT"},
  1593. {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT"},
  1594. {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
  1595. {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
  1596. {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
  1597. {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
  1598. {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
  1599. {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
  1600. {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
  1601. {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
  1602. {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
  1603. {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
  1604. {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT"},
  1605. {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT"},
  1606. {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT"},
  1607. {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT"},
  1608. {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT"},
  1609. {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT"},
  1610. {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT"},
  1611. {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT"},
  1612. {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT"},
  1613. {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT"},
  1614. {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT"},
  1615. {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT"},
  1616. {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
  1617. {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
  1618. {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
  1619. {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
  1620. {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
  1621. {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
  1622. {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
  1623. {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
  1624. {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
  1625. {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
  1626. {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT"},
  1627. {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT"},
  1628. {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT"},
  1629. {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT"},
  1630. {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT"},
  1631. {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT"},
  1632. {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT"},
  1633. {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT"},
  1634. {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT"},
  1635. {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT"},
  1636. {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT"},
  1637. {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT"},
  1638. };
  1639. static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls[] = {
  1640. SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
  1641. LPASS_CDC_TX0_TX_VOL_CTL,
  1642. -84, 40, digital_gain),
  1643. SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
  1644. LPASS_CDC_TX1_TX_VOL_CTL,
  1645. -84, 40, digital_gain),
  1646. SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
  1647. LPASS_CDC_TX2_TX_VOL_CTL,
  1648. -84, 40, digital_gain),
  1649. SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
  1650. LPASS_CDC_TX3_TX_VOL_CTL,
  1651. -84, 40, digital_gain),
  1652. SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
  1653. LPASS_CDC_TX4_TX_VOL_CTL,
  1654. -84, 40, digital_gain),
  1655. SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
  1656. LPASS_CDC_TX5_TX_VOL_CTL,
  1657. -84, 40, digital_gain),
  1658. SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
  1659. LPASS_CDC_TX6_TX_VOL_CTL,
  1660. -84, 40, digital_gain),
  1661. SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
  1662. LPASS_CDC_TX7_TX_VOL_CTL,
  1663. -84, 40, digital_gain),
  1664. SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum,
  1665. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1666. SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum,
  1667. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1668. SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum,
  1669. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1670. SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum,
  1671. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1672. SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum,
  1673. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1674. SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum,
  1675. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1676. SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum,
  1677. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1678. SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum,
  1679. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1680. SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
  1681. SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
  1682. SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
  1683. SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
  1684. SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
  1685. SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
  1686. SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
  1687. SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
  1688. SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
  1689. lpass_cdc_tx_macro_get_bcs, lpass_cdc_tx_macro_set_bcs),
  1690. SOC_SINGLE_EXT("TX_SWR_DMIC Enable", SND_SOC_NOPM, 0, 1, 0,
  1691. lpass_cdc_tx_macro_swr_dmic_get, lpass_cdc_tx_macro_swr_dmic_put),
  1692. SOC_ENUM_EXT("BCS Channel", bcs_ch_enum,
  1693. lpass_cdc_tx_macro_bcs_ch_get, lpass_cdc_tx_macro_bcs_ch_put),
  1694. SOC_ENUM_EXT("BCS CH_SEL", bcs_ch_sel_mux_enum,
  1695. lpass_cdc_tx_macro_get_bcs_ch_sel, lpass_cdc_tx_macro_put_bcs_ch_sel),
  1696. SOC_ENUM_EXT("DMIC_RATE OVERRIDE", dmic_rate_enum,
  1697. lpass_cdc_dmic_rate_override_get, lpass_cdc_dmic_rate_override_put),
  1698. };
  1699. static int lpass_cdc_tx_macro_clk_div_get(struct snd_soc_component *component)
  1700. {
  1701. struct device *tx_dev = NULL;
  1702. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1703. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1704. return -EINVAL;
  1705. if (tx_priv->dmic_rate_override)
  1706. return dmic_clk_rate_div[tx_priv->dmic_rate_override];
  1707. return (int)tx_priv->dmic_clk_div;
  1708. }
  1709. static int lpass_cdc_tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
  1710. struct lpass_cdc_tx_macro_priv *tx_priv)
  1711. {
  1712. u32 div_factor = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1713. u32 mclk_rate = LPASS_CDC_TX_MACRO_MCLK_FREQ;
  1714. if (dmic_sample_rate == LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED ||
  1715. mclk_rate % dmic_sample_rate != 0)
  1716. goto undefined_rate;
  1717. div_factor = mclk_rate / dmic_sample_rate;
  1718. switch (div_factor) {
  1719. case 2:
  1720. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1721. break;
  1722. case 3:
  1723. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_3;
  1724. break;
  1725. case 4:
  1726. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_4;
  1727. break;
  1728. case 6:
  1729. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_6;
  1730. break;
  1731. case 8:
  1732. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_8;
  1733. break;
  1734. case 16:
  1735. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_16;
  1736. break;
  1737. default:
  1738. /* Any other DIV factor is invalid */
  1739. goto undefined_rate;
  1740. }
  1741. /* Valid dmic DIV factors */
  1742. dev_dbg(tx_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
  1743. __func__, div_factor, mclk_rate);
  1744. return dmic_sample_rate;
  1745. undefined_rate:
  1746. dev_dbg(tx_priv->dev, "%s: Invalid rate %d, for mclk %d\n",
  1747. __func__, dmic_sample_rate, mclk_rate);
  1748. dmic_sample_rate = LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED;
  1749. return dmic_sample_rate;
  1750. }
  1751. static const struct lpass_cdc_tx_macro_reg_mask_val
  1752. lpass_cdc_tx_macro_reg_init[] = {
  1753. {LPASS_CDC_TX0_TX_PATH_SEC7, 0x3F, 0x0A},
  1754. {LPASS_CDC_TX0_TX_PATH_CFG1, 0x0F, 0x0A},
  1755. {LPASS_CDC_TX1_TX_PATH_CFG1, 0x0F, 0x0A},
  1756. {LPASS_CDC_TX2_TX_PATH_CFG1, 0x0F, 0x0A},
  1757. };
  1758. static int lpass_cdc_tx_macro_init(struct snd_soc_component *component)
  1759. {
  1760. struct snd_soc_dapm_context *dapm =
  1761. snd_soc_component_get_dapm(component);
  1762. int ret = 0, i = 0;
  1763. struct device *tx_dev = NULL;
  1764. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1765. tx_dev = lpass_cdc_get_device_ptr(component->dev, TX_MACRO);
  1766. if (!tx_dev) {
  1767. dev_err(component->dev,
  1768. "%s: null device for macro!\n", __func__);
  1769. return -EINVAL;
  1770. }
  1771. tx_priv = dev_get_drvdata(tx_dev);
  1772. if (!tx_priv) {
  1773. dev_err(component->dev,
  1774. "%s: priv is null for macro!\n", __func__);
  1775. return -EINVAL;
  1776. }
  1777. tx_priv->version = lpass_cdc_get_version(tx_dev);
  1778. ret = snd_soc_dapm_new_controls(dapm, lpass_cdc_tx_macro_dapm_widgets,
  1779. ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets));
  1780. if (ret < 0) {
  1781. dev_err(tx_dev, "%s: Failed to add controls\n",
  1782. __func__);
  1783. return ret;
  1784. }
  1785. ret = snd_soc_dapm_add_routes(dapm, tx_audio_map,
  1786. ARRAY_SIZE(tx_audio_map));
  1787. if (ret < 0) {
  1788. dev_err(tx_dev, "%s: Failed to add routes\n",
  1789. __func__);
  1790. return ret;
  1791. }
  1792. ret = snd_soc_dapm_new_widgets(dapm->card);
  1793. if (ret < 0) {
  1794. dev_err(tx_dev, "%s: Failed to add widgets\n", __func__);
  1795. return ret;
  1796. }
  1797. ret = snd_soc_add_component_controls(component,
  1798. lpass_cdc_tx_macro_snd_controls,
  1799. ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls));
  1800. if (ret < 0) {
  1801. dev_err(tx_dev, "%s: Failed to add snd_ctls\n",
  1802. __func__);
  1803. return ret;
  1804. }
  1805. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF1 Capture");
  1806. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF2 Capture");
  1807. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF3 Capture");
  1808. snd_soc_dapm_ignore_suspend(dapm, "TX SWR_INPUT");
  1809. snd_soc_dapm_sync(dapm);
  1810. for (i = 0; i < NUM_DECIMATORS; i++) {
  1811. tx_priv->tx_hpf_work[i].tx_priv = tx_priv;
  1812. tx_priv->tx_hpf_work[i].decimator = i;
  1813. INIT_DELAYED_WORK(&tx_priv->tx_hpf_work[i].dwork,
  1814. lpass_cdc_tx_macro_tx_hpf_corner_freq_callback);
  1815. }
  1816. for (i = 0; i < NUM_DECIMATORS; i++) {
  1817. tx_priv->tx_mute_dwork[i].tx_priv = tx_priv;
  1818. tx_priv->tx_mute_dwork[i].decimator = i;
  1819. INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork,
  1820. lpass_cdc_tx_macro_mute_update_callback);
  1821. }
  1822. tx_priv->component = component;
  1823. for (i = 0; i < ARRAY_SIZE(lpass_cdc_tx_macro_reg_init); i++)
  1824. snd_soc_component_update_bits(component,
  1825. lpass_cdc_tx_macro_reg_init[i].reg,
  1826. lpass_cdc_tx_macro_reg_init[i].mask,
  1827. lpass_cdc_tx_macro_reg_init[i].val);
  1828. return 0;
  1829. }
  1830. static int lpass_cdc_tx_macro_deinit(struct snd_soc_component *component)
  1831. {
  1832. struct device *tx_dev = NULL;
  1833. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1834. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1835. return -EINVAL;
  1836. tx_priv->component = NULL;
  1837. return 0;
  1838. }
  1839. static void lpass_cdc_tx_macro_init_ops(struct macro_ops *ops,
  1840. char __iomem *tx_io_base)
  1841. {
  1842. memset(ops, 0, sizeof(struct macro_ops));
  1843. ops->init = lpass_cdc_tx_macro_init;
  1844. ops->exit = lpass_cdc_tx_macro_deinit;
  1845. ops->io_base = tx_io_base;
  1846. ops->dai_ptr = lpass_cdc_tx_macro_dai;
  1847. ops->num_dais = ARRAY_SIZE(lpass_cdc_tx_macro_dai);
  1848. ops->event_handler = lpass_cdc_tx_macro_event_handler;
  1849. ops->clk_div_get = lpass_cdc_tx_macro_clk_div_get;
  1850. ops->clk_enable = __lpass_cdc_tx_macro_mclk_enable;
  1851. }
  1852. static int lpass_cdc_tx_macro_probe(struct platform_device *pdev)
  1853. {
  1854. struct macro_ops ops = {0};
  1855. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1856. u32 tx_base_addr = 0, sample_rate = 0;
  1857. char __iomem *tx_io_base = NULL;
  1858. int ret = 0;
  1859. const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate";
  1860. if (!lpass_cdc_is_va_macro_registered(&pdev->dev)) {
  1861. dev_err(&pdev->dev,
  1862. "%s: va-macro not registered yet, defer\n", __func__);
  1863. return -EPROBE_DEFER;
  1864. }
  1865. tx_priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_tx_macro_priv),
  1866. GFP_KERNEL);
  1867. if (!tx_priv)
  1868. return -ENOMEM;
  1869. platform_set_drvdata(pdev, tx_priv);
  1870. tx_priv->dev = &pdev->dev;
  1871. ret = of_property_read_u32(pdev->dev.of_node, "reg",
  1872. &tx_base_addr);
  1873. if (ret) {
  1874. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  1875. __func__, "reg");
  1876. return ret;
  1877. }
  1878. dev_set_drvdata(&pdev->dev, tx_priv);
  1879. tx_io_base = devm_ioremap(&pdev->dev,
  1880. tx_base_addr, LPASS_CDC_TX_MACRO_MAX_OFFSET);
  1881. if (!tx_io_base) {
  1882. dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);
  1883. return -ENOMEM;
  1884. }
  1885. tx_priv->tx_io_base = tx_io_base;
  1886. tx_priv->swr_dmic_enable = false;
  1887. tx_priv->wlock_holders = 0;
  1888. ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate,
  1889. &sample_rate);
  1890. if (ret) {
  1891. dev_err(&pdev->dev,
  1892. "%s: could not find sample_rate entry in dt\n",
  1893. __func__);
  1894. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1895. } else {
  1896. if (lpass_cdc_tx_macro_validate_dmic_sample_rate(
  1897. sample_rate, tx_priv) == LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED)
  1898. return -EINVAL;
  1899. }
  1900. mutex_init(&tx_priv->mclk_lock);
  1901. mutex_init(&tx_priv->wlock);
  1902. lpass_cdc_tx_macro_init_ops(&ops, tx_io_base);
  1903. ops.clk_id_req = TX_CORE_CLK;
  1904. ops.default_clk_id = TX_CORE_CLK;
  1905. ret = lpass_cdc_register_macro(&pdev->dev, TX_MACRO, &ops);
  1906. if (ret) {
  1907. dev_err(&pdev->dev,
  1908. "%s: register macro failed\n", __func__);
  1909. goto err_reg_macro;
  1910. }
  1911. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
  1912. pm_runtime_use_autosuspend(&pdev->dev);
  1913. pm_runtime_set_suspended(&pdev->dev);
  1914. pm_suspend_ignore_children(&pdev->dev, true);
  1915. pm_runtime_enable(&pdev->dev);
  1916. return 0;
  1917. err_reg_macro:
  1918. mutex_destroy(&tx_priv->mclk_lock);
  1919. mutex_destroy(&tx_priv->wlock);
  1920. return ret;
  1921. }
  1922. static int lpass_cdc_tx_macro_remove(struct platform_device *pdev)
  1923. {
  1924. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1925. tx_priv = platform_get_drvdata(pdev);
  1926. if (!tx_priv)
  1927. return -EINVAL;
  1928. pm_runtime_disable(&pdev->dev);
  1929. pm_runtime_set_suspended(&pdev->dev);
  1930. mutex_destroy(&tx_priv->mclk_lock);
  1931. mutex_destroy(&tx_priv->wlock);
  1932. lpass_cdc_unregister_macro(&pdev->dev, TX_MACRO);
  1933. return 0;
  1934. }
  1935. static const struct of_device_id lpass_cdc_tx_macro_dt_match[] = {
  1936. {.compatible = "qcom,lpass-cdc-tx-macro"},
  1937. {}
  1938. };
  1939. static const struct dev_pm_ops lpass_cdc_dev_pm_ops = {
  1940. SET_SYSTEM_SLEEP_PM_OPS(
  1941. pm_runtime_force_suspend,
  1942. pm_runtime_force_resume
  1943. )
  1944. SET_RUNTIME_PM_OPS(
  1945. lpass_cdc_runtime_suspend,
  1946. lpass_cdc_runtime_resume,
  1947. NULL
  1948. )
  1949. };
  1950. static struct platform_driver lpass_cdc_tx_macro_driver = {
  1951. .driver = {
  1952. .name = "lpass_cdc_tx_macro",
  1953. .owner = THIS_MODULE,
  1954. .pm = &lpass_cdc_dev_pm_ops,
  1955. .of_match_table = lpass_cdc_tx_macro_dt_match,
  1956. .suppress_bind_attrs = true,
  1957. },
  1958. .probe = lpass_cdc_tx_macro_probe,
  1959. .remove = lpass_cdc_tx_macro_remove,
  1960. };
  1961. module_platform_driver(lpass_cdc_tx_macro_driver);
  1962. MODULE_DESCRIPTION("TX macro driver");
  1963. MODULE_LICENSE("GPL v2");