5694bc2eee
DSI PLL is tightly coupled with DSI PHY. This change removes separate DSI pll driver and makes DSI pll as a subnode to DSI PHY which is an accurate way of representation. In addition, this change adds support for 5nm DSI ctrl and PHY revisions and adds DSI pll support for 5nm. Remove support for older DSI pll revisions such as 7nm, 10nm, 14nm, 20nm, 28nm. Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
149 行
3.4 KiB
C
149 行
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "dsi_pll.h"
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static int dsi_pll_clock_register(struct platform_device *pdev,
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struct dsi_pll_resource *pll_res)
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{
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int rc;
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switch (pll_res->pll_revision) {
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case DSI_PLL_5NM:
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rc = dsi_pll_clock_register_5nm(pdev, pll_res);
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break;
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default:
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rc = -EINVAL;
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break;
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}
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if (rc)
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DSI_PLL_ERR(pll_res, "clock register failed rc=%d\n", rc);
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return rc;
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}
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static inline int dsi_pll_get_ioresources(struct platform_device *pdev,
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void __iomem **regmap, char *resource_name)
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{
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int rc = 0;
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struct resource *rsc = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, resource_name);
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if (rsc) {
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if (!regmap)
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return -ENOMEM;
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*regmap = devm_ioremap(&pdev->dev,
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rsc->start, resource_size(rsc));
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if (!*regmap)
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return -ENOMEM;
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}
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return rc;
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}
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int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll)
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{
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int rc = 0;
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const char *label;
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struct dsi_pll_resource *pll_res = NULL;
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if (!pdev->dev.of_node) {
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pr_err("Invalid DSI PHY node\n");
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return -ENOTSUPP;
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}
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pll_res = devm_kzalloc(&pdev->dev, sizeof(struct dsi_pll_resource),
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GFP_KERNEL);
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if (!pll_res)
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return -ENOMEM;
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*pll = pll_res;
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label = of_get_property(pdev->dev.of_node, "pll-label", NULL);
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if (!label)
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DSI_PLL_INFO(pll_res, "DSI pll label not specified\n");
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else
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DSI_PLL_INFO(pll_res, "DSI pll label = %s\n", label);
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/**
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* Currently, Only supports 5nm PLL version. Will add
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* support for other versions as needed.
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*/
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if (!strcmp(label, "dsi_pll_5nm"))
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pll_res->pll_revision = DSI_PLL_5NM;
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else
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return -ENOTSUPP;
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rc = of_property_read_u32(pdev->dev.of_node, "cell-index",
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&pll_res->index);
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if (rc) {
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DSI_PLL_ERR(pll_res, "Unable to get the cell-index rc=%d\n", rc);
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pll_res->index = 0;
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}
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pll_res->ssc_en = of_property_read_bool(pdev->dev.of_node,
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"qcom,dsi-pll-ssc-en");
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if (pll_res->ssc_en) {
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DSI_PLL_INFO(pll_res, "PLL SSC enabled\n");
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rc = of_property_read_u32(pdev->dev.of_node,
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"qcom,ssc-frequency-hz", &pll_res->ssc_freq);
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rc = of_property_read_u32(pdev->dev.of_node,
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"qcom,ssc-ppm", &pll_res->ssc_ppm);
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pll_res->ssc_center = false;
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label = of_get_property(pdev->dev.of_node,
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"qcom,dsi-pll-ssc-mode", NULL);
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if (label && !strcmp(label, "center-spread"))
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pll_res->ssc_center = true;
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}
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if (dsi_pll_get_ioresources(pdev, &pll_res->pll_base, "pll_base")) {
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DSI_PLL_ERR(pll_res, "Unable to remap pll base resources\n");
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return -ENOMEM;
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}
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pr_info("PLL base=%p\n", pll_res->pll_base);
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if (dsi_pll_get_ioresources(pdev, &pll_res->phy_base, "dsi_phy")) {
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DSI_PLL_ERR(pll_res, "Unable to remap pll phy base resources\n");
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return -ENOMEM;
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}
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if (dsi_pll_get_ioresources(pdev, &pll_res->dyn_pll_base,
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"dyn_refresh_base")) {
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DSI_PLL_ERR(pll_res, "Unable to remap dynamic pll base resources\n");
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return -ENOMEM;
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}
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if (dsi_pll_get_ioresources(pdev, &pll_res->gdsc_base, "gdsc_base")) {
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DSI_PLL_ERR(pll_res, "Unable to remap gdsc base resources\n");
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return -ENOMEM;
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}
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rc = dsi_pll_clock_register(pdev, pll_res);
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if (rc) {
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DSI_PLL_ERR(pll_res, "clock register failed rc=%d\n", rc);
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return -EINVAL;
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}
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return rc;
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}
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