dp_ipa.c 124 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318
  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <wlan_ipa_core.h>
  20. #include <qdf_ipa_wdi3.h>
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <hal_hw_headers.h>
  24. #include <hal_api.h>
  25. #include <hal_reo.h>
  26. #include <hif.h>
  27. #include <htt.h>
  28. #include <wdi_event.h>
  29. #include <queue.h>
  30. #include "dp_types.h"
  31. #include "dp_htt.h"
  32. #include "dp_tx.h"
  33. #include "dp_rx.h"
  34. #include "dp_ipa.h"
  35. #include "dp_internal.h"
  36. #ifdef WIFI_MONITOR_SUPPORT
  37. #include "dp_mon.h"
  38. #endif
  39. #ifdef FEATURE_WDS
  40. #include "dp_txrx_wds.h"
  41. #endif
  42. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  43. #include <pld_common.h>
  44. #endif
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #define WLAN_IPA_AST_META_DATA_MASK htonl(0x000000FF)
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  70. #define REO_REMAP_HISTORY_SIZE 32
  71. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  72. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  73. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  74. {
  75. int next = qdf_atomic_inc_return(index);
  76. if (next == REO_REMAP_HISTORY_SIZE)
  77. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  78. return next % REO_REMAP_HISTORY_SIZE;
  79. }
  80. /**
  81. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  82. * @ix0_val: reo destination ring IX0 value
  83. * @ix2_val: reo destination ring IX2 value
  84. * @ix3_val: reo destination ring IX3 value
  85. *
  86. * Return: None
  87. */
  88. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  89. uint32_t ix3_val)
  90. {
  91. int idx = dp_ipa_reo_remap_record_index_next(
  92. &dp_ipa_reo_remap_history_index);
  93. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  94. record->timestamp = qdf_get_log_timestamp();
  95. record->ix0_reg = ix0_val;
  96. record->ix2_reg = ix2_val;
  97. record->ix3_reg = ix3_val;
  98. }
  99. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  100. qdf_nbuf_t nbuf,
  101. uint32_t size,
  102. bool create,
  103. const char *func,
  104. uint32_t line)
  105. {
  106. qdf_mem_info_t mem_map_table = {0};
  107. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  108. qdf_ipa_wdi_hdl_t hdl;
  109. /* Need to handle the case when one soc will
  110. * have multiple pdev(radio's), Currently passing
  111. * pdev_id as 0 assuming 1 soc has only 1 radio.
  112. */
  113. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  114. if (hdl == DP_IPA_HDL_INVALID) {
  115. dp_err("IPA handle is invalid");
  116. return QDF_STATUS_E_INVAL;
  117. }
  118. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  119. qdf_nbuf_get_frag_paddr(nbuf, 0),
  120. size);
  121. if (create) {
  122. /* Assert if PA is zero */
  123. qdf_assert_always(mem_map_table.pa);
  124. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  125. func, line);
  126. } else {
  127. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. }
  130. qdf_assert_always(!ret);
  131. /* Return status of mapping/unmapping is stored in
  132. * mem_map_table.result field, assert if the result
  133. * is failure
  134. */
  135. if (create)
  136. qdf_assert_always(!mem_map_table.result);
  137. else
  138. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  139. return ret;
  140. }
  141. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  142. qdf_nbuf_t nbuf,
  143. uint32_t size,
  144. bool create, const char *func,
  145. uint32_t line)
  146. {
  147. struct dp_pdev *pdev;
  148. int i;
  149. for (i = 0; i < soc->pdev_count; i++) {
  150. pdev = soc->pdev_list[i];
  151. if (pdev && dp_monitor_is_configured(pdev))
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  155. !qdf_mem_smmu_s1_enabled(soc->osdev))
  156. return QDF_STATUS_SUCCESS;
  157. /*
  158. * Even if ipa pipes is disabled, but if it's unmap
  159. * operation and nbuf has done ipa smmu map before,
  160. * do ipa smmu unmap as well.
  161. */
  162. if (!(qdf_atomic_read(&soc->ipa_pipes_enabled) &&
  163. qdf_atomic_read(&soc->ipa_map_allowed))) {
  164. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  165. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  166. } else {
  167. return QDF_STATUS_SUCCESS;
  168. }
  169. }
  170. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  171. if (create) {
  172. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  173. } else {
  174. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  175. }
  176. return QDF_STATUS_E_INVAL;
  177. }
  178. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  179. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  180. func, line);
  181. }
  182. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  183. struct dp_soc *soc,
  184. struct dp_pdev *pdev,
  185. bool create,
  186. const char *func,
  187. uint32_t line)
  188. {
  189. uint32_t index;
  190. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  191. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  192. qdf_nbuf_t nbuf;
  193. uint32_t buf_len;
  194. if (!ipa_is_ready()) {
  195. dp_info("IPA is not READY");
  196. return 0;
  197. }
  198. for (index = 0; index < tx_buffer_cnt; index++) {
  199. nbuf = (qdf_nbuf_t)
  200. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  201. if (!nbuf)
  202. continue;
  203. buf_len = qdf_nbuf_get_data_len(nbuf);
  204. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  205. create, func, line);
  206. }
  207. return ret;
  208. }
  209. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  210. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  211. bool lock_required)
  212. {
  213. hal_ring_handle_t hal_ring_hdl;
  214. int ring;
  215. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  216. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  217. hal_srng_lock(hal_ring_hdl);
  218. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  219. hal_srng_unlock(hal_ring_hdl);
  220. }
  221. }
  222. #else
  223. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  224. bool lock_required)
  225. {
  226. }
  227. #endif
  228. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  229. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  230. struct dp_pdev *pdev,
  231. bool create,
  232. const char *func,
  233. uint32_t line)
  234. {
  235. struct rx_desc_pool *rx_pool;
  236. uint8_t pdev_id;
  237. uint32_t num_desc, page_id, offset, i;
  238. uint16_t num_desc_per_page;
  239. union dp_rx_desc_list_elem_t *rx_desc_elem;
  240. struct dp_rx_desc *rx_desc;
  241. qdf_nbuf_t nbuf;
  242. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  243. if (!qdf_ipa_is_ready())
  244. return ret;
  245. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  246. return ret;
  247. pdev_id = pdev->pdev_id;
  248. rx_pool = &soc->rx_desc_buf[pdev_id];
  249. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  250. qdf_spin_lock_bh(&rx_pool->lock);
  251. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  252. num_desc = rx_pool->pool_size;
  253. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  254. for (i = 0; i < num_desc; i++) {
  255. page_id = i / num_desc_per_page;
  256. offset = i % num_desc_per_page;
  257. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  258. break;
  259. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  260. rx_desc = &rx_desc_elem->rx_desc;
  261. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  262. continue;
  263. nbuf = rx_desc->nbuf;
  264. if (qdf_unlikely(create ==
  265. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  266. if (create) {
  267. DP_STATS_INC(soc,
  268. rx.err.ipa_smmu_map_dup, 1);
  269. } else {
  270. DP_STATS_INC(soc,
  271. rx.err.ipa_smmu_unmap_dup, 1);
  272. }
  273. continue;
  274. }
  275. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  276. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  277. rx_pool->buf_size,
  278. create, func, line);
  279. }
  280. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  281. qdf_spin_unlock_bh(&rx_pool->lock);
  282. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  283. return ret;
  284. }
  285. #else
  286. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  287. struct dp_soc *soc,
  288. struct dp_pdev *pdev,
  289. bool create,
  290. const char *func,
  291. uint32_t line)
  292. {
  293. struct rx_desc_pool *rx_pool;
  294. uint8_t pdev_id;
  295. qdf_nbuf_t nbuf;
  296. int i;
  297. if (!qdf_ipa_is_ready())
  298. return QDF_STATUS_SUCCESS;
  299. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  300. return QDF_STATUS_SUCCESS;
  301. pdev_id = pdev->pdev_id;
  302. rx_pool = &soc->rx_desc_buf[pdev_id];
  303. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  304. qdf_spin_lock_bh(&rx_pool->lock);
  305. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  306. for (i = 0; i < rx_pool->pool_size; i++) {
  307. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  308. rx_pool->array[i].rx_desc.unmapped)
  309. continue;
  310. nbuf = rx_pool->array[i].rx_desc.nbuf;
  311. if (qdf_unlikely(create ==
  312. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  313. if (create) {
  314. DP_STATS_INC(soc,
  315. rx.err.ipa_smmu_map_dup, 1);
  316. } else {
  317. DP_STATS_INC(soc,
  318. rx.err.ipa_smmu_unmap_dup, 1);
  319. }
  320. continue;
  321. }
  322. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  323. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  324. create, func, line);
  325. }
  326. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  327. qdf_spin_unlock_bh(&rx_pool->lock);
  328. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  329. return QDF_STATUS_SUCCESS;
  330. }
  331. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  332. QDF_STATUS dp_ipa_set_smmu_mapped(struct cdp_soc_t *soc_hdl, int val)
  333. {
  334. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  335. qdf_atomic_set(&soc->ipa_map_allowed, val);
  336. return QDF_STATUS_SUCCESS;
  337. }
  338. int dp_ipa_get_smmu_mapped(struct cdp_soc_t *soc_hdl)
  339. {
  340. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  341. return qdf_atomic_read(&soc->ipa_map_allowed);
  342. }
  343. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  344. qdf_shared_mem_t *shared_mem,
  345. void *cpu_addr,
  346. qdf_dma_addr_t dma_addr,
  347. uint32_t size)
  348. {
  349. qdf_dma_addr_t paddr;
  350. int ret;
  351. shared_mem->vaddr = cpu_addr;
  352. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  353. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  354. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  355. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  356. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  357. shared_mem->vaddr, dma_addr, size);
  358. if (ret) {
  359. dp_err("Unable to get DMA sgtable");
  360. return QDF_STATUS_E_NOMEM;
  361. }
  362. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  363. return QDF_STATUS_SUCCESS;
  364. }
  365. /**
  366. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  367. * @soc: dp_soc handle
  368. * @bank_id: out parameter for bank id
  369. *
  370. * Return: QDF_STATUS
  371. */
  372. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  373. {
  374. if (soc->arch_ops.ipa_get_bank_id) {
  375. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  376. if (*bank_id < 0) {
  377. return QDF_STATUS_E_INVAL;
  378. } else {
  379. dp_info("bank_id %u", *bank_id);
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. } else {
  383. return QDF_STATUS_E_NOSUPPORT;
  384. }
  385. }
  386. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  387. defined(CONFIG_IPA_WDI_UNIFIED_API)
  388. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  389. qdf_ipa_wdi_pipe_setup_info_t *tx)
  390. {
  391. uint8_t bank_id;
  392. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  393. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  394. }
  395. static void
  396. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  397. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  398. {
  399. uint8_t bank_id;
  400. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  401. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  402. }
  403. #else
  404. static inline void
  405. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  406. qdf_ipa_wdi_pipe_setup_info_t *tx)
  407. {
  408. }
  409. static inline void
  410. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  411. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  412. {
  413. }
  414. #endif
  415. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  416. static void
  417. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  418. qdf_ipa_wdi_pipe_setup_info_t *tx)
  419. {
  420. uint8_t pmac_id = 0;
  421. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  422. if (soc->pdev_count > 1)
  423. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  424. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  425. }
  426. static void
  427. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  428. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  429. {
  430. uint8_t pmac_id = 0;
  431. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  432. if (soc->pdev_count > 1)
  433. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  434. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  435. }
  436. static void
  437. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  438. qdf_ipa_wdi_pipe_setup_info_t *tx)
  439. {
  440. uint8_t pmac_id;
  441. pmac_id = soc->pdev_list[0]->lmac_id;
  442. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  443. }
  444. static void
  445. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  446. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  447. {
  448. uint8_t pmac_id;
  449. pmac_id = soc->pdev_list[0]->lmac_id;
  450. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  451. }
  452. #else
  453. static inline void
  454. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  455. qdf_ipa_wdi_pipe_setup_info_t *tx)
  456. {
  457. }
  458. static inline void
  459. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  460. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  461. {
  462. }
  463. static inline void
  464. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  465. qdf_ipa_wdi_pipe_setup_info_t *tx)
  466. {
  467. }
  468. static inline void
  469. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  470. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  471. {
  472. }
  473. #endif
  474. #ifdef IPA_WDI3_TX_TWO_PIPES
  475. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  476. {
  477. struct dp_ipa_resources *ipa_res;
  478. qdf_nbuf_t nbuf;
  479. int idx;
  480. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  481. nbuf = (qdf_nbuf_t)
  482. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  483. if (!nbuf)
  484. continue;
  485. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  486. qdf_mem_dp_tx_skb_cnt_dec();
  487. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  488. qdf_nbuf_free(nbuf);
  489. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  490. (void *)NULL;
  491. }
  492. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  493. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  494. ipa_res = &pdev->ipa_resource;
  495. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  496. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  497. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  498. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  499. }
  500. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  501. {
  502. uint32_t tx_buffer_count;
  503. uint32_t ring_base_align = 8;
  504. qdf_dma_addr_t buffer_paddr;
  505. struct hal_srng *wbm_srng = (struct hal_srng *)
  506. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  507. struct hal_srng_params srng_params;
  508. uint32_t wbm_bm_id;
  509. void *ring_entry;
  510. int num_entries;
  511. qdf_nbuf_t nbuf;
  512. int retval = QDF_STATUS_SUCCESS;
  513. int max_alloc_count = 0;
  514. /*
  515. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  516. * unsigned int uc_tx_buf_sz =
  517. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  518. */
  519. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  520. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  521. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  522. IPA_TX_ALT_RING_IDX);
  523. hal_get_srng_params(soc->hal_soc,
  524. hal_srng_to_hal_ring_handle(wbm_srng),
  525. &srng_params);
  526. num_entries = srng_params.num_entries;
  527. max_alloc_count =
  528. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  529. if (max_alloc_count <= 0) {
  530. dp_err("incorrect value for buffer count %u", max_alloc_count);
  531. return -EINVAL;
  532. }
  533. dp_info("requested %d buffers to be posted to wbm ring",
  534. max_alloc_count);
  535. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  536. qdf_mem_malloc(num_entries *
  537. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  538. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  539. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  540. return -ENOMEM;
  541. }
  542. hal_srng_access_start_unlocked(soc->hal_soc,
  543. hal_srng_to_hal_ring_handle(wbm_srng));
  544. /*
  545. * Allocate Tx buffers as many as possible.
  546. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  547. * Populate Tx buffers into WBM2IPA ring
  548. * This initial buffer population will simulate H/W as source ring,
  549. * and update HP
  550. */
  551. for (tx_buffer_count = 0;
  552. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  553. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  554. 256, FALSE);
  555. if (!nbuf)
  556. break;
  557. ring_entry = hal_srng_dst_get_next_hp(
  558. soc->hal_soc,
  559. hal_srng_to_hal_ring_handle(wbm_srng));
  560. if (!ring_entry) {
  561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  562. "%s: Failed to get WBM ring entry",
  563. __func__);
  564. qdf_nbuf_free(nbuf);
  565. break;
  566. }
  567. qdf_nbuf_map_single(soc->osdev, nbuf,
  568. QDF_DMA_BIDIRECTIONAL);
  569. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  570. qdf_mem_dp_tx_skb_cnt_inc();
  571. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  572. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  573. buffer_paddr, 0, wbm_bm_id);
  574. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  575. tx_buffer_count] = (void *)nbuf;
  576. }
  577. hal_srng_access_end_unlocked(soc->hal_soc,
  578. hal_srng_to_hal_ring_handle(wbm_srng));
  579. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  580. if (tx_buffer_count) {
  581. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  582. } else {
  583. dp_err("Failed to allocate IPA TX buffer pool2");
  584. qdf_mem_free(
  585. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  586. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  587. retval = -ENOMEM;
  588. }
  589. return retval;
  590. }
  591. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  592. {
  593. struct dp_soc *soc = pdev->soc;
  594. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  595. ipa_res->tx_alt_ring_num_alloc_buffer =
  596. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  597. dp_ipa_get_shared_mem_info(
  598. soc->osdev, &ipa_res->tx_alt_ring,
  599. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  600. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  601. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  602. dp_ipa_get_shared_mem_info(
  603. soc->osdev, &ipa_res->tx_alt_comp_ring,
  604. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  605. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  606. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  607. if (!qdf_mem_get_dma_addr(soc->osdev,
  608. &ipa_res->tx_alt_comp_ring.mem_info))
  609. return QDF_STATUS_E_FAILURE;
  610. return QDF_STATUS_SUCCESS;
  611. }
  612. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  613. {
  614. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  615. struct hal_srng *hal_srng;
  616. struct hal_srng_params srng_params;
  617. unsigned long addr_offset, dev_base_paddr;
  618. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  619. hal_srng = (struct hal_srng *)
  620. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  621. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  622. hal_srng_to_hal_ring_handle(hal_srng),
  623. &srng_params);
  624. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  625. srng_params.ring_base_paddr;
  626. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  627. srng_params.ring_base_vaddr;
  628. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  629. (srng_params.num_entries * srng_params.entry_size) << 2;
  630. /*
  631. * For the register backed memory addresses, use the scn->mem_pa to
  632. * calculate the physical address of the shadow registers
  633. */
  634. dev_base_paddr =
  635. (unsigned long)
  636. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  637. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  638. (unsigned long)(hal_soc->dev_base_addr);
  639. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  640. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  641. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  642. (unsigned int)addr_offset,
  643. (unsigned int)dev_base_paddr,
  644. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  645. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  646. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  647. srng_params.num_entries,
  648. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  649. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  650. hal_srng = (struct hal_srng *)
  651. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  652. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  653. hal_srng_to_hal_ring_handle(hal_srng),
  654. &srng_params);
  655. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  656. srng_params.ring_base_paddr;
  657. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  658. srng_params.ring_base_vaddr;
  659. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  660. (srng_params.num_entries * srng_params.entry_size) << 2;
  661. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  662. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  663. hal_srng_to_hal_ring_handle(hal_srng));
  664. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  665. (unsigned long)(hal_soc->dev_base_addr);
  666. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  667. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  668. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  669. (unsigned int)addr_offset,
  670. (unsigned int)dev_base_paddr,
  671. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  672. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  673. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  674. srng_params.num_entries,
  675. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  676. }
  677. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  678. {
  679. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  680. uint32_t rx_ready_doorbell_dmaaddr;
  681. uint32_t tx_comp_doorbell_dmaaddr;
  682. struct dp_soc *soc = pdev->soc;
  683. int ret = 0;
  684. if (ipa_res->is_db_ddr_mapped)
  685. ipa_res->tx_comp_doorbell_vaddr =
  686. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  687. else
  688. ipa_res->tx_comp_doorbell_vaddr =
  689. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  690. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  691. ret = pld_smmu_map(soc->osdev->dev,
  692. ipa_res->tx_comp_doorbell_paddr,
  693. &tx_comp_doorbell_dmaaddr,
  694. sizeof(uint32_t));
  695. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  696. qdf_assert_always(!ret);
  697. ret = pld_smmu_map(soc->osdev->dev,
  698. ipa_res->rx_ready_doorbell_paddr,
  699. &rx_ready_doorbell_dmaaddr,
  700. sizeof(uint32_t));
  701. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  702. qdf_assert_always(!ret);
  703. }
  704. /* Setup for alternative TX pipe */
  705. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  706. return;
  707. if (ipa_res->is_db_ddr_mapped)
  708. ipa_res->tx_alt_comp_doorbell_vaddr =
  709. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  710. else
  711. ipa_res->tx_alt_comp_doorbell_vaddr =
  712. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  713. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  714. ret = pld_smmu_map(soc->osdev->dev,
  715. ipa_res->tx_alt_comp_doorbell_paddr,
  716. &tx_comp_doorbell_dmaaddr,
  717. sizeof(uint32_t));
  718. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  719. qdf_assert_always(!ret);
  720. }
  721. }
  722. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  723. {
  724. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  725. struct dp_soc *soc = pdev->soc;
  726. int ret = 0;
  727. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  728. return;
  729. /* Unmap must be in reverse order of map */
  730. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  731. ret = pld_smmu_unmap(soc->osdev->dev,
  732. ipa_res->tx_alt_comp_doorbell_paddr,
  733. sizeof(uint32_t));
  734. qdf_assert_always(!ret);
  735. }
  736. ret = pld_smmu_unmap(soc->osdev->dev,
  737. ipa_res->rx_ready_doorbell_paddr,
  738. sizeof(uint32_t));
  739. qdf_assert_always(!ret);
  740. ret = pld_smmu_unmap(soc->osdev->dev,
  741. ipa_res->tx_comp_doorbell_paddr,
  742. sizeof(uint32_t));
  743. qdf_assert_always(!ret);
  744. }
  745. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  746. struct dp_pdev *pdev,
  747. bool create, const char *func,
  748. uint32_t line)
  749. {
  750. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  751. struct ipa_dp_tx_rsc *rsc;
  752. uint32_t tx_buffer_cnt;
  753. uint32_t buf_len;
  754. qdf_nbuf_t nbuf;
  755. uint32_t index;
  756. if (!ipa_is_ready()) {
  757. dp_info("IPA is not READY");
  758. return QDF_STATUS_SUCCESS;
  759. }
  760. rsc = &soc->ipa_uc_tx_rsc_alt;
  761. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  762. for (index = 0; index < tx_buffer_cnt; index++) {
  763. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  764. if (!nbuf)
  765. continue;
  766. buf_len = qdf_nbuf_get_data_len(nbuf);
  767. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  768. create, func, line);
  769. }
  770. return ret;
  771. }
  772. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  773. struct dp_ipa_resources *ipa_res,
  774. qdf_ipa_wdi_pipe_setup_info_t *tx)
  775. {
  776. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  777. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  778. qdf_mem_get_dma_addr(soc->osdev,
  779. &ipa_res->tx_alt_comp_ring.mem_info);
  780. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  781. qdf_mem_get_dma_size(soc->osdev,
  782. &ipa_res->tx_alt_comp_ring.mem_info);
  783. /* WBM Tail Pointer Address */
  784. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  785. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  786. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  787. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  788. qdf_mem_get_dma_addr(soc->osdev,
  789. &ipa_res->tx_alt_ring.mem_info);
  790. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  791. qdf_mem_get_dma_size(soc->osdev,
  792. &ipa_res->tx_alt_ring.mem_info);
  793. /* TCL Head Pointer Address */
  794. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  795. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  796. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  797. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  798. ipa_res->tx_alt_ring_num_alloc_buffer;
  799. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  800. dp_ipa_setup_tx_params_bank_id(soc, tx);
  801. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  802. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  803. }
  804. static void
  805. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  806. struct dp_ipa_resources *ipa_res,
  807. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  808. {
  809. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  810. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  811. &ipa_res->tx_alt_comp_ring.sgtable,
  812. sizeof(sgtable_t));
  813. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  814. qdf_mem_get_dma_size(soc->osdev,
  815. &ipa_res->tx_alt_comp_ring.mem_info);
  816. /* WBM Tail Pointer Address */
  817. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  818. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  819. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  820. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  821. &ipa_res->tx_alt_ring.sgtable,
  822. sizeof(sgtable_t));
  823. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  824. qdf_mem_get_dma_size(soc->osdev,
  825. &ipa_res->tx_alt_ring.mem_info);
  826. /* TCL Head Pointer Address */
  827. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  828. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  829. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  830. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  831. ipa_res->tx_alt_ring_num_alloc_buffer;
  832. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  833. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  834. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  835. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  836. }
  837. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  838. struct dp_ipa_resources *res,
  839. qdf_ipa_wdi_conn_in_params_t *in)
  840. {
  841. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  842. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  843. qdf_ipa_ep_cfg_t *tx_cfg;
  844. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  845. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  846. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  847. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  848. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  849. } else {
  850. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  851. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  852. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  853. }
  854. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  855. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  856. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  857. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  858. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  859. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  860. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  861. }
  862. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  863. qdf_ipa_wdi_conn_out_params_t *out)
  864. {
  865. res->tx_comp_doorbell_paddr =
  866. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  867. res->rx_ready_doorbell_paddr =
  868. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  869. res->tx_alt_comp_doorbell_paddr =
  870. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  871. }
  872. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  873. uint8_t session_id)
  874. {
  875. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  876. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  877. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  878. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  879. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  880. }
  881. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  882. struct dp_ipa_resources *res)
  883. {
  884. struct hal_srng *wbm_srng;
  885. /* Init first TX comp ring */
  886. wbm_srng = (struct hal_srng *)
  887. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  888. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  889. res->tx_comp_doorbell_vaddr);
  890. /* Init the alternate TX comp ring */
  891. if (!res->tx_alt_comp_doorbell_paddr)
  892. return;
  893. wbm_srng = (struct hal_srng *)
  894. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  895. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  896. res->tx_alt_comp_doorbell_vaddr);
  897. }
  898. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  899. struct dp_ipa_resources *ipa_res)
  900. {
  901. struct hal_srng *wbm_srng;
  902. wbm_srng = (struct hal_srng *)
  903. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  904. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  905. ipa_res->tx_comp_doorbell_paddr);
  906. dp_info("paddr %pK vaddr %pK",
  907. (void *)ipa_res->tx_comp_doorbell_paddr,
  908. (void *)ipa_res->tx_comp_doorbell_vaddr);
  909. /* Setup for alternative TX comp ring */
  910. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  911. return;
  912. wbm_srng = (struct hal_srng *)
  913. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  914. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  915. ipa_res->tx_alt_comp_doorbell_paddr);
  916. dp_info("paddr %pK vaddr %pK",
  917. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  918. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  919. }
  920. #ifdef IPA_SET_RESET_TX_DB_PA
  921. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  922. struct dp_ipa_resources *ipa_res)
  923. {
  924. hal_ring_handle_t wbm_srng;
  925. qdf_dma_addr_t hp_addr;
  926. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  927. if (!wbm_srng)
  928. return QDF_STATUS_E_FAILURE;
  929. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  930. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  931. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  932. /* Reset alternative TX comp ring */
  933. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  934. if (!wbm_srng)
  935. return QDF_STATUS_E_FAILURE;
  936. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  937. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  938. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  939. return QDF_STATUS_SUCCESS;
  940. }
  941. #endif /* IPA_SET_RESET_TX_DB_PA */
  942. #else /* !IPA_WDI3_TX_TWO_PIPES */
  943. static inline
  944. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  945. {
  946. }
  947. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  948. {
  949. }
  950. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  951. {
  952. return 0;
  953. }
  954. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  955. {
  956. return QDF_STATUS_SUCCESS;
  957. }
  958. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  959. {
  960. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  961. uint32_t rx_ready_doorbell_dmaaddr;
  962. uint32_t tx_comp_doorbell_dmaaddr;
  963. struct dp_soc *soc = pdev->soc;
  964. int ret = 0;
  965. if (ipa_res->is_db_ddr_mapped)
  966. ipa_res->tx_comp_doorbell_vaddr =
  967. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  968. else
  969. ipa_res->tx_comp_doorbell_vaddr =
  970. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  971. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  972. ret = pld_smmu_map(soc->osdev->dev,
  973. ipa_res->tx_comp_doorbell_paddr,
  974. &tx_comp_doorbell_dmaaddr,
  975. sizeof(uint32_t));
  976. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  977. qdf_assert_always(!ret);
  978. ret = pld_smmu_map(soc->osdev->dev,
  979. ipa_res->rx_ready_doorbell_paddr,
  980. &rx_ready_doorbell_dmaaddr,
  981. sizeof(uint32_t));
  982. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  983. qdf_assert_always(!ret);
  984. }
  985. }
  986. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  987. {
  988. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  989. struct dp_soc *soc = pdev->soc;
  990. int ret = 0;
  991. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  992. return;
  993. ret = pld_smmu_unmap(soc->osdev->dev,
  994. ipa_res->rx_ready_doorbell_paddr,
  995. sizeof(uint32_t));
  996. qdf_assert_always(!ret);
  997. ret = pld_smmu_unmap(soc->osdev->dev,
  998. ipa_res->tx_comp_doorbell_paddr,
  999. sizeof(uint32_t));
  1000. qdf_assert_always(!ret);
  1001. }
  1002. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  1003. struct dp_pdev *pdev,
  1004. bool create,
  1005. const char *func,
  1006. uint32_t line)
  1007. {
  1008. return QDF_STATUS_SUCCESS;
  1009. }
  1010. static inline
  1011. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1012. qdf_ipa_wdi_conn_in_params_t *in)
  1013. {
  1014. }
  1015. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1016. qdf_ipa_wdi_conn_out_params_t *out)
  1017. {
  1018. res->tx_comp_doorbell_paddr =
  1019. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1020. res->rx_ready_doorbell_paddr =
  1021. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1022. }
  1023. #ifdef IPA_WDS_EASYMESH_FEATURE
  1024. /**
  1025. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1026. * @in: ipa in params
  1027. * @session_id: vdev id
  1028. *
  1029. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1030. * is stored at higher nibble so, no shift is required.
  1031. *
  1032. * Return: none
  1033. */
  1034. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1035. uint8_t session_id)
  1036. {
  1037. if (ucfg_ipa_is_wds_enabled())
  1038. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1039. else
  1040. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1041. }
  1042. #else
  1043. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1044. uint8_t session_id)
  1045. {
  1046. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1047. }
  1048. #endif
  1049. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1050. struct dp_ipa_resources *res)
  1051. {
  1052. struct hal_srng *wbm_srng = (struct hal_srng *)
  1053. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1054. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1055. res->tx_comp_doorbell_vaddr);
  1056. }
  1057. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1058. struct dp_ipa_resources *ipa_res)
  1059. {
  1060. struct hal_srng *wbm_srng = (struct hal_srng *)
  1061. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1062. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1063. ipa_res->tx_comp_doorbell_paddr);
  1064. dp_info("paddr %pK vaddr %pK",
  1065. (void *)ipa_res->tx_comp_doorbell_paddr,
  1066. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1067. }
  1068. #ifdef IPA_SET_RESET_TX_DB_PA
  1069. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1070. struct dp_ipa_resources *ipa_res)
  1071. {
  1072. hal_ring_handle_t wbm_srng =
  1073. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1074. qdf_dma_addr_t hp_addr;
  1075. if (!wbm_srng)
  1076. return QDF_STATUS_E_FAILURE;
  1077. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1078. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1079. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1080. return QDF_STATUS_SUCCESS;
  1081. }
  1082. #endif /* IPA_SET_RESET_TX_DB_PA */
  1083. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1084. /**
  1085. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1086. * @soc: data path instance
  1087. * @pdev: core txrx pdev context
  1088. *
  1089. * Free allocated TX buffers with WBM SRNG
  1090. *
  1091. * Return: none
  1092. */
  1093. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1094. {
  1095. int idx;
  1096. qdf_nbuf_t nbuf;
  1097. struct dp_ipa_resources *ipa_res;
  1098. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1099. nbuf = (qdf_nbuf_t)
  1100. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1101. if (!nbuf)
  1102. continue;
  1103. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1104. qdf_mem_dp_tx_skb_cnt_dec();
  1105. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1106. qdf_nbuf_free(nbuf);
  1107. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1108. (void *)NULL;
  1109. }
  1110. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1111. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1112. ipa_res = &pdev->ipa_resource;
  1113. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1114. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1115. }
  1116. /**
  1117. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1118. * @soc: data path instance
  1119. * @pdev: core txrx pdev context
  1120. *
  1121. * This function will detach DP RX into main device context
  1122. * will free DP Rx resources.
  1123. *
  1124. * Return: none
  1125. */
  1126. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1127. {
  1128. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1129. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1130. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1131. }
  1132. /**
  1133. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1134. * @soc: data path instance
  1135. * @pdev: core txrx pdev context
  1136. *
  1137. * This function will detach DP RX into main device context
  1138. * will free DP Rx resources.
  1139. *
  1140. * Return: none
  1141. */
  1142. #ifdef IPA_WDI3_VLAN_SUPPORT
  1143. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1144. {
  1145. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1146. if (!wlan_ipa_is_vlan_enabled())
  1147. return;
  1148. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1149. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1150. }
  1151. #else
  1152. static inline
  1153. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1154. { }
  1155. #endif
  1156. /**
  1157. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1158. * @soc: data path instance
  1159. * @pdev: core txrx pdev context
  1160. *
  1161. * This function will cleanup filter setup for optional wifi dp.
  1162. *
  1163. * Return: none
  1164. */
  1165. #ifdef IPA_OPT_WIFI_DP
  1166. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1167. {
  1168. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1169. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1170. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1171. int i;
  1172. for (i = count; i > 0; i--) {
  1173. dp_info("opt_dp: cleanup call pcie link down");
  1174. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1175. }
  1176. }
  1177. #else
  1178. static inline
  1179. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1180. {
  1181. }
  1182. #endif
  1183. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1184. {
  1185. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1186. return QDF_STATUS_SUCCESS;
  1187. /* TX resource detach */
  1188. dp_tx_ipa_uc_detach(soc, pdev);
  1189. /* Cleanup 2nd TX pipe resources */
  1190. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1191. /* RX resource detach */
  1192. dp_rx_ipa_uc_detach(soc, pdev);
  1193. /* Cleanup 2nd RX pipe resources */
  1194. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1195. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1196. return QDF_STATUS_SUCCESS; /* success */
  1197. }
  1198. /**
  1199. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1200. * @soc: data path instance
  1201. * @pdev: Physical device handle
  1202. *
  1203. * Allocate TX buffer from non-cacheable memory
  1204. * Attach allocated TX buffers with WBM SRNG
  1205. *
  1206. * Return: int
  1207. */
  1208. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1209. {
  1210. uint32_t tx_buffer_count;
  1211. uint32_t ring_base_align = 8;
  1212. qdf_dma_addr_t buffer_paddr;
  1213. struct hal_srng *wbm_srng = (struct hal_srng *)
  1214. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1215. struct hal_srng_params srng_params;
  1216. void *ring_entry;
  1217. int num_entries;
  1218. qdf_nbuf_t nbuf;
  1219. int retval = QDF_STATUS_SUCCESS;
  1220. int max_alloc_count = 0;
  1221. uint32_t wbm_bm_id;
  1222. /*
  1223. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1224. * unsigned int uc_tx_buf_sz =
  1225. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1226. */
  1227. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1228. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1229. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1230. IPA_TCL_DATA_RING_IDX);
  1231. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1232. &srng_params);
  1233. num_entries = srng_params.num_entries;
  1234. max_alloc_count =
  1235. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1236. if (max_alloc_count <= 0) {
  1237. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1238. return -EINVAL;
  1239. }
  1240. dp_info("requested %d buffers to be posted to wbm ring",
  1241. max_alloc_count);
  1242. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1243. qdf_mem_malloc(num_entries *
  1244. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1245. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1246. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1247. return -ENOMEM;
  1248. }
  1249. hal_srng_access_start_unlocked(soc->hal_soc,
  1250. hal_srng_to_hal_ring_handle(wbm_srng));
  1251. /*
  1252. * Allocate Tx buffers as many as possible.
  1253. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1254. * Populate Tx buffers into WBM2IPA ring
  1255. * This initial buffer population will simulate H/W as source ring,
  1256. * and update HP
  1257. */
  1258. for (tx_buffer_count = 0;
  1259. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1260. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  1261. 256, FALSE);
  1262. if (!nbuf)
  1263. break;
  1264. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1265. hal_srng_to_hal_ring_handle(wbm_srng));
  1266. if (!ring_entry) {
  1267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1268. "%s: Failed to get WBM ring entry",
  1269. __func__);
  1270. qdf_nbuf_free(nbuf);
  1271. break;
  1272. }
  1273. qdf_nbuf_map_single(soc->osdev, nbuf,
  1274. QDF_DMA_BIDIRECTIONAL);
  1275. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1276. qdf_mem_dp_tx_skb_cnt_inc();
  1277. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1278. /*
  1279. * TODO - KIWI code can directly call the be handler
  1280. * instead of hal soc ops.
  1281. */
  1282. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1283. buffer_paddr, 0, wbm_bm_id);
  1284. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1285. = (void *)nbuf;
  1286. }
  1287. hal_srng_access_end_unlocked(soc->hal_soc,
  1288. hal_srng_to_hal_ring_handle(wbm_srng));
  1289. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1290. if (tx_buffer_count) {
  1291. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1292. } else {
  1293. dp_err("No IPA WDI TX buffer allocated!");
  1294. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1295. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1296. retval = -ENOMEM;
  1297. }
  1298. return retval;
  1299. }
  1300. /**
  1301. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1302. * @soc: data path instance
  1303. * @pdev: core txrx pdev context
  1304. *
  1305. * This function will attach a DP RX instance into the main
  1306. * device (SOC) context.
  1307. *
  1308. * Return: QDF_STATUS_SUCCESS: success
  1309. * QDF_STATUS_E_RESOURCES: Error return
  1310. */
  1311. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1312. {
  1313. return QDF_STATUS_SUCCESS;
  1314. }
  1315. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1316. {
  1317. int error;
  1318. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1319. return QDF_STATUS_SUCCESS;
  1320. /* TX resource attach */
  1321. error = dp_tx_ipa_uc_attach(soc, pdev);
  1322. if (error) {
  1323. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1324. "%s: DP IPA UC TX attach fail code %d",
  1325. __func__, error);
  1326. return error;
  1327. }
  1328. /* Setup 2nd TX pipe */
  1329. error = dp_ipa_tx_alt_pool_attach(soc);
  1330. if (error) {
  1331. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1332. "%s: DP IPA TX pool2 attach fail code %d",
  1333. __func__, error);
  1334. dp_tx_ipa_uc_detach(soc, pdev);
  1335. return error;
  1336. }
  1337. /* RX resource attach */
  1338. error = dp_rx_ipa_uc_attach(soc, pdev);
  1339. if (error) {
  1340. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1341. "%s: DP IPA UC RX attach fail code %d",
  1342. __func__, error);
  1343. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1344. dp_tx_ipa_uc_detach(soc, pdev);
  1345. return error;
  1346. }
  1347. return QDF_STATUS_SUCCESS; /* success */
  1348. }
  1349. #ifdef IPA_WDI3_VLAN_SUPPORT
  1350. /**
  1351. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1352. * @soc: data path SoC handle
  1353. * @pdev: data path pdev handle
  1354. *
  1355. * Return: none
  1356. */
  1357. static
  1358. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1359. {
  1360. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1361. struct hal_srng *hal_srng;
  1362. struct hal_srng_params srng_params;
  1363. unsigned long addr_offset, dev_base_paddr;
  1364. qdf_dma_addr_t hp_addr;
  1365. if (!wlan_ipa_is_vlan_enabled())
  1366. return;
  1367. dev_base_paddr =
  1368. (unsigned long)
  1369. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1370. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1371. hal_srng = (struct hal_srng *)
  1372. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1373. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1374. hal_srng_to_hal_ring_handle(hal_srng),
  1375. &srng_params);
  1376. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1377. srng_params.ring_base_paddr;
  1378. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1379. srng_params.ring_base_vaddr;
  1380. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1381. (srng_params.num_entries * srng_params.entry_size) << 2;
  1382. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1383. (unsigned long)(hal_soc->dev_base_addr);
  1384. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1385. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1386. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1387. (unsigned int)addr_offset,
  1388. (unsigned int)dev_base_paddr,
  1389. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1390. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1391. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1392. srng_params.num_entries,
  1393. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1394. hal_srng = (struct hal_srng *)
  1395. pdev->rx_refill_buf_ring3.hal_srng;
  1396. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1397. hal_srng_to_hal_ring_handle(hal_srng),
  1398. &srng_params);
  1399. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1400. srng_params.ring_base_paddr;
  1401. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1402. srng_params.ring_base_vaddr;
  1403. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1404. (srng_params.num_entries * srng_params.entry_size) << 2;
  1405. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1406. hal_srng_to_hal_ring_handle(hal_srng));
  1407. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1408. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1409. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1410. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1411. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1412. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1413. srng_params.num_entries,
  1414. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1415. }
  1416. #else
  1417. static inline
  1418. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1419. { }
  1420. #endif
  1421. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1422. struct dp_pdev *pdev)
  1423. {
  1424. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1425. struct hal_srng *hal_srng;
  1426. struct hal_srng_params srng_params;
  1427. qdf_dma_addr_t hp_addr;
  1428. unsigned long addr_offset, dev_base_paddr;
  1429. uint32_t ix0;
  1430. uint8_t ix0_map[8];
  1431. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1432. return QDF_STATUS_SUCCESS;
  1433. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1434. hal_srng = (struct hal_srng *)
  1435. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1436. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1437. hal_srng_to_hal_ring_handle(hal_srng),
  1438. &srng_params);
  1439. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1440. srng_params.ring_base_paddr;
  1441. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1442. srng_params.ring_base_vaddr;
  1443. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1444. (srng_params.num_entries * srng_params.entry_size) << 2;
  1445. /*
  1446. * For the register backed memory addresses, use the scn->mem_pa to
  1447. * calculate the physical address of the shadow registers
  1448. */
  1449. dev_base_paddr =
  1450. (unsigned long)
  1451. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1452. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1453. (unsigned long)(hal_soc->dev_base_addr);
  1454. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1455. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1456. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1457. (unsigned int)addr_offset,
  1458. (unsigned int)dev_base_paddr,
  1459. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1460. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1461. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1462. srng_params.num_entries,
  1463. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1464. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1465. hal_srng = (struct hal_srng *)
  1466. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1467. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1468. hal_srng_to_hal_ring_handle(hal_srng),
  1469. &srng_params);
  1470. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1471. srng_params.ring_base_paddr;
  1472. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1473. srng_params.ring_base_vaddr;
  1474. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1475. (srng_params.num_entries * srng_params.entry_size) << 2;
  1476. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1477. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1478. hal_srng_to_hal_ring_handle(hal_srng));
  1479. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1480. (unsigned long)(hal_soc->dev_base_addr);
  1481. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1482. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1483. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1484. (unsigned int)addr_offset,
  1485. (unsigned int)dev_base_paddr,
  1486. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1487. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1488. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1489. srng_params.num_entries,
  1490. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1491. dp_ipa_tx_alt_ring_resource_setup(soc);
  1492. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1493. hal_srng = (struct hal_srng *)
  1494. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1495. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1496. hal_srng_to_hal_ring_handle(hal_srng),
  1497. &srng_params);
  1498. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1499. srng_params.ring_base_paddr;
  1500. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1501. srng_params.ring_base_vaddr;
  1502. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1503. (srng_params.num_entries * srng_params.entry_size) << 2;
  1504. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1505. (unsigned long)(hal_soc->dev_base_addr);
  1506. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1507. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1508. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1509. (unsigned int)addr_offset,
  1510. (unsigned int)dev_base_paddr,
  1511. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1512. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1513. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1514. srng_params.num_entries,
  1515. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1516. hal_srng = (struct hal_srng *)
  1517. pdev->rx_refill_buf_ring2.hal_srng;
  1518. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1519. hal_srng_to_hal_ring_handle(hal_srng),
  1520. &srng_params);
  1521. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1522. srng_params.ring_base_paddr;
  1523. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1524. srng_params.ring_base_vaddr;
  1525. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1526. (srng_params.num_entries * srng_params.entry_size) << 2;
  1527. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1528. hal_srng_to_hal_ring_handle(hal_srng));
  1529. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1530. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1531. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1532. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1533. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1534. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1535. srng_params.num_entries,
  1536. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1537. /*
  1538. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1539. * DESTINATION_RING_CTRL_IX_0.
  1540. */
  1541. ix0_map[0] = REO_REMAP_SW1;
  1542. ix0_map[1] = REO_REMAP_SW1;
  1543. ix0_map[2] = REO_REMAP_SW2;
  1544. ix0_map[3] = REO_REMAP_SW3;
  1545. ix0_map[4] = REO_REMAP_SW2;
  1546. ix0_map[5] = REO_REMAP_RELEASE;
  1547. ix0_map[6] = REO_REMAP_FW;
  1548. ix0_map[7] = REO_REMAP_FW;
  1549. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1550. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1551. ix0_map);
  1552. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1553. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1554. return 0;
  1555. }
  1556. #ifdef IPA_WDI3_VLAN_SUPPORT
  1557. /**
  1558. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1559. * @pdev: data path pdev handle
  1560. *
  1561. * Return: Success if resourece is found
  1562. */
  1563. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1564. {
  1565. struct dp_soc *soc = pdev->soc;
  1566. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1567. if (!wlan_ipa_is_vlan_enabled())
  1568. return QDF_STATUS_SUCCESS;
  1569. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1570. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1571. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1572. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1573. dp_ipa_get_shared_mem_info(
  1574. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1575. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1576. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1577. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1578. if (!qdf_mem_get_dma_addr(soc->osdev,
  1579. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1580. !qdf_mem_get_dma_addr(soc->osdev,
  1581. &ipa_res->rx_alt_refill_ring.mem_info))
  1582. return QDF_STATUS_E_FAILURE;
  1583. return QDF_STATUS_SUCCESS;
  1584. }
  1585. #else
  1586. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1587. {
  1588. return QDF_STATUS_SUCCESS;
  1589. }
  1590. #endif
  1591. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1592. {
  1593. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1594. struct dp_pdev *pdev =
  1595. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1596. struct dp_ipa_resources *ipa_res;
  1597. if (!pdev) {
  1598. dp_err("Invalid instance");
  1599. return QDF_STATUS_E_FAILURE;
  1600. }
  1601. ipa_res = &pdev->ipa_resource;
  1602. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1603. return QDF_STATUS_SUCCESS;
  1604. ipa_res->tx_num_alloc_buffer =
  1605. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1606. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1607. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1608. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1609. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1610. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1611. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1612. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1613. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1614. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1615. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1616. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1617. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1618. dp_ipa_get_shared_mem_info(
  1619. soc->osdev, &ipa_res->rx_refill_ring,
  1620. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1621. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1622. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1623. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1624. !qdf_mem_get_dma_addr(soc->osdev,
  1625. &ipa_res->tx_comp_ring.mem_info) ||
  1626. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1627. !qdf_mem_get_dma_addr(soc->osdev,
  1628. &ipa_res->rx_refill_ring.mem_info))
  1629. return QDF_STATUS_E_FAILURE;
  1630. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1631. return QDF_STATUS_E_FAILURE;
  1632. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1633. return QDF_STATUS_E_FAILURE;
  1634. return QDF_STATUS_SUCCESS;
  1635. }
  1636. #ifdef IPA_SET_RESET_TX_DB_PA
  1637. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1638. #else
  1639. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1640. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1641. #endif
  1642. #ifdef IPA_WDI3_VLAN_SUPPORT
  1643. /**
  1644. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1645. * @pdev: data path pdev handle
  1646. *
  1647. * Return: none
  1648. */
  1649. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1650. {
  1651. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1652. uint32_t rx_ready_doorbell_dmaaddr;
  1653. struct dp_soc *soc = pdev->soc;
  1654. struct hal_srng *reo_srng = (struct hal_srng *)
  1655. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1656. int ret = 0;
  1657. if (!wlan_ipa_is_vlan_enabled())
  1658. return;
  1659. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1660. ret = pld_smmu_map(soc->osdev->dev,
  1661. ipa_res->rx_alt_ready_doorbell_paddr,
  1662. &rx_ready_doorbell_dmaaddr,
  1663. sizeof(uint32_t));
  1664. ipa_res->rx_alt_ready_doorbell_paddr =
  1665. rx_ready_doorbell_dmaaddr;
  1666. qdf_assert_always(!ret);
  1667. }
  1668. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1669. ipa_res->rx_alt_ready_doorbell_paddr);
  1670. }
  1671. /**
  1672. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1673. * @pdev: data path pdev handle
  1674. *
  1675. * Return: none
  1676. */
  1677. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1678. {
  1679. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1680. struct dp_soc *soc = pdev->soc;
  1681. int ret = 0;
  1682. if (!wlan_ipa_is_vlan_enabled())
  1683. return;
  1684. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1685. return;
  1686. ret = pld_smmu_unmap(soc->osdev->dev,
  1687. ipa_res->rx_alt_ready_doorbell_paddr,
  1688. sizeof(uint32_t));
  1689. qdf_assert_always(!ret);
  1690. }
  1691. #else
  1692. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1693. { }
  1694. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1695. { }
  1696. #endif
  1697. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1698. {
  1699. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1700. struct dp_pdev *pdev =
  1701. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1702. struct dp_ipa_resources *ipa_res;
  1703. struct hal_srng *reo_srng = (struct hal_srng *)
  1704. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1705. if (!pdev) {
  1706. dp_err("Invalid instance");
  1707. return QDF_STATUS_E_FAILURE;
  1708. }
  1709. ipa_res = &pdev->ipa_resource;
  1710. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1711. return QDF_STATUS_SUCCESS;
  1712. dp_ipa_map_ring_doorbell_paddr(pdev);
  1713. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1714. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1715. /*
  1716. * For RX, REO module on Napier/Hastings does reordering on incoming
  1717. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1718. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1719. * to IPA.
  1720. * Set the doorbell addr for the REO ring.
  1721. */
  1722. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1723. ipa_res->rx_ready_doorbell_paddr);
  1724. return QDF_STATUS_SUCCESS;
  1725. }
  1726. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1727. uint8_t pdev_id)
  1728. {
  1729. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1730. struct dp_pdev *pdev =
  1731. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1732. struct dp_ipa_resources *ipa_res;
  1733. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1734. return QDF_STATUS_SUCCESS;
  1735. if (!pdev) {
  1736. dp_err("Invalid instance");
  1737. return QDF_STATUS_E_FAILURE;
  1738. }
  1739. ipa_res = &pdev->ipa_resource;
  1740. if (!ipa_res->is_db_ddr_mapped)
  1741. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1742. return QDF_STATUS_SUCCESS;
  1743. }
  1744. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1745. uint8_t *op_msg)
  1746. {
  1747. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1748. struct dp_pdev *pdev =
  1749. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1750. if (!pdev) {
  1751. dp_err("Invalid instance");
  1752. return QDF_STATUS_E_FAILURE;
  1753. }
  1754. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1755. return QDF_STATUS_SUCCESS;
  1756. if (pdev->ipa_uc_op_cb) {
  1757. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1758. } else {
  1759. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1760. "%s: IPA callback function is not registered", __func__);
  1761. qdf_mem_free(op_msg);
  1762. return QDF_STATUS_E_FAILURE;
  1763. }
  1764. return QDF_STATUS_SUCCESS;
  1765. }
  1766. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1767. ipa_uc_op_cb_type op_cb,
  1768. void *usr_ctxt)
  1769. {
  1770. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1771. struct dp_pdev *pdev =
  1772. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1773. if (!pdev) {
  1774. dp_err("Invalid instance");
  1775. return QDF_STATUS_E_FAILURE;
  1776. }
  1777. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1778. return QDF_STATUS_SUCCESS;
  1779. pdev->ipa_uc_op_cb = op_cb;
  1780. pdev->usr_ctxt = usr_ctxt;
  1781. return QDF_STATUS_SUCCESS;
  1782. }
  1783. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1784. {
  1785. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1786. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1787. if (!pdev) {
  1788. dp_err("Invalid instance");
  1789. return;
  1790. }
  1791. dp_debug("Deregister OP handler callback");
  1792. pdev->ipa_uc_op_cb = NULL;
  1793. pdev->usr_ctxt = NULL;
  1794. }
  1795. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1796. {
  1797. /* TBD */
  1798. return QDF_STATUS_SUCCESS;
  1799. }
  1800. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1801. qdf_nbuf_t skb)
  1802. {
  1803. qdf_nbuf_t ret;
  1804. /* Terminate the (single-element) list of tx frames */
  1805. qdf_nbuf_set_next(skb, NULL);
  1806. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1807. if (ret) {
  1808. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1809. "%s: Failed to tx", __func__);
  1810. return ret;
  1811. }
  1812. return NULL;
  1813. }
  1814. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1815. /**
  1816. * dp_ipa_is_target_ready() - check if target is ready or not
  1817. * @soc: datapath soc handle
  1818. *
  1819. * Return: true if target is ready
  1820. */
  1821. static inline
  1822. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1823. {
  1824. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1825. return false;
  1826. else
  1827. return true;
  1828. }
  1829. /**
  1830. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1831. * @dev: Pointer to device
  1832. * @txrx_smmu: WDI TX/RX configuration
  1833. *
  1834. * Return: None
  1835. */
  1836. static inline
  1837. void dp_ipa_update_txr_db_status(struct device *dev,
  1838. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1839. {
  1840. int pcie_slot = pld_get_pci_slot(dev);
  1841. if (pcie_slot)
  1842. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1843. else
  1844. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1845. }
  1846. /**
  1847. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1848. * @dev: Pointer to device
  1849. * @txrx_smmu: WDI TX/RX configuration
  1850. *
  1851. * Return: None
  1852. */
  1853. static inline
  1854. void dp_ipa_update_evt_db_status(struct device *dev,
  1855. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1856. {
  1857. int pcie_slot = pld_get_pci_slot(dev);
  1858. if (pcie_slot)
  1859. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1860. else
  1861. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1862. }
  1863. #else
  1864. static inline
  1865. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1866. {
  1867. return true;
  1868. }
  1869. static inline
  1870. void dp_ipa_update_txr_db_status(struct device *dev,
  1871. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1872. {
  1873. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1874. }
  1875. static inline
  1876. void dp_ipa_update_evt_db_status(struct device *dev,
  1877. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1878. {
  1879. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1880. }
  1881. #endif
  1882. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1883. {
  1884. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1885. struct dp_pdev *pdev =
  1886. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1887. uint32_t ix0;
  1888. uint32_t ix2;
  1889. uint8_t ix_map[8];
  1890. if (!pdev) {
  1891. dp_err("Invalid instance");
  1892. return QDF_STATUS_E_FAILURE;
  1893. }
  1894. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1895. return QDF_STATUS_SUCCESS;
  1896. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1897. return QDF_STATUS_E_AGAIN;
  1898. if (!dp_ipa_is_target_ready(soc))
  1899. return QDF_STATUS_E_AGAIN;
  1900. /* Call HAL API to remap REO rings to REO2IPA ring */
  1901. ix_map[0] = REO_REMAP_SW1;
  1902. ix_map[1] = REO_REMAP_SW4;
  1903. ix_map[2] = REO_REMAP_SW1;
  1904. if (wlan_ipa_is_vlan_enabled())
  1905. ix_map[3] = REO_REMAP_SW3;
  1906. else
  1907. ix_map[3] = REO_REMAP_SW4;
  1908. ix_map[4] = REO_REMAP_SW4;
  1909. ix_map[5] = REO_REMAP_RELEASE;
  1910. ix_map[6] = REO_REMAP_FW;
  1911. ix_map[7] = REO_REMAP_FW;
  1912. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1913. ix_map);
  1914. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1915. ix_map[0] = REO_REMAP_SW4;
  1916. ix_map[1] = REO_REMAP_SW4;
  1917. ix_map[2] = REO_REMAP_SW4;
  1918. ix_map[3] = REO_REMAP_SW4;
  1919. ix_map[4] = REO_REMAP_SW4;
  1920. ix_map[5] = REO_REMAP_SW4;
  1921. ix_map[6] = REO_REMAP_SW4;
  1922. ix_map[7] = REO_REMAP_SW4;
  1923. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1924. ix_map);
  1925. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1926. &ix2, &ix2);
  1927. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1928. } else {
  1929. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1930. NULL, NULL);
  1931. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1932. }
  1933. return QDF_STATUS_SUCCESS;
  1934. }
  1935. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1936. {
  1937. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1938. struct dp_pdev *pdev =
  1939. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1940. uint8_t ix0_map[8];
  1941. uint32_t ix0;
  1942. uint32_t ix1;
  1943. uint32_t ix2;
  1944. uint32_t ix3;
  1945. if (!pdev) {
  1946. dp_err("Invalid instance");
  1947. return QDF_STATUS_E_FAILURE;
  1948. }
  1949. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1950. return QDF_STATUS_SUCCESS;
  1951. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1952. return QDF_STATUS_E_AGAIN;
  1953. if (!dp_ipa_is_target_ready(soc))
  1954. return QDF_STATUS_E_AGAIN;
  1955. ix0_map[0] = REO_REMAP_SW1;
  1956. ix0_map[1] = REO_REMAP_SW1;
  1957. ix0_map[2] = REO_REMAP_SW2;
  1958. ix0_map[3] = REO_REMAP_SW3;
  1959. ix0_map[4] = REO_REMAP_SW2;
  1960. ix0_map[5] = REO_REMAP_RELEASE;
  1961. ix0_map[6] = REO_REMAP_FW;
  1962. ix0_map[7] = REO_REMAP_FW;
  1963. /* Call HAL API to remap REO rings to REO2IPA ring */
  1964. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1965. ix0_map);
  1966. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1967. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1968. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1969. &ix2, &ix3);
  1970. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1971. } else {
  1972. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1973. NULL, NULL);
  1974. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1975. }
  1976. return QDF_STATUS_SUCCESS;
  1977. }
  1978. /* This should be configurable per H/W configuration enable status */
  1979. #define L3_HEADER_PADDING 2
  1980. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1981. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1982. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1983. static inline void dp_setup_mcc_sys_pipes(
  1984. qdf_ipa_sys_connect_params_t *sys_in,
  1985. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1986. {
  1987. int i = 0;
  1988. /* Setup MCC sys pipe */
  1989. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1990. DP_IPA_MAX_IFACE;
  1991. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  1992. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  1993. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  1994. }
  1995. #else
  1996. static inline void dp_setup_mcc_sys_pipes(
  1997. qdf_ipa_sys_connect_params_t *sys_in,
  1998. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1999. {
  2000. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  2001. }
  2002. #endif
  2003. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  2004. struct dp_ipa_resources *ipa_res,
  2005. qdf_ipa_wdi_pipe_setup_info_t *tx,
  2006. bool over_gsi)
  2007. {
  2008. if (over_gsi)
  2009. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  2010. else
  2011. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2012. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2013. qdf_mem_get_dma_addr(soc->osdev,
  2014. &ipa_res->tx_comp_ring.mem_info);
  2015. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2016. qdf_mem_get_dma_size(soc->osdev,
  2017. &ipa_res->tx_comp_ring.mem_info);
  2018. /* WBM Tail Pointer Address */
  2019. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2020. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2021. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2022. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2023. qdf_mem_get_dma_addr(soc->osdev,
  2024. &ipa_res->tx_ring.mem_info);
  2025. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2026. qdf_mem_get_dma_size(soc->osdev,
  2027. &ipa_res->tx_ring.mem_info);
  2028. /* TCL Head Pointer Address */
  2029. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2030. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2031. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2032. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2033. ipa_res->tx_num_alloc_buffer;
  2034. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2035. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2036. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2037. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2038. }
  2039. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2040. struct dp_ipa_resources *ipa_res,
  2041. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2042. bool over_gsi)
  2043. {
  2044. if (over_gsi)
  2045. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2046. IPA_CLIENT_WLAN2_PROD;
  2047. else
  2048. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2049. IPA_CLIENT_WLAN1_PROD;
  2050. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2051. qdf_mem_get_dma_addr(soc->osdev,
  2052. &ipa_res->rx_rdy_ring.mem_info);
  2053. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2054. qdf_mem_get_dma_size(soc->osdev,
  2055. &ipa_res->rx_rdy_ring.mem_info);
  2056. /* REO Tail Pointer Address */
  2057. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2058. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2059. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2060. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2061. qdf_mem_get_dma_addr(soc->osdev,
  2062. &ipa_res->rx_refill_ring.mem_info);
  2063. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2064. qdf_mem_get_dma_size(soc->osdev,
  2065. &ipa_res->rx_refill_ring.mem_info);
  2066. /* FW Head Pointer Address */
  2067. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2068. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2069. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2070. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2071. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2072. }
  2073. static void
  2074. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2075. struct dp_ipa_resources *ipa_res,
  2076. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2077. bool over_gsi,
  2078. qdf_ipa_wdi_hdl_t hdl)
  2079. {
  2080. if (over_gsi) {
  2081. if (hdl == DP_IPA_HDL_FIRST)
  2082. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2083. IPA_CLIENT_WLAN2_CONS;
  2084. else if (hdl == DP_IPA_HDL_SECOND)
  2085. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2086. IPA_CLIENT_WLAN4_CONS;
  2087. else if (hdl == DP_IPA_HDL_THIRD)
  2088. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2089. IPA_CLIENT_WLAN1_CONS;
  2090. } else {
  2091. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2092. IPA_CLIENT_WLAN1_CONS;
  2093. }
  2094. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2095. &ipa_res->tx_comp_ring.sgtable,
  2096. sizeof(sgtable_t));
  2097. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2098. qdf_mem_get_dma_size(soc->osdev,
  2099. &ipa_res->tx_comp_ring.mem_info);
  2100. /* WBM Tail Pointer Address */
  2101. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2102. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2103. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2104. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2105. &ipa_res->tx_ring.sgtable,
  2106. sizeof(sgtable_t));
  2107. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2108. qdf_mem_get_dma_size(soc->osdev,
  2109. &ipa_res->tx_ring.mem_info);
  2110. /* TCL Head Pointer Address */
  2111. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2112. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2113. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2114. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2115. ipa_res->tx_num_alloc_buffer;
  2116. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2117. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2118. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2119. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2120. }
  2121. static void
  2122. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2123. struct dp_ipa_resources *ipa_res,
  2124. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2125. bool over_gsi,
  2126. qdf_ipa_wdi_hdl_t hdl)
  2127. {
  2128. if (over_gsi) {
  2129. if (hdl == DP_IPA_HDL_FIRST)
  2130. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2131. IPA_CLIENT_WLAN2_PROD;
  2132. else if (hdl == DP_IPA_HDL_SECOND)
  2133. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2134. IPA_CLIENT_WLAN3_PROD;
  2135. else if (hdl == DP_IPA_HDL_THIRD)
  2136. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2137. IPA_CLIENT_WLAN1_PROD;
  2138. } else {
  2139. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2140. IPA_CLIENT_WLAN1_PROD;
  2141. }
  2142. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2143. &ipa_res->rx_rdy_ring.sgtable,
  2144. sizeof(sgtable_t));
  2145. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2146. qdf_mem_get_dma_size(soc->osdev,
  2147. &ipa_res->rx_rdy_ring.mem_info);
  2148. /* REO Tail Pointer Address */
  2149. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2150. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2151. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2152. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2153. &ipa_res->rx_refill_ring.sgtable,
  2154. sizeof(sgtable_t));
  2155. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2156. qdf_mem_get_dma_size(soc->osdev,
  2157. &ipa_res->rx_refill_ring.mem_info);
  2158. /* FW Head Pointer Address */
  2159. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2160. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2161. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2162. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2163. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2164. }
  2165. #ifdef IPA_WDI3_VLAN_SUPPORT
  2166. /**
  2167. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2168. * @soc: data path soc handle
  2169. * @ipa_res: ipa resource pointer
  2170. * @rx_smmu: smmu pipe info handle
  2171. * @over_gsi: flag for IPA offload over gsi
  2172. * @hdl: ipa registered handle
  2173. *
  2174. * Return: none
  2175. */
  2176. static void
  2177. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2178. struct dp_ipa_resources *ipa_res,
  2179. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2180. bool over_gsi,
  2181. qdf_ipa_wdi_hdl_t hdl)
  2182. {
  2183. if (!wlan_ipa_is_vlan_enabled())
  2184. return;
  2185. if (over_gsi) {
  2186. if (hdl == DP_IPA_HDL_FIRST)
  2187. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2188. IPA_CLIENT_WLAN2_PROD1;
  2189. else if (hdl == DP_IPA_HDL_SECOND)
  2190. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2191. IPA_CLIENT_WLAN3_PROD1;
  2192. else if (hdl == DP_IPA_HDL_THIRD)
  2193. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2194. IPA_CLIENT_WLAN1_PROD1;
  2195. } else {
  2196. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2197. IPA_CLIENT_WLAN1_PROD;
  2198. }
  2199. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2200. &ipa_res->rx_alt_rdy_ring.sgtable,
  2201. sizeof(sgtable_t));
  2202. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2203. qdf_mem_get_dma_size(soc->osdev,
  2204. &ipa_res->rx_alt_rdy_ring.mem_info);
  2205. /* REO Tail Pointer Address */
  2206. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2207. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2208. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2209. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2210. &ipa_res->rx_alt_refill_ring.sgtable,
  2211. sizeof(sgtable_t));
  2212. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2213. qdf_mem_get_dma_size(soc->osdev,
  2214. &ipa_res->rx_alt_refill_ring.mem_info);
  2215. /* FW Head Pointer Address */
  2216. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2217. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2218. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2219. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2220. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2221. }
  2222. /**
  2223. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2224. * @soc: data path soc handle
  2225. * @ipa_res: ipa resource pointer
  2226. * @rx: pipe info handle
  2227. * @over_gsi: flag for IPA offload over gsi
  2228. * @hdl: ipa registered handle
  2229. *
  2230. * Return: none
  2231. */
  2232. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2233. struct dp_ipa_resources *ipa_res,
  2234. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2235. bool over_gsi,
  2236. qdf_ipa_wdi_hdl_t hdl)
  2237. {
  2238. if (!wlan_ipa_is_vlan_enabled())
  2239. return;
  2240. if (over_gsi) {
  2241. if (hdl == DP_IPA_HDL_FIRST)
  2242. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2243. IPA_CLIENT_WLAN2_PROD1;
  2244. else if (hdl == DP_IPA_HDL_SECOND)
  2245. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2246. IPA_CLIENT_WLAN3_PROD1;
  2247. else if (hdl == DP_IPA_HDL_THIRD)
  2248. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2249. IPA_CLIENT_WLAN1_PROD1;
  2250. } else {
  2251. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2252. IPA_CLIENT_WLAN1_PROD;
  2253. }
  2254. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2255. qdf_mem_get_dma_addr(soc->osdev,
  2256. &ipa_res->rx_alt_rdy_ring.mem_info);
  2257. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2258. qdf_mem_get_dma_size(soc->osdev,
  2259. &ipa_res->rx_alt_rdy_ring.mem_info);
  2260. /* REO Tail Pointer Address */
  2261. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2262. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2263. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2264. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2265. qdf_mem_get_dma_addr(soc->osdev,
  2266. &ipa_res->rx_alt_refill_ring.mem_info);
  2267. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2268. qdf_mem_get_dma_size(soc->osdev,
  2269. &ipa_res->rx_alt_refill_ring.mem_info);
  2270. /* FW Head Pointer Address */
  2271. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2272. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2273. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2274. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2275. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2276. }
  2277. /**
  2278. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2279. * @soc: data path soc handle
  2280. * @res: ipa resource pointer
  2281. * @in: pipe in handle
  2282. * @over_gsi: flag for IPA offload over gsi
  2283. * @hdl: ipa registered handle
  2284. *
  2285. * Return: none
  2286. */
  2287. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2288. struct dp_ipa_resources *res,
  2289. qdf_ipa_wdi_conn_in_params_t *in,
  2290. bool over_gsi,
  2291. qdf_ipa_wdi_hdl_t hdl)
  2292. {
  2293. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2294. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2295. qdf_ipa_ep_cfg_t *rx_cfg;
  2296. if (!wlan_ipa_is_vlan_enabled())
  2297. return;
  2298. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2299. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2300. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2301. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2302. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2303. over_gsi, hdl);
  2304. } else {
  2305. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2306. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2307. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2308. }
  2309. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2310. /* Update with wds len(96) + 4 if wds support is enabled */
  2311. if (ucfg_ipa_is_wds_enabled())
  2312. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2313. else
  2314. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2315. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2316. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2317. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2318. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2319. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2320. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2321. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2322. }
  2323. /**
  2324. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2325. * @res: ipa resource pointer
  2326. * @out: pipe out handle
  2327. *
  2328. * Return: none
  2329. */
  2330. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2331. qdf_ipa_wdi_conn_out_params_t *out)
  2332. {
  2333. if (!wlan_ipa_is_vlan_enabled())
  2334. return;
  2335. res->rx_alt_ready_doorbell_paddr =
  2336. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2337. dp_debug("Setting DB 0x%x for RX alt pipe",
  2338. res->rx_alt_ready_doorbell_paddr);
  2339. }
  2340. #else
  2341. static inline
  2342. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2343. struct dp_ipa_resources *res,
  2344. qdf_ipa_wdi_conn_in_params_t *in,
  2345. bool over_gsi,
  2346. qdf_ipa_wdi_hdl_t hdl)
  2347. { }
  2348. static inline
  2349. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2350. qdf_ipa_wdi_conn_out_params_t *out)
  2351. { }
  2352. #endif
  2353. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2354. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2355. void *ipa_wdi_meter_notifier_cb,
  2356. uint32_t ipa_desc_size, void *ipa_priv,
  2357. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2358. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2359. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2360. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2361. void *ipa_ast_notify_cb)
  2362. {
  2363. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2364. struct dp_pdev *pdev =
  2365. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2366. struct dp_ipa_resources *ipa_res;
  2367. qdf_ipa_ep_cfg_t *tx_cfg;
  2368. qdf_ipa_ep_cfg_t *rx_cfg;
  2369. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2370. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2371. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2372. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2373. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2374. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2375. int ret;
  2376. if (!pdev) {
  2377. dp_err("Invalid instance");
  2378. return QDF_STATUS_E_FAILURE;
  2379. }
  2380. ipa_res = &pdev->ipa_resource;
  2381. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2382. return QDF_STATUS_SUCCESS;
  2383. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2384. if (!pipe_in)
  2385. return QDF_STATUS_E_NOMEM;
  2386. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2387. if (is_smmu_enabled)
  2388. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2389. else
  2390. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2391. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2392. /* TX PIPE */
  2393. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2394. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2395. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2396. } else {
  2397. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2398. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2399. }
  2400. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2401. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2402. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2403. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2404. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2405. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2406. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2407. /*
  2408. * Transfer Ring: WBM Ring
  2409. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2410. * Event Ring: TCL ring
  2411. * Event Ring Doorbell PA: TCL Head Pointer Address
  2412. */
  2413. if (is_smmu_enabled)
  2414. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2415. else
  2416. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2417. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2418. /* RX PIPE */
  2419. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2420. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2421. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2422. } else {
  2423. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2424. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2425. }
  2426. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2427. if (ucfg_ipa_is_wds_enabled())
  2428. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2429. else
  2430. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2431. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2432. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2433. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2434. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2435. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2436. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2437. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2438. /*
  2439. * Transfer Ring: REO Ring
  2440. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2441. * Event Ring: FW ring
  2442. * Event Ring Doorbell PA: FW Head Pointer Address
  2443. */
  2444. if (is_smmu_enabled)
  2445. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2446. else
  2447. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2448. /* setup 2nd rx pipe */
  2449. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2450. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2451. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2452. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2453. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2454. /* Connect WDI IPA PIPEs */
  2455. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2456. if (ret) {
  2457. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2458. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2459. __func__, ret);
  2460. qdf_mem_free(pipe_in);
  2461. return QDF_STATUS_E_FAILURE;
  2462. }
  2463. /* IPA uC Doorbell registers */
  2464. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2465. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2466. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2467. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2468. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2469. ipa_res->is_db_ddr_mapped =
  2470. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2471. soc->ipa_first_tx_db_access = true;
  2472. qdf_mem_free(pipe_in);
  2473. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2474. soc->ipa_rx_buf_map_lock_initialized = true;
  2475. return QDF_STATUS_SUCCESS;
  2476. }
  2477. #ifdef IPA_WDI3_VLAN_SUPPORT
  2478. /**
  2479. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2480. * @in: pipe in handle
  2481. *
  2482. * Return: none
  2483. */
  2484. static inline
  2485. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2486. {
  2487. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2488. }
  2489. /**
  2490. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2491. * @in: pipe in handle
  2492. * @hdr: pointer to hdr
  2493. *
  2494. * Return: none
  2495. */
  2496. static inline
  2497. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2498. qdf_ipa_wdi_hdr_info_t *hdr)
  2499. {
  2500. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2501. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2502. }
  2503. /**
  2504. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2505. * @in: pipe in handle
  2506. * @hdr: pointer to hdr
  2507. *
  2508. * Return: none
  2509. */
  2510. static inline
  2511. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2512. qdf_ipa_wdi_hdr_info_t *hdr)
  2513. {
  2514. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2515. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2516. }
  2517. #else
  2518. static inline
  2519. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2520. { }
  2521. static inline
  2522. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2523. qdf_ipa_wdi_hdr_info_t *hdr)
  2524. { }
  2525. static inline
  2526. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2527. qdf_ipa_wdi_hdr_info_t *hdr)
  2528. { }
  2529. #endif
  2530. #ifdef IPA_WDS_EASYMESH_FEATURE
  2531. /**
  2532. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2533. * @hdr_info: Header info
  2534. *
  2535. * Return: None
  2536. */
  2537. static inline void
  2538. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2539. {
  2540. if (ucfg_ipa_is_wds_enabled())
  2541. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2542. IPA_HDR_L2_ETHERNET_II_AST;
  2543. else
  2544. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2545. IPA_HDR_L2_ETHERNET_II;
  2546. }
  2547. /**
  2548. * dp_ipa_setup_meta_data_mask() - Pass meta data mask to IPA
  2549. * @in: ipa in params
  2550. *
  2551. * Pass meta data mask to IPA.
  2552. *
  2553. * Return: none
  2554. */
  2555. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2556. {
  2557. if (ucfg_ipa_is_wds_enabled())
  2558. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_AST_META_DATA_MASK;
  2559. else
  2560. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2561. }
  2562. #else
  2563. static inline void
  2564. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2565. {
  2566. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2567. }
  2568. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2569. {
  2570. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2571. }
  2572. #endif
  2573. #ifdef IPA_WDI3_VLAN_SUPPORT
  2574. /**
  2575. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2576. * @hdr_info: Header info
  2577. *
  2578. * Return: None
  2579. */
  2580. static inline void
  2581. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2582. {
  2583. if (ucfg_ipa_is_wds_enabled())
  2584. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2585. IPA_HDR_L2_802_1Q_AST;
  2586. else
  2587. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2588. IPA_HDR_L2_802_1Q;
  2589. }
  2590. #else
  2591. static inline void
  2592. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2593. { }
  2594. #endif
  2595. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2596. qdf_ipa_client_type_t prod_client,
  2597. qdf_ipa_client_type_t cons_client,
  2598. uint8_t session_id, bool is_ipv6_enabled,
  2599. qdf_ipa_wdi_hdl_t hdl)
  2600. {
  2601. qdf_ipa_wdi_reg_intf_in_params_t in;
  2602. qdf_ipa_wdi_hdr_info_t hdr_info;
  2603. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2604. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2605. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2606. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2607. int ret = -EINVAL;
  2608. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2609. /* Need to reset the values to 0 as all the fields are not
  2610. * updated in the Header, Unused fields will be set to 0.
  2611. */
  2612. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2613. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2614. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2615. QDF_MAC_ADDR_REF(mac_addr));
  2616. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2617. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2618. /* IPV4 header */
  2619. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2620. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2621. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2622. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2623. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2624. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2625. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2626. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2627. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2628. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2629. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2630. dp_ipa_setup_meta_data_mask(&in);
  2631. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2632. dp_ipa_setup_iface_session_id(&in, session_id);
  2633. dp_debug("registering for session_id: %u", session_id);
  2634. /* IPV6 header */
  2635. if (is_ipv6_enabled) {
  2636. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2637. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2638. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2639. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2640. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2641. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2642. }
  2643. if (wlan_ipa_is_vlan_enabled()) {
  2644. /* Add vlan specific headers if vlan supporti is enabled */
  2645. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2646. dp_ipa_set_rx1_used(&in);
  2647. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2648. /* IPV4 Vlan header */
  2649. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2650. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2651. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2652. (uint8_t *)&uc_tx_vlan_hdr;
  2653. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2654. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2655. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2656. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2657. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2658. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2659. /* IPV6 Vlan header */
  2660. if (is_ipv6_enabled) {
  2661. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2662. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2663. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2664. qdf_htons(ETH_P_8021Q);
  2665. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2666. qdf_htons(ETH_P_IPV6);
  2667. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2668. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2669. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2670. }
  2671. }
  2672. ret = qdf_ipa_wdi_reg_intf(&in);
  2673. if (ret) {
  2674. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2675. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2676. __func__, ret);
  2677. return QDF_STATUS_E_FAILURE;
  2678. }
  2679. return QDF_STATUS_SUCCESS;
  2680. }
  2681. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2682. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2683. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2684. void *ipa_wdi_meter_notifier_cb,
  2685. uint32_t ipa_desc_size, void *ipa_priv,
  2686. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2687. uint32_t *rx_pipe_handle)
  2688. {
  2689. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2690. struct dp_pdev *pdev =
  2691. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2692. struct dp_ipa_resources *ipa_res;
  2693. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2694. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2695. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2696. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2697. struct tcl_data_cmd *tcl_desc_ptr;
  2698. uint8_t *desc_addr;
  2699. uint32_t desc_size;
  2700. int ret;
  2701. if (!pdev) {
  2702. dp_err("Invalid instance");
  2703. return QDF_STATUS_E_FAILURE;
  2704. }
  2705. ipa_res = &pdev->ipa_resource;
  2706. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2707. return QDF_STATUS_SUCCESS;
  2708. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2709. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2710. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2711. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2712. /* TX PIPE */
  2713. /*
  2714. * Transfer Ring: WBM Ring
  2715. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2716. * Event Ring: TCL ring
  2717. * Event Ring Doorbell PA: TCL Head Pointer Address
  2718. */
  2719. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2720. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2721. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2722. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2723. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2724. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2725. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2726. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2727. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2728. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2729. ipa_res->tx_comp_ring_base_paddr;
  2730. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2731. ipa_res->tx_comp_ring_size;
  2732. /* WBM Tail Pointer Address */
  2733. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2734. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2735. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2736. ipa_res->tx_ring_base_paddr;
  2737. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2738. /* TCL Head Pointer Address */
  2739. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2740. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2741. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2742. ipa_res->tx_num_alloc_buffer;
  2743. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2744. /* Preprogram TCL descriptor */
  2745. desc_addr =
  2746. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2747. desc_size = sizeof(struct tcl_data_cmd);
  2748. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2749. tcl_desc_ptr = (struct tcl_data_cmd *)
  2750. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2751. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2752. HAL_RX_BUF_RBM_SW2_BM;
  2753. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2754. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2755. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2756. /* RX PIPE */
  2757. /*
  2758. * Transfer Ring: REO Ring
  2759. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2760. * Event Ring: FW ring
  2761. * Event Ring Doorbell PA: FW Head Pointer Address
  2762. */
  2763. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2764. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2765. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2766. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2767. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2768. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2769. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2770. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2771. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2772. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2773. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2774. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2775. ipa_res->rx_rdy_ring_base_paddr;
  2776. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2777. ipa_res->rx_rdy_ring_size;
  2778. /* REO Tail Pointer Address */
  2779. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2780. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2781. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2782. ipa_res->rx_refill_ring_base_paddr;
  2783. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2784. ipa_res->rx_refill_ring_size;
  2785. /* FW Head Pointer Address */
  2786. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2787. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2788. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2789. L3_HEADER_PADDING;
  2790. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2791. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2792. /* Connect WDI IPA PIPE */
  2793. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2794. if (ret) {
  2795. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2796. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2797. __func__, ret);
  2798. return QDF_STATUS_E_FAILURE;
  2799. }
  2800. /* IPA uC Doorbell registers */
  2801. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2802. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2803. __func__,
  2804. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2805. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2806. ipa_res->tx_comp_doorbell_paddr =
  2807. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2808. ipa_res->tx_comp_doorbell_vaddr =
  2809. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2810. ipa_res->rx_ready_doorbell_paddr =
  2811. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2812. soc->ipa_first_tx_db_access = true;
  2813. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2814. soc->ipa_rx_buf_map_lock_initialized = true;
  2815. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2816. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2817. __func__,
  2818. "transfer_ring_base_pa",
  2819. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2820. "transfer_ring_size",
  2821. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2822. "transfer_ring_doorbell_pa",
  2823. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2824. "event_ring_base_pa",
  2825. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2826. "event_ring_size",
  2827. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2828. "event_ring_doorbell_pa",
  2829. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2830. "num_pkt_buffers",
  2831. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2832. "tx_comp_doorbell_paddr",
  2833. (void *)ipa_res->tx_comp_doorbell_paddr);
  2834. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2835. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2836. __func__,
  2837. "transfer_ring_base_pa",
  2838. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2839. "transfer_ring_size",
  2840. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2841. "transfer_ring_doorbell_pa",
  2842. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2843. "event_ring_base_pa",
  2844. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2845. "event_ring_size",
  2846. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2847. "event_ring_doorbell_pa",
  2848. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2849. "num_pkt_buffers",
  2850. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2851. "tx_comp_doorbell_paddr",
  2852. (void *)ipa_res->rx_ready_doorbell_paddr);
  2853. return QDF_STATUS_SUCCESS;
  2854. }
  2855. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2856. qdf_ipa_client_type_t prod_client,
  2857. qdf_ipa_client_type_t cons_client,
  2858. uint8_t session_id, bool is_ipv6_enabled,
  2859. qdf_ipa_wdi_hdl_t hdl)
  2860. {
  2861. qdf_ipa_wdi_reg_intf_in_params_t in;
  2862. qdf_ipa_wdi_hdr_info_t hdr_info;
  2863. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2864. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2865. int ret = -EINVAL;
  2866. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2867. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2868. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2869. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2870. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2871. /* IPV4 header */
  2872. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2873. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2874. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2875. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2876. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2877. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2878. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2879. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2880. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2881. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2882. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2883. htonl(session_id << 16);
  2884. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2885. /* IPV6 header */
  2886. if (is_ipv6_enabled) {
  2887. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2888. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2889. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2890. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2891. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2892. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2893. }
  2894. ret = qdf_ipa_wdi_reg_intf(&in);
  2895. if (ret) {
  2896. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2897. ret);
  2898. return QDF_STATUS_E_FAILURE;
  2899. }
  2900. return QDF_STATUS_SUCCESS;
  2901. }
  2902. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2903. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2904. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2905. qdf_ipa_wdi_hdl_t hdl)
  2906. {
  2907. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2908. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2909. struct dp_pdev *pdev;
  2910. int ret;
  2911. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2912. if (ret) {
  2913. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2914. ret);
  2915. status = QDF_STATUS_E_FAILURE;
  2916. }
  2917. if (soc->ipa_rx_buf_map_lock_initialized) {
  2918. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2919. soc->ipa_rx_buf_map_lock_initialized = false;
  2920. }
  2921. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2922. if (qdf_unlikely(!pdev)) {
  2923. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2924. status = QDF_STATUS_E_FAILURE;
  2925. goto exit;
  2926. }
  2927. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2928. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2929. exit:
  2930. return status;
  2931. }
  2932. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2933. qdf_ipa_wdi_hdl_t hdl)
  2934. {
  2935. int ret;
  2936. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2937. if (ret) {
  2938. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2939. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2940. __func__, ret);
  2941. return QDF_STATUS_E_FAILURE;
  2942. }
  2943. return QDF_STATUS_SUCCESS;
  2944. }
  2945. #ifdef IPA_SET_RESET_TX_DB_PA
  2946. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2947. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2948. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2949. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2950. #else
  2951. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2952. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2953. #endif
  2954. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2955. qdf_ipa_wdi_hdl_t hdl)
  2956. {
  2957. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2958. struct dp_pdev *pdev =
  2959. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2960. struct dp_ipa_resources *ipa_res;
  2961. QDF_STATUS result;
  2962. if (!pdev) {
  2963. dp_err("Invalid instance");
  2964. return QDF_STATUS_E_FAILURE;
  2965. }
  2966. ipa_res = &pdev->ipa_resource;
  2967. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2968. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2969. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  2970. qdf_atomic_set(&soc->ipa_map_allowed, 1);
  2971. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2972. __func__, __LINE__);
  2973. }
  2974. result = qdf_ipa_wdi_enable_pipes(hdl);
  2975. if (result) {
  2976. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2977. "%s: Enable WDI PIPE fail, code %d",
  2978. __func__, result);
  2979. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2980. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2981. if (qdf_atomic_read(&soc->ipa_map_allowed)) {
  2982. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  2983. dp_ipa_handle_rx_buf_pool_smmu_mapping(
  2984. soc, pdev, false, __func__, __LINE__);
  2985. }
  2986. return QDF_STATUS_E_FAILURE;
  2987. }
  2988. if (soc->ipa_first_tx_db_access) {
  2989. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2990. soc->ipa_first_tx_db_access = false;
  2991. }
  2992. return QDF_STATUS_SUCCESS;
  2993. }
  2994. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2995. qdf_ipa_wdi_hdl_t hdl)
  2996. {
  2997. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2998. struct dp_pdev *pdev =
  2999. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3000. QDF_STATUS result;
  3001. struct dp_ipa_resources *ipa_res;
  3002. if (!pdev) {
  3003. dp_err("Invalid instance");
  3004. return QDF_STATUS_E_FAILURE;
  3005. }
  3006. ipa_res = &pdev->ipa_resource;
  3007. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  3008. /*
  3009. * Reset the tx completion doorbell address before invoking IPA disable
  3010. * pipes API to ensure that there is no access to IPA tx doorbell
  3011. * address post disable pipes.
  3012. */
  3013. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3014. result = qdf_ipa_wdi_disable_pipes(hdl);
  3015. if (result) {
  3016. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3017. "%s: Disable WDI PIPE fail, code %d",
  3018. __func__, result);
  3019. qdf_assert_always(0);
  3020. return QDF_STATUS_E_FAILURE;
  3021. }
  3022. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3023. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  3024. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  3025. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  3026. __func__, __LINE__);
  3027. }
  3028. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  3029. }
  3030. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  3031. qdf_ipa_wdi_hdl_t hdl)
  3032. {
  3033. qdf_ipa_wdi_perf_profile_t profile;
  3034. QDF_STATUS result;
  3035. profile.client = client;
  3036. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  3037. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  3038. if (result) {
  3039. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3040. "%s: ipa_wdi_set_perf_profile fail, code %d",
  3041. __func__, result);
  3042. return QDF_STATUS_E_FAILURE;
  3043. }
  3044. return QDF_STATUS_SUCCESS;
  3045. }
  3046. #ifdef QCA_SUPPORT_WDS_EXTENDED
  3047. /**
  3048. * dp_ipa_rx_wdsext_iface() - Forward RX exception packets to wdsext interface
  3049. * @soc_hdl: data path soc handle
  3050. * @peer_id: Peer id to get respective peer
  3051. * @skb: socket buffer
  3052. *
  3053. * Return: true on success, else false
  3054. */
  3055. bool dp_ipa_rx_wdsext_iface(struct cdp_soc_t *soc_hdl, uint8_t peer_id,
  3056. qdf_nbuf_t skb)
  3057. {
  3058. struct dp_txrx_peer *txrx_peer;
  3059. dp_txrx_ref_handle txrx_ref_handle = NULL;
  3060. struct dp_soc *dp_soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3061. bool status = false;
  3062. txrx_peer = dp_tgt_txrx_peer_get_ref_by_id(soc_hdl, peer_id,
  3063. &txrx_ref_handle,
  3064. DP_MOD_ID_IPA);
  3065. if (qdf_likely(txrx_peer)) {
  3066. if (dp_rx_deliver_to_stack_ext(dp_soc, txrx_peer->vdev,
  3067. txrx_peer, skb)
  3068. status = true;
  3069. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_IPA);
  3070. }
  3071. return status;
  3072. }
  3073. #endif
  3074. /**
  3075. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3076. * @pdev: pdev
  3077. * @vdev: vdev
  3078. * @nbuf: skb
  3079. *
  3080. * Return: nbuf if TX fails and NULL if TX succeeds
  3081. */
  3082. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3083. struct dp_vdev *vdev,
  3084. qdf_nbuf_t nbuf)
  3085. {
  3086. struct dp_peer *vdev_peer;
  3087. uint16_t len;
  3088. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3089. if (qdf_unlikely(!vdev_peer))
  3090. return nbuf;
  3091. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3092. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3093. return nbuf;
  3094. }
  3095. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3096. len = qdf_nbuf_len(nbuf);
  3097. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3098. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3099. rx.intra_bss.fail, 1, len,
  3100. 0);
  3101. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3102. return nbuf;
  3103. }
  3104. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3105. rx.intra_bss.pkts, 1, len, 0);
  3106. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3107. return NULL;
  3108. }
  3109. #ifdef IPA_OPT_WIFI_DP
  3110. /**
  3111. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3112. *
  3113. * @soc_hdl: cdp soc
  3114. * @flt_params: filter tuple
  3115. *
  3116. * Return: QDF_STATUS
  3117. */
  3118. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3119. void *flt_params)
  3120. {
  3121. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3122. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3123. }
  3124. /**
  3125. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3126. * add/remove result to ipa
  3127. *
  3128. * @flt0_rslt : result for filter0 add/remove
  3129. * @flt1_rslt : result for filter1 add/remove
  3130. *
  3131. * Return: void
  3132. */
  3133. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3134. {
  3135. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3136. }
  3137. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3138. {
  3139. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3140. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3141. int response = 0;
  3142. response = hif_prevent_l1((hal_soc->hif_handle));
  3143. return response;
  3144. }
  3145. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3146. {
  3147. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3148. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3149. hif_allow_l1(hal_soc->hif_handle);
  3150. }
  3151. /**
  3152. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3153. * notification to ipa
  3154. *
  3155. * @flt0_rslt : result for filter0 release
  3156. * @flt1_rslt : result for filter1 release
  3157. *
  3158. *Return: void
  3159. */
  3160. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3161. {
  3162. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3163. }
  3164. /**
  3165. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3166. * notification to ipa
  3167. *
  3168. *@is_success : result of filter reservatiom
  3169. *
  3170. *Return: void
  3171. */
  3172. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3173. {
  3174. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3175. }
  3176. #endif
  3177. #ifdef IPA_WDS_EASYMESH_FEATURE
  3178. /**
  3179. * dp_ipa_peer_check() - Check for peer for given mac
  3180. * @soc: dp soc object
  3181. * @peer_mac_addr: peer mac address
  3182. * @vdev_id: vdev id
  3183. *
  3184. * Return: true if peer is found, else false
  3185. */
  3186. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3187. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3188. {
  3189. struct dp_ast_entry *ast_entry = NULL;
  3190. struct dp_peer *peer = NULL;
  3191. qdf_spin_lock_bh(&soc->ast_lock);
  3192. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3193. if ((!ast_entry) ||
  3194. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3195. qdf_spin_unlock_bh(&soc->ast_lock);
  3196. return false;
  3197. }
  3198. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3199. DP_MOD_ID_IPA);
  3200. if (!peer) {
  3201. qdf_spin_unlock_bh(&soc->ast_lock);
  3202. return false;
  3203. } else {
  3204. if (peer->vdev->vdev_id == vdev_id) {
  3205. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3206. qdf_spin_unlock_bh(&soc->ast_lock);
  3207. return true;
  3208. }
  3209. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3210. qdf_spin_unlock_bh(&soc->ast_lock);
  3211. return false;
  3212. }
  3213. }
  3214. #else
  3215. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3216. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3217. {
  3218. struct cdp_peer_info peer_info = {0};
  3219. struct dp_peer *peer = NULL;
  3220. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3221. CDP_WILD_PEER_TYPE);
  3222. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3223. if (peer) {
  3224. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3225. return true;
  3226. } else {
  3227. return false;
  3228. }
  3229. }
  3230. #endif
  3231. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3232. qdf_nbuf_t nbuf, bool *fwd_success)
  3233. {
  3234. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3235. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3236. DP_MOD_ID_IPA);
  3237. struct dp_pdev *pdev;
  3238. qdf_nbuf_t nbuf_copy;
  3239. uint8_t da_is_bcmc;
  3240. struct ethhdr *eh;
  3241. bool status = false;
  3242. *fwd_success = false; /* set default as failure */
  3243. /*
  3244. * WDI 3.0 skb->cb[] info from IPA driver
  3245. * skb->cb[0] = vdev_id
  3246. * skb->cb[1].bit#1 = da_is_bcmc
  3247. */
  3248. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3249. if (qdf_unlikely(!vdev))
  3250. return false;
  3251. pdev = vdev->pdev;
  3252. if (qdf_unlikely(!pdev))
  3253. goto out;
  3254. /* no fwd for station mode and just pass up to stack */
  3255. if (vdev->opmode == wlan_op_mode_sta)
  3256. goto out;
  3257. if (da_is_bcmc) {
  3258. nbuf_copy = qdf_nbuf_copy(nbuf);
  3259. if (!nbuf_copy)
  3260. goto out;
  3261. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3262. qdf_nbuf_free(nbuf_copy);
  3263. else
  3264. *fwd_success = true;
  3265. /* return false to pass original pkt up to stack */
  3266. goto out;
  3267. }
  3268. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3269. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3270. goto out;
  3271. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3272. goto out;
  3273. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3274. goto out;
  3275. /*
  3276. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3277. * Need to add skb to internal tracking table to avoid nbuf memory
  3278. * leak check for unallocated skb.
  3279. */
  3280. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3281. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3282. qdf_nbuf_free(nbuf);
  3283. else
  3284. *fwd_success = true;
  3285. status = true;
  3286. out:
  3287. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3288. return status;
  3289. }
  3290. #ifdef MDM_PLATFORM
  3291. bool dp_ipa_is_mdm_platform(void)
  3292. {
  3293. return true;
  3294. }
  3295. #else
  3296. bool dp_ipa_is_mdm_platform(void)
  3297. {
  3298. return false;
  3299. }
  3300. #endif
  3301. /**
  3302. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3303. * @soc: soc
  3304. * @nbuf: source skb
  3305. *
  3306. * Return: new nbuf if success and otherwise NULL
  3307. */
  3308. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3309. qdf_nbuf_t nbuf)
  3310. {
  3311. uint8_t *src_nbuf_data;
  3312. uint8_t *dst_nbuf_data;
  3313. qdf_nbuf_t dst_nbuf;
  3314. qdf_nbuf_t temp_nbuf = nbuf;
  3315. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3316. bool is_nbuf_head = true;
  3317. uint32_t copy_len = 0;
  3318. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  3319. RX_BUFFER_RESERVATION,
  3320. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3321. if (!dst_nbuf) {
  3322. dp_err_rl("nbuf allocate fail");
  3323. return NULL;
  3324. }
  3325. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  3326. qdf_nbuf_free(dst_nbuf);
  3327. dp_err_rl("nbuf is jumbo data");
  3328. return NULL;
  3329. }
  3330. /* prepeare to copy all data into new skb */
  3331. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3332. while (temp_nbuf) {
  3333. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3334. /* first head nbuf */
  3335. if (is_nbuf_head) {
  3336. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3337. soc->rx_pkt_tlv_size);
  3338. /* leave extra 2 bytes L3_HEADER_PADDING */
  3339. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3340. L3_HEADER_PADDING);
  3341. src_nbuf_data += soc->rx_pkt_tlv_size;
  3342. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3343. soc->rx_pkt_tlv_size;
  3344. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3345. is_nbuf_head = false;
  3346. } else {
  3347. copy_len = qdf_nbuf_len(temp_nbuf);
  3348. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3349. }
  3350. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3351. dst_nbuf_data += copy_len;
  3352. }
  3353. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3354. /* copy is done, free original nbuf */
  3355. qdf_nbuf_free(nbuf);
  3356. return dst_nbuf;
  3357. }
  3358. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3359. {
  3360. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3361. return nbuf;
  3362. /* WLAN IPA is run-time disabled */
  3363. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3364. return nbuf;
  3365. if (!qdf_nbuf_is_frag(nbuf))
  3366. return nbuf;
  3367. /* linearize skb for IPA */
  3368. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3369. }
  3370. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3371. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3372. const char *func, uint32_t line)
  3373. {
  3374. QDF_STATUS ret;
  3375. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3376. struct dp_pdev *pdev =
  3377. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3378. if (!pdev) {
  3379. dp_err("Invalid instance");
  3380. return QDF_STATUS_E_FAILURE;
  3381. }
  3382. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3383. dp_debug("SMMU S1 disabled");
  3384. return QDF_STATUS_SUCCESS;
  3385. }
  3386. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3387. if (ret)
  3388. return ret;
  3389. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3390. if (ret)
  3391. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3392. return ret;
  3393. }
  3394. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3395. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3396. uint32_t line)
  3397. {
  3398. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3399. struct dp_pdev *pdev =
  3400. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3401. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3402. dp_debug("SMMU S1 disabled");
  3403. return QDF_STATUS_SUCCESS;
  3404. }
  3405. if (!pdev) {
  3406. dp_err("Invalid pdev instance pdev_id:%d", pdev_id);
  3407. return QDF_STATUS_E_FAILURE;
  3408. }
  3409. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3410. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3411. return QDF_STATUS_E_FAILURE;
  3412. return QDF_STATUS_SUCCESS;
  3413. }
  3414. QDF_STATUS dp_ipa_rx_buf_pool_smmu_mapping(
  3415. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3416. bool create, const char *func, uint32_t line)
  3417. {
  3418. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3419. struct dp_pdev *pdev =
  3420. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3421. if (!pdev) {
  3422. dp_err("Invalid instance");
  3423. return QDF_STATUS_E_FAILURE;
  3424. }
  3425. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3426. dp_debug("SMMU S1 disabled");
  3427. return QDF_STATUS_SUCCESS;
  3428. }
  3429. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, create, func, line);
  3430. return QDF_STATUS_SUCCESS;
  3431. }
  3432. #ifdef IPA_WDS_EASYMESH_FEATURE
  3433. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3434. qdf_ipa_ast_info_type_t *data)
  3435. {
  3436. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3437. uint8_t *rx_tlv_hdr;
  3438. struct dp_peer *peer;
  3439. struct hal_rx_msdu_metadata msdu_metadata;
  3440. qdf_ipa_ast_info_type_t *ast_info;
  3441. if (!data) {
  3442. dp_err("Data is NULL !!!");
  3443. return QDF_STATUS_E_FAILURE;
  3444. }
  3445. ast_info = data;
  3446. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3447. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3448. DP_MOD_ID_IPA);
  3449. if (!peer) {
  3450. dp_err("Peer is NULL !!!!");
  3451. return QDF_STATUS_E_FAILURE;
  3452. }
  3453. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3454. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3455. ast_info->mac_addr_ad4_valid,
  3456. ast_info->first_msdu_in_mpdu_flag);
  3457. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3458. return QDF_STATUS_SUCCESS;
  3459. }
  3460. #endif
  3461. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3462. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3463. uint8_t vdev_id, uint8_t *peer_mac,
  3464. qdf_nbuf_t nbuf)
  3465. {
  3466. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3467. peer_mac, 0, vdev_id,
  3468. DP_MOD_ID_IPA);
  3469. struct dp_txrx_peer *txrx_peer;
  3470. uint8_t da_is_bcmc;
  3471. qdf_ether_header_t *eh;
  3472. if (!peer)
  3473. return QDF_STATUS_E_FAILURE;
  3474. txrx_peer = dp_get_txrx_peer(peer);
  3475. if (!txrx_peer) {
  3476. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3477. return QDF_STATUS_E_FAILURE;
  3478. }
  3479. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3480. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3481. if (da_is_bcmc) {
  3482. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3483. qdf_nbuf_len(nbuf), 0);
  3484. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3485. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3486. 1, qdf_nbuf_len(nbuf), 0);
  3487. }
  3488. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3489. return QDF_STATUS_SUCCESS;
  3490. }
  3491. void
  3492. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3493. {
  3494. uint8_t i = 0;
  3495. struct dp_rx_tid *rx_tid = NULL;
  3496. struct cdp_pkt_info rx_total = {0};
  3497. struct dp_txrx_peer *txrx_peer = NULL;
  3498. if (!peer->rx_tid)
  3499. return;
  3500. txrx_peer = dp_get_txrx_peer(peer);
  3501. if (!txrx_peer)
  3502. return;
  3503. for (i = 0; i < DP_MAX_TIDS; i++) {
  3504. rx_tid = &peer->rx_tid[i];
  3505. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3506. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3507. }
  3508. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3509. rx_total.num, 0);
  3510. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3511. rx_total.bytes, 0);
  3512. }
  3513. /**
  3514. * dp_ipa_update_vdev_stats(): update vdev stats
  3515. * @soc: soc handle
  3516. * @srcobj: DP_PEER object
  3517. * @arg: point to vdev stats structure
  3518. *
  3519. * Return: void
  3520. */
  3521. static inline
  3522. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3523. void *arg)
  3524. {
  3525. dp_peer_aggregate_tid_stats(srcobj);
  3526. dp_update_vdev_stats(soc, srcobj, arg);
  3527. }
  3528. /**
  3529. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3530. * @vdev: Data path vdev
  3531. * @vdev_stats: buffer to hold vdev stats
  3532. *
  3533. * Return: void
  3534. */
  3535. static inline
  3536. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3537. struct cdp_vdev_stats *vdev_stats)
  3538. {
  3539. struct dp_soc *soc = NULL;
  3540. if (!vdev || !vdev->pdev)
  3541. return;
  3542. soc = vdev->pdev->soc;
  3543. dp_update_vdev_ingress_stats(vdev);
  3544. qdf_mem_copy(vdev_stats, &vdev->stats, sizeof(vdev->stats));
  3545. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3546. DP_MOD_ID_GENERIC_STATS);
  3547. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3548. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3549. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3550. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3551. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3552. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3553. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3554. vdev_stats->rx.multicast.num;
  3555. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3556. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3557. vdev_stats->rx.multicast.bytes;
  3558. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3559. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3560. }
  3561. /**
  3562. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3563. * @pdev: Data path pdev
  3564. *
  3565. * Return: void
  3566. */
  3567. static inline
  3568. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3569. {
  3570. struct dp_vdev *vdev = NULL;
  3571. struct dp_soc *soc;
  3572. struct cdp_vdev_stats *vdev_stats =
  3573. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3574. if (!vdev_stats) {
  3575. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3576. pdev->soc);
  3577. return;
  3578. }
  3579. soc = pdev->soc;
  3580. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3581. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3582. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3583. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3584. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3585. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3586. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3587. dp_update_pdev_stats(pdev, vdev_stats);
  3588. dp_update_pdev_ingress_stats(pdev, vdev);
  3589. }
  3590. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3591. qdf_mem_free(vdev_stats);
  3592. }
  3593. /**
  3594. * dp_ipa_get_peer_stats - Get peer stats
  3595. * @peer: Data path peer
  3596. * @peer_stats: buffer to hold peer stats
  3597. *
  3598. * Return: void
  3599. */
  3600. static
  3601. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3602. struct cdp_peer_stats *peer_stats)
  3603. {
  3604. dp_peer_aggregate_tid_stats(peer);
  3605. dp_get_peer_stats(peer, peer_stats);
  3606. peer_stats->tx.tx_success.num =
  3607. peer_stats->tx.tx_ucast_success.num;
  3608. peer_stats->tx.tx_success.bytes =
  3609. peer_stats->tx.tx_ucast_success.bytes;
  3610. peer_stats->tx.ucast.num =
  3611. peer_stats->tx.tx_ucast_total.num;
  3612. peer_stats->tx.ucast.bytes =
  3613. peer_stats->tx.tx_ucast_total.bytes;
  3614. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3615. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3616. peer_stats->rx.multicast.num;
  3617. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3618. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3619. peer_stats->rx.multicast.bytes;
  3620. }
  3621. QDF_STATUS
  3622. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3623. struct cdp_pdev_stats *pdev_stats)
  3624. {
  3625. struct dp_pdev *pdev =
  3626. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3627. pdev_id);
  3628. if (!pdev)
  3629. return QDF_STATUS_E_FAILURE;
  3630. dp_ipa_aggregate_pdev_stats(pdev);
  3631. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3632. return QDF_STATUS_SUCCESS;
  3633. }
  3634. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3635. void *buf, bool is_aggregate)
  3636. {
  3637. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3638. struct cdp_vdev_stats *vdev_stats;
  3639. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3640. DP_MOD_ID_IPA);
  3641. if (!vdev)
  3642. return 1;
  3643. vdev_stats = (struct cdp_vdev_stats *)buf;
  3644. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3645. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3646. return 0;
  3647. }
  3648. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3649. uint8_t *peer_mac,
  3650. struct cdp_peer_stats *peer_stats)
  3651. {
  3652. struct dp_peer *peer = NULL;
  3653. struct cdp_peer_info peer_info = { 0 };
  3654. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3655. CDP_WILD_PEER_TYPE);
  3656. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3657. DP_MOD_ID_IPA);
  3658. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3659. if (!peer)
  3660. return QDF_STATUS_E_FAILURE;
  3661. dp_ipa_get_peer_stats(peer, peer_stats);
  3662. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3663. return QDF_STATUS_SUCCESS;
  3664. }
  3665. #endif
  3666. /**
  3667. * dp_ipa_get_wdi_version() - Get WDI version
  3668. * @soc_hdl: data path soc handle
  3669. * @wdi_ver: Out parameter for wdi version
  3670. *
  3671. * Get WDI version based on soc arch
  3672. *
  3673. * Return: None
  3674. */
  3675. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3676. {
  3677. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3678. if (soc->arch_ops.ipa_get_wdi_ver)
  3679. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3680. else
  3681. *wdi_ver = IPA_WDI_3;
  3682. }
  3683. #endif