49dfccf2601c2e0c331fc89be19653e26f6efbfe

Lane enable register reset is not required any delay to reflect the change. This change removes the unnecesaary delay from lane_enable register. Also, adding 1us of delay between back to back write in SW reset register along with condition based refelction of delay. CRs-Fixed: 2671221 Change-Id: I010570045a97fc1489a84d22ebd39df6f6f14f0a Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
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