sde_hw_dspp.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <drm/msm_drm_pp.h>
  7. #include "sde_hw_mdss.h"
  8. #include "sde_hwio.h"
  9. #include "sde_hw_catalog.h"
  10. #include "sde_hw_dspp.h"
  11. #include "sde_hw_color_processing.h"
  12. #include "sde_dbg.h"
  13. #include "sde_ad4.h"
  14. #include "sde_hw_rc.h"
  15. #include "sde_kms.h"
  16. #define DSPP_VALID_START_OFF 0x800
  17. static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
  18. struct sde_mdss_cfg *m,
  19. void __iomem *addr,
  20. struct sde_hw_blk_reg_map *b)
  21. {
  22. int i;
  23. if (!m || !addr || !b)
  24. return ERR_PTR(-EINVAL);
  25. for (i = 0; i < m->dspp_count; i++) {
  26. if (dspp == m->dspp[i].id) {
  27. b->base_off = addr;
  28. b->blk_off = m->dspp[i].base;
  29. b->length = m->dspp[i].len;
  30. b->hw_rev = m->hw_rev;
  31. b->log_mask = SDE_DBG_MASK_DSPP;
  32. return &m->dspp[i];
  33. }
  34. }
  35. return ERR_PTR(-EINVAL);
  36. }
  37. static void dspp_igc(struct sde_hw_dspp *c)
  38. {
  39. int ret = 0;
  40. if (c->cap->sblk->igc.version == SDE_COLOR_PROCESS_VER(0x3, 0x1)) {
  41. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  42. if (!ret)
  43. c->ops.setup_igc = reg_dmav1_setup_dspp_igcv31;
  44. else
  45. c->ops.setup_igc = sde_setup_dspp_igcv3;
  46. } else if (c->cap->sblk->igc.version ==
  47. SDE_COLOR_PROCESS_VER(0x4, 0x0)) {
  48. c->ops.setup_igc = NULL;
  49. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  50. if (!ret)
  51. c->ops.setup_igc = reg_dmav2_setup_dspp_igcv4;
  52. }
  53. }
  54. static void dspp_pcc(struct sde_hw_dspp *c)
  55. {
  56. int ret = 0;
  57. if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
  58. c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;
  59. else if (c->cap->sblk->pcc.version ==
  60. (SDE_COLOR_PROCESS_VER(0x4, 0x0))) {
  61. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
  62. if (!ret)
  63. c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4;
  64. else
  65. c->ops.setup_pcc = sde_setup_dspp_pccv4;
  66. } else if (c->cap->sblk->pcc.version ==
  67. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  68. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
  69. if (!ret)
  70. c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv5;
  71. else
  72. c->ops.setup_pcc = NULL;
  73. }
  74. }
  75. static void dspp_gc(struct sde_hw_dspp *c)
  76. {
  77. int ret = 0;
  78. if (c->cap->sblk->gc.version == SDE_COLOR_PROCESS_VER(0x1, 8)) {
  79. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GC, c->idx);
  80. if (!ret)
  81. c->ops.setup_gc = reg_dmav1_setup_dspp_gcv18;
  82. /**
  83. * programming for v18 through ahb is same as v17,
  84. * hence assign v17 function
  85. */
  86. else
  87. c->ops.setup_gc = sde_setup_dspp_gc_v1_7;
  88. }
  89. }
  90. static void dspp_hsic(struct sde_hw_dspp *c)
  91. {
  92. int ret = 0;
  93. if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  94. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_HSIC, c->idx);
  95. if (!ret)
  96. c->ops.setup_pa_hsic = reg_dmav1_setup_dspp_pa_hsicv17;
  97. else
  98. c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17;
  99. }
  100. }
  101. static void dspp_memcolor(struct sde_hw_dspp *c)
  102. {
  103. int ret = 0;
  104. if (c->cap->sblk->memcolor.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  105. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_MEMCOLOR, c->idx);
  106. if (!ret) {
  107. c->ops.setup_pa_memcol_skin =
  108. reg_dmav1_setup_dspp_memcol_skinv17;
  109. c->ops.setup_pa_memcol_sky =
  110. reg_dmav1_setup_dspp_memcol_skyv17;
  111. c->ops.setup_pa_memcol_foliage =
  112. reg_dmav1_setup_dspp_memcol_folv17;
  113. c->ops.setup_pa_memcol_prot =
  114. reg_dmav1_setup_dspp_memcol_protv17;
  115. } else {
  116. c->ops.setup_pa_memcol_skin =
  117. sde_setup_dspp_memcol_skin_v17;
  118. c->ops.setup_pa_memcol_sky =
  119. sde_setup_dspp_memcol_sky_v17;
  120. c->ops.setup_pa_memcol_foliage =
  121. sde_setup_dspp_memcol_foliage_v17;
  122. c->ops.setup_pa_memcol_prot =
  123. sde_setup_dspp_memcol_prot_v17;
  124. }
  125. }
  126. }
  127. static void dspp_sixzone(struct sde_hw_dspp *c)
  128. {
  129. int ret = 0;
  130. if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  131. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SIXZONE, c->idx);
  132. if (!ret)
  133. c->ops.setup_sixzone = reg_dmav1_setup_dspp_sixzonev17;
  134. else
  135. c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17;
  136. } else if (c->cap->sblk->sixzone.version ==
  137. SDE_COLOR_PROCESS_VER(0x2, 0x0)) {
  138. c->ops.setup_sixzone = NULL;
  139. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_SIXZONE, c->idx);
  140. if (!ret)
  141. c->ops.setup_sixzone = reg_dmav2_setup_dspp_sixzonev2;
  142. }
  143. }
  144. static void dspp_gamut(struct sde_hw_dspp *c)
  145. {
  146. int ret = 0;
  147. if (c->cap->sblk->gamut.version == SDE_COLOR_PROCESS_VER(0x4, 0)) {
  148. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  149. if (!ret)
  150. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv4;
  151. else
  152. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv4;
  153. } else if (c->cap->sblk->gamut.version ==
  154. SDE_COLOR_PROCESS_VER(0x4, 1)) {
  155. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  156. if (!ret)
  157. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv41;
  158. else
  159. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv41;
  160. } else if (c->cap->sblk->gamut.version ==
  161. SDE_COLOR_PROCESS_VER(0x4, 2)) {
  162. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  163. c->ops.setup_gamut = NULL;
  164. if (!ret)
  165. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv42;
  166. } else if (c->cap->sblk->gamut.version ==
  167. SDE_COLOR_PROCESS_VER(0x4, 3)) {
  168. c->ops.setup_gamut = NULL;
  169. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  170. if (!ret)
  171. c->ops.setup_gamut = reg_dmav2_setup_dspp_3d_gamutv43;
  172. }
  173. }
  174. static void dspp_dither(struct sde_hw_dspp *c)
  175. {
  176. if (c->cap->sblk->dither.version == SDE_COLOR_PROCESS_VER(0x1, 0x7))
  177. c->ops.setup_pa_dither = sde_setup_dspp_dither_v1_7;
  178. }
  179. static void dspp_hist(struct sde_hw_dspp *c)
  180. {
  181. if (c->cap->sblk->hist.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  182. c->ops.setup_histogram = sde_setup_dspp_hist_v1_7;
  183. c->ops.read_histogram = sde_read_dspp_hist_v1_7;
  184. c->ops.lock_histogram = sde_lock_dspp_hist_v1_7;
  185. }
  186. }
  187. static void dspp_vlut(struct sde_hw_dspp *c)
  188. {
  189. int ret = 0;
  190. if (c->cap->sblk->vlut.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  191. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;
  192. } else if (c->cap->sblk->vlut.version ==
  193. (SDE_COLOR_PROCESS_VER(0x1, 0x8))) {
  194. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_VLUT, c->idx);
  195. if (!ret)
  196. c->ops.setup_vlut = reg_dmav1_setup_dspp_vlutv18;
  197. else
  198. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_8;
  199. }
  200. }
  201. static void dspp_ad(struct sde_hw_dspp *c)
  202. {
  203. if (c->cap->sblk->ad.version == SDE_COLOR_PROCESS_VER(4, 0)) {
  204. c->ops.setup_ad = sde_setup_dspp_ad4;
  205. c->ops.ad_read_intr_resp = sde_read_intr_resp_ad4;
  206. c->ops.validate_ad = sde_validate_dspp_ad4;
  207. }
  208. }
  209. static void dspp_ltm(struct sde_hw_dspp *c)
  210. {
  211. int ret = 0;
  212. if (c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x0) ||
  213. c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x1) ||
  214. c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x2)) {
  215. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_INIT, c->idx);
  216. if (!ret)
  217. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_ROI, c->idx);
  218. if (!ret)
  219. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_VLUT, c->idx);
  220. if (!ret) {
  221. if (c->cap->sblk->ltm.version ==
  222. SDE_COLOR_PROCESS_VER(0x1, 0x2)) {
  223. c->ops.setup_ltm_vlut =
  224. reg_dmav1_setup_ltm_vlutv1_2;
  225. c->ops.setup_ltm_hist_ctrl =
  226. sde_setup_dspp_ltm_hist_ctrlv1_2;
  227. c->ops.clear_ltm_merge_mode =
  228. sde_ltm_clear_merge_modev1_2;
  229. } else {
  230. c->ops.setup_ltm_vlut =
  231. reg_dmav1_setup_ltm_vlutv1;
  232. c->ops.setup_ltm_hist_ctrl =
  233. sde_setup_dspp_ltm_hist_ctrlv1;
  234. c->ops.clear_ltm_merge_mode =
  235. sde_ltm_clear_merge_mode;
  236. }
  237. c->ops.setup_ltm_init = reg_dmav1_setup_ltm_initv1;
  238. c->ops.setup_ltm_roi = reg_dmav1_setup_ltm_roiv1;
  239. c->ops.setup_ltm_thresh = sde_setup_dspp_ltm_threshv1;
  240. c->ops.setup_ltm_hist_buffer =
  241. sde_setup_dspp_ltm_hist_bufferv1;
  242. c->ops.ltm_read_intr_status = sde_ltm_read_intr_status;
  243. } else {
  244. c->ops.setup_ltm_init = NULL;
  245. c->ops.setup_ltm_roi = NULL;
  246. c->ops.setup_ltm_vlut = NULL;
  247. c->ops.setup_ltm_thresh = NULL;
  248. c->ops.setup_ltm_hist_ctrl = NULL;
  249. c->ops.setup_ltm_hist_buffer = NULL;
  250. c->ops.ltm_read_intr_status = NULL;
  251. c->ops.clear_ltm_merge_mode = NULL;
  252. }
  253. if (!ret && (c->cap->sblk->ltm.version ==
  254. SDE_COLOR_PROCESS_VER(0x1, 0x1) ||
  255. c->cap->sblk->ltm.version ==
  256. SDE_COLOR_PROCESS_VER(0x1, 0x2)))
  257. c->ltm_checksum_support = true;
  258. else
  259. c->ltm_checksum_support = false;
  260. }
  261. }
  262. static void dspp_rc(struct sde_hw_dspp *c)
  263. {
  264. int ret = 0;
  265. if (!c) {
  266. SDE_ERROR("invalid arguments\n");
  267. return;
  268. }
  269. if (c->cap->sblk->rc.version == SDE_COLOR_PROCESS_VER(0x1, 0x0) ||
  270. c->cap->sblk->rc.version == SDE_COLOR_PROCESS_VER(0x1, 0x1)) {
  271. ret = sde_hw_rc_init(c);
  272. if (ret) {
  273. SDE_ERROR("rc init failed, ret %d\n", ret);
  274. return;
  275. }
  276. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_RC, c->idx);
  277. if (!ret)
  278. c->ops.setup_rc_data =
  279. sde_hw_rc_setup_data_dma;
  280. else
  281. c->ops.setup_rc_data =
  282. sde_hw_rc_setup_data_ahb;
  283. c->ops.validate_rc_mask = sde_hw_rc_check_mask;
  284. c->ops.setup_rc_mask = sde_hw_rc_setup_mask;
  285. c->ops.validate_rc_pu_roi = sde_hw_rc_check_pu_roi;
  286. c->ops.setup_rc_pu_roi = sde_hw_rc_setup_pu_roi;
  287. }
  288. }
  289. static void dspp_spr(struct sde_hw_dspp *c)
  290. {
  291. int ret = 0;
  292. if (!c) {
  293. SDE_ERROR("invalid arguments\n");
  294. return;
  295. }
  296. c->ops.setup_spr_init_config = NULL;
  297. c->ops.setup_spr_pu_config = NULL;
  298. if (c->cap->sblk->spr.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  299. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SPR, c->idx);
  300. if (ret) {
  301. SDE_ERROR("regdma init failed for spr, ret %d\n", ret);
  302. return;
  303. }
  304. c->ops.setup_spr_init_config = reg_dmav1_setup_spr_init_cfgv1;
  305. c->ops.setup_spr_pu_config = reg_dmav1_setup_spr_pu_cfgv1;
  306. }
  307. }
  308. static void dspp_demura(struct sde_hw_dspp *c)
  309. {
  310. int ret;
  311. if (c->cap->sblk->demura.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  312. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA, c->idx);
  313. c->ops.setup_demura_cfg = NULL;
  314. c->ops.setup_demura_backlight_cfg = NULL;
  315. if (!ret) {
  316. c->ops.setup_demura_cfg = reg_dmav1_setup_demurav1;
  317. c->ops.setup_demura_backlight_cfg =
  318. sde_demura_backlight_cfg;
  319. c->ops.demura_read_plane_status =
  320. sde_demura_read_plane_status;
  321. c->ops.setup_demura_pu_config = sde_demura_pu_cfg;
  322. }
  323. }
  324. }
  325. static void (*dspp_blocks[SDE_DSPP_MAX])(struct sde_hw_dspp *c);
  326. static void _init_dspp_ops(void)
  327. {
  328. dspp_blocks[SDE_DSPP_IGC] = dspp_igc;
  329. dspp_blocks[SDE_DSPP_PCC] = dspp_pcc;
  330. dspp_blocks[SDE_DSPP_GC] = dspp_gc;
  331. dspp_blocks[SDE_DSPP_HSIC] = dspp_hsic;
  332. dspp_blocks[SDE_DSPP_MEMCOLOR] = dspp_memcolor;
  333. dspp_blocks[SDE_DSPP_SIXZONE] = dspp_sixzone;
  334. dspp_blocks[SDE_DSPP_GAMUT] = dspp_gamut;
  335. dspp_blocks[SDE_DSPP_DITHER] = dspp_dither;
  336. dspp_blocks[SDE_DSPP_HIST] = dspp_hist;
  337. dspp_blocks[SDE_DSPP_VLUT] = dspp_vlut;
  338. dspp_blocks[SDE_DSPP_AD] = dspp_ad;
  339. dspp_blocks[SDE_DSPP_LTM] = dspp_ltm;
  340. dspp_blocks[SDE_DSPP_RC] = dspp_rc;
  341. dspp_blocks[SDE_DSPP_SPR] = dspp_spr;
  342. dspp_blocks[SDE_DSPP_DEMURA] = dspp_demura;
  343. }
  344. static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
  345. {
  346. int i = 0;
  347. if (!c->cap->sblk)
  348. return;
  349. for (i = 0; i < SDE_DSPP_MAX; i++) {
  350. if (!test_bit(i, &features))
  351. continue;
  352. if (dspp_blocks[i])
  353. dspp_blocks[i](c);
  354. }
  355. }
  356. struct sde_hw_blk_reg_map *sde_hw_dspp_init(enum sde_dspp idx,
  357. void __iomem *addr,
  358. struct sde_mdss_cfg *m)
  359. {
  360. struct sde_hw_dspp *c;
  361. struct sde_dspp_cfg *cfg;
  362. char buf[256];
  363. if (!addr || !m)
  364. return ERR_PTR(-EINVAL);
  365. c = kzalloc(sizeof(*c), GFP_KERNEL);
  366. if (!c)
  367. return ERR_PTR(-ENOMEM);
  368. cfg = _dspp_offset(idx, m, addr, &c->hw);
  369. if (IS_ERR_OR_NULL(cfg)) {
  370. kfree(c);
  371. return ERR_PTR(-EINVAL);
  372. }
  373. /* Populate DSPP Top HW block */
  374. c->hw_top.base_off = addr;
  375. c->hw_top.blk_off = m->dspp_top.base;
  376. c->hw_top.length = m->dspp_top.len;
  377. c->hw_top.hw_rev = m->hw_rev;
  378. c->hw_top.log_mask = SDE_DBG_MASK_DSPP;
  379. /* Assign ops */
  380. c->idx = idx;
  381. c->cap = cfg;
  382. _init_dspp_ops();
  383. _setup_dspp_ops(c, c->cap->features);
  384. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
  385. c->hw.blk_off + DSPP_VALID_START_OFF,
  386. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  387. if ((cfg->sblk->ltm.id == SDE_DSPP_LTM) && cfg->sblk->ltm.base) {
  388. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "LTM",
  389. c->hw.blk_off + cfg->sblk->ltm.base,
  390. c->hw.blk_off + cfg->sblk->ltm.base + 0xC4,
  391. c->hw.xin_id);
  392. }
  393. if ((cfg->sblk->rc.id == SDE_DSPP_RC) && cfg->sblk->rc.base) {
  394. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "rc", c->idx - DSPP_0);
  395. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  396. c->hw.blk_off + cfg->sblk->rc.base,
  397. c->hw.blk_off + cfg->sblk->rc.base +
  398. cfg->sblk->rc.len, c->hw.xin_id);
  399. }
  400. if ((cfg->sblk->spr.id == SDE_DSPP_SPR) && cfg->sblk->spr.base) {
  401. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "spr", c->idx - DSPP_0);
  402. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  403. c->hw.blk_off + cfg->sblk->spr.base,
  404. c->hw.blk_off + cfg->sblk->spr.base +
  405. cfg->sblk->spr.len, c->hw.xin_id);
  406. }
  407. if ((cfg->sblk->demura.id == SDE_DSPP_DEMURA) &&
  408. cfg->sblk->demura.base) {
  409. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "demura",
  410. c->idx - DSPP_0);
  411. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  412. c->hw.blk_off + cfg->sblk->demura.base,
  413. c->hw.blk_off + cfg->sblk->demura.base +
  414. cfg->sblk->demura.len, c->hw.xin_id);
  415. }
  416. return &c->hw;
  417. }
  418. void sde_hw_dspp_destroy(struct sde_hw_blk_reg_map *hw)
  419. {
  420. struct sde_hw_dspp *dspp;
  421. if (hw) {
  422. dspp = to_sde_hw_dspp(hw);
  423. reg_dmav1_deinit_dspp_ops(dspp->idx);
  424. reg_dmav1_deinit_ltm_ops(dspp->idx);
  425. kfree(dspp);
  426. }
  427. }