dsi_drm.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "dsi-drm:[%s] " fmt, __func__
  6. #include <drm/drm_atomic_helper.h>
  7. #include <drm/drm_atomic.h>
  8. #include "msm_kms.h"
  9. #include "sde_connector.h"
  10. #include "dsi_drm.h"
  11. #include "sde_trace.h"
  12. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  13. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  14. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  15. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  16. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  17. #define DEFAULT_PANEL_PREFILL_LINES 25
  18. static struct dsi_display_mode_priv_info default_priv_info = {
  19. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  20. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  21. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  22. .dsc_enabled = false,
  23. };
  24. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  25. struct dsi_display_mode *dsi_mode)
  26. {
  27. memset(dsi_mode, 0, sizeof(*dsi_mode));
  28. dsi_mode->timing.h_active = drm_mode->hdisplay;
  29. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  30. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  31. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  32. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  33. drm_mode->hdisplay;
  34. dsi_mode->timing.h_skew = drm_mode->hskew;
  35. dsi_mode->timing.v_active = drm_mode->vdisplay;
  36. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  37. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  38. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  39. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  40. drm_mode->vdisplay;
  41. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  42. dsi_mode->pixel_clk_khz = drm_mode->clock;
  43. dsi_mode->priv_info =
  44. (struct dsi_display_mode_priv_info *)drm_mode->private;
  45. if (dsi_mode->priv_info) {
  46. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  47. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  48. }
  49. if (msm_is_mode_seamless(drm_mode))
  50. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  51. if (msm_is_mode_dynamic_fps(drm_mode))
  52. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  53. if (msm_needs_vblank_pre_modeset(drm_mode))
  54. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  55. if (msm_is_mode_seamless_dms(drm_mode))
  56. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  57. if (msm_is_mode_seamless_vrr(drm_mode))
  58. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  59. if (msm_is_mode_seamless_poms(drm_mode))
  60. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  61. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  62. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  63. dsi_mode->timing.h_sync_polarity =
  64. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  65. dsi_mode->timing.v_sync_polarity =
  66. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  67. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  68. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  69. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  70. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  71. }
  72. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  73. struct drm_display_mode *drm_mode)
  74. {
  75. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  76. memset(drm_mode, 0, sizeof(*drm_mode));
  77. drm_mode->hdisplay = dsi_mode->timing.h_active;
  78. drm_mode->hsync_start = drm_mode->hdisplay +
  79. dsi_mode->timing.h_front_porch;
  80. drm_mode->hsync_end = drm_mode->hsync_start +
  81. dsi_mode->timing.h_sync_width;
  82. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  83. drm_mode->hskew = dsi_mode->timing.h_skew;
  84. drm_mode->vdisplay = dsi_mode->timing.v_active;
  85. drm_mode->vsync_start = drm_mode->vdisplay +
  86. dsi_mode->timing.v_front_porch;
  87. drm_mode->vsync_end = drm_mode->vsync_start +
  88. dsi_mode->timing.v_sync_width;
  89. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  90. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  91. drm_mode->clock = dsi_mode->pixel_clk_khz;
  92. drm_mode->private = (int *)dsi_mode->priv_info;
  93. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  94. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  95. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  96. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  97. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  98. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  99. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  100. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  101. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  102. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  103. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  104. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  105. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  106. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  107. if (dsi_mode->timing.h_sync_polarity)
  108. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  109. if (dsi_mode->timing.v_sync_polarity)
  110. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  111. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  112. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  113. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  114. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  115. /* set mode name */
  116. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  117. drm_mode->hdisplay, drm_mode->vdisplay,
  118. drm_mode->vrefresh, drm_mode->clock,
  119. video_mode ? "vid" : "cmd");
  120. }
  121. static int dsi_bridge_attach(struct drm_bridge *bridge)
  122. {
  123. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  124. if (!bridge) {
  125. pr_err("Invalid params\n");
  126. return -EINVAL;
  127. }
  128. pr_debug("[%d] attached\n", c_bridge->id);
  129. return 0;
  130. }
  131. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  132. {
  133. int rc = 0;
  134. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  135. if (!bridge) {
  136. pr_err("Invalid params\n");
  137. return;
  138. }
  139. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  140. pr_err("Incorrect bridge details\n");
  141. return;
  142. }
  143. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  144. /* By this point mode should have been validated through mode_fixup */
  145. rc = dsi_display_set_mode(c_bridge->display,
  146. &(c_bridge->dsi_mode), 0x0);
  147. if (rc) {
  148. pr_err("[%d] failed to perform a mode set, rc=%d\n",
  149. c_bridge->id, rc);
  150. return;
  151. }
  152. if (c_bridge->dsi_mode.dsi_mode_flags &
  153. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  154. DSI_MODE_FLAG_DYN_CLK)) {
  155. pr_debug("[%d] seamless pre-enable\n", c_bridge->id);
  156. return;
  157. }
  158. SDE_ATRACE_BEGIN("dsi_bridge_pre_enable");
  159. rc = dsi_display_prepare(c_bridge->display);
  160. if (rc) {
  161. pr_err("[%d] DSI display prepare failed, rc=%d\n",
  162. c_bridge->id, rc);
  163. SDE_ATRACE_END("dsi_bridge_pre_enable");
  164. return;
  165. }
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. pr_err("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. SDE_ATRACE_END("dsi_bridge_pre_enable");
  175. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  176. if (rc)
  177. pr_err("Continuous splash pipeline cleanup failed, rc=%d\n",
  178. rc);
  179. }
  180. static void dsi_bridge_enable(struct drm_bridge *bridge)
  181. {
  182. int rc = 0;
  183. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  184. struct dsi_display *display;
  185. if (!bridge) {
  186. pr_err("Invalid params\n");
  187. return;
  188. }
  189. if (c_bridge->dsi_mode.dsi_mode_flags &
  190. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  191. DSI_MODE_FLAG_DYN_CLK)) {
  192. pr_debug("[%d] seamless enable\n", c_bridge->id);
  193. return;
  194. }
  195. display = c_bridge->display;
  196. rc = dsi_display_post_enable(display);
  197. if (rc)
  198. pr_err("[%d] DSI display post enabled failed, rc=%d\n",
  199. c_bridge->id, rc);
  200. if (display && display->drm_conn)
  201. sde_connector_helper_bridge_enable(display->drm_conn);
  202. }
  203. static void dsi_bridge_disable(struct drm_bridge *bridge)
  204. {
  205. int rc = 0;
  206. struct dsi_display *display;
  207. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  208. if (!bridge) {
  209. pr_err("Invalid params\n");
  210. return;
  211. }
  212. display = c_bridge->display;
  213. if (display && display->drm_conn) {
  214. if (bridge->encoder->crtc->state->adjusted_mode.private_flags &
  215. MSM_MODE_FLAG_SEAMLESS_POMS) {
  216. display->poms_pending = true;
  217. /* Disable ESD thread, during panel mode switch */
  218. sde_connector_schedule_status_work(display->drm_conn,
  219. false);
  220. } else {
  221. display->poms_pending = false;
  222. sde_connector_helper_bridge_disable(display->drm_conn);
  223. }
  224. }
  225. rc = dsi_display_pre_disable(c_bridge->display);
  226. if (rc) {
  227. pr_err("[%d] DSI display pre disable failed, rc=%d\n",
  228. c_bridge->id, rc);
  229. }
  230. }
  231. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  232. {
  233. int rc = 0;
  234. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  235. if (!bridge) {
  236. pr_err("Invalid params\n");
  237. return;
  238. }
  239. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  240. SDE_ATRACE_BEGIN("dsi_display_disable");
  241. rc = dsi_display_disable(c_bridge->display);
  242. if (rc) {
  243. pr_err("[%d] DSI display disable failed, rc=%d\n",
  244. c_bridge->id, rc);
  245. SDE_ATRACE_END("dsi_display_disable");
  246. return;
  247. }
  248. SDE_ATRACE_END("dsi_display_disable");
  249. rc = dsi_display_unprepare(c_bridge->display);
  250. if (rc) {
  251. pr_err("[%d] DSI display unprepare failed, rc=%d\n",
  252. c_bridge->id, rc);
  253. SDE_ATRACE_END("dsi_bridge_post_disable");
  254. return;
  255. }
  256. SDE_ATRACE_END("dsi_bridge_post_disable");
  257. }
  258. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  259. struct drm_display_mode *mode,
  260. struct drm_display_mode *adjusted_mode)
  261. {
  262. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  263. if (!bridge || !mode || !adjusted_mode) {
  264. pr_err("Invalid params\n");
  265. return;
  266. }
  267. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  268. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  269. /* restore bit_clk_rate also for dynamic clk use cases */
  270. c_bridge->dsi_mode.timing.clk_rate_hz =
  271. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  272. pr_debug("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  273. }
  274. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  275. const struct drm_display_mode *mode,
  276. struct drm_display_mode *adjusted_mode)
  277. {
  278. int rc = 0;
  279. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  280. struct dsi_display *display;
  281. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  282. struct drm_display_mode cur_mode;
  283. struct drm_crtc_state *crtc_state;
  284. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  285. if (!bridge || !mode || !adjusted_mode) {
  286. pr_err("Invalid params\n");
  287. return false;
  288. }
  289. display = c_bridge->display;
  290. if (!display) {
  291. pr_err("Invalid params\n");
  292. return false;
  293. }
  294. /*
  295. * if no timing defined in panel, it must be external mode
  296. * and we'll use empty priv info to populate the mode
  297. */
  298. if (display->panel && !display->panel->num_timing_nodes) {
  299. *adjusted_mode = *mode;
  300. adjusted_mode->private = (int *)&default_priv_info;
  301. adjusted_mode->private_flags = 0;
  302. return true;
  303. }
  304. convert_to_dsi_mode(mode, &dsi_mode);
  305. /*
  306. * retrieve dsi mode from dsi driver's cache since not safe to take
  307. * the drm mode config mutex in all paths
  308. */
  309. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  310. if (rc)
  311. return rc;
  312. /* propagate the private info to the adjusted_mode derived dsi mode */
  313. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  314. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  315. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  316. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  317. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  318. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  319. if (rc) {
  320. pr_err("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  321. return false;
  322. }
  323. if (bridge->encoder && bridge->encoder->crtc &&
  324. crtc_state->crtc) {
  325. convert_to_dsi_mode(&crtc_state->crtc->state->mode,
  326. &cur_dsi_mode);
  327. cur_dsi_mode.timing.dsc_enabled =
  328. dsi_mode.priv_info->dsc_enabled;
  329. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  330. rc = dsi_display_validate_mode_change(c_bridge->display,
  331. &cur_dsi_mode, &dsi_mode);
  332. if (rc) {
  333. pr_err("[%s] seamless mode mismatch failure rc=%d\n",
  334. c_bridge->display->name, rc);
  335. return false;
  336. }
  337. cur_mode = crtc_state->crtc->mode;
  338. /* No panel mode switch when drm pipeline is changing */
  339. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  340. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  341. (crtc_state->enable ==
  342. crtc_state->crtc->state->enable))
  343. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  344. /* No DMS/VRR when drm pipeline is changing */
  345. if (!drm_mode_equal(&cur_mode, adjusted_mode) &&
  346. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  347. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  348. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  349. (!crtc_state->active_changed ||
  350. display->is_cont_splash_enabled))
  351. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  352. }
  353. /* convert back to drm mode, propagating the private info & flags */
  354. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  355. return true;
  356. }
  357. u64 dsi_drm_find_bit_clk_rate(void *display,
  358. const struct drm_display_mode *drm_mode)
  359. {
  360. int i = 0, count = 0;
  361. struct dsi_display *dsi_display = display;
  362. struct dsi_display_mode *dsi_mode;
  363. u64 bit_clk_rate = 0;
  364. if (!dsi_display || !drm_mode)
  365. return 0;
  366. dsi_display_get_mode_count(dsi_display, &count);
  367. for (i = 0; i < count; i++) {
  368. dsi_mode = &dsi_display->modes[i];
  369. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  370. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  371. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  372. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  373. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  374. break;
  375. }
  376. }
  377. return bit_clk_rate;
  378. }
  379. int dsi_conn_get_mode_info(struct drm_connector *connector,
  380. const struct drm_display_mode *drm_mode,
  381. struct msm_mode_info *mode_info,
  382. void *display, const struct msm_resource_caps_info *avail_res)
  383. {
  384. struct dsi_display_mode dsi_mode;
  385. struct dsi_mode_info *timing;
  386. if (!drm_mode || !mode_info)
  387. return -EINVAL;
  388. convert_to_dsi_mode(drm_mode, &dsi_mode);
  389. if (!dsi_mode.priv_info)
  390. return -EINVAL;
  391. memset(mode_info, 0, sizeof(*mode_info));
  392. timing = &dsi_mode.timing;
  393. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  394. mode_info->vtotal = DSI_V_TOTAL(timing);
  395. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  396. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  397. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  398. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  399. mode_info->mdp_transfer_time_us =
  400. dsi_mode.priv_info->mdp_transfer_time_us;
  401. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  402. sizeof(struct msm_display_topology));
  403. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  404. if (dsi_mode.priv_info->dsc_enabled) {
  405. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  406. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  407. sizeof(dsi_mode.priv_info->dsc));
  408. mode_info->comp_info.comp_ratio =
  409. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1;
  410. }
  411. if (dsi_mode.priv_info->roi_caps.enabled) {
  412. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  413. sizeof(dsi_mode.priv_info->roi_caps));
  414. }
  415. return 0;
  416. }
  417. static const struct drm_bridge_funcs dsi_bridge_ops = {
  418. .attach = dsi_bridge_attach,
  419. .mode_fixup = dsi_bridge_mode_fixup,
  420. .pre_enable = dsi_bridge_pre_enable,
  421. .enable = dsi_bridge_enable,
  422. .disable = dsi_bridge_disable,
  423. .post_disable = dsi_bridge_post_disable,
  424. .mode_set = dsi_bridge_mode_set,
  425. };
  426. int dsi_conn_set_info_blob(struct drm_connector *connector,
  427. void *info, void *display, struct msm_mode_info *mode_info)
  428. {
  429. struct dsi_display *dsi_display = display;
  430. struct dsi_panel *panel;
  431. enum dsi_pixel_format fmt;
  432. u32 bpp;
  433. if (!info || !dsi_display)
  434. return -EINVAL;
  435. dsi_display->drm_conn = connector;
  436. sde_kms_info_add_keystr(info,
  437. "display type", dsi_display->display_type);
  438. switch (dsi_display->type) {
  439. case DSI_DISPLAY_SINGLE:
  440. sde_kms_info_add_keystr(info, "display config",
  441. "single display");
  442. break;
  443. case DSI_DISPLAY_EXT_BRIDGE:
  444. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  445. break;
  446. case DSI_DISPLAY_SPLIT:
  447. sde_kms_info_add_keystr(info, "display config",
  448. "split display");
  449. break;
  450. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  451. sde_kms_info_add_keystr(info, "display config",
  452. "split ext bridge");
  453. break;
  454. default:
  455. pr_debug("invalid display type:%d\n", dsi_display->type);
  456. break;
  457. }
  458. if (!dsi_display->panel) {
  459. pr_debug("invalid panel data\n");
  460. goto end;
  461. }
  462. panel = dsi_display->panel;
  463. sde_kms_info_add_keystr(info, "panel name", panel->name);
  464. switch (panel->panel_mode) {
  465. case DSI_OP_VIDEO_MODE:
  466. sde_kms_info_add_keystr(info, "panel mode", "video");
  467. sde_kms_info_add_keystr(info, "qsync support",
  468. panel->qsync_min_fps ? "true" : "false");
  469. break;
  470. case DSI_OP_CMD_MODE:
  471. sde_kms_info_add_keystr(info, "panel mode", "command");
  472. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  473. mode_info->mdp_transfer_time_us);
  474. sde_kms_info_add_keystr(info, "qsync support",
  475. panel->qsync_min_fps ? "true" : "false");
  476. break;
  477. default:
  478. pr_debug("invalid panel type:%d\n", panel->panel_mode);
  479. break;
  480. }
  481. sde_kms_info_add_keystr(info, "dfps support",
  482. panel->dfps_caps.dfps_support ? "true" : "false");
  483. if (panel->dfps_caps.dfps_support) {
  484. sde_kms_info_add_keyint(info, "min_fps",
  485. panel->dfps_caps.min_refresh_rate);
  486. sde_kms_info_add_keyint(info, "max_fps",
  487. panel->dfps_caps.max_refresh_rate);
  488. }
  489. sde_kms_info_add_keystr(info, "dyn bitclk support",
  490. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  491. switch (panel->phy_props.rotation) {
  492. case DSI_PANEL_ROTATE_NONE:
  493. sde_kms_info_add_keystr(info, "panel orientation", "none");
  494. break;
  495. case DSI_PANEL_ROTATE_H_FLIP:
  496. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  497. break;
  498. case DSI_PANEL_ROTATE_V_FLIP:
  499. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  500. break;
  501. case DSI_PANEL_ROTATE_HV_FLIP:
  502. sde_kms_info_add_keystr(info, "panel orientation",
  503. "horz & vert flip");
  504. break;
  505. default:
  506. pr_debug("invalid panel rotation:%d\n",
  507. panel->phy_props.rotation);
  508. break;
  509. }
  510. switch (panel->bl_config.type) {
  511. case DSI_BACKLIGHT_PWM:
  512. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  513. break;
  514. case DSI_BACKLIGHT_WLED:
  515. sde_kms_info_add_keystr(info, "backlight type", "wled");
  516. break;
  517. case DSI_BACKLIGHT_DCS:
  518. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  519. break;
  520. default:
  521. pr_debug("invalid panel backlight type:%d\n",
  522. panel->bl_config.type);
  523. break;
  524. }
  525. if (mode_info && mode_info->roi_caps.enabled) {
  526. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  527. mode_info->roi_caps.num_roi);
  528. sde_kms_info_add_keyint(info, "partial_update_xstart",
  529. mode_info->roi_caps.align.xstart_pix_align);
  530. sde_kms_info_add_keyint(info, "partial_update_walign",
  531. mode_info->roi_caps.align.width_pix_align);
  532. sde_kms_info_add_keyint(info, "partial_update_wmin",
  533. mode_info->roi_caps.align.min_width);
  534. sde_kms_info_add_keyint(info, "partial_update_ystart",
  535. mode_info->roi_caps.align.ystart_pix_align);
  536. sde_kms_info_add_keyint(info, "partial_update_halign",
  537. mode_info->roi_caps.align.height_pix_align);
  538. sde_kms_info_add_keyint(info, "partial_update_hmin",
  539. mode_info->roi_caps.align.min_height);
  540. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  541. mode_info->roi_caps.merge_rois);
  542. }
  543. fmt = dsi_display->config.common_config.dst_format;
  544. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  545. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  546. end:
  547. return 0;
  548. }
  549. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  550. bool force,
  551. void *display)
  552. {
  553. enum drm_connector_status status = connector_status_unknown;
  554. struct msm_display_info info;
  555. int rc;
  556. if (!conn || !display)
  557. return status;
  558. /* get display dsi_info */
  559. memset(&info, 0x0, sizeof(info));
  560. rc = dsi_display_get_info(conn, &info, display);
  561. if (rc) {
  562. pr_err("failed to get display info, rc=%d\n", rc);
  563. return connector_status_disconnected;
  564. }
  565. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  566. status = (info.is_connected ? connector_status_connected :
  567. connector_status_disconnected);
  568. else
  569. status = connector_status_connected;
  570. conn->display_info.width_mm = info.width_mm;
  571. conn->display_info.height_mm = info.height_mm;
  572. return status;
  573. }
  574. void dsi_connector_put_modes(struct drm_connector *connector,
  575. void *display)
  576. {
  577. struct drm_display_mode *drm_mode;
  578. struct dsi_display_mode dsi_mode;
  579. struct dsi_display *dsi_display;
  580. if (!connector || !display)
  581. return;
  582. list_for_each_entry(drm_mode, &connector->modes, head) {
  583. convert_to_dsi_mode(drm_mode, &dsi_mode);
  584. dsi_display_put_mode(display, &dsi_mode);
  585. }
  586. /* free the display structure modes also */
  587. dsi_display = display;
  588. kfree(dsi_display->modes);
  589. dsi_display->modes = NULL;
  590. }
  591. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  592. {
  593. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  594. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  595. u32 dtd_size = 18;
  596. u32 header_size = sizeof(standard_header);
  597. if (!name)
  598. return -EINVAL;
  599. /* Fill standard header */
  600. memcpy(dtd, standard_header, header_size);
  601. dtd_size -= header_size;
  602. dtd_size = min_t(u32, dtd_size, strlen(name));
  603. memcpy(dtd + header_size, name, dtd_size);
  604. return 0;
  605. }
  606. static void dsi_drm_update_dtd(struct edid *edid,
  607. struct dsi_display_mode *modes, u32 modes_count)
  608. {
  609. u32 i;
  610. u32 count = min_t(u32, modes_count, 3);
  611. for (i = 0; i < count; i++) {
  612. struct detailed_timing *dtd = &edid->detailed_timings[i];
  613. struct dsi_display_mode *mode = &modes[i];
  614. struct dsi_mode_info *timing = &mode->timing;
  615. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  616. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  617. timing->h_back_porch;
  618. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  619. timing->v_back_porch;
  620. u32 h_img = 0, v_img = 0;
  621. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  622. pd->hactive_lo = timing->h_active & 0xFF;
  623. pd->hblank_lo = h_blank & 0xFF;
  624. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  625. ((timing->h_active >> 8) & 0xF) << 4;
  626. pd->vactive_lo = timing->v_active & 0xFF;
  627. pd->vblank_lo = v_blank & 0xFF;
  628. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  629. ((timing->v_active >> 8) & 0xF) << 4;
  630. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  631. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  632. pd->vsync_offset_pulse_width_lo =
  633. ((timing->v_front_porch & 0xF) << 4) |
  634. (timing->v_sync_width & 0xF);
  635. pd->hsync_vsync_offset_pulse_width_hi =
  636. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  637. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  638. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  639. (((timing->v_sync_width >> 4) & 0x3) << 0);
  640. pd->width_mm_lo = h_img & 0xFF;
  641. pd->height_mm_lo = v_img & 0xFF;
  642. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  643. ((v_img >> 8) & 0xF);
  644. pd->hborder = 0;
  645. pd->vborder = 0;
  646. pd->misc = 0;
  647. }
  648. }
  649. static void dsi_drm_update_checksum(struct edid *edid)
  650. {
  651. u8 *data = (u8 *)edid;
  652. u32 i, sum = 0;
  653. for (i = 0; i < EDID_LENGTH - 1; i++)
  654. sum += data[i];
  655. edid->checksum = 0x100 - (sum & 0xFF);
  656. }
  657. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  658. const struct msm_resource_caps_info *avail_res)
  659. {
  660. int rc, i;
  661. u32 count = 0, edid_size;
  662. struct dsi_display_mode *modes = NULL;
  663. struct drm_display_mode drm_mode;
  664. struct dsi_display *display = data;
  665. struct edid edid;
  666. const u8 edid_buf[EDID_LENGTH] = {
  667. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  668. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  669. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  670. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  671. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  672. 0x01, 0x01, 0x01, 0x01,
  673. };
  674. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  675. memcpy(&edid, edid_buf, edid_size);
  676. rc = dsi_display_get_mode_count(display, &count);
  677. if (rc) {
  678. pr_err("failed to get num of modes, rc=%d\n", rc);
  679. goto end;
  680. }
  681. rc = dsi_display_get_modes(display, &modes);
  682. if (rc) {
  683. pr_err("failed to get modes, rc=%d\n", rc);
  684. count = 0;
  685. goto end;
  686. }
  687. for (i = 0; i < count; i++) {
  688. struct drm_display_mode *m;
  689. memset(&drm_mode, 0x0, sizeof(drm_mode));
  690. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  691. m = drm_mode_duplicate(connector->dev, &drm_mode);
  692. if (!m) {
  693. pr_err("failed to add mode %ux%u\n",
  694. drm_mode.hdisplay,
  695. drm_mode.vdisplay);
  696. count = -ENOMEM;
  697. goto end;
  698. }
  699. m->width_mm = connector->display_info.width_mm;
  700. m->height_mm = connector->display_info.height_mm;
  701. /* set the first mode in list as preferred */
  702. if (i == 0)
  703. m->type |= DRM_MODE_TYPE_PREFERRED;
  704. drm_mode_probed_add(connector, m);
  705. }
  706. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  707. if (rc) {
  708. count = 0;
  709. goto end;
  710. }
  711. edid.width_cm = (connector->display_info.width_mm) / 10;
  712. edid.height_cm = (connector->display_info.height_mm) / 10;
  713. dsi_drm_update_dtd(&edid, modes, count);
  714. dsi_drm_update_checksum(&edid);
  715. rc = drm_connector_update_edid_property(connector, &edid);
  716. if (rc)
  717. count = 0;
  718. end:
  719. pr_debug("MODE COUNT =%d\n\n", count);
  720. return count;
  721. }
  722. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  723. struct drm_display_mode *mode,
  724. void *display, const struct msm_resource_caps_info *avail_res)
  725. {
  726. struct dsi_display_mode dsi_mode;
  727. int rc;
  728. if (!connector || !mode) {
  729. pr_err("Invalid params\n");
  730. return MODE_ERROR;
  731. }
  732. convert_to_dsi_mode(mode, &dsi_mode);
  733. rc = dsi_display_validate_mode(display, &dsi_mode,
  734. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  735. if (rc) {
  736. pr_err("mode not supported, rc=%d\n", rc);
  737. return MODE_BAD;
  738. }
  739. return MODE_OK;
  740. }
  741. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  742. void *display,
  743. struct msm_display_kickoff_params *params)
  744. {
  745. if (!connector || !display || !params) {
  746. pr_err("Invalid params\n");
  747. return -EINVAL;
  748. }
  749. return dsi_display_pre_kickoff(connector, display, params);
  750. }
  751. void dsi_conn_enable_event(struct drm_connector *connector,
  752. uint32_t event_idx, bool enable, void *display)
  753. {
  754. struct dsi_event_cb_info event_info;
  755. memset(&event_info, 0, sizeof(event_info));
  756. event_info.event_cb = sde_connector_trigger_event;
  757. event_info.event_usr_ptr = connector;
  758. dsi_display_enable_event(connector, display,
  759. event_idx, &event_info, enable);
  760. }
  761. int dsi_conn_post_kickoff(struct drm_connector *connector)
  762. {
  763. struct drm_encoder *encoder;
  764. struct dsi_bridge *c_bridge;
  765. struct dsi_display_mode adj_mode;
  766. struct dsi_display *display;
  767. struct dsi_display_ctrl *m_ctrl, *ctrl;
  768. int i, rc = 0;
  769. if (!connector || !connector->state) {
  770. pr_err("invalid connector or connector state\n");
  771. return -EINVAL;
  772. }
  773. encoder = connector->state->best_encoder;
  774. if (!encoder) {
  775. pr_debug("best encoder is not available\n");
  776. return 0;
  777. }
  778. c_bridge = to_dsi_bridge(encoder->bridge);
  779. adj_mode = c_bridge->dsi_mode;
  780. display = c_bridge->display;
  781. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  782. m_ctrl = &display->ctrl[display->clk_master_idx];
  783. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  784. if (rc) {
  785. pr_err("[%s] failed to dfps update rc=%d\n",
  786. display->name, rc);
  787. return -EINVAL;
  788. }
  789. /* Update the rest of the controllers */
  790. display_for_each_ctrl(i, display) {
  791. ctrl = &display->ctrl[i];
  792. if (!ctrl->ctrl || (ctrl == m_ctrl))
  793. continue;
  794. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  795. if (rc) {
  796. pr_err("[%s] failed to dfps update rc=%d\n",
  797. display->name, rc);
  798. return -EINVAL;
  799. }
  800. }
  801. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  802. }
  803. /* ensure dynamic clk switch flag is reset */
  804. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  805. return 0;
  806. }
  807. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  808. struct drm_device *dev,
  809. struct drm_encoder *encoder)
  810. {
  811. int rc = 0;
  812. struct dsi_bridge *bridge;
  813. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  814. if (!bridge) {
  815. rc = -ENOMEM;
  816. goto error;
  817. }
  818. bridge->display = display;
  819. bridge->base.funcs = &dsi_bridge_ops;
  820. bridge->base.encoder = encoder;
  821. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  822. if (rc) {
  823. pr_err("failed to attach bridge, rc=%d\n", rc);
  824. goto error_free_bridge;
  825. }
  826. encoder->bridge = &bridge->base;
  827. return bridge;
  828. error_free_bridge:
  829. kfree(bridge);
  830. error:
  831. return ERR_PTR(rc);
  832. }
  833. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  834. {
  835. if (bridge && bridge->base.encoder)
  836. bridge->base.encoder->bridge = NULL;
  837. kfree(bridge);
  838. }