dp_rx_mon_dest.c 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662
  1. /*
  2. * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "dp_types.h"
  20. #include "dp_rx.h"
  21. #include "dp_peer.h"
  22. #include "hal_rx.h"
  23. #include "hal_api.h"
  24. #include "qdf_trace.h"
  25. #include "qdf_nbuf.h"
  26. #include "hal_api_mon.h"
  27. #include "dp_rx_mon.h"
  28. #include "wlan_cfg.h"
  29. #include "dp_internal.h"
  30. /* The maxinum buffer length allocated for radio tap */
  31. #define MAX_MONITOR_HEADER (512)
  32. /*
  33. * PPDU id is from 0 to 64k-1. PPDU id read from status ring and PPDU id
  34. * read from destination ring shall track each other. If the distance of
  35. * two ppdu id is less than 20000. It is assume no wrap around. Otherwise,
  36. * It is assume wrap around.
  37. */
  38. #define NOT_PPDU_ID_WRAP_AROUND 20000
  39. /**
  40. * dp_rx_mon_link_desc_return() - Return a MPDU link descriptor to HW
  41. * (WBM), following error handling
  42. *
  43. * @dp_pdev: core txrx pdev context
  44. * @buf_addr_info: void pointer to monitor link descriptor buf addr info
  45. * Return: QDF_STATUS
  46. */
  47. static QDF_STATUS
  48. dp_rx_mon_link_desc_return(struct dp_pdev *dp_pdev,
  49. void *buf_addr_info, int mac_id)
  50. {
  51. struct dp_srng *dp_srng;
  52. void *hal_srng;
  53. void *hal_soc;
  54. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  55. void *src_srng_desc;
  56. int mac_for_pdev = dp_get_mac_id_for_mac(dp_pdev->soc, mac_id);
  57. hal_soc = dp_pdev->soc->hal_soc;
  58. dp_srng = &dp_pdev->rxdma_mon_desc_ring[mac_for_pdev];
  59. hal_srng = dp_srng->hal_srng;
  60. qdf_assert(hal_srng);
  61. if (qdf_unlikely(hal_srng_access_start(hal_soc, hal_srng))) {
  62. /* TODO */
  63. /*
  64. * Need API to convert from hal_ring pointer to
  65. * Ring Type / Ring Id combo
  66. */
  67. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  68. "%s %d : \
  69. HAL RING Access For WBM Release SRNG Failed -- %pK",
  70. __func__, __LINE__, hal_srng);
  71. goto done;
  72. }
  73. src_srng_desc = hal_srng_src_get_next(hal_soc, hal_srng);
  74. if (qdf_likely(src_srng_desc)) {
  75. /* Return link descriptor through WBM ring (SW2WBM)*/
  76. hal_rx_mon_msdu_link_desc_set(hal_soc,
  77. src_srng_desc, buf_addr_info);
  78. status = QDF_STATUS_SUCCESS;
  79. } else {
  80. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  81. "%s %d -- Monitor Link Desc WBM Release Ring Full",
  82. __func__, __LINE__);
  83. }
  84. done:
  85. hal_srng_access_end(hal_soc, hal_srng);
  86. return status;
  87. }
  88. /**
  89. * dp_mon_adjust_frag_len() - MPDU and MSDU may spread across
  90. * multiple nbufs. This function
  91. * is to return data length in
  92. * fragmented buffer
  93. *
  94. * @total_len: pointer to remaining data length.
  95. * @frag_len: pointer to data length in this fragment.
  96. */
  97. static inline void dp_mon_adjust_frag_len(uint32_t *total_len,
  98. uint32_t *frag_len)
  99. {
  100. if (*total_len >= (RX_BUFFER_SIZE - RX_PKT_TLVS_LEN)) {
  101. *frag_len = RX_BUFFER_SIZE - RX_PKT_TLVS_LEN;
  102. *total_len -= *frag_len;
  103. } else {
  104. *frag_len = *total_len;
  105. *total_len = 0;
  106. }
  107. }
  108. /**
  109. * dp_rx_cookie_2_mon_link_desc() - Retrieve Link descriptor based on target
  110. * @pdev: core physical device context
  111. * @hal_buf_info: structure holding the buffer info
  112. * mac_id: mac number
  113. *
  114. * Return: link descriptor address
  115. */
  116. static inline
  117. void *dp_rx_cookie_2_mon_link_desc(struct dp_pdev *pdev,
  118. struct hal_buf_info buf_info,
  119. uint8_t mac_id)
  120. {
  121. if (pdev->soc->wlan_cfg_ctx->rxdma1_enable)
  122. return dp_rx_cookie_2_mon_link_desc_va(pdev, &buf_info,
  123. mac_id);
  124. return dp_rx_cookie_2_link_desc_va(pdev->soc, &buf_info);
  125. }
  126. /**
  127. * dp_rx_monitor_link_desc_return() - Return Link descriptor based on target
  128. * @pdev: core physical device context
  129. * @p_last_buf_addr_info: MPDU Link descriptor
  130. * mac_id: mac number
  131. *
  132. * Return: QDF_STATUS
  133. */
  134. static inline
  135. QDF_STATUS dp_rx_monitor_link_desc_return(struct dp_pdev *pdev,
  136. void *p_last_buf_addr_info,
  137. uint8_t mac_id, uint8_t bm_action)
  138. {
  139. if (pdev->soc->wlan_cfg_ctx->rxdma1_enable)
  140. return dp_rx_mon_link_desc_return(pdev, p_last_buf_addr_info,
  141. mac_id);
  142. return dp_rx_link_desc_return(pdev->soc, p_last_buf_addr_info,
  143. bm_action);
  144. }
  145. /**
  146. * dp_rxdma_get_mon_dst_ring() - Return the pointer to rxdma_err_dst_ring
  147. * or mon_dst_ring based on the target
  148. * @pdev: core physical device context
  149. * @mac_for_pdev: mac_id number
  150. *
  151. * Return: ring address
  152. */
  153. static inline
  154. void *dp_rxdma_get_mon_dst_ring(struct dp_pdev *pdev,
  155. uint8_t mac_for_pdev)
  156. {
  157. if (pdev->soc->wlan_cfg_ctx->rxdma1_enable)
  158. return pdev->rxdma_mon_dst_ring[mac_for_pdev].hal_srng;
  159. return pdev->rxdma_err_dst_ring[mac_for_pdev].hal_srng;
  160. }
  161. /**
  162. * dp_rxdma_get_mon_buf_ring() - Return monitor buf ring address
  163. * based on target
  164. * @pdev: core physical device context
  165. * @mac_for_pdev: mac id number
  166. *
  167. * Return: ring address
  168. */
  169. static inline
  170. struct dp_srng *dp_rxdma_get_mon_buf_ring(struct dp_pdev *pdev,
  171. uint8_t mac_for_pdev)
  172. {
  173. if (pdev->soc->wlan_cfg_ctx->rxdma1_enable)
  174. return &pdev->rxdma_mon_buf_ring[mac_for_pdev];
  175. return &pdev->rx_refill_buf_ring;
  176. }
  177. /**
  178. * dp_rx_get_mon_desc_pool() - Return monitor descriptor pool
  179. * based on target
  180. * @soc: soc handle
  181. * @mac_id: mac id number
  182. * @pdev_id: pdev id number
  183. *
  184. * Return: descriptor pool address
  185. */
  186. static inline
  187. struct rx_desc_pool *dp_rx_get_mon_desc_pool(struct dp_soc *soc,
  188. uint8_t mac_id,
  189. uint8_t pdev_id)
  190. {
  191. if (soc->wlan_cfg_ctx->rxdma1_enable)
  192. return &soc->rx_desc_mon[mac_id];
  193. return &soc->rx_desc_buf[pdev_id];
  194. }
  195. /**
  196. * dp_rx_get_mon_desc() - Return Rx descriptor based on target
  197. * @soc: soc handle
  198. * @cookie: cookie value
  199. *
  200. * Return: Rx descriptor
  201. */
  202. static inline
  203. struct dp_rx_desc *dp_rx_get_mon_desc(struct dp_soc *soc,
  204. uint32_t cookie)
  205. {
  206. if (soc->wlan_cfg_ctx->rxdma1_enable)
  207. return dp_rx_cookie_2_va_mon_buf(soc, cookie);
  208. return dp_rx_cookie_2_va_rxdma_buf(soc, cookie);
  209. }
  210. /**
  211. * dp_rx_mon_mpdu_pop() - Return a MPDU link descriptor to HW
  212. * (WBM), following error handling
  213. *
  214. * @soc: core DP main context
  215. * @mac_id: mac id which is one of 3 mac_ids
  216. * @rxdma_dst_ring_desc: void pointer to monitor link descriptor buf addr info
  217. * @head_msdu: head of msdu to be popped
  218. * @tail_msdu: tail of msdu to be popped
  219. * @npackets: number of packet to be popped
  220. * @ppdu_id: ppdu id of processing ppdu
  221. * @head: head of descs list to be freed
  222. * @tail: tail of decs list to be freed
  223. *
  224. * Return: number of msdu in MPDU to be popped
  225. */
  226. static inline uint32_t
  227. dp_rx_mon_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
  228. void *rxdma_dst_ring_desc, qdf_nbuf_t *head_msdu,
  229. qdf_nbuf_t *tail_msdu, uint32_t *npackets, uint32_t *ppdu_id,
  230. union dp_rx_desc_list_elem_t **head,
  231. union dp_rx_desc_list_elem_t **tail)
  232. {
  233. struct dp_pdev *dp_pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  234. void *rx_desc_tlv;
  235. void *rx_msdu_link_desc;
  236. qdf_nbuf_t msdu;
  237. qdf_nbuf_t last;
  238. struct hal_rx_msdu_list msdu_list;
  239. uint16_t num_msdus;
  240. uint32_t rx_buf_size, rx_pkt_offset;
  241. struct hal_buf_info buf_info;
  242. void *p_buf_addr_info;
  243. void *p_last_buf_addr_info;
  244. uint32_t rx_bufs_used = 0;
  245. uint32_t msdu_ppdu_id, msdu_cnt;
  246. uint8_t *data;
  247. uint32_t i;
  248. uint32_t total_frag_len = 0, frag_len = 0;
  249. bool is_frag, is_first_msdu;
  250. bool drop_mpdu = false;
  251. uint8_t bm_action = HAL_BM_ACTION_PUT_IN_IDLE_LIST;
  252. uint64_t nbuf_paddr = 0;
  253. msdu = 0;
  254. last = NULL;
  255. hal_rx_reo_ent_buf_paddr_get(rxdma_dst_ring_desc, &buf_info,
  256. &p_last_buf_addr_info, &msdu_cnt);
  257. if ((hal_rx_reo_ent_rxdma_push_reason_get(rxdma_dst_ring_desc) ==
  258. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR)) {
  259. uint8_t rxdma_err =
  260. hal_rx_reo_ent_rxdma_error_code_get(
  261. rxdma_dst_ring_desc);
  262. if (qdf_unlikely((rxdma_err == HAL_RXDMA_ERR_FLUSH_REQUEST) ||
  263. (rxdma_err == HAL_RXDMA_ERR_MPDU_LENGTH) ||
  264. (rxdma_err == HAL_RXDMA_ERR_OVERFLOW))) {
  265. drop_mpdu = true;
  266. dp_pdev->rx_mon_stats.dest_mpdu_drop++;
  267. }
  268. }
  269. is_frag = false;
  270. is_first_msdu = true;
  271. do {
  272. /* WAR for duplicate link descriptors received from HW */
  273. if (qdf_unlikely(dp_pdev->mon_last_linkdesc_paddr ==
  274. buf_info.paddr)) {
  275. dp_pdev->rx_mon_stats.dup_mon_linkdesc_cnt++;
  276. return rx_bufs_used;
  277. }
  278. rx_msdu_link_desc =
  279. dp_rx_cookie_2_mon_link_desc(dp_pdev,
  280. buf_info, mac_id);
  281. qdf_assert(rx_msdu_link_desc);
  282. hal_rx_msdu_list_get(soc->hal_soc, rx_msdu_link_desc,
  283. &msdu_list, &num_msdus);
  284. for (i = 0; i < num_msdus; i++) {
  285. uint32_t l2_hdr_offset;
  286. struct dp_rx_desc *rx_desc = NULL;
  287. rx_desc = dp_rx_get_mon_desc(soc,
  288. msdu_list.sw_cookie[i]);
  289. qdf_assert_always(rx_desc);
  290. msdu = rx_desc->nbuf;
  291. if (msdu)
  292. nbuf_paddr = qdf_nbuf_get_frag_paddr(msdu, 0);
  293. /* WAR for duplicate buffers received from HW */
  294. if (qdf_unlikely(dp_pdev->mon_last_buf_cookie ==
  295. msdu_list.sw_cookie[i] ||
  296. !msdu ||
  297. msdu_list.paddr[i] != nbuf_paddr ||
  298. !rx_desc->in_use)) {
  299. /* Skip duplicate buffer and drop subsequent
  300. * buffers in this MPDU
  301. */
  302. drop_mpdu = true;
  303. dp_pdev->rx_mon_stats.dup_mon_buf_cnt++;
  304. dp_pdev->mon_last_linkdesc_paddr =
  305. buf_info.paddr;
  306. continue;
  307. }
  308. if (rx_desc->unmapped == 0) {
  309. qdf_nbuf_unmap_single(soc->osdev, msdu,
  310. QDF_DMA_FROM_DEVICE);
  311. rx_desc->unmapped = 1;
  312. }
  313. if (drop_mpdu) {
  314. dp_pdev->mon_last_linkdesc_paddr =
  315. buf_info.paddr;
  316. qdf_nbuf_free(msdu);
  317. msdu = NULL;
  318. goto next_msdu;
  319. }
  320. data = qdf_nbuf_data(msdu);
  321. rx_desc_tlv = HAL_RX_MON_DEST_GET_DESC(data);
  322. QDF_TRACE(QDF_MODULE_ID_DP,
  323. QDF_TRACE_LEVEL_DEBUG,
  324. "[%s] i=%d, ppdu_id=%x, num_msdus = %u",
  325. __func__, i, *ppdu_id, num_msdus);
  326. if (is_first_msdu) {
  327. if (!HAL_RX_HW_DESC_MPDU_VALID(
  328. rx_desc_tlv)) {
  329. drop_mpdu = true;
  330. qdf_nbuf_free(msdu);
  331. msdu = NULL;
  332. dp_pdev->mon_last_linkdesc_paddr =
  333. buf_info.paddr;
  334. goto next_msdu;
  335. }
  336. msdu_ppdu_id = HAL_RX_HW_DESC_GET_PPDUID_GET(
  337. rx_desc_tlv);
  338. is_first_msdu = false;
  339. QDF_TRACE(QDF_MODULE_ID_DP,
  340. QDF_TRACE_LEVEL_DEBUG,
  341. "[%s] msdu_ppdu_id=%x",
  342. __func__, msdu_ppdu_id);
  343. if (*ppdu_id > msdu_ppdu_id)
  344. QDF_TRACE(QDF_MODULE_ID_DP,
  345. QDF_TRACE_LEVEL_DEBUG,
  346. "[%s][%d] ppdu_id=%d "
  347. "msdu_ppdu_id=%d",
  348. __func__, __LINE__, *ppdu_id,
  349. msdu_ppdu_id);
  350. if ((*ppdu_id < msdu_ppdu_id) && (
  351. (msdu_ppdu_id - *ppdu_id) <
  352. NOT_PPDU_ID_WRAP_AROUND)) {
  353. *ppdu_id = msdu_ppdu_id;
  354. return rx_bufs_used;
  355. } else if ((*ppdu_id > msdu_ppdu_id) && (
  356. (*ppdu_id - msdu_ppdu_id) >
  357. NOT_PPDU_ID_WRAP_AROUND)) {
  358. *ppdu_id = msdu_ppdu_id;
  359. return rx_bufs_used;
  360. }
  361. dp_pdev->mon_last_linkdesc_paddr =
  362. buf_info.paddr;
  363. }
  364. if (hal_rx_desc_is_first_msdu(rx_desc_tlv))
  365. hal_rx_mon_hw_desc_get_mpdu_status(soc->hal_soc,
  366. rx_desc_tlv,
  367. &(dp_pdev->ppdu_info.rx_status));
  368. if (msdu_list.msdu_info[i].msdu_flags &
  369. HAL_MSDU_F_MSDU_CONTINUATION) {
  370. if (!is_frag) {
  371. total_frag_len =
  372. msdu_list.msdu_info[i].msdu_len;
  373. is_frag = true;
  374. }
  375. dp_mon_adjust_frag_len(
  376. &total_frag_len, &frag_len);
  377. } else {
  378. if (is_frag) {
  379. dp_mon_adjust_frag_len(
  380. &total_frag_len, &frag_len);
  381. } else {
  382. frag_len =
  383. msdu_list.msdu_info[i].msdu_len;
  384. }
  385. is_frag = false;
  386. msdu_cnt--;
  387. }
  388. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  389. "%s total_len %u frag_len %u flags %u",
  390. __func__, total_frag_len, frag_len,
  391. msdu_list.msdu_info[i].msdu_flags);
  392. rx_pkt_offset = HAL_RX_MON_HW_RX_DESC_SIZE();
  393. /*
  394. * HW structures call this L3 header padding
  395. * -- even though this is actually the offset
  396. * from the buffer beginning where the L2
  397. * header begins.
  398. */
  399. l2_hdr_offset =
  400. hal_rx_msdu_end_l3_hdr_padding_get(data);
  401. rx_buf_size = rx_pkt_offset + l2_hdr_offset
  402. + frag_len;
  403. qdf_nbuf_set_pktlen(msdu, rx_buf_size);
  404. #if 0
  405. /* Disble it.see packet on msdu done set to 0 */
  406. /*
  407. * Check if DMA completed -- msdu_done is the
  408. * last bit to be written
  409. */
  410. if (!hal_rx_attn_msdu_done_get(rx_desc_tlv)) {
  411. QDF_TRACE(QDF_MODULE_ID_DP,
  412. QDF_TRACE_LEVEL_ERROR,
  413. "%s:%d: Pkt Desc",
  414. __func__, __LINE__);
  415. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  416. QDF_TRACE_LEVEL_ERROR,
  417. rx_desc_tlv, 128);
  418. qdf_assert_always(0);
  419. }
  420. #endif
  421. QDF_TRACE(QDF_MODULE_ID_DP,
  422. QDF_TRACE_LEVEL_DEBUG,
  423. "%s: rx_pkt_offset=%d, l2_hdr_offset=%d, msdu_len=%d, addr=%pK skb->len %u",
  424. __func__, rx_pkt_offset, l2_hdr_offset,
  425. msdu_list.msdu_info[i].msdu_len,
  426. qdf_nbuf_data(msdu),
  427. (uint32_t)qdf_nbuf_len(msdu));
  428. if (head_msdu && !*head_msdu) {
  429. *head_msdu = msdu;
  430. } else {
  431. if (last)
  432. qdf_nbuf_set_next(last, msdu);
  433. }
  434. last = msdu;
  435. next_msdu:
  436. dp_pdev->mon_last_buf_cookie = msdu_list.sw_cookie[i];
  437. rx_bufs_used++;
  438. dp_rx_add_to_free_desc_list(head,
  439. tail, rx_desc);
  440. }
  441. hal_rx_mon_next_link_desc_get(rx_msdu_link_desc, &buf_info,
  442. &p_buf_addr_info);
  443. if (dp_rx_monitor_link_desc_return(dp_pdev,
  444. p_last_buf_addr_info,
  445. mac_id,
  446. bm_action)
  447. != QDF_STATUS_SUCCESS)
  448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  449. "dp_rx_monitor_link_desc_return failed");
  450. p_last_buf_addr_info = p_buf_addr_info;
  451. } while (buf_info.paddr && msdu_cnt);
  452. if (last)
  453. qdf_nbuf_set_next(last, NULL);
  454. *tail_msdu = msdu;
  455. return rx_bufs_used;
  456. }
  457. static inline
  458. void dp_rx_msdus_set_payload(qdf_nbuf_t msdu)
  459. {
  460. uint8_t *data;
  461. uint32_t rx_pkt_offset, l2_hdr_offset;
  462. data = qdf_nbuf_data(msdu);
  463. rx_pkt_offset = HAL_RX_MON_HW_RX_DESC_SIZE();
  464. l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(data);
  465. qdf_nbuf_pull_head(msdu, rx_pkt_offset + l2_hdr_offset);
  466. }
  467. static inline
  468. qdf_nbuf_t dp_rx_mon_restitch_mpdu_from_msdus(struct dp_soc *soc,
  469. uint32_t mac_id, qdf_nbuf_t head_msdu, qdf_nbuf_t last_msdu,
  470. struct cdp_mon_status *rx_status)
  471. {
  472. qdf_nbuf_t msdu, mpdu_buf, prev_buf, msdu_orig, head_frag_list;
  473. uint32_t decap_format, wifi_hdr_len, sec_hdr_len, msdu_llc_len,
  474. mpdu_buf_len, decap_hdr_pull_bytes, frag_list_sum_len, dir,
  475. is_amsdu, is_first_frag, amsdu_pad;
  476. void *rx_desc;
  477. char *hdr_desc;
  478. unsigned char *dest;
  479. struct ieee80211_frame *wh;
  480. struct ieee80211_qoscntl *qos;
  481. struct dp_pdev *dp_pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  482. head_frag_list = NULL;
  483. mpdu_buf = NULL;
  484. /* The nbuf has been pulled just beyond the status and points to the
  485. * payload
  486. */
  487. if (!head_msdu)
  488. goto mpdu_stitch_fail;
  489. msdu_orig = head_msdu;
  490. rx_desc = qdf_nbuf_data(msdu_orig);
  491. if (HAL_RX_DESC_GET_MPDU_LENGTH_ERR(rx_desc)) {
  492. /* It looks like there is some issue on MPDU len err */
  493. /* Need further investigate if drop the packet */
  494. DP_STATS_INC(dp_pdev, dropped.mon_rx_drop, 1);
  495. return NULL;
  496. }
  497. rx_desc = qdf_nbuf_data(last_msdu);
  498. rx_status->cdp_rs_fcs_err = HAL_RX_DESC_GET_MPDU_FCS_ERR(rx_desc);
  499. dp_pdev->ppdu_info.rx_status.rs_fcs_err =
  500. HAL_RX_DESC_GET_MPDU_FCS_ERR(rx_desc);
  501. /* Fill out the rx_status from the PPDU start and end fields */
  502. /* HAL_RX_GET_PPDU_STATUS(soc, mac_id, rx_status); */
  503. rx_desc = qdf_nbuf_data(head_msdu);
  504. decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_desc);
  505. /* Easy case - The MSDU status indicates that this is a non-decapped
  506. * packet in RAW mode.
  507. */
  508. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) {
  509. /* Note that this path might suffer from headroom unavailabilty
  510. * - but the RX status is usually enough
  511. */
  512. dp_rx_msdus_set_payload(head_msdu);
  513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  514. "[%s][%d] decap format raw head %pK head->next %pK last_msdu %pK last_msdu->next %pK",
  515. __func__, __LINE__, head_msdu, head_msdu->next,
  516. last_msdu, last_msdu->next);
  517. mpdu_buf = head_msdu;
  518. prev_buf = mpdu_buf;
  519. frag_list_sum_len = 0;
  520. msdu = qdf_nbuf_next(head_msdu);
  521. is_first_frag = 1;
  522. while (msdu) {
  523. dp_rx_msdus_set_payload(msdu);
  524. if (is_first_frag) {
  525. is_first_frag = 0;
  526. head_frag_list = msdu;
  527. }
  528. frag_list_sum_len += qdf_nbuf_len(msdu);
  529. /* Maintain the linking of the cloned MSDUS */
  530. qdf_nbuf_set_next_ext(prev_buf, msdu);
  531. /* Move to the next */
  532. prev_buf = msdu;
  533. msdu = qdf_nbuf_next(msdu);
  534. }
  535. qdf_nbuf_trim_tail(prev_buf, HAL_RX_FCS_LEN);
  536. /* If there were more fragments to this RAW frame */
  537. if (head_frag_list) {
  538. if (frag_list_sum_len <
  539. sizeof(struct ieee80211_frame_min_one)) {
  540. DP_STATS_INC(dp_pdev, dropped.mon_rx_drop, 1);
  541. return NULL;
  542. }
  543. frag_list_sum_len -= HAL_RX_FCS_LEN;
  544. qdf_nbuf_append_ext_list(mpdu_buf, head_frag_list,
  545. frag_list_sum_len);
  546. qdf_nbuf_set_next(mpdu_buf, NULL);
  547. }
  548. goto mpdu_stitch_done;
  549. }
  550. /* Decap mode:
  551. * Calculate the amount of header in decapped packet to knock off based
  552. * on the decap type and the corresponding number of raw bytes to copy
  553. * status header
  554. */
  555. rx_desc = qdf_nbuf_data(head_msdu);
  556. hdr_desc = HAL_RX_DESC_GET_80211_HDR(rx_desc);
  557. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  558. "[%s][%d] decap format not raw",
  559. __func__, __LINE__);
  560. /* Base size */
  561. wifi_hdr_len = sizeof(struct ieee80211_frame);
  562. wh = (struct ieee80211_frame *)hdr_desc;
  563. dir = wh->i_fc[1] & IEEE80211_FC1_DIR_MASK;
  564. if (dir == IEEE80211_FC1_DIR_DSTODS)
  565. wifi_hdr_len += 6;
  566. is_amsdu = 0;
  567. if (wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) {
  568. qos = (struct ieee80211_qoscntl *)
  569. (hdr_desc + wifi_hdr_len);
  570. wifi_hdr_len += 2;
  571. is_amsdu = (qos->i_qos[0] & IEEE80211_QOS_AMSDU);
  572. }
  573. /*Calculate security header length based on 'Protected'
  574. * and 'EXT_IV' flag
  575. * */
  576. if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
  577. char *iv = (char *)wh + wifi_hdr_len;
  578. if (iv[3] & KEY_EXTIV)
  579. sec_hdr_len = 8;
  580. else
  581. sec_hdr_len = 4;
  582. } else {
  583. sec_hdr_len = 0;
  584. }
  585. wifi_hdr_len += sec_hdr_len;
  586. /* MSDU related stuff LLC - AMSDU subframe header etc */
  587. msdu_llc_len = is_amsdu ? (14 + 8) : 8;
  588. mpdu_buf_len = wifi_hdr_len + msdu_llc_len;
  589. /* "Decap" header to remove from MSDU buffer */
  590. decap_hdr_pull_bytes = 14;
  591. /* Allocate a new nbuf for holding the 802.11 header retrieved from the
  592. * status of the now decapped first msdu. Leave enough headroom for
  593. * accomodating any radio-tap /prism like PHY header
  594. */
  595. mpdu_buf = qdf_nbuf_alloc(soc->osdev,
  596. MAX_MONITOR_HEADER + mpdu_buf_len,
  597. MAX_MONITOR_HEADER, 4, FALSE);
  598. if (!mpdu_buf)
  599. goto mpdu_stitch_done;
  600. /* Copy the MPDU related header and enc headers into the first buffer
  601. * - Note that there can be a 2 byte pad between heaader and enc header
  602. */
  603. prev_buf = mpdu_buf;
  604. dest = qdf_nbuf_put_tail(prev_buf, wifi_hdr_len);
  605. if (!dest)
  606. goto mpdu_stitch_fail;
  607. qdf_mem_copy(dest, hdr_desc, wifi_hdr_len);
  608. hdr_desc += wifi_hdr_len;
  609. #if 0
  610. dest = qdf_nbuf_put_tail(prev_buf, sec_hdr_len);
  611. adf_os_mem_copy(dest, hdr_desc, sec_hdr_len);
  612. hdr_desc += sec_hdr_len;
  613. #endif
  614. /* The first LLC len is copied into the MPDU buffer */
  615. frag_list_sum_len = 0;
  616. msdu_orig = head_msdu;
  617. is_first_frag = 1;
  618. amsdu_pad = 0;
  619. while (msdu_orig) {
  620. /* TODO: intra AMSDU padding - do we need it ??? */
  621. msdu = msdu_orig;
  622. if (is_first_frag) {
  623. head_frag_list = msdu;
  624. } else {
  625. /* Reload the hdr ptr only on non-first MSDUs */
  626. rx_desc = qdf_nbuf_data(msdu_orig);
  627. hdr_desc = HAL_RX_DESC_GET_80211_HDR(rx_desc);
  628. }
  629. /* Copy this buffers MSDU related status into the prev buffer */
  630. if (is_first_frag) {
  631. is_first_frag = 0;
  632. }
  633. /* Update protocol tag for MSDU */
  634. dp_rx_mon_update_protocol_tag(soc, dp_pdev, msdu_orig, rx_desc);
  635. dest = qdf_nbuf_put_tail(prev_buf,
  636. msdu_llc_len + amsdu_pad);
  637. if (!dest)
  638. goto mpdu_stitch_fail;
  639. dest += amsdu_pad;
  640. qdf_mem_copy(dest, hdr_desc, msdu_llc_len);
  641. dp_rx_msdus_set_payload(msdu);
  642. /* Push the MSDU buffer beyond the decap header */
  643. qdf_nbuf_pull_head(msdu, decap_hdr_pull_bytes);
  644. frag_list_sum_len += msdu_llc_len + qdf_nbuf_len(msdu)
  645. + amsdu_pad;
  646. /* Set up intra-AMSDU pad to be added to start of next buffer -
  647. * AMSDU pad is 4 byte pad on AMSDU subframe */
  648. amsdu_pad = (msdu_llc_len + qdf_nbuf_len(msdu)) & 0x3;
  649. amsdu_pad = amsdu_pad ? (4 - amsdu_pad) : 0;
  650. /* TODO FIXME How do we handle MSDUs that have fraglist - Should
  651. * probably iterate all the frags cloning them along the way and
  652. * and also updating the prev_buf pointer
  653. */
  654. /* Move to the next */
  655. prev_buf = msdu;
  656. msdu_orig = qdf_nbuf_next(msdu_orig);
  657. }
  658. #if 0
  659. /* Add in the trailer section - encryption trailer + FCS */
  660. qdf_nbuf_put_tail(prev_buf, HAL_RX_FCS_LEN);
  661. frag_list_sum_len += HAL_RX_FCS_LEN;
  662. #endif
  663. frag_list_sum_len -= msdu_llc_len;
  664. /* TODO: Convert this to suitable adf routines */
  665. qdf_nbuf_append_ext_list(mpdu_buf, head_frag_list,
  666. frag_list_sum_len);
  667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  668. "%s %d mpdu_buf %pK mpdu_buf->len %u",
  669. __func__, __LINE__,
  670. mpdu_buf, mpdu_buf->len);
  671. mpdu_stitch_done:
  672. /* Check if this buffer contains the PPDU end status for TSF */
  673. /* Need revist this code to see where we can get tsf timestamp */
  674. #if 0
  675. /* PPDU end TLV will be retrieved from monitor status ring */
  676. last_mpdu =
  677. (*(((u_int32_t *)&rx_desc->attention)) &
  678. RX_ATTENTION_0_LAST_MPDU_MASK) >>
  679. RX_ATTENTION_0_LAST_MPDU_LSB;
  680. if (last_mpdu)
  681. rx_status->rs_tstamp.tsf = rx_desc->ppdu_end.tsf_timestamp;
  682. #endif
  683. return mpdu_buf;
  684. mpdu_stitch_fail:
  685. if ((mpdu_buf) && (decap_format != HAL_HW_RX_DECAP_FORMAT_RAW)) {
  686. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  687. "%s mpdu_stitch_fail mpdu_buf %pK",
  688. __func__, mpdu_buf);
  689. /* Free the head buffer */
  690. qdf_nbuf_free(mpdu_buf);
  691. }
  692. return NULL;
  693. }
  694. /**
  695. * dp_send_mgmt_packet_to_stack(): send indicataion to upper layers
  696. *
  697. * @soc: soc handle
  698. * @nbuf: Mgmt packet
  699. * @pdev: pdev handle
  700. *
  701. * Return: QDF_STATUS_SUCCESS on success
  702. * QDF_STATUS_E_INVAL in error
  703. */
  704. #ifdef FEATURE_PERPKT_INFO
  705. static inline QDF_STATUS dp_send_mgmt_packet_to_stack(struct dp_soc *soc,
  706. qdf_nbuf_t nbuf,
  707. struct dp_pdev *pdev)
  708. {
  709. uint32_t *nbuf_data;
  710. struct ieee80211_frame *wh;
  711. if (!nbuf)
  712. return QDF_STATUS_E_INVAL;
  713. /*check if this is not a mgmt packet*/
  714. wh = (struct ieee80211_frame *)qdf_nbuf_data(nbuf);
  715. if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
  716. IEEE80211_FC0_TYPE_MGT) &&
  717. ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
  718. IEEE80211_FC0_TYPE_CTL)) {
  719. qdf_nbuf_free(nbuf);
  720. return QDF_STATUS_E_INVAL;
  721. }
  722. nbuf_data = (uint32_t *)qdf_nbuf_push_head(nbuf, 4);
  723. if (!nbuf_data) {
  724. QDF_TRACE(QDF_MODULE_ID_DP,
  725. QDF_TRACE_LEVEL_ERROR,
  726. FL("No headroom"));
  727. qdf_nbuf_free(nbuf);
  728. return QDF_STATUS_E_INVAL;
  729. }
  730. *nbuf_data = pdev->ppdu_info.com_info.ppdu_id;
  731. dp_wdi_event_handler(WDI_EVENT_RX_MGMT_CTRL, soc, nbuf,
  732. HTT_INVALID_PEER,
  733. WDI_NO_VAL, pdev->pdev_id);
  734. return QDF_STATUS_SUCCESS;
  735. }
  736. #else
  737. static inline QDF_STATUS dp_send_mgmt_packet_to_stack(struct dp_soc *soc,
  738. qdf_nbuf_t nbuf,
  739. struct dp_pdev *pdev)
  740. {
  741. return QDF_STATUS_SUCCESS;
  742. }
  743. #endif
  744. /**
  745. * dp_rx_extract_radiotap_info(): Extract and populate information in
  746. * struct mon_rx_status type
  747. * @rx_status: Receive status
  748. * @mon_rx_status: Monitor mode status
  749. *
  750. * Returns: None
  751. */
  752. static inline
  753. void dp_rx_extract_radiotap_info(struct cdp_mon_status *rx_status,
  754. struct mon_rx_status *rx_mon_status)
  755. {
  756. rx_mon_status->tsft = rx_status->cdp_rs_tstamp.cdp_tsf;
  757. rx_mon_status->chan_freq = rx_status->rs_freq;
  758. rx_mon_status->chan_num = rx_status->rs_channel;
  759. rx_mon_status->chan_flags = rx_status->rs_flags;
  760. rx_mon_status->rate = rx_status->rs_datarate;
  761. /* TODO: rx_mon_status->ant_signal_db */
  762. /* TODO: rx_mon_status->nr_ant */
  763. rx_mon_status->mcs = rx_status->cdf_rs_rate_mcs;
  764. rx_mon_status->is_stbc = rx_status->cdp_rs_stbc;
  765. rx_mon_status->sgi = rx_status->cdp_rs_sgi;
  766. /* TODO: rx_mon_status->ldpc */
  767. /* TODO: rx_mon_status->beamformed */
  768. /* TODO: rx_mon_status->vht_flags */
  769. /* TODO: rx_mon_status->vht_flag_values1 */
  770. }
  771. /*
  772. * dp_rx_mon_deliver(): function to deliver packets to stack
  773. * @soc: DP soc
  774. * @mac_id: MAC ID
  775. * @head_msdu: head of msdu list
  776. * @tail_msdu: tail of msdu list
  777. *
  778. * Return: status: 0 - Success, non-zero: Failure
  779. */
  780. QDF_STATUS dp_rx_mon_deliver(struct dp_soc *soc, uint32_t mac_id,
  781. qdf_nbuf_t head_msdu, qdf_nbuf_t tail_msdu)
  782. {
  783. struct dp_pdev *pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  784. struct cdp_mon_status *rs = &pdev->rx_mon_recv_status;
  785. qdf_nbuf_t mon_skb, skb_next;
  786. qdf_nbuf_t mon_mpdu = NULL;
  787. if (!pdev->monitor_vdev && !pdev->mcopy_mode)
  788. goto mon_deliver_fail;
  789. /* restitch mon MPDU for delivery via monitor interface */
  790. mon_mpdu = dp_rx_mon_restitch_mpdu_from_msdus(soc, mac_id, head_msdu,
  791. tail_msdu, rs);
  792. /* monitor vap cannot be present when mcopy is enabled
  793. * hence same skb can be consumed
  794. */
  795. if (pdev->mcopy_mode)
  796. return dp_send_mgmt_packet_to_stack(soc, mon_mpdu, pdev);
  797. if (mon_mpdu && pdev->monitor_vdev && pdev->monitor_vdev->osif_vdev &&
  798. pdev->monitor_vdev->osif_rx_mon) {
  799. pdev->ppdu_info.rx_status.ppdu_id =
  800. pdev->ppdu_info.com_info.ppdu_id;
  801. pdev->ppdu_info.rx_status.device_id = soc->device_id;
  802. pdev->ppdu_info.rx_status.chan_noise_floor =
  803. pdev->chan_noise_floor;
  804. /*
  805. * if chan_num is not fetched correctly from ppdu RX TLV,
  806. * get it from pdev saved.
  807. */
  808. if (pdev->ppdu_info.rx_status.chan_num == 0)
  809. pdev->ppdu_info.rx_status.chan_num = pdev->mon_chan_num;
  810. qdf_nbuf_update_radiotap(&(pdev->ppdu_info.rx_status),
  811. mon_mpdu, sizeof(struct rx_pkt_tlvs));
  812. pdev->monitor_vdev->osif_rx_mon(pdev->monitor_vdev->osif_vdev,
  813. mon_mpdu,
  814. &pdev->ppdu_info.rx_status);
  815. } else {
  816. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  817. "[%s][%d] mon_mpdu=%pK monitor_vdev %pK osif_vdev %pK"
  818. , __func__, __LINE__, mon_mpdu, pdev->monitor_vdev,
  819. (pdev->monitor_vdev ? pdev->monitor_vdev->osif_vdev
  820. : NULL));
  821. goto mon_deliver_fail;
  822. }
  823. return QDF_STATUS_SUCCESS;
  824. mon_deliver_fail:
  825. mon_skb = head_msdu;
  826. while (mon_skb) {
  827. skb_next = qdf_nbuf_next(mon_skb);
  828. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  829. "[%s][%d] mon_skb=%pK len %u", __func__,
  830. __LINE__, mon_skb, mon_skb->len);
  831. qdf_nbuf_free(mon_skb);
  832. mon_skb = skb_next;
  833. }
  834. return QDF_STATUS_E_INVAL;
  835. }
  836. /**
  837. * dp_rx_mon_deliver_non_std()
  838. * @soc: core txrx main contex
  839. * @mac_id: MAC ID
  840. *
  841. * This function delivers the radio tap and dummy MSDU
  842. * into user layer application for preamble only PPDU.
  843. *
  844. * Return: QDF_STATUS
  845. */
  846. QDF_STATUS dp_rx_mon_deliver_non_std(struct dp_soc *soc,
  847. uint32_t mac_id)
  848. {
  849. struct dp_pdev *pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  850. ol_txrx_rx_mon_fp osif_rx_mon;
  851. qdf_nbuf_t dummy_msdu;
  852. /* Sanity checking */
  853. if ((!pdev->monitor_vdev) || (!pdev->monitor_vdev->osif_rx_mon))
  854. goto mon_deliver_non_std_fail;
  855. /* Generate a dummy skb_buff */
  856. osif_rx_mon = pdev->monitor_vdev->osif_rx_mon;
  857. dummy_msdu = qdf_nbuf_alloc(soc->osdev, MAX_MONITOR_HEADER,
  858. MAX_MONITOR_HEADER, 4, FALSE);
  859. if (!dummy_msdu)
  860. goto allocate_dummy_msdu_fail;
  861. qdf_nbuf_set_pktlen(dummy_msdu, 0);
  862. qdf_nbuf_set_next(dummy_msdu, NULL);
  863. pdev->ppdu_info.rx_status.ppdu_id =
  864. pdev->ppdu_info.com_info.ppdu_id;
  865. /* Apply the radio header to this dummy skb */
  866. qdf_nbuf_update_radiotap(&pdev->ppdu_info.rx_status,
  867. dummy_msdu, MAX_MONITOR_HEADER);
  868. /* deliver to the user layer application */
  869. osif_rx_mon(pdev->monitor_vdev->osif_vdev,
  870. dummy_msdu, NULL);
  871. /* Clear rx_status*/
  872. qdf_mem_zero(&pdev->ppdu_info.rx_status,
  873. sizeof(pdev->ppdu_info.rx_status));
  874. pdev->mon_ppdu_status = DP_PPDU_STATUS_START;
  875. return QDF_STATUS_SUCCESS;
  876. allocate_dummy_msdu_fail:
  877. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP, "[%s][%d] mon_skb=%pK ",
  878. __func__, __LINE__, dummy_msdu);
  879. mon_deliver_non_std_fail:
  880. return QDF_STATUS_E_INVAL;
  881. }
  882. /**
  883. * dp_rx_mon_dest_process() - Brain of the Rx processing functionality
  884. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  885. * @soc: core txrx main contex
  886. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  887. * @quota: No. of units (packets) that can be serviced in one shot.
  888. *
  889. * This function implements the core of Rx functionality. This is
  890. * expected to handle only non-error frames.
  891. *
  892. * Return: none
  893. */
  894. void dp_rx_mon_dest_process(struct dp_soc *soc, uint32_t mac_id, uint32_t quota)
  895. {
  896. struct dp_pdev *pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  897. uint8_t pdev_id;
  898. void *hal_soc;
  899. void *rxdma_dst_ring_desc;
  900. void *mon_dst_srng;
  901. union dp_rx_desc_list_elem_t *head = NULL;
  902. union dp_rx_desc_list_elem_t *tail = NULL;
  903. uint32_t ppdu_id;
  904. uint32_t rx_bufs_used;
  905. int mac_for_pdev = dp_get_mac_id_for_mac(soc, mac_id);
  906. struct cdp_pdev_mon_stats *rx_mon_stats;
  907. mon_dst_srng = dp_rxdma_get_mon_dst_ring(pdev, mac_for_pdev);
  908. if (!mon_dst_srng || !hal_srng_initialized(mon_dst_srng)) {
  909. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  910. "%s %d : HAL Monitor Destination Ring Init Failed -- %pK",
  911. __func__, __LINE__, mon_dst_srng);
  912. return;
  913. }
  914. hal_soc = soc->hal_soc;
  915. qdf_assert((hal_soc && pdev));
  916. qdf_spin_lock_bh(&pdev->mon_lock);
  917. if (qdf_unlikely(hal_srng_access_start(hal_soc, mon_dst_srng))) {
  918. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  919. "%s %d : HAL Monitor Destination Ring access Failed -- %pK",
  920. __func__, __LINE__, mon_dst_srng);
  921. return;
  922. }
  923. pdev_id = pdev->pdev_id;
  924. ppdu_id = pdev->ppdu_info.com_info.ppdu_id;
  925. rx_bufs_used = 0;
  926. rx_mon_stats = &pdev->rx_mon_stats;
  927. while (qdf_likely(rxdma_dst_ring_desc =
  928. hal_srng_dst_peek(hal_soc, mon_dst_srng))) {
  929. qdf_nbuf_t head_msdu, tail_msdu;
  930. uint32_t npackets;
  931. head_msdu = (qdf_nbuf_t) NULL;
  932. tail_msdu = (qdf_nbuf_t) NULL;
  933. rx_bufs_used += dp_rx_mon_mpdu_pop(soc, mac_id,
  934. rxdma_dst_ring_desc,
  935. &head_msdu, &tail_msdu,
  936. &npackets, &ppdu_id,
  937. &head, &tail);
  938. if (ppdu_id != pdev->ppdu_info.com_info.ppdu_id) {
  939. rx_mon_stats->stat_ring_ppdu_id_hist[
  940. rx_mon_stats->ppdu_id_hist_idx] =
  941. pdev->ppdu_info.com_info.ppdu_id;
  942. rx_mon_stats->dest_ring_ppdu_id_hist[
  943. rx_mon_stats->ppdu_id_hist_idx] = ppdu_id;
  944. rx_mon_stats->ppdu_id_hist_idx =
  945. (rx_mon_stats->ppdu_id_hist_idx + 1) &
  946. (MAX_PPDU_ID_HIST - 1);
  947. pdev->mon_ppdu_status = DP_PPDU_STATUS_START;
  948. qdf_mem_zero(&(pdev->ppdu_info.rx_status),
  949. sizeof(pdev->ppdu_info.rx_status));
  950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  951. "%s %d ppdu_id %x != ppdu_info.com_info .ppdu_id %x",
  952. __func__, __LINE__,
  953. ppdu_id, pdev->ppdu_info.com_info.ppdu_id);
  954. break;
  955. }
  956. if (qdf_likely((head_msdu) && (tail_msdu))) {
  957. rx_mon_stats->dest_mpdu_done++;
  958. dp_rx_mon_deliver(soc, mac_id, head_msdu, tail_msdu);
  959. }
  960. rxdma_dst_ring_desc = hal_srng_dst_get_next(hal_soc,
  961. mon_dst_srng);
  962. }
  963. hal_srng_access_end(hal_soc, mon_dst_srng);
  964. qdf_spin_unlock_bh(&pdev->mon_lock);
  965. if (rx_bufs_used) {
  966. rx_mon_stats->dest_ppdu_done++;
  967. dp_rx_buffers_replenish(soc, mac_id,
  968. dp_rxdma_get_mon_buf_ring(pdev,
  969. mac_for_pdev),
  970. dp_rx_get_mon_desc_pool(soc, mac_id,
  971. pdev_id),
  972. rx_bufs_used, &head, &tail);
  973. }
  974. }
  975. #ifndef DISABLE_MON_CONFIG
  976. #ifndef QCA_WIFI_QCA6390
  977. /**
  978. * dp_rx_pdev_mon_buf_attach() - Allocate the monitor descriptor pool
  979. *
  980. * @pdev: physical device handle
  981. * @mac_id: mac id
  982. *
  983. * Return: QDF_STATUS
  984. */
  985. static QDF_STATUS
  986. dp_rx_pdev_mon_buf_attach(struct dp_pdev *pdev, int mac_id) {
  987. uint8_t pdev_id = pdev->pdev_id;
  988. struct dp_soc *soc = pdev->soc;
  989. union dp_rx_desc_list_elem_t *desc_list = NULL;
  990. union dp_rx_desc_list_elem_t *tail = NULL;
  991. struct dp_srng *mon_buf_ring;
  992. uint32_t num_entries;
  993. struct rx_desc_pool *rx_desc_pool;
  994. QDF_STATUS status = QDF_STATUS_SUCCESS;
  995. uint8_t mac_for_pdev = dp_get_mac_id_for_mac(soc, mac_id);
  996. uint32_t rx_desc_pool_size;
  997. mon_buf_ring = &pdev->rxdma_mon_buf_ring[mac_for_pdev];
  998. num_entries = mon_buf_ring->num_entries;
  999. rx_desc_pool = &soc->rx_desc_mon[mac_id];
  1000. dp_debug("Mon RX Desc Pool[%d] entries=%u",
  1001. pdev_id, num_entries);
  1002. rx_desc_pool_size = DP_RX_DESC_ALLOC_MULTIPLIER * num_entries;
  1003. status = dp_rx_desc_pool_alloc(soc, mac_id, rx_desc_pool_size,
  1004. rx_desc_pool);
  1005. if (!QDF_IS_STATUS_SUCCESS(status))
  1006. return status;
  1007. rx_desc_pool->owner = HAL_RX_BUF_RBM_SW3_BM;
  1008. status = dp_rx_buffers_replenish(soc, mac_id, mon_buf_ring,
  1009. rx_desc_pool, num_entries,
  1010. &desc_list, &tail);
  1011. return status;
  1012. }
  1013. static QDF_STATUS
  1014. dp_rx_pdev_mon_buf_detach(struct dp_pdev *pdev, int mac_id)
  1015. {
  1016. struct dp_soc *soc = pdev->soc;
  1017. struct rx_desc_pool *rx_desc_pool;
  1018. rx_desc_pool = &soc->rx_desc_mon[mac_id];
  1019. if (rx_desc_pool->pool_size != 0) {
  1020. if (!dp_is_soc_reinit(soc))
  1021. dp_rx_desc_nbuf_and_pool_free(soc, mac_id,
  1022. rx_desc_pool);
  1023. else
  1024. dp_rx_desc_nbuf_free(soc, rx_desc_pool);
  1025. }
  1026. return QDF_STATUS_SUCCESS;
  1027. }
  1028. /**
  1029. * dp_mon_link_desc_pool_setup(): Allocate and setup link descriptor pool
  1030. * that will be used by HW for various link
  1031. * and queue descriptorsand managed by WBM
  1032. *
  1033. * @soc: soc handle
  1034. * @mac_id: mac id
  1035. *
  1036. * Return: QDF_STATUS
  1037. */
  1038. static
  1039. QDF_STATUS dp_mon_link_desc_pool_setup(struct dp_soc *soc, uint32_t mac_id)
  1040. {
  1041. struct dp_pdev *dp_pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  1042. int mac_for_pdev = dp_get_mac_id_for_mac(soc, mac_id);
  1043. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1044. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1045. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1046. uint32_t total_link_descs, total_mem_size;
  1047. uint32_t num_link_desc_banks;
  1048. uint32_t last_bank_size = 0;
  1049. uint32_t entry_size, num_entries;
  1050. void *mon_desc_srng;
  1051. uint32_t num_replenish_buf;
  1052. struct dp_srng *dp_srng;
  1053. int i;
  1054. qdf_dma_addr_t *baseaddr = NULL;
  1055. dp_srng = &dp_pdev->rxdma_mon_desc_ring[mac_for_pdev];
  1056. num_entries = dp_srng->alloc_size/hal_srng_get_entrysize(
  1057. soc->hal_soc, RXDMA_MONITOR_DESC);
  1058. /* Round up to power of 2 */
  1059. total_link_descs = 1;
  1060. while (total_link_descs < num_entries)
  1061. total_link_descs <<= 1;
  1062. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_HIGH,
  1063. "%s: total_link_descs: %u, link_desc_size: %d",
  1064. __func__, total_link_descs, link_desc_size);
  1065. total_mem_size = total_link_descs * link_desc_size;
  1066. total_mem_size += link_desc_align;
  1067. if (total_mem_size <= max_alloc_size) {
  1068. num_link_desc_banks = 0;
  1069. last_bank_size = total_mem_size;
  1070. } else {
  1071. num_link_desc_banks = (total_mem_size) /
  1072. (max_alloc_size - link_desc_align);
  1073. last_bank_size = total_mem_size %
  1074. (max_alloc_size - link_desc_align);
  1075. }
  1076. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  1077. "%s: total_mem_size: %d, num_link_desc_banks: %u",
  1078. __func__, total_mem_size, num_link_desc_banks);
  1079. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  1080. "%s: max_alloc_size: %d last_bank_size: %d",
  1081. __func__, max_alloc_size, last_bank_size);
  1082. for (i = 0; i < num_link_desc_banks; i++) {
  1083. baseaddr = &dp_pdev->link_desc_banks[mac_for_pdev][i].
  1084. base_paddr_unaligned;
  1085. if (!dp_is_soc_reinit(soc)) {
  1086. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1087. base_vaddr_unaligned =
  1088. qdf_mem_alloc_consistent(soc->osdev,
  1089. soc->osdev->dev,
  1090. max_alloc_size,
  1091. baseaddr);
  1092. if (!dp_pdev->link_desc_banks[mac_for_pdev][i].
  1093. base_vaddr_unaligned) {
  1094. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1095. QDF_TRACE_LEVEL_ERROR,
  1096. "%s: Link desc mem alloc failed",
  1097. __func__);
  1098. goto fail;
  1099. }
  1100. }
  1101. dp_pdev->link_desc_banks[mac_for_pdev][i].size = max_alloc_size;
  1102. dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr =
  1103. (void *)((unsigned long)
  1104. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1105. base_vaddr_unaligned) +
  1106. ((unsigned long)
  1107. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1108. base_vaddr_unaligned) %
  1109. link_desc_align));
  1110. dp_pdev->link_desc_banks[mac_for_pdev][i].base_paddr =
  1111. (unsigned long)
  1112. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1113. base_paddr_unaligned) +
  1114. ((unsigned long)
  1115. (dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr) -
  1116. (unsigned long)
  1117. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1118. base_vaddr_unaligned));
  1119. }
  1120. if (last_bank_size) {
  1121. /* Allocate last bank in case total memory required is not exact
  1122. * multiple of max_alloc_size
  1123. */
  1124. baseaddr = &dp_pdev->link_desc_banks[mac_for_pdev][i].
  1125. base_paddr_unaligned;
  1126. if (!dp_is_soc_reinit(soc)) {
  1127. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1128. base_vaddr_unaligned =
  1129. qdf_mem_alloc_consistent(soc->osdev,
  1130. soc->osdev->dev,
  1131. last_bank_size,
  1132. baseaddr);
  1133. if (!dp_pdev->link_desc_banks[mac_for_pdev][i].
  1134. base_vaddr_unaligned) {
  1135. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1136. QDF_TRACE_LEVEL_ERROR,
  1137. "%s: alloc fail:mon link desc pool",
  1138. __func__);
  1139. goto fail;
  1140. }
  1141. }
  1142. dp_pdev->link_desc_banks[mac_for_pdev][i].size = last_bank_size;
  1143. dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr =
  1144. (void *)((unsigned long)
  1145. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1146. base_vaddr_unaligned) +
  1147. ((unsigned long)
  1148. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1149. base_vaddr_unaligned) %
  1150. link_desc_align));
  1151. dp_pdev->link_desc_banks[mac_for_pdev][i].base_paddr =
  1152. (unsigned long)
  1153. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1154. base_paddr_unaligned) +
  1155. ((unsigned long)
  1156. (dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr) -
  1157. (unsigned long)
  1158. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1159. base_vaddr_unaligned));
  1160. }
  1161. /* Allocate and setup link descriptor idle list for HW internal use */
  1162. entry_size = hal_srng_get_entrysize(soc->hal_soc, RXDMA_MONITOR_DESC);
  1163. total_mem_size = entry_size * total_link_descs;
  1164. mon_desc_srng = dp_pdev->rxdma_mon_desc_ring[mac_for_pdev].hal_srng;
  1165. num_replenish_buf = 0;
  1166. if (total_mem_size <= max_alloc_size) {
  1167. void *desc;
  1168. for (i = 0;
  1169. i < MAX_MON_LINK_DESC_BANKS &&
  1170. dp_pdev->link_desc_banks[mac_for_pdev][i].base_paddr;
  1171. i++) {
  1172. uint32_t num_entries =
  1173. (dp_pdev->link_desc_banks[mac_for_pdev][i].size -
  1174. (unsigned long)
  1175. (dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr) -
  1176. (unsigned long)
  1177. (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1178. base_vaddr_unaligned)) / link_desc_size;
  1179. unsigned long paddr =
  1180. (unsigned long)
  1181. (dp_pdev->link_desc_banks[mac_for_pdev][i].base_paddr);
  1182. unsigned long vaddr =
  1183. (unsigned long)
  1184. (dp_pdev->link_desc_banks[mac_for_pdev][i].base_vaddr);
  1185. hal_srng_access_start_unlocked(soc->hal_soc,
  1186. mon_desc_srng);
  1187. while (num_entries && (desc =
  1188. hal_srng_src_get_next(soc->hal_soc,
  1189. mon_desc_srng))) {
  1190. hal_set_link_desc_addr(desc, i, paddr);
  1191. num_entries--;
  1192. num_replenish_buf++;
  1193. paddr += link_desc_size;
  1194. vaddr += link_desc_size;
  1195. }
  1196. hal_srng_access_end_unlocked(soc->hal_soc,
  1197. mon_desc_srng);
  1198. }
  1199. } else {
  1200. qdf_assert(0);
  1201. }
  1202. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  1203. "%s: successfully replenished %d buffer",
  1204. __func__, num_replenish_buf);
  1205. return QDF_STATUS_SUCCESS;
  1206. fail:
  1207. for (i = 0; i < MAX_MON_LINK_DESC_BANKS; i++) {
  1208. if (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1209. base_vaddr_unaligned) {
  1210. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1211. dp_pdev->link_desc_banks[mac_for_pdev][i].size,
  1212. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1213. base_vaddr_unaligned,
  1214. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1215. base_paddr_unaligned, 0);
  1216. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1217. base_vaddr_unaligned = NULL;
  1218. }
  1219. }
  1220. return QDF_STATUS_E_FAILURE;
  1221. }
  1222. /*
  1223. * Free link descriptor pool that was setup HW
  1224. */
  1225. static
  1226. void dp_mon_link_desc_pool_cleanup(struct dp_soc *soc, uint32_t mac_id)
  1227. {
  1228. struct dp_pdev *dp_pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  1229. int mac_for_pdev = dp_get_mac_id_for_mac(soc, mac_id);
  1230. int i;
  1231. for (i = 0; i < MAX_MON_LINK_DESC_BANKS; i++) {
  1232. if (dp_pdev->link_desc_banks[mac_for_pdev][i].
  1233. base_vaddr_unaligned) {
  1234. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1235. dp_pdev->link_desc_banks[mac_for_pdev][i].size,
  1236. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1237. base_vaddr_unaligned,
  1238. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1239. base_paddr_unaligned, 0);
  1240. dp_pdev->link_desc_banks[mac_for_pdev][i].
  1241. base_vaddr_unaligned = NULL;
  1242. }
  1243. }
  1244. }
  1245. #else
  1246. static
  1247. QDF_STATUS dp_mon_link_desc_pool_setup(struct dp_soc *soc, uint32_t mac_id)
  1248. {
  1249. return QDF_STATUS_SUCCESS;
  1250. }
  1251. static QDF_STATUS
  1252. dp_rx_pdev_mon_buf_attach(struct dp_pdev *pdev, int mac_id)
  1253. {
  1254. return QDF_STATUS_SUCCESS;
  1255. }
  1256. static
  1257. void dp_mon_link_desc_pool_cleanup(struct dp_soc *soc, uint32_t mac_id)
  1258. {
  1259. }
  1260. static QDF_STATUS
  1261. dp_rx_pdev_mon_buf_detach(struct dp_pdev *pdev, int mac_id)
  1262. {
  1263. return QDF_STATUS_SUCCESS;
  1264. }
  1265. #endif
  1266. /**
  1267. * dp_rx_pdev_mon_cmn_detach() - detach dp rx for monitor mode
  1268. * @pdev: core txrx pdev context
  1269. * @mac_id: mac_id for which deinit is to be done
  1270. *
  1271. * This function will free DP Rx resources for
  1272. * monitor mode
  1273. *
  1274. * Return: QDF_STATUS_SUCCESS: success
  1275. * QDF_STATUS_E_RESOURCES: Error return
  1276. */
  1277. static QDF_STATUS
  1278. dp_rx_pdev_mon_cmn_detach(struct dp_pdev *pdev, int mac_id) {
  1279. struct dp_soc *soc = pdev->soc;
  1280. uint8_t pdev_id = pdev->pdev_id;
  1281. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  1282. dp_mon_link_desc_pool_cleanup(soc, mac_for_pdev);
  1283. dp_rx_pdev_mon_status_detach(pdev, mac_for_pdev);
  1284. dp_rx_pdev_mon_buf_detach(pdev, mac_for_pdev);
  1285. return QDF_STATUS_SUCCESS;
  1286. }
  1287. /**
  1288. * dp_rx_pdev_mon_cmn_attach() - attach DP RX for monitor mode
  1289. * @pdev: core txrx pdev context
  1290. * @mac_id: mac_id for which init is to be done
  1291. *
  1292. * This function Will allocate dp rx resource and
  1293. * initialize resources for monitor mode.
  1294. *
  1295. * Return: QDF_STATUS_SUCCESS: success
  1296. * QDF_STATUS_E_RESOURCES: Error return
  1297. */
  1298. static QDF_STATUS
  1299. dp_rx_pdev_mon_cmn_attach(struct dp_pdev *pdev, int mac_id) {
  1300. struct dp_soc *soc = pdev->soc;
  1301. uint8_t pdev_id = pdev->pdev_id;
  1302. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  1303. QDF_STATUS status;
  1304. status = dp_rx_pdev_mon_buf_attach(pdev, mac_for_pdev);
  1305. if (!QDF_IS_STATUS_SUCCESS(status)) {
  1306. dp_err("%s: dp_rx_pdev_mon_buf_attach() failed\n", __func__);
  1307. goto fail;
  1308. }
  1309. status = dp_rx_pdev_mon_status_attach(pdev, mac_for_pdev);
  1310. if (!QDF_IS_STATUS_SUCCESS(status)) {
  1311. dp_err("%s: dp_rx_pdev_mon_status_attach() failed", __func__);
  1312. goto mon_buf_detach;
  1313. }
  1314. status = dp_mon_link_desc_pool_setup(soc, mac_for_pdev);
  1315. if (!QDF_IS_STATUS_SUCCESS(status)) {
  1316. dp_err("%s: dp_mon_link_desc_pool_setup() failed", __func__);
  1317. goto mon_status_detach;
  1318. }
  1319. return status;
  1320. mon_status_detach:
  1321. dp_rx_pdev_mon_status_detach(pdev, mac_for_pdev);
  1322. mon_buf_detach:
  1323. dp_rx_pdev_mon_buf_detach(pdev, mac_for_pdev);
  1324. fail:
  1325. return status;
  1326. }
  1327. /**
  1328. * dp_rx_pdev_mon_attach() - attach DP RX for monitor mode
  1329. * @pdev: core txrx pdev context
  1330. *
  1331. * This function will attach a DP RX for monitor mode instance into
  1332. * the main device (SOC) context. Will allocate dp rx resource and
  1333. * initialize resources.
  1334. *
  1335. * Return: QDF_STATUS_SUCCESS: success
  1336. * QDF_STATUS_E_RESOURCES: Error return
  1337. */
  1338. QDF_STATUS
  1339. dp_rx_pdev_mon_attach(struct dp_pdev *pdev) {
  1340. QDF_STATUS status;
  1341. uint8_t pdev_id = pdev->pdev_id;
  1342. int mac_id;
  1343. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  1344. "%s: pdev attach id=%d", __func__, pdev_id);
  1345. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1346. status = dp_rx_pdev_mon_cmn_attach(pdev, mac_id);
  1347. if (!QDF_IS_STATUS_SUCCESS(status)) {
  1348. QDF_TRACE(QDF_MODULE_ID_DP,
  1349. QDF_TRACE_LEVEL_ERROR,
  1350. "%s: dp_rx_pdev_mon_cmn_attach(%d) failed\n",
  1351. __func__, mac_id);
  1352. goto fail;
  1353. }
  1354. }
  1355. pdev->mon_last_linkdesc_paddr = 0;
  1356. pdev->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
  1357. qdf_spinlock_create(&pdev->mon_lock);
  1358. return QDF_STATUS_SUCCESS;
  1359. fail:
  1360. for (mac_id = mac_id - 1; mac_id >= 0; mac_id--)
  1361. dp_rx_pdev_mon_cmn_detach(pdev, mac_id);
  1362. return status;
  1363. }
  1364. QDF_STATUS
  1365. dp_mon_link_free(struct dp_pdev *pdev) {
  1366. uint8_t pdev_id = pdev->pdev_id;
  1367. struct dp_soc *soc = pdev->soc;
  1368. int mac_id;
  1369. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1370. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  1371. dp_mon_link_desc_pool_cleanup(soc, mac_for_pdev);
  1372. }
  1373. return QDF_STATUS_SUCCESS;
  1374. }
  1375. /**
  1376. * dp_rx_pdev_mon_detach() - detach dp rx for monitor mode
  1377. * @pdev: core txrx pdev context
  1378. *
  1379. * This function will detach DP RX for monitor mode from
  1380. * main device context. will free DP Rx resources for
  1381. * monitor mode
  1382. *
  1383. * Return: QDF_STATUS_SUCCESS: success
  1384. * QDF_STATUS_E_RESOURCES: Error return
  1385. */
  1386. QDF_STATUS
  1387. dp_rx_pdev_mon_detach(struct dp_pdev *pdev) {
  1388. uint8_t pdev_id = pdev->pdev_id;
  1389. int mac_id;
  1390. qdf_spinlock_destroy(&pdev->mon_lock);
  1391. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1392. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  1393. dp_rx_pdev_mon_status_detach(pdev, mac_for_pdev);
  1394. dp_rx_pdev_mon_buf_detach(pdev, mac_for_pdev);
  1395. }
  1396. return QDF_STATUS_SUCCESS;
  1397. }
  1398. #else
  1399. QDF_STATUS
  1400. dp_rx_pdev_mon_attach(struct dp_pdev *pdev) {
  1401. return QDF_STATUS_SUCCESS;
  1402. }
  1403. QDF_STATUS
  1404. dp_rx_pdev_mon_detach(struct dp_pdev *pdev) {
  1405. return QDF_STATUS_SUCCESS;
  1406. }
  1407. QDF_STATUS
  1408. dp_mon_link_free(struct dp_pdev *pdev) {
  1409. return QDF_STATUS_SUCCESS;
  1410. }
  1411. #endif /* DISABLE_MON_CONFIG */