sde_encoder.c 158 KB

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  1. /*
  2. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/kthread.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/input.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/sde_rsc.h>
  25. #include "msm_drv.h"
  26. #include "sde_kms.h"
  27. #include <drm/drm_crtc.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "sde_hwio.h"
  30. #include "sde_hw_catalog.h"
  31. #include "sde_hw_intf.h"
  32. #include "sde_hw_ctl.h"
  33. #include "sde_formats.h"
  34. #include "sde_encoder.h"
  35. #include "sde_encoder_phys.h"
  36. #include "sde_hw_dsc.h"
  37. #include "sde_crtc.h"
  38. #include "sde_trace.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_hw_top.h"
  41. #include "sde_hw_qdss.h"
  42. #include "sde_encoder_dce.h"
  43. #include "sde_vm.h"
  44. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  47. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  48. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  49. (p) ? (p)->parent->base.id : -1, \
  50. (p) ? (p)->intf_idx - INTF_0 : -1, \
  51. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  52. ##__VA_ARGS__)
  53. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  54. (p) ? (p)->parent->base.id : -1, \
  55. (p) ? (p)->intf_idx - INTF_0 : -1, \
  56. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  57. ##__VA_ARGS__)
  58. #define SEC_TO_MILLI_SEC 1000
  59. #define MISR_BUFF_SIZE 256
  60. #define IDLE_SHORT_TIMEOUT 1
  61. #define EVT_TIME_OUT_SPLIT 2
  62. /* worst case poll time for delay_kickoff to be cleared */
  63. #define DELAY_KICKOFF_POLL_TIMEOUT_US 100000
  64. /* Maximum number of VSYNC wait attempts for RSC state transition */
  65. #define MAX_RSC_WAIT 5
  66. /**
  67. * enum sde_enc_rc_events - events for resource control state machine
  68. * @SDE_ENC_RC_EVENT_KICKOFF:
  69. * This event happens at NORMAL priority.
  70. * Event that signals the start of the transfer. When this event is
  71. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  72. * Regardless of the previous state, the resource should be in ON state
  73. * at the end of this event. At the end of this event, a delayed work is
  74. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  75. * ktime.
  76. * @SDE_ENC_RC_EVENT_PRE_STOP:
  77. * This event happens at NORMAL priority.
  78. * This event, when received during the ON state, set RSC to IDLE, and
  79. * and leave the RC STATE in the PRE_OFF state.
  80. * It should be followed by the STOP event as part of encoder disable.
  81. * If received during IDLE or OFF states, it will do nothing.
  82. * @SDE_ENC_RC_EVENT_STOP:
  83. * This event happens at NORMAL priority.
  84. * When this event is received, disable all the MDP/DSI core clocks, and
  85. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  86. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  87. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  88. * Resource state should be in OFF at the end of the event.
  89. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that there is a seamless mode switch is in prgoress. A
  92. * client needs to leave clocks ON to reduce the mode switch latency.
  93. * @SDE_ENC_RC_EVENT_POST_MODESET:
  94. * This event happens at NORMAL priority from a work item.
  95. * Event signals that seamless mode switch is complete and resources are
  96. * acquired. Clients wants to update the rsc with new vtotal and update
  97. * pm_qos vote.
  98. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  99. * This event happens at NORMAL priority from a work item.
  100. * Event signals that there were no frame updates for
  101. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  102. * and request RSC with IDLE state and change the resource state to IDLE.
  103. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  104. * This event is triggered from the input event thread when touch event is
  105. * received from the input device. On receiving this event,
  106. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  107. clocks and enable RSC.
  108. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  109. * off work since a new commit is imminent.
  110. */
  111. enum sde_enc_rc_events {
  112. SDE_ENC_RC_EVENT_KICKOFF = 1,
  113. SDE_ENC_RC_EVENT_PRE_STOP,
  114. SDE_ENC_RC_EVENT_STOP,
  115. SDE_ENC_RC_EVENT_PRE_MODESET,
  116. SDE_ENC_RC_EVENT_POST_MODESET,
  117. SDE_ENC_RC_EVENT_ENTER_IDLE,
  118. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  119. };
  120. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  121. {
  122. struct sde_encoder_virt *sde_enc;
  123. int i;
  124. sde_enc = to_sde_encoder_virt(drm_enc);
  125. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  126. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  127. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  128. if (enable)
  129. SDE_EVT32(DRMID(drm_enc), enable);
  130. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  131. }
  132. }
  133. }
  134. ktime_t sde_encoder_calc_last_vsync_timestamp(struct drm_encoder *drm_enc)
  135. {
  136. struct sde_encoder_virt *sde_enc;
  137. struct sde_encoder_phys *cur_master;
  138. u64 vsync_counter, qtmr_counter, hw_diff, hw_diff_ns, frametime_ns;
  139. ktime_t tvblank, cur_time;
  140. struct intf_status intf_status = {0};
  141. u32 fps;
  142. sde_enc = to_sde_encoder_virt(drm_enc);
  143. cur_master = sde_enc->cur_master;
  144. fps = sde_encoder_get_fps(drm_enc);
  145. if (!cur_master || !cur_master->hw_intf || !fps
  146. || !cur_master->hw_intf->ops.get_vsync_timestamp
  147. || (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)
  148. && !sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  149. return 0;
  150. /*
  151. * avoid calculation and rely on ktime_get, if programmable fetch is enabled
  152. * as the HW VSYNC timestamp will be updated at panel vsync and not at MDP VSYNC
  153. */
  154. if (cur_master->hw_intf->ops.get_status) {
  155. cur_master->hw_intf->ops.get_status(cur_master->hw_intf, &intf_status);
  156. if (intf_status.is_prog_fetch_en)
  157. return 0;
  158. }
  159. vsync_counter = cur_master->hw_intf->ops.get_vsync_timestamp(cur_master->hw_intf);
  160. qtmr_counter = arch_timer_read_counter();
  161. cur_time = ktime_get_ns();
  162. /* check for counter rollover between the two timestamps [56 bits] */
  163. if (qtmr_counter < vsync_counter) {
  164. hw_diff = (0xffffffffffffff - vsync_counter) + qtmr_counter;
  165. SDE_EVT32(DRMID(drm_enc), vsync_counter >> 32, vsync_counter,
  166. qtmr_counter >> 32, qtmr_counter, hw_diff,
  167. fps, SDE_EVTLOG_FUNC_CASE1);
  168. } else {
  169. hw_diff = qtmr_counter - vsync_counter;
  170. }
  171. hw_diff_ns = DIV_ROUND_UP(hw_diff * 1000 * 10, 192); /* 19.2 MHz clock */
  172. frametime_ns = DIV_ROUND_UP(1000000000, fps);
  173. /* avoid setting timestamp, if diff is more than one vsync */
  174. if (ktime_compare(hw_diff_ns, frametime_ns) > 0) {
  175. tvblank = 0;
  176. SDE_EVT32(DRMID(drm_enc), vsync_counter >> 32, vsync_counter,
  177. qtmr_counter >> 32, qtmr_counter, ktime_to_us(hw_diff_ns),
  178. fps, SDE_EVTLOG_ERROR);
  179. } else {
  180. tvblank = ktime_sub_ns(cur_time, hw_diff_ns);
  181. }
  182. SDE_DEBUG_ENC(sde_enc,
  183. "vsync:%llu, qtmr:%llu, diff_ns:%llu, ts:%llu, cur_ts:%llu, fps:%d\n",
  184. vsync_counter, qtmr_counter, ktime_to_us(hw_diff_ns),
  185. ktime_to_us(tvblank), ktime_to_us(cur_time), fps);
  186. SDE_EVT32_VERBOSE(DRMID(drm_enc), hw_diff >> 32, hw_diff, ktime_to_us(hw_diff_ns),
  187. ktime_to_us(tvblank), ktime_to_us(cur_time), fps, SDE_EVTLOG_FUNC_CASE2);
  188. return tvblank;
  189. }
  190. static void _sde_encoder_control_fal10_veto(struct drm_encoder *drm_enc, bool veto)
  191. {
  192. bool clone_mode;
  193. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  194. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  195. struct sde_uidle_cfg *uidle_cfg;
  196. if (!sde_kms->catalog || !sde_kms->hw_uidle ||
  197. !sde_kms->hw_uidle->ops.uidle_fal10_override) {
  198. SDE_ERROR("invalid args\n");
  199. return;
  200. }
  201. /*
  202. * clone mode is the only scenario where we want to enable software override
  203. * of fal10 veto.
  204. */
  205. uidle_cfg = &sde_kms->catalog->uidle_cfg;
  206. clone_mode = sde_encoder_in_clone_mode(drm_enc);
  207. SDE_EVT32(DRMID(drm_enc), clone_mode, veto);
  208. if (clone_mode && veto) {
  209. sde_kms->hw_uidle->ops.uidle_fal10_override(sde_kms->hw_uidle, veto);
  210. sde_enc->fal10_veto_override = true;
  211. } else if (sde_enc->fal10_veto_override && !veto) {
  212. sde_kms->hw_uidle->ops.uidle_fal10_override(sde_kms->hw_uidle, veto);
  213. sde_enc->fal10_veto_override = false;
  214. }
  215. }
  216. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  217. {
  218. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  219. struct msm_drm_private *priv;
  220. struct sde_kms *sde_kms;
  221. struct device *cpu_dev;
  222. struct cpumask *cpu_mask = NULL;
  223. int cpu = 0;
  224. u32 cpu_dma_latency;
  225. priv = drm_enc->dev->dev_private;
  226. sde_kms = to_sde_kms(priv->kms);
  227. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  228. return;
  229. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  230. cpumask_clear(&sde_enc->valid_cpu_mask);
  231. if (sde_enc->mode_info.frame_rate > DEFAULT_FPS)
  232. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  233. if (!cpu_mask &&
  234. sde_encoder_check_curr_mode(drm_enc,
  235. MSM_DISPLAY_CMD_MODE))
  236. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  237. if (!cpu_mask)
  238. return;
  239. for_each_cpu(cpu, cpu_mask) {
  240. cpu_dev = get_cpu_device(cpu);
  241. if (!cpu_dev) {
  242. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  243. cpu);
  244. return;
  245. }
  246. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  247. dev_pm_qos_add_request(cpu_dev,
  248. &sde_enc->pm_qos_cpu_req[cpu],
  249. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  250. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  251. }
  252. }
  253. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  254. {
  255. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  256. struct device *cpu_dev;
  257. int cpu = 0;
  258. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  259. cpu_dev = get_cpu_device(cpu);
  260. if (!cpu_dev) {
  261. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  262. cpu);
  263. continue;
  264. }
  265. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  266. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  267. }
  268. cpumask_clear(&sde_enc->valid_cpu_mask);
  269. }
  270. static bool _sde_encoder_is_autorefresh_enabled(
  271. struct sde_encoder_virt *sde_enc)
  272. {
  273. struct drm_connector *drm_conn;
  274. if (!sde_enc->cur_master ||
  275. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  276. return false;
  277. drm_conn = sde_enc->cur_master->connector;
  278. if (!drm_conn || !drm_conn->state)
  279. return false;
  280. return sde_connector_get_property(drm_conn->state,
  281. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  282. }
  283. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  284. struct sde_hw_qdss *hw_qdss,
  285. struct sde_encoder_phys *phys, bool enable)
  286. {
  287. if (sde_enc->qdss_status == enable)
  288. return;
  289. sde_enc->qdss_status = enable;
  290. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  291. sde_enc->qdss_status);
  292. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  293. }
  294. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  295. s64 timeout_ms, struct sde_encoder_wait_info *info)
  296. {
  297. int rc = 0;
  298. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  299. ktime_t cur_ktime;
  300. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  301. do {
  302. rc = wait_event_timeout(*(info->wq),
  303. atomic_read(info->atomic_cnt) == info->count_check,
  304. wait_time_jiffies);
  305. cur_ktime = ktime_get();
  306. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  307. timeout_ms, atomic_read(info->atomic_cnt),
  308. info->count_check);
  309. /* If we timed out, counter is valid and time is less, wait again */
  310. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  311. (rc == 0) &&
  312. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  313. return rc;
  314. }
  315. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  316. {
  317. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  318. return sde_enc &&
  319. (sde_enc->disp_info.display_type ==
  320. SDE_CONNECTOR_PRIMARY);
  321. }
  322. bool sde_encoder_is_built_in_display(struct drm_encoder *drm_enc)
  323. {
  324. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  325. return sde_enc &&
  326. (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY ||
  327. sde_enc->disp_info.display_type == SDE_CONNECTOR_SECONDARY);
  328. }
  329. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  330. {
  331. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  332. return sde_enc &&
  333. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  334. }
  335. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  336. {
  337. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  338. return sde_enc && sde_enc->cur_master &&
  339. sde_enc->cur_master->cont_splash_enabled;
  340. }
  341. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  342. enum sde_intr_idx intr_idx)
  343. {
  344. SDE_EVT32(DRMID(phys_enc->parent),
  345. phys_enc->intf_idx - INTF_0,
  346. phys_enc->hw_pp->idx - PINGPONG_0,
  347. intr_idx);
  348. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  349. if (phys_enc->parent_ops.handle_frame_done)
  350. phys_enc->parent_ops.handle_frame_done(
  351. phys_enc->parent, phys_enc,
  352. SDE_ENCODER_FRAME_EVENT_ERROR);
  353. }
  354. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  355. enum sde_intr_idx intr_idx,
  356. struct sde_encoder_wait_info *wait_info)
  357. {
  358. struct sde_encoder_irq *irq;
  359. u32 irq_status;
  360. int ret, i;
  361. if (!phys_enc || !phys_enc->hw_pp || !wait_info || intr_idx >= INTR_IDX_MAX) {
  362. SDE_ERROR("invalid params\n");
  363. return -EINVAL;
  364. }
  365. irq = &phys_enc->irq[intr_idx];
  366. /* note: do master / slave checking outside */
  367. /* return EWOULDBLOCK since we know the wait isn't necessary */
  368. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  369. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  370. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  371. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  372. return -EWOULDBLOCK;
  373. }
  374. if (irq->irq_idx < 0) {
  375. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  376. irq->name, irq->hw_idx);
  377. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  378. irq->irq_idx);
  379. return 0;
  380. }
  381. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  382. atomic_read(wait_info->atomic_cnt));
  383. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  384. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  385. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  386. /*
  387. * Some module X may disable interrupt for longer duration
  388. * and it may trigger all interrupts including timer interrupt
  389. * when module X again enable the interrupt.
  390. * That may cause interrupt wait timeout API in this API.
  391. * It is handled by split the wait timer in two halves.
  392. */
  393. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  394. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  395. irq->hw_idx,
  396. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  397. wait_info);
  398. if (ret)
  399. break;
  400. }
  401. if (ret <= 0) {
  402. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  403. irq->irq_idx, true);
  404. if (irq_status) {
  405. unsigned long flags;
  406. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  407. irq->hw_idx, irq->irq_idx,
  408. phys_enc->hw_pp->idx - PINGPONG_0,
  409. atomic_read(wait_info->atomic_cnt));
  410. SDE_DEBUG_PHYS(phys_enc,
  411. "done but irq %d not triggered\n",
  412. irq->irq_idx);
  413. local_irq_save(flags);
  414. irq->cb.func(phys_enc, irq->irq_idx);
  415. local_irq_restore(flags);
  416. ret = 0;
  417. } else {
  418. ret = -ETIMEDOUT;
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  420. irq->hw_idx, irq->irq_idx,
  421. phys_enc->hw_pp->idx - PINGPONG_0,
  422. atomic_read(wait_info->atomic_cnt), irq_status,
  423. SDE_EVTLOG_ERROR);
  424. }
  425. } else {
  426. ret = 0;
  427. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  428. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  429. atomic_read(wait_info->atomic_cnt));
  430. }
  431. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  432. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  433. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  434. return ret;
  435. }
  436. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  437. enum sde_intr_idx intr_idx)
  438. {
  439. struct sde_encoder_irq *irq;
  440. int ret = 0;
  441. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  442. SDE_ERROR("invalid params\n");
  443. return -EINVAL;
  444. }
  445. irq = &phys_enc->irq[intr_idx];
  446. if (irq->irq_idx >= 0) {
  447. SDE_DEBUG_PHYS(phys_enc,
  448. "skipping already registered irq %s type %d\n",
  449. irq->name, irq->intr_type);
  450. return 0;
  451. }
  452. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  453. irq->intr_type, irq->hw_idx);
  454. if (irq->irq_idx < 0) {
  455. SDE_ERROR_PHYS(phys_enc,
  456. "failed to lookup IRQ index for %s type:%d\n",
  457. irq->name, irq->intr_type);
  458. return -EINVAL;
  459. }
  460. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  461. &irq->cb);
  462. if (ret) {
  463. SDE_ERROR_PHYS(phys_enc,
  464. "failed to register IRQ callback for %s\n",
  465. irq->name);
  466. irq->irq_idx = -EINVAL;
  467. return ret;
  468. }
  469. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  470. if (ret) {
  471. SDE_ERROR_PHYS(phys_enc,
  472. "enable IRQ for intr:%s failed, irq_idx %d\n",
  473. irq->name, irq->irq_idx);
  474. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  475. irq->irq_idx, &irq->cb);
  476. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  477. irq->irq_idx, SDE_EVTLOG_ERROR);
  478. irq->irq_idx = -EINVAL;
  479. return ret;
  480. }
  481. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  482. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  483. irq->name, irq->irq_idx);
  484. return ret;
  485. }
  486. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  487. enum sde_intr_idx intr_idx)
  488. {
  489. struct sde_encoder_irq *irq;
  490. int ret;
  491. if (!phys_enc) {
  492. SDE_ERROR("invalid encoder\n");
  493. return -EINVAL;
  494. }
  495. irq = &phys_enc->irq[intr_idx];
  496. /* silently skip irqs that weren't registered */
  497. if (irq->irq_idx < 0) {
  498. SDE_ERROR(
  499. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  500. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  501. irq->irq_idx);
  502. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  503. irq->irq_idx, SDE_EVTLOG_ERROR);
  504. return 0;
  505. }
  506. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  507. if (ret)
  508. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  509. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  510. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  511. &irq->cb);
  512. if (ret)
  513. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  514. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  515. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  516. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  517. irq->irq_idx = -EINVAL;
  518. return 0;
  519. }
  520. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  521. struct sde_encoder_hw_resources *hw_res,
  522. struct drm_connector_state *conn_state)
  523. {
  524. struct sde_encoder_virt *sde_enc = NULL;
  525. int ret, i = 0;
  526. if (!hw_res || !drm_enc || !conn_state || !hw_res->comp_info) {
  527. SDE_ERROR("rc %d, drm_enc %d, res %d, state %d, comp-info %d\n",
  528. -EINVAL, !drm_enc, !hw_res, !conn_state,
  529. hw_res ? !hw_res->comp_info : 0);
  530. return;
  531. }
  532. sde_enc = to_sde_encoder_virt(drm_enc);
  533. SDE_DEBUG_ENC(sde_enc, "\n");
  534. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  535. hw_res->display_type = sde_enc->disp_info.display_type;
  536. /* Query resources used by phys encs, expected to be without overlap */
  537. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  538. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  539. if (phys && phys->ops.get_hw_resources)
  540. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  541. }
  542. /*
  543. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  544. * called from atomic_check phase. Use the below API to get mode
  545. * information of the temporary conn_state passed
  546. */
  547. ret = sde_connector_state_get_topology(conn_state, &hw_res->topology);
  548. if (ret)
  549. SDE_ERROR("failed to get topology ret %d\n", ret);
  550. ret = sde_connector_state_get_compression_info(conn_state,
  551. hw_res->comp_info);
  552. if (ret)
  553. SDE_ERROR("failed to get compression info ret %d\n", ret);
  554. }
  555. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  556. {
  557. struct sde_encoder_virt *sde_enc = NULL;
  558. int i = 0;
  559. unsigned int num_encs;
  560. if (!drm_enc) {
  561. SDE_ERROR("invalid encoder\n");
  562. return;
  563. }
  564. sde_enc = to_sde_encoder_virt(drm_enc);
  565. SDE_DEBUG_ENC(sde_enc, "\n");
  566. num_encs = sde_enc->num_phys_encs;
  567. mutex_lock(&sde_enc->enc_lock);
  568. sde_rsc_client_destroy(sde_enc->rsc_client);
  569. for (i = 0; i < num_encs; i++) {
  570. struct sde_encoder_phys *phys;
  571. phys = sde_enc->phys_vid_encs[i];
  572. if (phys && phys->ops.destroy) {
  573. phys->ops.destroy(phys);
  574. --sde_enc->num_phys_encs;
  575. sde_enc->phys_vid_encs[i] = NULL;
  576. }
  577. phys = sde_enc->phys_cmd_encs[i];
  578. if (phys && phys->ops.destroy) {
  579. phys->ops.destroy(phys);
  580. --sde_enc->num_phys_encs;
  581. sde_enc->phys_cmd_encs[i] = NULL;
  582. }
  583. phys = sde_enc->phys_encs[i];
  584. if (phys && phys->ops.destroy) {
  585. phys->ops.destroy(phys);
  586. --sde_enc->num_phys_encs;
  587. sde_enc->phys_encs[i] = NULL;
  588. }
  589. }
  590. if (sde_enc->num_phys_encs)
  591. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  592. sde_enc->num_phys_encs);
  593. sde_enc->num_phys_encs = 0;
  594. mutex_unlock(&sde_enc->enc_lock);
  595. drm_encoder_cleanup(drm_enc);
  596. mutex_destroy(&sde_enc->enc_lock);
  597. kfree(sde_enc->input_handler);
  598. sde_enc->input_handler = NULL;
  599. kfree(sde_enc);
  600. }
  601. void sde_encoder_helper_update_intf_cfg(
  602. struct sde_encoder_phys *phys_enc)
  603. {
  604. struct sde_encoder_virt *sde_enc;
  605. struct sde_hw_intf_cfg_v1 *intf_cfg;
  606. enum sde_3d_blend_mode mode_3d;
  607. if (!phys_enc || !phys_enc->hw_pp) {
  608. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  609. return;
  610. }
  611. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  612. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  613. SDE_DEBUG_ENC(sde_enc,
  614. "intf_cfg updated for %d at idx %d\n",
  615. phys_enc->intf_idx,
  616. intf_cfg->intf_count);
  617. /* setup interface configuration */
  618. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  619. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  620. return;
  621. }
  622. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  623. if (phys_enc == sde_enc->cur_master) {
  624. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  625. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  626. else
  627. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  628. }
  629. /* configure this interface as master for split display */
  630. if (phys_enc->split_role == ENC_ROLE_MASTER)
  631. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  632. /* setup which pp blk will connect to this intf */
  633. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  634. phys_enc->hw_intf->ops.bind_pingpong_blk(
  635. phys_enc->hw_intf,
  636. true,
  637. phys_enc->hw_pp->idx);
  638. /*setup merge_3d configuration */
  639. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  640. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  641. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  642. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  643. phys_enc->hw_pp->merge_3d->idx;
  644. if (phys_enc->hw_pp->ops.setup_3d_mode)
  645. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  646. mode_3d);
  647. }
  648. void sde_encoder_helper_split_config(
  649. struct sde_encoder_phys *phys_enc,
  650. enum sde_intf interface)
  651. {
  652. struct sde_encoder_virt *sde_enc;
  653. struct split_pipe_cfg *cfg;
  654. struct sde_hw_mdp *hw_mdptop;
  655. enum sde_rm_topology_name topology;
  656. struct msm_display_info *disp_info;
  657. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  658. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  659. return;
  660. }
  661. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  662. hw_mdptop = phys_enc->hw_mdptop;
  663. disp_info = &sde_enc->disp_info;
  664. cfg = &phys_enc->hw_intf->cfg;
  665. memset(cfg, 0, sizeof(*cfg));
  666. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  667. return;
  668. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  669. cfg->split_link_en = true;
  670. /**
  671. * disable split modes since encoder will be operating in as the only
  672. * encoder, either for the entire use case in the case of, for example,
  673. * single DSI, or for this frame in the case of left/right only partial
  674. * update.
  675. */
  676. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  677. if (hw_mdptop->ops.setup_split_pipe)
  678. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  679. if (hw_mdptop->ops.setup_pp_split)
  680. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  681. return;
  682. }
  683. cfg->en = true;
  684. cfg->mode = phys_enc->intf_mode;
  685. cfg->intf = interface;
  686. if (cfg->en && phys_enc->ops.needs_single_flush &&
  687. phys_enc->ops.needs_single_flush(phys_enc))
  688. cfg->split_flush_en = true;
  689. topology = sde_connector_get_topology_name(phys_enc->connector);
  690. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  691. cfg->pp_split_slave = cfg->intf;
  692. else
  693. cfg->pp_split_slave = INTF_MAX;
  694. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  695. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  696. if (hw_mdptop->ops.setup_split_pipe)
  697. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  698. } else if (sde_enc->hw_pp[0]) {
  699. /*
  700. * slave encoder
  701. * - determine split index from master index,
  702. * assume master is first pp
  703. */
  704. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  705. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  706. cfg->pp_split_index);
  707. if (hw_mdptop->ops.setup_pp_split)
  708. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  709. }
  710. }
  711. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  712. {
  713. struct sde_encoder_virt *sde_enc;
  714. int i = 0;
  715. if (!drm_enc)
  716. return false;
  717. sde_enc = to_sde_encoder_virt(drm_enc);
  718. if (!sde_enc)
  719. return false;
  720. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  721. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  722. if (phys && phys->in_clone_mode)
  723. return true;
  724. }
  725. return false;
  726. }
  727. bool sde_encoder_is_cwb_disabling(struct drm_encoder *drm_enc,
  728. struct drm_crtc *crtc)
  729. {
  730. struct sde_encoder_virt *sde_enc;
  731. int i;
  732. if (!drm_enc)
  733. return false;
  734. sde_enc = to_sde_encoder_virt(drm_enc);
  735. if (sde_enc->disp_info.intf_type != DRM_MODE_CONNECTOR_VIRTUAL)
  736. return false;
  737. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  738. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  739. if (sde_encoder_phys_is_cwb_disabling(phys, crtc))
  740. return true;
  741. }
  742. return false;
  743. }
  744. void sde_encoder_set_clone_mode(struct drm_encoder *drm_enc,
  745. struct drm_crtc_state *crtc_state)
  746. {
  747. struct sde_encoder_virt *sde_enc;
  748. struct sde_crtc_state *sde_crtc_state;
  749. int i = 0;
  750. if (!drm_enc || !crtc_state) {
  751. SDE_DEBUG("invalid params\n");
  752. return;
  753. }
  754. sde_enc = to_sde_encoder_virt(drm_enc);
  755. sde_crtc_state = to_sde_crtc_state(crtc_state);
  756. if ((sde_enc->disp_info.intf_type != DRM_MODE_CONNECTOR_VIRTUAL) ||
  757. (!(sde_crtc_state->cwb_enc_mask & drm_encoder_mask(drm_enc))))
  758. return;
  759. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  760. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  761. if (phys) {
  762. phys->in_clone_mode = true;
  763. SDE_DEBUG("enc:%d phys state:%d\n", DRMID(drm_enc), phys->enable_state);
  764. }
  765. }
  766. sde_crtc_state->cwb_enc_mask = 0;
  767. }
  768. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  769. struct drm_crtc_state *crtc_state,
  770. struct drm_connector_state *conn_state)
  771. {
  772. const struct drm_display_mode *mode;
  773. struct drm_display_mode *adj_mode;
  774. int i = 0;
  775. int ret = 0;
  776. mode = &crtc_state->mode;
  777. adj_mode = &crtc_state->adjusted_mode;
  778. /* perform atomic check on the first physical encoder (master) */
  779. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  780. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  781. if (phys && phys->ops.atomic_check)
  782. ret = phys->ops.atomic_check(phys, crtc_state,
  783. conn_state);
  784. else if (phys && phys->ops.mode_fixup)
  785. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  786. ret = -EINVAL;
  787. if (ret) {
  788. SDE_ERROR_ENC(sde_enc,
  789. "mode unsupported, phys idx %d\n", i);
  790. break;
  791. }
  792. }
  793. return ret;
  794. }
  795. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  796. struct drm_crtc_state *crtc_state,
  797. struct drm_connector_state *conn_state,
  798. struct sde_connector_state *sde_conn_state,
  799. struct sde_crtc_state *sde_crtc_state)
  800. {
  801. int ret = 0;
  802. if (crtc_state->mode_changed || crtc_state->active_changed) {
  803. struct sde_rect mode_roi, roi;
  804. mode_roi.x = 0;
  805. mode_roi.y = 0;
  806. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  807. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  808. if (sde_conn_state->rois.num_rects) {
  809. sde_kms_rect_merge_rectangles(
  810. &sde_conn_state->rois, &roi);
  811. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  812. SDE_ERROR_ENC(sde_enc,
  813. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  814. roi.x, roi.y, roi.w, roi.h);
  815. ret = -EINVAL;
  816. }
  817. }
  818. if (sde_crtc_state->user_roi_list.num_rects) {
  819. sde_kms_rect_merge_rectangles(
  820. &sde_crtc_state->user_roi_list, &roi);
  821. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  822. SDE_ERROR_ENC(sde_enc,
  823. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  824. roi.x, roi.y, roi.w, roi.h);
  825. ret = -EINVAL;
  826. }
  827. }
  828. }
  829. return ret;
  830. }
  831. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  832. struct drm_crtc_state *crtc_state,
  833. struct drm_connector_state *conn_state,
  834. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  835. struct sde_connector *sde_conn,
  836. struct sde_connector_state *sde_conn_state)
  837. {
  838. int ret = 0;
  839. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  840. struct msm_sub_mode sub_mode;
  841. if (sde_conn && msm_atomic_needs_modeset(crtc_state, conn_state)) {
  842. struct msm_display_topology *topology = NULL;
  843. sub_mode.dsc_mode = sde_connector_get_property(conn_state,
  844. CONNECTOR_PROP_DSC_MODE);
  845. ret = sde_connector_get_mode_info(&sde_conn->base,
  846. adj_mode, &sub_mode, &sde_conn_state->mode_info);
  847. if (ret) {
  848. SDE_ERROR_ENC(sde_enc,
  849. "failed to get mode info, rc = %d\n", ret);
  850. return ret;
  851. }
  852. if (sde_conn_state->mode_info.comp_info.comp_type &&
  853. sde_conn_state->mode_info.comp_info.comp_ratio >=
  854. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  855. SDE_ERROR_ENC(sde_enc,
  856. "invalid compression ratio: %d\n",
  857. sde_conn_state->mode_info.comp_info.comp_ratio);
  858. ret = -EINVAL;
  859. return ret;
  860. }
  861. /* Reserve dynamic resources, indicating atomic_check phase */
  862. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  863. conn_state, true);
  864. if (ret) {
  865. if (ret != -EAGAIN)
  866. SDE_ERROR_ENC(sde_enc,
  867. "RM failed to reserve resources, rc = %d\n", ret);
  868. return ret;
  869. }
  870. /**
  871. * Update connector state with the topology selected for the
  872. * resource set validated. Reset the topology if we are
  873. * de-activating crtc.
  874. */
  875. if (crtc_state->active) {
  876. topology = &sde_conn_state->mode_info.topology;
  877. ret = sde_rm_update_topology(&sde_kms->rm,
  878. conn_state, topology);
  879. if (ret) {
  880. SDE_ERROR_ENC(sde_enc,
  881. "RM failed to update topology, rc: %d\n", ret);
  882. return ret;
  883. }
  884. }
  885. ret = sde_connector_set_blob_data(conn_state->connector,
  886. conn_state,
  887. CONNECTOR_PROP_SDE_INFO);
  888. if (ret) {
  889. SDE_ERROR_ENC(sde_enc,
  890. "connector failed to update info, rc: %d\n",
  891. ret);
  892. return ret;
  893. }
  894. }
  895. return ret;
  896. }
  897. static void _sde_encoder_get_qsync_fps_callback(struct drm_encoder *drm_enc,
  898. u32 *qsync_fps, struct drm_connector_state *conn_state)
  899. {
  900. struct sde_encoder_virt *sde_enc;
  901. int rc = 0;
  902. struct sde_connector *sde_conn;
  903. if (!qsync_fps)
  904. return;
  905. *qsync_fps = 0;
  906. if (!drm_enc) {
  907. SDE_ERROR("invalid drm encoder\n");
  908. return;
  909. }
  910. sde_enc = to_sde_encoder_virt(drm_enc);
  911. if (!sde_enc->cur_master) {
  912. SDE_ERROR("invalid qsync settings %d\n", !sde_enc->cur_master);
  913. return;
  914. }
  915. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  916. if (sde_conn->ops.get_qsync_min_fps)
  917. rc = sde_conn->ops.get_qsync_min_fps(conn_state);
  918. if (rc < 0) {
  919. SDE_ERROR("invalid qsync min fps %d\n", rc);
  920. return;
  921. }
  922. *qsync_fps = rc;
  923. }
  924. static int _sde_encoder_avr_step_check(struct sde_connector *sde_conn,
  925. struct sde_connector_state *sde_conn_state, u32 step)
  926. {
  927. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(sde_conn_state->base.best_encoder);
  928. u32 nom_fps = drm_mode_vrefresh(sde_conn_state->msm_mode.base);
  929. u32 min_fps, req_fps = 0;
  930. u32 vtotal = sde_conn_state->msm_mode.base->vtotal;
  931. bool has_panel_req = sde_enc->disp_info.has_avr_step_req;
  932. u32 qsync_mode = sde_connector_get_property(&sde_conn_state->base,
  933. CONNECTOR_PROP_QSYNC_MODE);
  934. if (has_panel_req) {
  935. if (!sde_conn->ops.get_avr_step_req) {
  936. SDE_ERROR("unable to retrieve required step rate\n");
  937. return -EINVAL;
  938. }
  939. req_fps = sde_conn->ops.get_avr_step_req(sde_conn->display, nom_fps);
  940. /* when qsync is enabled, the step fps *must* be set to the panel requirement */
  941. if (qsync_mode && req_fps != step) {
  942. SDE_ERROR("invalid avr_step %u, panel requires %u at nominal %u fps\n",
  943. step, req_fps, nom_fps);
  944. return -EINVAL;
  945. }
  946. }
  947. if (!step)
  948. return 0;
  949. _sde_encoder_get_qsync_fps_callback(sde_conn_state->base.best_encoder, &min_fps,
  950. &sde_conn_state->base);
  951. if (!min_fps || !nom_fps || step % nom_fps || step % min_fps || step < nom_fps ||
  952. (vtotal * nom_fps) % step) {
  953. SDE_ERROR("invalid avr_step rate! nom:%u min:%u step:%u vtotal:%u\n", nom_fps,
  954. min_fps, step, vtotal);
  955. return -EINVAL;
  956. }
  957. return 0;
  958. }
  959. static int _sde_encoder_atomic_check_qsync(struct sde_connector *sde_conn,
  960. struct sde_connector_state *sde_conn_state)
  961. {
  962. int rc = 0;
  963. u32 avr_step;
  964. bool qsync_dirty, has_modeset;
  965. struct drm_connector_state *conn_state = &sde_conn_state->base;
  966. u32 qsync_mode = sde_connector_get_property(&sde_conn_state->base,
  967. CONNECTOR_PROP_QSYNC_MODE);
  968. has_modeset = sde_crtc_atomic_check_has_modeset(conn_state->state, conn_state->crtc);
  969. qsync_dirty = msm_property_is_dirty(&sde_conn->property_info,
  970. &sde_conn_state->property_state, CONNECTOR_PROP_QSYNC_MODE);
  971. if (has_modeset && qsync_dirty && (msm_is_mode_seamless_poms(&sde_conn_state->msm_mode) ||
  972. msm_is_mode_seamless_dyn_clk(&sde_conn_state->msm_mode))) {
  973. SDE_ERROR("invalid qsync update during modeset priv flag:%x\n",
  974. sde_conn_state->msm_mode.private_flags);
  975. return -EINVAL;
  976. }
  977. avr_step = sde_connector_get_property(conn_state, CONNECTOR_PROP_AVR_STEP);
  978. if (qsync_dirty || (avr_step != sde_conn->avr_step) || (qsync_mode && has_modeset))
  979. rc = _sde_encoder_avr_step_check(sde_conn, sde_conn_state, avr_step);
  980. return rc;
  981. }
  982. static int sde_encoder_virt_atomic_check(
  983. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  984. struct drm_connector_state *conn_state)
  985. {
  986. struct sde_encoder_virt *sde_enc;
  987. struct sde_kms *sde_kms;
  988. const struct drm_display_mode *mode;
  989. struct drm_display_mode *adj_mode;
  990. struct sde_connector *sde_conn = NULL;
  991. struct sde_connector_state *sde_conn_state = NULL;
  992. struct sde_crtc_state *sde_crtc_state = NULL;
  993. enum sde_rm_topology_name old_top;
  994. enum sde_rm_topology_name top_name;
  995. struct msm_display_info *disp_info;
  996. int ret = 0;
  997. if (!drm_enc || !crtc_state || !conn_state) {
  998. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  999. !drm_enc, !crtc_state, !conn_state);
  1000. return -EINVAL;
  1001. }
  1002. sde_enc = to_sde_encoder_virt(drm_enc);
  1003. disp_info = &sde_enc->disp_info;
  1004. SDE_DEBUG_ENC(sde_enc, "\n");
  1005. sde_kms = sde_encoder_get_kms(drm_enc);
  1006. if (!sde_kms)
  1007. return -EINVAL;
  1008. mode = &crtc_state->mode;
  1009. adj_mode = &crtc_state->adjusted_mode;
  1010. sde_conn = to_sde_connector(conn_state->connector);
  1011. sde_conn_state = to_sde_connector_state(conn_state);
  1012. sde_crtc_state = to_sde_crtc_state(crtc_state);
  1013. ret = sde_connector_set_msm_mode(conn_state, adj_mode);
  1014. if (ret)
  1015. return ret;
  1016. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  1017. crtc_state->active_changed, crtc_state->connectors_changed);
  1018. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  1019. conn_state);
  1020. if (ret)
  1021. return ret;
  1022. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  1023. conn_state, sde_conn_state, sde_crtc_state);
  1024. if (ret)
  1025. return ret;
  1026. /**
  1027. * record topology in previous atomic state to be able to handle
  1028. * topology transitions correctly.
  1029. */
  1030. old_top = sde_connector_get_property(conn_state,
  1031. CONNECTOR_PROP_TOPOLOGY_NAME);
  1032. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  1033. if (ret)
  1034. return ret;
  1035. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  1036. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  1037. if (ret)
  1038. return ret;
  1039. top_name = sde_connector_get_property(conn_state,
  1040. CONNECTOR_PROP_TOPOLOGY_NAME);
  1041. if ((disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK) && crtc_state->active) {
  1042. if ((top_name != SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) &&
  1043. (top_name != SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE)) {
  1044. SDE_ERROR_ENC(sde_enc, "Splitlink check failed, top_name:%d",
  1045. top_name);
  1046. return -EINVAL;
  1047. }
  1048. }
  1049. ret = sde_connector_roi_v1_check_roi(conn_state);
  1050. if (ret) {
  1051. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  1052. ret);
  1053. return ret;
  1054. }
  1055. drm_mode_set_crtcinfo(adj_mode, 0);
  1056. ret = _sde_encoder_atomic_check_qsync(sde_conn, sde_conn_state);
  1057. SDE_EVT32(DRMID(drm_enc), adj_mode->flags,
  1058. sde_conn_state->msm_mode.private_flags,
  1059. old_top, drm_mode_vrefresh(adj_mode), adj_mode->hdisplay,
  1060. adj_mode->vdisplay, adj_mode->htotal, adj_mode->vtotal, ret);
  1061. return ret;
  1062. }
  1063. static void _sde_encoder_get_connector_roi(
  1064. struct sde_encoder_virt *sde_enc,
  1065. struct sde_rect *merged_conn_roi)
  1066. {
  1067. struct drm_connector *drm_conn;
  1068. struct sde_connector_state *c_state;
  1069. if (!sde_enc || !merged_conn_roi)
  1070. return;
  1071. drm_conn = sde_enc->phys_encs[0]->connector;
  1072. if (!drm_conn || !drm_conn->state)
  1073. return;
  1074. c_state = to_sde_connector_state(drm_conn->state);
  1075. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  1076. }
  1077. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  1078. {
  1079. struct sde_encoder_virt *sde_enc;
  1080. struct drm_connector *drm_conn;
  1081. struct drm_display_mode *adj_mode;
  1082. struct sde_rect roi;
  1083. if (!drm_enc) {
  1084. SDE_ERROR("invalid encoder parameter\n");
  1085. return -EINVAL;
  1086. }
  1087. sde_enc = to_sde_encoder_virt(drm_enc);
  1088. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  1089. SDE_ERROR("invalid crtc parameter\n");
  1090. return -EINVAL;
  1091. }
  1092. if (!sde_enc->cur_master) {
  1093. SDE_ERROR("invalid cur_master parameter\n");
  1094. return -EINVAL;
  1095. }
  1096. adj_mode = &sde_enc->cur_master->cached_mode;
  1097. drm_conn = sde_enc->cur_master->connector;
  1098. _sde_encoder_get_connector_roi(sde_enc, &roi);
  1099. if (sde_kms_rect_is_null(&roi)) {
  1100. roi.w = adj_mode->hdisplay;
  1101. roi.h = adj_mode->vdisplay;
  1102. }
  1103. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  1104. sizeof(sde_enc->prv_conn_roi));
  1105. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  1106. return 0;
  1107. }
  1108. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, u32 vsync_source)
  1109. {
  1110. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  1111. struct sde_kms *sde_kms;
  1112. struct sde_hw_mdp *hw_mdptop;
  1113. struct sde_encoder_virt *sde_enc;
  1114. int i;
  1115. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  1116. if (!sde_enc) {
  1117. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  1118. return;
  1119. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1120. SDE_ERROR("invalid num phys enc %d/%d\n",
  1121. sde_enc->num_phys_encs,
  1122. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1123. return;
  1124. }
  1125. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  1126. if (!sde_kms) {
  1127. SDE_ERROR("invalid sde_kms\n");
  1128. return;
  1129. }
  1130. hw_mdptop = sde_kms->hw_mdp;
  1131. if (!hw_mdptop) {
  1132. SDE_ERROR("invalid mdptop\n");
  1133. return;
  1134. }
  1135. if (hw_mdptop->ops.setup_vsync_source) {
  1136. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1137. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  1138. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  1139. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  1140. vsync_cfg.vsync_source = vsync_source;
  1141. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  1142. }
  1143. }
  1144. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  1145. struct msm_display_info *disp_info)
  1146. {
  1147. struct sde_encoder_phys *phys;
  1148. struct sde_connector *sde_conn;
  1149. int i;
  1150. u32 vsync_source;
  1151. if (!sde_enc || !disp_info) {
  1152. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  1153. sde_enc != NULL, disp_info != NULL);
  1154. return;
  1155. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1156. SDE_ERROR("invalid num phys enc %d/%d\n",
  1157. sde_enc->num_phys_encs,
  1158. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1159. return;
  1160. }
  1161. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  1162. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  1163. if (disp_info->is_te_using_watchdog_timer || sde_conn->panel_dead)
  1164. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4 + sde_enc->te_source;
  1165. else
  1166. vsync_source = sde_enc->te_source;
  1167. SDE_EVT32(DRMID(&sde_enc->base), vsync_source,
  1168. disp_info->is_te_using_watchdog_timer);
  1169. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1170. phys = sde_enc->phys_encs[i];
  1171. if (phys && phys->ops.setup_vsync_source)
  1172. phys->ops.setup_vsync_source(phys, vsync_source, disp_info);
  1173. }
  1174. }
  1175. }
  1176. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  1177. bool watchdog_te)
  1178. {
  1179. struct sde_encoder_virt *sde_enc;
  1180. struct msm_display_info disp_info;
  1181. if (!drm_enc) {
  1182. pr_err("invalid drm encoder\n");
  1183. return -EINVAL;
  1184. }
  1185. sde_enc = to_sde_encoder_virt(drm_enc);
  1186. sde_encoder_control_te(drm_enc, false);
  1187. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  1188. disp_info.is_te_using_watchdog_timer = watchdog_te;
  1189. _sde_encoder_update_vsync_source(sde_enc, &disp_info);
  1190. sde_encoder_control_te(drm_enc, true);
  1191. return 0;
  1192. }
  1193. static int _sde_encoder_rsc_client_update_vsync_wait(
  1194. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  1195. int wait_vblank_crtc_id)
  1196. {
  1197. int wait_refcount = 0, ret = 0;
  1198. int pipe = -1;
  1199. int wait_count = 0;
  1200. struct drm_crtc *primary_crtc;
  1201. struct drm_crtc *crtc;
  1202. crtc = sde_enc->crtc;
  1203. if (wait_vblank_crtc_id)
  1204. wait_refcount =
  1205. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  1206. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1207. SDE_EVTLOG_FUNC_ENTRY);
  1208. if (crtc->base.id != wait_vblank_crtc_id) {
  1209. primary_crtc = drm_crtc_find(drm_enc->dev,
  1210. NULL, wait_vblank_crtc_id);
  1211. if (!primary_crtc) {
  1212. SDE_ERROR_ENC(sde_enc,
  1213. "failed to find primary crtc id %d\n",
  1214. wait_vblank_crtc_id);
  1215. return -EINVAL;
  1216. }
  1217. pipe = drm_crtc_index(primary_crtc);
  1218. }
  1219. /**
  1220. * note: VBLANK is expected to be enabled at this point in
  1221. * resource control state machine if on primary CRTC
  1222. */
  1223. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  1224. if (sde_rsc_client_is_state_update_complete(
  1225. sde_enc->rsc_client))
  1226. break;
  1227. if (crtc->base.id == wait_vblank_crtc_id)
  1228. ret = sde_encoder_wait_for_event(drm_enc,
  1229. MSM_ENC_VBLANK);
  1230. else
  1231. drm_wait_one_vblank(drm_enc->dev, pipe);
  1232. if (ret) {
  1233. SDE_ERROR_ENC(sde_enc,
  1234. "wait for vblank failed ret:%d\n", ret);
  1235. /**
  1236. * rsc hardware may hang without vsync. avoid rsc hang
  1237. * by generating the vsync from watchdog timer.
  1238. */
  1239. if (crtc->base.id == wait_vblank_crtc_id)
  1240. sde_encoder_helper_switch_vsync(drm_enc, true);
  1241. }
  1242. }
  1243. if (wait_count >= MAX_RSC_WAIT)
  1244. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  1245. SDE_EVTLOG_ERROR);
  1246. if (wait_refcount)
  1247. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1248. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1249. SDE_EVTLOG_FUNC_EXIT);
  1250. return ret;
  1251. }
  1252. static int _sde_encoder_update_rsc_client(
  1253. struct drm_encoder *drm_enc, bool enable)
  1254. {
  1255. struct sde_encoder_virt *sde_enc;
  1256. struct drm_crtc *crtc;
  1257. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1258. struct sde_rsc_cmd_config *rsc_config;
  1259. int ret;
  1260. struct msm_display_info *disp_info;
  1261. struct msm_mode_info *mode_info;
  1262. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1263. u32 qsync_mode = 0, v_front_porch;
  1264. struct drm_display_mode *mode;
  1265. bool is_vid_mode;
  1266. struct drm_encoder *enc;
  1267. if (!drm_enc || !drm_enc->dev) {
  1268. SDE_ERROR("invalid encoder arguments\n");
  1269. return -EINVAL;
  1270. }
  1271. sde_enc = to_sde_encoder_virt(drm_enc);
  1272. mode_info = &sde_enc->mode_info;
  1273. crtc = sde_enc->crtc;
  1274. if (!sde_enc->crtc) {
  1275. SDE_ERROR("invalid crtc parameter\n");
  1276. return -EINVAL;
  1277. }
  1278. disp_info = &sde_enc->disp_info;
  1279. rsc_config = &sde_enc->rsc_config;
  1280. if (!sde_enc->rsc_client) {
  1281. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1282. return 0;
  1283. }
  1284. /**
  1285. * only primary command mode panel without Qsync can request CMD state.
  1286. * all other panels/displays can request for VID state including
  1287. * secondary command mode panel.
  1288. * Clone mode encoder can request CLK STATE only.
  1289. */
  1290. if (sde_enc->cur_master) {
  1291. qsync_mode = sde_connector_get_qsync_mode(
  1292. sde_enc->cur_master->connector);
  1293. sde_enc->autorefresh_solver_disable =
  1294. _sde_encoder_is_autorefresh_enabled(sde_enc) ? true : false;
  1295. }
  1296. /* left primary encoder keep vote */
  1297. if (sde_encoder_in_clone_mode(drm_enc)) {
  1298. SDE_EVT32(rsc_state, SDE_EVTLOG_FUNC_CASE1);
  1299. return 0;
  1300. }
  1301. if ((disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1302. (disp_info->display_type && qsync_mode) ||
  1303. sde_enc->autorefresh_solver_disable || mode_info->disable_rsc_solver)
  1304. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1305. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1306. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1307. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1308. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1309. drm_for_each_encoder(enc, drm_enc->dev) {
  1310. if (enc->base.id != drm_enc->base.id &&
  1311. sde_encoder_in_cont_splash(enc))
  1312. rsc_state = SDE_RSC_CLK_STATE;
  1313. }
  1314. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1315. MSM_DISPLAY_VIDEO_MODE);
  1316. mode = &sde_enc->crtc->state->mode;
  1317. v_front_porch = mode->vsync_start - mode->vdisplay;
  1318. /* compare specific items and reconfigure the rsc */
  1319. if ((rsc_config->fps != mode_info->frame_rate) ||
  1320. (rsc_config->vtotal != mode_info->vtotal) ||
  1321. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1322. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1323. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1324. rsc_config->fps = mode_info->frame_rate;
  1325. rsc_config->vtotal = mode_info->vtotal;
  1326. rsc_config->prefill_lines = mode_info->prefill_lines;
  1327. rsc_config->jitter_numer = mode_info->jitter_numer;
  1328. rsc_config->jitter_denom = mode_info->jitter_denom;
  1329. sde_enc->rsc_state_init = false;
  1330. }
  1331. SDE_EVT32(DRMID(drm_enc), rsc_state, qsync_mode,
  1332. rsc_config->fps, sde_enc->rsc_state_init);
  1333. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1334. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1335. /* update it only once */
  1336. sde_enc->rsc_state_init = true;
  1337. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1338. rsc_state, rsc_config, crtc->base.id,
  1339. &wait_vblank_crtc_id);
  1340. } else {
  1341. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1342. rsc_state, NULL, crtc->base.id,
  1343. &wait_vblank_crtc_id);
  1344. }
  1345. /**
  1346. * if RSC performed a state change that requires a VBLANK wait, it will
  1347. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1348. *
  1349. * if we are the primary display, we will need to enable and wait
  1350. * locally since we hold the commit thread
  1351. *
  1352. * if we are an external display, we must send a signal to the primary
  1353. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1354. * by the primary panel's VBLANK signals
  1355. */
  1356. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1357. if (ret) {
  1358. SDE_ERROR_ENC(sde_enc,
  1359. "sde rsc client update failed ret:%d\n", ret);
  1360. return ret;
  1361. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1362. return ret;
  1363. }
  1364. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1365. sde_enc, wait_vblank_crtc_id);
  1366. return ret;
  1367. }
  1368. void sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1369. {
  1370. struct sde_encoder_virt *sde_enc;
  1371. int i;
  1372. if (!drm_enc) {
  1373. SDE_ERROR("invalid encoder\n");
  1374. return;
  1375. }
  1376. sde_enc = to_sde_encoder_virt(drm_enc);
  1377. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1378. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1379. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1380. if (phys && phys->ops.irq_control)
  1381. phys->ops.irq_control(phys, enable);
  1382. }
  1383. sde_kms_cpu_vote_for_irq(sde_encoder_get_kms(drm_enc), enable);
  1384. }
  1385. /* keep track of the userspace vblank during modeset */
  1386. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1387. u32 sw_event)
  1388. {
  1389. struct sde_encoder_virt *sde_enc;
  1390. bool enable;
  1391. int i;
  1392. if (!drm_enc) {
  1393. SDE_ERROR("invalid encoder\n");
  1394. return;
  1395. }
  1396. sde_enc = to_sde_encoder_virt(drm_enc);
  1397. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1398. sw_event, sde_enc->vblank_enabled);
  1399. /* nothing to do if vblank not enabled by userspace */
  1400. if (!sde_enc->vblank_enabled)
  1401. return;
  1402. /* disable vblank on pre_modeset */
  1403. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1404. enable = false;
  1405. /* enable vblank on post_modeset */
  1406. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1407. enable = true;
  1408. else
  1409. return;
  1410. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1411. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1412. if (phys && phys->ops.control_vblank_irq)
  1413. phys->ops.control_vblank_irq(phys, enable);
  1414. }
  1415. }
  1416. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1417. {
  1418. struct sde_encoder_virt *sde_enc;
  1419. if (!drm_enc)
  1420. return NULL;
  1421. sde_enc = to_sde_encoder_virt(drm_enc);
  1422. return sde_enc->rsc_client;
  1423. }
  1424. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1425. bool enable)
  1426. {
  1427. struct sde_kms *sde_kms;
  1428. struct sde_encoder_virt *sde_enc;
  1429. int rc;
  1430. sde_enc = to_sde_encoder_virt(drm_enc);
  1431. sde_kms = sde_encoder_get_kms(drm_enc);
  1432. if (!sde_kms)
  1433. return -EINVAL;
  1434. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1435. SDE_EVT32(DRMID(drm_enc), enable);
  1436. if (!sde_enc->cur_master) {
  1437. SDE_ERROR("encoder master not set\n");
  1438. return -EINVAL;
  1439. }
  1440. if (enable) {
  1441. /* enable SDE core clks */
  1442. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1443. if (rc < 0) {
  1444. SDE_ERROR("failed to enable power resource %d\n", rc);
  1445. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1446. return rc;
  1447. }
  1448. sde_enc->elevated_ahb_vote = true;
  1449. /* enable DSI clks */
  1450. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1451. true);
  1452. if (rc) {
  1453. SDE_ERROR("failed to enable clk control %d\n", rc);
  1454. pm_runtime_put_sync(drm_enc->dev->dev);
  1455. return rc;
  1456. }
  1457. /* enable all the irq */
  1458. sde_encoder_irq_control(drm_enc, true);
  1459. _sde_encoder_pm_qos_add_request(drm_enc);
  1460. } else {
  1461. _sde_encoder_pm_qos_remove_request(drm_enc);
  1462. /* disable all the irq */
  1463. sde_encoder_irq_control(drm_enc, false);
  1464. /* disable DSI clks */
  1465. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1466. /* disable SDE core clks */
  1467. pm_runtime_put_sync(drm_enc->dev->dev);
  1468. }
  1469. return 0;
  1470. }
  1471. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1472. bool enable, u32 frame_count)
  1473. {
  1474. struct sde_encoder_virt *sde_enc;
  1475. int i;
  1476. if (!drm_enc) {
  1477. SDE_ERROR("invalid encoder\n");
  1478. return;
  1479. }
  1480. sde_enc = to_sde_encoder_virt(drm_enc);
  1481. if (!sde_enc->misr_reconfigure)
  1482. return;
  1483. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1484. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1485. if (!phys || !phys->ops.setup_misr)
  1486. continue;
  1487. phys->ops.setup_misr(phys, enable, frame_count);
  1488. }
  1489. sde_enc->misr_reconfigure = false;
  1490. }
  1491. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1492. unsigned int type, unsigned int code, int value)
  1493. {
  1494. struct drm_encoder *drm_enc = NULL;
  1495. struct sde_encoder_virt *sde_enc = NULL;
  1496. struct msm_drm_thread *disp_thread = NULL;
  1497. struct msm_drm_private *priv = NULL;
  1498. if (!handle || !handle->handler || !handle->handler->private) {
  1499. SDE_ERROR("invalid encoder for the input event\n");
  1500. return;
  1501. }
  1502. drm_enc = (struct drm_encoder *)handle->handler->private;
  1503. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1504. SDE_ERROR("invalid parameters\n");
  1505. return;
  1506. }
  1507. priv = drm_enc->dev->dev_private;
  1508. sde_enc = to_sde_encoder_virt(drm_enc);
  1509. if (!sde_enc->crtc || (sde_enc->crtc->index
  1510. >= ARRAY_SIZE(priv->disp_thread))) {
  1511. SDE_DEBUG_ENC(sde_enc,
  1512. "invalid cached CRTC: %d or crtc index: %d\n",
  1513. sde_enc->crtc == NULL,
  1514. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1515. return;
  1516. }
  1517. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1518. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1519. kthread_queue_work(&disp_thread->worker,
  1520. &sde_enc->input_event_work);
  1521. }
  1522. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1523. {
  1524. struct sde_encoder_virt *sde_enc;
  1525. if (!drm_enc) {
  1526. SDE_ERROR("invalid encoder\n");
  1527. return;
  1528. }
  1529. sde_enc = to_sde_encoder_virt(drm_enc);
  1530. /* return early if there is no state change */
  1531. if (sde_enc->idle_pc_enabled == enable)
  1532. return;
  1533. sde_enc->idle_pc_enabled = enable;
  1534. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1535. SDE_EVT32(sde_enc->idle_pc_enabled);
  1536. }
  1537. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1538. u32 sw_event)
  1539. {
  1540. struct drm_encoder *drm_enc = &sde_enc->base;
  1541. struct msm_drm_private *priv;
  1542. unsigned int lp, idle_pc_duration;
  1543. struct msm_drm_thread *disp_thread;
  1544. /* return early if called from esd thread */
  1545. if (sde_enc->delay_kickoff)
  1546. return;
  1547. /* set idle timeout based on master connector's lp value */
  1548. if (sde_enc->cur_master)
  1549. lp = sde_connector_get_lp(
  1550. sde_enc->cur_master->connector);
  1551. else
  1552. lp = SDE_MODE_DPMS_ON;
  1553. if (lp == SDE_MODE_DPMS_LP2)
  1554. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1555. else
  1556. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1557. priv = drm_enc->dev->dev_private;
  1558. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1559. kthread_mod_delayed_work(
  1560. &disp_thread->worker,
  1561. &sde_enc->delayed_off_work,
  1562. msecs_to_jiffies(idle_pc_duration));
  1563. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1564. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1565. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1566. sw_event);
  1567. }
  1568. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1569. u32 sw_event)
  1570. {
  1571. if (kthread_cancel_delayed_work_sync(&sde_enc->delayed_off_work))
  1572. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1573. sw_event);
  1574. }
  1575. void sde_encoder_cancel_delayed_work(struct drm_encoder *encoder)
  1576. {
  1577. struct sde_encoder_virt *sde_enc;
  1578. if (!encoder)
  1579. return;
  1580. sde_enc = to_sde_encoder_virt(encoder);
  1581. _sde_encoder_rc_cancel_delayed(sde_enc, 0);
  1582. }
  1583. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1584. u32 sw_event)
  1585. {
  1586. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1587. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1588. else
  1589. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1590. }
  1591. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1592. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1593. {
  1594. int ret = 0;
  1595. mutex_lock(&sde_enc->rc_lock);
  1596. /* return if the resource control is already in ON state */
  1597. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1598. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1599. sw_event);
  1600. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1601. SDE_EVTLOG_FUNC_CASE1);
  1602. goto end;
  1603. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1604. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1605. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1606. sw_event, sde_enc->rc_state);
  1607. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1608. SDE_EVTLOG_ERROR);
  1609. goto end;
  1610. }
  1611. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1612. sde_encoder_irq_control(drm_enc, true);
  1613. _sde_encoder_pm_qos_add_request(drm_enc);
  1614. } else {
  1615. /* enable all the clks and resources */
  1616. ret = _sde_encoder_resource_control_helper(drm_enc,
  1617. true);
  1618. if (ret) {
  1619. SDE_ERROR_ENC(sde_enc,
  1620. "sw_event:%d, rc in state %d\n",
  1621. sw_event, sde_enc->rc_state);
  1622. SDE_EVT32(DRMID(drm_enc), sw_event,
  1623. sde_enc->rc_state,
  1624. SDE_EVTLOG_ERROR);
  1625. goto end;
  1626. }
  1627. _sde_encoder_update_rsc_client(drm_enc, true);
  1628. }
  1629. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1630. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1631. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1632. end:
  1633. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1634. mutex_unlock(&sde_enc->rc_lock);
  1635. return ret;
  1636. }
  1637. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1638. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1639. {
  1640. /* cancel delayed off work, if any */
  1641. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1642. mutex_lock(&sde_enc->rc_lock);
  1643. if (is_vid_mode &&
  1644. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1645. sde_encoder_irq_control(drm_enc, true);
  1646. }
  1647. /* skip if is already OFF or IDLE, resources are off already */
  1648. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1649. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1650. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1651. sw_event, sde_enc->rc_state);
  1652. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1653. SDE_EVTLOG_FUNC_CASE3);
  1654. goto end;
  1655. }
  1656. /**
  1657. * IRQs are still enabled currently, which allows wait for
  1658. * VBLANK which RSC may require to correctly transition to OFF
  1659. */
  1660. _sde_encoder_update_rsc_client(drm_enc, false);
  1661. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1662. SDE_ENC_RC_STATE_PRE_OFF,
  1663. SDE_EVTLOG_FUNC_CASE3);
  1664. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1665. end:
  1666. mutex_unlock(&sde_enc->rc_lock);
  1667. return 0;
  1668. }
  1669. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1670. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1671. {
  1672. int ret = 0;
  1673. mutex_lock(&sde_enc->rc_lock);
  1674. /* return if the resource control is already in OFF state */
  1675. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1676. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1677. sw_event);
  1678. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1679. SDE_EVTLOG_FUNC_CASE4);
  1680. goto end;
  1681. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1682. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1683. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1684. sw_event, sde_enc->rc_state);
  1685. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1686. SDE_EVTLOG_ERROR);
  1687. ret = -EINVAL;
  1688. goto end;
  1689. }
  1690. /**
  1691. * expect to arrive here only if in either idle state or pre-off
  1692. * and in IDLE state the resources are already disabled
  1693. */
  1694. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1695. _sde_encoder_resource_control_helper(drm_enc, false);
  1696. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1697. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1698. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1699. end:
  1700. mutex_unlock(&sde_enc->rc_lock);
  1701. return ret;
  1702. }
  1703. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1704. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1705. {
  1706. int ret = 0;
  1707. mutex_lock(&sde_enc->rc_lock);
  1708. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1709. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1710. sw_event);
  1711. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1712. SDE_EVTLOG_FUNC_CASE5);
  1713. goto end;
  1714. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1715. /* enable all the clks and resources */
  1716. ret = _sde_encoder_resource_control_helper(drm_enc,
  1717. true);
  1718. if (ret) {
  1719. SDE_ERROR_ENC(sde_enc,
  1720. "sw_event:%d, rc in state %d\n",
  1721. sw_event, sde_enc->rc_state);
  1722. SDE_EVT32(DRMID(drm_enc), sw_event,
  1723. sde_enc->rc_state,
  1724. SDE_EVTLOG_ERROR);
  1725. goto end;
  1726. }
  1727. _sde_encoder_update_rsc_client(drm_enc, true);
  1728. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1729. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1730. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1731. }
  1732. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1733. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1734. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1735. _sde_encoder_pm_qos_remove_request(drm_enc);
  1736. end:
  1737. mutex_unlock(&sde_enc->rc_lock);
  1738. return ret;
  1739. }
  1740. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1741. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1742. {
  1743. int ret = 0;
  1744. mutex_lock(&sde_enc->rc_lock);
  1745. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1746. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1747. sw_event);
  1748. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1749. SDE_EVTLOG_FUNC_CASE5);
  1750. goto end;
  1751. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1752. SDE_ERROR_ENC(sde_enc,
  1753. "sw_event:%d, rc:%d !MODESET state\n",
  1754. sw_event, sde_enc->rc_state);
  1755. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1756. SDE_EVTLOG_ERROR);
  1757. ret = -EINVAL;
  1758. goto end;
  1759. }
  1760. _sde_encoder_update_rsc_client(drm_enc, true);
  1761. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1762. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1763. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1764. _sde_encoder_pm_qos_add_request(drm_enc);
  1765. end:
  1766. mutex_unlock(&sde_enc->rc_lock);
  1767. return ret;
  1768. }
  1769. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1770. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1771. {
  1772. struct msm_drm_private *priv;
  1773. struct sde_kms *sde_kms;
  1774. struct drm_crtc *crtc = drm_enc->crtc;
  1775. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1776. struct sde_connector *sde_conn;
  1777. priv = drm_enc->dev->dev_private;
  1778. sde_kms = to_sde_kms(priv->kms);
  1779. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  1780. mutex_lock(&sde_enc->rc_lock);
  1781. if (sde_conn->panel_dead) {
  1782. SDE_DEBUG_ENC(sde_enc, "skip idle. Panel in dead state\n");
  1783. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, SDE_EVTLOG_ERROR);
  1784. goto end;
  1785. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1786. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1787. sw_event, sde_enc->rc_state);
  1788. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, SDE_EVTLOG_ERROR);
  1789. goto end;
  1790. } else if (sde_crtc_frame_pending(sde_enc->crtc) ||
  1791. sde_crtc->kickoff_in_progress) {
  1792. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1793. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1794. sde_crtc_frame_pending(sde_enc->crtc), SDE_EVTLOG_ERROR);
  1795. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1796. goto end;
  1797. }
  1798. if (is_vid_mode) {
  1799. sde_encoder_irq_control(drm_enc, false);
  1800. _sde_encoder_pm_qos_remove_request(drm_enc);
  1801. } else {
  1802. /* disable all the clks and resources */
  1803. _sde_encoder_update_rsc_client(drm_enc, false);
  1804. _sde_encoder_resource_control_helper(drm_enc, false);
  1805. if (!sde_kms->perf.bw_vote_mode)
  1806. memset(&sde_crtc->cur_perf, 0,
  1807. sizeof(struct sde_core_perf_params));
  1808. }
  1809. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1810. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1811. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1812. end:
  1813. mutex_unlock(&sde_enc->rc_lock);
  1814. return 0;
  1815. }
  1816. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1817. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1818. struct msm_drm_private *priv, bool is_vid_mode)
  1819. {
  1820. bool autorefresh_enabled = false;
  1821. struct msm_drm_thread *disp_thread;
  1822. int ret = 0;
  1823. if (!sde_enc->crtc ||
  1824. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1825. SDE_DEBUG_ENC(sde_enc,
  1826. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1827. sde_enc->crtc == NULL,
  1828. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1829. sw_event);
  1830. return -EINVAL;
  1831. }
  1832. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1833. mutex_lock(&sde_enc->rc_lock);
  1834. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1835. if (sde_enc->cur_master &&
  1836. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1837. autorefresh_enabled =
  1838. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1839. sde_enc->cur_master);
  1840. if (autorefresh_enabled) {
  1841. SDE_DEBUG_ENC(sde_enc,
  1842. "not handling early wakeup since auto refresh is enabled\n");
  1843. goto end;
  1844. }
  1845. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1846. kthread_mod_delayed_work(&disp_thread->worker,
  1847. &sde_enc->delayed_off_work,
  1848. msecs_to_jiffies(
  1849. IDLE_POWERCOLLAPSE_DURATION));
  1850. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1851. /* enable all the clks and resources */
  1852. ret = _sde_encoder_resource_control_helper(drm_enc,
  1853. true);
  1854. if (ret) {
  1855. SDE_ERROR_ENC(sde_enc,
  1856. "sw_event:%d, rc in state %d\n",
  1857. sw_event, sde_enc->rc_state);
  1858. SDE_EVT32(DRMID(drm_enc), sw_event,
  1859. sde_enc->rc_state,
  1860. SDE_EVTLOG_ERROR);
  1861. goto end;
  1862. }
  1863. _sde_encoder_update_rsc_client(drm_enc, true);
  1864. /*
  1865. * In some cases, commit comes with slight delay
  1866. * (> 80 ms)after early wake up, prevent clock switch
  1867. * off to avoid jank in next update. So, increase the
  1868. * command mode idle timeout sufficiently to prevent
  1869. * such case.
  1870. */
  1871. kthread_mod_delayed_work(&disp_thread->worker,
  1872. &sde_enc->delayed_off_work,
  1873. msecs_to_jiffies(
  1874. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1875. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1876. }
  1877. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1878. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1879. end:
  1880. mutex_unlock(&sde_enc->rc_lock);
  1881. return ret;
  1882. }
  1883. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1884. u32 sw_event)
  1885. {
  1886. struct sde_encoder_virt *sde_enc;
  1887. struct msm_drm_private *priv;
  1888. int ret = 0;
  1889. bool is_vid_mode = false;
  1890. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1891. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1892. sw_event);
  1893. return -EINVAL;
  1894. }
  1895. sde_enc = to_sde_encoder_virt(drm_enc);
  1896. priv = drm_enc->dev->dev_private;
  1897. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1898. is_vid_mode = true;
  1899. /*
  1900. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1901. * events and return early for other events (ie wb display).
  1902. */
  1903. if (!sde_enc->idle_pc_enabled &&
  1904. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1905. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1906. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1907. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1908. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1909. return 0;
  1910. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1911. sw_event, sde_enc->idle_pc_enabled);
  1912. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1913. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1914. switch (sw_event) {
  1915. case SDE_ENC_RC_EVENT_KICKOFF:
  1916. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1917. is_vid_mode);
  1918. break;
  1919. case SDE_ENC_RC_EVENT_PRE_STOP:
  1920. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1921. is_vid_mode);
  1922. break;
  1923. case SDE_ENC_RC_EVENT_STOP:
  1924. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1925. break;
  1926. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1927. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1928. break;
  1929. case SDE_ENC_RC_EVENT_POST_MODESET:
  1930. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1931. break;
  1932. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1933. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1934. is_vid_mode);
  1935. break;
  1936. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1937. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1938. priv, is_vid_mode);
  1939. break;
  1940. default:
  1941. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1942. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1943. break;
  1944. }
  1945. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1946. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1947. return ret;
  1948. }
  1949. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1950. enum sde_intf_mode intf_mode, struct msm_display_mode *adj_mode)
  1951. {
  1952. int i = 0;
  1953. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1954. bool poms_to_vid = msm_is_mode_seamless_poms_to_vid(adj_mode);
  1955. bool poms_to_cmd = msm_is_mode_seamless_poms_to_cmd(adj_mode);
  1956. if (poms_to_vid)
  1957. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1958. else if (poms_to_cmd)
  1959. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1960. _sde_encoder_update_rsc_client(drm_enc, true);
  1961. if (intf_mode == INTF_MODE_CMD && poms_to_vid) {
  1962. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1963. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1964. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1965. SDE_EVT32(DRMID(&sde_enc->base), intf_mode, poms_to_cmd, poms_to_vid,
  1966. SDE_EVTLOG_FUNC_CASE1);
  1967. } else if (intf_mode == INTF_MODE_VIDEO && poms_to_cmd) {
  1968. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1969. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1970. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1971. SDE_EVT32(DRMID(&sde_enc->base), intf_mode, poms_to_cmd, poms_to_vid,
  1972. SDE_EVTLOG_FUNC_CASE2);
  1973. }
  1974. }
  1975. struct drm_connector *sde_encoder_get_connector(
  1976. struct drm_device *dev, struct drm_encoder *drm_enc)
  1977. {
  1978. struct drm_connector_list_iter conn_iter;
  1979. struct drm_connector *conn = NULL, *conn_search;
  1980. drm_connector_list_iter_begin(dev, &conn_iter);
  1981. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1982. if (conn_search->encoder == drm_enc) {
  1983. conn = conn_search;
  1984. break;
  1985. }
  1986. }
  1987. drm_connector_list_iter_end(&conn_iter);
  1988. return conn;
  1989. }
  1990. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1991. {
  1992. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1993. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1994. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1995. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1996. struct sde_rm_hw_request request_hw;
  1997. int i, j;
  1998. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1999. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2000. sde_enc->hw_pp[i] = NULL;
  2001. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  2002. break;
  2003. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  2004. }
  2005. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2006. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2007. if (phys) {
  2008. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  2009. SDE_HW_BLK_QDSS);
  2010. for (j = 0; j < QDSS_MAX; j++) {
  2011. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  2012. phys->hw_qdss =
  2013. (struct sde_hw_qdss *)qdss_iter.hw;
  2014. break;
  2015. }
  2016. }
  2017. }
  2018. }
  2019. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  2020. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2021. sde_enc->hw_dsc[i] = NULL;
  2022. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  2023. break;
  2024. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  2025. }
  2026. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  2027. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2028. sde_enc->hw_vdc[i] = NULL;
  2029. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  2030. break;
  2031. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  2032. }
  2033. /* Get PP for DSC configuration */
  2034. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2035. struct sde_hw_pingpong *pp = NULL;
  2036. unsigned long features = 0;
  2037. if (!sde_enc->hw_dsc[i])
  2038. continue;
  2039. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  2040. request_hw.type = SDE_HW_BLK_PINGPONG;
  2041. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  2042. break;
  2043. pp = (struct sde_hw_pingpong *) request_hw.hw;
  2044. features = pp->ops.get_hw_caps(pp);
  2045. if (test_bit(SDE_PINGPONG_DSC, &features))
  2046. sde_enc->hw_dsc_pp[i] = pp;
  2047. else
  2048. sde_enc->hw_dsc_pp[i] = NULL;
  2049. }
  2050. }
  2051. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  2052. struct drm_display_mode *adj_mode, struct msm_display_mode *msm_mode, bool pre_modeset)
  2053. {
  2054. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2055. enum sde_intf_mode intf_mode;
  2056. struct drm_display_mode *old_adj_mode = NULL;
  2057. int ret;
  2058. bool is_cmd_mode = false, res_switch = false;
  2059. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2060. is_cmd_mode = true;
  2061. if (pre_modeset) {
  2062. if (sde_enc->cur_master)
  2063. old_adj_mode = &sde_enc->cur_master->cached_mode;
  2064. if (old_adj_mode && is_cmd_mode)
  2065. res_switch = !drm_mode_match(old_adj_mode, adj_mode,
  2066. DRM_MODE_MATCH_TIMINGS);
  2067. if (res_switch && sde_enc->disp_info.is_te_using_watchdog_timer) {
  2068. /*
  2069. * add tx wait for sim panel to avoid wd timer getting
  2070. * updated in middle of frame to avoid early vsync
  2071. */
  2072. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2073. if (ret && ret != -EWOULDBLOCK) {
  2074. SDE_ERROR_ENC(sde_enc, "wait for idle failed %d\n", ret);
  2075. SDE_EVT32(DRMID(drm_enc), ret, SDE_EVTLOG_ERROR);
  2076. return ret;
  2077. }
  2078. }
  2079. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2080. if (msm_is_mode_seamless_dms(msm_mode) ||
  2081. (msm_is_mode_seamless_dyn_clk(msm_mode) &&
  2082. is_cmd_mode)) {
  2083. /* restore resource state before releasing them */
  2084. ret = sde_encoder_resource_control(drm_enc,
  2085. SDE_ENC_RC_EVENT_PRE_MODESET);
  2086. if (ret) {
  2087. SDE_ERROR_ENC(sde_enc,
  2088. "sde resource control failed: %d\n",
  2089. ret);
  2090. return ret;
  2091. }
  2092. /*
  2093. * Disable dce before switching the mode and after pre-
  2094. * modeset to guarantee previous kickoff has finished.
  2095. */
  2096. sde_encoder_dce_disable(sde_enc);
  2097. } else if (msm_is_mode_seamless_poms(msm_mode)) {
  2098. _sde_encoder_modeset_helper_locked(drm_enc,
  2099. SDE_ENC_RC_EVENT_PRE_MODESET);
  2100. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  2101. msm_mode);
  2102. }
  2103. } else {
  2104. if (msm_is_mode_seamless_dms(msm_mode) ||
  2105. (msm_is_mode_seamless_dyn_clk(msm_mode) &&
  2106. is_cmd_mode))
  2107. sde_encoder_resource_control(&sde_enc->base,
  2108. SDE_ENC_RC_EVENT_POST_MODESET);
  2109. else if (msm_is_mode_seamless_poms(msm_mode))
  2110. _sde_encoder_modeset_helper_locked(drm_enc,
  2111. SDE_ENC_RC_EVENT_POST_MODESET);
  2112. }
  2113. return 0;
  2114. }
  2115. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  2116. struct drm_display_mode *mode,
  2117. struct drm_display_mode *adj_mode)
  2118. {
  2119. struct sde_encoder_virt *sde_enc;
  2120. struct sde_kms *sde_kms;
  2121. struct drm_connector *conn;
  2122. struct sde_connector_state *c_state;
  2123. struct msm_display_mode *msm_mode;
  2124. struct sde_crtc *sde_crtc;
  2125. int i = 0, ret;
  2126. int num_lm, num_intf, num_pp_per_intf;
  2127. if (!drm_enc) {
  2128. SDE_ERROR("invalid encoder\n");
  2129. return;
  2130. }
  2131. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2132. SDE_ERROR("power resource is not enabled\n");
  2133. return;
  2134. }
  2135. sde_kms = sde_encoder_get_kms(drm_enc);
  2136. if (!sde_kms)
  2137. return;
  2138. sde_enc = to_sde_encoder_virt(drm_enc);
  2139. SDE_DEBUG_ENC(sde_enc, "\n");
  2140. SDE_EVT32(DRMID(drm_enc));
  2141. /*
  2142. * cache the crtc in sde_enc on enable for duration of use case
  2143. * for correctly servicing asynchronous irq events and timers
  2144. */
  2145. if (!drm_enc->crtc) {
  2146. SDE_ERROR("invalid crtc\n");
  2147. return;
  2148. }
  2149. sde_enc->crtc = drm_enc->crtc;
  2150. sde_crtc = to_sde_crtc(drm_enc->crtc);
  2151. sde_crtc_set_qos_dirty(drm_enc->crtc);
  2152. /* get and store the mode_info */
  2153. conn = sde_encoder_get_connector(sde_kms->dev, drm_enc);
  2154. if (!conn) {
  2155. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  2156. return;
  2157. } else if (!conn->state) {
  2158. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  2159. return;
  2160. }
  2161. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  2162. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  2163. c_state = to_sde_connector_state(conn->state);
  2164. if (!c_state) {
  2165. SDE_ERROR_ENC(sde_enc, "could not get connector state");
  2166. return;
  2167. }
  2168. /* cancel delayed off work, if any */
  2169. kthread_cancel_delayed_work_sync(&sde_enc->delayed_off_work);
  2170. /* release resources before seamless mode change */
  2171. msm_mode = &c_state->msm_mode;
  2172. ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, msm_mode, true);
  2173. if (ret)
  2174. return;
  2175. /* reserve dynamic resources now, indicating non test-only */
  2176. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state, conn->state, false);
  2177. if (ret) {
  2178. SDE_ERROR_ENC(sde_enc, "failed to reserve hw resources, %d\n", ret);
  2179. return;
  2180. }
  2181. /* assign the reserved HW blocks to this encoder */
  2182. _sde_encoder_virt_populate_hw_res(drm_enc);
  2183. /* determine left HW PP block to map to INTF */
  2184. num_lm = sde_enc->mode_info.topology.num_lm;
  2185. num_intf = sde_enc->mode_info.topology.num_intf;
  2186. num_pp_per_intf = num_lm / num_intf;
  2187. if (!num_pp_per_intf)
  2188. num_pp_per_intf = 1;
  2189. /* perform mode_set on phys_encs */
  2190. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2191. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2192. if (phys) {
  2193. if (!sde_enc->hw_pp[i * num_pp_per_intf]) {
  2194. SDE_ERROR_ENC(sde_enc, "invalid phys %d pp_per_intf %d",
  2195. i, num_pp_per_intf);
  2196. return;
  2197. }
  2198. phys->hw_pp = sde_enc->hw_pp[i * num_pp_per_intf];
  2199. phys->connector = conn;
  2200. if (phys->ops.mode_set)
  2201. phys->ops.mode_set(phys, mode, adj_mode,
  2202. &sde_crtc->reinit_crtc_mixers);
  2203. }
  2204. }
  2205. /* update resources after seamless mode change */
  2206. sde_encoder_virt_modeset_rc(drm_enc, adj_mode, msm_mode, false);
  2207. }
  2208. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  2209. {
  2210. struct sde_encoder_virt *sde_enc;
  2211. struct sde_encoder_phys *phys;
  2212. int i;
  2213. if (!drm_enc) {
  2214. SDE_ERROR("invalid parameters\n");
  2215. return;
  2216. }
  2217. sde_enc = to_sde_encoder_virt(drm_enc);
  2218. if (!sde_enc) {
  2219. SDE_ERROR("invalid sde encoder\n");
  2220. return;
  2221. }
  2222. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2223. phys = sde_enc->phys_encs[i];
  2224. if (phys && phys->ops.control_te)
  2225. phys->ops.control_te(phys, enable);
  2226. }
  2227. }
  2228. static int _sde_encoder_input_connect(struct input_handler *handler,
  2229. struct input_dev *dev, const struct input_device_id *id)
  2230. {
  2231. struct input_handle *handle;
  2232. int rc = 0;
  2233. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  2234. if (!handle)
  2235. return -ENOMEM;
  2236. handle->dev = dev;
  2237. handle->handler = handler;
  2238. handle->name = handler->name;
  2239. rc = input_register_handle(handle);
  2240. if (rc) {
  2241. pr_err("failed to register input handle\n");
  2242. goto error;
  2243. }
  2244. rc = input_open_device(handle);
  2245. if (rc) {
  2246. pr_err("failed to open input device\n");
  2247. goto error_unregister;
  2248. }
  2249. return 0;
  2250. error_unregister:
  2251. input_unregister_handle(handle);
  2252. error:
  2253. kfree(handle);
  2254. return rc;
  2255. }
  2256. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  2257. {
  2258. input_close_device(handle);
  2259. input_unregister_handle(handle);
  2260. kfree(handle);
  2261. }
  2262. /**
  2263. * Structure for specifying event parameters on which to receive callbacks.
  2264. * This structure will trigger a callback in case of a touch event (specified by
  2265. * EV_ABS) where there is a change in X and Y coordinates,
  2266. */
  2267. static const struct input_device_id sde_input_ids[] = {
  2268. {
  2269. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  2270. .evbit = { BIT_MASK(EV_ABS) },
  2271. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  2272. BIT_MASK(ABS_MT_POSITION_X) |
  2273. BIT_MASK(ABS_MT_POSITION_Y) },
  2274. },
  2275. { },
  2276. };
  2277. static void _sde_encoder_input_handler_register(
  2278. struct drm_encoder *drm_enc)
  2279. {
  2280. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2281. int rc;
  2282. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2283. !sde_enc->input_event_enabled)
  2284. return;
  2285. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2286. sde_enc->input_handler->private = sde_enc;
  2287. /* register input handler if not already registered */
  2288. rc = input_register_handler(sde_enc->input_handler);
  2289. if (rc) {
  2290. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2291. rc);
  2292. kfree(sde_enc->input_handler);
  2293. }
  2294. }
  2295. }
  2296. static void _sde_encoder_input_handler_unregister(
  2297. struct drm_encoder *drm_enc)
  2298. {
  2299. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2300. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2301. !sde_enc->input_event_enabled)
  2302. return;
  2303. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2304. input_unregister_handler(sde_enc->input_handler);
  2305. sde_enc->input_handler->private = NULL;
  2306. }
  2307. }
  2308. static int _sde_encoder_input_handler(
  2309. struct sde_encoder_virt *sde_enc)
  2310. {
  2311. struct input_handler *input_handler = NULL;
  2312. int rc = 0;
  2313. if (sde_enc->input_handler) {
  2314. SDE_ERROR_ENC(sde_enc,
  2315. "input_handle is active. unexpected\n");
  2316. return -EINVAL;
  2317. }
  2318. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2319. if (!input_handler)
  2320. return -ENOMEM;
  2321. input_handler->event = sde_encoder_input_event_handler;
  2322. input_handler->connect = _sde_encoder_input_connect;
  2323. input_handler->disconnect = _sde_encoder_input_disconnect;
  2324. input_handler->name = "sde";
  2325. input_handler->id_table = sde_input_ids;
  2326. sde_enc->input_handler = input_handler;
  2327. return rc;
  2328. }
  2329. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2330. {
  2331. struct sde_encoder_virt *sde_enc = NULL;
  2332. struct sde_kms *sde_kms;
  2333. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2334. SDE_ERROR("invalid parameters\n");
  2335. return;
  2336. }
  2337. sde_kms = sde_encoder_get_kms(drm_enc);
  2338. if (!sde_kms)
  2339. return;
  2340. sde_enc = to_sde_encoder_virt(drm_enc);
  2341. if (!sde_enc || !sde_enc->cur_master) {
  2342. SDE_DEBUG("invalid sde encoder/master\n");
  2343. return;
  2344. }
  2345. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2346. sde_enc->cur_master->hw_mdptop &&
  2347. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2348. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2349. sde_enc->cur_master->hw_mdptop);
  2350. if (sde_enc->cur_master->hw_mdptop &&
  2351. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc &&
  2352. !sde_in_trusted_vm(sde_kms))
  2353. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2354. sde_enc->cur_master->hw_mdptop,
  2355. sde_kms->catalog);
  2356. if (sde_enc->cur_master->hw_ctl &&
  2357. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2358. !sde_enc->cur_master->cont_splash_enabled)
  2359. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2360. sde_enc->cur_master->hw_ctl,
  2361. &sde_enc->cur_master->intf_cfg_v1);
  2362. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info);
  2363. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2364. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2365. _sde_encoder_control_fal10_veto(drm_enc, true);
  2366. }
  2367. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2368. {
  2369. struct sde_kms *sde_kms;
  2370. void *dither_cfg = NULL;
  2371. int ret = 0, i = 0;
  2372. size_t len = 0;
  2373. enum sde_rm_topology_name topology;
  2374. struct drm_encoder *drm_enc;
  2375. struct msm_display_dsc_info *dsc = NULL;
  2376. struct sde_encoder_virt *sde_enc;
  2377. struct sde_hw_pingpong *hw_pp;
  2378. u32 bpp, bpc;
  2379. int num_lm;
  2380. if (!phys || !phys->connector || !phys->hw_pp ||
  2381. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2382. return;
  2383. sde_kms = sde_encoder_get_kms(phys->parent);
  2384. if (!sde_kms)
  2385. return;
  2386. topology = sde_connector_get_topology_name(phys->connector);
  2387. if ((topology == SDE_RM_TOPOLOGY_NONE) ||
  2388. ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2389. (phys->split_role == ENC_ROLE_SLAVE)))
  2390. return;
  2391. drm_enc = phys->parent;
  2392. sde_enc = to_sde_encoder_virt(drm_enc);
  2393. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2394. bpc = dsc->config.bits_per_component;
  2395. bpp = dsc->config.bits_per_pixel;
  2396. /* disable dither for 10 bpp or 10bpc dsc config */
  2397. if (bpp == 10 || bpc == 10) {
  2398. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2399. return;
  2400. }
  2401. ret = sde_connector_get_dither_cfg(phys->connector,
  2402. phys->connector->state, &dither_cfg,
  2403. &len, sde_enc->idle_pc_restore);
  2404. /* skip reg writes when return values are invalid or no data */
  2405. if (ret && ret == -ENODATA)
  2406. return;
  2407. num_lm = sde_rm_topology_get_num_lm(&sde_kms->rm, topology);
  2408. for (i = 0; i < num_lm; i++) {
  2409. hw_pp = sde_enc->hw_pp[i];
  2410. phys->hw_pp->ops.setup_dither(hw_pp,
  2411. dither_cfg, len);
  2412. }
  2413. }
  2414. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2415. {
  2416. struct sde_encoder_virt *sde_enc = NULL;
  2417. int i;
  2418. if (!drm_enc) {
  2419. SDE_ERROR("invalid encoder\n");
  2420. return;
  2421. }
  2422. sde_enc = to_sde_encoder_virt(drm_enc);
  2423. if (!sde_enc->cur_master) {
  2424. SDE_DEBUG("virt encoder has no master\n");
  2425. return;
  2426. }
  2427. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2428. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2429. sde_enc->idle_pc_restore = true;
  2430. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2431. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2432. if (!phys)
  2433. continue;
  2434. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2435. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2436. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2437. phys->ops.restore(phys);
  2438. _sde_encoder_setup_dither(phys);
  2439. }
  2440. if (sde_enc->cur_master->ops.restore)
  2441. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2442. _sde_encoder_virt_enable_helper(drm_enc);
  2443. sde_encoder_control_te(drm_enc, true);
  2444. }
  2445. static void sde_encoder_populate_encoder_phys(struct drm_encoder *drm_enc,
  2446. struct sde_encoder_virt *sde_enc, struct msm_display_mode *msm_mode)
  2447. {
  2448. struct msm_compression_info *comp_info = &sde_enc->mode_info.comp_info;
  2449. struct msm_display_info *disp_info = &sde_enc->disp_info;
  2450. int i;
  2451. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2452. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2453. if (!phys)
  2454. continue;
  2455. phys->comp_type = comp_info->comp_type;
  2456. phys->comp_ratio = comp_info->comp_ratio;
  2457. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2458. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2459. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2460. phys->dsc_extra_pclk_cycle_cnt =
  2461. comp_info->dsc_info.pclk_per_line;
  2462. phys->dsc_extra_disp_width =
  2463. comp_info->dsc_info.extra_width;
  2464. phys->dce_bytes_per_line =
  2465. comp_info->dsc_info.bytes_per_pkt *
  2466. comp_info->dsc_info.pkt_per_line;
  2467. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2468. phys->dce_bytes_per_line =
  2469. comp_info->vdc_info.bytes_per_pkt *
  2470. comp_info->vdc_info.pkt_per_line;
  2471. }
  2472. if (phys != sde_enc->cur_master) {
  2473. /**
  2474. * on DMS request, the encoder will be enabled
  2475. * already. Invoke restore to reconfigure the
  2476. * new mode.
  2477. */
  2478. if ((msm_is_mode_seamless_dms(msm_mode) ||
  2479. msm_is_mode_seamless_dyn_clk(msm_mode)) &&
  2480. phys->ops.restore)
  2481. phys->ops.restore(phys);
  2482. else if (phys->ops.enable)
  2483. phys->ops.enable(phys);
  2484. }
  2485. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2486. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2487. phys->ops.setup_misr(phys, true,
  2488. sde_enc->misr_frame_count);
  2489. }
  2490. if ((msm_is_mode_seamless_dms(msm_mode) ||
  2491. msm_is_mode_seamless_dyn_clk(msm_mode)) &&
  2492. sde_enc->cur_master->ops.restore)
  2493. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2494. else if (sde_enc->cur_master->ops.enable)
  2495. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2496. }
  2497. static void sde_encoder_off_work(struct kthread_work *work)
  2498. {
  2499. struct sde_encoder_virt *sde_enc = container_of(work,
  2500. struct sde_encoder_virt, delayed_off_work.work);
  2501. struct drm_encoder *drm_enc;
  2502. if (!sde_enc) {
  2503. SDE_ERROR("invalid sde encoder\n");
  2504. return;
  2505. }
  2506. drm_enc = &sde_enc->base;
  2507. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2508. sde_encoder_idle_request(drm_enc);
  2509. SDE_ATRACE_END("sde_encoder_off_work");
  2510. }
  2511. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2512. {
  2513. struct sde_encoder_virt *sde_enc = NULL;
  2514. bool has_master_enc = false;
  2515. int i, ret = 0;
  2516. struct sde_connector_state *c_state;
  2517. struct drm_display_mode *cur_mode = NULL;
  2518. struct msm_display_mode *msm_mode;
  2519. if (!drm_enc || !drm_enc->crtc) {
  2520. SDE_ERROR("invalid encoder\n");
  2521. return;
  2522. }
  2523. sde_enc = to_sde_encoder_virt(drm_enc);
  2524. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2525. SDE_ERROR("power resource is not enabled\n");
  2526. return;
  2527. }
  2528. if (!sde_enc->crtc)
  2529. sde_enc->crtc = drm_enc->crtc;
  2530. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2531. SDE_DEBUG_ENC(sde_enc, "\n");
  2532. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2533. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2534. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2535. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2536. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2537. sde_enc->cur_master = phys;
  2538. has_master_enc = true;
  2539. break;
  2540. }
  2541. }
  2542. if (!has_master_enc) {
  2543. sde_enc->cur_master = NULL;
  2544. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2545. return;
  2546. }
  2547. _sde_encoder_input_handler_register(drm_enc);
  2548. c_state = to_sde_connector_state(sde_enc->cur_master->connector->state);
  2549. if (!c_state) {
  2550. SDE_ERROR("invalid connector state\n");
  2551. return;
  2552. }
  2553. msm_mode = &c_state->msm_mode;
  2554. if ((drm_enc->crtc->state->connectors_changed &&
  2555. sde_encoder_in_clone_mode(drm_enc)) ||
  2556. !(msm_is_mode_seamless_vrr(msm_mode)
  2557. || msm_is_mode_seamless_dms(msm_mode)
  2558. || msm_is_mode_seamless_dyn_clk(msm_mode)))
  2559. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2560. sde_encoder_off_work);
  2561. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2562. if (ret) {
  2563. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2564. ret);
  2565. return;
  2566. }
  2567. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2568. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2569. /* turn off vsync_in to update tear check configuration */
  2570. sde_encoder_control_te(drm_enc, false);
  2571. sde_encoder_populate_encoder_phys(drm_enc, sde_enc, msm_mode);
  2572. _sde_encoder_virt_enable_helper(drm_enc);
  2573. sde_encoder_control_te(drm_enc, true);
  2574. }
  2575. void sde_encoder_virt_reset(struct drm_encoder *drm_enc)
  2576. {
  2577. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2578. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  2579. int i = 0;
  2580. _sde_encoder_control_fal10_veto(drm_enc, false);
  2581. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2582. if (sde_enc->phys_encs[i]) {
  2583. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2584. sde_enc->phys_encs[i]->connector = NULL;
  2585. }
  2586. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2587. }
  2588. sde_enc->cur_master = NULL;
  2589. /*
  2590. * clear the cached crtc in sde_enc on use case finish, after all the
  2591. * outstanding events and timers have been completed
  2592. */
  2593. sde_enc->crtc = NULL;
  2594. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2595. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2596. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2597. }
  2598. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2599. {
  2600. struct sde_encoder_virt *sde_enc = NULL;
  2601. struct sde_connector *sde_conn;
  2602. struct sde_kms *sde_kms;
  2603. enum sde_intf_mode intf_mode;
  2604. int ret, i = 0;
  2605. if (!drm_enc) {
  2606. SDE_ERROR("invalid encoder\n");
  2607. return;
  2608. } else if (!drm_enc->dev) {
  2609. SDE_ERROR("invalid dev\n");
  2610. return;
  2611. } else if (!drm_enc->dev->dev_private) {
  2612. SDE_ERROR("invalid dev_private\n");
  2613. return;
  2614. }
  2615. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2616. SDE_ERROR("power resource is not enabled\n");
  2617. return;
  2618. }
  2619. sde_enc = to_sde_encoder_virt(drm_enc);
  2620. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  2621. SDE_DEBUG_ENC(sde_enc, "\n");
  2622. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2623. if (!sde_kms)
  2624. return;
  2625. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2626. SDE_EVT32(DRMID(drm_enc));
  2627. /* wait for idle */
  2628. if (!sde_encoder_in_clone_mode(drm_enc))
  2629. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2630. _sde_encoder_input_handler_unregister(drm_enc);
  2631. flush_delayed_work(&sde_conn->status_work);
  2632. /*
  2633. * For primary command mode and video mode encoders, execute the
  2634. * resource control pre-stop operations before the physical encoders
  2635. * are disabled, to allow the rsc to transition its states properly.
  2636. *
  2637. * For other encoder types, rsc should not be enabled until after
  2638. * they have been fully disabled, so delay the pre-stop operations
  2639. * until after the physical disable calls have returned.
  2640. */
  2641. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2642. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2643. sde_encoder_resource_control(drm_enc,
  2644. SDE_ENC_RC_EVENT_PRE_STOP);
  2645. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2646. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2647. if (phys && phys->ops.disable)
  2648. phys->ops.disable(phys);
  2649. }
  2650. } else {
  2651. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2652. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2653. if (phys && phys->ops.disable)
  2654. phys->ops.disable(phys);
  2655. }
  2656. sde_encoder_resource_control(drm_enc,
  2657. SDE_ENC_RC_EVENT_PRE_STOP);
  2658. }
  2659. /*
  2660. * disable dce after the transfer is complete (for command mode)
  2661. * and after physical encoder is disabled, to make sure timing
  2662. * engine is already disabled (for video mode).
  2663. */
  2664. if (!sde_in_trusted_vm(sde_kms))
  2665. sde_encoder_dce_disable(sde_enc);
  2666. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2667. /* reset connector topology name property */
  2668. if (sde_enc->cur_master && sde_enc->cur_master->connector &&
  2669. sde_enc->crtc && sde_enc->crtc->state->active_changed) {
  2670. ret = sde_rm_update_topology(&sde_kms->rm,
  2671. sde_enc->cur_master->connector->state, NULL);
  2672. if (ret) {
  2673. SDE_ERROR_ENC(sde_enc, "RM failed to update topology, rc: %d\n", ret);
  2674. return;
  2675. }
  2676. }
  2677. if (!sde_encoder_in_clone_mode(drm_enc))
  2678. sde_encoder_virt_reset(drm_enc);
  2679. }
  2680. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2681. struct sde_encoder_phys_wb *wb_enc)
  2682. {
  2683. struct sde_encoder_virt *sde_enc;
  2684. struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
  2685. struct sde_ctl_flush_cfg cfg;
  2686. struct sde_hw_dsc *hw_dsc = NULL;
  2687. int i;
  2688. ctl->ops.reset(ctl);
  2689. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2690. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2691. if (wb_enc) {
  2692. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2693. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2694. false, phys_enc->hw_pp->idx);
  2695. if (ctl->ops.update_bitmask)
  2696. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_WB,
  2697. wb_enc->hw_wb->idx, true);
  2698. }
  2699. } else {
  2700. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2701. if (sde_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2702. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2703. sde_enc->phys_encs[i]->hw_intf, false,
  2704. sde_enc->phys_encs[i]->hw_pp->idx);
  2705. if (ctl->ops.update_bitmask)
  2706. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF,
  2707. sde_enc->phys_encs[i]->hw_intf->idx, true);
  2708. }
  2709. }
  2710. }
  2711. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2712. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2713. if (ctl->ops.update_bitmask && phys_enc->hw_pp->merge_3d)
  2714. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,
  2715. phys_enc->hw_pp->merge_3d->idx, true);
  2716. }
  2717. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2718. phys_enc->hw_pp) {
  2719. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2720. false, phys_enc->hw_pp->idx);
  2721. if (ctl->ops.update_bitmask)
  2722. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_CDM,
  2723. phys_enc->hw_cdm->idx, true);
  2724. }
  2725. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2726. ctl->ops.reset_post_disable)
  2727. ctl->ops.reset_post_disable(ctl, &phys_enc->intf_cfg_v1,
  2728. phys_enc->hw_pp->merge_3d ?
  2729. phys_enc->hw_pp->merge_3d->idx : 0);
  2730. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2731. hw_dsc = sde_enc->hw_dsc[i];
  2732. if (hw_dsc && hw_dsc->ops.bind_pingpong_blk) {
  2733. hw_dsc->ops.bind_pingpong_blk(hw_dsc, false, PINGPONG_MAX);
  2734. if (ctl->ops.update_bitmask)
  2735. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_DSC, hw_dsc->idx, true);
  2736. }
  2737. }
  2738. sde_crtc_disable_cp_features(sde_enc->base.crtc);
  2739. ctl->ops.get_pending_flush(ctl, &cfg);
  2740. SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);
  2741. ctl->ops.trigger_flush(ctl);
  2742. ctl->ops.trigger_start(ctl);
  2743. ctl->ops.clear_pending_flush(ctl);
  2744. }
  2745. void sde_encoder_helper_phys_reset(struct sde_encoder_phys *phys_enc)
  2746. {
  2747. struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
  2748. struct sde_ctl_flush_cfg cfg;
  2749. ctl->ops.reset(ctl);
  2750. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2751. ctl->ops.get_pending_flush(ctl, &cfg);
  2752. SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);
  2753. ctl->ops.trigger_flush(ctl);
  2754. ctl->ops.trigger_start(ctl);
  2755. }
  2756. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2757. enum sde_intf_type type, u32 controller_id)
  2758. {
  2759. int i = 0;
  2760. for (i = 0; i < catalog->intf_count; i++) {
  2761. if (catalog->intf[i].type == type
  2762. && catalog->intf[i].controller_id == controller_id) {
  2763. return catalog->intf[i].id;
  2764. }
  2765. }
  2766. return INTF_MAX;
  2767. }
  2768. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2769. enum sde_intf_type type, u32 controller_id)
  2770. {
  2771. if (controller_id < catalog->wb_count)
  2772. return catalog->wb[controller_id].id;
  2773. return WB_MAX;
  2774. }
  2775. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2776. struct drm_crtc *crtc)
  2777. {
  2778. struct sde_hw_uidle *uidle;
  2779. struct sde_uidle_cntr cntr;
  2780. struct sde_uidle_status status;
  2781. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2782. pr_err("invalid params %d %d\n",
  2783. !sde_kms, !crtc);
  2784. return;
  2785. }
  2786. /* check if perf counters are enabled and setup */
  2787. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2788. return;
  2789. uidle = sde_kms->hw_uidle;
  2790. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2791. && uidle->ops.uidle_get_status) {
  2792. uidle->ops.uidle_get_status(uidle, &status);
  2793. trace_sde_perf_uidle_status(
  2794. crtc->base.id,
  2795. status.uidle_danger_status_0,
  2796. status.uidle_danger_status_1,
  2797. status.uidle_safe_status_0,
  2798. status.uidle_safe_status_1,
  2799. status.uidle_idle_status_0,
  2800. status.uidle_idle_status_1,
  2801. status.uidle_fal_status_0,
  2802. status.uidle_fal_status_1,
  2803. status.uidle_status,
  2804. status.uidle_en_fal10);
  2805. }
  2806. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2807. && uidle->ops.uidle_get_cntr) {
  2808. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2809. trace_sde_perf_uidle_cntr(
  2810. crtc->base.id,
  2811. cntr.fal1_gate_cntr,
  2812. cntr.fal10_gate_cntr,
  2813. cntr.fal_wait_gate_cntr,
  2814. cntr.fal1_num_transitions_cntr,
  2815. cntr.fal10_num_transitions_cntr,
  2816. cntr.min_gate_cntr,
  2817. cntr.max_gate_cntr);
  2818. }
  2819. }
  2820. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2821. struct sde_encoder_phys *phy_enc)
  2822. {
  2823. struct sde_encoder_virt *sde_enc = NULL;
  2824. unsigned long lock_flags;
  2825. ktime_t ts = 0;
  2826. if (!drm_enc || !phy_enc)
  2827. return;
  2828. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2829. sde_enc = to_sde_encoder_virt(drm_enc);
  2830. /*
  2831. * calculate accurate vsync timestamp when available
  2832. * set current time otherwise
  2833. */
  2834. if (phy_enc->sde_kms && phy_enc->sde_kms->catalog->has_precise_vsync_ts)
  2835. ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
  2836. if (!ts)
  2837. ts = ktime_get();
  2838. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2839. phy_enc->last_vsync_timestamp = ts;
  2840. atomic_inc(&phy_enc->vsync_cnt);
  2841. if (sde_enc->crtc_vblank_cb)
  2842. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data, ts);
  2843. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2844. if (phy_enc->sde_kms &&
  2845. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2846. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2847. SDE_ATRACE_END("encoder_vblank_callback");
  2848. }
  2849. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2850. struct sde_encoder_phys *phy_enc)
  2851. {
  2852. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2853. if (!phy_enc)
  2854. return;
  2855. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2856. atomic_inc(&phy_enc->underrun_cnt);
  2857. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2858. if (sde_enc->cur_master &&
  2859. sde_enc->cur_master->ops.get_underrun_line_count)
  2860. sde_enc->cur_master->ops.get_underrun_line_count(
  2861. sde_enc->cur_master);
  2862. trace_sde_encoder_underrun(DRMID(drm_enc),
  2863. atomic_read(&phy_enc->underrun_cnt));
  2864. if (phy_enc->sde_kms &&
  2865. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2866. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2867. SDE_DBG_CTRL("stop_ftrace");
  2868. SDE_DBG_CTRL("panic_underrun");
  2869. SDE_ATRACE_END("encoder_underrun_callback");
  2870. }
  2871. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2872. void (*vbl_cb)(void *, ktime_t), void *vbl_data)
  2873. {
  2874. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2875. unsigned long lock_flags;
  2876. bool enable;
  2877. int i;
  2878. enable = vbl_cb ? true : false;
  2879. if (!drm_enc) {
  2880. SDE_ERROR("invalid encoder\n");
  2881. return;
  2882. }
  2883. SDE_DEBUG_ENC(sde_enc, "\n");
  2884. SDE_EVT32(DRMID(drm_enc), enable);
  2885. if (sde_encoder_in_clone_mode(drm_enc)) {
  2886. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  2887. return;
  2888. }
  2889. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2890. sde_enc->crtc_vblank_cb = vbl_cb;
  2891. sde_enc->crtc_vblank_cb_data = vbl_data;
  2892. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2893. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2894. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2895. if (phys && phys->ops.control_vblank_irq)
  2896. phys->ops.control_vblank_irq(phys, enable);
  2897. }
  2898. sde_enc->vblank_enabled = enable;
  2899. }
  2900. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2901. void (*frame_event_cb)(void *, u32 event, ktime_t ts),
  2902. struct drm_crtc *crtc)
  2903. {
  2904. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2905. unsigned long lock_flags;
  2906. bool enable;
  2907. enable = frame_event_cb ? true : false;
  2908. if (!drm_enc) {
  2909. SDE_ERROR("invalid encoder\n");
  2910. return;
  2911. }
  2912. SDE_DEBUG_ENC(sde_enc, "\n");
  2913. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2914. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2915. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2916. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2917. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2918. }
  2919. static void sde_encoder_frame_done_callback(
  2920. struct drm_encoder *drm_enc,
  2921. struct sde_encoder_phys *ready_phys, u32 event)
  2922. {
  2923. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2924. struct sde_kms *sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2925. unsigned int i;
  2926. bool trigger = true;
  2927. bool is_cmd_mode = false;
  2928. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2929. ktime_t ts = 0;
  2930. if (!sde_kms || !sde_enc->cur_master) {
  2931. SDE_ERROR("invalid param: sde_kms %pK, cur_master %pK\n",
  2932. sde_kms, sde_enc->cur_master);
  2933. return;
  2934. }
  2935. sde_enc->crtc_frame_event_cb_data.connector =
  2936. sde_enc->cur_master->connector;
  2937. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2938. is_cmd_mode = true;
  2939. /* get precise vsync timestamp for retire fence, if precise vsync timestamp is enabled */
  2940. if (sde_kms->catalog->has_precise_vsync_ts
  2941. && (event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2942. && (!(event & (SDE_ENCODER_FRAME_EVENT_ERROR | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD))))
  2943. ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
  2944. /*
  2945. * get current ktime for other events and when precise timestamp is not
  2946. * available for retire-fence
  2947. */
  2948. if (!ts)
  2949. ts = ktime_get();
  2950. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2951. | SDE_ENCODER_FRAME_EVENT_ERROR
  2952. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2953. if (ready_phys->connector)
  2954. topology = sde_connector_get_topology_name(
  2955. ready_phys->connector);
  2956. /* One of the physical encoders has become idle */
  2957. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2958. if (sde_enc->phys_encs[i] == ready_phys) {
  2959. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2960. atomic_read(&sde_enc->frame_done_cnt[i]));
  2961. if (!atomic_add_unless(
  2962. &sde_enc->frame_done_cnt[i], 1, 2)) {
  2963. SDE_EVT32(DRMID(drm_enc), event,
  2964. ready_phys->intf_idx,
  2965. SDE_EVTLOG_ERROR);
  2966. SDE_ERROR_ENC(sde_enc,
  2967. "intf idx:%d, event:%d\n",
  2968. ready_phys->intf_idx, event);
  2969. return;
  2970. }
  2971. }
  2972. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2973. atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
  2974. trigger = false;
  2975. }
  2976. if (trigger) {
  2977. if (sde_enc->crtc_frame_event_cb)
  2978. sde_enc->crtc_frame_event_cb(
  2979. &sde_enc->crtc_frame_event_cb_data, event, ts);
  2980. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2981. atomic_add_unless(&sde_enc->frame_done_cnt[i],
  2982. -1, 0);
  2983. }
  2984. } else if (sde_enc->crtc_frame_event_cb) {
  2985. sde_enc->crtc_frame_event_cb(&sde_enc->crtc_frame_event_cb_data, event, ts);
  2986. }
  2987. }
  2988. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2989. {
  2990. struct sde_encoder_virt *sde_enc;
  2991. if (!drm_enc) {
  2992. SDE_ERROR("invalid drm encoder\n");
  2993. return -EINVAL;
  2994. }
  2995. sde_enc = to_sde_encoder_virt(drm_enc);
  2996. sde_encoder_resource_control(&sde_enc->base,
  2997. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2998. return 0;
  2999. }
  3000. /**
  3001. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  3002. * drm_enc: Pointer to drm encoder structure
  3003. * phys: Pointer to physical encoder structure
  3004. * extra_flush: Additional bit mask to include in flush trigger
  3005. * config_changed: if true new config is applied, avoid increment of retire
  3006. * count if false
  3007. */
  3008. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  3009. struct sde_encoder_phys *phys,
  3010. struct sde_ctl_flush_cfg *extra_flush,
  3011. bool config_changed)
  3012. {
  3013. struct sde_hw_ctl *ctl;
  3014. unsigned long lock_flags;
  3015. struct sde_encoder_virt *sde_enc;
  3016. int pend_ret_fence_cnt;
  3017. struct sde_connector *c_conn;
  3018. if (!drm_enc || !phys) {
  3019. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  3020. !drm_enc, !phys);
  3021. return;
  3022. }
  3023. sde_enc = to_sde_encoder_virt(drm_enc);
  3024. c_conn = to_sde_connector(phys->connector);
  3025. if (!phys->hw_pp) {
  3026. SDE_ERROR("invalid pingpong hw\n");
  3027. return;
  3028. }
  3029. ctl = phys->hw_ctl;
  3030. if (!ctl || !phys->ops.trigger_flush) {
  3031. SDE_ERROR("missing ctl/trigger cb\n");
  3032. return;
  3033. }
  3034. if (phys->split_role == ENC_ROLE_SKIP) {
  3035. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  3036. "skip flush pp%d ctl%d\n",
  3037. phys->hw_pp->idx - PINGPONG_0,
  3038. ctl->idx - CTL_0);
  3039. return;
  3040. }
  3041. /* update pending counts and trigger kickoff ctl flush atomically */
  3042. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  3043. if (phys->ops.is_master && phys->ops.is_master(phys) && config_changed)
  3044. atomic_inc(&phys->pending_retire_fence_cnt);
  3045. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  3046. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  3047. ctl->ops.update_bitmask) {
  3048. /* perform peripheral flush on every frame update for dp dsc */
  3049. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  3050. phys->comp_ratio && c_conn->ops.update_pps) {
  3051. c_conn->ops.update_pps(phys->connector, NULL,
  3052. c_conn->display);
  3053. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  3054. phys->hw_intf->idx, 1);
  3055. }
  3056. if (sde_enc->dynamic_hdr_updated)
  3057. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  3058. phys->hw_intf->idx, 1);
  3059. }
  3060. if ((extra_flush && extra_flush->pending_flush_mask)
  3061. && ctl->ops.update_pending_flush)
  3062. ctl->ops.update_pending_flush(ctl, extra_flush);
  3063. phys->ops.trigger_flush(phys);
  3064. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  3065. if (ctl->ops.get_pending_flush) {
  3066. struct sde_ctl_flush_cfg pending_flush = {0,};
  3067. ctl->ops.get_pending_flush(ctl, &pending_flush);
  3068. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  3069. ctl->idx - CTL_0,
  3070. pending_flush.pending_flush_mask,
  3071. pend_ret_fence_cnt);
  3072. } else {
  3073. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  3074. ctl->idx - CTL_0,
  3075. pend_ret_fence_cnt);
  3076. }
  3077. }
  3078. /**
  3079. * _sde_encoder_trigger_start - trigger start for a physical encoder
  3080. * phys: Pointer to physical encoder structure
  3081. */
  3082. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  3083. {
  3084. struct sde_hw_ctl *ctl;
  3085. struct sde_encoder_virt *sde_enc;
  3086. if (!phys) {
  3087. SDE_ERROR("invalid argument(s)\n");
  3088. return;
  3089. }
  3090. if (!phys->hw_pp) {
  3091. SDE_ERROR("invalid pingpong hw\n");
  3092. return;
  3093. }
  3094. if (!phys->parent) {
  3095. SDE_ERROR("invalid parent\n");
  3096. return;
  3097. }
  3098. /* avoid ctrl start for encoder in clone mode */
  3099. if (phys->in_clone_mode)
  3100. return;
  3101. ctl = phys->hw_ctl;
  3102. sde_enc = to_sde_encoder_virt(phys->parent);
  3103. if (phys->split_role == ENC_ROLE_SKIP) {
  3104. SDE_DEBUG_ENC(sde_enc,
  3105. "skip start pp%d ctl%d\n",
  3106. phys->hw_pp->idx - PINGPONG_0,
  3107. ctl->idx - CTL_0);
  3108. return;
  3109. }
  3110. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  3111. phys->ops.trigger_start(phys);
  3112. }
  3113. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  3114. {
  3115. struct sde_hw_ctl *ctl;
  3116. if (!phys_enc) {
  3117. SDE_ERROR("invalid encoder\n");
  3118. return;
  3119. }
  3120. ctl = phys_enc->hw_ctl;
  3121. if (ctl && ctl->ops.trigger_flush)
  3122. ctl->ops.trigger_flush(ctl);
  3123. }
  3124. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  3125. {
  3126. struct sde_hw_ctl *ctl;
  3127. if (!phys_enc) {
  3128. SDE_ERROR("invalid encoder\n");
  3129. return;
  3130. }
  3131. ctl = phys_enc->hw_ctl;
  3132. if (ctl && ctl->ops.trigger_start) {
  3133. ctl->ops.trigger_start(ctl);
  3134. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  3135. }
  3136. }
  3137. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  3138. {
  3139. struct sde_encoder_virt *sde_enc;
  3140. struct sde_connector *sde_con;
  3141. void *sde_con_disp;
  3142. struct sde_hw_ctl *ctl;
  3143. int rc;
  3144. if (!phys_enc) {
  3145. SDE_ERROR("invalid encoder\n");
  3146. return;
  3147. }
  3148. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  3149. ctl = phys_enc->hw_ctl;
  3150. if (!ctl || !ctl->ops.reset)
  3151. return;
  3152. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  3153. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  3154. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  3155. phys_enc->connector) {
  3156. sde_con = to_sde_connector(phys_enc->connector);
  3157. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  3158. if (sde_con->ops.soft_reset) {
  3159. rc = sde_con->ops.soft_reset(sde_con_disp);
  3160. if (rc) {
  3161. SDE_ERROR_ENC(sde_enc,
  3162. "connector soft reset failure\n");
  3163. SDE_DBG_DUMP(SDE_DBG_BUILT_IN_ALL, "panic");
  3164. }
  3165. }
  3166. }
  3167. phys_enc->enable_state = SDE_ENC_ENABLED;
  3168. }
  3169. /**
  3170. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  3171. * Iterate through the physical encoders and perform consolidated flush
  3172. * and/or control start triggering as needed. This is done in the virtual
  3173. * encoder rather than the individual physical ones in order to handle
  3174. * use cases that require visibility into multiple physical encoders at
  3175. * a time.
  3176. * sde_enc: Pointer to virtual encoder structure
  3177. * config_changed: if true new config is applied. Avoid regdma_flush and
  3178. * incrementing the retire count if false.
  3179. */
  3180. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc,
  3181. bool config_changed)
  3182. {
  3183. struct sde_hw_ctl *ctl;
  3184. uint32_t i;
  3185. struct sde_ctl_flush_cfg pending_flush = {0,};
  3186. u32 pending_kickoff_cnt;
  3187. struct msm_drm_private *priv = NULL;
  3188. struct sde_kms *sde_kms = NULL;
  3189. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  3190. bool is_regdma_blocking = false, is_vid_mode = false;
  3191. struct sde_crtc *sde_crtc;
  3192. if (!sde_enc) {
  3193. SDE_ERROR("invalid encoder\n");
  3194. return;
  3195. }
  3196. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3197. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  3198. is_vid_mode = true;
  3199. is_regdma_blocking = (is_vid_mode ||
  3200. _sde_encoder_is_autorefresh_enabled(sde_enc));
  3201. /* don't perform flush/start operations for slave encoders */
  3202. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3203. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3204. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  3205. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3206. continue;
  3207. ctl = phys->hw_ctl;
  3208. if (!ctl)
  3209. continue;
  3210. if (phys->connector)
  3211. topology = sde_connector_get_topology_name(
  3212. phys->connector);
  3213. if (!phys->ops.needs_single_flush ||
  3214. !phys->ops.needs_single_flush(phys)) {
  3215. if (config_changed && ctl->ops.reg_dma_flush)
  3216. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  3217. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0,
  3218. config_changed);
  3219. } else if (ctl->ops.get_pending_flush) {
  3220. ctl->ops.get_pending_flush(ctl, &pending_flush);
  3221. }
  3222. }
  3223. /* for split flush, combine pending flush masks and send to master */
  3224. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  3225. ctl = sde_enc->cur_master->hw_ctl;
  3226. if (config_changed && ctl->ops.reg_dma_flush)
  3227. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  3228. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  3229. &pending_flush,
  3230. config_changed);
  3231. }
  3232. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  3233. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3234. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3235. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3236. continue;
  3237. if (!phys->ops.needs_single_flush ||
  3238. !phys->ops.needs_single_flush(phys)) {
  3239. pending_kickoff_cnt =
  3240. sde_encoder_phys_inc_pending(phys);
  3241. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  3242. } else {
  3243. pending_kickoff_cnt =
  3244. sde_encoder_phys_inc_pending(phys);
  3245. SDE_EVT32(pending_kickoff_cnt,
  3246. pending_flush.pending_flush_mask,
  3247. SDE_EVTLOG_FUNC_CASE2);
  3248. }
  3249. }
  3250. if (sde_enc->misr_enable)
  3251. sde_encoder_misr_configure(&sde_enc->base, true,
  3252. sde_enc->misr_frame_count);
  3253. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  3254. if (crtc_misr_info.misr_enable && sde_crtc &&
  3255. sde_crtc->misr_reconfigure) {
  3256. sde_crtc_misr_setup(sde_enc->crtc, true,
  3257. crtc_misr_info.misr_frame_count);
  3258. sde_crtc->misr_reconfigure = false;
  3259. }
  3260. _sde_encoder_trigger_start(sde_enc->cur_master);
  3261. if (sde_enc->elevated_ahb_vote) {
  3262. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3263. priv = sde_enc->base.dev->dev_private;
  3264. if (sde_kms != NULL) {
  3265. sde_power_scale_reg_bus(&priv->phandle,
  3266. VOTE_INDEX_LOW,
  3267. false);
  3268. }
  3269. sde_enc->elevated_ahb_vote = false;
  3270. }
  3271. }
  3272. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  3273. struct drm_encoder *drm_enc,
  3274. unsigned long *affected_displays,
  3275. int num_active_phys)
  3276. {
  3277. struct sde_encoder_virt *sde_enc;
  3278. struct sde_encoder_phys *master;
  3279. enum sde_rm_topology_name topology;
  3280. bool is_right_only;
  3281. if (!drm_enc || !affected_displays)
  3282. return;
  3283. sde_enc = to_sde_encoder_virt(drm_enc);
  3284. master = sde_enc->cur_master;
  3285. if (!master || !master->connector)
  3286. return;
  3287. topology = sde_connector_get_topology_name(master->connector);
  3288. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  3289. return;
  3290. /*
  3291. * For pingpong split, the slave pingpong won't generate IRQs. For
  3292. * right-only updates, we can't swap pingpongs, or simply swap the
  3293. * master/slave assignment, we actually have to swap the interfaces
  3294. * so that the master physical encoder will use a pingpong/interface
  3295. * that generates irqs on which to wait.
  3296. */
  3297. is_right_only = !test_bit(0, affected_displays) &&
  3298. test_bit(1, affected_displays);
  3299. if (is_right_only && !sde_enc->intfs_swapped) {
  3300. /* right-only update swap interfaces */
  3301. swap(sde_enc->phys_encs[0]->intf_idx,
  3302. sde_enc->phys_encs[1]->intf_idx);
  3303. sde_enc->intfs_swapped = true;
  3304. } else if (!is_right_only && sde_enc->intfs_swapped) {
  3305. /* left-only or full update, swap back */
  3306. swap(sde_enc->phys_encs[0]->intf_idx,
  3307. sde_enc->phys_encs[1]->intf_idx);
  3308. sde_enc->intfs_swapped = false;
  3309. }
  3310. SDE_DEBUG_ENC(sde_enc,
  3311. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  3312. is_right_only, sde_enc->intfs_swapped,
  3313. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3314. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  3315. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  3316. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3317. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  3318. *affected_displays);
  3319. /* ppsplit always uses master since ppslave invalid for irqs*/
  3320. if (num_active_phys == 1)
  3321. *affected_displays = BIT(0);
  3322. }
  3323. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  3324. struct sde_encoder_kickoff_params *params)
  3325. {
  3326. struct sde_encoder_virt *sde_enc;
  3327. struct sde_encoder_phys *phys;
  3328. int i, num_active_phys;
  3329. bool master_assigned = false;
  3330. if (!drm_enc || !params)
  3331. return;
  3332. sde_enc = to_sde_encoder_virt(drm_enc);
  3333. if (sde_enc->num_phys_encs <= 1)
  3334. return;
  3335. /* count bits set */
  3336. num_active_phys = hweight_long(params->affected_displays);
  3337. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  3338. params->affected_displays, num_active_phys);
  3339. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  3340. num_active_phys);
  3341. /* for left/right only update, ppsplit master switches interface */
  3342. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  3343. &params->affected_displays, num_active_phys);
  3344. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3345. enum sde_enc_split_role prv_role, new_role;
  3346. bool active = false;
  3347. phys = sde_enc->phys_encs[i];
  3348. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  3349. continue;
  3350. active = test_bit(i, &params->affected_displays);
  3351. prv_role = phys->split_role;
  3352. if (active && num_active_phys == 1)
  3353. new_role = ENC_ROLE_SOLO;
  3354. else if (active && !master_assigned)
  3355. new_role = ENC_ROLE_MASTER;
  3356. else if (active)
  3357. new_role = ENC_ROLE_SLAVE;
  3358. else
  3359. new_role = ENC_ROLE_SKIP;
  3360. phys->ops.update_split_role(phys, new_role);
  3361. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  3362. sde_enc->cur_master = phys;
  3363. master_assigned = true;
  3364. }
  3365. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  3366. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3367. phys->split_role, active);
  3368. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  3369. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3370. phys->split_role, active, num_active_phys);
  3371. }
  3372. }
  3373. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  3374. {
  3375. struct sde_encoder_virt *sde_enc;
  3376. struct msm_display_info *disp_info;
  3377. if (!drm_enc) {
  3378. SDE_ERROR("invalid encoder\n");
  3379. return false;
  3380. }
  3381. sde_enc = to_sde_encoder_virt(drm_enc);
  3382. disp_info = &sde_enc->disp_info;
  3383. return (disp_info->curr_panel_mode == mode);
  3384. }
  3385. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3386. {
  3387. struct sde_encoder_virt *sde_enc;
  3388. struct sde_encoder_phys *phys;
  3389. unsigned int i;
  3390. struct sde_hw_ctl *ctl;
  3391. if (!drm_enc) {
  3392. SDE_ERROR("invalid encoder\n");
  3393. return;
  3394. }
  3395. sde_enc = to_sde_encoder_virt(drm_enc);
  3396. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3397. phys = sde_enc->phys_encs[i];
  3398. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3399. sde_encoder_check_curr_mode(drm_enc,
  3400. MSM_DISPLAY_CMD_MODE)) {
  3401. ctl = phys->hw_ctl;
  3402. if (ctl->ops.trigger_pending)
  3403. /* update only for command mode primary ctl */
  3404. ctl->ops.trigger_pending(ctl);
  3405. }
  3406. }
  3407. sde_enc->idle_pc_restore = false;
  3408. }
  3409. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3410. {
  3411. struct sde_encoder_virt *sde_enc = container_of(work,
  3412. struct sde_encoder_virt, esd_trigger_work);
  3413. if (!sde_enc) {
  3414. SDE_ERROR("invalid sde encoder\n");
  3415. return;
  3416. }
  3417. sde_encoder_resource_control(&sde_enc->base,
  3418. SDE_ENC_RC_EVENT_KICKOFF);
  3419. }
  3420. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3421. {
  3422. struct sde_encoder_virt *sde_enc = container_of(work,
  3423. struct sde_encoder_virt, input_event_work);
  3424. if (!sde_enc) {
  3425. SDE_ERROR("invalid sde encoder\n");
  3426. return;
  3427. }
  3428. sde_encoder_resource_control(&sde_enc->base,
  3429. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3430. }
  3431. static void sde_encoder_early_wakeup_work_handler(struct kthread_work *work)
  3432. {
  3433. struct sde_encoder_virt *sde_enc = container_of(work,
  3434. struct sde_encoder_virt, early_wakeup_work);
  3435. struct sde_kms *sde_kms = to_sde_kms(ddev_to_msm_kms(sde_enc->base.dev));
  3436. sde_vm_lock(sde_kms);
  3437. if (!sde_vm_owns_hw(sde_kms)) {
  3438. sde_vm_unlock(sde_kms);
  3439. SDE_DEBUG("skip early wakeup for ENC-%d, HW is owned by other VM\n",
  3440. DRMID(&sde_enc->base));
  3441. return;
  3442. }
  3443. SDE_ATRACE_BEGIN("encoder_early_wakeup");
  3444. sde_encoder_resource_control(&sde_enc->base,
  3445. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3446. SDE_ATRACE_END("encoder_early_wakeup");
  3447. sde_vm_unlock(sde_kms);
  3448. }
  3449. void sde_encoder_early_wakeup(struct drm_encoder *drm_enc)
  3450. {
  3451. struct sde_encoder_virt *sde_enc = NULL;
  3452. struct msm_drm_thread *disp_thread = NULL;
  3453. struct msm_drm_private *priv = NULL;
  3454. priv = drm_enc->dev->dev_private;
  3455. sde_enc = to_sde_encoder_virt(drm_enc);
  3456. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)) {
  3457. SDE_DEBUG_ENC(sde_enc,
  3458. "should only early wake up command mode display\n");
  3459. return;
  3460. }
  3461. if (!sde_enc->crtc || (sde_enc->crtc->index
  3462. >= ARRAY_SIZE(priv->event_thread))) {
  3463. SDE_DEBUG_ENC(sde_enc, "invalid CRTC: %d or crtc index: %d\n",
  3464. sde_enc->crtc == NULL,
  3465. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  3466. return;
  3467. }
  3468. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  3469. SDE_ATRACE_BEGIN("queue_early_wakeup_work");
  3470. kthread_queue_work(&disp_thread->worker,
  3471. &sde_enc->early_wakeup_work);
  3472. SDE_ATRACE_END("queue_early_wakeup_work");
  3473. }
  3474. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3475. {
  3476. static const uint64_t timeout_us = 50000;
  3477. static const uint64_t sleep_us = 20;
  3478. struct sde_encoder_virt *sde_enc;
  3479. ktime_t cur_ktime, exp_ktime;
  3480. uint32_t line_count, tmp, i;
  3481. if (!drm_enc) {
  3482. SDE_ERROR("invalid encoder\n");
  3483. return -EINVAL;
  3484. }
  3485. sde_enc = to_sde_encoder_virt(drm_enc);
  3486. if (!sde_enc->cur_master ||
  3487. !sde_enc->cur_master->ops.get_line_count) {
  3488. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3489. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3490. return -EINVAL;
  3491. }
  3492. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3493. line_count = sde_enc->cur_master->ops.get_line_count(
  3494. sde_enc->cur_master);
  3495. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3496. tmp = line_count;
  3497. line_count = sde_enc->cur_master->ops.get_line_count(
  3498. sde_enc->cur_master);
  3499. if (line_count < tmp) {
  3500. SDE_EVT32(DRMID(drm_enc), line_count);
  3501. return 0;
  3502. }
  3503. cur_ktime = ktime_get();
  3504. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3505. break;
  3506. usleep_range(sleep_us / 2, sleep_us);
  3507. }
  3508. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3509. return -ETIMEDOUT;
  3510. }
  3511. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3512. {
  3513. struct drm_encoder *drm_enc;
  3514. struct sde_rm_hw_iter rm_iter;
  3515. bool lm_valid = false;
  3516. bool intf_valid = false;
  3517. if (!phys_enc || !phys_enc->parent) {
  3518. SDE_ERROR("invalid encoder\n");
  3519. return -EINVAL;
  3520. }
  3521. drm_enc = phys_enc->parent;
  3522. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3523. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3524. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3525. phys_enc->has_intf_te)) {
  3526. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3527. SDE_HW_BLK_INTF);
  3528. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3529. struct sde_hw_intf *hw_intf =
  3530. (struct sde_hw_intf *)rm_iter.hw;
  3531. if (!hw_intf)
  3532. continue;
  3533. if (phys_enc->hw_ctl->ops.update_bitmask)
  3534. phys_enc->hw_ctl->ops.update_bitmask(
  3535. phys_enc->hw_ctl,
  3536. SDE_HW_FLUSH_INTF,
  3537. hw_intf->idx, 1);
  3538. intf_valid = true;
  3539. }
  3540. if (!intf_valid) {
  3541. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3542. "intf not found to flush\n");
  3543. return -EFAULT;
  3544. }
  3545. } else {
  3546. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3547. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3548. struct sde_hw_mixer *hw_lm =
  3549. (struct sde_hw_mixer *)rm_iter.hw;
  3550. if (!hw_lm)
  3551. continue;
  3552. /* update LM flush for HW without INTF TE */
  3553. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3554. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3555. phys_enc->hw_ctl,
  3556. hw_lm->idx, 1);
  3557. lm_valid = true;
  3558. }
  3559. if (!lm_valid) {
  3560. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3561. "lm not found to flush\n");
  3562. return -EFAULT;
  3563. }
  3564. }
  3565. return 0;
  3566. }
  3567. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3568. struct sde_encoder_virt *sde_enc)
  3569. {
  3570. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3571. struct sde_hw_mdp *mdptop = NULL;
  3572. sde_enc->dynamic_hdr_updated = false;
  3573. if (sde_enc->cur_master) {
  3574. mdptop = sde_enc->cur_master->hw_mdptop;
  3575. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3576. sde_enc->cur_master->connector);
  3577. }
  3578. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3579. return;
  3580. if (mdptop->ops.set_hdr_plus_metadata) {
  3581. sde_enc->dynamic_hdr_updated = true;
  3582. mdptop->ops.set_hdr_plus_metadata(
  3583. mdptop, dhdr_meta->dynamic_hdr_payload,
  3584. dhdr_meta->dynamic_hdr_payload_size,
  3585. sde_enc->cur_master->intf_idx == INTF_0 ?
  3586. 0 : 1);
  3587. }
  3588. }
  3589. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3590. {
  3591. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3592. struct sde_encoder_phys *phys;
  3593. int i;
  3594. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3595. phys = sde_enc->phys_encs[i];
  3596. if (phys && phys->ops.hw_reset)
  3597. phys->ops.hw_reset(phys);
  3598. }
  3599. }
  3600. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3601. struct sde_encoder_kickoff_params *params)
  3602. {
  3603. struct sde_encoder_virt *sde_enc;
  3604. struct sde_encoder_phys *phys;
  3605. struct sde_kms *sde_kms = NULL;
  3606. struct sde_crtc *sde_crtc;
  3607. bool needs_hw_reset = false, is_cmd_mode;
  3608. int i, rc, ret = 0;
  3609. struct msm_display_info *disp_info;
  3610. if (!drm_enc || !params || !drm_enc->dev ||
  3611. !drm_enc->dev->dev_private) {
  3612. SDE_ERROR("invalid args\n");
  3613. return -EINVAL;
  3614. }
  3615. sde_enc = to_sde_encoder_virt(drm_enc);
  3616. sde_kms = sde_encoder_get_kms(drm_enc);
  3617. if (!sde_kms)
  3618. return -EINVAL;
  3619. disp_info = &sde_enc->disp_info;
  3620. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3621. SDE_DEBUG_ENC(sde_enc, "\n");
  3622. SDE_EVT32(DRMID(drm_enc));
  3623. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3624. MSM_DISPLAY_CMD_MODE);
  3625. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3626. && is_cmd_mode)
  3627. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3628. sde_enc->cur_master->connector->state,
  3629. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3630. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3631. /* prepare for next kickoff, may include waiting on previous kickoff */
  3632. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3633. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3634. phys = sde_enc->phys_encs[i];
  3635. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3636. params->recovery_events_enabled =
  3637. sde_enc->recovery_events_enabled;
  3638. if (phys) {
  3639. if (phys->ops.prepare_for_kickoff) {
  3640. rc = phys->ops.prepare_for_kickoff(
  3641. phys, params);
  3642. if (rc)
  3643. ret = rc;
  3644. }
  3645. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3646. needs_hw_reset = true;
  3647. _sde_encoder_setup_dither(phys);
  3648. if (sde_enc->cur_master &&
  3649. sde_connector_is_qsync_updated(
  3650. sde_enc->cur_master->connector))
  3651. _helper_flush_qsync(phys);
  3652. }
  3653. }
  3654. if (is_cmd_mode && sde_enc->cur_master &&
  3655. (sde_connector_is_qsync_updated(sde_enc->cur_master->connector) ||
  3656. _sde_encoder_is_autorefresh_enabled(sde_enc)))
  3657. _sde_encoder_update_rsc_client(drm_enc, true);
  3658. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3659. if (rc) {
  3660. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3661. ret = rc;
  3662. goto end;
  3663. }
  3664. /* if any phys needs reset, reset all phys, in-order */
  3665. if (needs_hw_reset)
  3666. sde_encoder_needs_hw_reset(drm_enc);
  3667. _sde_encoder_update_master(drm_enc, params);
  3668. _sde_encoder_update_roi(drm_enc);
  3669. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3670. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3671. if (rc) {
  3672. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3673. sde_enc->cur_master->connector->base.id,
  3674. rc);
  3675. ret = rc;
  3676. }
  3677. }
  3678. if (sde_enc->cur_master &&
  3679. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3680. !sde_enc->cur_master->cont_splash_enabled)) {
  3681. rc = sde_encoder_dce_setup(sde_enc, params);
  3682. if (rc) {
  3683. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3684. ret = rc;
  3685. }
  3686. }
  3687. sde_encoder_dce_flush(sde_enc);
  3688. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3689. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3690. sde_enc->cur_master, sde_kms->qdss_enabled);
  3691. end:
  3692. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3693. return ret;
  3694. }
  3695. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool config_changed)
  3696. {
  3697. struct sde_encoder_virt *sde_enc;
  3698. struct sde_encoder_phys *phys;
  3699. unsigned int i;
  3700. if (!drm_enc) {
  3701. SDE_ERROR("invalid encoder\n");
  3702. return;
  3703. }
  3704. SDE_ATRACE_BEGIN("encoder_kickoff");
  3705. sde_enc = to_sde_encoder_virt(drm_enc);
  3706. SDE_DEBUG_ENC(sde_enc, "\n");
  3707. if (sde_enc->delay_kickoff) {
  3708. u32 loop_count = 20;
  3709. u32 sleep = DELAY_KICKOFF_POLL_TIMEOUT_US / loop_count;
  3710. for (i = 0; i < loop_count; i++) {
  3711. usleep_range(sleep, sleep * 2);
  3712. if (!sde_enc->delay_kickoff)
  3713. break;
  3714. }
  3715. SDE_EVT32(DRMID(drm_enc), i, SDE_EVTLOG_FUNC_CASE1);
  3716. }
  3717. /* All phys encs are ready to go, trigger the kickoff */
  3718. _sde_encoder_kickoff_phys(sde_enc, config_changed);
  3719. /* allow phys encs to handle any post-kickoff business */
  3720. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3721. phys = sde_enc->phys_encs[i];
  3722. if (phys && phys->ops.handle_post_kickoff)
  3723. phys->ops.handle_post_kickoff(phys);
  3724. }
  3725. if (sde_enc->autorefresh_solver_disable &&
  3726. !_sde_encoder_is_autorefresh_enabled(sde_enc))
  3727. _sde_encoder_update_rsc_client(drm_enc, true);
  3728. SDE_ATRACE_END("encoder_kickoff");
  3729. }
  3730. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3731. struct sde_hw_pp_vsync_info *info)
  3732. {
  3733. struct sde_encoder_virt *sde_enc;
  3734. struct sde_encoder_phys *phys;
  3735. int i, ret;
  3736. if (!drm_enc || !info)
  3737. return;
  3738. sde_enc = to_sde_encoder_virt(drm_enc);
  3739. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3740. phys = sde_enc->phys_encs[i];
  3741. if (phys && phys->hw_intf && phys->hw_pp
  3742. && phys->hw_intf->ops.get_vsync_info) {
  3743. ret = phys->hw_intf->ops.get_vsync_info(
  3744. phys->hw_intf, &info[i]);
  3745. if (!ret) {
  3746. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3747. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3748. }
  3749. }
  3750. }
  3751. }
  3752. void sde_encoder_get_transfer_time(struct drm_encoder *drm_enc,
  3753. u32 *transfer_time_us)
  3754. {
  3755. struct sde_encoder_virt *sde_enc;
  3756. struct msm_mode_info *info;
  3757. if (!drm_enc || !transfer_time_us) {
  3758. SDE_ERROR("bad arg: encoder:%d transfer_time:%d\n", !drm_enc,
  3759. !transfer_time_us);
  3760. return;
  3761. }
  3762. sde_enc = to_sde_encoder_virt(drm_enc);
  3763. info = &sde_enc->mode_info;
  3764. *transfer_time_us = info->mdp_transfer_time_us;
  3765. }
  3766. u32 sde_encoder_helper_get_kickoff_timeout_ms(struct drm_encoder *drm_enc)
  3767. {
  3768. struct drm_encoder *src_enc = drm_enc;
  3769. struct sde_encoder_virt *sde_enc;
  3770. u32 fps;
  3771. if (!drm_enc) {
  3772. SDE_ERROR("invalid encoder\n");
  3773. return DEFAULT_KICKOFF_TIMEOUT_MS;
  3774. }
  3775. if (sde_encoder_in_clone_mode(drm_enc))
  3776. src_enc = sde_crtc_get_src_encoder_of_clone(drm_enc->crtc);
  3777. if (!src_enc)
  3778. return DEFAULT_KICKOFF_TIMEOUT_MS;
  3779. sde_enc = to_sde_encoder_virt(src_enc);
  3780. fps = sde_enc->mode_info.frame_rate;
  3781. if (!fps || fps >= DEFAULT_TIMEOUT_FPS_THRESHOLD)
  3782. return DEFAULT_KICKOFF_TIMEOUT_MS;
  3783. else
  3784. return (SEC_TO_MILLI_SEC / fps) * 2;
  3785. }
  3786. int sde_encoder_get_avr_status(struct drm_encoder *drm_enc)
  3787. {
  3788. struct sde_encoder_virt *sde_enc;
  3789. struct sde_encoder_phys *master;
  3790. bool is_vid_mode;
  3791. if (!drm_enc)
  3792. return -EINVAL;
  3793. sde_enc = to_sde_encoder_virt(drm_enc);
  3794. master = sde_enc->cur_master;
  3795. is_vid_mode = sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CAP_VID_MODE);
  3796. if (!master || !is_vid_mode || !sde_connector_get_qsync_mode(master->connector))
  3797. return -ENODATA;
  3798. if (!master->hw_intf->ops.get_avr_status)
  3799. return -EOPNOTSUPP;
  3800. return master->hw_intf->ops.get_avr_status(master->hw_intf);
  3801. }
  3802. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3803. struct drm_framebuffer *fb)
  3804. {
  3805. struct drm_encoder *drm_enc;
  3806. struct sde_hw_mixer_cfg mixer;
  3807. struct sde_rm_hw_iter lm_iter;
  3808. bool lm_valid = false;
  3809. if (!phys_enc || !phys_enc->parent) {
  3810. SDE_ERROR("invalid encoder\n");
  3811. return -EINVAL;
  3812. }
  3813. drm_enc = phys_enc->parent;
  3814. memset(&mixer, 0, sizeof(mixer));
  3815. /* reset associated CTL/LMs */
  3816. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3817. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3818. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3819. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3820. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3821. if (!hw_lm)
  3822. continue;
  3823. /* need to flush LM to remove it */
  3824. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3825. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3826. phys_enc->hw_ctl,
  3827. hw_lm->idx, 1);
  3828. if (fb) {
  3829. /* assume a single LM if targeting a frame buffer */
  3830. if (lm_valid)
  3831. continue;
  3832. mixer.out_height = fb->height;
  3833. mixer.out_width = fb->width;
  3834. if (hw_lm->ops.setup_mixer_out)
  3835. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3836. }
  3837. lm_valid = true;
  3838. /* only enable border color on LM */
  3839. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3840. phys_enc->hw_ctl->ops.setup_blendstage(
  3841. phys_enc->hw_ctl, hw_lm->idx, NULL, false);
  3842. }
  3843. if (!lm_valid) {
  3844. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3845. return -EFAULT;
  3846. }
  3847. return 0;
  3848. }
  3849. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3850. {
  3851. struct sde_encoder_virt *sde_enc;
  3852. struct sde_encoder_phys *phys;
  3853. int i, rc = 0, ret = 0;
  3854. struct sde_hw_ctl *ctl;
  3855. if (!drm_enc) {
  3856. SDE_ERROR("invalid encoder\n");
  3857. return -EINVAL;
  3858. }
  3859. sde_enc = to_sde_encoder_virt(drm_enc);
  3860. /* update the qsync parameters for the current frame */
  3861. if (sde_enc->cur_master)
  3862. sde_connector_set_qsync_params(
  3863. sde_enc->cur_master->connector);
  3864. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3865. phys = sde_enc->phys_encs[i];
  3866. if (phys && phys->ops.prepare_commit)
  3867. phys->ops.prepare_commit(phys);
  3868. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3869. ret = -ETIMEDOUT;
  3870. if (phys && phys->hw_ctl) {
  3871. ctl = phys->hw_ctl;
  3872. /*
  3873. * avoid clearing the pending flush during the first
  3874. * frame update after idle power collpase as the
  3875. * restore path would have updated the pending flush
  3876. */
  3877. if (!sde_enc->idle_pc_restore &&
  3878. ctl->ops.clear_pending_flush)
  3879. ctl->ops.clear_pending_flush(ctl);
  3880. }
  3881. }
  3882. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3883. rc = sde_connector_prepare_commit(
  3884. sde_enc->cur_master->connector);
  3885. if (rc)
  3886. SDE_ERROR_ENC(sde_enc,
  3887. "prepare commit failed conn %d rc %d\n",
  3888. sde_enc->cur_master->connector->base.id,
  3889. rc);
  3890. }
  3891. return ret;
  3892. }
  3893. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3894. bool enable, u32 frame_count)
  3895. {
  3896. if (!phys_enc)
  3897. return;
  3898. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3899. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3900. enable, frame_count);
  3901. }
  3902. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3903. bool nonblock, u32 *misr_value)
  3904. {
  3905. if (!phys_enc)
  3906. return -EINVAL;
  3907. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3908. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3909. nonblock, misr_value) : -ENOTSUPP;
  3910. }
  3911. #ifdef CONFIG_DEBUG_FS
  3912. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3913. {
  3914. struct sde_encoder_virt *sde_enc;
  3915. int i;
  3916. if (!s || !s->private)
  3917. return -EINVAL;
  3918. sde_enc = s->private;
  3919. mutex_lock(&sde_enc->enc_lock);
  3920. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3921. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3922. if (!phys)
  3923. continue;
  3924. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3925. phys->intf_idx - INTF_0,
  3926. atomic_read(&phys->vsync_cnt),
  3927. atomic_read(&phys->underrun_cnt));
  3928. switch (phys->intf_mode) {
  3929. case INTF_MODE_VIDEO:
  3930. seq_puts(s, "mode: video\n");
  3931. break;
  3932. case INTF_MODE_CMD:
  3933. seq_puts(s, "mode: command\n");
  3934. break;
  3935. case INTF_MODE_WB_BLOCK:
  3936. seq_puts(s, "mode: wb block\n");
  3937. break;
  3938. case INTF_MODE_WB_LINE:
  3939. seq_puts(s, "mode: wb line\n");
  3940. break;
  3941. default:
  3942. seq_puts(s, "mode: ???\n");
  3943. break;
  3944. }
  3945. }
  3946. mutex_unlock(&sde_enc->enc_lock);
  3947. return 0;
  3948. }
  3949. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3950. struct file *file)
  3951. {
  3952. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3953. }
  3954. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3955. const char __user *user_buf, size_t count, loff_t *ppos)
  3956. {
  3957. struct sde_encoder_virt *sde_enc;
  3958. char buf[MISR_BUFF_SIZE + 1];
  3959. size_t buff_copy;
  3960. u32 frame_count, enable;
  3961. struct sde_kms *sde_kms = NULL;
  3962. struct drm_encoder *drm_enc;
  3963. if (!file || !file->private_data)
  3964. return -EINVAL;
  3965. sde_enc = file->private_data;
  3966. if (!sde_enc)
  3967. return -EINVAL;
  3968. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3969. if (!sde_kms)
  3970. return -EINVAL;
  3971. drm_enc = &sde_enc->base;
  3972. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3973. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3974. return -ENOTSUPP;
  3975. }
  3976. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3977. if (copy_from_user(buf, user_buf, buff_copy))
  3978. return -EINVAL;
  3979. buf[buff_copy] = 0; /* end of string */
  3980. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3981. return -EINVAL;
  3982. sde_enc->misr_enable = enable;
  3983. sde_enc->misr_reconfigure = true;
  3984. sde_enc->misr_frame_count = frame_count;
  3985. return count;
  3986. }
  3987. static ssize_t _sde_encoder_misr_read(struct file *file,
  3988. char __user *user_buff, size_t count, loff_t *ppos)
  3989. {
  3990. struct sde_encoder_virt *sde_enc;
  3991. struct sde_kms *sde_kms = NULL;
  3992. struct drm_encoder *drm_enc;
  3993. int i = 0, len = 0;
  3994. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3995. int rc;
  3996. if (*ppos)
  3997. return 0;
  3998. if (!file || !file->private_data)
  3999. return -EINVAL;
  4000. sde_enc = file->private_data;
  4001. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4002. if (!sde_kms)
  4003. return -EINVAL;
  4004. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4005. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  4006. return -ENOTSUPP;
  4007. }
  4008. drm_enc = &sde_enc->base;
  4009. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  4010. if (rc < 0)
  4011. return rc;
  4012. sde_vm_lock(sde_kms);
  4013. if (!sde_vm_owns_hw(sde_kms)) {
  4014. SDE_DEBUG("op not supported due to HW unavailablity\n");
  4015. rc = -EOPNOTSUPP;
  4016. goto end;
  4017. }
  4018. if (!sde_enc->misr_enable) {
  4019. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4020. "disabled\n");
  4021. goto buff_check;
  4022. }
  4023. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4024. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4025. u32 misr_value = 0;
  4026. if (!phys || !phys->ops.collect_misr) {
  4027. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4028. "invalid\n");
  4029. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  4030. continue;
  4031. }
  4032. rc = phys->ops.collect_misr(phys, false, &misr_value);
  4033. if (rc) {
  4034. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4035. "invalid\n");
  4036. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  4037. rc);
  4038. continue;
  4039. } else {
  4040. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4041. "Intf idx:%d\n",
  4042. phys->intf_idx - INTF_0);
  4043. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4044. "0x%x\n", misr_value);
  4045. }
  4046. }
  4047. buff_check:
  4048. if (count <= len) {
  4049. len = 0;
  4050. goto end;
  4051. }
  4052. if (copy_to_user(user_buff, buf, len)) {
  4053. len = -EFAULT;
  4054. goto end;
  4055. }
  4056. *ppos += len; /* increase offset */
  4057. end:
  4058. sde_vm_unlock(sde_kms);
  4059. pm_runtime_put_sync(drm_enc->dev->dev);
  4060. return len;
  4061. }
  4062. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  4063. {
  4064. struct sde_encoder_virt *sde_enc;
  4065. struct sde_kms *sde_kms;
  4066. int i;
  4067. static const struct file_operations debugfs_status_fops = {
  4068. .open = _sde_encoder_debugfs_status_open,
  4069. .read = seq_read,
  4070. .llseek = seq_lseek,
  4071. .release = single_release,
  4072. };
  4073. static const struct file_operations debugfs_misr_fops = {
  4074. .open = simple_open,
  4075. .read = _sde_encoder_misr_read,
  4076. .write = _sde_encoder_misr_setup,
  4077. };
  4078. char name[SDE_NAME_SIZE];
  4079. if (!drm_enc) {
  4080. SDE_ERROR("invalid encoder\n");
  4081. return -EINVAL;
  4082. }
  4083. sde_enc = to_sde_encoder_virt(drm_enc);
  4084. sde_kms = sde_encoder_get_kms(drm_enc);
  4085. if (!sde_kms) {
  4086. SDE_ERROR("invalid sde_kms\n");
  4087. return -EINVAL;
  4088. }
  4089. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  4090. /* create overall sub-directory for the encoder */
  4091. sde_enc->debugfs_root = debugfs_create_dir(name,
  4092. drm_enc->dev->primary->debugfs_root);
  4093. if (!sde_enc->debugfs_root)
  4094. return -ENOMEM;
  4095. /* don't error check these */
  4096. debugfs_create_file("status", 0400,
  4097. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  4098. debugfs_create_file("misr_data", 0600,
  4099. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  4100. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  4101. &sde_enc->idle_pc_enabled);
  4102. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  4103. &sde_enc->frame_trigger_mode);
  4104. for (i = 0; i < sde_enc->num_phys_encs; i++)
  4105. if (sde_enc->phys_encs[i] &&
  4106. sde_enc->phys_encs[i]->ops.late_register)
  4107. sde_enc->phys_encs[i]->ops.late_register(
  4108. sde_enc->phys_encs[i],
  4109. sde_enc->debugfs_root);
  4110. return 0;
  4111. }
  4112. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4113. {
  4114. struct sde_encoder_virt *sde_enc;
  4115. if (!drm_enc)
  4116. return;
  4117. sde_enc = to_sde_encoder_virt(drm_enc);
  4118. debugfs_remove_recursive(sde_enc->debugfs_root);
  4119. }
  4120. #else
  4121. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  4122. {
  4123. return 0;
  4124. }
  4125. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4126. {
  4127. }
  4128. #endif
  4129. static int sde_encoder_late_register(struct drm_encoder *encoder)
  4130. {
  4131. return _sde_encoder_init_debugfs(encoder);
  4132. }
  4133. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  4134. {
  4135. _sde_encoder_destroy_debugfs(encoder);
  4136. }
  4137. static int sde_encoder_virt_add_phys_encs(
  4138. struct msm_display_info *disp_info,
  4139. struct sde_encoder_virt *sde_enc,
  4140. struct sde_enc_phys_init_params *params)
  4141. {
  4142. struct sde_encoder_phys *enc = NULL;
  4143. u32 display_caps = disp_info->capabilities;
  4144. SDE_DEBUG_ENC(sde_enc, "\n");
  4145. /*
  4146. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  4147. * in this function, check up-front.
  4148. */
  4149. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  4150. ARRAY_SIZE(sde_enc->phys_encs)) {
  4151. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4152. sde_enc->num_phys_encs);
  4153. return -EINVAL;
  4154. }
  4155. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  4156. enc = sde_encoder_phys_vid_init(params);
  4157. if (IS_ERR_OR_NULL(enc)) {
  4158. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  4159. PTR_ERR(enc));
  4160. return !enc ? -EINVAL : PTR_ERR(enc);
  4161. }
  4162. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  4163. }
  4164. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  4165. enc = sde_encoder_phys_cmd_init(params);
  4166. if (IS_ERR_OR_NULL(enc)) {
  4167. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  4168. PTR_ERR(enc));
  4169. return !enc ? -EINVAL : PTR_ERR(enc);
  4170. }
  4171. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  4172. }
  4173. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  4174. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4175. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  4176. else
  4177. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4178. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  4179. ++sde_enc->num_phys_encs;
  4180. return 0;
  4181. }
  4182. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  4183. struct sde_enc_phys_init_params *params)
  4184. {
  4185. struct sde_encoder_phys *enc = NULL;
  4186. if (!sde_enc) {
  4187. SDE_ERROR("invalid encoder\n");
  4188. return -EINVAL;
  4189. }
  4190. SDE_DEBUG_ENC(sde_enc, "\n");
  4191. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  4192. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4193. sde_enc->num_phys_encs);
  4194. return -EINVAL;
  4195. }
  4196. enc = sde_encoder_phys_wb_init(params);
  4197. if (IS_ERR_OR_NULL(enc)) {
  4198. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  4199. PTR_ERR(enc));
  4200. return !enc ? -EINVAL : PTR_ERR(enc);
  4201. }
  4202. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  4203. ++sde_enc->num_phys_encs;
  4204. return 0;
  4205. }
  4206. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  4207. struct sde_kms *sde_kms,
  4208. struct msm_display_info *disp_info,
  4209. int *drm_enc_mode)
  4210. {
  4211. int ret = 0;
  4212. int i = 0;
  4213. enum sde_intf_type intf_type;
  4214. struct sde_encoder_virt_ops parent_ops = {
  4215. sde_encoder_vblank_callback,
  4216. sde_encoder_underrun_callback,
  4217. sde_encoder_frame_done_callback,
  4218. _sde_encoder_get_qsync_fps_callback,
  4219. };
  4220. struct sde_enc_phys_init_params phys_params;
  4221. if (!sde_enc || !sde_kms) {
  4222. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  4223. !sde_enc, !sde_kms);
  4224. return -EINVAL;
  4225. }
  4226. memset(&phys_params, 0, sizeof(phys_params));
  4227. phys_params.sde_kms = sde_kms;
  4228. phys_params.parent = &sde_enc->base;
  4229. phys_params.parent_ops = parent_ops;
  4230. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  4231. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  4232. SDE_DEBUG("\n");
  4233. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  4234. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  4235. intf_type = INTF_DSI;
  4236. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  4237. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4238. intf_type = INTF_HDMI;
  4239. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  4240. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  4241. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  4242. else
  4243. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4244. intf_type = INTF_DP;
  4245. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  4246. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  4247. intf_type = INTF_WB;
  4248. } else {
  4249. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  4250. return -EINVAL;
  4251. }
  4252. WARN_ON(disp_info->num_of_h_tiles < 1);
  4253. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  4254. sde_enc->te_source = disp_info->te_source;
  4255. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  4256. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  4257. sde_enc->input_event_enabled = sde_kms->catalog->wakeup_with_touch;
  4258. mutex_lock(&sde_enc->enc_lock);
  4259. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  4260. /*
  4261. * Left-most tile is at index 0, content is controller id
  4262. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  4263. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  4264. */
  4265. u32 controller_id = disp_info->h_tile_instance[i];
  4266. if (disp_info->num_of_h_tiles > 1) {
  4267. if (i == 0)
  4268. phys_params.split_role = ENC_ROLE_MASTER;
  4269. else
  4270. phys_params.split_role = ENC_ROLE_SLAVE;
  4271. } else {
  4272. phys_params.split_role = ENC_ROLE_SOLO;
  4273. }
  4274. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  4275. i, controller_id, phys_params.split_role);
  4276. if (intf_type == INTF_WB) {
  4277. phys_params.intf_idx = INTF_MAX;
  4278. phys_params.wb_idx = sde_encoder_get_wb(
  4279. sde_kms->catalog,
  4280. intf_type, controller_id);
  4281. if (phys_params.wb_idx == WB_MAX) {
  4282. SDE_ERROR_ENC(sde_enc,
  4283. "could not get wb: type %d, id %d\n",
  4284. intf_type, controller_id);
  4285. ret = -EINVAL;
  4286. }
  4287. } else {
  4288. phys_params.wb_idx = WB_MAX;
  4289. phys_params.intf_idx = sde_encoder_get_intf(
  4290. sde_kms->catalog, intf_type,
  4291. controller_id);
  4292. if (phys_params.intf_idx == INTF_MAX) {
  4293. SDE_ERROR_ENC(sde_enc,
  4294. "could not get wb: type %d, id %d\n",
  4295. intf_type, controller_id);
  4296. ret = -EINVAL;
  4297. }
  4298. }
  4299. if (!ret) {
  4300. if (intf_type == INTF_WB)
  4301. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  4302. &phys_params);
  4303. else
  4304. ret = sde_encoder_virt_add_phys_encs(
  4305. disp_info,
  4306. sde_enc,
  4307. &phys_params);
  4308. if (ret)
  4309. SDE_ERROR_ENC(sde_enc,
  4310. "failed to add phys encs\n");
  4311. }
  4312. }
  4313. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4314. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  4315. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  4316. if (vid_phys) {
  4317. atomic_set(&vid_phys->vsync_cnt, 0);
  4318. atomic_set(&vid_phys->underrun_cnt, 0);
  4319. }
  4320. if (cmd_phys) {
  4321. atomic_set(&cmd_phys->vsync_cnt, 0);
  4322. atomic_set(&cmd_phys->underrun_cnt, 0);
  4323. }
  4324. }
  4325. mutex_unlock(&sde_enc->enc_lock);
  4326. return ret;
  4327. }
  4328. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  4329. .mode_set = sde_encoder_virt_mode_set,
  4330. .disable = sde_encoder_virt_disable,
  4331. .enable = sde_encoder_virt_enable,
  4332. .atomic_check = sde_encoder_virt_atomic_check,
  4333. };
  4334. static const struct drm_encoder_funcs sde_encoder_funcs = {
  4335. .destroy = sde_encoder_destroy,
  4336. .late_register = sde_encoder_late_register,
  4337. .early_unregister = sde_encoder_early_unregister,
  4338. };
  4339. struct drm_encoder *sde_encoder_init(struct drm_device *dev, struct msm_display_info *disp_info)
  4340. {
  4341. struct msm_drm_private *priv = dev->dev_private;
  4342. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  4343. struct drm_encoder *drm_enc = NULL;
  4344. struct sde_encoder_virt *sde_enc = NULL;
  4345. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  4346. char name[SDE_NAME_SIZE];
  4347. int ret = 0, i, intf_index = INTF_MAX;
  4348. struct sde_encoder_phys *phys = NULL;
  4349. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4350. if (!sde_enc) {
  4351. ret = -ENOMEM;
  4352. goto fail;
  4353. }
  4354. mutex_init(&sde_enc->enc_lock);
  4355. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4356. &drm_enc_mode);
  4357. if (ret)
  4358. goto fail;
  4359. sde_enc->cur_master = NULL;
  4360. spin_lock_init(&sde_enc->enc_spinlock);
  4361. mutex_init(&sde_enc->vblank_ctl_lock);
  4362. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4363. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4364. drm_enc = &sde_enc->base;
  4365. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4366. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4367. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4368. phys = sde_enc->phys_encs[i];
  4369. if (!phys)
  4370. continue;
  4371. if (phys->ops.is_master && phys->ops.is_master(phys))
  4372. intf_index = phys->intf_idx - INTF_0;
  4373. }
  4374. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4375. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4376. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4377. SDE_RSC_PRIMARY_DISP_CLIENT :
  4378. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4379. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4380. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4381. PTR_ERR(sde_enc->rsc_client));
  4382. sde_enc->rsc_client = NULL;
  4383. }
  4384. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE &&
  4385. sde_enc->input_event_enabled) {
  4386. ret = _sde_encoder_input_handler(sde_enc);
  4387. if (ret)
  4388. SDE_ERROR(
  4389. "input handler registration failed, rc = %d\n", ret);
  4390. }
  4391. mutex_init(&sde_enc->rc_lock);
  4392. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4393. sde_encoder_off_work);
  4394. sde_enc->vblank_enabled = false;
  4395. sde_enc->qdss_status = false;
  4396. kthread_init_work(&sde_enc->input_event_work,
  4397. sde_encoder_input_event_work_handler);
  4398. kthread_init_work(&sde_enc->early_wakeup_work,
  4399. sde_encoder_early_wakeup_work_handler);
  4400. kthread_init_work(&sde_enc->esd_trigger_work,
  4401. sde_encoder_esd_trigger_work_handler);
  4402. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4403. SDE_DEBUG_ENC(sde_enc, "created\n");
  4404. return drm_enc;
  4405. fail:
  4406. SDE_ERROR("failed to create encoder\n");
  4407. if (drm_enc)
  4408. sde_encoder_destroy(drm_enc);
  4409. return ERR_PTR(ret);
  4410. }
  4411. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4412. enum msm_event_wait event)
  4413. {
  4414. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4415. struct sde_encoder_virt *sde_enc = NULL;
  4416. int i, ret = 0;
  4417. char atrace_buf[32];
  4418. if (!drm_enc) {
  4419. SDE_ERROR("invalid encoder\n");
  4420. return -EINVAL;
  4421. }
  4422. sde_enc = to_sde_encoder_virt(drm_enc);
  4423. SDE_DEBUG_ENC(sde_enc, "\n");
  4424. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4425. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4426. switch (event) {
  4427. case MSM_ENC_COMMIT_DONE:
  4428. fn_wait = phys->ops.wait_for_commit_done;
  4429. break;
  4430. case MSM_ENC_TX_COMPLETE:
  4431. fn_wait = phys->ops.wait_for_tx_complete;
  4432. break;
  4433. case MSM_ENC_VBLANK:
  4434. fn_wait = phys->ops.wait_for_vblank;
  4435. break;
  4436. case MSM_ENC_ACTIVE_REGION:
  4437. fn_wait = phys->ops.wait_for_active;
  4438. break;
  4439. default:
  4440. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4441. event);
  4442. return -EINVAL;
  4443. }
  4444. if (phys && fn_wait) {
  4445. snprintf(atrace_buf, sizeof(atrace_buf),
  4446. "wait_completion_event_%d", event);
  4447. SDE_ATRACE_BEGIN(atrace_buf);
  4448. ret = fn_wait(phys);
  4449. SDE_ATRACE_END(atrace_buf);
  4450. if (ret)
  4451. return ret;
  4452. }
  4453. }
  4454. return ret;
  4455. }
  4456. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4457. u64 *l_bound, u64 *u_bound)
  4458. {
  4459. struct sde_encoder_virt *sde_enc;
  4460. u64 jitter_ns, frametime_ns;
  4461. struct msm_mode_info *info;
  4462. if (!drm_enc) {
  4463. SDE_ERROR("invalid encoder\n");
  4464. return;
  4465. }
  4466. sde_enc = to_sde_encoder_virt(drm_enc);
  4467. info = &sde_enc->mode_info;
  4468. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4469. jitter_ns = info->jitter_numer * frametime_ns;
  4470. do_div(jitter_ns, info->jitter_denom * 100);
  4471. *l_bound = frametime_ns - jitter_ns;
  4472. *u_bound = frametime_ns + jitter_ns;
  4473. }
  4474. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4475. {
  4476. struct sde_encoder_virt *sde_enc;
  4477. if (!drm_enc) {
  4478. SDE_ERROR("invalid encoder\n");
  4479. return 0;
  4480. }
  4481. sde_enc = to_sde_encoder_virt(drm_enc);
  4482. return sde_enc->mode_info.frame_rate;
  4483. }
  4484. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4485. {
  4486. struct sde_encoder_virt *sde_enc = NULL;
  4487. int i;
  4488. if (!encoder) {
  4489. SDE_ERROR("invalid encoder\n");
  4490. return INTF_MODE_NONE;
  4491. }
  4492. sde_enc = to_sde_encoder_virt(encoder);
  4493. if (sde_enc->cur_master)
  4494. return sde_enc->cur_master->intf_mode;
  4495. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4496. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4497. if (phys)
  4498. return phys->intf_mode;
  4499. }
  4500. return INTF_MODE_NONE;
  4501. }
  4502. u32 sde_encoder_get_frame_count(struct drm_encoder *encoder)
  4503. {
  4504. struct sde_encoder_virt *sde_enc = NULL;
  4505. struct sde_encoder_phys *phys;
  4506. if (!encoder) {
  4507. SDE_ERROR("invalid encoder\n");
  4508. return 0;
  4509. }
  4510. sde_enc = to_sde_encoder_virt(encoder);
  4511. phys = sde_enc->cur_master;
  4512. return phys ? atomic_read(&phys->vsync_cnt) : 0;
  4513. }
  4514. bool sde_encoder_get_vblank_timestamp(struct drm_encoder *encoder,
  4515. ktime_t *tvblank)
  4516. {
  4517. struct sde_encoder_virt *sde_enc = NULL;
  4518. struct sde_encoder_phys *phys;
  4519. if (!encoder) {
  4520. SDE_ERROR("invalid encoder\n");
  4521. return false;
  4522. }
  4523. sde_enc = to_sde_encoder_virt(encoder);
  4524. phys = sde_enc->cur_master;
  4525. if (!phys)
  4526. return false;
  4527. *tvblank = phys->last_vsync_timestamp;
  4528. return *tvblank ? true : false;
  4529. }
  4530. static void _sde_encoder_cache_hw_res_cont_splash(
  4531. struct drm_encoder *encoder,
  4532. struct sde_kms *sde_kms)
  4533. {
  4534. int i, idx;
  4535. struct sde_encoder_virt *sde_enc;
  4536. struct sde_encoder_phys *phys_enc;
  4537. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4538. sde_enc = to_sde_encoder_virt(encoder);
  4539. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4540. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4541. sde_enc->hw_pp[i] = NULL;
  4542. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4543. break;
  4544. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4545. }
  4546. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4547. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4548. sde_enc->hw_dsc[i] = NULL;
  4549. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4550. break;
  4551. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4552. }
  4553. /*
  4554. * If we have multiple phys encoders with one controller, make
  4555. * sure to populate the controller pointer in both phys encoders.
  4556. */
  4557. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4558. phys_enc = sde_enc->phys_encs[idx];
  4559. phys_enc->hw_ctl = NULL;
  4560. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4561. SDE_HW_BLK_CTL);
  4562. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4563. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4564. phys_enc->hw_ctl =
  4565. (struct sde_hw_ctl *) ctl_iter.hw;
  4566. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4567. phys_enc->intf_idx, phys_enc->hw_ctl);
  4568. }
  4569. }
  4570. }
  4571. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4572. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4573. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4574. phys->hw_intf = NULL;
  4575. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4576. break;
  4577. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4578. }
  4579. }
  4580. /**
  4581. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4582. * device bootup when cont_splash is enabled
  4583. * @drm_enc: Pointer to drm encoder structure
  4584. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4585. * @enable: boolean indicates enable or displae state of splash
  4586. * @Return: true if successful in updating the encoder structure
  4587. */
  4588. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4589. struct sde_splash_display *splash_display, bool enable)
  4590. {
  4591. struct sde_encoder_virt *sde_enc;
  4592. struct msm_drm_private *priv;
  4593. struct sde_kms *sde_kms;
  4594. struct drm_connector *conn = NULL;
  4595. struct sde_connector *sde_conn = NULL;
  4596. struct sde_connector_state *sde_conn_state = NULL;
  4597. struct drm_display_mode *drm_mode = NULL;
  4598. struct sde_encoder_phys *phys_enc;
  4599. struct drm_bridge *bridge;
  4600. int ret = 0, i;
  4601. struct msm_sub_mode sub_mode;
  4602. if (!encoder) {
  4603. SDE_ERROR("invalid drm enc\n");
  4604. return -EINVAL;
  4605. }
  4606. sde_enc = to_sde_encoder_virt(encoder);
  4607. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4608. if (!sde_kms) {
  4609. SDE_ERROR("invalid sde_kms\n");
  4610. return -EINVAL;
  4611. }
  4612. priv = encoder->dev->dev_private;
  4613. if (!priv->num_connectors) {
  4614. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4615. return -EINVAL;
  4616. }
  4617. SDE_DEBUG_ENC(sde_enc,
  4618. "num of connectors: %d\n", priv->num_connectors);
  4619. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4620. if (!enable) {
  4621. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4622. phys_enc = sde_enc->phys_encs[i];
  4623. if (phys_enc)
  4624. phys_enc->cont_splash_enabled = false;
  4625. }
  4626. return ret;
  4627. }
  4628. if (!splash_display) {
  4629. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4630. return -EINVAL;
  4631. }
  4632. for (i = 0; i < priv->num_connectors; i++) {
  4633. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4634. priv->connectors[i]->base.id);
  4635. sde_conn = to_sde_connector(priv->connectors[i]);
  4636. if (!sde_conn->encoder) {
  4637. SDE_DEBUG_ENC(sde_enc,
  4638. "encoder not attached to connector\n");
  4639. continue;
  4640. }
  4641. if (sde_conn->encoder->base.id
  4642. == encoder->base.id) {
  4643. conn = (priv->connectors[i]);
  4644. break;
  4645. }
  4646. }
  4647. if (!conn || !conn->state) {
  4648. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4649. return -EINVAL;
  4650. }
  4651. sde_conn_state = to_sde_connector_state(conn->state);
  4652. if (!sde_conn->ops.get_mode_info) {
  4653. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4654. return -EINVAL;
  4655. }
  4656. sub_mode.dsc_mode = splash_display->dsc_cnt ? MSM_DISPLAY_DSC_MODE_ENABLED :
  4657. MSM_DISPLAY_DSC_MODE_DISABLED;
  4658. drm_mode = &encoder->crtc->state->adjusted_mode;
  4659. ret = sde_connector_get_mode_info(&sde_conn->base,
  4660. drm_mode, &sub_mode, &sde_conn_state->mode_info);
  4661. if (ret) {
  4662. SDE_ERROR_ENC(sde_enc,
  4663. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4664. return ret;
  4665. }
  4666. if (sde_conn->encoder) {
  4667. conn->state->best_encoder = sde_conn->encoder;
  4668. SDE_DEBUG_ENC(sde_enc,
  4669. "configured cstate->best_encoder to ID = %d\n",
  4670. conn->state->best_encoder->base.id);
  4671. } else {
  4672. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4673. conn->base.id);
  4674. }
  4675. sde_enc->crtc = encoder->crtc;
  4676. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4677. conn->state, false);
  4678. if (ret) {
  4679. SDE_ERROR_ENC(sde_enc,
  4680. "failed to reserve hw resources, %d\n", ret);
  4681. return ret;
  4682. }
  4683. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4684. sde_connector_get_topology_name(conn));
  4685. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4686. drm_mode->hdisplay, drm_mode->vdisplay);
  4687. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4688. bridge = drm_bridge_chain_get_first_bridge(encoder);
  4689. if (bridge) {
  4690. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4691. /*
  4692. * For cont-splash use case, we update the mode
  4693. * configurations manually. This will skip the
  4694. * usually mode set call when actual frame is
  4695. * pushed from framework. The bridge needs to
  4696. * be updated with the current drm mode by
  4697. * calling the bridge mode set ops.
  4698. */
  4699. drm_bridge_chain_mode_set(bridge, drm_mode, drm_mode);
  4700. } else {
  4701. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4702. }
  4703. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4704. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4705. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4706. if (!phys) {
  4707. SDE_ERROR_ENC(sde_enc,
  4708. "phys encoders not initialized\n");
  4709. return -EINVAL;
  4710. }
  4711. /* update connector for master and slave phys encoders */
  4712. phys->connector = conn;
  4713. phys->cont_splash_enabled = true;
  4714. phys->hw_pp = sde_enc->hw_pp[i];
  4715. if (phys->ops.cont_splash_mode_set)
  4716. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4717. if (phys->ops.is_master && phys->ops.is_master(phys))
  4718. sde_enc->cur_master = phys;
  4719. }
  4720. return ret;
  4721. }
  4722. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4723. bool skip_pre_kickoff)
  4724. {
  4725. struct msm_drm_thread *event_thread = NULL;
  4726. struct msm_drm_private *priv = NULL;
  4727. struct sde_encoder_virt *sde_enc = NULL;
  4728. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4729. SDE_ERROR("invalid parameters\n");
  4730. return -EINVAL;
  4731. }
  4732. priv = enc->dev->dev_private;
  4733. sde_enc = to_sde_encoder_virt(enc);
  4734. if (!sde_enc->crtc || (sde_enc->crtc->index
  4735. >= ARRAY_SIZE(priv->event_thread))) {
  4736. SDE_DEBUG_ENC(sde_enc,
  4737. "invalid cached CRTC: %d or crtc index: %d\n",
  4738. sde_enc->crtc == NULL,
  4739. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4740. return -EINVAL;
  4741. }
  4742. SDE_EVT32_VERBOSE(DRMID(enc));
  4743. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4744. if (!skip_pre_kickoff) {
  4745. sde_enc->delay_kickoff = true;
  4746. kthread_queue_work(&event_thread->worker,
  4747. &sde_enc->esd_trigger_work);
  4748. kthread_flush_work(&sde_enc->esd_trigger_work);
  4749. }
  4750. /*
  4751. * panel may stop generating te signal (vsync) during esd failure. rsc
  4752. * hardware may hang without vsync. Avoid rsc hang by generating the
  4753. * vsync from watchdog timer instead of panel.
  4754. */
  4755. sde_encoder_helper_switch_vsync(enc, true);
  4756. if (!skip_pre_kickoff) {
  4757. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4758. sde_enc->delay_kickoff = false;
  4759. }
  4760. return 0;
  4761. }
  4762. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4763. {
  4764. struct sde_encoder_virt *sde_enc;
  4765. if (!encoder) {
  4766. SDE_ERROR("invalid drm enc\n");
  4767. return false;
  4768. }
  4769. sde_enc = to_sde_encoder_virt(encoder);
  4770. return sde_enc->recovery_events_enabled;
  4771. }
  4772. void sde_encoder_enable_recovery_event(struct drm_encoder *encoder)
  4773. {
  4774. struct sde_encoder_virt *sde_enc;
  4775. if (!encoder) {
  4776. SDE_ERROR("invalid drm enc\n");
  4777. return;
  4778. }
  4779. sde_enc = to_sde_encoder_virt(encoder);
  4780. sde_enc->recovery_events_enabled = true;
  4781. }
  4782. bool sde_encoder_needs_dsc_disable(struct drm_encoder *drm_enc)
  4783. {
  4784. struct sde_kms *sde_kms;
  4785. struct drm_connector *conn;
  4786. struct sde_connector_state *conn_state;
  4787. if (!drm_enc)
  4788. return false;
  4789. sde_kms = sde_encoder_get_kms(drm_enc);
  4790. if (!sde_kms)
  4791. return false;
  4792. conn = sde_encoder_get_connector(sde_kms->dev, drm_enc);
  4793. if (!conn || !conn->state)
  4794. return false;
  4795. conn_state = to_sde_connector_state(conn->state);
  4796. return TOPOLOGY_DSC_MODE(conn_state->old_topology_name);
  4797. }
  4798. void sde_encoder_add_data_to_minidump_va(struct drm_encoder *drm_enc)
  4799. {
  4800. struct sde_encoder_virt *sde_enc;
  4801. struct sde_encoder_phys *phys_enc;
  4802. u32 i;
  4803. sde_enc = to_sde_encoder_virt(drm_enc);
  4804. for( i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4805. {
  4806. phys_enc = sde_enc->phys_encs[i];
  4807. if(phys_enc && phys_enc->ops.add_to_minidump)
  4808. phys_enc->ops.add_to_minidump(phys_enc);
  4809. phys_enc = sde_enc->phys_cmd_encs[i];
  4810. if(phys_enc && phys_enc->ops.add_to_minidump)
  4811. phys_enc->ops.add_to_minidump(phys_enc);
  4812. phys_enc = sde_enc->phys_vid_encs[i];
  4813. if(phys_enc && phys_enc->ops.add_to_minidump)
  4814. phys_enc->ops.add_to_minidump(phys_enc);
  4815. }
  4816. }