dp_tx.c 80 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. /**
  68. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  69. * @vdev: DP Virtual device handle
  70. * @nbuf: Buffer pointer
  71. * @queue: queue ids container for nbuf
  72. *
  73. * TX packet queue has 2 instances, software descriptors id and dma ring id
  74. * Based on tx feature and hardware configuration queue id combination could be
  75. * different.
  76. * For example -
  77. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  78. * With no XPS,lock based resource protection, Descriptor pool ids are different
  79. * for each vdev, dma ring id will be same as single pdev id
  80. *
  81. * Return: None
  82. */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. qdf_atomic_dec(&pdev->num_tx_outstanding);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  168. qdf_atomic_dec(&pdev->num_tx_exception);
  169. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  170. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  171. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  172. else
  173. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  175. "Tx Completion Release desc %d status %d outstanding %d",
  176. tx_desc->id, comp_status,
  177. qdf_atomic_read(&pdev->num_tx_outstanding));
  178. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  179. return;
  180. }
  181. /**
  182. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  183. * @vdev: DP vdev Handle
  184. * @nbuf: skb
  185. *
  186. * Prepares and fills HTT metadata in the frame pre-header for special frames
  187. * that should be transmitted using varying transmit parameters.
  188. * There are 2 VDEV modes that currently needs this special metadata -
  189. * 1) Mesh Mode
  190. * 2) DSRC Mode
  191. *
  192. * Return: HTT metadata size
  193. *
  194. */
  195. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  196. uint32_t *meta_data)
  197. {
  198. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  199. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  200. uint8_t htt_desc_size;
  201. /* Size rounded of multiple of 8 bytes */
  202. uint8_t htt_desc_size_aligned;
  203. uint8_t *hdr = NULL;
  204. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  205. /*
  206. * Metadata - HTT MSDU Extension header
  207. */
  208. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  209. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  210. if (vdev->mesh_vdev) {
  211. /* Fill and add HTT metaheader */
  212. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  213. if (hdr == NULL) {
  214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  215. "Error in filling HTT metadata\n");
  216. return 0;
  217. }
  218. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  219. } else if (vdev->opmode == wlan_op_mode_ocb) {
  220. /* Todo - Add support for DSRC */
  221. }
  222. return htt_desc_size_aligned;
  223. }
  224. /**
  225. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  226. * @tso_seg: TSO segment to process
  227. * @ext_desc: Pointer to MSDU extension descriptor
  228. *
  229. * Return: void
  230. */
  231. #if defined(FEATURE_TSO)
  232. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  233. void *ext_desc)
  234. {
  235. uint8_t num_frag;
  236. uint32_t tso_flags;
  237. /*
  238. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  239. * tcp_flag_mask
  240. *
  241. * Checksum enable flags are set in TCL descriptor and not in Extension
  242. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  243. */
  244. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  245. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  246. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  247. tso_seg->tso_flags.ip_len);
  248. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  249. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  250. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  251. uint32_t lo = 0;
  252. uint32_t hi = 0;
  253. qdf_dmaaddr_to_32s(
  254. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  255. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  256. tso_seg->tso_frags[num_frag].length);
  257. }
  258. return;
  259. }
  260. #else
  261. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  262. void *ext_desc)
  263. {
  264. return;
  265. }
  266. #endif
  267. #if defined(FEATURE_TSO)
  268. /**
  269. * dp_tx_free_tso_seg() - Loop through the tso segments
  270. * allocated and free them
  271. *
  272. * @soc: soc handle
  273. * @free_seg: list of tso segments
  274. * @msdu_info: msdu descriptor
  275. *
  276. * Return - void
  277. */
  278. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  279. struct qdf_tso_seg_elem_t *free_seg,
  280. struct dp_tx_msdu_info_s *msdu_info)
  281. {
  282. struct qdf_tso_seg_elem_t *next_seg;
  283. while (free_seg) {
  284. next_seg = free_seg->next;
  285. dp_tx_tso_desc_free(soc,
  286. msdu_info->tx_queue.desc_pool_id,
  287. free_seg);
  288. free_seg = next_seg;
  289. }
  290. }
  291. /**
  292. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  293. * allocated and free them
  294. *
  295. * @soc: soc handle
  296. * @free_seg: list of tso segments
  297. * @msdu_info: msdu descriptor
  298. * Return - void
  299. */
  300. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  301. struct qdf_tso_num_seg_elem_t *free_seg,
  302. struct dp_tx_msdu_info_s *msdu_info)
  303. {
  304. struct qdf_tso_num_seg_elem_t *next_seg;
  305. while (free_seg) {
  306. next_seg = free_seg->next;
  307. dp_tso_num_seg_free(soc,
  308. msdu_info->tx_queue.desc_pool_id,
  309. free_seg);
  310. free_seg = next_seg;
  311. }
  312. }
  313. /**
  314. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  315. * @vdev: virtual device handle
  316. * @msdu: network buffer
  317. * @msdu_info: meta data associated with the msdu
  318. *
  319. * Return: QDF_STATUS_SUCCESS success
  320. */
  321. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  322. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *tso_seg;
  325. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  326. struct dp_soc *soc = vdev->pdev->soc;
  327. struct qdf_tso_info_t *tso_info;
  328. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  329. tso_info = &msdu_info->u.tso_info;
  330. tso_info->curr_seg = NULL;
  331. tso_info->tso_seg_list = NULL;
  332. tso_info->num_segs = num_seg;
  333. msdu_info->frm_type = dp_tx_frm_tso;
  334. tso_info->tso_num_seg_list = NULL;
  335. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  336. while (num_seg) {
  337. tso_seg = dp_tx_tso_desc_alloc(
  338. soc, msdu_info->tx_queue.desc_pool_id);
  339. if (tso_seg) {
  340. tso_seg->next = tso_info->tso_seg_list;
  341. tso_info->tso_seg_list = tso_seg;
  342. num_seg--;
  343. } else {
  344. struct qdf_tso_seg_elem_t *free_seg =
  345. tso_info->tso_seg_list;
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. }
  350. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  351. tso_num_seg = dp_tso_num_seg_alloc(soc,
  352. msdu_info->tx_queue.desc_pool_id);
  353. if (tso_num_seg) {
  354. tso_num_seg->next = tso_info->tso_num_seg_list;
  355. tso_info->tso_num_seg_list = tso_num_seg;
  356. } else {
  357. /* Bug: free tso_num_seg and tso_seg */
  358. /* Free the already allocated num of segments */
  359. struct qdf_tso_seg_elem_t *free_seg =
  360. tso_info->tso_seg_list;
  361. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  362. __func__);
  363. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  364. return QDF_STATUS_E_NOMEM;
  365. }
  366. msdu_info->num_seg =
  367. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  368. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  369. msdu_info->num_seg);
  370. if (!(msdu_info->num_seg)) {
  371. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  372. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  373. msdu_info);
  374. return QDF_STATUS_E_INVAL;
  375. }
  376. tso_info->curr_seg = tso_info->tso_seg_list;
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. #else
  380. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  381. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. return QDF_STATUS_E_NOMEM;
  384. }
  385. #endif
  386. /**
  387. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  388. * @vdev: DP Vdev handle
  389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  390. * @desc_pool_id: Descriptor Pool ID
  391. *
  392. * Return:
  393. */
  394. static
  395. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  396. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  397. {
  398. uint8_t i;
  399. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  400. struct dp_tx_seg_info_s *seg_info;
  401. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  402. struct dp_soc *soc = vdev->pdev->soc;
  403. /* Allocate an extension descriptor */
  404. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  405. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  406. if (!msdu_ext_desc) {
  407. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  408. return NULL;
  409. }
  410. if (qdf_unlikely(vdev->mesh_vdev)) {
  411. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  412. &msdu_info->meta_data[0],
  413. sizeof(struct htt_tx_msdu_desc_ext2_t));
  414. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  415. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  416. }
  417. switch (msdu_info->frm_type) {
  418. case dp_tx_frm_sg:
  419. case dp_tx_frm_me:
  420. case dp_tx_frm_raw:
  421. seg_info = msdu_info->u.sg_info.curr_seg;
  422. /* Update the buffer pointers in MSDU Extension Descriptor */
  423. for (i = 0; i < seg_info->frag_cnt; i++) {
  424. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  425. seg_info->frags[i].paddr_lo,
  426. seg_info->frags[i].paddr_hi,
  427. seg_info->frags[i].len);
  428. }
  429. break;
  430. case dp_tx_frm_tso:
  431. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  432. &cached_ext_desc[0]);
  433. break;
  434. default:
  435. break;
  436. }
  437. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  438. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  439. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  440. msdu_ext_desc->vaddr);
  441. return msdu_ext_desc;
  442. }
  443. /**
  444. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  445. * @vdev: DP vdev handle
  446. * @nbuf: skb
  447. * @desc_pool_id: Descriptor pool ID
  448. * Allocate and prepare Tx descriptor with msdu information.
  449. *
  450. * Return: Pointer to Tx Descriptor on success,
  451. * NULL on failure
  452. */
  453. static
  454. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  455. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  456. uint32_t *meta_data)
  457. {
  458. uint8_t align_pad;
  459. uint8_t is_exception = 0;
  460. uint8_t htt_hdr_size;
  461. struct ether_header *eh;
  462. struct dp_tx_desc_s *tx_desc;
  463. struct dp_pdev *pdev = vdev->pdev;
  464. struct dp_soc *soc = pdev->soc;
  465. /* Allocate software Tx descriptor */
  466. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  467. if (qdf_unlikely(!tx_desc)) {
  468. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  469. return NULL;
  470. }
  471. /* Flow control/Congestion Control counters */
  472. qdf_atomic_inc(&pdev->num_tx_outstanding);
  473. /* Initialize the SW tx descriptor */
  474. tx_desc->nbuf = nbuf;
  475. tx_desc->frm_type = dp_tx_frm_std;
  476. tx_desc->tx_encap_type = vdev->tx_encap_type;
  477. tx_desc->vdev = vdev;
  478. tx_desc->pdev = pdev;
  479. tx_desc->msdu_ext_desc = NULL;
  480. tx_desc->pkt_offset = 0;
  481. /*
  482. * For special modes (vdev_type == ocb or mesh), data frames should be
  483. * transmitted using varying transmit parameters (tx spec) which include
  484. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  485. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  486. * These frames are sent as exception packets to firmware.
  487. *
  488. * HW requirement is that metadata should always point to a
  489. * 8-byte aligned address. So we add alignment pad to start of buffer.
  490. * HTT Metadata should be ensured to be multiple of 8-bytes,
  491. * to get 8-byte aligned start address along with align_pad added
  492. *
  493. * |-----------------------------|
  494. * | |
  495. * |-----------------------------| <-----Buffer Pointer Address given
  496. * | | ^ in HW descriptor (aligned)
  497. * | HTT Metadata | |
  498. * | | |
  499. * | | | Packet Offset given in descriptor
  500. * | | |
  501. * |-----------------------------| |
  502. * | Alignment Pad | v
  503. * |-----------------------------| <----- Actual buffer start address
  504. * | SKB Data | (Unaligned)
  505. * | |
  506. * | |
  507. * | |
  508. * | |
  509. * | |
  510. * |-----------------------------|
  511. */
  512. if (qdf_unlikely(vdev->mesh_vdev ||
  513. (vdev->opmode == wlan_op_mode_ocb))) {
  514. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  515. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  516. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  517. "qdf_nbuf_push_head failed\n");
  518. goto failure;
  519. }
  520. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  521. meta_data);
  522. if (htt_hdr_size == 0)
  523. goto failure;
  524. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  525. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  526. is_exception = 1;
  527. }
  528. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  529. qdf_nbuf_map(soc->osdev, nbuf,
  530. QDF_DMA_TO_DEVICE))) {
  531. /* Handle failure */
  532. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  533. "qdf_nbuf_map failed\n");
  534. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  535. goto failure;
  536. }
  537. if (qdf_unlikely(vdev->nawds_enabled)) {
  538. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  539. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  540. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  541. is_exception = 1;
  542. }
  543. }
  544. #if !TQM_BYPASS_WAR
  545. if (is_exception)
  546. #endif
  547. {
  548. /* Temporary WAR due to TQM VP issues */
  549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  550. qdf_atomic_inc(&pdev->num_tx_exception);
  551. }
  552. return tx_desc;
  553. failure:
  554. dp_tx_desc_release(tx_desc, desc_pool_id);
  555. return NULL;
  556. }
  557. /**
  558. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  559. * @vdev: DP vdev handle
  560. * @nbuf: skb
  561. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  562. * @desc_pool_id : Descriptor Pool ID
  563. *
  564. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  565. * information. For frames wth fragments, allocate and prepare
  566. * an MSDU extension descriptor
  567. *
  568. * Return: Pointer to Tx Descriptor on success,
  569. * NULL on failure
  570. */
  571. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  572. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  573. uint8_t desc_pool_id)
  574. {
  575. struct dp_tx_desc_s *tx_desc;
  576. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  577. struct dp_pdev *pdev = vdev->pdev;
  578. struct dp_soc *soc = pdev->soc;
  579. /* Allocate software Tx descriptor */
  580. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  581. if (!tx_desc) {
  582. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  583. return NULL;
  584. }
  585. /* Flow control/Congestion Control counters */
  586. qdf_atomic_inc(&pdev->num_tx_outstanding);
  587. /* Initialize the SW tx descriptor */
  588. tx_desc->nbuf = nbuf;
  589. tx_desc->frm_type = msdu_info->frm_type;
  590. tx_desc->tx_encap_type = vdev->tx_encap_type;
  591. tx_desc->vdev = vdev;
  592. tx_desc->pdev = pdev;
  593. tx_desc->pkt_offset = 0;
  594. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  595. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  596. /* Handle scattered frames - TSO/SG/ME */
  597. /* Allocate and prepare an extension descriptor for scattered frames */
  598. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  599. if (!msdu_ext_desc) {
  600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  601. "%s Tx Extension Descriptor Alloc Fail\n",
  602. __func__);
  603. goto failure;
  604. }
  605. #if TQM_BYPASS_WAR
  606. /* Temporary WAR due to TQM VP issues */
  607. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  608. qdf_atomic_inc(&pdev->num_tx_exception);
  609. #endif
  610. if (qdf_unlikely(vdev->mesh_vdev))
  611. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  612. tx_desc->msdu_ext_desc = msdu_ext_desc;
  613. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  614. return tx_desc;
  615. failure:
  616. dp_tx_desc_release(tx_desc, desc_pool_id);
  617. return NULL;
  618. }
  619. /**
  620. * dp_tx_prepare_raw() - Prepare RAW packet TX
  621. * @vdev: DP vdev handle
  622. * @nbuf: buffer pointer
  623. * @seg_info: Pointer to Segment info Descriptor to be prepared
  624. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  625. * descriptor
  626. *
  627. * Return:
  628. */
  629. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  630. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  631. {
  632. qdf_nbuf_t curr_nbuf = NULL;
  633. uint16_t total_len = 0;
  634. qdf_dma_addr_t paddr;
  635. int32_t i;
  636. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  637. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  638. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  639. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  640. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  641. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  642. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  643. QDF_DMA_TO_DEVICE)) {
  644. qdf_print("dma map error\n");
  645. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  646. qdf_nbuf_free(nbuf);
  647. return NULL;
  648. }
  649. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  650. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  651. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  652. seg_info->frags[i].paddr_lo = paddr;
  653. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  654. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  655. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  656. total_len += qdf_nbuf_len(curr_nbuf);
  657. }
  658. seg_info->frag_cnt = i;
  659. seg_info->total_len = total_len;
  660. seg_info->next = NULL;
  661. sg_info->curr_seg = seg_info;
  662. msdu_info->frm_type = dp_tx_frm_raw;
  663. msdu_info->num_seg = 1;
  664. return nbuf;
  665. }
  666. /**
  667. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  668. * @soc: DP Soc Handle
  669. * @vdev: DP vdev handle
  670. * @tx_desc: Tx Descriptor Handle
  671. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  672. * @fw_metadata: Metadata to send to Target Firmware along with frame
  673. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  674. *
  675. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  676. * from software Tx descriptor
  677. *
  678. * Return:
  679. */
  680. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  681. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  682. uint16_t fw_metadata, uint8_t ring_id)
  683. {
  684. uint8_t type;
  685. uint16_t length;
  686. void *hal_tx_desc, *hal_tx_desc_cached;
  687. qdf_dma_addr_t dma_addr;
  688. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  689. /* Return Buffer Manager ID */
  690. uint8_t bm_id = ring_id;
  691. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  692. hal_tx_desc_cached = (void *) cached_desc;
  693. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  694. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  695. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  696. type = HAL_TX_BUF_TYPE_EXT_DESC;
  697. dma_addr = tx_desc->msdu_ext_desc->paddr;
  698. } else {
  699. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  700. type = HAL_TX_BUF_TYPE_BUFFER;
  701. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  702. }
  703. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  704. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  705. dma_addr , bm_id, tx_desc->id, type);
  706. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  707. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  708. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  709. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  710. vdev->dscp_tid_map_id);
  711. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  712. sec_type_map[vdev->sec_type]);
  713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  714. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  715. __func__, length, type, (uint64_t)dma_addr,
  716. tx_desc->pkt_offset, tx_desc->id);
  717. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  718. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  719. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  720. vdev->hal_desc_addr_search_flags);
  721. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  722. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  723. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  724. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  725. }
  726. if (tid != HTT_TX_EXT_TID_INVALID)
  727. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  728. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  729. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  730. /* Sync cached descriptor with HW */
  731. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  732. if (!hal_tx_desc) {
  733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  734. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  735. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  736. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  737. return QDF_STATUS_E_RESOURCES;
  738. }
  739. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  740. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  741. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  742. /*
  743. * If one packet is enqueued in HW, PM usage count needs to be
  744. * incremented by one to prevent future runtime suspend. This
  745. * should be tied with the success of enqueuing. It will be
  746. * decremented after the packet has been sent.
  747. */
  748. hif_pm_runtime_get_noresume(soc->hif_handle);
  749. return QDF_STATUS_SUCCESS;
  750. }
  751. /**
  752. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  753. * @vdev: DP vdev handle
  754. * @nbuf: skb
  755. *
  756. * Extract the DSCP or PCP information from frame and map into TID value.
  757. * Software based TID classification is required when more than 2 DSCP-TID
  758. * mapping tables are needed.
  759. * Hardware supports 2 DSCP-TID mapping tables
  760. *
  761. * Return: void
  762. */
  763. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  764. struct dp_tx_msdu_info_s *msdu_info)
  765. {
  766. uint8_t tos = 0, dscp_tid_override = 0;
  767. uint8_t *hdr_ptr, *L3datap;
  768. uint8_t is_mcast = 0;
  769. struct ether_header *eh = NULL;
  770. qdf_ethervlan_header_t *evh = NULL;
  771. uint16_t ether_type;
  772. qdf_llc_t *llcHdr;
  773. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  774. /* for mesh packets don't do any classification */
  775. if (qdf_unlikely(vdev->mesh_vdev))
  776. return;
  777. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  778. eh = (struct ether_header *) nbuf->data;
  779. hdr_ptr = eh->ether_dhost;
  780. L3datap = hdr_ptr + sizeof(struct ether_header);
  781. } else {
  782. qdf_dot3_qosframe_t *qos_wh =
  783. (qdf_dot3_qosframe_t *) nbuf->data;
  784. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  785. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  786. return;
  787. }
  788. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  789. ether_type = eh->ether_type;
  790. /*
  791. * Check if packet is dot3 or eth2 type.
  792. */
  793. if (IS_LLC_PRESENT(ether_type)) {
  794. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  795. sizeof(*llcHdr));
  796. if (ether_type == htons(ETHERTYPE_8021Q)) {
  797. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  798. sizeof(*llcHdr);
  799. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  800. + sizeof(*llcHdr) +
  801. sizeof(qdf_net_vlanhdr_t));
  802. } else {
  803. L3datap = hdr_ptr + sizeof(struct ether_header) +
  804. sizeof(*llcHdr);
  805. }
  806. } else {
  807. if (ether_type == htons(ETHERTYPE_8021Q)) {
  808. evh = (qdf_ethervlan_header_t *) eh;
  809. ether_type = evh->ether_type;
  810. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  811. }
  812. }
  813. /*
  814. * Find priority from IP TOS DSCP field
  815. */
  816. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  817. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  818. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  819. /* Only for unicast frames */
  820. if (!is_mcast) {
  821. /* send it on VO queue */
  822. msdu_info->tid = DP_VO_TID;
  823. }
  824. } else {
  825. /*
  826. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  827. * from TOS byte.
  828. */
  829. tos = ip->ip_tos;
  830. dscp_tid_override = 1;
  831. }
  832. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  833. /* TODO
  834. * use flowlabel
  835. *igmpmld cases to be handled in phase 2
  836. */
  837. unsigned long ver_pri_flowlabel;
  838. unsigned long pri;
  839. ver_pri_flowlabel = *(unsigned long *) L3datap;
  840. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  841. DP_IPV6_PRIORITY_SHIFT;
  842. tos = pri;
  843. dscp_tid_override = 1;
  844. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  845. msdu_info->tid = DP_VO_TID;
  846. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  847. /* Only for unicast frames */
  848. if (!is_mcast) {
  849. /* send ucast arp on VO queue */
  850. msdu_info->tid = DP_VO_TID;
  851. }
  852. }
  853. /*
  854. * Assign all MCAST packets to BE
  855. */
  856. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  857. if (is_mcast) {
  858. tos = 0;
  859. dscp_tid_override = 1;
  860. }
  861. }
  862. if (dscp_tid_override == 1) {
  863. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  864. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  865. }
  866. return;
  867. }
  868. #ifdef CONVERGED_TDLS_ENABLE
  869. /**
  870. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  871. * @tx_desc: TX descriptor
  872. *
  873. * Return: None
  874. */
  875. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  876. {
  877. if (tx_desc->vdev) {
  878. if (tx_desc->vdev->is_tdls_frame)
  879. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  880. tx_desc->vdev->is_tdls_frame = false;
  881. }
  882. }
  883. /**
  884. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  885. * @tx_desc: TX descriptor
  886. * @vdev: datapath vdev handle
  887. *
  888. * Return: None
  889. */
  890. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  891. struct dp_vdev *vdev)
  892. {
  893. struct hal_tx_completion_status ts = {0};
  894. qdf_nbuf_t nbuf = tx_desc->nbuf;
  895. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  896. if (vdev->tx_non_std_data_callback.func) {
  897. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  898. vdev->tx_non_std_data_callback.func(
  899. vdev->tx_non_std_data_callback.ctxt,
  900. nbuf, ts.status);
  901. return;
  902. }
  903. }
  904. #endif
  905. /**
  906. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  907. * @vdev: DP vdev handle
  908. * @nbuf: skb
  909. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  910. * @tx_q: Tx queue to be used for this Tx frame
  911. * @peer_id: peer_id of the peer in case of NAWDS frames
  912. *
  913. * Return: NULL on success,
  914. * nbuf when it fails to send
  915. */
  916. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  917. uint8_t tid, struct dp_tx_queue *tx_q,
  918. uint32_t *meta_data, uint16_t peer_id)
  919. {
  920. struct dp_pdev *pdev = vdev->pdev;
  921. struct dp_soc *soc = pdev->soc;
  922. struct dp_tx_desc_s *tx_desc;
  923. QDF_STATUS status;
  924. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  925. uint16_t htt_tcl_metadata = 0;
  926. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  927. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  928. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  929. if (!tx_desc) {
  930. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  931. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  932. __func__, vdev, tx_q->desc_pool_id);
  933. return nbuf;
  934. }
  935. dp_tx_update_tdls_flags(tx_desc);
  936. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  937. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  938. "%s %d : HAL RING Access Failed -- %pK\n",
  939. __func__, __LINE__, hal_srng);
  940. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  941. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  942. goto fail_return;
  943. }
  944. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  945. htt_tcl_metadata = vdev->htt_tcl_metadata;
  946. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  947. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  948. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  949. HTT_TCL_METADATA_TYPE_PEER_BASED);
  950. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  951. peer_id);
  952. } else
  953. htt_tcl_metadata = vdev->htt_tcl_metadata;
  954. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  955. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  956. htt_tcl_metadata, tx_q->ring_id);
  957. if (status != QDF_STATUS_SUCCESS) {
  958. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  959. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  960. __func__, tx_desc, tx_q->ring_id);
  961. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  962. goto fail_return;
  963. }
  964. nbuf = NULL;
  965. fail_return:
  966. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  967. hal_srng_access_end(soc->hal_soc, hal_srng);
  968. hif_pm_runtime_put(soc->hif_handle);
  969. } else {
  970. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  971. }
  972. return nbuf;
  973. }
  974. /**
  975. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  976. * @vdev: DP vdev handle
  977. * @nbuf: skb
  978. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  979. *
  980. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  981. *
  982. * Return: NULL on success,
  983. * nbuf when it fails to send
  984. */
  985. #if QDF_LOCK_STATS
  986. static noinline
  987. #else
  988. static
  989. #endif
  990. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  991. struct dp_tx_msdu_info_s *msdu_info)
  992. {
  993. uint8_t i;
  994. struct dp_pdev *pdev = vdev->pdev;
  995. struct dp_soc *soc = pdev->soc;
  996. struct dp_tx_desc_s *tx_desc;
  997. QDF_STATUS status;
  998. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  999. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1000. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1001. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1002. "%s %d : HAL RING Access Failed -- %pK\n",
  1003. __func__, __LINE__, hal_srng);
  1004. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1005. return nbuf;
  1006. }
  1007. if (msdu_info->frm_type == dp_tx_frm_me)
  1008. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1009. i = 0;
  1010. /* Print statement to track i and num_seg */
  1011. /*
  1012. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1013. * descriptors using information in msdu_info
  1014. */
  1015. while (i < msdu_info->num_seg) {
  1016. /*
  1017. * Setup Tx descriptor for an MSDU, and MSDU extension
  1018. * descriptor
  1019. */
  1020. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1021. tx_q->desc_pool_id);
  1022. if (!tx_desc) {
  1023. if (msdu_info->frm_type == dp_tx_frm_me) {
  1024. dp_tx_me_free_buf(pdev,
  1025. (void *)(msdu_info->u.sg_info
  1026. .curr_seg->frags[0].vaddr));
  1027. }
  1028. goto done;
  1029. }
  1030. if (msdu_info->frm_type == dp_tx_frm_me) {
  1031. tx_desc->me_buffer =
  1032. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1033. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1034. }
  1035. /*
  1036. * Enqueue the Tx MSDU descriptor to HW for transmit
  1037. */
  1038. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1039. vdev->htt_tcl_metadata, tx_q->ring_id);
  1040. if (status != QDF_STATUS_SUCCESS) {
  1041. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1042. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1043. __func__, tx_desc, tx_q->ring_id);
  1044. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1045. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1046. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1047. goto done;
  1048. }
  1049. /*
  1050. * TODO
  1051. * if tso_info structure can be modified to have curr_seg
  1052. * as first element, following 2 blocks of code (for TSO and SG)
  1053. * can be combined into 1
  1054. */
  1055. /*
  1056. * For frames with multiple segments (TSO, ME), jump to next
  1057. * segment.
  1058. */
  1059. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1060. if (msdu_info->u.tso_info.curr_seg->next) {
  1061. msdu_info->u.tso_info.curr_seg =
  1062. msdu_info->u.tso_info.curr_seg->next;
  1063. /*
  1064. * If this is a jumbo nbuf, then increment the number of
  1065. * nbuf users for each additional segment of the msdu.
  1066. * This will ensure that the skb is freed only after
  1067. * receiving tx completion for all segments of an nbuf
  1068. */
  1069. qdf_nbuf_inc_users(nbuf);
  1070. /* Check with MCL if this is needed */
  1071. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1072. }
  1073. }
  1074. /*
  1075. * For Multicast-Unicast converted packets,
  1076. * each converted frame (for a client) is represented as
  1077. * 1 segment
  1078. */
  1079. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1080. (msdu_info->frm_type == dp_tx_frm_me)) {
  1081. if (msdu_info->u.sg_info.curr_seg->next) {
  1082. msdu_info->u.sg_info.curr_seg =
  1083. msdu_info->u.sg_info.curr_seg->next;
  1084. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1085. }
  1086. }
  1087. i++;
  1088. }
  1089. nbuf = NULL;
  1090. done:
  1091. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1092. hal_srng_access_end(soc->hal_soc, hal_srng);
  1093. hif_pm_runtime_put(soc->hif_handle);
  1094. } else {
  1095. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1096. }
  1097. return nbuf;
  1098. }
  1099. /**
  1100. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1101. * for SG frames
  1102. * @vdev: DP vdev handle
  1103. * @nbuf: skb
  1104. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1105. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1106. *
  1107. * Return: NULL on success,
  1108. * nbuf when it fails to send
  1109. */
  1110. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1111. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1112. {
  1113. uint32_t cur_frag, nr_frags;
  1114. qdf_dma_addr_t paddr;
  1115. struct dp_tx_sg_info_s *sg_info;
  1116. sg_info = &msdu_info->u.sg_info;
  1117. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1118. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1119. QDF_DMA_TO_DEVICE)) {
  1120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1121. "dma map error\n");
  1122. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1123. qdf_nbuf_free(nbuf);
  1124. return NULL;
  1125. }
  1126. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1127. seg_info->frags[0].paddr_lo = paddr;
  1128. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1129. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1130. seg_info->frags[0].vaddr = (void *) nbuf;
  1131. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1132. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1133. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1135. "frag dma map error\n");
  1136. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1137. qdf_nbuf_free(nbuf);
  1138. return NULL;
  1139. }
  1140. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1141. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1142. seg_info->frags[cur_frag + 1].paddr_hi =
  1143. ((uint64_t) paddr) >> 32;
  1144. seg_info->frags[cur_frag + 1].len =
  1145. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1146. }
  1147. seg_info->frag_cnt = (cur_frag + 1);
  1148. seg_info->total_len = qdf_nbuf_len(nbuf);
  1149. seg_info->next = NULL;
  1150. sg_info->curr_seg = seg_info;
  1151. msdu_info->frm_type = dp_tx_frm_sg;
  1152. msdu_info->num_seg = 1;
  1153. return nbuf;
  1154. }
  1155. #ifdef MESH_MODE_SUPPORT
  1156. /**
  1157. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1158. and prepare msdu_info for mesh frames.
  1159. * @vdev: DP vdev handle
  1160. * @nbuf: skb
  1161. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1162. *
  1163. * Return: NULL on failure,
  1164. * nbuf when extracted successfully
  1165. */
  1166. static
  1167. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1168. struct dp_tx_msdu_info_s *msdu_info)
  1169. {
  1170. struct meta_hdr_s *mhdr;
  1171. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1172. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1173. nbuf = qdf_nbuf_unshare(nbuf);
  1174. if (nbuf == NULL) {
  1175. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1176. "qdf_nbuf_unshare failed\n");
  1177. return nbuf;
  1178. }
  1179. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1180. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1181. meta_data->host_tx_desc_pool = 1;
  1182. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1183. meta_data->power = mhdr->power;
  1184. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1185. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1186. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1187. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1188. meta_data->dyn_bw = 1;
  1189. meta_data->valid_pwr = 1;
  1190. meta_data->valid_mcs_mask = 1;
  1191. meta_data->valid_nss_mask = 1;
  1192. meta_data->valid_preamble_type = 1;
  1193. meta_data->valid_retries = 1;
  1194. meta_data->valid_bw_info = 1;
  1195. }
  1196. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1197. meta_data->encrypt_type = 0;
  1198. meta_data->valid_encrypt_type = 1;
  1199. }
  1200. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1201. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1202. else
  1203. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1204. meta_data->valid_key_flags = 1;
  1205. meta_data->key_flags = (mhdr->keyix & 0x3);
  1206. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1208. "qdf_nbuf_pull_head failed\n");
  1209. qdf_nbuf_free(nbuf);
  1210. return NULL;
  1211. }
  1212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1213. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1214. __func__, msdu_info->meta_data[0],
  1215. msdu_info->meta_data[1],
  1216. msdu_info->meta_data[2],
  1217. msdu_info->meta_data[3],
  1218. msdu_info->meta_data[4]);
  1219. return nbuf;
  1220. }
  1221. #else
  1222. static
  1223. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1224. struct dp_tx_msdu_info_s *msdu_info)
  1225. {
  1226. return nbuf;
  1227. }
  1228. #endif
  1229. #ifdef DP_FEATURE_NAWDS_TX
  1230. /**
  1231. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1232. * @vdev: dp_vdev handle
  1233. * @nbuf: skb
  1234. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1235. * @tx_q: Tx queue to be used for this Tx frame
  1236. * @meta_data: Meta date for mesh
  1237. * @peer_id: peer_id of the peer in case of NAWDS frames
  1238. *
  1239. * return: NULL on success nbuf on failure
  1240. */
  1241. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1242. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data)
  1243. {
  1244. struct dp_peer *peer = NULL;
  1245. struct dp_soc *soc = vdev->pdev->soc;
  1246. struct dp_ast_entry *ast_entry = NULL;
  1247. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1248. uint16_t peer_id = HTT_INVALID_PEER;
  1249. struct dp_peer *sa_peer = NULL;
  1250. qdf_nbuf_t nbuf_copy;
  1251. qdf_spin_lock_bh(&(soc->ast_lock));
  1252. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1253. if (ast_entry)
  1254. sa_peer = ast_entry->peer;
  1255. qdf_spin_unlock_bh(&(soc->ast_lock));
  1256. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1257. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1258. (peer->nawds_enabled)) {
  1259. if (sa_peer == peer) {
  1260. QDF_TRACE(QDF_MODULE_ID_DP,
  1261. QDF_TRACE_LEVEL_DEBUG,
  1262. " %s: broadcast multicast packet",
  1263. __func__);
  1264. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1265. continue;
  1266. }
  1267. nbuf_copy = qdf_nbuf_copy(nbuf);
  1268. if (!nbuf_copy) {
  1269. QDF_TRACE(QDF_MODULE_ID_DP,
  1270. QDF_TRACE_LEVEL_ERROR,
  1271. "nbuf copy failed");
  1272. }
  1273. peer_id = peer->peer_ids[0];
  1274. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1275. tx_q, meta_data, peer_id);
  1276. if (nbuf_copy != NULL) {
  1277. qdf_nbuf_free(nbuf_copy);
  1278. continue;
  1279. }
  1280. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1281. 1, qdf_nbuf_len(nbuf));
  1282. }
  1283. }
  1284. if (peer_id == HTT_INVALID_PEER)
  1285. return nbuf;
  1286. return NULL;
  1287. }
  1288. #endif
  1289. /**
  1290. * dp_tx_send() - Transmit a frame on a given VAP
  1291. * @vap_dev: DP vdev handle
  1292. * @nbuf: skb
  1293. *
  1294. * Entry point for Core Tx layer (DP_TX) invoked from
  1295. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1296. * cases
  1297. *
  1298. * Return: NULL on success,
  1299. * nbuf when it fails to send
  1300. */
  1301. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1302. {
  1303. struct ether_header *eh = NULL;
  1304. struct dp_tx_msdu_info_s msdu_info;
  1305. struct dp_tx_seg_info_s seg_info;
  1306. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1307. uint16_t peer_id = HTT_INVALID_PEER;
  1308. qdf_nbuf_t nbuf_mesh = NULL;
  1309. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1310. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1311. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1313. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1314. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1315. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1316. /*
  1317. * Set Default Host TID value to invalid TID
  1318. * (TID override disabled)
  1319. */
  1320. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1321. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1322. if (qdf_unlikely(vdev->mesh_vdev)) {
  1323. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1324. &msdu_info);
  1325. if (nbuf_mesh == NULL) {
  1326. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1327. "Extracting mesh metadata failed\n");
  1328. return nbuf;
  1329. }
  1330. nbuf = nbuf_mesh;
  1331. }
  1332. /*
  1333. * Get HW Queue to use for this frame.
  1334. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1335. * dedicated for data and 1 for command.
  1336. * "queue_id" maps to one hardware ring.
  1337. * With each ring, we also associate a unique Tx descriptor pool
  1338. * to minimize lock contention for these resources.
  1339. */
  1340. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1341. /*
  1342. * TCL H/W supports 2 DSCP-TID mapping tables.
  1343. * Table 1 - Default DSCP-TID mapping table
  1344. * Table 2 - 1 DSCP-TID override table
  1345. *
  1346. * If we need a different DSCP-TID mapping for this vap,
  1347. * call tid_classify to extract DSCP/ToS from frame and
  1348. * map to a TID and store in msdu_info. This is later used
  1349. * to fill in TCL Input descriptor (per-packet TID override).
  1350. */
  1351. if (vdev->dscp_tid_map_id > 1)
  1352. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1353. /* Reset the control block */
  1354. qdf_nbuf_reset_ctxt(nbuf);
  1355. /*
  1356. * Classify the frame and call corresponding
  1357. * "prepare" function which extracts the segment (TSO)
  1358. * and fragmentation information (for TSO , SG, ME, or Raw)
  1359. * into MSDU_INFO structure which is later used to fill
  1360. * SW and HW descriptors.
  1361. */
  1362. if (qdf_nbuf_is_tso(nbuf)) {
  1363. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1364. "%s TSO frame %pK\n", __func__, vdev);
  1365. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1366. qdf_nbuf_len(nbuf));
  1367. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1368. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1369. return nbuf;
  1370. }
  1371. goto send_multiple;
  1372. }
  1373. /* SG */
  1374. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1375. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1377. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1378. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1379. qdf_nbuf_len(nbuf));
  1380. goto send_multiple;
  1381. }
  1382. #ifdef ATH_SUPPORT_IQUE
  1383. /* Mcast to Ucast Conversion*/
  1384. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1385. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1386. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1387. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1388. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1389. DP_STATS_INC_PKT(vdev,
  1390. tx_i.mcast_en.mcast_pkt, 1,
  1391. qdf_nbuf_len(nbuf));
  1392. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1393. qdf_nbuf_free(nbuf);
  1394. return NULL;
  1395. }
  1396. return nbuf;
  1397. }
  1398. }
  1399. #endif
  1400. /* RAW */
  1401. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1402. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1403. if (nbuf == NULL)
  1404. return NULL;
  1405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1406. "%s Raw frame %pK\n", __func__, vdev);
  1407. goto send_multiple;
  1408. }
  1409. /* Single linear frame */
  1410. /*
  1411. * If nbuf is a simple linear frame, use send_single function to
  1412. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1413. * SRNG. There is no need to setup a MSDU extension descriptor.
  1414. */
  1415. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1416. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1417. return nbuf;
  1418. send_multiple:
  1419. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1420. return nbuf;
  1421. }
  1422. /**
  1423. * dp_tx_reinject_handler() - Tx Reinject Handler
  1424. * @tx_desc: software descriptor head pointer
  1425. * @status : Tx completion status from HTT descriptor
  1426. *
  1427. * This function reinjects frames back to Target.
  1428. * Todo - Host queue needs to be added
  1429. *
  1430. * Return: none
  1431. */
  1432. static
  1433. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1434. {
  1435. struct dp_vdev *vdev;
  1436. struct dp_peer *peer = NULL;
  1437. uint32_t peer_id = HTT_INVALID_PEER;
  1438. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1439. qdf_nbuf_t nbuf_copy = NULL;
  1440. struct dp_tx_msdu_info_s msdu_info;
  1441. struct dp_peer *sa_peer = NULL;
  1442. struct dp_ast_entry *ast_entry = NULL;
  1443. struct dp_soc *soc = NULL;
  1444. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1445. vdev = tx_desc->vdev;
  1446. soc = vdev->pdev->soc;
  1447. qdf_assert(vdev);
  1448. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1449. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1451. "%s Tx reinject path\n", __func__);
  1452. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1453. qdf_nbuf_len(tx_desc->nbuf));
  1454. qdf_spin_lock_bh(&(soc->ast_lock));
  1455. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1456. if (ast_entry)
  1457. sa_peer = ast_entry->peer;
  1458. qdf_spin_unlock_bh(&(soc->ast_lock));
  1459. if (qdf_unlikely(vdev->mesh_vdev)) {
  1460. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1461. } else {
  1462. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1463. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1464. ((peer->bss_peer &&
  1465. !(vdev->osif_proxy_arp(
  1466. vdev->osif_vdev,
  1467. nbuf))) ||
  1468. peer->nawds_enabled)) {
  1469. peer_id = DP_INVALID_PEER;
  1470. if (peer->nawds_enabled) {
  1471. peer_id = peer->peer_ids[0];
  1472. if (sa_peer == peer) {
  1473. QDF_TRACE(
  1474. QDF_MODULE_ID_DP,
  1475. QDF_TRACE_LEVEL_DEBUG,
  1476. " %s: multicast packet",
  1477. __func__);
  1478. DP_STATS_INC(peer,
  1479. tx.nawds_mcast_drop, 1);
  1480. continue;
  1481. }
  1482. }
  1483. nbuf_copy = qdf_nbuf_copy(nbuf);
  1484. if (!nbuf_copy) {
  1485. QDF_TRACE(QDF_MODULE_ID_DP,
  1486. QDF_TRACE_LEVEL_DEBUG,
  1487. FL("nbuf copy failed"));
  1488. break;
  1489. }
  1490. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1491. nbuf_copy,
  1492. msdu_info.tid,
  1493. &msdu_info.tx_queue,
  1494. msdu_info.meta_data,
  1495. peer_id);
  1496. if (nbuf_copy) {
  1497. QDF_TRACE(QDF_MODULE_ID_DP,
  1498. QDF_TRACE_LEVEL_DEBUG,
  1499. FL("pkt send failed"));
  1500. qdf_nbuf_free(nbuf_copy);
  1501. } else {
  1502. if (peer_id != DP_INVALID_PEER)
  1503. DP_STATS_INC_PKT(peer,
  1504. tx.nawds_mcast,
  1505. 1, qdf_nbuf_len(nbuf));
  1506. }
  1507. }
  1508. }
  1509. }
  1510. if (vdev->nawds_enabled) {
  1511. peer_id = DP_INVALID_PEER;
  1512. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1513. 1, qdf_nbuf_len(nbuf));
  1514. nbuf = dp_tx_send_msdu_single(vdev,
  1515. nbuf, msdu_info.tid,
  1516. &msdu_info.tx_queue,
  1517. msdu_info.meta_data, peer_id);
  1518. if (nbuf) {
  1519. QDF_TRACE(QDF_MODULE_ID_DP,
  1520. QDF_TRACE_LEVEL_DEBUG,
  1521. FL("pkt send failed"));
  1522. qdf_nbuf_free(nbuf);
  1523. }
  1524. } else
  1525. qdf_nbuf_free(nbuf);
  1526. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1527. }
  1528. /**
  1529. * dp_tx_inspect_handler() - Tx Inspect Handler
  1530. * @tx_desc: software descriptor head pointer
  1531. * @status : Tx completion status from HTT descriptor
  1532. *
  1533. * Handles Tx frames sent back to Host for inspection
  1534. * (ProxyARP)
  1535. *
  1536. * Return: none
  1537. */
  1538. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1539. {
  1540. struct dp_soc *soc;
  1541. struct dp_pdev *pdev = tx_desc->pdev;
  1542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1543. "%s Tx inspect path\n",
  1544. __func__);
  1545. qdf_assert(pdev);
  1546. soc = pdev->soc;
  1547. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1548. qdf_nbuf_len(tx_desc->nbuf));
  1549. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1550. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1551. }
  1552. #ifdef FEATURE_PERPKT_INFO
  1553. static QDF_STATUS
  1554. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1555. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1556. {
  1557. struct tx_capture_hdr *ppdu_hdr;
  1558. struct dp_peer *peer = NULL;
  1559. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->am_copy_mode))
  1560. return QDF_STATUS_E_NOSUPPORT;
  1561. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1562. dp_peer_find_by_id(soc, peer_id);
  1563. if (!peer) {
  1564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1565. FL("Peer Invalid"));
  1566. return QDF_STATUS_E_INVAL;
  1567. }
  1568. if (pdev->am_copy_mode) {
  1569. if ((pdev->am_copy_id.tx_ppdu_id == ppdu_id) &&
  1570. (pdev->am_copy_id.tx_peer_id == peer_id)) {
  1571. return QDF_STATUS_E_INVAL;
  1572. }
  1573. pdev->am_copy_id.tx_ppdu_id = ppdu_id;
  1574. pdev->am_copy_id.tx_peer_id = peer_id;
  1575. }
  1576. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1578. FL("No headroom"));
  1579. return QDF_STATUS_E_NOMEM;
  1580. }
  1581. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1582. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1583. IEEE80211_ADDR_LEN);
  1584. ppdu_hdr->ppdu_id = ppdu_id;
  1585. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1586. IEEE80211_ADDR_LEN);
  1587. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1588. netbuf, peer_id,
  1589. WDI_NO_VAL, pdev->pdev_id);
  1590. return QDF_STATUS_SUCCESS;
  1591. }
  1592. #else
  1593. static QDF_STATUS
  1594. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1595. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1596. {
  1597. return QDF_STATUS_E_NOSUPPORT;
  1598. }
  1599. #endif
  1600. /**
  1601. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1602. * @soc: Soc handle
  1603. * @desc: software Tx descriptor to be processed
  1604. *
  1605. * Return: none
  1606. */
  1607. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1608. struct dp_tx_desc_s *desc)
  1609. {
  1610. struct dp_vdev *vdev = desc->vdev;
  1611. qdf_nbuf_t nbuf = desc->nbuf;
  1612. struct hal_tx_completion_status ts = {0};
  1613. if (desc)
  1614. hal_tx_comp_get_status(&desc->comp, &ts);
  1615. /* If it is TDLS mgmt, don't unmap or free the frame */
  1616. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1617. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1618. /* 0 : MSDU buffer, 1 : MLE */
  1619. if (desc->msdu_ext_desc) {
  1620. /* TSO free */
  1621. if (hal_tx_ext_desc_get_tso_enable(
  1622. desc->msdu_ext_desc->vaddr)) {
  1623. /* If remaining number of segment is 0
  1624. * actual TSO may unmap and free */
  1625. if (!DP_DESC_NUM_FRAG(desc)) {
  1626. qdf_nbuf_unmap(soc->osdev, nbuf,
  1627. QDF_DMA_TO_DEVICE);
  1628. qdf_nbuf_free(nbuf);
  1629. return;
  1630. }
  1631. }
  1632. }
  1633. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1634. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1635. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1636. if (dp_send_compl_to_stack(soc, desc->pdev, ts.peer_id,
  1637. ts.ppdu_id, nbuf) == QDF_STATUS_SUCCESS)
  1638. return;
  1639. if (!vdev->mesh_vdev) {
  1640. qdf_nbuf_free(nbuf);
  1641. } else {
  1642. vdev->osif_tx_free_ext((nbuf));
  1643. }
  1644. }
  1645. /**
  1646. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1647. * @vdev: pointer to dp dev handler
  1648. * @status : Tx completion status from HTT descriptor
  1649. *
  1650. * Handles MEC notify event sent from fw to Host
  1651. *
  1652. * Return: none
  1653. */
  1654. #ifdef FEATURE_WDS
  1655. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1656. {
  1657. struct dp_soc *soc;
  1658. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1659. struct dp_peer *peer;
  1660. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1661. soc = vdev->pdev->soc;
  1662. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1663. peer = TAILQ_FIRST(&vdev->peer_list);
  1664. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1665. if (!peer) {
  1666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1667. FL("peer is NULL"));
  1668. return;
  1669. }
  1670. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1671. "%s Tx MEC Handler\n",
  1672. __func__);
  1673. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1674. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1675. status[(DP_MAC_ADDR_LEN - 2) + i];
  1676. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1677. !dp_peer_add_ast(soc, peer, mac_addr, 2)) {
  1678. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1679. vdev->pdev->osif_pdev,
  1680. mac_addr,
  1681. vdev->mac_addr.raw,
  1682. flags);
  1683. }
  1684. }
  1685. #else
  1686. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1687. {
  1688. }
  1689. #endif
  1690. /**
  1691. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1692. * @tx_desc: software descriptor head pointer
  1693. * @status : Tx completion status from HTT descriptor
  1694. *
  1695. * This function will process HTT Tx indication messages from Target
  1696. *
  1697. * Return: none
  1698. */
  1699. static
  1700. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1701. {
  1702. uint8_t tx_status;
  1703. struct dp_pdev *pdev;
  1704. struct dp_vdev *vdev;
  1705. struct dp_soc *soc;
  1706. uint32_t *htt_status_word = (uint32_t *) status;
  1707. qdf_assert(tx_desc->pdev);
  1708. pdev = tx_desc->pdev;
  1709. vdev = tx_desc->vdev;
  1710. soc = pdev->soc;
  1711. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1712. switch (tx_status) {
  1713. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1714. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1715. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1716. {
  1717. dp_tx_comp_free_buf(soc, tx_desc);
  1718. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1719. break;
  1720. }
  1721. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1722. {
  1723. dp_tx_reinject_handler(tx_desc, status);
  1724. break;
  1725. }
  1726. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1727. {
  1728. dp_tx_inspect_handler(tx_desc, status);
  1729. break;
  1730. }
  1731. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1732. {
  1733. dp_tx_mec_handler(vdev, status);
  1734. break;
  1735. }
  1736. default:
  1737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1738. "%s Invalid HTT tx_status %d\n",
  1739. __func__, tx_status);
  1740. break;
  1741. }
  1742. }
  1743. #ifdef MESH_MODE_SUPPORT
  1744. /**
  1745. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1746. * in mesh meta header
  1747. * @tx_desc: software descriptor head pointer
  1748. * @ts: pointer to tx completion stats
  1749. * Return: none
  1750. */
  1751. static
  1752. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1753. struct hal_tx_completion_status *ts)
  1754. {
  1755. struct meta_hdr_s *mhdr;
  1756. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1757. if (!tx_desc->msdu_ext_desc) {
  1758. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1759. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1760. "netbuf %pK offset %d\n",
  1761. netbuf, tx_desc->pkt_offset);
  1762. return;
  1763. }
  1764. }
  1765. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1767. "netbuf %pK offset %d\n", netbuf,
  1768. sizeof(struct meta_hdr_s));
  1769. return;
  1770. }
  1771. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1772. mhdr->rssi = ts->ack_frame_rssi;
  1773. mhdr->channel = tx_desc->pdev->operating_channel;
  1774. }
  1775. #else
  1776. static
  1777. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1778. struct hal_tx_completion_status *ts)
  1779. {
  1780. }
  1781. #endif
  1782. /**
  1783. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1784. * @peer: Handle to DP peer
  1785. * @ts: pointer to HAL Tx completion stats
  1786. * @length: MSDU length
  1787. *
  1788. * Return: None
  1789. */
  1790. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1791. struct hal_tx_completion_status *ts, uint32_t length)
  1792. {
  1793. struct dp_pdev *pdev = peer->vdev->pdev;
  1794. struct dp_soc *soc = pdev->soc;
  1795. uint8_t mcs, pkt_type;
  1796. mcs = ts->mcs;
  1797. pkt_type = ts->pkt_type;
  1798. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1799. return;
  1800. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1801. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1802. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1803. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1804. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1805. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1806. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1807. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1808. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1809. return;
  1810. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1811. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1812. if (!(soc->process_tx_status))
  1813. return;
  1814. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1815. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  1816. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1817. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  1818. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1819. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1820. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1821. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1822. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1823. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1824. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1825. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1826. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1827. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1828. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1829. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1830. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1831. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1832. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1833. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1834. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1835. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1836. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1837. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1838. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1839. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1840. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1841. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1842. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1843. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1844. &peer->stats, ts->peer_id,
  1845. UPDATE_PEER_STATS);
  1846. }
  1847. }
  1848. /**
  1849. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1850. * @tx_desc: software descriptor head pointer
  1851. * @length: packet length
  1852. *
  1853. * Return: none
  1854. */
  1855. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1856. uint32_t length)
  1857. {
  1858. struct hal_tx_completion_status ts;
  1859. struct dp_soc *soc = NULL;
  1860. struct dp_vdev *vdev = tx_desc->vdev;
  1861. struct dp_peer *peer = NULL;
  1862. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1863. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1864. "-------------------- \n"
  1865. "Tx Completion Stats: \n"
  1866. "-------------------- \n"
  1867. "ack_frame_rssi = %d \n"
  1868. "first_msdu = %d \n"
  1869. "last_msdu = %d \n"
  1870. "msdu_part_of_amsdu = %d \n"
  1871. "rate_stats valid = %d \n"
  1872. "bw = %d \n"
  1873. "pkt_type = %d \n"
  1874. "stbc = %d \n"
  1875. "ldpc = %d \n"
  1876. "sgi = %d \n"
  1877. "mcs = %d \n"
  1878. "ofdma = %d \n"
  1879. "tones_in_ru = %d \n"
  1880. "tsf = %d \n"
  1881. "ppdu_id = %d \n"
  1882. "transmit_cnt = %d \n"
  1883. "tid = %d \n"
  1884. "peer_id = %d \n",
  1885. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1886. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1887. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1888. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1889. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1890. ts.peer_id);
  1891. if (!vdev) {
  1892. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1893. "invalid vdev");
  1894. goto out;
  1895. }
  1896. soc = vdev->pdev->soc;
  1897. /* Update SoC level stats */
  1898. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  1899. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  1900. /* Update per-packet stats */
  1901. if (qdf_unlikely(vdev->mesh_vdev))
  1902. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1903. /* Update peer level stats */
  1904. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1905. if (!peer) {
  1906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1907. "invalid peer");
  1908. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1909. goto out;
  1910. }
  1911. dp_tx_update_peer_stats(peer, &ts, length);
  1912. out:
  1913. return;
  1914. }
  1915. /**
  1916. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1917. * @soc: core txrx main context
  1918. * @comp_head: software descriptor head pointer
  1919. *
  1920. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1921. * and release the software descriptors after processing is complete
  1922. *
  1923. * Return: none
  1924. */
  1925. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1926. struct dp_tx_desc_s *comp_head)
  1927. {
  1928. struct dp_tx_desc_s *desc;
  1929. struct dp_tx_desc_s *next;
  1930. struct hal_tx_completion_status ts = {0};
  1931. uint32_t length;
  1932. struct dp_peer *peer;
  1933. DP_HIST_INIT();
  1934. desc = comp_head;
  1935. while (desc) {
  1936. hal_tx_comp_get_status(&desc->comp, &ts);
  1937. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1938. length = qdf_nbuf_len(desc->nbuf);
  1939. /* Process Tx status in descriptor */
  1940. if (soc->process_tx_status ||
  1941. (desc->vdev && desc->vdev->mesh_vdev))
  1942. dp_tx_comp_process_tx_status(desc, length);
  1943. dp_tx_comp_free_buf(soc, desc);
  1944. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1945. next = desc->next;
  1946. dp_tx_desc_release(desc, desc->pool_id);
  1947. desc = next;
  1948. }
  1949. DP_TX_HIST_STATS_PER_PDEV();
  1950. }
  1951. /**
  1952. * dp_tx_comp_handler() - Tx completion handler
  1953. * @soc: core txrx main context
  1954. * @ring_id: completion ring id
  1955. * @quota: No. of packets/descriptors that can be serviced in one loop
  1956. *
  1957. * This function will collect hardware release ring element contents and
  1958. * handle descriptor contents. Based on contents, free packet or handle error
  1959. * conditions
  1960. *
  1961. * Return: none
  1962. */
  1963. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  1964. {
  1965. void *tx_comp_hal_desc;
  1966. uint8_t buffer_src;
  1967. uint8_t pool_id;
  1968. uint32_t tx_desc_id;
  1969. struct dp_tx_desc_s *tx_desc = NULL;
  1970. struct dp_tx_desc_s *head_desc = NULL;
  1971. struct dp_tx_desc_s *tail_desc = NULL;
  1972. uint32_t num_processed;
  1973. uint32_t count;
  1974. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1975. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1976. "%s %d : HAL RING Access Failed -- %pK\n",
  1977. __func__, __LINE__, hal_srng);
  1978. return 0;
  1979. }
  1980. num_processed = 0;
  1981. count = 0;
  1982. /* Find head descriptor from completion ring */
  1983. while (qdf_likely(tx_comp_hal_desc =
  1984. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1985. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1986. /* If this buffer was not released by TQM or FW, then it is not
  1987. * Tx completion indication, assert */
  1988. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1989. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP,
  1991. QDF_TRACE_LEVEL_FATAL,
  1992. "Tx comp release_src != TQM | FW");
  1993. qdf_assert_always(0);
  1994. }
  1995. /* Get descriptor id */
  1996. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1997. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1998. DP_TX_DESC_ID_POOL_OS;
  1999. /* Pool ID is out of limit. Error */
  2000. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2001. soc->wlan_cfg_ctx)) {
  2002. QDF_TRACE(QDF_MODULE_ID_DP,
  2003. QDF_TRACE_LEVEL_FATAL,
  2004. "Tx Comp pool id %d not valid",
  2005. pool_id);
  2006. qdf_assert_always(0);
  2007. }
  2008. /* Find Tx descriptor */
  2009. tx_desc = dp_tx_desc_find(soc, pool_id,
  2010. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2011. DP_TX_DESC_ID_PAGE_OS,
  2012. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2013. DP_TX_DESC_ID_OFFSET_OS);
  2014. /* Pool id is not matching. Error */
  2015. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  2016. QDF_TRACE(QDF_MODULE_ID_DP,
  2017. QDF_TRACE_LEVEL_FATAL,
  2018. "Tx Comp pool id %d not matched %d",
  2019. pool_id, tx_desc->pool_id);
  2020. qdf_assert_always(0);
  2021. }
  2022. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2023. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2024. QDF_TRACE(QDF_MODULE_ID_DP,
  2025. QDF_TRACE_LEVEL_FATAL,
  2026. "Txdesc invalid, flgs = %x,id = %d",
  2027. tx_desc->flags, tx_desc_id);
  2028. qdf_assert_always(0);
  2029. }
  2030. /*
  2031. * If the release source is FW, process the HTT status
  2032. */
  2033. if (qdf_unlikely(buffer_src ==
  2034. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2035. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2036. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2037. htt_tx_status);
  2038. dp_tx_process_htt_completion(tx_desc,
  2039. htt_tx_status);
  2040. } else {
  2041. /* First ring descriptor on the cycle */
  2042. if (!head_desc) {
  2043. head_desc = tx_desc;
  2044. tail_desc = tx_desc;
  2045. }
  2046. tail_desc->next = tx_desc;
  2047. tx_desc->next = NULL;
  2048. tail_desc = tx_desc;
  2049. /* Collect hw completion contents */
  2050. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2051. &tx_desc->comp, soc->process_tx_status);
  2052. }
  2053. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2054. /* Decrement PM usage count if the packet has been sent.*/
  2055. hif_pm_runtime_put(soc->hif_handle);
  2056. /*
  2057. * Processed packet count is more than given quota
  2058. * stop to processing
  2059. */
  2060. if ((num_processed >= quota))
  2061. break;
  2062. count++;
  2063. }
  2064. hal_srng_access_end(soc->hal_soc, hal_srng);
  2065. /* Process the reaped descriptors */
  2066. if (head_desc)
  2067. dp_tx_comp_process_desc(soc, head_desc);
  2068. return num_processed;
  2069. }
  2070. #ifdef CONVERGED_TDLS_ENABLE
  2071. /**
  2072. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2073. *
  2074. * @data_vdev - which vdev should transmit the tx data frames
  2075. * @tx_spec - what non-standard handling to apply to the tx data frames
  2076. * @msdu_list - NULL-terminated list of tx MSDUs
  2077. *
  2078. * Return: NULL on success,
  2079. * nbuf when it fails to send
  2080. */
  2081. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2082. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2083. {
  2084. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2085. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2086. vdev->is_tdls_frame = true;
  2087. return dp_tx_send(vdev_handle, msdu_list);
  2088. }
  2089. #endif
  2090. /**
  2091. * dp_tx_vdev_attach() - attach vdev to dp tx
  2092. * @vdev: virtual device instance
  2093. *
  2094. * Return: QDF_STATUS_SUCCESS: success
  2095. * QDF_STATUS_E_RESOURCES: Error return
  2096. */
  2097. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2098. {
  2099. /*
  2100. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2101. */
  2102. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2103. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2104. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2105. vdev->vdev_id);
  2106. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2107. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2108. /*
  2109. * Set HTT Extension Valid bit to 0 by default
  2110. */
  2111. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2112. dp_tx_vdev_update_search_flags(vdev);
  2113. return QDF_STATUS_SUCCESS;
  2114. }
  2115. /**
  2116. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2117. * @vdev: virtual device instance
  2118. *
  2119. * Return: void
  2120. *
  2121. */
  2122. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2123. {
  2124. /*
  2125. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2126. * for TDLS link
  2127. *
  2128. * Enable AddrY (SA based search) only for non-WDS STA and
  2129. * ProxySTA VAP modes.
  2130. *
  2131. * In all other VAP modes, only DA based search should be
  2132. * enabled
  2133. */
  2134. if (vdev->opmode == wlan_op_mode_sta &&
  2135. vdev->tdls_link_connected)
  2136. vdev->hal_desc_addr_search_flags =
  2137. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2138. else if ((vdev->opmode == wlan_op_mode_sta &&
  2139. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2140. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2141. else
  2142. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2143. }
  2144. /**
  2145. * dp_tx_vdev_detach() - detach vdev from dp tx
  2146. * @vdev: virtual device instance
  2147. *
  2148. * Return: QDF_STATUS_SUCCESS: success
  2149. * QDF_STATUS_E_RESOURCES: Error return
  2150. */
  2151. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2152. {
  2153. return QDF_STATUS_SUCCESS;
  2154. }
  2155. /**
  2156. * dp_tx_pdev_attach() - attach pdev to dp tx
  2157. * @pdev: physical device instance
  2158. *
  2159. * Return: QDF_STATUS_SUCCESS: success
  2160. * QDF_STATUS_E_RESOURCES: Error return
  2161. */
  2162. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2163. {
  2164. struct dp_soc *soc = pdev->soc;
  2165. /* Initialize Flow control counters */
  2166. qdf_atomic_init(&pdev->num_tx_exception);
  2167. qdf_atomic_init(&pdev->num_tx_outstanding);
  2168. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2169. /* Initialize descriptors in TCL Ring */
  2170. hal_tx_init_data_ring(soc->hal_soc,
  2171. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2172. }
  2173. return QDF_STATUS_SUCCESS;
  2174. }
  2175. /**
  2176. * dp_tx_pdev_detach() - detach pdev from dp tx
  2177. * @pdev: physical device instance
  2178. *
  2179. * Return: QDF_STATUS_SUCCESS: success
  2180. * QDF_STATUS_E_RESOURCES: Error return
  2181. */
  2182. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2183. {
  2184. /* What should do here? */
  2185. return QDF_STATUS_SUCCESS;
  2186. }
  2187. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2188. /* Pools will be allocated dynamically */
  2189. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2190. int num_desc)
  2191. {
  2192. uint8_t i;
  2193. for (i = 0; i < num_pool; i++) {
  2194. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2195. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2196. }
  2197. return 0;
  2198. }
  2199. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2200. {
  2201. uint8_t i;
  2202. for (i = 0; i < num_pool; i++)
  2203. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2204. }
  2205. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2206. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2207. int num_desc)
  2208. {
  2209. uint8_t i;
  2210. /* Allocate software Tx descriptor pools */
  2211. for (i = 0; i < num_pool; i++) {
  2212. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2214. "%s Tx Desc Pool alloc %d failed %pK\n",
  2215. __func__, i, soc);
  2216. return ENOMEM;
  2217. }
  2218. }
  2219. return 0;
  2220. }
  2221. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2222. {
  2223. uint8_t i;
  2224. for (i = 0; i < num_pool; i++) {
  2225. if (dp_tx_desc_pool_free(soc, i)) {
  2226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2227. "%s Tx Desc Pool Free failed\n", __func__);
  2228. }
  2229. }
  2230. }
  2231. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2232. /**
  2233. * dp_tx_soc_detach() - detach soc from dp tx
  2234. * @soc: core txrx main context
  2235. *
  2236. * This function will detach dp tx into main device context
  2237. * will free dp tx resource and initialize resources
  2238. *
  2239. * Return: QDF_STATUS_SUCCESS: success
  2240. * QDF_STATUS_E_RESOURCES: Error return
  2241. */
  2242. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2243. {
  2244. uint8_t num_pool;
  2245. uint16_t num_desc;
  2246. uint16_t num_ext_desc;
  2247. uint8_t i;
  2248. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2249. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2250. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2251. dp_tx_flow_control_deinit(soc);
  2252. dp_tx_delete_static_pools(soc, num_pool);
  2253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2254. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2255. __func__, num_pool, num_desc);
  2256. for (i = 0; i < num_pool; i++) {
  2257. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2258. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2259. "%s Tx Ext Desc Pool Free failed\n",
  2260. __func__);
  2261. return QDF_STATUS_E_RESOURCES;
  2262. }
  2263. }
  2264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2265. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2266. __func__, num_pool, num_ext_desc);
  2267. for (i = 0; i < num_pool; i++) {
  2268. dp_tx_tso_desc_pool_free(soc, i);
  2269. }
  2270. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2271. "%s TSO Desc Pool %d Free descs = %d\n",
  2272. __func__, num_pool, num_desc);
  2273. for (i = 0; i < num_pool; i++)
  2274. dp_tx_tso_num_seg_pool_free(soc, i);
  2275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2276. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2277. __func__, num_pool, num_desc);
  2278. return QDF_STATUS_SUCCESS;
  2279. }
  2280. /**
  2281. * dp_tx_soc_attach() - attach soc to dp tx
  2282. * @soc: core txrx main context
  2283. *
  2284. * This function will attach dp tx into main device context
  2285. * will allocate dp tx resource and initialize resources
  2286. *
  2287. * Return: QDF_STATUS_SUCCESS: success
  2288. * QDF_STATUS_E_RESOURCES: Error return
  2289. */
  2290. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2291. {
  2292. uint8_t i;
  2293. uint8_t num_pool;
  2294. uint32_t num_desc;
  2295. uint32_t num_ext_desc;
  2296. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2297. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2298. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2299. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2300. goto fail;
  2301. dp_tx_flow_control_init(soc);
  2302. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2303. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2304. __func__, num_pool, num_desc);
  2305. /* Allocate extension tx descriptor pools */
  2306. for (i = 0; i < num_pool; i++) {
  2307. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2308. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2309. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2310. i, soc);
  2311. goto fail;
  2312. }
  2313. }
  2314. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2315. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2316. __func__, num_pool, num_ext_desc);
  2317. for (i = 0; i < num_pool; i++) {
  2318. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2319. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2320. "TSO Desc Pool alloc %d failed %pK\n",
  2321. i, soc);
  2322. goto fail;
  2323. }
  2324. }
  2325. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2326. "%s TSO Desc Alloc %d, descs = %d\n",
  2327. __func__, num_pool, num_desc);
  2328. for (i = 0; i < num_pool; i++) {
  2329. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2331. "TSO Num of seg Pool alloc %d failed %pK\n",
  2332. i, soc);
  2333. goto fail;
  2334. }
  2335. }
  2336. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2337. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2338. __func__, num_pool, num_desc);
  2339. /* Initialize descriptors in TCL Rings */
  2340. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2341. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2342. hal_tx_init_data_ring(soc->hal_soc,
  2343. soc->tcl_data_ring[i].hal_srng);
  2344. }
  2345. }
  2346. /*
  2347. * todo - Add a runtime config option to enable this.
  2348. */
  2349. /*
  2350. * Due to multiple issues on NPR EMU, enable it selectively
  2351. * only for NPR EMU, should be removed, once NPR platforms
  2352. * are stable.
  2353. */
  2354. soc->process_tx_status = 0;
  2355. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2356. "%s HAL Tx init Success\n", __func__);
  2357. return QDF_STATUS_SUCCESS;
  2358. fail:
  2359. /* Detach will take care of freeing only allocated resources */
  2360. dp_tx_soc_detach(soc);
  2361. return QDF_STATUS_E_RESOURCES;
  2362. }
  2363. /*
  2364. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2365. * pdev: pointer to DP PDEV structure
  2366. * seg_info_head: Pointer to the head of list
  2367. *
  2368. * return: void
  2369. */
  2370. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2371. struct dp_tx_seg_info_s *seg_info_head)
  2372. {
  2373. struct dp_tx_me_buf_t *mc_uc_buf;
  2374. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2375. qdf_nbuf_t nbuf = NULL;
  2376. uint64_t phy_addr;
  2377. while (seg_info_head) {
  2378. nbuf = seg_info_head->nbuf;
  2379. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2380. seg_info_new->frags[0].vaddr;
  2381. phy_addr = seg_info_head->frags[0].paddr_hi;
  2382. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2383. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2384. phy_addr,
  2385. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2386. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2387. qdf_nbuf_free(nbuf);
  2388. seg_info_new = seg_info_head;
  2389. seg_info_head = seg_info_head->next;
  2390. qdf_mem_free(seg_info_new);
  2391. }
  2392. }
  2393. /**
  2394. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2395. * @vdev: DP VDEV handle
  2396. * @nbuf: Multicast nbuf
  2397. * @newmac: Table of the clients to which packets have to be sent
  2398. * @new_mac_cnt: No of clients
  2399. *
  2400. * return: no of converted packets
  2401. */
  2402. uint16_t
  2403. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2404. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2405. {
  2406. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2407. struct dp_pdev *pdev = vdev->pdev;
  2408. struct ether_header *eh;
  2409. uint8_t *data;
  2410. uint16_t len;
  2411. /* reference to frame dst addr */
  2412. uint8_t *dstmac;
  2413. /* copy of original frame src addr */
  2414. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2415. /* local index into newmac */
  2416. uint8_t new_mac_idx = 0;
  2417. struct dp_tx_me_buf_t *mc_uc_buf;
  2418. qdf_nbuf_t nbuf_clone;
  2419. struct dp_tx_msdu_info_s msdu_info;
  2420. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2421. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2422. struct dp_tx_seg_info_s *seg_info_new;
  2423. struct dp_tx_frag_info_s data_frag;
  2424. qdf_dma_addr_t paddr_data;
  2425. qdf_dma_addr_t paddr_mcbuf = 0;
  2426. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2427. QDF_STATUS status;
  2428. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2429. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2430. eh = (struct ether_header *) nbuf;
  2431. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2432. len = qdf_nbuf_len(nbuf);
  2433. data = qdf_nbuf_data(nbuf);
  2434. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2435. QDF_DMA_TO_DEVICE);
  2436. if (status) {
  2437. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2438. "Mapping failure Error:%d", status);
  2439. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2440. return 0;
  2441. }
  2442. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2443. /*preparing data fragment*/
  2444. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2445. data_frag.paddr_lo = (uint32_t)paddr_data;
  2446. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2447. data_frag.len = len - DP_MAC_ADDR_LEN;
  2448. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2449. dstmac = newmac[new_mac_idx];
  2450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2451. "added mac addr (%pM)", dstmac);
  2452. /* Check for NULL Mac Address */
  2453. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2454. continue;
  2455. /* frame to self mac. skip */
  2456. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2457. continue;
  2458. /*
  2459. * TODO: optimize to avoid malloc in per-packet path
  2460. * For eg. seg_pool can be made part of vdev structure
  2461. */
  2462. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2463. if (!seg_info_new) {
  2464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2465. "alloc failed");
  2466. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2467. goto fail_seg_alloc;
  2468. }
  2469. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2470. if (mc_uc_buf == NULL)
  2471. goto fail_buf_alloc;
  2472. /*
  2473. * TODO: Check if we need to clone the nbuf
  2474. * Or can we just use the reference for all cases
  2475. */
  2476. if (new_mac_idx < (new_mac_cnt - 1)) {
  2477. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2478. if (nbuf_clone == NULL) {
  2479. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2480. goto fail_clone;
  2481. }
  2482. } else {
  2483. /*
  2484. * Update the ref
  2485. * to account for frame sent without cloning
  2486. */
  2487. qdf_nbuf_ref(nbuf);
  2488. nbuf_clone = nbuf;
  2489. }
  2490. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2491. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2492. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2493. &paddr_mcbuf);
  2494. if (status) {
  2495. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2496. "Mapping failure Error:%d", status);
  2497. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2498. goto fail_map;
  2499. }
  2500. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2501. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2502. seg_info_new->frags[0].paddr_hi =
  2503. ((uint64_t) paddr_mcbuf >> 32);
  2504. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2505. seg_info_new->frags[1] = data_frag;
  2506. seg_info_new->nbuf = nbuf_clone;
  2507. seg_info_new->frag_cnt = 2;
  2508. seg_info_new->total_len = len;
  2509. seg_info_new->next = NULL;
  2510. if (seg_info_head == NULL)
  2511. seg_info_head = seg_info_new;
  2512. else
  2513. seg_info_tail->next = seg_info_new;
  2514. seg_info_tail = seg_info_new;
  2515. }
  2516. if (!seg_info_head)
  2517. return 0;
  2518. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2519. msdu_info.num_seg = new_mac_cnt;
  2520. msdu_info.frm_type = dp_tx_frm_me;
  2521. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2522. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2523. while (seg_info_head->next) {
  2524. seg_info_new = seg_info_head;
  2525. seg_info_head = seg_info_head->next;
  2526. qdf_mem_free(seg_info_new);
  2527. }
  2528. qdf_mem_free(seg_info_head);
  2529. return new_mac_cnt;
  2530. fail_map:
  2531. qdf_nbuf_free(nbuf_clone);
  2532. fail_clone:
  2533. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2534. fail_buf_alloc:
  2535. qdf_mem_free(seg_info_new);
  2536. fail_seg_alloc:
  2537. dp_tx_me_mem_free(pdev, seg_info_head);
  2538. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2539. return 0;
  2540. }