cam_packet_util.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/slab.h>
  7. #include "cam_mem_mgr.h"
  8. #include "cam_packet_util.h"
  9. #include "cam_debug_util.h"
  10. #define CAM_UNIQUE_SRC_HDL_MAX 50
  11. struct cam_patch_unique_src_buf_tbl {
  12. int32_t hdl;
  13. dma_addr_t iova;
  14. size_t buf_size;
  15. };
  16. int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr,
  17. size_t *len)
  18. {
  19. int rc = 0;
  20. uintptr_t kmd_buf_addr = 0;
  21. rc = cam_mem_get_cpu_buf(handle, &kmd_buf_addr, len);
  22. if (rc) {
  23. CAM_ERR(CAM_UTIL, "Unable to get the virtual address %d", rc);
  24. } else {
  25. if (kmd_buf_addr && *len) {
  26. *buf_addr = (uint32_t *)kmd_buf_addr;
  27. } else {
  28. CAM_ERR(CAM_UTIL, "Invalid addr and length :%zd", *len);
  29. rc = -ENOMEM;
  30. }
  31. }
  32. return rc;
  33. }
  34. int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc)
  35. {
  36. if ((cmd_desc->length > cmd_desc->size) ||
  37. (cmd_desc->mem_handle <= 0)) {
  38. CAM_ERR(CAM_UTIL, "invalid cmd arg %d %d %d %d",
  39. cmd_desc->offset, cmd_desc->length,
  40. cmd_desc->mem_handle, cmd_desc->size);
  41. return -EINVAL;
  42. }
  43. return 0;
  44. }
  45. int cam_packet_util_validate_packet(struct cam_packet *packet,
  46. size_t remain_len)
  47. {
  48. size_t sum_cmd_desc = 0;
  49. size_t sum_io_cfgs = 0;
  50. size_t sum_patch_desc = 0;
  51. size_t pkt_wo_payload = 0;
  52. if (!packet)
  53. return -EINVAL;
  54. if ((size_t)packet->header.size > remain_len) {
  55. CAM_ERR(CAM_UTIL,
  56. "Invalid packet size: %zu, CPU buf length: %zu",
  57. (size_t)packet->header.size, remain_len);
  58. return -EINVAL;
  59. }
  60. CAM_DBG(CAM_UTIL, "num cmd buf:%d num of io config:%d kmd buf index:%d",
  61. packet->num_cmd_buf, packet->num_io_configs,
  62. packet->kmd_cmd_buf_index);
  63. sum_cmd_desc = packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc);
  64. sum_io_cfgs = packet->num_io_configs * sizeof(struct cam_buf_io_cfg);
  65. sum_patch_desc = packet->num_patches * sizeof(struct cam_patch_desc);
  66. pkt_wo_payload = offsetof(struct cam_packet, payload);
  67. if ((!packet->header.size) ||
  68. ((pkt_wo_payload + (size_t)packet->cmd_buf_offset +
  69. sum_cmd_desc) > (size_t)packet->header.size) ||
  70. ((pkt_wo_payload + (size_t)packet->io_configs_offset +
  71. sum_io_cfgs) > (size_t)packet->header.size) ||
  72. ((pkt_wo_payload + (size_t)packet->patch_offset +
  73. sum_patch_desc) > (size_t)packet->header.size)) {
  74. CAM_ERR(CAM_UTIL, "params not within mem len:%zu %zu %zu %zu",
  75. (size_t)packet->header.size, sum_cmd_desc,
  76. sum_io_cfgs, sum_patch_desc);
  77. return -EINVAL;
  78. }
  79. return 0;
  80. }
  81. int cam_packet_util_get_kmd_buffer(struct cam_packet *packet,
  82. struct cam_kmd_buf_info *kmd_buf)
  83. {
  84. int rc = 0;
  85. size_t len = 0;
  86. size_t remain_len = 0;
  87. struct cam_cmd_buf_desc *cmd_desc;
  88. uint32_t *cpu_addr;
  89. if (!packet || !kmd_buf) {
  90. CAM_ERR(CAM_UTIL, "Invalid arg %pK %pK", packet, kmd_buf);
  91. return -EINVAL;
  92. }
  93. if ((packet->kmd_cmd_buf_index < 0) ||
  94. (packet->kmd_cmd_buf_index >= packet->num_cmd_buf)) {
  95. CAM_ERR(CAM_UTIL, "Invalid kmd buf index: %d",
  96. packet->kmd_cmd_buf_index);
  97. return -EINVAL;
  98. }
  99. /* Take first command descriptor and add offset to it for kmd*/
  100. cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *)
  101. &packet->payload + packet->cmd_buf_offset);
  102. cmd_desc += packet->kmd_cmd_buf_index;
  103. rc = cam_packet_util_validate_cmd_desc(cmd_desc);
  104. if (rc)
  105. return rc;
  106. rc = cam_packet_util_get_cmd_mem_addr(cmd_desc->mem_handle, &cpu_addr,
  107. &len);
  108. if (rc)
  109. return rc;
  110. remain_len = len;
  111. if (((size_t)cmd_desc->offset >= len) ||
  112. ((size_t)cmd_desc->size > (len - (size_t)cmd_desc->offset))) {
  113. CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d",
  114. len, cmd_desc->size);
  115. return -EINVAL;
  116. }
  117. remain_len -= (size_t)cmd_desc->offset;
  118. if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) {
  119. CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu",
  120. (size_t)packet->kmd_cmd_buf_offset);
  121. return -EINVAL;
  122. }
  123. cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4);
  124. CAM_DBG(CAM_UTIL, "total size %d, cmd size: %d, KMD buffer size: %d",
  125. cmd_desc->size, cmd_desc->length,
  126. cmd_desc->size - cmd_desc->length);
  127. CAM_DBG(CAM_UTIL, "hdl 0x%x, cmd offset %d, kmd offset %d, addr 0x%pK",
  128. cmd_desc->mem_handle, cmd_desc->offset,
  129. packet->kmd_cmd_buf_offset, cpu_addr);
  130. kmd_buf->cpu_addr = cpu_addr;
  131. kmd_buf->handle = cmd_desc->mem_handle;
  132. kmd_buf->offset = cmd_desc->offset + packet->kmd_cmd_buf_offset;
  133. kmd_buf->size = cmd_desc->size - cmd_desc->length;
  134. kmd_buf->used_bytes = 0;
  135. return rc;
  136. }
  137. void cam_packet_dump_patch_info(struct cam_packet *packet,
  138. int32_t iommu_hdl, int32_t sec_mmu_hdl)
  139. {
  140. struct cam_patch_desc *patch_desc = NULL;
  141. dma_addr_t iova_addr;
  142. size_t dst_buf_len;
  143. size_t src_buf_size;
  144. int i, rc = 0;
  145. int32_t hdl;
  146. uintptr_t cpu_addr = 0;
  147. uint32_t *dst_cpu_addr;
  148. uint64_t value = 0;
  149. patch_desc = (struct cam_patch_desc *)
  150. ((uint32_t *) &packet->payload +
  151. packet->patch_offset/4);
  152. CAM_INFO(CAM_UTIL, "Total num of patches : %d",
  153. packet->num_patches);
  154. for (i = 0; i < packet->num_patches; i++) {
  155. hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ?
  156. sec_mmu_hdl : iommu_hdl;
  157. rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl,
  158. hdl, &iova_addr, &src_buf_size);
  159. if (rc < 0) {
  160. CAM_ERR(CAM_UTIL,
  161. "unable to get src buf address for hdl 0x%x",
  162. hdl);
  163. return;
  164. }
  165. rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
  166. &cpu_addr, &dst_buf_len);
  167. if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) {
  168. CAM_ERR(CAM_UTIL, "unable to get dst buf address");
  169. return;
  170. }
  171. dst_cpu_addr = (uint32_t *)cpu_addr;
  172. dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
  173. patch_desc[i].dst_offset);
  174. value = *((uint64_t *)dst_cpu_addr);
  175. CAM_INFO(CAM_UTIL,
  176. "i = %d src_buf 0x%llx src_hdl 0x%x src_buf_with_offset 0x%llx size 0x%llx dst %p dst_offset %u dst_hdl 0x%x value 0x%llx",
  177. i, iova_addr, patch_desc[i].src_buf_hdl,
  178. (iova_addr + patch_desc[i].src_offset),
  179. src_buf_size, dst_cpu_addr,
  180. patch_desc[i].dst_offset,
  181. patch_desc[i].dst_buf_hdl, value);
  182. if (!(*dst_cpu_addr))
  183. CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr);
  184. }
  185. }
  186. static int cam_packet_util_get_patch_iova(
  187. struct cam_patch_unique_src_buf_tbl *tbl,
  188. int32_t hdl, uint32_t buf_hdl, dma_addr_t *iova, size_t *buf_size)
  189. {
  190. int idx = 0;
  191. int rc = 0;
  192. size_t src_buf_size;
  193. dma_addr_t iova_addr;
  194. bool is_found = false;
  195. for (idx = 0; idx < CAM_UNIQUE_SRC_HDL_MAX; idx++) {
  196. if (buf_hdl == tbl[idx].hdl) {
  197. CAM_DBG(CAM_UTIL,
  198. "Matched entry for src_buf_hdl: 0x%x with src_hdl[%d]: 0x%x",
  199. buf_hdl, idx, tbl[idx].hdl);
  200. *iova = tbl[idx].iova;
  201. *buf_size = tbl[idx].buf_size;
  202. is_found = true;
  203. break;
  204. } else if ((tbl[idx].hdl == 0) || (tbl[idx].iova == 0)) {
  205. CAM_DBG(CAM_UTIL, "New src handle detected 0x%x",
  206. buf_hdl);
  207. is_found = false;
  208. break;
  209. }
  210. CAM_DBG(CAM_UTIL,
  211. "Index: %d is filled with differnt src_hdl: 0x%x",
  212. idx, buf_hdl);
  213. }
  214. if (!is_found) {
  215. CAM_DBG(CAM_UTIL, "src_hdl 0x%x not found in table entries",
  216. buf_hdl);
  217. rc = cam_mem_get_io_buf(buf_hdl, hdl,
  218. &iova_addr, &src_buf_size);
  219. if (rc < 0) {
  220. CAM_ERR(CAM_UTIL,
  221. "unable to get iova for src_hdl: 0x%x",
  222. buf_hdl);
  223. return rc;
  224. }
  225. /* Update the table entry with unique src buf handle */
  226. if (idx < CAM_UNIQUE_SRC_HDL_MAX && tbl[idx].hdl == 0) {
  227. tbl[idx].buf_size = src_buf_size;
  228. tbl[idx].iova = iova_addr;
  229. tbl[idx].hdl = buf_hdl;
  230. CAM_DBG(CAM_UTIL,
  231. "Updated table index: %d with src_buf_hdl: 0x%x",
  232. idx, tbl[idx].hdl);
  233. }
  234. *iova = iova_addr;
  235. *buf_size = src_buf_size;
  236. }
  237. return rc;
  238. }
  239. int cam_packet_util_process_patches(struct cam_packet *packet,
  240. int32_t iommu_hdl, int32_t sec_mmu_hdl)
  241. {
  242. struct cam_patch_desc *patch_desc = NULL;
  243. dma_addr_t iova_addr;
  244. uintptr_t cpu_addr = 0;
  245. uint32_t temp;
  246. uint32_t *dst_cpu_addr;
  247. uint32_t *src_buf_iova_addr;
  248. size_t dst_buf_len;
  249. size_t src_buf_size;
  250. int i = 0;
  251. int rc = 0;
  252. int32_t hdl;
  253. struct cam_patch_unique_src_buf_tbl
  254. tbl[CAM_UNIQUE_SRC_HDL_MAX];
  255. memset(tbl, 0, CAM_UNIQUE_SRC_HDL_MAX *
  256. sizeof(struct cam_patch_unique_src_buf_tbl));
  257. /* process patch descriptor */
  258. patch_desc = (struct cam_patch_desc *)
  259. ((uint32_t *) &packet->payload +
  260. packet->patch_offset/4);
  261. CAM_DBG(CAM_UTIL, "packet = %pK patch_desc = %pK size = %lu",
  262. (void *)packet, (void *)patch_desc,
  263. sizeof(struct cam_patch_desc));
  264. for (i = 0; i < packet->num_patches; i++) {
  265. hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ?
  266. sec_mmu_hdl : iommu_hdl;
  267. rc = cam_packet_util_get_patch_iova(&tbl[0], hdl,
  268. patch_desc[i].src_buf_hdl, &iova_addr, &src_buf_size);
  269. if (rc) {
  270. CAM_ERR(CAM_UTIL,
  271. "get_iova failed for patch[%d], src_buf_hdl: 0x%x: rc: %d",
  272. i, patch_desc[i].src_buf_hdl, rc);
  273. return rc;
  274. }
  275. if ((size_t)patch_desc[i].src_offset >= src_buf_size) {
  276. CAM_ERR(CAM_UTIL,
  277. "Invalid src buf patch offset: patch:src_offset: 0x%x, src_buf_size: %zu",
  278. patch_desc[i].src_offset, src_buf_size);
  279. return -EINVAL;
  280. }
  281. src_buf_iova_addr = (uint32_t *)iova_addr;
  282. temp = iova_addr;
  283. rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
  284. &cpu_addr, &dst_buf_len);
  285. if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) {
  286. CAM_ERR(CAM_UTIL, "unable to get dst buf address");
  287. return rc;
  288. }
  289. dst_cpu_addr = (uint32_t *)cpu_addr;
  290. CAM_DBG(CAM_UTIL, "i = %d patch info = %x %x %x %x", i,
  291. patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset,
  292. patch_desc[i].src_buf_hdl, patch_desc[i].src_offset);
  293. if ((dst_buf_len < sizeof(void *)) ||
  294. ((dst_buf_len - sizeof(void *)) <
  295. (size_t)patch_desc[i].dst_offset)) {
  296. CAM_ERR(CAM_UTIL,
  297. "Invalid dst buf patch offset");
  298. return -EINVAL;
  299. }
  300. dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
  301. patch_desc[i].dst_offset);
  302. temp += patch_desc[i].src_offset;
  303. *dst_cpu_addr = temp;
  304. CAM_DBG(CAM_UTIL,
  305. "patch is done for dst %pK with src %pK value %llx",
  306. dst_cpu_addr, src_buf_iova_addr,
  307. *((uint64_t *)dst_cpu_addr));
  308. }
  309. return rc;
  310. }
  311. int cam_packet_util_process_generic_cmd_buffer(
  312. struct cam_cmd_buf_desc *cmd_buf,
  313. cam_packet_generic_blob_handler blob_handler_cb, void *user_data)
  314. {
  315. int rc = 0;
  316. uintptr_t cpu_addr = 0;
  317. size_t buf_size;
  318. size_t remain_len = 0;
  319. uint32_t *blob_ptr;
  320. uint32_t blob_type, blob_size, blob_block_size, len_read;
  321. if (!cmd_buf || !blob_handler_cb) {
  322. CAM_ERR(CAM_UTIL, "Invalid args %pK %pK",
  323. cmd_buf, blob_handler_cb);
  324. return -EINVAL;
  325. }
  326. if (!cmd_buf->length || !cmd_buf->size) {
  327. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  328. cmd_buf->length, cmd_buf->size);
  329. return -EINVAL;
  330. }
  331. rc = cam_mem_get_cpu_buf(cmd_buf->mem_handle, &cpu_addr, &buf_size);
  332. if (rc || !cpu_addr || (buf_size == 0)) {
  333. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  334. rc, (void *)cpu_addr);
  335. return rc;
  336. }
  337. remain_len = buf_size;
  338. if ((buf_size < sizeof(uint32_t)) ||
  339. ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) {
  340. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  341. (size_t)cmd_buf->offset);
  342. return -EINVAL;
  343. }
  344. remain_len -= (size_t)cmd_buf->offset;
  345. if (remain_len < (size_t)cmd_buf->length) {
  346. CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu",
  347. (size_t)cmd_buf->length);
  348. return -EINVAL;
  349. }
  350. blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) +
  351. cmd_buf->offset);
  352. CAM_DBG(CAM_UTIL,
  353. "GenericCmdBuffer cpuaddr=%pK, blobptr=%pK, len=%d",
  354. (void *)cpu_addr, (void *)blob_ptr, cmd_buf->length);
  355. len_read = 0;
  356. while (len_read < cmd_buf->length) {
  357. blob_type =
  358. ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK) >>
  359. CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT;
  360. blob_size =
  361. ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK) >>
  362. CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT;
  363. blob_block_size = sizeof(uint32_t) +
  364. (((blob_size + sizeof(uint32_t) - 1) /
  365. sizeof(uint32_t)) * sizeof(uint32_t));
  366. CAM_DBG(CAM_UTIL,
  367. "Blob type=%d size=%d block_size=%d len_read=%d total=%d",
  368. blob_type, blob_size, blob_block_size, len_read,
  369. cmd_buf->length);
  370. if (len_read + blob_block_size > cmd_buf->length) {
  371. CAM_ERR(CAM_UTIL, "Invalid Blob %d %d %d %d",
  372. blob_type, blob_size, len_read,
  373. cmd_buf->length);
  374. rc = -EINVAL;
  375. goto end;
  376. }
  377. len_read += blob_block_size;
  378. rc = blob_handler_cb(user_data, blob_type, blob_size,
  379. (uint8_t *)(blob_ptr + 1));
  380. if (rc) {
  381. CAM_ERR(CAM_UTIL, "Error in handling blob type %d %d",
  382. blob_type, blob_size);
  383. goto end;
  384. }
  385. blob_ptr += (blob_block_size / sizeof(uint32_t));
  386. }
  387. end:
  388. return rc;
  389. }