cvp_hfi.c 139 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <asm/memory.h>
  6. #include <linux/coresight-stm.h>
  7. #include <linux/delay.h>
  8. #include <linux/devfreq.h>
  9. #include <linux/hash.h>
  10. #include <linux/io.h>
  11. #include <linux/iommu.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/of.h>
  14. #include <linux/pm_qos.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/slab.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/soc/qcom/llcc-qcom.h>
  20. #include <linux/qcom_scm.h>
  21. #include <linux/soc/qcom/smem.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/reset.h>
  24. #include <linux/pm_wakeup.h>
  25. #include "hfi_packetization.h"
  26. #include "msm_cvp_debug.h"
  27. #include "cvp_core_hfi.h"
  28. #include "cvp_hfi_helper.h"
  29. #include "cvp_hfi_io.h"
  30. #include "msm_cvp_dsp.h"
  31. #include "msm_cvp_clocks.h"
  32. #include "vm/cvp_vm.h"
  33. #include "cvp_dump.h"
  34. // ysi - added for debug
  35. #include <linux/clk/qcom.h>
  36. #include "msm_cvp_common.h"
  37. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  38. #define QDSS_IOVA_START 0x80001000
  39. #define MIN_PAYLOAD_SIZE 3
  40. struct cvp_tzbsp_memprot {
  41. u32 cp_start;
  42. u32 cp_size;
  43. u32 cp_nonpixel_start;
  44. u32 cp_nonpixel_size;
  45. };
  46. #define TZBSP_CVP_PAS_ID 26
  47. /* Poll interval in uS */
  48. #define POLL_INTERVAL_US 50
  49. enum tzbsp_subsys_state {
  50. TZ_SUBSYS_STATE_SUSPEND = 0,
  51. TZ_SUBSYS_STATE_RESUME = 1,
  52. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  53. };
  54. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  55. .data = NULL,
  56. .data_count = 0,
  57. };
  58. const int cvp_max_packets = 32;
  59. static void iris_hfi_pm_handler(struct work_struct *work);
  60. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  61. static inline int __resume(struct iris_hfi_device *device);
  62. static inline int __suspend(struct iris_hfi_device *device);
  63. static int __disable_regulator(struct iris_hfi_device *device,
  64. const char *name);
  65. static int __enable_regulator(struct iris_hfi_device *device,
  66. const char *name);
  67. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  68. static int __initialize_packetization(struct iris_hfi_device *device);
  69. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  70. u32 session_id);
  71. static bool __is_session_valid(struct iris_hfi_device *device,
  72. struct cvp_hal_session *session, const char *func);
  73. static int __iface_cmdq_write(struct iris_hfi_device *device,
  74. void *pkt);
  75. static int __load_fw(struct iris_hfi_device *device);
  76. static int __power_on_init(struct iris_hfi_device *device);
  77. static void __unload_fw(struct iris_hfi_device *device);
  78. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  79. static int __enable_subcaches(struct iris_hfi_device *device);
  80. static int __set_subcaches(struct iris_hfi_device *device);
  81. static int __release_subcaches(struct iris_hfi_device *device);
  82. static int __disable_subcaches(struct iris_hfi_device *device);
  83. static int __power_collapse(struct iris_hfi_device *device, bool force);
  84. static int iris_hfi_noc_error_info(void *dev);
  85. static void interrupt_init_iris2(struct iris_hfi_device *device);
  86. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  87. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  88. static void power_off_iris2(struct iris_hfi_device *device);
  89. static int __set_ubwc_config(struct iris_hfi_device *device);
  90. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  91. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  92. static int __disable_hw_power_collapse(struct iris_hfi_device *device);
  93. static int __power_off_controller(struct iris_hfi_device *device);
  94. static int __hwfence_regs_map(struct iris_hfi_device *device);
  95. static int __hwfence_regs_unmap(struct iris_hfi_device *device);
  96. static int __reset_control_assert_name(struct iris_hfi_device *device, const char *name);
  97. static int __reset_control_deassert_name(struct iris_hfi_device *device, const char *name);
  98. static int __reset_control_acquire(struct iris_hfi_device *device, const char *name);
  99. static int __reset_control_release(struct iris_hfi_device *device, const char *name);
  100. static struct iris_hfi_vpu_ops iris2_ops = {
  101. .interrupt_init = interrupt_init_iris2,
  102. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  103. .clock_config_on_enable = clock_config_on_enable_vpu5,
  104. .power_off = power_off_iris2,
  105. .noc_error_info = __noc_error_info_iris2,
  106. .reset_control_assert_name = __reset_control_assert_name,
  107. .reset_control_deassert_name = __reset_control_deassert_name,
  108. .reset_control_acquire_name = __reset_control_acquire,
  109. .reset_control_release_name = __reset_control_release,
  110. };
  111. /**
  112. * Utility function to enforce some of our assumptions. Spam calls to this
  113. * in hotspots in code to double check some of the assumptions that we hold.
  114. */
  115. static inline void __strict_check(struct iris_hfi_device *device)
  116. {
  117. msm_cvp_res_handle_fatal_hw_error(device->res,
  118. !mutex_is_locked(&device->lock));
  119. }
  120. static inline void __set_state(struct iris_hfi_device *device,
  121. enum iris_hfi_state state)
  122. {
  123. device->state = state;
  124. }
  125. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  126. {
  127. return device->state != IRIS_STATE_DEINIT;
  128. }
  129. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  130. {
  131. return device->res->sys_cache_present;
  132. }
  133. static int cvp_synx_recover(void)
  134. {
  135. #ifdef CVP_SYNX_ENABLED
  136. return synx_recover(SYNX_CLIENT_EVA_CTX0);
  137. #else
  138. return 0;
  139. #endif /* End of CVP_SYNX_ENABLED */
  140. }
  141. #define ROW_SIZE 32
  142. int get_hfi_version(void)
  143. {
  144. struct msm_cvp_core *core;
  145. struct iris_hfi_device *hfi;
  146. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  147. hfi = (struct iris_hfi_device *)core->device->hfi_device_data;
  148. return hfi->version;
  149. }
  150. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  151. {
  152. struct msm_cvp_core *core;
  153. struct iris_hfi_device *device;
  154. u32 minor_ver;
  155. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  156. if (core)
  157. device = core->device->hfi_device_data;
  158. else
  159. return 0;
  160. if (!device) {
  161. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  162. return 0;
  163. }
  164. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  165. HFI_VERSION_MINOR_SHIFT;
  166. if (minor_ver < 2)
  167. return sizeof(struct cvp_hfi_msg_session_hdr);
  168. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  169. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  170. else
  171. return sizeof(struct cvp_hfi_msg_session_hdr);
  172. }
  173. unsigned int get_msg_session_id(void *msg)
  174. {
  175. struct cvp_hfi_msg_session_hdr *hdr =
  176. (struct cvp_hfi_msg_session_hdr *)msg;
  177. return hdr->session_id;
  178. }
  179. unsigned int get_msg_errorcode(void *msg)
  180. {
  181. struct cvp_hfi_msg_session_hdr *hdr =
  182. (struct cvp_hfi_msg_session_hdr *)msg;
  183. return hdr->error_type;
  184. }
  185. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  186. unsigned int *error_type, unsigned int *config_id)
  187. {
  188. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  189. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  190. *session_id = cfg->session_id;
  191. *error_type = cfg->error_type;
  192. *config_id = cfg->op_conf_id;
  193. return 0;
  194. }
  195. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  196. {
  197. u32 c = 0, packet_size = *(u32 *)packet;
  198. /*
  199. * row must contain enough for 0xdeadbaad * 8 to be converted into
  200. * "de ad ba ab " * 8 + '\0'
  201. */
  202. char row[3 * ROW_SIZE];
  203. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  204. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  205. packet_size % ROW_SIZE : ROW_SIZE;
  206. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  207. ROW_SIZE, 4, row, sizeof(row), false);
  208. dprintk(log_level, "%s\n", row);
  209. }
  210. }
  211. static int __dsp_suspend(struct iris_hfi_device *device, bool force)
  212. {
  213. int rc;
  214. if (msm_cvp_dsp_disable)
  215. return 0;
  216. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  217. rc = cvp_dsp_suspend(force);
  218. if (rc) {
  219. if (rc != -EBUSY)
  220. dprintk(CVP_ERR,
  221. "%s: dsp suspend failed with error %d\n",
  222. __func__, rc);
  223. return rc;
  224. }
  225. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  226. return 0;
  227. }
  228. static int __dsp_resume(struct iris_hfi_device *device)
  229. {
  230. int rc;
  231. if (msm_cvp_dsp_disable)
  232. return 0;
  233. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  234. rc = cvp_dsp_resume();
  235. if (rc) {
  236. dprintk(CVP_ERR,
  237. "%s: dsp resume failed with error %d\n",
  238. __func__, rc);
  239. return rc;
  240. }
  241. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  242. return rc;
  243. }
  244. static int __dsp_shutdown(struct iris_hfi_device *device)
  245. {
  246. int rc;
  247. if (msm_cvp_dsp_disable)
  248. return 0;
  249. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  250. rc = cvp_dsp_shutdown();
  251. if (rc) {
  252. dprintk(CVP_ERR,
  253. "%s: dsp shutdown failed with error %d\n",
  254. __func__, rc);
  255. WARN_ON(1);
  256. }
  257. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  258. return rc;
  259. }
  260. static int __acquire_regulator(struct regulator_info *rinfo,
  261. struct iris_hfi_device *device)
  262. {
  263. int rc = 0;
  264. if (rinfo->has_hw_power_collapse) {
  265. rc = regulator_set_mode(rinfo->regulator,
  266. REGULATOR_MODE_NORMAL);
  267. if (rc) {
  268. /*
  269. * This is somewhat fatal, but nothing we can do
  270. * about it. We can't disable the regulator w/o
  271. * getting it back under s/w control
  272. */
  273. dprintk(CVP_WARN,
  274. "Failed to acquire regulator control: %s\n",
  275. rinfo->name);
  276. } else {
  277. dprintk(CVP_PWR,
  278. "Acquire regulator control from HW: %s\n",
  279. rinfo->name);
  280. }
  281. }
  282. if (!regulator_is_enabled(rinfo->regulator)) {
  283. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  284. rinfo->name);
  285. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  286. }
  287. return rc;
  288. }
  289. static int __hand_off_regulator(struct regulator_info *rinfo)
  290. {
  291. int rc = 0;
  292. if (rinfo->has_hw_power_collapse) {
  293. rc = regulator_set_mode(rinfo->regulator,
  294. REGULATOR_MODE_FAST);
  295. if (rc) {
  296. dprintk(CVP_WARN,
  297. "Failed to hand off regulator control: %s\n",
  298. rinfo->name);
  299. } else {
  300. dprintk(CVP_PWR,
  301. "Hand off regulator control to HW: %s\n",
  302. rinfo->name);
  303. }
  304. }
  305. return rc;
  306. }
  307. static int __hand_off_regulators(struct iris_hfi_device *device)
  308. {
  309. struct regulator_info *rinfo;
  310. int rc = 0, c = 0;
  311. iris_hfi_for_each_regulator(device, rinfo) {
  312. rc = __hand_off_regulator(rinfo);
  313. /*
  314. * If one regulator hand off failed, driver should take
  315. * the control for other regulators back.
  316. */
  317. if (rc)
  318. goto err_reg_handoff_failed;
  319. c++;
  320. }
  321. return rc;
  322. err_reg_handoff_failed:
  323. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  324. __acquire_regulator(rinfo, device);
  325. return rc;
  326. }
  327. static int __take_back_regulators(struct iris_hfi_device *device)
  328. {
  329. struct regulator_info *rinfo;
  330. int rc = 0;
  331. iris_hfi_for_each_regulator(device, rinfo) {
  332. rc = __acquire_regulator(rinfo, device);
  333. /*
  334. * if one regulator hand off failed, driver should take
  335. * the control for other regulators back.
  336. */
  337. if (rc)
  338. return rc;
  339. }
  340. return rc;
  341. }
  342. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  343. bool *rx_req_is_set)
  344. {
  345. struct cvp_hfi_queue_header *queue;
  346. struct cvp_hfi_cmd_session_hdr *cmd_pkt;
  347. u32 packet_size_in_words, new_write_idx;
  348. u32 empty_space, read_idx, write_idx;
  349. u32 *write_ptr;
  350. if (!qinfo || !packet) {
  351. dprintk(CVP_ERR, "Invalid Params\n");
  352. return -EINVAL;
  353. } else if (!qinfo->q_array.align_virtual_addr) {
  354. dprintk(CVP_WARN, "Queues have already been freed\n");
  355. return -EINVAL;
  356. }
  357. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  358. if (!queue) {
  359. dprintk(CVP_ERR, "queue not present\n");
  360. return -ENOENT;
  361. }
  362. cmd_pkt = (struct cvp_hfi_cmd_session_hdr *)packet;
  363. if (cmd_pkt->size >= sizeof(struct cvp_hfi_cmd_session_hdr))
  364. dprintk(CVP_CMD, "%s: "
  365. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  366. __func__, cmd_pkt->packet_type,
  367. cmd_pkt->session_id,
  368. cmd_pkt->client_data.transaction_id,
  369. cmd_pkt->client_data.kdata & (FENCE_BIT - 1));
  370. else
  371. dprintk(CVP_CMD, "%s: "
  372. "pkt_type %08x", __func__, cmd_pkt->packet_type);
  373. if (msm_cvp_debug & CVP_PKT) {
  374. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  375. __dump_packet(packet, CVP_PKT);
  376. }
  377. packet_size_in_words = (*(u32 *)packet) >> 2;
  378. if (!packet_size_in_words || packet_size_in_words >
  379. qinfo->q_array.mem_size>>2) {
  380. dprintk(CVP_ERR, "Invalid packet size\n");
  381. return -ENODATA;
  382. }
  383. spin_lock(&qinfo->hfi_lock);
  384. read_idx = queue->qhdr_read_idx;
  385. write_idx = queue->qhdr_write_idx;
  386. empty_space = (write_idx >= read_idx) ?
  387. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  388. (read_idx - write_idx);
  389. if (empty_space <= packet_size_in_words) {
  390. queue->qhdr_tx_req = 1;
  391. spin_unlock(&qinfo->hfi_lock);
  392. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  393. empty_space, packet_size_in_words);
  394. return -ENOTEMPTY;
  395. }
  396. queue->qhdr_tx_req = 0;
  397. new_write_idx = write_idx + packet_size_in_words;
  398. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  399. (write_idx << 2));
  400. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  401. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  402. qinfo->q_array.mem_size)) {
  403. spin_unlock(&qinfo->hfi_lock);
  404. dprintk(CVP_ERR, "Invalid write index\n");
  405. return -ENODATA;
  406. }
  407. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  408. memcpy(write_ptr, packet, packet_size_in_words << 2);
  409. } else {
  410. new_write_idx -= qinfo->q_array.mem_size >> 2;
  411. memcpy(write_ptr, packet, (packet_size_in_words -
  412. new_write_idx) << 2);
  413. memcpy((void *)qinfo->q_array.align_virtual_addr,
  414. packet + ((packet_size_in_words - new_write_idx) << 2),
  415. new_write_idx << 2);
  416. }
  417. /*
  418. * Memory barrier to make sure packet is written before updating the
  419. * write index
  420. */
  421. mb();
  422. queue->qhdr_write_idx = new_write_idx;
  423. if (rx_req_is_set)
  424. *rx_req_is_set = queue->qhdr_rx_req == 1;
  425. /*
  426. * Memory barrier to make sure write index is updated before an
  427. * interrupt is raised.
  428. */
  429. mb();
  430. spin_unlock(&qinfo->hfi_lock);
  431. return 0;
  432. }
  433. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  434. u32 *pb_tx_req_is_set)
  435. {
  436. struct cvp_hfi_queue_header *queue;
  437. struct cvp_hfi_msg_session_hdr *msg_pkt;
  438. u32 packet_size_in_words, new_read_idx;
  439. u32 *read_ptr;
  440. u32 receive_request = 0;
  441. u32 read_idx, write_idx;
  442. int rc = 0;
  443. if (!qinfo || !packet || !pb_tx_req_is_set) {
  444. dprintk(CVP_ERR, "Invalid Params\n");
  445. return -EINVAL;
  446. } else if (!qinfo->q_array.align_virtual_addr) {
  447. dprintk(CVP_WARN, "Queues have already been freed\n");
  448. return -EINVAL;
  449. }
  450. /*
  451. * Memory barrier to make sure data is valid before
  452. *reading it
  453. */
  454. mb();
  455. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  456. if (!queue) {
  457. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  458. return -ENOMEM;
  459. }
  460. /*
  461. * Do not set receive request for debug queue, if set,
  462. * Iris generates interrupt for debug messages even
  463. * when there is no response message available.
  464. * In general debug queue will not become full as it
  465. * is being emptied out for every interrupt from Iris.
  466. * Iris will anyway generates interrupt if it is full.
  467. */
  468. spin_lock(&qinfo->hfi_lock);
  469. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  470. receive_request = 1;
  471. read_idx = queue->qhdr_read_idx;
  472. write_idx = queue->qhdr_write_idx;
  473. if (read_idx == write_idx) {
  474. queue->qhdr_rx_req = receive_request;
  475. /*
  476. * mb() to ensure qhdr is updated in main memory
  477. * so that iris reads the updated header values
  478. */
  479. mb();
  480. *pb_tx_req_is_set = 0;
  481. if (write_idx != queue->qhdr_write_idx) {
  482. queue->qhdr_rx_req = 0;
  483. } else {
  484. spin_unlock(&qinfo->hfi_lock);
  485. dprintk(CVP_HFI,
  486. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  487. receive_request ? "message" : "debug",
  488. queue->qhdr_rx_req, queue->qhdr_tx_req,
  489. queue->qhdr_read_idx);
  490. return -ENODATA;
  491. }
  492. }
  493. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  494. (read_idx << 2));
  495. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  496. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  497. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  498. spin_unlock(&qinfo->hfi_lock);
  499. dprintk(CVP_ERR, "Invalid read index\n");
  500. return -ENODATA;
  501. }
  502. packet_size_in_words = (*read_ptr) >> 2;
  503. if (!packet_size_in_words) {
  504. spin_unlock(&qinfo->hfi_lock);
  505. dprintk(CVP_ERR, "Zero packet size\n");
  506. return -ENODATA;
  507. }
  508. new_read_idx = read_idx + packet_size_in_words;
  509. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  510. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  511. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  512. memcpy(packet, read_ptr,
  513. packet_size_in_words << 2);
  514. } else {
  515. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  516. memcpy(packet, read_ptr,
  517. (packet_size_in_words - new_read_idx) << 2);
  518. memcpy(packet + ((packet_size_in_words -
  519. new_read_idx) << 2),
  520. (u8 *)qinfo->q_array.align_virtual_addr,
  521. new_read_idx << 2);
  522. }
  523. } else {
  524. dprintk(CVP_WARN,
  525. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  526. read_idx, packet_size_in_words << 2);
  527. dprintk(CVP_WARN, "Dropping this packet\n");
  528. new_read_idx = write_idx;
  529. rc = -ENODATA;
  530. }
  531. if (new_read_idx != queue->qhdr_write_idx)
  532. queue->qhdr_rx_req = 0;
  533. else
  534. queue->qhdr_rx_req = receive_request;
  535. queue->qhdr_read_idx = new_read_idx;
  536. /*
  537. * mb() to ensure qhdr is updated in main memory
  538. * so that iris reads the updated header values
  539. */
  540. mb();
  541. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  542. spin_unlock(&qinfo->hfi_lock);
  543. if (!(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  544. msg_pkt = (struct cvp_hfi_msg_session_hdr *)packet;
  545. dprintk(CVP_CMD, "%s: "
  546. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  547. __func__, msg_pkt->packet_type,
  548. msg_pkt->session_id,
  549. msg_pkt->client_data.transaction_id,
  550. msg_pkt->client_data.kdata & (FENCE_BIT - 1));
  551. }
  552. if ((msm_cvp_debug & CVP_PKT) &&
  553. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  554. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  555. __dump_packet(packet, CVP_PKT);
  556. }
  557. return rc;
  558. }
  559. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  560. u32 size, u32 align, u32 flags)
  561. {
  562. struct msm_cvp_smem *alloc = &mem->mem_data;
  563. int rc = 0;
  564. if (!dev || !mem || !size) {
  565. dprintk(CVP_ERR, "Invalid Params\n");
  566. return -EINVAL;
  567. }
  568. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  569. alloc->flags = flags;
  570. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  571. if (rc) {
  572. dprintk(CVP_ERR, "Alloc failed\n");
  573. rc = -ENOMEM;
  574. goto fail_smem_alloc;
  575. }
  576. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  577. alloc->kvaddr, size);
  578. mem->mem_size = alloc->size;
  579. mem->align_virtual_addr = alloc->kvaddr;
  580. mem->align_device_addr = alloc->device_addr;
  581. alloc->pkt_type = 0;
  582. alloc->buf_idx = 0;
  583. return rc;
  584. fail_smem_alloc:
  585. return rc;
  586. }
  587. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  588. {
  589. if (!dev || !mem) {
  590. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  591. return;
  592. }
  593. msm_cvp_smem_free(mem);
  594. }
  595. static void __write_register(struct iris_hfi_device *device,
  596. u32 reg, u32 value)
  597. {
  598. u32 hwiosymaddr = reg;
  599. u8 *base_addr;
  600. if (!device) {
  601. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  602. return;
  603. }
  604. __strict_check(device);
  605. if (!device->power_enabled) {
  606. dprintk(CVP_WARN,
  607. "HFI Write register failed : Power is OFF\n");
  608. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  609. return;
  610. }
  611. base_addr = device->cvp_hal_data->register_base;
  612. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  613. base_addr, hwiosymaddr, value);
  614. base_addr += hwiosymaddr;
  615. writel_relaxed(value, base_addr);
  616. /*
  617. * Memory barrier to make sure value is written into the register.
  618. */
  619. wmb();
  620. }
  621. static int __read_gcc_register(struct iris_hfi_device *device, u32 reg)
  622. {
  623. int rc = 0;
  624. u8 *base_addr;
  625. if (!device) {
  626. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  627. return -EINVAL;
  628. }
  629. __strict_check(device);
  630. if (!device->power_enabled) {
  631. dprintk(CVP_WARN,
  632. "%s HFI Read register failed : Power is OFF\n",
  633. __func__);
  634. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  635. return -EINVAL;
  636. }
  637. base_addr = device->cvp_hal_data->gcc_reg_base;
  638. rc = readl_relaxed(base_addr + reg);
  639. /*
  640. * Memory barrier to make sure value is read correctly from the
  641. * register.
  642. */
  643. rmb();
  644. dprintk(CVP_REG,
  645. "GCC Base addr: %pK, read from: %#x, value: %#x...\n",
  646. base_addr, reg, rc);
  647. return rc;
  648. }
  649. static int __read_register(struct iris_hfi_device *device, u32 reg)
  650. {
  651. int rc = 0;
  652. u8 *base_addr;
  653. if (!device) {
  654. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  655. return -EINVAL;
  656. }
  657. __strict_check(device);
  658. if (!device->power_enabled) {
  659. dprintk(CVP_WARN,
  660. "HFI Read register failed : Power is OFF\n");
  661. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  662. return -EINVAL;
  663. }
  664. base_addr = device->cvp_hal_data->register_base;
  665. rc = readl_relaxed(base_addr + reg);
  666. /*
  667. * Memory barrier to make sure value is read correctly from the
  668. * register.
  669. */
  670. rmb();
  671. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  672. base_addr, reg, rc);
  673. return rc;
  674. }
  675. static int __set_registers(struct iris_hfi_device *device)
  676. {
  677. struct msm_cvp_core *core;
  678. struct msm_cvp_platform_data *pdata;
  679. struct reg_set *reg_set;
  680. int i;
  681. if (!device->res) {
  682. dprintk(CVP_ERR,
  683. "device resources null, cannot set registers\n");
  684. return -EINVAL ;
  685. }
  686. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  687. pdata = core->platform_data;
  688. reg_set = &device->res->reg_set;
  689. for (i = 0; i < reg_set->count; i++) {
  690. __write_register(device, reg_set->reg_tbl[i].reg,
  691. reg_set->reg_tbl[i].value);
  692. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  693. reg_set->reg_tbl[i].reg,
  694. reg_set->reg_tbl[i].value);
  695. }
  696. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  697. if (i) {
  698. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  699. return -EINVAL;
  700. }
  701. __write_register(device, CVP_CPU_CS_AXI4_QOS,
  702. pdata->noc_qos->axi_qos);
  703. __write_register(device, CVP_NOC_RGE_PRIORITYLUT_LOW,
  704. pdata->noc_qos->prioritylut_low);
  705. __write_register(device, CVP_NOC_RGE_PRIORITYLUT_HIGH,
  706. pdata->noc_qos->prioritylut_high);
  707. __write_register(device, CVP_NOC_RGE_URGENCY_LOW,
  708. pdata->noc_qos->urgency_low);
  709. __write_register(device, CVP_NOC_RGE_DANGERLUT_LOW,
  710. pdata->noc_qos->dangerlut_low);
  711. __write_register(device, CVP_NOC_RGE_SAFELUT_LOW,
  712. pdata->noc_qos->safelut_low);
  713. __write_register(device, CVP_NOC_CDM_PRIORITYLUT_LOW,
  714. pdata->noc_qos->prioritylut_low);
  715. __write_register(device, CVP_NOC_CDM_PRIORITYLUT_HIGH,
  716. pdata->noc_qos->prioritylut_high);
  717. __write_register(device, CVP_NOC_CDM_URGENCY_LOW,
  718. pdata->noc_qos->urgency_low);
  719. __write_register(device, CVP_NOC_CDM_DANGERLUT_LOW,
  720. pdata->noc_qos->dangerlut_low);
  721. __write_register(device, CVP_NOC_CDM_SAFELUT_LOW,
  722. pdata->noc_qos->safelut_low);
  723. /* Below registers write moved from FW to SW to enable UBWC */
  724. __write_register(device, CVP_NOC_RGE_NIU_DECCTL_LOW,
  725. 0x1);
  726. __write_register(device, CVP_NOC_RGE_NIU_ENCCTL_LOW,
  727. 0x1);
  728. __write_register(device, CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW,
  729. 0x1);
  730. __write_register(device, CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW,
  731. 0x1);
  732. __write_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS,
  733. 0x3);
  734. __write_register(device, CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW,
  735. 0x1);
  736. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  737. return 0;
  738. }
  739. /*
  740. * The existence of this function is a hack for 8996 (or certain Iris versions)
  741. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  742. * (after calling __hand_off_regulators()), the values of the threshold
  743. * registers (typically programmed by TZ) are incorrectly reset. As a result
  744. * reprogram these registers at certain agreed upon points.
  745. */
  746. static void __set_threshold_registers(struct iris_hfi_device *device)
  747. {
  748. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  749. version &= ~GENMASK(15, 0);
  750. if (version != (0x3 << 28 | 0x43 << 16))
  751. return;
  752. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  753. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  754. }
  755. static int __unvote_buses(struct iris_hfi_device *device)
  756. {
  757. int rc = 0;
  758. struct bus_info *bus = NULL;
  759. kfree(device->bus_vote.data);
  760. device->bus_vote.data = NULL;
  761. device->bus_vote.data_count = 0;
  762. iris_hfi_for_each_bus(device, bus) {
  763. rc = msm_cvp_set_bw(bus, 0);
  764. if (rc) {
  765. dprintk(CVP_ERR,
  766. "%s: Failed unvoting bus\n", __func__);
  767. goto err_unknown_device;
  768. }
  769. }
  770. err_unknown_device:
  771. return rc;
  772. }
  773. static int __vote_buses(struct iris_hfi_device *device,
  774. struct cvp_bus_vote_data *data, int num_data)
  775. {
  776. int rc = 0;
  777. struct bus_info *bus = NULL;
  778. struct cvp_bus_vote_data *new_data = NULL;
  779. if (!num_data) {
  780. dprintk(CVP_PWR, "No vote data available\n");
  781. goto no_data_count;
  782. } else if (!data) {
  783. dprintk(CVP_ERR, "Invalid voting data\n");
  784. return -EINVAL;
  785. }
  786. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  787. if (!new_data) {
  788. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  789. rc = -ENOMEM;
  790. goto err_no_mem;
  791. }
  792. no_data_count:
  793. kfree(device->bus_vote.data);
  794. device->bus_vote.data = new_data;
  795. device->bus_vote.data_count = num_data;
  796. iris_hfi_for_each_bus(device, bus) {
  797. if (bus) {
  798. rc = msm_cvp_set_bw(bus, bus->range[1]);
  799. if (rc)
  800. dprintk(CVP_ERR,
  801. "Failed voting bus %s to ab %u\n",
  802. bus->name, bus->range[1]*1000);
  803. }
  804. }
  805. err_no_mem:
  806. return rc;
  807. }
  808. static int iris_hfi_vote_buses(void *dev, struct cvp_bus_vote_data *d, int n)
  809. {
  810. int rc = 0;
  811. struct iris_hfi_device *device = dev;
  812. if (!device)
  813. return -EINVAL;
  814. mutex_lock(&device->lock);
  815. rc = __vote_buses(device, d, n);
  816. mutex_unlock(&device->lock);
  817. return rc;
  818. }
  819. static int __core_set_resource(struct iris_hfi_device *device,
  820. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  821. {
  822. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  823. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  824. int rc = 0;
  825. if (!device || !resource_hdr || !resource_value) {
  826. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  827. return -EINVAL;
  828. }
  829. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  830. rc = call_hfi_pkt_op(device, sys_set_resource,
  831. pkt, resource_hdr, resource_value);
  832. if (rc) {
  833. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  834. goto err_create_pkt;
  835. }
  836. rc = __iface_cmdq_write(device, pkt);
  837. if (rc)
  838. rc = -ENOTEMPTY;
  839. err_create_pkt:
  840. return rc;
  841. }
  842. static int __core_release_resource(struct iris_hfi_device *device,
  843. struct cvp_resource_hdr *resource_hdr)
  844. {
  845. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  846. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  847. int rc = 0;
  848. if (!device || !resource_hdr) {
  849. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  850. return -EINVAL;
  851. }
  852. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  853. rc = call_hfi_pkt_op(device, sys_release_resource,
  854. pkt, resource_hdr);
  855. if (rc) {
  856. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  857. goto err_create_pkt;
  858. }
  859. rc = __iface_cmdq_write(device, pkt);
  860. if (rc)
  861. rc = -ENOTEMPTY;
  862. err_create_pkt:
  863. return rc;
  864. }
  865. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  866. {
  867. int rc = 0;
  868. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  869. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  870. if (rc) {
  871. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  872. return rc;
  873. }
  874. return 0;
  875. }
  876. /*
  877. * Based on fal10_veto, X2RPMh, core_pwr_on and PWAitMode value, infer
  878. * value of xtss_sw_reset. xtss_sw_reset is a TZ register bit. Driver
  879. * cannot access it directly.
  880. *
  881. * In __boot_firmware() function, the caller of this function. It checks
  882. * "core_pwr_on" == false, basically core powered off. So this function
  883. * doesn't check core_pwr_on. Assume core_pwr_on = false.
  884. *
  885. * fal10_veto = VPU_CPU_CS_X2RPMh[2] |
  886. * ( ~VPU_CPU_CS_X2RPMh[1] & core_pwr_on ) |
  887. * ( ~VPU_CPU_CS_X2RPMh[0] & ~( xtss_sw_reset | PWaitMode ) ) ;
  888. */
  889. static inline void check_tensilica_in_reset(struct iris_hfi_device *device)
  890. {
  891. u32 X2RPMh, fal10_veto, wait_mode;
  892. X2RPMh = __read_register(device, CVP_CPU_CS_X2RPMh);
  893. X2RPMh = X2RPMh & 0x7;
  894. /* wait_mode = 1: Tensilica is in WFI mode (PWaitMode = true) */
  895. wait_mode = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  896. wait_mode = wait_mode & 0x1;
  897. fal10_veto = __read_register(device, CVP_CPU_CS_X2RPMh_STATUS);
  898. fal10_veto = fal10_veto & 0x1;
  899. dprintk(CVP_WARN, "tensilica reset check %#x %#x %#x\n",
  900. X2RPMh, wait_mode, fal10_veto);
  901. }
  902. static const char boot_states[0x40][32] = {
  903. "NOT INIT",
  904. "RST_START",
  905. "INIT_MEMCTL",
  906. "INTENABLE_RST",
  907. "LITBASE_RST",
  908. "PREFETCH_EN",
  909. "MPU_INIT",
  910. "CTRL_INIT_READ",
  911. "MEMCTL_L1_FIX",
  912. "RESTORE_EXTRA_NW",
  913. "CORE_RESTORE",
  914. "COLD_BOOT",
  915. "DISABLE_CACHE",
  916. "BEFORE_MPU_C",
  917. "RET_MPU_C",
  918. "IN_MPU_C",
  919. "IN_MPU_DEFAULT",
  920. "IN_MPU_SYNX",
  921. "UCR_SIZE_FAIL",
  922. "UCR_ADDR_FAIL",
  923. "UCR1_SIZE_FAIL",
  924. "UCR1_ADDR_FAIL",
  925. "UCR_OVERLAPPED_UCR1",
  926. "UCR1_OVERLAPPED_UCR",
  927. "UCR_EQ_UCR1",
  928. "MPU_CHECK_DONE",
  929. "BEFORE_INT_LOCK",
  930. "AFTER_INT_LOCK",
  931. "BEFORE_INT_UNLOCK",
  932. "AFTER_INT_UNLOCK",
  933. "CALL_START",
  934. "MAIN_ENTRY",
  935. "VENUS_INIT_ENTRY",
  936. "VSYS_INIT_ENTRY",
  937. "BEFORE_XOS_CLK",
  938. "AFTER_XOS_CLK",
  939. "LOG_MUTEX_INIT",
  940. "CREATE_FRAMEWORK_ENTRY",
  941. "DTG_INIT",
  942. "IDLE_TASK_INIT",
  943. "VENUS_CORE_INIT",
  944. "HW_CORES_INIT",
  945. "RST_THREAD_INIT",
  946. "HOST_THREAD_INIT",
  947. "ALL_THREADS_INIT",
  948. "TASK_MEMPOOL",
  949. "SESSION_MUTEX",
  950. "SIGNALS_INIT",
  951. "RST_SIGNAL_INIT",
  952. "INTR_EN_HOST",
  953. "INTR_REG_HOST",
  954. "INTR_EN_DSP",
  955. "INTR_REG_DSP",
  956. "X2HSOFTINTEN",
  957. "H2XSOFTINTEN",
  958. "CPU2DSPINTEN",
  959. "DSP2CPUINT_SWRESET",
  960. "THREADS_START",
  961. "RST_THREAD_START",
  962. "HST_THREAD_START",
  963. "HST_THREAD_ENTRY"
  964. };
  965. static inline int __boot_firmware(struct iris_hfi_device *device)
  966. {
  967. int rc = 0, loop = 10;
  968. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 500;
  969. u32 reg_gdsc;
  970. /*
  971. * Hand off control of regulators to h/w _after_ enabling clocks.
  972. * Note that the GDSC will turn off when switching from normal
  973. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  974. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  975. */
  976. if (__enable_hw_power_collapse(device))
  977. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  978. if (!msm_cvp_fw_low_power_mode)
  979. goto skip_core_power_check;
  980. while (loop) {
  981. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  982. if (reg_gdsc & 0x80000000) {
  983. usleep_range(100, 200);
  984. loop--;
  985. } else {
  986. break;
  987. }
  988. }
  989. if (!loop)
  990. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  991. skip_core_power_check:
  992. ctrl_init_val = BIT(0);
  993. /* RUMI: CVP_CTRL_INIT in MPTest has bit 0 and 3 set */
  994. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  995. while (!(ctrl_status & CVP_CTRL_INIT_STATUS__M) && count < max_tries) {
  996. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  997. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  998. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  999. rc = -ENODATA;
  1000. break;
  1001. }
  1002. /* Reduce to 500, 1000 on silicon */
  1003. usleep_range(500, 1000);
  1004. count++;
  1005. }
  1006. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1007. ctrl_init_val = __read_register(device, CVP_CTRL_INIT);
  1008. dprintk(CVP_ERR,
  1009. "Failed to boot FW status: %x %x %s\n",
  1010. ctrl_status, ctrl_init_val,
  1011. boot_states[(ctrl_status >> 9) & 0x3f]);
  1012. check_tensilica_in_reset(device);
  1013. rc = -ENODEV;
  1014. }
  1015. /* Enable interrupt before sending commands to tensilica */
  1016. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1017. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1018. return rc;
  1019. }
  1020. static int iris_hfi_resume(void *dev)
  1021. {
  1022. int rc = 0;
  1023. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1024. if (!device) {
  1025. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1026. return -EINVAL;
  1027. }
  1028. dprintk(CVP_CORE, "Resuming Iris\n");
  1029. mutex_lock(&device->lock);
  1030. rc = __resume(device);
  1031. mutex_unlock(&device->lock);
  1032. return rc;
  1033. }
  1034. static int iris_hfi_suspend(void *dev)
  1035. {
  1036. int rc = 0;
  1037. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1038. if (!device) {
  1039. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1040. return -EINVAL;
  1041. } else if (!device->res->sw_power_collapsible) {
  1042. return -ENOTSUPP;
  1043. }
  1044. dprintk(CVP_CORE, "Suspending Iris\n");
  1045. mutex_lock(&device->lock);
  1046. rc = __power_collapse(device, true);
  1047. if (rc) {
  1048. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1049. rc = -EBUSY;
  1050. }
  1051. mutex_unlock(&device->lock);
  1052. /* Cancel pending delayed works if any */
  1053. if (!rc)
  1054. cancel_delayed_work(&iris_hfi_pm_work);
  1055. return rc;
  1056. }
  1057. static void cvp_dump_csr(struct iris_hfi_device *dev)
  1058. {
  1059. u32 reg;
  1060. if (!dev)
  1061. return;
  1062. if (!dev->power_enabled || dev->reg_dumped)
  1063. return;
  1064. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1065. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1066. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1067. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1068. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1069. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1070. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1071. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1072. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1073. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1074. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1075. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1076. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1077. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1078. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1079. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1080. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1081. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1082. dev->reg_dumped = true;
  1083. }
  1084. static int iris_hfi_flush_debug_queue(void *dev)
  1085. {
  1086. int rc = 0;
  1087. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1088. if (!device) {
  1089. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1090. return -EINVAL;
  1091. }
  1092. mutex_lock(&device->lock);
  1093. if (!device->power_enabled) {
  1094. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1095. rc = -EINVAL;
  1096. goto exit;
  1097. }
  1098. cvp_dump_csr(device);
  1099. __flush_debug_queue(device, NULL);
  1100. exit:
  1101. mutex_unlock(&device->lock);
  1102. return rc;
  1103. }
  1104. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1105. {
  1106. int rc = 0;
  1107. struct iris_hfi_device *device = dev;
  1108. if (!device) {
  1109. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1110. return -EINVAL;
  1111. }
  1112. mutex_lock(&device->lock);
  1113. if (__resume(device)) {
  1114. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1115. rc = -ENODEV;
  1116. goto exit;
  1117. }
  1118. rc = msm_cvp_set_clocks_impl(device, freq);
  1119. exit:
  1120. mutex_unlock(&device->lock);
  1121. return rc;
  1122. }
  1123. /* Writes into cmdq without raising an interrupt */
  1124. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1125. void *pkt, bool *requires_interrupt)
  1126. {
  1127. struct cvp_iface_q_info *q_info;
  1128. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1129. int result = -E2BIG;
  1130. if (!device || !pkt) {
  1131. dprintk(CVP_ERR, "Invalid Params\n");
  1132. return -EINVAL;
  1133. }
  1134. __strict_check(device);
  1135. if (!__core_in_valid_state(device)) {
  1136. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1137. result = -EINVAL;
  1138. goto err_q_null;
  1139. }
  1140. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1141. device->last_packet_type = cmd_packet->packet_type;
  1142. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1143. if (!q_info) {
  1144. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1145. goto err_q_null;
  1146. }
  1147. if (!q_info->q_array.align_virtual_addr) {
  1148. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1149. result = -ENODATA;
  1150. goto err_q_null;
  1151. }
  1152. if (__resume(device)) {
  1153. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1154. goto err_q_write;
  1155. }
  1156. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1157. if (device->res->sw_power_collapsible) {
  1158. cancel_delayed_work(&iris_hfi_pm_work);
  1159. if (!queue_delayed_work(device->iris_pm_workq,
  1160. &iris_hfi_pm_work,
  1161. msecs_to_jiffies(
  1162. device->res->msm_cvp_pwr_collapse_delay))) {
  1163. dprintk(CVP_PWR,
  1164. "PM work already scheduled\n");
  1165. }
  1166. }
  1167. result = 0;
  1168. } else {
  1169. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1170. }
  1171. err_q_write:
  1172. err_q_null:
  1173. return result;
  1174. }
  1175. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1176. {
  1177. bool needs_interrupt = false;
  1178. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1179. if (!rc && needs_interrupt) {
  1180. /* Consumer of cmdq prefers that we raise an interrupt */
  1181. rc = 0;
  1182. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1183. }
  1184. return rc;
  1185. }
  1186. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1187. {
  1188. u32 tx_req_is_set = 0;
  1189. int rc = 0;
  1190. struct cvp_iface_q_info *q_info;
  1191. if (!pkt) {
  1192. dprintk(CVP_ERR, "Invalid Params\n");
  1193. return -EINVAL;
  1194. }
  1195. __strict_check(device);
  1196. if (!__core_in_valid_state(device)) {
  1197. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1198. rc = -EINVAL;
  1199. goto read_error_null;
  1200. }
  1201. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1202. if (q_info->q_array.align_virtual_addr == NULL) {
  1203. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1204. rc = -ENODATA;
  1205. goto read_error_null;
  1206. }
  1207. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1208. if (tx_req_is_set)
  1209. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1210. rc = 0;
  1211. } else
  1212. rc = -ENODATA;
  1213. read_error_null:
  1214. return rc;
  1215. }
  1216. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1217. {
  1218. u32 tx_req_is_set = 0;
  1219. int rc = 0;
  1220. struct cvp_iface_q_info *q_info;
  1221. if (!pkt) {
  1222. dprintk(CVP_ERR, "Invalid Params\n");
  1223. return -EINVAL;
  1224. }
  1225. __strict_check(device);
  1226. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1227. if (q_info->q_array.align_virtual_addr == NULL) {
  1228. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1229. rc = -ENODATA;
  1230. goto dbg_error_null;
  1231. }
  1232. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1233. if (tx_req_is_set)
  1234. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1235. rc = 0;
  1236. } else
  1237. rc = -ENODATA;
  1238. dbg_error_null:
  1239. return rc;
  1240. }
  1241. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1242. {
  1243. q_hdr->qhdr_status = 0x1;
  1244. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1245. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1246. q_hdr->qhdr_pkt_size = 0;
  1247. q_hdr->qhdr_rx_wm = 0x1;
  1248. q_hdr->qhdr_tx_wm = 0x1;
  1249. q_hdr->qhdr_rx_req = 0x1;
  1250. q_hdr->qhdr_tx_req = 0x0;
  1251. q_hdr->qhdr_rx_irq_status = 0x0;
  1252. q_hdr->qhdr_tx_irq_status = 0x0;
  1253. q_hdr->qhdr_read_idx = 0x0;
  1254. q_hdr->qhdr_write_idx = 0x0;
  1255. }
  1256. /*
  1257. *Unused, keep for reference
  1258. */
  1259. /*
  1260. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1261. {
  1262. int i;
  1263. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1264. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1265. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1266. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1267. return;
  1268. }
  1269. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1270. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1271. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1272. mem_data->kvaddr, mem_data->dma_handle);
  1273. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1274. device->dsp_iface_queues[i].q_hdr = NULL;
  1275. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1276. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1277. }
  1278. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1279. device->dsp_iface_q_table.align_device_addr = 0;
  1280. }
  1281. */
  1282. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1283. {
  1284. int rc = 0;
  1285. u32 i;
  1286. struct cvp_iface_q_info *iface_q;
  1287. int offset = 0;
  1288. phys_addr_t fw_bias = 0;
  1289. size_t q_size;
  1290. struct msm_cvp_smem *mem_data;
  1291. void *kvaddr;
  1292. dma_addr_t dma_handle;
  1293. dma_addr_t iova;
  1294. struct context_bank_info *cb;
  1295. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1296. mem_data = &dev->dsp_iface_q_table.mem_data;
  1297. if (mem_data->kvaddr) {
  1298. memset((void *)mem_data->kvaddr, 0, q_size);
  1299. cvp_dsp_init_hfi_queue_hdr(dev);
  1300. return 0;
  1301. }
  1302. /* Allocate dsp queues from CDSP device memory */
  1303. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1304. &dma_handle, GFP_KERNEL);
  1305. if (IS_ERR_OR_NULL(kvaddr)) {
  1306. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1307. goto fail_dma_alloc;
  1308. }
  1309. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1310. if (!cb) {
  1311. dprintk(CVP_ERR,
  1312. "%s: failed to get context bank\n", __func__);
  1313. goto fail_dma_map;
  1314. }
  1315. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1316. q_size, DMA_BIDIRECTIONAL, 0);
  1317. if (dma_mapping_error(cb->dev, iova)) {
  1318. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1319. goto fail_dma_map;
  1320. }
  1321. dprintk(CVP_DSP,
  1322. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1323. __func__, kvaddr, dma_handle, iova, q_size);
  1324. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1325. mem_data->kvaddr = kvaddr;
  1326. mem_data->device_addr = iova;
  1327. mem_data->dma_handle = dma_handle;
  1328. mem_data->size = q_size;
  1329. mem_data->mapping_info.cb_info = cb;
  1330. if (!is_iommu_present(dev->res))
  1331. fw_bias = dev->cvp_hal_data->firmware_base;
  1332. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1333. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1334. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1335. offset = dev->dsp_iface_q_table.mem_size;
  1336. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1337. iface_q = &dev->dsp_iface_queues[i];
  1338. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1339. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1340. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1341. offset += iface_q->q_array.mem_size;
  1342. spin_lock_init(&iface_q->hfi_lock);
  1343. }
  1344. cvp_dsp_init_hfi_queue_hdr(dev);
  1345. return rc;
  1346. fail_dma_map:
  1347. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1348. fail_dma_alloc:
  1349. return -ENOMEM;
  1350. }
  1351. static void __interface_queues_release(struct iris_hfi_device *device)
  1352. {
  1353. #ifdef CONFIG_EVA_TVM
  1354. int i;
  1355. struct cvp_hfi_mem_map_table *qdss;
  1356. struct cvp_hfi_mem_map *mem_map;
  1357. int num_entries = device->res->qdss_addr_set.count;
  1358. unsigned long mem_map_table_base_addr;
  1359. struct context_bank_info *cb;
  1360. if (device->qdss.align_virtual_addr) {
  1361. qdss = (struct cvp_hfi_mem_map_table *)
  1362. device->qdss.align_virtual_addr;
  1363. qdss->mem_map_num_entries = num_entries;
  1364. mem_map_table_base_addr =
  1365. device->qdss.align_device_addr +
  1366. sizeof(struct cvp_hfi_mem_map_table);
  1367. qdss->mem_map_table_base_addr =
  1368. (u32)mem_map_table_base_addr;
  1369. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1370. mem_map_table_base_addr) {
  1371. dprintk(CVP_ERR,
  1372. "Invalid mem_map_table_base_addr %#lx",
  1373. mem_map_table_base_addr);
  1374. }
  1375. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1376. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1377. for (i = 0; cb && i < num_entries; i++) {
  1378. iommu_unmap(cb->domain,
  1379. mem_map[i].virtual_addr,
  1380. mem_map[i].size);
  1381. }
  1382. __smem_free(device, &device->qdss.mem_data);
  1383. }
  1384. __smem_free(device, &device->iface_q_table.mem_data);
  1385. __smem_free(device, &device->sfr.mem_data);
  1386. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1387. device->iface_queues[i].q_hdr = NULL;
  1388. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1389. device->iface_queues[i].q_array.align_device_addr = 0;
  1390. }
  1391. device->iface_q_table.align_virtual_addr = NULL;
  1392. device->iface_q_table.align_device_addr = 0;
  1393. device->qdss.align_virtual_addr = NULL;
  1394. device->qdss.align_device_addr = 0;
  1395. device->sfr.align_virtual_addr = NULL;
  1396. device->sfr.align_device_addr = 0;
  1397. device->mem_addr.align_virtual_addr = NULL;
  1398. device->mem_addr.align_device_addr = 0;
  1399. #endif
  1400. }
  1401. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1402. struct cvp_hfi_mem_map *mem_map,
  1403. struct iommu_domain *domain)
  1404. {
  1405. int i;
  1406. int rc = 0;
  1407. dma_addr_t iova = QDSS_IOVA_START;
  1408. int num_entries = dev->res->qdss_addr_set.count;
  1409. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1410. if (!num_entries)
  1411. return -ENODATA;
  1412. for (i = 0; i < num_entries; i++) {
  1413. if (domain) {
  1414. rc = iommu_map(domain, iova,
  1415. qdss_addr_tbl[i].start,
  1416. qdss_addr_tbl[i].size,
  1417. IOMMU_READ | IOMMU_WRITE);
  1418. if (rc) {
  1419. dprintk(CVP_ERR,
  1420. "IOMMU QDSS mapping failed for addr %#x\n",
  1421. qdss_addr_tbl[i].start);
  1422. rc = -ENOMEM;
  1423. break;
  1424. }
  1425. } else {
  1426. iova = qdss_addr_tbl[i].start;
  1427. }
  1428. mem_map[i].virtual_addr = (u32)iova;
  1429. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1430. mem_map[i].size = qdss_addr_tbl[i].size;
  1431. mem_map[i].attr = 0x0;
  1432. iova += mem_map[i].size;
  1433. }
  1434. if (i < num_entries) {
  1435. dprintk(CVP_ERR,
  1436. "QDSS mapping failed, Freeing other entries %d\n", i);
  1437. for (--i; domain && i >= 0; i--) {
  1438. iommu_unmap(domain,
  1439. mem_map[i].virtual_addr,
  1440. mem_map[i].size);
  1441. }
  1442. }
  1443. return rc;
  1444. }
  1445. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1446. {
  1447. __write_register(device, CVP_UC_REGION_ADDR,
  1448. (u32)device->iface_q_table.align_device_addr);
  1449. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1450. __write_register(device, CVP_QTBL_ADDR,
  1451. (u32)device->iface_q_table.align_device_addr);
  1452. __write_register(device, CVP_QTBL_INFO, 0x01);
  1453. if (device->sfr.align_device_addr)
  1454. __write_register(device, CVP_SFR_ADDR,
  1455. (u32)device->sfr.align_device_addr);
  1456. if (device->qdss.align_device_addr)
  1457. __write_register(device, CVP_MMAP_ADDR,
  1458. (u32)device->qdss.align_device_addr);
  1459. call_iris_op(device, setup_dsp_uc_memmap, device);
  1460. }
  1461. static void __hfi_queue_init(struct iris_hfi_device *dev)
  1462. {
  1463. int i, offset = 0;
  1464. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1465. struct cvp_iface_q_info *iface_q;
  1466. struct cvp_hfi_queue_header *q_hdr;
  1467. if (!dev)
  1468. return;
  1469. offset += dev->iface_q_table.mem_size;
  1470. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1471. iface_q = &dev->iface_queues[i];
  1472. iface_q->q_array.align_device_addr =
  1473. dev->iface_q_table.align_device_addr + offset;
  1474. iface_q->q_array.align_virtual_addr =
  1475. dev->iface_q_table.align_virtual_addr + offset;
  1476. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1477. offset += iface_q->q_array.mem_size;
  1478. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1479. dev->iface_q_table.align_virtual_addr, i);
  1480. __set_queue_hdr_defaults(iface_q->q_hdr);
  1481. spin_lock_init(&iface_q->hfi_lock);
  1482. }
  1483. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1484. dev->iface_q_table.align_virtual_addr;
  1485. q_tbl_hdr->qtbl_version = 0;
  1486. q_tbl_hdr->device_addr = (void *)dev;
  1487. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1488. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1489. q_tbl_hdr->qtbl_qhdr0_offset =
  1490. sizeof(struct cvp_hfi_queue_table_header);
  1491. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1492. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1493. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1494. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1495. q_hdr = iface_q->q_hdr;
  1496. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1497. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1498. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1499. q_hdr = iface_q->q_hdr;
  1500. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1501. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1502. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1503. q_hdr = iface_q->q_hdr;
  1504. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1505. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1506. /*
  1507. * Set receive request to zero on debug queue as there is no
  1508. * need of interrupt from cvp hardware for debug messages
  1509. */
  1510. q_hdr->qhdr_rx_req = 0;
  1511. }
  1512. static void __sfr_init(struct iris_hfi_device *dev)
  1513. {
  1514. struct cvp_hfi_sfr_struct *vsfr;
  1515. if (!dev)
  1516. return;
  1517. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1518. if (vsfr)
  1519. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1520. }
  1521. static int __interface_queues_init(struct iris_hfi_device *dev)
  1522. {
  1523. int rc = 0;
  1524. struct cvp_hfi_mem_map_table *qdss;
  1525. struct cvp_hfi_mem_map *mem_map;
  1526. struct cvp_mem_addr *mem_addr;
  1527. int num_entries = dev->res->qdss_addr_set.count;
  1528. phys_addr_t fw_bias = 0;
  1529. size_t q_size;
  1530. unsigned long mem_map_table_base_addr;
  1531. struct context_bank_info *cb;
  1532. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1533. mem_addr = &dev->mem_addr;
  1534. if (!is_iommu_present(dev->res))
  1535. fw_bias = dev->cvp_hal_data->firmware_base;
  1536. if (dev->iface_q_table.align_virtual_addr) {
  1537. memset((void *)dev->iface_q_table.align_virtual_addr,
  1538. 0, q_size);
  1539. goto hfi_queue_init;
  1540. }
  1541. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1542. if (rc) {
  1543. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1544. goto fail_alloc_queue;
  1545. }
  1546. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1547. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1548. fw_bias;
  1549. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1550. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1551. hfi_queue_init:
  1552. __hfi_queue_init(dev);
  1553. if (dev->sfr.align_virtual_addr) {
  1554. memset((void *)dev->sfr.align_virtual_addr,
  1555. 0, ALIGNED_SFR_SIZE);
  1556. goto sfr_init;
  1557. }
  1558. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1559. if (rc) {
  1560. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1561. dev->sfr.align_device_addr = 0;
  1562. } else {
  1563. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1564. fw_bias;
  1565. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1566. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1567. dev->sfr.mem_data = mem_addr->mem_data;
  1568. }
  1569. sfr_init:
  1570. __sfr_init(dev);
  1571. if (dev->qdss.align_virtual_addr)
  1572. goto dsp_hfi_queue_init;
  1573. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1574. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1575. SMEM_UNCACHED);
  1576. if (rc) {
  1577. dprintk(CVP_WARN,
  1578. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1579. dev->qdss.align_device_addr = 0;
  1580. } else {
  1581. dev->qdss.align_device_addr =
  1582. mem_addr->align_device_addr - fw_bias;
  1583. dev->qdss.align_virtual_addr =
  1584. mem_addr->align_virtual_addr;
  1585. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1586. dev->qdss.mem_data = mem_addr->mem_data;
  1587. }
  1588. }
  1589. if (dev->qdss.align_virtual_addr) {
  1590. qdss =
  1591. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1592. qdss->mem_map_num_entries = num_entries;
  1593. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1594. sizeof(struct cvp_hfi_mem_map_table);
  1595. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1596. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1597. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1598. if (!cb) {
  1599. dprintk(CVP_ERR,
  1600. "%s: failed to get context bank\n", __func__);
  1601. return -EINVAL;
  1602. }
  1603. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1604. if (rc) {
  1605. dprintk(CVP_ERR,
  1606. "IOMMU mapping failed, Freeing qdss memdata\n");
  1607. __smem_free(dev, &dev->qdss.mem_data);
  1608. dev->qdss.align_virtual_addr = NULL;
  1609. dev->qdss.align_device_addr = 0;
  1610. }
  1611. }
  1612. dsp_hfi_queue_init:
  1613. rc = __interface_dsp_queues_init(dev);
  1614. if (rc) {
  1615. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1616. goto fail_alloc_queue;
  1617. }
  1618. __setup_ucregion_memory_map(dev);
  1619. return 0;
  1620. fail_alloc_queue:
  1621. return -ENOMEM;
  1622. }
  1623. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1624. {
  1625. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1626. int rc = 0;
  1627. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1628. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1629. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1630. if (rc) {
  1631. dprintk(CVP_WARN,
  1632. "Debug mode setting to FW failed\n");
  1633. return -ENOTEMPTY;
  1634. }
  1635. if (__iface_cmdq_write(device, pkt))
  1636. return -ENOTEMPTY;
  1637. return 0;
  1638. }
  1639. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1640. bool enable)
  1641. {
  1642. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1643. int rc = 0;
  1644. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1645. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1646. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1647. if (__iface_cmdq_write(device, pkt))
  1648. return -ENOTEMPTY;
  1649. return 0;
  1650. }
  1651. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1652. {
  1653. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1654. int rc = 0;
  1655. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1656. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1657. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1658. pkt, mode);
  1659. if (rc) {
  1660. dprintk(CVP_WARN,
  1661. "Coverage mode setting to FW failed\n");
  1662. return -ENOTEMPTY;
  1663. }
  1664. if (__iface_cmdq_write(device, pkt)) {
  1665. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1666. return -ENOTEMPTY;
  1667. }
  1668. return 0;
  1669. }
  1670. static int __sys_set_power_control(struct iris_hfi_device *device,
  1671. bool enable)
  1672. {
  1673. struct regulator_info *rinfo;
  1674. bool supported = false;
  1675. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1676. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1677. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1678. iris_hfi_for_each_regulator(device, rinfo) {
  1679. if (rinfo->has_hw_power_collapse) {
  1680. supported = true;
  1681. break;
  1682. }
  1683. }
  1684. if (!supported)
  1685. return 0;
  1686. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1687. if (__iface_cmdq_write(device, pkt))
  1688. return -ENOTEMPTY;
  1689. return 0;
  1690. }
  1691. static void cvp_pm_qos_update(struct iris_hfi_device *device, bool vote_on)
  1692. {
  1693. u32 latency, off_vote_cnt;
  1694. int i, err = 0;
  1695. spin_lock(&device->res->pm_qos.lock);
  1696. off_vote_cnt = device->res->pm_qos.off_vote_cnt;
  1697. spin_unlock(&device->res->pm_qos.lock);
  1698. if (vote_on && off_vote_cnt)
  1699. return;
  1700. latency = vote_on ? device->res->pm_qos.latency_us :
  1701. PM_QOS_RESUME_LATENCY_DEFAULT_VALUE;
  1702. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  1703. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1704. err = dev_pm_qos_update_request(
  1705. &device->res->pm_qos.pm_qos_hdls[i],
  1706. latency);
  1707. if (err < 0) {
  1708. if (vote_on) {
  1709. dprintk(CVP_WARN,
  1710. "pm qos on failed %d\n", err);
  1711. } else {
  1712. dprintk(CVP_WARN,
  1713. "pm qos off failed %d\n", err);
  1714. }
  1715. }
  1716. }
  1717. }
  1718. static int iris_pm_qos_update(void *device)
  1719. {
  1720. struct iris_hfi_device *dev;
  1721. if (!device) {
  1722. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  1723. return -ENODEV;
  1724. }
  1725. dev = device;
  1726. mutex_lock(&dev->lock);
  1727. cvp_pm_qos_update(dev, true);
  1728. mutex_unlock(&dev->lock);
  1729. return 0;
  1730. }
  1731. static int __hwfence_regs_map(struct iris_hfi_device *device)
  1732. {
  1733. int rc = 0;
  1734. struct context_bank_info *cb;
  1735. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1736. if (!cb) {
  1737. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1738. return -EINVAL;
  1739. }
  1740. if (device->res->reg_mappings.ipclite_phyaddr != 0) {
  1741. rc = iommu_map(cb->domain,
  1742. device->res->reg_mappings.ipclite_iova,
  1743. device->res->reg_mappings.ipclite_phyaddr,
  1744. device->res->reg_mappings.ipclite_size,
  1745. IOMMU_READ | IOMMU_WRITE);
  1746. if (rc) {
  1747. dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
  1748. rc, device->res->reg_mappings.ipclite_iova,
  1749. device->res->reg_mappings.ipclite_phyaddr,
  1750. device->res->reg_mappings.ipclite_size);
  1751. return rc;
  1752. }
  1753. }
  1754. if (device->res->reg_mappings.hwmutex_phyaddr != 0) {
  1755. rc = iommu_map(cb->domain,
  1756. device->res->reg_mappings.hwmutex_iova,
  1757. device->res->reg_mappings.hwmutex_phyaddr,
  1758. device->res->reg_mappings.hwmutex_size,
  1759. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1760. if (rc) {
  1761. dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
  1762. rc, device->res->reg_mappings.hwmutex_iova,
  1763. device->res->reg_mappings.hwmutex_phyaddr,
  1764. device->res->reg_mappings.hwmutex_size);
  1765. return rc;
  1766. }
  1767. }
  1768. if (device->res->reg_mappings.aon_phyaddr != 0) {
  1769. rc = iommu_map(cb->domain,
  1770. device->res->reg_mappings.aon_iova,
  1771. device->res->reg_mappings.aon_phyaddr,
  1772. device->res->reg_mappings.aon_size,
  1773. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1774. if (rc) {
  1775. dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
  1776. rc, device->res->reg_mappings.aon_iova,
  1777. device->res->reg_mappings.aon_phyaddr,
  1778. device->res->reg_mappings.aon_size);
  1779. return rc;
  1780. }
  1781. }
  1782. if (device->res->reg_mappings.timer_phyaddr != 0) {
  1783. rc = iommu_map(cb->domain,
  1784. device->res->reg_mappings.timer_iova,
  1785. device->res->reg_mappings.timer_phyaddr,
  1786. device->res->reg_mappings.timer_size,
  1787. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1788. if (rc) {
  1789. dprintk(CVP_ERR, "map timer fail %d %#x %#x %#x\n",
  1790. rc, device->res->reg_mappings.timer_iova,
  1791. device->res->reg_mappings.timer_phyaddr,
  1792. device->res->reg_mappings.timer_size);
  1793. return rc;
  1794. }
  1795. }
  1796. return rc;
  1797. }
  1798. static int __hwfence_regs_unmap(struct iris_hfi_device *device)
  1799. {
  1800. int rc = 0;
  1801. struct context_bank_info *cb;
  1802. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1803. if (!cb) {
  1804. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1805. return -EINVAL;
  1806. }
  1807. if (device->res->reg_mappings.ipclite_iova != 0) {
  1808. iommu_unmap(cb->domain,
  1809. device->res->reg_mappings.ipclite_iova,
  1810. device->res->reg_mappings.ipclite_size);
  1811. }
  1812. if (device->res->reg_mappings.hwmutex_iova != 0) {
  1813. iommu_unmap(cb->domain,
  1814. device->res->reg_mappings.hwmutex_iova,
  1815. device->res->reg_mappings.hwmutex_size);
  1816. }
  1817. if (device->res->reg_mappings.aon_iova != 0) {
  1818. iommu_unmap(cb->domain,
  1819. device->res->reg_mappings.aon_iova,
  1820. device->res->reg_mappings.aon_size);
  1821. }
  1822. if (device->res->reg_mappings.timer_iova != 0) {
  1823. iommu_unmap(cb->domain,
  1824. device->res->reg_mappings.timer_iova,
  1825. device->res->reg_mappings.timer_size);
  1826. }
  1827. return rc;
  1828. }
  1829. static int iris_hfi_core_init(void *device)
  1830. {
  1831. int rc = 0;
  1832. u32 ipcc_iova;
  1833. struct cvp_hfi_cmd_sys_init_packet pkt;
  1834. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1835. struct iris_hfi_device *dev;
  1836. if (!device) {
  1837. dprintk(CVP_ERR, "Invalid device\n");
  1838. return -ENODEV;
  1839. }
  1840. dev = device;
  1841. dprintk(CVP_CORE, "Core initializing\n");
  1842. pm_stay_awake(dev->res->pdev->dev.parent);
  1843. mutex_lock(&dev->lock);
  1844. dev->bus_vote.data =
  1845. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1846. if (!dev->bus_vote.data) {
  1847. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1848. rc = -ENOMEM;
  1849. goto err_no_mem;
  1850. }
  1851. dev->bus_vote.data_count = 1;
  1852. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1853. __hwfence_regs_map(dev);
  1854. rc = __power_on_init(dev);
  1855. if (rc) {
  1856. dprintk(CVP_ERR, "Failed to power on init EVA\n");
  1857. goto err_load_fw;
  1858. }
  1859. #ifdef CVP_CONFIG_SYNX_V2
  1860. rc = cvp_synx_recover();
  1861. if (rc) {
  1862. dprintk(CVP_ERR, "Failed to recover synx\n");
  1863. goto err_core_init;
  1864. }
  1865. #endif
  1866. /* mmrm registration */
  1867. if (msm_cvp_mmrm_enabled) {
  1868. rc = msm_cvp_mmrm_register(device);
  1869. if (rc) {
  1870. dprintk(CVP_ERR, "Failed to register mmrm client\n");
  1871. goto err_core_init;
  1872. }
  1873. }
  1874. __set_state(dev, IRIS_STATE_INIT);
  1875. dev->reg_dumped = false;
  1876. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1877. &dev->cvp_hal_data->firmware_base,
  1878. dev->cvp_hal_data->register_base);
  1879. rc = __interface_queues_init(dev);
  1880. if (rc) {
  1881. dprintk(CVP_ERR, "failed to init queues\n");
  1882. rc = -ENOMEM;
  1883. goto err_core_init;
  1884. }
  1885. cvp_register_va_md_region();
  1886. // Add node for dev struct
  1887. add_va_node_to_list(CVP_QUEUE_DUMP, dev,
  1888. sizeof(struct iris_hfi_device),
  1889. "iris_hfi_device-dev", false);
  1890. add_queue_header_to_va_md_list((void*)dev);
  1891. add_hfi_queue_to_va_md_list((void*)dev);
  1892. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1893. if (!rc) {
  1894. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1895. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1896. }
  1897. rc = __load_fw(dev);
  1898. if (rc) {
  1899. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  1900. goto err_core_init;
  1901. }
  1902. rc = __boot_firmware(dev);
  1903. if (rc) {
  1904. dprintk(CVP_ERR, "Failed to start core\n");
  1905. rc = -ENODEV;
  1906. goto err_core_init;
  1907. }
  1908. dev->version = __read_register(dev, CVP_VERSION_INFO);
  1909. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  1910. if (rc) {
  1911. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  1912. goto err_core_init;
  1913. }
  1914. if (__iface_cmdq_write(dev, &pkt)) {
  1915. rc = -ENOTEMPTY;
  1916. goto err_core_init;
  1917. }
  1918. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  1919. if (rc || __iface_cmdq_write(dev, &version_pkt))
  1920. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  1921. __sys_set_debug(device, msm_cvp_fw_debug);
  1922. __enable_subcaches(device);
  1923. __set_subcaches(device);
  1924. __set_ubwc_config(device);
  1925. __sys_set_idle_indicator(device, true);
  1926. if (dev->res->pm_qos.latency_us) {
  1927. int err = 0;
  1928. u32 i, cpu;
  1929. dev->res->pm_qos.pm_qos_hdls = kcalloc(
  1930. dev->res->pm_qos.silver_count,
  1931. sizeof(struct dev_pm_qos_request),
  1932. GFP_KERNEL);
  1933. if (!dev->res->pm_qos.pm_qos_hdls) {
  1934. dprintk(CVP_WARN, "Failed allocate pm_qos_hdls\n");
  1935. goto pm_qos_bail;
  1936. }
  1937. for (i = 0; i < dev->res->pm_qos.silver_count; i++) {
  1938. cpu = dev->res->pm_qos.silver_cores[i];
  1939. err = dev_pm_qos_add_request(
  1940. get_cpu_device(cpu),
  1941. &dev->res->pm_qos.pm_qos_hdls[i],
  1942. DEV_PM_QOS_RESUME_LATENCY,
  1943. dev->res->pm_qos.latency_us);
  1944. if (err < 0)
  1945. dprintk(CVP_WARN,
  1946. "%s pm_qos_add_req %d failed\n",
  1947. __func__, i);
  1948. }
  1949. }
  1950. pm_qos_bail:
  1951. mutex_unlock(&dev->lock);
  1952. cvp_dsp_send_hfi_queue();
  1953. pm_relax(dev->res->pdev->dev.parent);
  1954. dprintk(CVP_CORE, "Core inited successfully\n");
  1955. return 0;
  1956. err_core_init:
  1957. __set_state(dev, IRIS_STATE_DEINIT);
  1958. __unload_fw(dev);
  1959. if (dev->mmrm_cvp)
  1960. {
  1961. msm_cvp_mmrm_deregister(dev);
  1962. }
  1963. err_load_fw:
  1964. __hwfence_regs_unmap(dev);
  1965. err_no_mem:
  1966. dprintk(CVP_ERR, "Core init failed\n");
  1967. mutex_unlock(&dev->lock);
  1968. pm_relax(dev->res->pdev->dev.parent);
  1969. return rc;
  1970. }
  1971. static int iris_hfi_core_release(void *dev)
  1972. {
  1973. int rc = 0, i;
  1974. struct iris_hfi_device *device = dev;
  1975. struct cvp_hal_session *session, *next;
  1976. struct dev_pm_qos_request *qos_hdl;
  1977. if (!device) {
  1978. dprintk(CVP_ERR, "invalid device\n");
  1979. return -ENODEV;
  1980. }
  1981. mutex_lock(&device->lock);
  1982. dprintk(CVP_WARN, "Core releasing\n");
  1983. if (device->res->pm_qos.latency_us &&
  1984. device->res->pm_qos.pm_qos_hdls) {
  1985. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1986. qos_hdl = &device->res->pm_qos.pm_qos_hdls[i];
  1987. if ((qos_hdl != NULL) && dev_pm_qos_request_active(qos_hdl))
  1988. dev_pm_qos_remove_request(qos_hdl);
  1989. }
  1990. kfree(device->res->pm_qos.pm_qos_hdls);
  1991. device->res->pm_qos.pm_qos_hdls = NULL;
  1992. }
  1993. __resume(device);
  1994. __set_state(device, IRIS_STATE_DEINIT);
  1995. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  1996. if (rc)
  1997. dprintk(CVP_WARN, "Failed to suspend cvp FW%d\n", rc);
  1998. __dsp_shutdown(device);
  1999. __disable_subcaches(device);
  2000. __unload_fw(device);
  2001. __hwfence_regs_unmap(device);
  2002. if (msm_cvp_mmrm_enabled) {
  2003. rc = msm_cvp_mmrm_deregister(device);
  2004. if (rc) {
  2005. dprintk(CVP_ERR,
  2006. "%s: Failed msm_cvp_mmrm_deregister:%d\n",
  2007. __func__, rc);
  2008. }
  2009. }
  2010. /* unlink all sessions from device */
  2011. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  2012. list_del(&session->list);
  2013. session->device = NULL;
  2014. }
  2015. dprintk(CVP_CORE, "Core released successfully\n");
  2016. mutex_unlock(&device->lock);
  2017. return rc;
  2018. }
  2019. static void __core_clear_interrupt(struct iris_hfi_device *device)
  2020. {
  2021. u32 intr_status = 0, mask = 0;
  2022. if (!device) {
  2023. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2024. return;
  2025. }
  2026. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  2027. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  2028. if (intr_status & mask) {
  2029. device->intr_status |= intr_status;
  2030. device->reg_count++;
  2031. dprintk(CVP_CORE,
  2032. "INTERRUPT for device: %pK: times: %d status: %d\n",
  2033. device, device->reg_count, intr_status);
  2034. } else {
  2035. device->spur_count++;
  2036. }
  2037. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  2038. }
  2039. static int iris_hfi_core_trigger_ssr(void *device,
  2040. enum hal_ssr_trigger_type type)
  2041. {
  2042. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  2043. int rc = 0;
  2044. struct iris_hfi_device *dev;
  2045. cvp_free_va_md_list();
  2046. if (!device) {
  2047. dprintk(CVP_ERR, "invalid device\n");
  2048. return -ENODEV;
  2049. }
  2050. dev = device;
  2051. if (mutex_trylock(&dev->lock)) {
  2052. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  2053. if (rc) {
  2054. dprintk(CVP_ERR, "%s: failed to create packet\n",
  2055. __func__);
  2056. goto err_create_pkt;
  2057. }
  2058. if (__iface_cmdq_write(dev, &pkt))
  2059. rc = -ENOTEMPTY;
  2060. } else {
  2061. return -EAGAIN;
  2062. }
  2063. err_create_pkt:
  2064. mutex_unlock(&dev->lock);
  2065. return rc;
  2066. }
  2067. static void __set_default_sys_properties(struct iris_hfi_device *device)
  2068. {
  2069. if (__sys_set_debug(device, msm_cvp_fw_debug))
  2070. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  2071. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  2072. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  2073. }
  2074. static void __session_clean(struct cvp_hal_session *session)
  2075. {
  2076. struct cvp_hal_session *temp, *next;
  2077. struct iris_hfi_device *device;
  2078. if (!session || !session->device) {
  2079. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  2080. return;
  2081. }
  2082. device = session->device;
  2083. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  2084. /*
  2085. * session might have been removed from the device list in
  2086. * core_release, so check and remove if it is in the list
  2087. */
  2088. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  2089. if (session == temp) {
  2090. list_del(&session->list);
  2091. break;
  2092. }
  2093. }
  2094. /* Poison the session handle with zeros */
  2095. *session = (struct cvp_hal_session){ {0} };
  2096. kfree(session);
  2097. }
  2098. static int iris_hfi_session_clean(void *session)
  2099. {
  2100. struct cvp_hal_session *sess_close;
  2101. struct iris_hfi_device *device;
  2102. if (!session) {
  2103. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2104. return -EINVAL;
  2105. }
  2106. sess_close = session;
  2107. device = sess_close->device;
  2108. if (!device) {
  2109. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  2110. return -EINVAL;
  2111. }
  2112. mutex_lock(&device->lock);
  2113. __session_clean(sess_close);
  2114. mutex_unlock(&device->lock);
  2115. return 0;
  2116. }
  2117. static int iris_debug_hook(void *device)
  2118. {
  2119. struct iris_hfi_device *dev = device;
  2120. u32 val;
  2121. if (!device) {
  2122. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  2123. return -ENODEV;
  2124. }
  2125. /******* FDU & MPU *****/
  2126. #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
  2127. #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94
  2128. #define CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE 0xA0
  2129. #define CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE 0xA4
  2130. #define CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE 0xA8
  2131. #define CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE 0xAC
  2132. val = __read_register(dev, CVP0_CVP_SS_FDU_SECURE_ENABLE);
  2133. dprintk(CVP_ERR, "FDU_SECURE_ENABLE %#x\n", val);
  2134. val = __read_register(dev, CVP0_CVP_SS_MPU_SECURE_ENABLE);
  2135. dprintk(CVP_ERR, "MPU_SECURE_ENABLE %#x\n", val);
  2136. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE);
  2137. dprintk(CVP_ERR, "ARP_THREAD_0_SECURE_ENABLE %#x\n", val);
  2138. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE);
  2139. dprintk(CVP_ERR, "ARP_THREAD_1_SECURE_ENABLE %#x\n", val);
  2140. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE);
  2141. dprintk(CVP_ERR, "ARP_THREAD_2_SECURE_ENABLE %#x\n", val);
  2142. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE);
  2143. dprintk(CVP_ERR, "ARP_THREAD_3_SECURE_ENABLE %#x\n", val);
  2144. if (true)
  2145. return 0;
  2146. /***** GCE *******
  2147. * Bit 0 of below register is CDM secure enable for GCE
  2148. * CDM buffer will be in CB4 if set
  2149. */
  2150. #define CVP_GCE_GCE_SS_CP_CTL 0x51100
  2151. /* STATUS bit0 && CFG bit 4 of below register set,
  2152. * expect pixel buffers in CB3,
  2153. * otherwise in CB0
  2154. * CFG bit 9:8 b01 -> LMC input in CB3
  2155. * CFG bit 9:8 b10 -> LMC input in CB4
  2156. */
  2157. #define CVP_GCE0_CP_STATUS 0x51080
  2158. #define CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG 0x52020
  2159. val = __read_register(dev, CVP_GCE_GCE_SS_CP_CTL);
  2160. dprintk(CVP_ERR, "CVP_GCE_GCE_SS_CP_CTL %#x\n", val);
  2161. val = __read_register(dev, CVP_GCE0_CP_STATUS);
  2162. dprintk(CVP_ERR, "CVP_GCE0_CP_STATUS %#x\n", val);
  2163. val = __read_register(dev, CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG);
  2164. dprintk(CVP_ERR, "CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2165. /***** RGE *****
  2166. * Bit 0 of below regiser is CDM secure enable for RGE
  2167. * CDM buffer to be in CB4 i fset
  2168. */
  2169. #define CVP_RGE0_TOPRGE_CP_CTL 0x31010
  2170. /* CFG bit 4 && IN bit 0:
  2171. * if both are set, expect CB3 or CB4 depending on IN 6:4 field
  2172. * either is clear, expect CB0
  2173. */
  2174. #define CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG 0x32020
  2175. #define CVP_RGE0_TOPSPARE_IN 0x311F4
  2176. val = __read_register(dev, CVP_RGE0_TOPRGE_CP_CTL);
  2177. dprintk(CVP_ERR, "CVP_RGE0_TOPRGE_CP_CTL %#x\n", val);
  2178. val = __read_register(dev, CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2179. dprintk(CVP_ERR, "CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2180. val = __read_register(dev, CVP_RGE0_TOPSPARE_IN);
  2181. dprintk(CVP_ERR, "CVP_RGE0_TOPSPARE_IN %#x\n", val);
  2182. /****** VADL ******
  2183. * Bit 0 of below register is CDM secure enable for VADL
  2184. * CDM buffer will bei in CB4 if set
  2185. */
  2186. #define CVP_VADL0_VADL_SS_CP_CTL 0x21010
  2187. /* Below registers are used the same way as RGE */
  2188. #define CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG 0x22020
  2189. #define CVP_VADL0_SPARE_IN 0x211F4
  2190. val = __read_register(dev, CVP_VADL0_VADL_SS_CP_CTL);
  2191. dprintk(CVP_ERR, "CVP_VADL0_VADL_SS_CP_CTL %#x\n", val);
  2192. val = __read_register(dev, CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2193. dprintk(CVP_ERR, "CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2194. val = __read_register(dev, CVP_VADL0_SPARE_IN);
  2195. dprintk(CVP_ERR, "CVP_VADL0_SPARE_IN %#x\n", val);
  2196. /****** ITOF *****
  2197. * Below registers are used the same way as RGE
  2198. */
  2199. #define CVP_ITOF0_TOF_SS_CP_CTL 0x41010
  2200. #define CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG 0x42020
  2201. #define CVP_ITOF0_TOF_SS_SPARE_IN 0x411F4
  2202. val = __read_register(dev, CVP_ITOF0_TOF_SS_CP_CTL);
  2203. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_CP_CTL %#x\n", val);
  2204. val = __read_register(dev, CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2205. dprintk(CVP_ERR, "CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2206. val = __read_register(dev, CVP_ITOF0_TOF_SS_SPARE_IN);
  2207. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_SPARE_IN %#x\n", val);
  2208. return 0;
  2209. }
  2210. static int iris_hfi_session_init(void *device, void *session_id,
  2211. void **new_session)
  2212. {
  2213. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  2214. struct iris_hfi_device *dev;
  2215. struct cvp_hal_session *s;
  2216. if (!device || !new_session) {
  2217. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  2218. return -EINVAL;
  2219. }
  2220. dev = device;
  2221. mutex_lock(&dev->lock);
  2222. s = kzalloc(sizeof(*s), GFP_KERNEL);
  2223. if (!s) {
  2224. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  2225. goto err_session_init_fail;
  2226. }
  2227. s->session_id = session_id;
  2228. s->device = dev;
  2229. dprintk(CVP_SESS,
  2230. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  2231. list_add_tail(&s->list, &dev->sess_head);
  2232. __set_default_sys_properties(device);
  2233. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  2234. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  2235. goto err_session_init_fail;
  2236. }
  2237. *new_session = s;
  2238. if (__iface_cmdq_write(dev, &pkt))
  2239. goto err_session_init_fail;
  2240. mutex_unlock(&dev->lock);
  2241. return 0;
  2242. err_session_init_fail:
  2243. if (s)
  2244. __session_clean(s);
  2245. *new_session = NULL;
  2246. mutex_unlock(&dev->lock);
  2247. return -EINVAL;
  2248. }
  2249. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  2250. {
  2251. struct cvp_hal_session_cmd_pkt pkt;
  2252. int rc = 0;
  2253. struct iris_hfi_device *device = session->device;
  2254. if (!__is_session_valid(device, session, __func__))
  2255. return -ECONNRESET;
  2256. rc = call_hfi_pkt_op(device, session_cmd,
  2257. &pkt, pkt_type, session);
  2258. if (rc == -EPERM)
  2259. return 0;
  2260. if (rc) {
  2261. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2262. goto err_create_pkt;
  2263. }
  2264. if (__iface_cmdq_write(session->device, &pkt))
  2265. rc = -ENOTEMPTY;
  2266. err_create_pkt:
  2267. return rc;
  2268. }
  2269. static int iris_hfi_session_end(void *session)
  2270. {
  2271. struct cvp_hal_session *sess;
  2272. struct iris_hfi_device *device;
  2273. int rc = 0;
  2274. if (!session) {
  2275. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2276. return -EINVAL;
  2277. }
  2278. sess = session;
  2279. device = sess->device;
  2280. if (!device) {
  2281. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2282. return -EINVAL;
  2283. }
  2284. mutex_lock(&device->lock);
  2285. if (msm_cvp_fw_coverage) {
  2286. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2287. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2288. }
  2289. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2290. mutex_unlock(&device->lock);
  2291. return rc;
  2292. }
  2293. static int iris_hfi_session_abort(void *sess)
  2294. {
  2295. struct cvp_hal_session *session = sess;
  2296. struct iris_hfi_device *device;
  2297. int rc = 0;
  2298. if (!session || !session->device) {
  2299. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2300. return -EINVAL;
  2301. }
  2302. device = session->device;
  2303. mutex_lock(&device->lock);
  2304. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2305. mutex_unlock(&device->lock);
  2306. return rc;
  2307. }
  2308. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2309. {
  2310. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2311. int rc = 0;
  2312. struct cvp_hal_session *session = sess;
  2313. struct iris_hfi_device *device;
  2314. if (!session || !session->device || !iova || !size) {
  2315. dprintk(CVP_ERR, "Invalid Params\n");
  2316. return -EINVAL;
  2317. }
  2318. device = session->device;
  2319. mutex_lock(&device->lock);
  2320. if (!__is_session_valid(device, session, __func__)) {
  2321. rc = -ECONNRESET;
  2322. goto err_create_pkt;
  2323. }
  2324. rc = call_hfi_pkt_op(device, session_set_buffers,
  2325. &pkt, session, iova, size);
  2326. if (rc) {
  2327. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2328. goto err_create_pkt;
  2329. }
  2330. if (__iface_cmdq_write(session->device, &pkt))
  2331. rc = -ENOTEMPTY;
  2332. err_create_pkt:
  2333. mutex_unlock(&device->lock);
  2334. return rc;
  2335. }
  2336. static int iris_hfi_session_release_buffers(void *sess)
  2337. {
  2338. struct cvp_session_release_buffers_packet pkt;
  2339. int rc = 0;
  2340. struct cvp_hal_session *session = sess;
  2341. struct iris_hfi_device *device;
  2342. if (!session || !session->device) {
  2343. dprintk(CVP_ERR, "Invalid Params\n");
  2344. return -EINVAL;
  2345. }
  2346. device = session->device;
  2347. mutex_lock(&device->lock);
  2348. if (!__is_session_valid(device, session, __func__)) {
  2349. rc = -ECONNRESET;
  2350. goto err_create_pkt;
  2351. }
  2352. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2353. if (rc) {
  2354. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2355. goto err_create_pkt;
  2356. }
  2357. if (__iface_cmdq_write(session->device, &pkt))
  2358. rc = -ENOTEMPTY;
  2359. err_create_pkt:
  2360. mutex_unlock(&device->lock);
  2361. return rc;
  2362. }
  2363. static int iris_hfi_session_send(void *sess,
  2364. struct eva_kmd_hfi_packet *in_pkt)
  2365. {
  2366. int rc = 0;
  2367. struct eva_kmd_hfi_packet pkt;
  2368. struct cvp_hal_session *session = sess;
  2369. struct iris_hfi_device *device;
  2370. if (!session || !session->device) {
  2371. dprintk(CVP_ERR, "invalid session");
  2372. return -ENODEV;
  2373. }
  2374. device = session->device;
  2375. mutex_lock(&device->lock);
  2376. if (!__is_session_valid(device, session, __func__)) {
  2377. rc = -ECONNRESET;
  2378. goto err_send_pkt;
  2379. }
  2380. rc = call_hfi_pkt_op(device, session_send,
  2381. &pkt, session, in_pkt);
  2382. if (rc) {
  2383. dprintk(CVP_ERR,
  2384. "failed to create pkt\n");
  2385. goto err_send_pkt;
  2386. }
  2387. if (__iface_cmdq_write(session->device, &pkt))
  2388. rc = -ENOTEMPTY;
  2389. err_send_pkt:
  2390. mutex_unlock(&device->lock);
  2391. return rc;
  2392. return rc;
  2393. }
  2394. static int iris_hfi_session_flush(void *sess)
  2395. {
  2396. struct cvp_hal_session *session = sess;
  2397. struct iris_hfi_device *device;
  2398. int rc = 0;
  2399. if (!session || !session->device) {
  2400. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2401. return -EINVAL;
  2402. }
  2403. device = session->device;
  2404. mutex_lock(&device->lock);
  2405. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2406. mutex_unlock(&device->lock);
  2407. return rc;
  2408. }
  2409. static int iris_hfi_session_start(void *sess)
  2410. {
  2411. struct cvp_hal_session *session = sess;
  2412. struct iris_hfi_device *device;
  2413. int rc = 0;
  2414. if (!session || !session->device) {
  2415. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2416. return -EINVAL;
  2417. }
  2418. device = session->device;
  2419. mutex_lock(&device->lock);
  2420. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_START);
  2421. mutex_unlock(&device->lock);
  2422. return rc;
  2423. }
  2424. static int iris_hfi_session_stop(void *sess)
  2425. {
  2426. struct cvp_hal_session *session = sess;
  2427. struct iris_hfi_device *device;
  2428. int rc = 0;
  2429. if (!session || !session->device) {
  2430. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2431. return -EINVAL;
  2432. }
  2433. device = session->device;
  2434. mutex_lock(&device->lock);
  2435. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_STOP);
  2436. mutex_unlock(&device->lock);
  2437. return rc;
  2438. }
  2439. static void __process_fatal_error(
  2440. struct iris_hfi_device *device)
  2441. {
  2442. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2443. cmd_done.device_id = device->device_id;
  2444. device->callback(HAL_SYS_ERROR, &cmd_done);
  2445. }
  2446. static int __prepare_pc(struct iris_hfi_device *device)
  2447. {
  2448. int rc = 0;
  2449. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2450. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2451. if (rc) {
  2452. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2453. goto err_pc_prep;
  2454. }
  2455. if (__iface_cmdq_write(device, &pkt))
  2456. rc = -ENOTEMPTY;
  2457. if (rc)
  2458. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2459. err_pc_prep:
  2460. return rc;
  2461. }
  2462. static void iris_hfi_pm_handler(struct work_struct *work)
  2463. {
  2464. int rc = 0;
  2465. struct msm_cvp_core *core;
  2466. struct iris_hfi_device *device;
  2467. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2468. if (core)
  2469. device = core->device->hfi_device_data;
  2470. else
  2471. return;
  2472. if (!device) {
  2473. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2474. return;
  2475. }
  2476. dprintk(CVP_PWR,
  2477. "Entering %s\n", __func__);
  2478. /*
  2479. * It is ok to check this variable outside the lock since
  2480. * it is being updated in this context only
  2481. */
  2482. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2483. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2484. device->skip_pc_count);
  2485. device->skip_pc_count = 0;
  2486. __process_fatal_error(device);
  2487. return;
  2488. }
  2489. mutex_lock(&device->lock);
  2490. if (gfa_cv.state == DSP_SUSPEND)
  2491. rc = __power_collapse(device, true);
  2492. else
  2493. rc = __power_collapse(device, false);
  2494. mutex_unlock(&device->lock);
  2495. switch (rc) {
  2496. case 0:
  2497. device->skip_pc_count = 0;
  2498. /* Cancel pending delayed works if any */
  2499. cancel_delayed_work(&iris_hfi_pm_work);
  2500. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2501. __func__);
  2502. break;
  2503. case -EBUSY:
  2504. device->skip_pc_count = 0;
  2505. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2506. queue_delayed_work(device->iris_pm_workq,
  2507. &iris_hfi_pm_work, msecs_to_jiffies(
  2508. device->res->msm_cvp_pwr_collapse_delay));
  2509. break;
  2510. case -EAGAIN:
  2511. device->skip_pc_count++;
  2512. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2513. __func__, device->skip_pc_count);
  2514. queue_delayed_work(device->iris_pm_workq,
  2515. &iris_hfi_pm_work, msecs_to_jiffies(
  2516. device->res->msm_cvp_pwr_collapse_delay));
  2517. break;
  2518. default:
  2519. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2520. break;
  2521. }
  2522. }
  2523. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2524. {
  2525. int rc = 0;
  2526. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2527. int count = 0;
  2528. const int max_tries = 150;
  2529. if (!device) {
  2530. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2531. return -EINVAL;
  2532. }
  2533. if (!device->power_enabled) {
  2534. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2535. __func__);
  2536. goto exit;
  2537. }
  2538. rc = __core_in_valid_state(device);
  2539. if (!rc) {
  2540. dprintk(CVP_WARN,
  2541. "Core is in bad state, Skipping power collapse\n");
  2542. return -EINVAL;
  2543. }
  2544. rc = __dsp_suspend(device, force);
  2545. if (rc == -EBUSY)
  2546. goto exit;
  2547. else if (rc)
  2548. goto skip_power_off;
  2549. __flush_debug_queue(device, device->raw_packet);
  2550. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2551. CVP_CTRL_STATUS_PC_READY;
  2552. if (!pc_ready) {
  2553. wfi_status = __read_register(device,
  2554. CVP_WRAPPER_CPU_STATUS);
  2555. idle_status = __read_register(device,
  2556. CVP_CTRL_STATUS);
  2557. if (!(wfi_status & BIT(0))) {
  2558. dprintk(CVP_WARN,
  2559. "Skipping PC as wfi_status (%#x) bit not set\n",
  2560. wfi_status);
  2561. goto skip_power_off;
  2562. }
  2563. if (!(idle_status & BIT(30))) {
  2564. dprintk(CVP_WARN,
  2565. "Skipping PC as idle_status (%#x) bit not set\n",
  2566. idle_status);
  2567. goto skip_power_off;
  2568. }
  2569. rc = __prepare_pc(device);
  2570. if (rc) {
  2571. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2572. goto skip_power_off;
  2573. }
  2574. while (count < max_tries) {
  2575. wfi_status = __read_register(device,
  2576. CVP_WRAPPER_CPU_STATUS);
  2577. pc_ready = __read_register(device,
  2578. CVP_CTRL_STATUS);
  2579. if ((wfi_status & BIT(0)) && (pc_ready &
  2580. CVP_CTRL_STATUS_PC_READY))
  2581. break;
  2582. usleep_range(150, 250);
  2583. count++;
  2584. }
  2585. if (count == max_tries) {
  2586. dprintk(CVP_ERR,
  2587. "Skip PC. Core is not ready (%#x, %#x)\n",
  2588. wfi_status, pc_ready);
  2589. goto skip_power_off;
  2590. }
  2591. } else {
  2592. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  2593. if (!(wfi_status & BIT(0))) {
  2594. dprintk(CVP_WARN,
  2595. "Skip PC as wfi_status (%#x) bit not set\n",
  2596. wfi_status);
  2597. goto skip_power_off;
  2598. }
  2599. }
  2600. rc = __suspend(device);
  2601. if (rc)
  2602. dprintk(CVP_ERR, "Failed __suspend\n");
  2603. exit:
  2604. return rc;
  2605. skip_power_off:
  2606. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2607. wfi_status, idle_status, pc_ready);
  2608. __flush_debug_queue(device, device->raw_packet);
  2609. return -EAGAIN;
  2610. }
  2611. static void __process_sys_error(struct iris_hfi_device *device)
  2612. {
  2613. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2614. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2615. if (vsfr) {
  2616. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2617. /*
  2618. * SFR isn't guaranteed to be NULL terminated
  2619. * since SYS_ERROR indicates that Iris is in the
  2620. * process of crashing.
  2621. */
  2622. if (p == NULL)
  2623. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2624. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2625. vsfr->rg_data);
  2626. }
  2627. }
  2628. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2629. {
  2630. bool local_packet = false;
  2631. enum cvp_msg_prio log_level = CVP_FW;
  2632. if (!device) {
  2633. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2634. return;
  2635. }
  2636. if (!packet) {
  2637. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2638. if (!packet) {
  2639. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2640. __func__);
  2641. return;
  2642. }
  2643. local_packet = true;
  2644. /*
  2645. * Local packek is used when something FATAL occurred.
  2646. * It is good to print these logs by default.
  2647. */
  2648. log_level = CVP_ERR;
  2649. }
  2650. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2651. if (pkt_size < pkt_hdr_size || \
  2652. payload_size < MIN_PAYLOAD_SIZE || \
  2653. payload_size > \
  2654. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2655. dprintk(CVP_ERR, \
  2656. "%s: invalid msg size - %d\n", \
  2657. __func__, pkt->msg_size); \
  2658. continue; \
  2659. } \
  2660. })
  2661. while (!__iface_dbgq_read(device, packet)) {
  2662. struct cvp_hfi_packet_header *pkt =
  2663. (struct cvp_hfi_packet_header *) packet;
  2664. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2665. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2666. __func__);
  2667. continue;
  2668. }
  2669. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2670. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2671. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2672. SKIP_INVALID_PKT(pkt->size,
  2673. pkt->msg_size, sizeof(*pkt));
  2674. /*
  2675. * All fw messages starts with new line character. This
  2676. * causes dprintk to print this message in two lines
  2677. * in the kernel log. Ignoring the first character
  2678. * from the message fixes this to print it in a single
  2679. * line.
  2680. */
  2681. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2682. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2683. }
  2684. }
  2685. #undef SKIP_INVALID_PKT
  2686. if (local_packet)
  2687. kfree(packet);
  2688. }
  2689. static bool __is_session_valid(struct iris_hfi_device *device,
  2690. struct cvp_hal_session *session, const char *func)
  2691. {
  2692. struct cvp_hal_session *temp = NULL;
  2693. if (!device || !session)
  2694. goto invalid;
  2695. list_for_each_entry(temp, &device->sess_head, list)
  2696. if (session == temp)
  2697. return true;
  2698. invalid:
  2699. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2700. func, device, session);
  2701. return false;
  2702. }
  2703. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2704. u32 session_id)
  2705. {
  2706. struct cvp_hal_session *temp = NULL;
  2707. list_for_each_entry(temp, &device->sess_head, list) {
  2708. if (session_id == hash32_ptr(temp))
  2709. return temp;
  2710. }
  2711. return NULL;
  2712. }
  2713. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2714. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2715. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2716. static void process_system_msg(struct msm_cvp_cb_info *info,
  2717. struct iris_hfi_device *device,
  2718. void *raw_packet)
  2719. {
  2720. struct cvp_hal_sys_init_done sys_init_done = {0};
  2721. switch (info->response_type) {
  2722. case HAL_SYS_ERROR:
  2723. __process_sys_error(device);
  2724. break;
  2725. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2726. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2727. break;
  2728. case HAL_SYS_INIT_DONE:
  2729. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2730. sys_init_done.capabilities =
  2731. device->sys_init_capabilities;
  2732. cvp_hfi_process_sys_init_done_prop_read(
  2733. (struct cvp_hfi_msg_sys_init_done_packet *)
  2734. raw_packet, &sys_init_done);
  2735. info->response.cmd.data.sys_init_done = sys_init_done;
  2736. break;
  2737. default:
  2738. break;
  2739. }
  2740. }
  2741. static void **get_session_id(struct msm_cvp_cb_info *info)
  2742. {
  2743. void **session_id = NULL;
  2744. /* For session-related packets, validate session */
  2745. switch (info->response_type) {
  2746. case HAL_SESSION_INIT_DONE:
  2747. case HAL_SESSION_END_DONE:
  2748. case HAL_SESSION_ABORT_DONE:
  2749. case HAL_SESSION_START_DONE:
  2750. case HAL_SESSION_STOP_DONE:
  2751. case HAL_SESSION_FLUSH_DONE:
  2752. case HAL_SESSION_SET_BUFFER_DONE:
  2753. case HAL_SESSION_SUSPEND_DONE:
  2754. case HAL_SESSION_RESUME_DONE:
  2755. case HAL_SESSION_SET_PROP_DONE:
  2756. case HAL_SESSION_GET_PROP_DONE:
  2757. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2758. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2759. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2760. case HAL_SESSION_PROPERTY_INFO:
  2761. case HAL_SESSION_EVENT_CHANGE:
  2762. case HAL_SESSION_DUMP_NOTIFY:
  2763. session_id = &info->response.cmd.session_id;
  2764. break;
  2765. case HAL_SESSION_ERROR:
  2766. session_id = &info->response.data.session_id;
  2767. break;
  2768. case HAL_RESPONSE_UNUSED:
  2769. default:
  2770. session_id = NULL;
  2771. break;
  2772. }
  2773. return session_id;
  2774. }
  2775. static void print_msg_hdr(void *hdr)
  2776. {
  2777. struct cvp_hfi_msg_session_hdr *new_hdr =
  2778. (struct cvp_hfi_msg_session_hdr *)hdr;
  2779. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x %#llx\n",
  2780. new_hdr->size, new_hdr->packet_type,
  2781. new_hdr->session_id,
  2782. new_hdr->client_data.transaction_id,
  2783. new_hdr->client_data.data1,
  2784. new_hdr->client_data.data2,
  2785. new_hdr->error_type,
  2786. new_hdr->client_data.kdata);
  2787. }
  2788. static int __response_handler(struct iris_hfi_device *device)
  2789. {
  2790. struct msm_cvp_cb_info *packets;
  2791. int packet_count = 0;
  2792. u8 *raw_packet = NULL;
  2793. bool requeue_pm_work = true;
  2794. if (!device || device->state != IRIS_STATE_INIT)
  2795. return 0;
  2796. packets = device->response_pkt;
  2797. raw_packet = device->raw_packet;
  2798. if (!raw_packet || !packets) {
  2799. dprintk(CVP_ERR,
  2800. "%s: Invalid args : Res pkt = %pK, Raw pkt = %pK\n",
  2801. __func__, packets, raw_packet);
  2802. return 0;
  2803. }
  2804. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2805. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2806. device->sfr.align_virtual_addr;
  2807. struct msm_cvp_cb_info info = {
  2808. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2809. .response.cmd = {
  2810. .device_id = device->device_id,
  2811. }
  2812. };
  2813. if (vsfr)
  2814. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2815. vsfr->rg_data);
  2816. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2817. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2818. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2819. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2820. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2821. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2822. packets[packet_count++] = info;
  2823. goto exit;
  2824. }
  2825. /* Bleed the msg queue dry of packets */
  2826. while (!__iface_msgq_read(device, raw_packet)) {
  2827. void **session_id = NULL;
  2828. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2829. struct cvp_hfi_msg_session_hdr *hdr =
  2830. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2831. int rc = 0;
  2832. print_msg_hdr(hdr);
  2833. rc = cvp_hfi_process_msg_packet(device->device_id,
  2834. raw_packet, info);
  2835. if (rc) {
  2836. dprintk(CVP_WARN,
  2837. "Corrupt/unknown packet found, discarding\n");
  2838. --packet_count;
  2839. continue;
  2840. } else if (info->response_type == HAL_NO_RESP) {
  2841. --packet_count;
  2842. continue;
  2843. }
  2844. /* Process the packet types that we're interested in */
  2845. process_system_msg(info, device, raw_packet);
  2846. session_id = get_session_id(info);
  2847. /*
  2848. * hfi_process_msg_packet provides a session_id that's a hashed
  2849. * value of struct cvp_hal_session, we need to coerce the hashed
  2850. * value back to pointer that we can use. Ideally, hfi_process\
  2851. * _msg_packet should take care of this, but it doesn't have
  2852. * required information for it
  2853. */
  2854. if (session_id) {
  2855. struct cvp_hal_session *session = NULL;
  2856. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2857. dprintk(CVP_ERR,
  2858. "Upper 32-bits != 0 for sess_id=%pK\n",
  2859. *session_id);
  2860. }
  2861. session = __get_session(device,
  2862. (u32)(uintptr_t)*session_id);
  2863. if (!session) {
  2864. dprintk(CVP_ERR, _INVALID_MSG_,
  2865. info->response_type,
  2866. *session_id);
  2867. --packet_count;
  2868. continue;
  2869. }
  2870. *session_id = session->session_id;
  2871. }
  2872. if (packet_count >= cvp_max_packets) {
  2873. dprintk(CVP_WARN,
  2874. "Too many packets in message queue!\n");
  2875. break;
  2876. }
  2877. /* do not read packets after sys error packet */
  2878. if (info->response_type == HAL_SYS_ERROR)
  2879. break;
  2880. }
  2881. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2882. cancel_delayed_work(&iris_hfi_pm_work);
  2883. if (!queue_delayed_work(device->iris_pm_workq,
  2884. &iris_hfi_pm_work,
  2885. msecs_to_jiffies(
  2886. device->res->msm_cvp_pwr_collapse_delay))) {
  2887. dprintk(CVP_ERR, "PM work already scheduled\n");
  2888. }
  2889. }
  2890. exit:
  2891. __flush_debug_queue(device, raw_packet);
  2892. return packet_count;
  2893. }
  2894. static void iris_hfi_core_work_handler(struct work_struct *work)
  2895. {
  2896. struct msm_cvp_core *core;
  2897. struct iris_hfi_device *device;
  2898. int num_responses = 0, i = 0;
  2899. u32 intr_status;
  2900. static bool warning_on = true;
  2901. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2902. if (core)
  2903. device = core->device->hfi_device_data;
  2904. else
  2905. return;
  2906. mutex_lock(&device->lock);
  2907. if (!__core_in_valid_state(device)) {
  2908. if (warning_on) {
  2909. dprintk(CVP_WARN, "%s Core not in init state\n",
  2910. __func__);
  2911. warning_on = false;
  2912. }
  2913. goto err_no_work;
  2914. }
  2915. warning_on = true;
  2916. if (!device->callback) {
  2917. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  2918. device);
  2919. goto err_no_work;
  2920. }
  2921. if (__resume(device)) {
  2922. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  2923. goto err_no_work;
  2924. }
  2925. __core_clear_interrupt(device);
  2926. num_responses = __response_handler(device);
  2927. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  2928. __func__, num_responses);
  2929. err_no_work:
  2930. /* Keep the interrupt status before releasing device lock */
  2931. intr_status = device->intr_status;
  2932. mutex_unlock(&device->lock);
  2933. /*
  2934. * Issue the callbacks outside of the locked contex to preserve
  2935. * re-entrancy.
  2936. */
  2937. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  2938. i < num_responses; ++i) {
  2939. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  2940. void *rsp = (void *)&r->response;
  2941. if (!__core_in_valid_state(device)) {
  2942. dprintk(CVP_ERR,
  2943. _INVALID_STATE_, (i + 1), num_responses);
  2944. break;
  2945. }
  2946. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  2947. (i + 1), num_responses, r->response_type);
  2948. device->callback(r->response_type, rsp);
  2949. }
  2950. /* We need re-enable the irq which was disabled in ISR handler */
  2951. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  2952. enable_irq(device->cvp_hal_data->irq);
  2953. /*
  2954. * XXX: Don't add any code beyond here. Reacquiring locks after release
  2955. * it above doesn't guarantee the atomicity that we're aiming for.
  2956. */
  2957. }
  2958. static DECLARE_WORK(iris_hfi_work, iris_hfi_core_work_handler);
  2959. irqreturn_t cvp_hfi_isr(int irq, void *dev)
  2960. {
  2961. struct iris_hfi_device *device = dev;
  2962. disable_irq_nosync(irq);
  2963. queue_work(device->cvp_workq, &iris_hfi_work);
  2964. return IRQ_HANDLED;
  2965. }
  2966. static void iris_hfi_wd_work_handler(struct work_struct *work)
  2967. {
  2968. struct msm_cvp_core *core;
  2969. struct iris_hfi_device *device;
  2970. struct msm_cvp_cb_cmd_done response = {0};
  2971. enum hal_command_response cmd = HAL_SYS_WATCHDOG_TIMEOUT;
  2972. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2973. if (core)
  2974. device = core->device->hfi_device_data;
  2975. else
  2976. return;
  2977. if (msm_cvp_hw_wd_recovery) {
  2978. dprintk(CVP_ERR, "Cleaning up as HW WD recovery is enable %d\n",
  2979. msm_cvp_hw_wd_recovery);
  2980. response.device_id = device->device_id;
  2981. handle_sys_error(cmd, (void *) &response);
  2982. enable_irq(device->cvp_hal_data->irq_wd);
  2983. }
  2984. else {
  2985. dprintk(CVP_ERR, "Crashing the device as HW WD recovery is disable %d\n",
  2986. msm_cvp_hw_wd_recovery);
  2987. BUG_ON(1);
  2988. }
  2989. }
  2990. static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
  2991. irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
  2992. {
  2993. struct iris_hfi_device *device = dev;
  2994. dprintk(CVP_ERR, "Got HW WDOG IRQ! \n");
  2995. disable_irq_nosync(irq);
  2996. queue_work(device->cvp_workq, &iris_hfi_wd_work);
  2997. return IRQ_HANDLED;
  2998. }
  2999. static int __init_reset_clk(struct msm_cvp_platform_resources *res,
  3000. int reset_index)
  3001. {
  3002. int rc = 0;
  3003. struct reset_control *rst;
  3004. struct reset_info *rst_info;
  3005. struct reset_set *rst_set = &res->reset_set;
  3006. if (!rst_set->reset_tbl)
  3007. return 0;
  3008. rst_info = &rst_set->reset_tbl[reset_index];
  3009. rst = rst_info->rst;
  3010. dprintk(CVP_PWR, "reset_clk: name %s rst %pK required_stage=%d\n",
  3011. rst_set->reset_tbl[reset_index].name, rst, rst_info->required_stage);
  3012. if (rst)
  3013. goto skip_reset_init;
  3014. if (rst_info->required_stage == CVP_ON_USE) {
  3015. rst = reset_control_get_exclusive_released(&res->pdev->dev,
  3016. rst_set->reset_tbl[reset_index].name);
  3017. if (IS_ERR(rst)) {
  3018. rc = PTR_ERR(rst);
  3019. dprintk(CVP_ERR, "reset get exclusive fail %d\n", rc);
  3020. return rc;
  3021. }
  3022. dprintk(CVP_PWR, "reset_clk: name %s get exclusive rst %llx\n",
  3023. rst_set->reset_tbl[reset_index].name, rst);
  3024. } else if (rst_info->required_stage == CVP_ON_INIT) {
  3025. rst = devm_reset_control_get(&res->pdev->dev,
  3026. rst_set->reset_tbl[reset_index].name);
  3027. if (IS_ERR(rst)) {
  3028. rc = PTR_ERR(rst);
  3029. dprintk(CVP_ERR, "reset get fail %d\n", rc);
  3030. return rc;
  3031. }
  3032. dprintk(CVP_PWR, "reset_clk: name %s get rst %llx\n",
  3033. rst_set->reset_tbl[reset_index].name, rst);
  3034. } else {
  3035. dprintk(CVP_ERR, "Invalid reset stage\n");
  3036. return -EINVAL;
  3037. }
  3038. rst_set->reset_tbl[reset_index].rst = rst;
  3039. rst_info->state = RESET_INIT;
  3040. return 0;
  3041. skip_reset_init:
  3042. return rc;
  3043. }
  3044. static int __reset_control_assert_name(struct iris_hfi_device *device,
  3045. const char *name)
  3046. {
  3047. struct reset_info *rcinfo = NULL;
  3048. int rc = 0;
  3049. bool found = false;
  3050. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3051. if (strcmp(rcinfo->name, name))
  3052. continue;
  3053. found = true;
  3054. rc = reset_control_assert(rcinfo->rst);
  3055. if (rc)
  3056. dprintk(CVP_ERR,
  3057. "%s: failed to assert reset control (%s), rc = %d\n",
  3058. __func__, rcinfo->name, rc);
  3059. else
  3060. dprintk(CVP_PWR, "%s: assert reset control (%s)\n",
  3061. __func__, rcinfo->name);
  3062. break;
  3063. }
  3064. if (!found) {
  3065. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3066. __func__, name);
  3067. rc = -EINVAL;
  3068. }
  3069. return rc;
  3070. }
  3071. static int __reset_control_deassert_name(struct iris_hfi_device *device,
  3072. const char *name)
  3073. {
  3074. struct reset_info *rcinfo = NULL;
  3075. int rc = 0;
  3076. bool found = false;
  3077. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3078. if (strcmp(rcinfo->name, name))
  3079. continue;
  3080. found = true;
  3081. rc = reset_control_deassert(rcinfo->rst);
  3082. if (rc)
  3083. dprintk(CVP_ERR,
  3084. "%s: deassert reset control for (%s) failed, rc %d\n",
  3085. __func__, rcinfo->name, rc);
  3086. else
  3087. dprintk(CVP_PWR, "%s: deassert reset control (%s)\n",
  3088. __func__, rcinfo->name);
  3089. break;
  3090. }
  3091. if (!found) {
  3092. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3093. __func__, name);
  3094. rc = -EINVAL;
  3095. }
  3096. return rc;
  3097. }
  3098. static int __reset_control_acquire(struct iris_hfi_device *device,
  3099. const char *name)
  3100. {
  3101. struct reset_info *rcinfo = NULL;
  3102. int rc = 0;
  3103. bool found = false;
  3104. int max_retries = 10;
  3105. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3106. if (strcmp(rcinfo->name, name))
  3107. continue;
  3108. found = true;
  3109. if (rcinfo->state == RESET_ACQUIRED)
  3110. return rc;
  3111. acquire_again:
  3112. rc = reset_control_acquire(rcinfo->rst);
  3113. if (rc) {
  3114. if (rc == -EBUSY) {
  3115. usleep_range(500, 1000);
  3116. max_retries--;
  3117. if (max_retries) {
  3118. goto acquire_again;
  3119. } else {
  3120. dprintk(CVP_ERR,
  3121. "%s acquire %s -EBUSY\n",
  3122. __func__, rcinfo->name);
  3123. rc = -EINVAL;
  3124. }
  3125. } else {
  3126. dprintk(CVP_ERR,
  3127. "%s: acquire failed (%s) rc %d\n",
  3128. __func__, rcinfo->name, rc);
  3129. rc = -EINVAL;
  3130. }
  3131. } else {
  3132. dprintk(CVP_PWR, "%s: reset acquire succeed (%s)\n",
  3133. __func__, rcinfo->name);
  3134. rcinfo->state = RESET_ACQUIRED;
  3135. }
  3136. break;
  3137. }
  3138. if (!found) {
  3139. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3140. __func__, name);
  3141. rc = -EINVAL;
  3142. }
  3143. return rc;
  3144. }
  3145. static int __reset_control_release(struct iris_hfi_device *device,
  3146. const char *name)
  3147. {
  3148. struct reset_info *rcinfo = NULL;
  3149. int rc = 0;
  3150. bool found = false;
  3151. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3152. if (strcmp(rcinfo->name, name))
  3153. continue;
  3154. found = true;
  3155. if (rcinfo->state != RESET_ACQUIRED) {
  3156. dprintk(CVP_WARN, "Double releasing reset clk?\n");
  3157. return -EINVAL;
  3158. }
  3159. reset_control_release(rcinfo->rst);
  3160. dprintk(CVP_PWR, "%s: reset release succeed (%s)\n",
  3161. __func__, rcinfo->name);
  3162. rcinfo->state = RESET_RELEASED;
  3163. break;
  3164. }
  3165. if (!found) {
  3166. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3167. __func__, name);
  3168. rc = -EINVAL;
  3169. }
  3170. return rc;
  3171. }
  3172. static void __deinit_bus(struct iris_hfi_device *device)
  3173. {
  3174. struct bus_info *bus = NULL;
  3175. if (!device)
  3176. return;
  3177. kfree(device->bus_vote.data);
  3178. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  3179. iris_hfi_for_each_bus_reverse(device, bus) {
  3180. dev_set_drvdata(bus->dev, NULL);
  3181. icc_put(bus->client);
  3182. bus->client = NULL;
  3183. }
  3184. }
  3185. static int __init_bus(struct iris_hfi_device *device)
  3186. {
  3187. struct bus_info *bus = NULL;
  3188. int rc = 0;
  3189. if (!device)
  3190. return -EINVAL;
  3191. iris_hfi_for_each_bus(device, bus) {
  3192. /*
  3193. * This is stupid, but there's no other easy way to ahold
  3194. * of struct bus_info in iris_hfi_devfreq_*()
  3195. */
  3196. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  3197. dev_name(bus->dev));
  3198. dev_set_drvdata(bus->dev, device);
  3199. bus->client = icc_get(&device->res->pdev->dev,
  3200. bus->master, bus->slave);
  3201. if (IS_ERR_OR_NULL(bus->client)) {
  3202. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  3203. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  3204. bus->name, rc);
  3205. bus->client = NULL;
  3206. goto err_add_dev;
  3207. }
  3208. }
  3209. return 0;
  3210. err_add_dev:
  3211. __deinit_bus(device);
  3212. return rc;
  3213. }
  3214. static void __deinit_regulators(struct iris_hfi_device *device)
  3215. {
  3216. struct regulator_info *rinfo = NULL;
  3217. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3218. if (rinfo->regulator) {
  3219. regulator_put(rinfo->regulator);
  3220. rinfo->regulator = NULL;
  3221. }
  3222. }
  3223. }
  3224. static int __init_regulators(struct iris_hfi_device *device)
  3225. {
  3226. int rc = 0;
  3227. struct regulator_info *rinfo = NULL;
  3228. iris_hfi_for_each_regulator(device, rinfo) {
  3229. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3230. rinfo->name);
  3231. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3232. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3233. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3234. rinfo->name);
  3235. rinfo->regulator = NULL;
  3236. goto err_reg_get;
  3237. }
  3238. }
  3239. return 0;
  3240. err_reg_get:
  3241. __deinit_regulators(device);
  3242. return rc;
  3243. }
  3244. static void __deinit_subcaches(struct iris_hfi_device *device)
  3245. {
  3246. struct subcache_info *sinfo = NULL;
  3247. if (!device) {
  3248. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3249. device);
  3250. goto exit;
  3251. }
  3252. if (!is_sys_cache_present(device))
  3253. goto exit;
  3254. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3255. if (sinfo->subcache) {
  3256. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3257. sinfo->name);
  3258. llcc_slice_putd(sinfo->subcache);
  3259. sinfo->subcache = NULL;
  3260. }
  3261. }
  3262. exit:
  3263. return;
  3264. }
  3265. static int __init_subcaches(struct iris_hfi_device *device)
  3266. {
  3267. int rc = 0;
  3268. struct subcache_info *sinfo = NULL;
  3269. if (!device) {
  3270. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3271. device);
  3272. return -EINVAL;
  3273. }
  3274. if (!is_sys_cache_present(device))
  3275. return 0;
  3276. iris_hfi_for_each_subcache(device, sinfo) {
  3277. if (!strcmp("cvp", sinfo->name)) {
  3278. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3279. } else if (!strcmp("cvpfw", sinfo->name)) {
  3280. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3281. } else {
  3282. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3283. sinfo->name);
  3284. }
  3285. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3286. rc = PTR_ERR(sinfo->subcache) ?
  3287. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3288. dprintk(CVP_ERR,
  3289. "init_subcaches: invalid subcache: %s rc %d\n",
  3290. sinfo->name, rc);
  3291. sinfo->subcache = NULL;
  3292. goto err_subcache_get;
  3293. }
  3294. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3295. sinfo->name);
  3296. }
  3297. return 0;
  3298. err_subcache_get:
  3299. __deinit_subcaches(device);
  3300. return rc;
  3301. }
  3302. static int __init_resources(struct iris_hfi_device *device,
  3303. struct msm_cvp_platform_resources *res)
  3304. {
  3305. int i, rc = 0;
  3306. rc = __init_regulators(device);
  3307. if (rc) {
  3308. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3309. return -ENODEV;
  3310. }
  3311. rc = msm_cvp_init_clocks(device);
  3312. if (rc) {
  3313. dprintk(CVP_ERR, "Failed to init clocks\n");
  3314. rc = -ENODEV;
  3315. goto err_init_clocks;
  3316. }
  3317. for (i = 0; i < device->res->reset_set.count; i++) {
  3318. rc = __init_reset_clk(res, i);
  3319. if (rc) {
  3320. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3321. rc = -ENODEV;
  3322. goto err_init_reset_clk;
  3323. }
  3324. }
  3325. rc = __init_bus(device);
  3326. if (rc) {
  3327. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3328. goto err_init_bus;
  3329. }
  3330. rc = __init_subcaches(device);
  3331. if (rc)
  3332. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3333. device->sys_init_capabilities =
  3334. kzalloc(sizeof(struct msm_cvp_capability)
  3335. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3336. return rc;
  3337. err_init_reset_clk:
  3338. err_init_bus:
  3339. msm_cvp_deinit_clocks(device);
  3340. err_init_clocks:
  3341. __deinit_regulators(device);
  3342. return rc;
  3343. }
  3344. static void __deinit_resources(struct iris_hfi_device *device)
  3345. {
  3346. __deinit_subcaches(device);
  3347. __deinit_bus(device);
  3348. msm_cvp_deinit_clocks(device);
  3349. __deinit_regulators(device);
  3350. kfree(device->sys_init_capabilities);
  3351. device->sys_init_capabilities = NULL;
  3352. }
  3353. static int __disable_regulator_impl(struct regulator_info *rinfo,
  3354. struct iris_hfi_device *device)
  3355. {
  3356. int rc = 0;
  3357. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3358. /*
  3359. * This call is needed. Driver needs to acquire the control back
  3360. * from HW in order to disable the regualtor. Else the behavior
  3361. * is unknown.
  3362. */
  3363. rc = __acquire_regulator(rinfo, device);
  3364. if (rc) {
  3365. /*
  3366. * This is somewhat fatal, but nothing we can do
  3367. * about it. We can't disable the regulator w/o
  3368. * getting it back under s/w control
  3369. */
  3370. dprintk(CVP_WARN,
  3371. "Failed to acquire control on %s\n",
  3372. rinfo->name);
  3373. goto disable_regulator_failed;
  3374. }
  3375. rc = regulator_disable(rinfo->regulator);
  3376. if (rc) {
  3377. dprintk(CVP_WARN,
  3378. "Failed to disable %s: %d\n",
  3379. rinfo->name, rc);
  3380. goto disable_regulator_failed;
  3381. }
  3382. return 0;
  3383. disable_regulator_failed:
  3384. /* Bring attention to this issue */
  3385. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3386. return rc;
  3387. }
  3388. static int __disable_hw_power_collapse(struct iris_hfi_device *device)
  3389. {
  3390. int rc = 0;
  3391. if (!msm_cvp_fw_low_power_mode) {
  3392. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3393. return 0;
  3394. }
  3395. rc = __take_back_regulators(device);
  3396. if (rc)
  3397. dprintk(CVP_WARN,
  3398. "%s : Failed to disable HW power collapse %d\n",
  3399. __func__, rc);
  3400. return rc;
  3401. }
  3402. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3403. {
  3404. int rc = 0;
  3405. if (!msm_cvp_fw_low_power_mode) {
  3406. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3407. return 0;
  3408. }
  3409. rc = __hand_off_regulators(device);
  3410. if (rc)
  3411. dprintk(CVP_WARN,
  3412. "%s : Failed to enable HW power collapse %d\n",
  3413. __func__, rc);
  3414. return rc;
  3415. }
  3416. static int __enable_regulator(struct iris_hfi_device *device,
  3417. const char *name)
  3418. {
  3419. int rc = 0;
  3420. struct regulator_info *rinfo;
  3421. iris_hfi_for_each_regulator(device, rinfo) {
  3422. if (strcmp(rinfo->name, name))
  3423. continue;
  3424. rc = regulator_enable(rinfo->regulator);
  3425. if (rc) {
  3426. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3427. rinfo->name, rc);
  3428. return rc;
  3429. }
  3430. if (!regulator_is_enabled(rinfo->regulator)) {
  3431. dprintk(CVP_ERR,"%s: regulator %s not enabled\n",
  3432. __func__, rinfo->name);
  3433. regulator_disable(rinfo->regulator);
  3434. return -EINVAL;
  3435. }
  3436. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3437. return 0;
  3438. }
  3439. dprintk(CVP_ERR, "regulator %s not found\n", name);
  3440. return -EINVAL;
  3441. }
  3442. static int __disable_regulator(struct iris_hfi_device *device,
  3443. const char *name)
  3444. {
  3445. struct regulator_info *rinfo;
  3446. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3447. if (strcmp(rinfo->name, name))
  3448. continue;
  3449. __disable_regulator_impl(rinfo, device);
  3450. dprintk(CVP_PWR, "%s Disabled regulator %s\n", __func__, name);
  3451. return 0;
  3452. }
  3453. dprintk(CVP_ERR, "%s regulator %s not found\n", __func__, name);
  3454. return -EINVAL;
  3455. }
  3456. static int __enable_subcaches(struct iris_hfi_device *device)
  3457. {
  3458. int rc = 0;
  3459. u32 c = 0;
  3460. struct subcache_info *sinfo;
  3461. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3462. return 0;
  3463. /* Activate subcaches */
  3464. iris_hfi_for_each_subcache(device, sinfo) {
  3465. rc = llcc_slice_activate(sinfo->subcache);
  3466. if (rc) {
  3467. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3468. sinfo->name, rc);
  3469. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3470. goto err_activate_fail;
  3471. }
  3472. sinfo->isactive = true;
  3473. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3474. c++;
  3475. }
  3476. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3477. return 0;
  3478. err_activate_fail:
  3479. __release_subcaches(device);
  3480. __disable_subcaches(device);
  3481. return 0;
  3482. }
  3483. static int __set_subcaches(struct iris_hfi_device *device)
  3484. {
  3485. int rc = 0;
  3486. u32 c = 0;
  3487. struct subcache_info *sinfo;
  3488. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3489. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3490. struct cvp_hfi_resource_subcache_type *sc_res;
  3491. struct cvp_resource_hdr rhdr;
  3492. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3493. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3494. return 0;
  3495. }
  3496. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3497. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3498. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3499. iris_hfi_for_each_subcache(device, sinfo) {
  3500. if (sinfo->isactive) {
  3501. sc_res[c].size = sinfo->subcache->slice_size;
  3502. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3503. c++;
  3504. }
  3505. }
  3506. /* Set resource to CVP for activated subcaches */
  3507. if (c) {
  3508. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3509. rhdr.resource_handle = sc_res_info; /* cookie */
  3510. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3511. sc_res_info->num_entries = c;
  3512. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3513. if (rc) {
  3514. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3515. goto err_fail_set_subacaches;
  3516. }
  3517. iris_hfi_for_each_subcache(device, sinfo) {
  3518. if (sinfo->isactive)
  3519. sinfo->isset = true;
  3520. }
  3521. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3522. device->res->sys_cache_res_set = true;
  3523. }
  3524. return 0;
  3525. err_fail_set_subacaches:
  3526. __disable_subcaches(device);
  3527. return 0;
  3528. }
  3529. static int __release_subcaches(struct iris_hfi_device *device)
  3530. {
  3531. struct subcache_info *sinfo;
  3532. int rc = 0;
  3533. u32 c = 0;
  3534. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3535. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3536. struct cvp_hfi_resource_subcache_type *sc_res;
  3537. struct cvp_resource_hdr rhdr;
  3538. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3539. return 0;
  3540. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3541. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3542. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3543. /* Release resource command to Iris */
  3544. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3545. if (sinfo->isset) {
  3546. /* Update the entry */
  3547. sc_res[c].size = sinfo->subcache->slice_size;
  3548. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3549. c++;
  3550. sinfo->isset = false;
  3551. }
  3552. }
  3553. if (c > 0) {
  3554. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3555. rhdr.resource_handle = sc_res_info; /* cookie */
  3556. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3557. rc = __core_release_resource(device, &rhdr);
  3558. if (rc)
  3559. dprintk(CVP_WARN,
  3560. "Failed to release %d subcaches\n", c);
  3561. }
  3562. device->res->sys_cache_res_set = false;
  3563. return 0;
  3564. }
  3565. static int __disable_subcaches(struct iris_hfi_device *device)
  3566. {
  3567. struct subcache_info *sinfo;
  3568. int rc = 0;
  3569. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3570. return 0;
  3571. /* De-activate subcaches */
  3572. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3573. if (sinfo->isactive) {
  3574. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3575. sinfo->name);
  3576. rc = llcc_slice_deactivate(sinfo->subcache);
  3577. if (rc) {
  3578. dprintk(CVP_WARN,
  3579. "Failed to de-activate %s: %d\n",
  3580. sinfo->name, rc);
  3581. }
  3582. sinfo->isactive = false;
  3583. }
  3584. }
  3585. return 0;
  3586. }
  3587. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3588. {
  3589. u32 mask_val = 0;
  3590. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3591. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3592. /* Write 0 to unmask CPU and WD interrupts */
  3593. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3594. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3595. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3596. CVP_WRAPPER_INTR_MASK, mask_val);
  3597. mask_val = 0;
  3598. mask_val = __read_register(device, CVP_SS_IRQ_MASK);
  3599. mask_val &= ~(CVP_SS_INTR_BMASK);
  3600. __write_register(device, CVP_SS_IRQ_MASK, mask_val);
  3601. dprintk(CVP_REG, "Init irq_wd: reg: %x, mask value %x\n",
  3602. CVP_SS_IRQ_MASK, mask_val);
  3603. }
  3604. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3605. {
  3606. /* initialize DSP QTBL & UCREGION with CPU queues */
  3607. __write_register(device, HFI_DSP_QTBL_ADDR,
  3608. (u32)device->dsp_iface_q_table.align_device_addr);
  3609. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3610. (u32)device->dsp_iface_q_table.align_device_addr);
  3611. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3612. device->dsp_iface_q_table.mem_data.size);
  3613. }
  3614. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3615. {
  3616. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3617. }
  3618. static int __set_ubwc_config(struct iris_hfi_device *device)
  3619. {
  3620. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3621. int rc = 0;
  3622. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3623. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3624. if (!device->res->ubwc_config)
  3625. return 0;
  3626. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3627. device->res->ubwc_config);
  3628. if (rc) {
  3629. dprintk(CVP_WARN,
  3630. "ubwc config setting to FW failed\n");
  3631. rc = -ENOTEMPTY;
  3632. goto fail_to_set_ubwc_config;
  3633. }
  3634. if (__iface_cmdq_write(device, pkt)) {
  3635. rc = -ENOTEMPTY;
  3636. goto fail_to_set_ubwc_config;
  3637. }
  3638. fail_to_set_ubwc_config:
  3639. return rc;
  3640. }
  3641. static int __power_on_controller(struct iris_hfi_device *device)
  3642. {
  3643. int rc = 0;
  3644. rc = __enable_regulator(device, "cvp");
  3645. if (rc) {
  3646. dprintk(CVP_ERR, "Failed to enable ctrler: %d\n", rc);
  3647. return rc;
  3648. }
  3649. rc = msm_cvp_prepare_enable_clk(device, "sleep_clk");
  3650. if (rc) {
  3651. dprintk(CVP_ERR, "Failed to enable sleep clk: %d\n", rc);
  3652. goto fail_reset_clks;
  3653. }
  3654. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3655. if (rc)
  3656. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3657. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3658. if (rc)
  3659. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3660. /* wait for deassert */
  3661. usleep_range(1000, 1050);
  3662. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3663. if (rc)
  3664. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3665. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3666. if (rc)
  3667. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3668. rc = msm_cvp_prepare_enable_clk(device, "gcc_video_axi1");
  3669. if (rc) {
  3670. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3671. goto fail_reset_clks;
  3672. }
  3673. rc = msm_cvp_prepare_enable_clk(device, "cvp_clk");
  3674. if (rc) {
  3675. dprintk(CVP_ERR, "Failed to enable cvp_clk: %d\n", rc);
  3676. goto fail_enable_clk;
  3677. }
  3678. dprintk(CVP_PWR, "EVA controller powered on\n");
  3679. return 0;
  3680. fail_enable_clk:
  3681. msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3682. fail_reset_clks:
  3683. __disable_regulator(device, "cvp");
  3684. return rc;
  3685. }
  3686. static int __power_on_core(struct iris_hfi_device *device)
  3687. {
  3688. int rc = 0;
  3689. rc = __enable_regulator(device, "cvp-core");
  3690. if (rc) {
  3691. dprintk(CVP_ERR, "Failed to enable core: %d\n", rc);
  3692. return rc;
  3693. }
  3694. rc = msm_cvp_prepare_enable_clk(device, "video_cc_mvs1_clk_src");
  3695. if (rc) {
  3696. dprintk(CVP_ERR, "Failed to enable video_cc_mvs1_clk_src:%d\n",
  3697. rc);
  3698. __disable_regulator(device, "cvp-core");
  3699. return rc;
  3700. }
  3701. rc = msm_cvp_prepare_enable_clk(device, "core_clk");
  3702. if (rc) {
  3703. dprintk(CVP_ERR, "Failed to enable core_clk: %d\n", rc);
  3704. __disable_regulator(device, "cvp-core");
  3705. return rc;
  3706. }
  3707. /*#ifdef CONFIG_EVA_PINEAPPLE
  3708. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0);
  3709. __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f);
  3710. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1);
  3711. __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1);
  3712. usleep_range(50, 100);
  3713. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0);
  3714. #endif*/
  3715. dprintk(CVP_PWR, "EVA core powered on\n");
  3716. return 0;
  3717. }
  3718. static int __iris_power_on(struct iris_hfi_device *device)
  3719. {
  3720. int rc = 0;
  3721. if (device->power_enabled)
  3722. return 0;
  3723. /* Vote for all hardware resources */
  3724. rc = __vote_buses(device, device->bus_vote.data,
  3725. device->bus_vote.data_count);
  3726. if (rc) {
  3727. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3728. goto fail_vote_buses;
  3729. }
  3730. rc = __power_on_controller(device);
  3731. if (rc)
  3732. goto fail_enable_controller;
  3733. rc = __power_on_core(device);
  3734. if (rc)
  3735. goto fail_enable_core;
  3736. rc = msm_cvp_scale_clocks(device);
  3737. if (rc) {
  3738. dprintk(CVP_WARN,
  3739. "Failed to scale clocks, perf may regress\n");
  3740. rc = 0;
  3741. } else {
  3742. dprintk(CVP_PWR, "Done with scaling\n");
  3743. }
  3744. /*Do not access registers before this point!*/
  3745. device->power_enabled = true;
  3746. /*
  3747. * Re-program all of the registers that get reset as a result of
  3748. * regulator_disable() and _enable()
  3749. * calling below function requires CORE powered on
  3750. */
  3751. rc = __set_registers(device);
  3752. if (rc)
  3753. goto fail_enable_core;
  3754. dprintk(CVP_CORE, "Done with register set\n");
  3755. call_iris_op(device, interrupt_init, device);
  3756. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3757. device->intr_status = 0;
  3758. enable_irq(device->cvp_hal_data->irq);
  3759. __write_register(device,
  3760. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3761. pr_info_ratelimited(CVP_DBG_TAG "cvp (eva) powered on\n", "pwr");
  3762. return 0;
  3763. fail_enable_core:
  3764. __power_off_controller(device);
  3765. fail_enable_controller:
  3766. __unvote_buses(device);
  3767. fail_vote_buses:
  3768. device->power_enabled = false;
  3769. return rc;
  3770. }
  3771. static inline int __suspend(struct iris_hfi_device *device)
  3772. {
  3773. int rc = 0;
  3774. if (!device) {
  3775. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3776. return -EINVAL;
  3777. } else if (!device->power_enabled) {
  3778. dprintk(CVP_PWR, "Power already disabled\n");
  3779. return 0;
  3780. }
  3781. dprintk(CVP_PWR, "Entering suspend\n");
  3782. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3783. if (rc) {
  3784. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3785. goto err_tzbsp_suspend;
  3786. }
  3787. __disable_subcaches(device);
  3788. call_iris_op(device, power_off, device);
  3789. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  3790. cvp_pm_qos_update(device, false);
  3791. return rc;
  3792. err_tzbsp_suspend:
  3793. return rc;
  3794. }
  3795. static void __print_sidebandmanager_regs(struct iris_hfi_device *device)
  3796. {
  3797. u32 sbm_ln0_low, axi_cbcr;
  3798. u32 main_sbm_ln0_low = 0xdeadbeef, main_sbm_ln0_high = 0xdeadbeef;
  3799. u32 main_sbm_ln1_high = 0xdeadbeef, cpu_cs_x2rpmh;
  3800. int rc;
  3801. sbm_ln0_low =
  3802. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3803. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3804. __write_register(device, CVP_CPU_CS_X2RPMh,
  3805. (cpu_cs_x2rpmh | CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK));
  3806. usleep_range(500, 1000);
  3807. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3808. if (!(cpu_cs_x2rpmh & CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK)) {
  3809. dprintk(CVP_WARN,
  3810. "failed set CVP_CPU_CS_X2RPMH mask %x\n",
  3811. cpu_cs_x2rpmh);
  3812. goto exit;
  3813. }
  3814. axi_cbcr = __read_gcc_register(device, CVP_GCC_VIDEO_AXI1_CBCR);
  3815. if (axi_cbcr & 0x80000000) {
  3816. dprintk(CVP_WARN, "failed to turn on AXI clock %x\n",
  3817. axi_cbcr);
  3818. goto exit;
  3819. }
  3820. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3821. if (rc) {
  3822. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  3823. goto exit;
  3824. }
  3825. main_sbm_ln0_low = __read_register(device,
  3826. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW);
  3827. main_sbm_ln0_high = __read_register(device,
  3828. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_HIGH);
  3829. main_sbm_ln1_high = __read_register(device,
  3830. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH);
  3831. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3832. exit:
  3833. cpu_cs_x2rpmh = cpu_cs_x2rpmh & (~CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK);
  3834. __write_register(device, CVP_CPU_CS_X2RPMh, cpu_cs_x2rpmh);
  3835. dprintk(CVP_WARN, "Sidebandmanager regs %x %x %x %x %x\n",
  3836. sbm_ln0_low, main_sbm_ln0_low,
  3837. main_sbm_ln0_high, main_sbm_ln1_high,
  3838. cpu_cs_x2rpmh);
  3839. }
  3840. static int __power_off_controller(struct iris_hfi_device *device)
  3841. {
  3842. u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
  3843. u32 sbm_ln0_low;
  3844. int rc;
  3845. u32 spare_val, spare_status;
  3846. /* HPG 6.2.2 Step 1 */
  3847. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  3848. /* HPG 6.2.2 Step 2, noc to low power */
  3849. /* New addition to put CPU/Tensilica to low power */
  3850. reg_status = 0;
  3851. count = 0;
  3852. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  3853. while (!reg_status && count < max_count) {
  3854. lpi_status =
  3855. __read_register(device,
  3856. CVP_WRAPPER_CPU_NOC_LPI_STATUS);
  3857. reg_status = lpi_status & BIT(0);
  3858. /* Wait for CPU noc lpi status to be set */
  3859. usleep_range(50, 100);
  3860. count++;
  3861. }
  3862. sbm_ln0_low = __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3863. dprintk(CVP_PWR,
  3864. "CPU Noc: lpi_status %x noc_status %x (count %d) 0x%x\n",
  3865. lpi_status, reg_status, count, sbm_ln0_low);
  3866. if (count == max_count) {
  3867. u32 pc_ready, wfi_status;
  3868. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  3869. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  3870. dprintk(CVP_WARN,
  3871. "CPU NOC not in qaccept status %x %x %x %x\n",
  3872. reg_status, lpi_status, wfi_status, pc_ready);
  3873. __print_sidebandmanager_regs(device);
  3874. }
  3875. /* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
  3876. /* HPG 6.2.2 Step 4, debug bridge to lpi release */
  3877. __write_register(device,
  3878. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  3879. lpi_status = 0x1;
  3880. count = 0;
  3881. while (lpi_status && count < max_count) {
  3882. lpi_status = __read_register(device,
  3883. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  3884. usleep_range(50, 100);
  3885. count++;
  3886. }
  3887. dprintk(CVP_PWR,
  3888. "DBLP Release: lpi_status %d(count %d)\n",
  3889. lpi_status, count);
  3890. if (count == max_count) {
  3891. dprintk(CVP_WARN,
  3892. "DBLP Release: lpi_status %x\n", lpi_status);
  3893. }
  3894. /* PDXFIFO reset: addition for Kailua / Lanai */
  3895. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x3);
  3896. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x1);
  3897. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x0);
  3898. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x0);
  3899. /* HPG 6.2.2 Step 5 */
  3900. msm_cvp_disable_unprepare_clk(device, "cvp_clk");
  3901. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3902. if (rc)
  3903. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3904. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3905. if (rc)
  3906. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3907. /* wait for deassert */
  3908. usleep_range(1000, 1050);
  3909. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3910. if (rc)
  3911. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3912. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3913. if (rc)
  3914. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3915. /* disable EVA NoC clock */
  3916. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x1);
  3917. /* enable EVA NoC reset */
  3918. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x1);
  3919. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3920. if (rc) {
  3921. dprintk(CVP_ERR, "FATAL ERROR, HPG step 17 to 20 will be bypassed\n");
  3922. goto skip_xo_reset;
  3923. }
  3924. spare_status = 0x1;
  3925. while (spare_status != 0x0) {
  3926. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3927. spare_status = spare_val & 0x2;
  3928. usleep_range(50, 100);
  3929. }
  3930. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x1);
  3931. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_xo_reset");
  3932. if (rc)
  3933. dprintk(CVP_ERR, "%s: assert cvp_xo_reset failed\n", __func__);
  3934. /* de-assert EVA_NoC reset */
  3935. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x0);
  3936. /* de-assert EVA video_cc XO reset and enable video_cc XO clock after 80us */
  3937. usleep_range(80, 100);
  3938. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_xo_reset");
  3939. if (rc)
  3940. dprintk(CVP_ERR, "%s: de-assert cvp_xo_reset failed\n", __func__);
  3941. /* clear XO mask bit - this step was missing in previous sequence */
  3942. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x0);
  3943. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3944. skip_xo_reset:
  3945. /* enable EVA NoC clock */
  3946. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x0);
  3947. /* De-assert EVA_CTL Force Sleep Retention */
  3948. usleep_range(400, 500);
  3949. /* HPG 6.2.2 Step 6 */
  3950. __disable_regulator(device, "cvp");
  3951. /* HPG 6.2.2 Step 7 */
  3952. rc = msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3953. if (rc) {
  3954. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3955. }
  3956. rc = msm_cvp_disable_unprepare_clk(device, "sleep_clk");
  3957. if (rc) {
  3958. dprintk(CVP_ERR, "Failed to disable sleep clk: %d\n", rc);
  3959. }
  3960. return 0;
  3961. }
  3962. static int __power_off_core(struct iris_hfi_device *device)
  3963. {
  3964. u32 reg_status = 0, lpi_status, config, value = 0, count = 0;
  3965. u32 warn_flag = 0, max_count = 10;
  3966. value = __read_register(device, CVP_CC_MVS1_GDSCR);
  3967. if (!(value & 0x80000000)) {
  3968. /*
  3969. * Core has been powered off by f/w.
  3970. * Check NOC reset registers to ensure
  3971. * NO outstanding NoC transactions
  3972. */
  3973. value = __read_register(device, CVP_NOC_RESET_ACK);
  3974. if (value) {
  3975. dprintk(CVP_WARN,
  3976. "Core off with NOC RESET ACK non-zero %x\n",
  3977. value);
  3978. __print_sidebandmanager_regs(device);
  3979. }
  3980. __disable_regulator(device, "cvp-core");
  3981. msm_cvp_disable_unprepare_clk(device, "core_clk");
  3982. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  3983. return 0;
  3984. } else if (!(value & 0x2)) {
  3985. /*
  3986. * HW_CONTROL PC disabled, then core is powered on for
  3987. * CVP NoC access
  3988. */
  3989. __disable_regulator(device, "cvp-core");
  3990. msm_cvp_disable_unprepare_clk(device, "core_clk");
  3991. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  3992. return 0;
  3993. }
  3994. dprintk(CVP_PWR, "Driver controls Core power off now\n");
  3995. /*
  3996. * check to make sure core clock branch enabled else
  3997. * we cannot read core idle register
  3998. */
  3999. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4000. if (config) {
  4001. dprintk(CVP_PWR,
  4002. "core clock config not enabled, enable it to access core\n");
  4003. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4004. }
  4005. /*
  4006. * add MNoC idle check before collapsing MVS1 per HPG update
  4007. * poll for NoC DMA idle -> HPG 6.2.1
  4008. *
  4009. */
  4010. do {
  4011. value = __read_register(device, CVP_SS_IDLE_STATUS);
  4012. if (value & 0x400000)
  4013. break;
  4014. else
  4015. usleep_range(1000, 2000);
  4016. count++;
  4017. } while (count < max_count);
  4018. if (count == max_count) {
  4019. dprintk(CVP_WARN, "Core fail to go idle %x\n", value);
  4020. warn_flag = 1;
  4021. }
  4022. count = 0;
  4023. max_count = 1000;
  4024. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1);
  4025. while (!reg_status && count < max_count) {
  4026. lpi_status =
  4027. __read_register(device,
  4028. CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS);
  4029. reg_status = lpi_status & BIT(0);
  4030. /* Wait for Core noc lpi status to be set */
  4031. usleep_range(50, 100);
  4032. count++;
  4033. }
  4034. dprintk(CVP_PWR,
  4035. "Core Noc: lpi_status %x noc_status %x (count %d)\n",
  4036. lpi_status, reg_status, count);
  4037. if (count == max_count) {
  4038. u32 pc_ready, wfi_status;
  4039. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4040. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4041. dprintk(CVP_WARN,
  4042. "Core NOC not in qaccept status %x %x %x %x\n",
  4043. reg_status, lpi_status, wfi_status, pc_ready);
  4044. __print_sidebandmanager_regs(device);
  4045. }
  4046. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x0);
  4047. if (warn_flag)
  4048. __print_sidebandmanager_regs(device);
  4049. /* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) */
  4050. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x3);
  4051. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x2);
  4052. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x0);
  4053. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4054. __disable_hw_power_collapse(device);
  4055. usleep_range(100, 200);
  4056. __disable_regulator(device, "cvp-core");
  4057. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4058. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4059. return 0;
  4060. }
  4061. static void power_off_iris2(struct iris_hfi_device *device)
  4062. {
  4063. if (!device->power_enabled || !device->res->sw_power_collapsible)
  4064. return;
  4065. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  4066. disable_irq_nosync(device->cvp_hal_data->irq);
  4067. device->intr_status = 0;
  4068. __power_off_core(device);
  4069. __power_off_controller(device);
  4070. if (__unvote_buses(device))
  4071. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  4072. /*Do not access registers after this point!*/
  4073. device->power_enabled = false;
  4074. pr_info(CVP_DBG_TAG "cvp (eva) power collapsed\n", "pwr");
  4075. }
  4076. static inline int __resume(struct iris_hfi_device *device)
  4077. {
  4078. int rc = 0;
  4079. u32 reg_gdsc, reg_cbcr;
  4080. struct msm_cvp_core *core;
  4081. if (!device) {
  4082. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  4083. return -EINVAL;
  4084. } else if (device->power_enabled) {
  4085. goto exit;
  4086. } else if (!__core_in_valid_state(device)) {
  4087. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  4088. return -EINVAL;
  4089. }
  4090. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  4091. dprintk(CVP_PWR, "Resuming from power collapse\n");
  4092. rc = __iris_power_on(device);
  4093. if (rc) {
  4094. dprintk(CVP_ERR, "Failed to power on cvp\n");
  4095. goto err_iris_power_on;
  4096. }
  4097. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  4098. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  4099. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000))
  4100. dprintk(CVP_ERR, "CVP power on failed gdsc %x cbcr %x\n",
  4101. reg_gdsc, reg_cbcr);
  4102. __setup_ucregion_memory_map(device);
  4103. /* RUMI: set CVP_CTRL_INIT register to disable synx in FW */
  4104. /* Reboot the firmware */
  4105. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  4106. if (rc) {
  4107. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  4108. goto err_set_cvp_state;
  4109. }
  4110. /* Wait for boot completion */
  4111. rc = __boot_firmware(device);
  4112. if (rc) {
  4113. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  4114. msm_cvp_trigger_ssr(core, SSR_ERR_FATAL);
  4115. goto err_reset_core;
  4116. }
  4117. /*
  4118. * Work around for H/W bug, need to reprogram these registers once
  4119. * firmware is out reset
  4120. */
  4121. __set_threshold_registers(device);
  4122. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  4123. cvp_pm_qos_update(device, true);
  4124. __sys_set_debug(device, msm_cvp_fw_debug);
  4125. __enable_subcaches(device);
  4126. __set_subcaches(device);
  4127. __dsp_resume(device);
  4128. dprintk(CVP_PWR, "Resumed from power collapse\n");
  4129. exit:
  4130. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  4131. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  4132. device->skip_pc_count = 0;
  4133. return rc;
  4134. err_reset_core:
  4135. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  4136. err_set_cvp_state:
  4137. call_iris_op(device, power_off, device);
  4138. err_iris_power_on:
  4139. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  4140. return rc;
  4141. }
  4142. static int __power_on_init(struct iris_hfi_device *device)
  4143. {
  4144. int rc = 0;
  4145. /* Initialize resources */
  4146. rc = __init_resources(device, device->res);
  4147. if (rc) {
  4148. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  4149. return rc;
  4150. }
  4151. rc = __initialize_packetization(device);
  4152. if (rc) {
  4153. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  4154. goto fail_iris_init;
  4155. }
  4156. rc = __iris_power_on(device);
  4157. if (rc) {
  4158. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  4159. goto fail_iris_init;
  4160. }
  4161. return rc;
  4162. fail_iris_init:
  4163. __deinit_resources(device);
  4164. return rc;
  4165. }
  4166. static int __load_fw(struct iris_hfi_device *device)
  4167. {
  4168. int rc = 0;
  4169. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  4170. || device->res->use_non_secure_pil) {
  4171. rc = load_cvp_fw_impl(device);
  4172. if (rc)
  4173. goto fail_load_fw;
  4174. }
  4175. return rc;
  4176. fail_load_fw:
  4177. call_iris_op(device, power_off, device);
  4178. return rc;
  4179. }
  4180. static void __unload_fw(struct iris_hfi_device *device)
  4181. {
  4182. if (!device->resources.fw.cookie)
  4183. return;
  4184. cancel_delayed_work(&iris_hfi_pm_work);
  4185. if (device->state != IRIS_STATE_DEINIT)
  4186. flush_workqueue(device->iris_pm_workq);
  4187. unload_cvp_fw_impl(device);
  4188. __interface_queues_release(device);
  4189. call_iris_op(device, power_off, device);
  4190. __deinit_resources(device);
  4191. dprintk(CVP_WARN, "Firmware unloaded\n");
  4192. }
  4193. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  4194. {
  4195. int i = 0;
  4196. struct iris_hfi_device *device = dev;
  4197. if (!device || !fw_info) {
  4198. dprintk(CVP_ERR,
  4199. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  4200. __func__, device, fw_info);
  4201. return -EINVAL;
  4202. }
  4203. mutex_lock(&device->lock);
  4204. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  4205. ;
  4206. if (i == CVP_VERSION_LENGTH - 1) {
  4207. dprintk(CVP_WARN, "Iris version string is not proper\n");
  4208. fw_info->version[0] = '\0';
  4209. goto fail_version_string;
  4210. }
  4211. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  4212. CVP_VERSION_LENGTH);
  4213. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  4214. fail_version_string:
  4215. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  4216. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  4217. fw_info->register_base = device->res->register_base;
  4218. fw_info->register_size = device->cvp_hal_data->register_size;
  4219. fw_info->irq = device->cvp_hal_data->irq;
  4220. mutex_unlock(&device->lock);
  4221. return 0;
  4222. }
  4223. static int iris_hfi_get_core_capabilities(void *dev)
  4224. {
  4225. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  4226. return 0;
  4227. }
  4228. static const char * const mid_names[16] = {
  4229. "CVP_FW",
  4230. "ARP_DATA",
  4231. "CVP_MPU_PIXEL",
  4232. "CVP_MPU_NON_PIXEL",
  4233. "CVP_FDU_PIXEL",
  4234. "CVP_FDU_NON_PIXEL",
  4235. "CVP_GCE_PIXEL",
  4236. "CVP_GCE_NON_PIXEL",
  4237. "CVP_TOF_PIXEL",
  4238. "CVP_TOF_NON_PIXEL",
  4239. "CVP_VADL_PIXEL",
  4240. "CVP_VADL_NON_PIXEL",
  4241. "CVP_RGE_NON_PIXEL",
  4242. "CVP_CDM",
  4243. "Invalid",
  4244. "Invalid"
  4245. };
  4246. static void __print_reg_details(u32 val)
  4247. {
  4248. u32 mid, sid;
  4249. mid = (val >> 5) & 0xF;
  4250. sid = (val >> 2) & 0x7;
  4251. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  4252. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  4253. }
  4254. static void __err_log(bool logging, u32 *data, const char *name, u32 val)
  4255. {
  4256. if (logging)
  4257. *data = val;
  4258. dprintk(CVP_ERR, "%s: %#x\n", name, val);
  4259. }
  4260. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  4261. {
  4262. struct msm_cvp_core *core;
  4263. struct cvp_noc_log *noc_log;
  4264. u32 val = 0, regi, regii, regiii, i;
  4265. bool log_required = false;
  4266. int rc;
  4267. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  4268. if (!core->ssr_count && core->resources.max_ssr_allowed > 1)
  4269. log_required = true;
  4270. noc_log = &core->log.noc_log;
  4271. if (noc_log->used) {
  4272. dprintk(CVP_WARN, "Data already in NoC log, skip logging\n");
  4273. return;
  4274. }
  4275. noc_log->used = 1;
  4276. __disable_hw_power_collapse(device);
  4277. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4278. regi = __read_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL);
  4279. regii = __read_register(device, CVP_CC_MVS1_CBCR);
  4280. regiii = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4281. dprintk(CVP_ERR, "noc reg check: %#x %#x %#x %#x\n",
  4282. val, regi, regii, regiii);
  4283. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  4284. __err_log(log_required, &noc_log->err_ctrl_swid_low,
  4285. "CVP_NOC_ERL_MAIN_SWID_LOW", val);
  4286. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  4287. __err_log(log_required, &noc_log->err_ctrl_swid_high,
  4288. "CVP_NOC_ERL_MAIN_SWID_HIGH", val);
  4289. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  4290. __err_log(log_required, &noc_log->err_ctrl_mainctl_low,
  4291. "CVP_NOC_ERL_MAIN_MAINCTL_LOW", val);
  4292. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  4293. __err_log(log_required, &noc_log->err_ctrl_errvld_low,
  4294. "CVP_NOC_ERL_MAIN_ERRVLD_LOW", val);
  4295. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  4296. __err_log(log_required, &noc_log->err_ctrl_errclr_low,
  4297. "CVP_NOC_ERL_MAIN_ERRCLR_LOW", val);
  4298. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  4299. __err_log(log_required, &noc_log->err_ctrl_errlog0_low,
  4300. "CVP_NOC_ERL_MAIN_ERRLOG0_LOW", val);
  4301. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  4302. __err_log(log_required, &noc_log->err_ctrl_errlog0_high,
  4303. "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH", val);
  4304. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4305. __err_log(log_required, &noc_log->err_ctrl_errlog1_low,
  4306. "CVP_NOC_ERL_MAIN_ERRLOG1_LOW", val);
  4307. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4308. __err_log(log_required, &noc_log->err_ctrl_errlog1_high,
  4309. "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH", val);
  4310. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4311. __err_log(log_required, &noc_log->err_ctrl_errlog2_low,
  4312. "CVP_NOC_ERL_MAIN_ERRLOG2_LOW", val);
  4313. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4314. __err_log(log_required, &noc_log->err_ctrl_errlog2_high,
  4315. "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH", val);
  4316. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4317. __err_log(log_required, &noc_log->err_ctrl_errlog3_low,
  4318. "CVP_NOC_ERL_MAIN_ERRLOG3_LOW", val);
  4319. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4320. __err_log(log_required, &noc_log->err_ctrl_errlog3_high,
  4321. "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH", val);
  4322. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4323. if (rc) {
  4324. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4325. return;
  4326. }
  4327. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS);
  4328. __err_log(log_required, &noc_log->err_core_swid_low,
  4329. "CVP_NOC__CORE_ERL_MAIN_SWID_LOW", val);
  4330. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS);
  4331. __err_log(log_required, &noc_log->err_core_swid_high,
  4332. "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH", val);
  4333. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  4334. __err_log(log_required, &noc_log->err_core_mainctl_low,
  4335. "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW", val);
  4336. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS);
  4337. __err_log(log_required, &noc_log->err_core_errvld_low,
  4338. "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW", val);
  4339. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS);
  4340. __err_log(log_required, &noc_log->err_core_errclr_low,
  4341. "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW", val);
  4342. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS);
  4343. __err_log(log_required, &noc_log->err_core_errlog0_low,
  4344. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW", val);
  4345. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS);
  4346. __err_log(log_required, &noc_log->err_core_errlog0_high,
  4347. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH", val);
  4348. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS);
  4349. __err_log(log_required, &noc_log->err_core_errlog1_low,
  4350. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW", val);
  4351. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS);
  4352. __err_log(log_required, &noc_log->err_core_errlog1_high,
  4353. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH", val);
  4354. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS);
  4355. __err_log(log_required, &noc_log->err_core_errlog2_low,
  4356. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW", val);
  4357. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS);
  4358. __err_log(log_required, &noc_log->err_core_errlog2_high,
  4359. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH", val);
  4360. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS);
  4361. __err_log(log_required, &noc_log->err_core_errlog3_low,
  4362. "CORE ERRLOG3_LOW, below details", val);
  4363. __print_reg_details(val);
  4364. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS);
  4365. __err_log(log_required, &noc_log->err_core_errlog3_high,
  4366. "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH", val);
  4367. __write_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS, 0x1);
  4368. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4369. #define CVP_SS_CLK_HALT 0x8
  4370. #define CVP_SS_CLK_EN 0xC
  4371. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  4372. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  4373. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  4374. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  4375. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  4376. __write_register(device, CVP_SS_CLK_HALT, 0);
  4377. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  4378. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  4379. for (i = 0; i < 15; i++) {
  4380. regi = 0xC0000000 + i;
  4381. __write_register(device, CVP_SS_ARP_TEST_BUS_CONTROL, regi);
  4382. val = __read_register(device, CVP_SS_ARP_TEST_BUS_REGISTER);
  4383. noc_log->arp_test_bus[i] = val;
  4384. }
  4385. for (i = 0; i < 512; i++) {
  4386. regi = 0x40000000 + i;
  4387. __write_register(device, CVP_DMA_TEST_BUS_CONTROL, regi);
  4388. val = __read_register(device, CVP_DMA_TEST_BUS_REGISTER);
  4389. noc_log->dma_test_bus[i] = val;
  4390. }
  4391. }
  4392. static int iris_hfi_noc_error_info(void *dev)
  4393. {
  4394. struct iris_hfi_device *device;
  4395. if (!dev) {
  4396. dprintk(CVP_ERR, "%s: null device\n", __func__);
  4397. return -EINVAL;
  4398. }
  4399. device = dev;
  4400. mutex_lock(&device->lock);
  4401. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  4402. call_iris_op(device, noc_error_info, device);
  4403. mutex_unlock(&device->lock);
  4404. return 0;
  4405. }
  4406. static int __initialize_packetization(struct iris_hfi_device *device)
  4407. {
  4408. int rc = 0;
  4409. if (!device || !device->res) {
  4410. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  4411. return -EINVAL;
  4412. }
  4413. device->packetization_type = HFI_PACKETIZATION_4XX;
  4414. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  4415. device->packetization_type);
  4416. if (!device->pkt_ops) {
  4417. rc = -EINVAL;
  4418. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  4419. }
  4420. return rc;
  4421. }
  4422. void __init_cvp_ops(struct iris_hfi_device *device)
  4423. {
  4424. device->vpu_ops = &iris2_ops;
  4425. }
  4426. static struct iris_hfi_device *__add_device(u32 device_id,
  4427. struct msm_cvp_platform_resources *res,
  4428. hfi_cmd_response_callback callback)
  4429. {
  4430. struct iris_hfi_device *hdevice = NULL;
  4431. int rc = 0;
  4432. if (!res || !callback) {
  4433. dprintk(CVP_ERR, "Invalid Parameters\n");
  4434. return NULL;
  4435. }
  4436. dprintk(CVP_INFO, "%s: device_id: %d\n", __func__, device_id);
  4437. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  4438. if (!hdevice) {
  4439. dprintk(CVP_ERR, "failed to allocate new device\n");
  4440. goto exit;
  4441. }
  4442. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  4443. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  4444. if (!hdevice->response_pkt) {
  4445. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  4446. goto err_cleanup;
  4447. }
  4448. hdevice->raw_packet =
  4449. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  4450. if (!hdevice->raw_packet) {
  4451. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  4452. goto err_cleanup;
  4453. }
  4454. rc = vm_manager.vm_ops->vm_init_reg_and_irq(hdevice, res);
  4455. if (rc)
  4456. goto err_cleanup;
  4457. hdevice->res = res;
  4458. hdevice->device_id = device_id;
  4459. hdevice->callback = callback;
  4460. __init_cvp_ops(hdevice);
  4461. hdevice->cvp_workq = create_singlethread_workqueue(
  4462. "msm_cvp_workerq_iris");
  4463. if (!hdevice->cvp_workq) {
  4464. dprintk(CVP_ERR, ": create cvp workq failed\n");
  4465. goto err_cleanup;
  4466. }
  4467. hdevice->iris_pm_workq = create_singlethread_workqueue(
  4468. "pm_workerq_iris");
  4469. if (!hdevice->iris_pm_workq) {
  4470. dprintk(CVP_ERR, ": create pm workq failed\n");
  4471. goto err_cleanup;
  4472. }
  4473. mutex_init(&hdevice->lock);
  4474. INIT_LIST_HEAD(&hdevice->sess_head);
  4475. return hdevice;
  4476. err_cleanup:
  4477. if (hdevice->iris_pm_workq)
  4478. destroy_workqueue(hdevice->iris_pm_workq);
  4479. if (hdevice->cvp_workq)
  4480. destroy_workqueue(hdevice->cvp_workq);
  4481. kfree(hdevice->response_pkt);
  4482. kfree(hdevice->raw_packet);
  4483. kfree(hdevice);
  4484. exit:
  4485. return NULL;
  4486. }
  4487. static struct iris_hfi_device *__get_device(u32 device_id,
  4488. struct msm_cvp_platform_resources *res,
  4489. hfi_cmd_response_callback callback)
  4490. {
  4491. if (!res || !callback) {
  4492. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  4493. return NULL;
  4494. }
  4495. return __add_device(device_id, res, callback);
  4496. }
  4497. void cvp_iris_hfi_delete_device(void *device)
  4498. {
  4499. struct msm_cvp_core *core;
  4500. struct iris_hfi_device *dev = NULL;
  4501. if (!device)
  4502. return;
  4503. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  4504. if (core)
  4505. dev = core->device->hfi_device_data;
  4506. if (!dev)
  4507. return;
  4508. mutex_destroy(&dev->lock);
  4509. destroy_workqueue(dev->cvp_workq);
  4510. destroy_workqueue(dev->iris_pm_workq);
  4511. free_irq(dev->cvp_hal_data->irq, dev);
  4512. iounmap(dev->cvp_hal_data->register_base);
  4513. iounmap(dev->cvp_hal_data->gcc_reg_base);
  4514. kfree(dev->cvp_hal_data);
  4515. kfree(dev->response_pkt);
  4516. kfree(dev->raw_packet);
  4517. kfree(dev);
  4518. }
  4519. static int iris_hfi_validate_session(void *sess, const char *func)
  4520. {
  4521. struct cvp_hal_session *session = sess;
  4522. int rc = 0;
  4523. struct iris_hfi_device *device;
  4524. if (!session || !session->device) {
  4525. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  4526. return -EINVAL;
  4527. }
  4528. device = session->device;
  4529. mutex_lock(&device->lock);
  4530. if (!__is_session_valid(device, session, func))
  4531. rc = -ECONNRESET;
  4532. mutex_unlock(&device->lock);
  4533. return rc;
  4534. }
  4535. static void iris_init_hfi_callbacks(struct cvp_hfi_device *hdev)
  4536. {
  4537. hdev->core_init = iris_hfi_core_init;
  4538. hdev->core_release = iris_hfi_core_release;
  4539. hdev->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  4540. hdev->session_init = iris_hfi_session_init;
  4541. hdev->session_end = iris_hfi_session_end;
  4542. hdev->session_start = iris_hfi_session_start;
  4543. hdev->session_stop = iris_hfi_session_stop;
  4544. hdev->session_abort = iris_hfi_session_abort;
  4545. hdev->session_clean = iris_hfi_session_clean;
  4546. hdev->session_set_buffers = iris_hfi_session_set_buffers;
  4547. hdev->session_release_buffers = iris_hfi_session_release_buffers;
  4548. hdev->session_send = iris_hfi_session_send;
  4549. hdev->session_flush = iris_hfi_session_flush;
  4550. hdev->scale_clocks = iris_hfi_scale_clocks;
  4551. hdev->vote_bus = iris_hfi_vote_buses;
  4552. hdev->get_fw_info = iris_hfi_get_fw_info;
  4553. hdev->get_core_capabilities = iris_hfi_get_core_capabilities;
  4554. hdev->suspend = iris_hfi_suspend;
  4555. hdev->resume = iris_hfi_resume;
  4556. hdev->flush_debug_queue = iris_hfi_flush_debug_queue;
  4557. hdev->noc_error_info = iris_hfi_noc_error_info;
  4558. hdev->validate_session = iris_hfi_validate_session;
  4559. hdev->pm_qos_update = iris_pm_qos_update;
  4560. hdev->debug_hook = iris_debug_hook;
  4561. }
  4562. int cvp_iris_hfi_initialize(struct cvp_hfi_device *hdev, u32 device_id,
  4563. struct msm_cvp_platform_resources *res,
  4564. hfi_cmd_response_callback callback)
  4565. {
  4566. int rc = 0;
  4567. if (!hdev || !res || !callback) {
  4568. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  4569. hdev, res, callback);
  4570. rc = -EINVAL;
  4571. goto err_iris_hfi_init;
  4572. }
  4573. hdev->hfi_device_data = __get_device(device_id, res, callback);
  4574. if (IS_ERR_OR_NULL(hdev->hfi_device_data)) {
  4575. rc = PTR_ERR(hdev->hfi_device_data) ?: -EINVAL;
  4576. goto err_iris_hfi_init;
  4577. }
  4578. iris_init_hfi_callbacks(hdev);
  4579. err_iris_hfi_init:
  4580. return rc;
  4581. }