sde_encoder_phys_vid.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  7. #include "sde_encoder_phys.h"
  8. #include "sde_hw_interrupts.h"
  9. #include "sde_core_irq.h"
  10. #include "sde_formats.h"
  11. #include "dsi_display.h"
  12. #include "sde_trace.h"
  13. #include <drm/drm_fixed.h>
  14. #define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
  15. (e) && (e)->base.parent ? \
  16. (e)->base.parent->base.id : -1, \
  17. (e) && (e)->base.hw_intf ? \
  18. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  19. #define SDE_ERROR_VIDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
  20. (e) && (e)->base.parent ? \
  21. (e)->base.parent->base.id : -1, \
  22. (e) && (e)->base.hw_intf ? \
  23. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  24. #define to_sde_encoder_phys_vid(x) \
  25. container_of(x, struct sde_encoder_phys_vid, base)
  26. /* Poll time to do recovery during active region */
  27. #define POLL_TIME_USEC_FOR_LN_CNT 500
  28. #define MAX_POLL_CNT 10
  29. static bool sde_encoder_phys_vid_is_master(
  30. struct sde_encoder_phys *phys_enc)
  31. {
  32. bool ret = false;
  33. if (phys_enc->split_role != ENC_ROLE_SLAVE)
  34. ret = true;
  35. return ret;
  36. }
  37. static void drm_mode_to_intf_timing_params(
  38. const struct sde_encoder_phys_vid *vid_enc,
  39. const struct drm_display_mode *mode,
  40. struct intf_timing_params *timing)
  41. {
  42. const struct sde_encoder_phys *phys_enc = &vid_enc->base;
  43. s64 comp_ratio, width;
  44. memset(timing, 0, sizeof(*timing));
  45. if ((mode->htotal < mode->hsync_end)
  46. || (mode->hsync_start < mode->hdisplay)
  47. || (mode->vtotal < mode->vsync_end)
  48. || (mode->vsync_start < mode->vdisplay)
  49. || (mode->hsync_end < mode->hsync_start)
  50. || (mode->vsync_end < mode->vsync_start)) {
  51. SDE_ERROR(
  52. "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
  53. mode->hsync_start, mode->hsync_end,
  54. mode->htotal, mode->hdisplay);
  55. SDE_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
  56. mode->vsync_start, mode->vsync_end,
  57. mode->vtotal, mode->vdisplay);
  58. return;
  59. }
  60. /*
  61. * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
  62. * Active Region Front Porch Sync Back Porch
  63. * <-----------------><------------><-----><----------->
  64. * <- [hv]display --->
  65. * <--------- [hv]sync_start ------>
  66. * <----------------- [hv]sync_end ------->
  67. * <---------------------------- [hv]total ------------->
  68. */
  69. timing->poms_align_vsync = phys_enc->poms_align_vsync;
  70. timing->width = mode->hdisplay; /* active width */
  71. timing->height = mode->vdisplay; /* active height */
  72. timing->xres = timing->width;
  73. timing->yres = timing->height;
  74. timing->h_back_porch = mode->htotal - mode->hsync_end;
  75. timing->h_front_porch = mode->hsync_start - mode->hdisplay;
  76. timing->v_back_porch = mode->vtotal - mode->vsync_end;
  77. timing->v_front_porch = mode->vsync_start - mode->vdisplay;
  78. timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
  79. timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
  80. timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
  81. timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
  82. timing->border_clr = 0;
  83. timing->underflow_clr = 0xff;
  84. timing->hsync_skew = mode->hskew;
  85. timing->v_front_porch_fixed = vid_enc->base.vfp_cached;
  86. timing->vrefresh = drm_mode_vrefresh(&phys_enc->cached_mode);
  87. if (vid_enc->base.comp_type != MSM_DISPLAY_COMPRESSION_NONE) {
  88. timing->compression_en = true;
  89. timing->dce_bytes_per_line = vid_enc->base.dce_bytes_per_line;
  90. }
  91. /* DSI controller cannot handle active-low sync signals. */
  92. if (phys_enc->hw_intf->cap->type == INTF_DSI) {
  93. timing->hsync_polarity = 0;
  94. timing->vsync_polarity = 0;
  95. }
  96. /* for DP/EDP, Shift timings to align it to bottom right */
  97. if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
  98. (phys_enc->hw_intf->cap->type == INTF_EDP)) {
  99. timing->h_back_porch += timing->h_front_porch;
  100. timing->h_front_porch = 0;
  101. timing->v_back_porch += timing->v_front_porch;
  102. timing->v_front_porch = 0;
  103. }
  104. timing->wide_bus_en = sde_encoder_is_widebus_enabled(phys_enc->parent);
  105. /*
  106. * for DP, divide the horizonal parameters by 2 when
  107. * widebus or compression is enabled, irrespective of
  108. * compression ratio
  109. */
  110. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  111. (timing->wide_bus_en ||
  112. (vid_enc->base.comp_ratio > MSM_DISPLAY_COMPRESSION_RATIO_NONE))) {
  113. timing->width = timing->width >> 1;
  114. timing->xres = timing->xres >> 1;
  115. timing->h_back_porch = timing->h_back_porch >> 1;
  116. timing->h_front_porch = timing->h_front_porch >> 1;
  117. timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
  118. if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  119. (vid_enc->base.comp_ratio > MSM_DISPLAY_COMPRESSION_RATIO_NONE)) {
  120. timing->extra_dto_cycles =
  121. vid_enc->base.dsc_extra_pclk_cycle_cnt;
  122. timing->width += vid_enc->base.dsc_extra_disp_width;
  123. timing->h_back_porch +=
  124. vid_enc->base.dsc_extra_disp_width;
  125. }
  126. }
  127. /*
  128. * for DSI, if compression is enabled, then divide the horizonal active
  129. * timing parameters by compression ratio.
  130. */
  131. if ((phys_enc->hw_intf->cap->type != INTF_DP) &&
  132. ((vid_enc->base.comp_type ==
  133. MSM_DISPLAY_COMPRESSION_DSC) ||
  134. (vid_enc->base.comp_type ==
  135. MSM_DISPLAY_COMPRESSION_VDC))) {
  136. // adjust active dimensions
  137. width = drm_fixp_from_fraction(timing->width, 1);
  138. comp_ratio = drm_fixp_from_fraction(vid_enc->base.comp_ratio, 100);
  139. width = drm_fixp_div(width, comp_ratio);
  140. timing->width = drm_fixp2int_ceil(width);
  141. timing->xres = timing->width;
  142. }
  143. /*
  144. * For edp only:
  145. * DISPLAY_V_START = (VBP * HCYCLE) + HBP
  146. * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
  147. */
  148. /*
  149. * if (vid_enc->hw->cap->type == INTF_EDP) {
  150. * display_v_start += mode->htotal - mode->hsync_start;
  151. * display_v_end -= mode->hsync_start - mode->hdisplay;
  152. * }
  153. */
  154. }
  155. static inline u32 get_horizontal_total(const struct intf_timing_params *timing)
  156. {
  157. u32 active = timing->xres;
  158. u32 inactive =
  159. timing->h_back_porch + timing->h_front_porch +
  160. timing->hsync_pulse_width;
  161. return active + inactive;
  162. }
  163. static inline u32 get_vertical_total(const struct intf_timing_params *timing)
  164. {
  165. u32 active = timing->yres;
  166. u32 inactive = timing->v_back_porch + timing->v_front_porch +
  167. timing->vsync_pulse_width;
  168. return active + inactive;
  169. }
  170. /*
  171. * programmable_fetch_get_num_lines:
  172. * Number of fetch lines in vertical front porch
  173. * @timing: Pointer to the intf timing information for the requested mode
  174. *
  175. * Returns the number of fetch lines in vertical front porch at which mdp
  176. * can start fetching the next frame.
  177. *
  178. * Number of needed prefetch lines is anything that cannot be absorbed in the
  179. * start of frame time (back porch + vsync pulse width).
  180. *
  181. * Some panels have very large VFP, however we only need a total number of
  182. * lines based on the chip worst case latencies.
  183. */
  184. static u32 programmable_fetch_get_num_lines(
  185. struct sde_encoder_phys_vid *vid_enc,
  186. const struct intf_timing_params *timing)
  187. {
  188. struct sde_encoder_phys *phys_enc = &vid_enc->base;
  189. struct sde_mdss_cfg *m;
  190. u32 needed_prefill_lines, needed_vfp_lines, actual_vfp_lines;
  191. const u32 fixed_prefill_fps = DEFAULT_FPS;
  192. u32 default_prefill_lines =
  193. phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
  194. u32 start_of_frame_lines =
  195. timing->v_back_porch + timing->vsync_pulse_width;
  196. u32 v_front_porch = timing->v_front_porch;
  197. u32 vrefresh, max_fps;
  198. m = phys_enc->sde_kms->catalog;
  199. max_fps = sde_encoder_get_dfps_maxfps(phys_enc->parent);
  200. vrefresh = (max_fps > timing->vrefresh) ? max_fps : timing->vrefresh;
  201. /* minimum prefill lines are defined based on 60fps */
  202. needed_prefill_lines = (vrefresh > fixed_prefill_fps) ?
  203. ((default_prefill_lines * vrefresh) /
  204. fixed_prefill_fps) : default_prefill_lines;
  205. needed_vfp_lines = needed_prefill_lines - start_of_frame_lines;
  206. /* Fetch must be outside active lines, otherwise undefined. */
  207. if (start_of_frame_lines >= needed_prefill_lines) {
  208. SDE_DEBUG_VIDENC(vid_enc,
  209. "prog fetch always enabled case\n");
  210. actual_vfp_lines = (test_bit(SDE_FEATURE_DELAY_PRG_FETCH, m->features)) ? 2 : 1;
  211. } else if (v_front_porch < needed_vfp_lines) {
  212. /* Warn fetch needed, but not enough porch in panel config */
  213. pr_warn_once
  214. ("low vbp+vfp may lead to perf issues in some cases\n");
  215. SDE_DEBUG_VIDENC(vid_enc,
  216. "less vfp than fetch req, using entire vfp\n");
  217. actual_vfp_lines = v_front_porch;
  218. } else {
  219. SDE_DEBUG_VIDENC(vid_enc, "room in vfp for needed prefetch\n");
  220. actual_vfp_lines = needed_vfp_lines;
  221. }
  222. SDE_DEBUG_VIDENC(vid_enc,
  223. "vrefresh:%u v_front_porch:%u v_back_porch:%u vsync_pulse_width:%u\n",
  224. vrefresh, v_front_porch, timing->v_back_porch,
  225. timing->vsync_pulse_width);
  226. SDE_DEBUG_VIDENC(vid_enc,
  227. "prefill_lines:%u needed_vfp_lines:%u actual_vfp_lines:%u\n",
  228. needed_prefill_lines, needed_vfp_lines, actual_vfp_lines);
  229. return actual_vfp_lines;
  230. }
  231. /*
  232. * programmable_fetch_config: Programs HW to prefetch lines by offsetting
  233. * the start of fetch into the vertical front porch for cases where the
  234. * vsync pulse width and vertical back porch time is insufficient
  235. *
  236. * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
  237. * HW layer requires VSYNC counter of first pixel of tgt VFP line.
  238. *
  239. * @timing: Pointer to the intf timing information for the requested mode
  240. */
  241. static void programmable_fetch_config(struct sde_encoder_phys *phys_enc,
  242. const struct intf_timing_params *timing)
  243. {
  244. struct sde_encoder_phys_vid *vid_enc =
  245. to_sde_encoder_phys_vid(phys_enc);
  246. struct intf_prog_fetch f = { 0 };
  247. u32 vfp_fetch_lines = 0;
  248. u32 horiz_total = 0;
  249. u32 vert_total = 0;
  250. u32 vfp_fetch_start_vsync_counter = 0;
  251. unsigned long lock_flags;
  252. struct sde_mdss_cfg *m;
  253. if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
  254. return;
  255. m = phys_enc->sde_kms->catalog;
  256. phys_enc->pf_time_in_us = 0;
  257. vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);
  258. if (vfp_fetch_lines) {
  259. vert_total = get_vertical_total(timing);
  260. horiz_total = get_horizontal_total(timing);
  261. vfp_fetch_start_vsync_counter =
  262. (vert_total - vfp_fetch_lines) * horiz_total + 1;
  263. phys_enc->pf_time_in_us = DIV_ROUND_UP(1000000 * vfp_fetch_lines,
  264. vert_total * timing->vrefresh);
  265. /**
  266. * Check if we need to throttle the fetch to start
  267. * from second line after the active region.
  268. */
  269. if (test_bit(SDE_FEATURE_DELAY_PRG_FETCH, m->features))
  270. vfp_fetch_start_vsync_counter += horiz_total;
  271. f.enable = 1;
  272. f.fetch_start = vfp_fetch_start_vsync_counter;
  273. }
  274. SDE_DEBUG_VIDENC(vid_enc,
  275. "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
  276. vfp_fetch_lines, vfp_fetch_start_vsync_counter);
  277. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  278. phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
  279. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  280. }
  281. static bool sde_encoder_phys_vid_mode_fixup(
  282. struct sde_encoder_phys *phys_enc,
  283. const struct drm_display_mode *mode,
  284. struct drm_display_mode *adj_mode)
  285. {
  286. if (phys_enc)
  287. SDE_DEBUG_VIDENC(to_sde_encoder_phys_vid(phys_enc), "\n");
  288. /*
  289. * Modifying mode has consequences when the mode comes back to us
  290. */
  291. return true;
  292. }
  293. /* vid_enc timing_params must be configured before calling this function */
  294. static void _sde_encoder_phys_vid_setup_avr(
  295. struct sde_encoder_phys *phys_enc, u32 qsync_min_fps)
  296. {
  297. struct sde_encoder_phys_vid *vid_enc;
  298. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  299. if (vid_enc->base.hw_intf->ops.avr_setup) {
  300. struct intf_avr_params avr_params = {0};
  301. u32 default_fps = drm_mode_vrefresh(&phys_enc->cached_mode);
  302. int ret;
  303. if (!default_fps) {
  304. SDE_ERROR_VIDENC(vid_enc,
  305. "invalid default fps %d\n",
  306. default_fps);
  307. return;
  308. }
  309. if (qsync_min_fps > default_fps) {
  310. SDE_ERROR_VIDENC(vid_enc,
  311. "qsync fps %d must be less than default %d\n",
  312. qsync_min_fps, default_fps);
  313. return;
  314. }
  315. avr_params.default_fps = default_fps;
  316. avr_params.min_fps = qsync_min_fps;
  317. ret = vid_enc->base.hw_intf->ops.avr_setup(
  318. vid_enc->base.hw_intf,
  319. &vid_enc->timing_params, &avr_params);
  320. if (ret)
  321. SDE_ERROR_VIDENC(vid_enc,
  322. "bad settings, can't configure AVR\n");
  323. SDE_EVT32(DRMID(phys_enc->parent), default_fps,
  324. qsync_min_fps, ret);
  325. }
  326. }
  327. static void _sde_encoder_phys_vid_avr_ctrl(struct sde_encoder_phys *phys_enc)
  328. {
  329. struct intf_avr_params avr_params;
  330. struct sde_encoder_phys_vid *vid_enc = to_sde_encoder_phys_vid(phys_enc);
  331. struct drm_connector *conn = phys_enc->connector;
  332. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(phys_enc->parent);
  333. struct msm_mode_info *info = &sde_enc->mode_info;
  334. u32 avr_step_state;
  335. if (!conn || !conn->state)
  336. return;
  337. avr_step_state = sde_connector_get_property(conn->state, CONNECTOR_PROP_AVR_STEP_STATE);
  338. memset(&avr_params, 0, sizeof(avr_params));
  339. avr_params.avr_mode = sde_connector_get_qsync_mode(phys_enc->connector);
  340. if (info->avr_step_fps && (avr_step_state == AVR_STEP_ENABLE))
  341. avr_params.avr_step_lines = mult_frac(phys_enc->cached_mode.vtotal,
  342. vid_enc->timing_params.vrefresh, info->avr_step_fps);
  343. if (vid_enc->base.hw_intf->ops.avr_ctrl)
  344. vid_enc->base.hw_intf->ops.avr_ctrl(vid_enc->base.hw_intf, &avr_params);
  345. if (vid_enc->base.hw_intf->ops.enable_te_level_trigger &&
  346. !sde_enc->disp_info.is_te_using_watchdog_timer)
  347. vid_enc->base.hw_intf->ops.enable_te_level_trigger(vid_enc->base.hw_intf,
  348. (avr_step_state == AVR_STEP_ENABLE));
  349. SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0, avr_params.avr_mode,
  350. avr_params.avr_step_lines, info->avr_step_fps, avr_step_state,
  351. sde_enc->disp_info.is_te_using_watchdog_timer);
  352. }
  353. static void sde_encoder_phys_vid_setup_timing_engine(
  354. struct sde_encoder_phys *phys_enc)
  355. {
  356. struct sde_encoder_phys_vid *vid_enc;
  357. struct drm_display_mode mode;
  358. struct intf_timing_params timing_params = { 0 };
  359. const struct sde_format *fmt = NULL;
  360. u32 fmt_fourcc = DRM_FORMAT_RGB888;
  361. u32 qsync_min_fps = 0;
  362. unsigned long lock_flags;
  363. struct sde_hw_intf_cfg intf_cfg = { 0 };
  364. bool is_split_link = false;
  365. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->hw_ctl ||
  366. !phys_enc->hw_intf || !phys_enc->connector) {
  367. SDE_ERROR("invalid encoder %d\n", !phys_enc);
  368. return;
  369. }
  370. mode = phys_enc->cached_mode;
  371. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  372. if (!phys_enc->hw_intf->ops.setup_timing_gen) {
  373. SDE_ERROR("timing engine setup is not supported\n");
  374. return;
  375. }
  376. SDE_DEBUG_VIDENC(vid_enc, "enabling mode:\n");
  377. drm_mode_debug_printmodeline(&mode);
  378. is_split_link = phys_enc->hw_intf->cfg.split_link_en;
  379. if (phys_enc->split_role != ENC_ROLE_SOLO || is_split_link) {
  380. mode.hdisplay >>= 1;
  381. mode.htotal >>= 1;
  382. mode.hsync_start >>= 1;
  383. mode.hsync_end >>= 1;
  384. SDE_DEBUG_VIDENC(vid_enc,
  385. "split_role %d, halve horizontal %d %d %d %d\n",
  386. phys_enc->split_role,
  387. mode.hdisplay, mode.htotal,
  388. mode.hsync_start, mode.hsync_end);
  389. }
  390. if (!phys_enc->vfp_cached) {
  391. phys_enc->vfp_cached =
  392. sde_connector_get_panel_vfp(phys_enc->connector, &mode);
  393. if (phys_enc->vfp_cached <= 0)
  394. phys_enc->vfp_cached = mode.vsync_start - mode.vdisplay;
  395. }
  396. drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);
  397. vid_enc->timing_params = timing_params;
  398. if (phys_enc->cont_splash_enabled) {
  399. SDE_DEBUG_VIDENC(vid_enc,
  400. "skipping intf programming since cont splash is enabled\n");
  401. goto exit;
  402. }
  403. fmt = sde_get_sde_format(fmt_fourcc);
  404. SDE_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
  405. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  406. phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
  407. &timing_params, fmt);
  408. if (test_bit(SDE_CTL_ACTIVE_CFG,
  409. &phys_enc->hw_ctl->caps->features)) {
  410. sde_encoder_helper_update_intf_cfg(phys_enc);
  411. } else if (phys_enc->hw_ctl->ops.setup_intf_cfg) {
  412. intf_cfg.intf = phys_enc->hw_intf->idx;
  413. intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  414. intf_cfg.stream_sel = 0; /* Don't care value for video mode */
  415. intf_cfg.mode_3d =
  416. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  417. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  418. &intf_cfg);
  419. }
  420. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  421. if (phys_enc->hw_intf->cap->type == INTF_DSI)
  422. programmable_fetch_config(phys_enc, &timing_params);
  423. exit:
  424. if (phys_enc->parent_ops.get_qsync_fps)
  425. phys_enc->parent_ops.get_qsync_fps(
  426. phys_enc->parent, &qsync_min_fps, phys_enc->connector->state);
  427. /* only panels which support qsync will have a non-zero min fps */
  428. if (qsync_min_fps) {
  429. _sde_encoder_phys_vid_setup_avr(phys_enc, qsync_min_fps);
  430. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  431. }
  432. }
  433. static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
  434. {
  435. struct sde_encoder_phys *phys_enc = arg;
  436. struct sde_hw_ctl *hw_ctl;
  437. struct intf_status intf_status = {0};
  438. unsigned long lock_flags;
  439. u32 flush_register = ~0;
  440. u32 reset_status = 0;
  441. int new_cnt = -1, old_cnt = -1;
  442. u32 event = 0;
  443. int pend_ret_fence_cnt = 0;
  444. u32 fence_ready = -1;
  445. if (!phys_enc)
  446. return;
  447. hw_ctl = phys_enc->hw_ctl;
  448. if (!hw_ctl)
  449. return;
  450. SDE_ATRACE_BEGIN("vblank_irq");
  451. /*
  452. * only decrement the pending flush count if we've actually flushed
  453. * hardware. due to sw irq latency, vblank may have already happened
  454. * so we need to double-check with hw that it accepted the flush bits
  455. */
  456. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  457. old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
  458. if (hw_ctl->ops.get_flush_register)
  459. flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
  460. if (flush_register)
  461. goto not_flushed;
  462. new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
  463. pend_ret_fence_cnt = atomic_read(&phys_enc->pending_retire_fence_cnt);
  464. /* signal only for master, where there is a pending kickoff */
  465. if (sde_encoder_phys_vid_is_master(phys_enc) &&
  466. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  467. event = SDE_ENCODER_FRAME_EVENT_DONE |
  468. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE |
  469. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  470. }
  471. not_flushed:
  472. if (hw_ctl->ops.get_reset)
  473. reset_status = hw_ctl->ops.get_reset(hw_ctl);
  474. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  475. if (event && phys_enc->parent_ops.handle_frame_done)
  476. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  477. phys_enc, event);
  478. if (phys_enc->parent_ops.handle_vblank_virt)
  479. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  480. phys_enc);
  481. if (phys_enc->hw_intf->ops.get_status)
  482. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  483. &intf_status);
  484. if (flush_register && hw_ctl->ops.get_hw_fence_status)
  485. fence_ready = hw_ctl->ops.get_hw_fence_status(hw_ctl);
  486. SDE_EVT32_IRQ(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  487. old_cnt, atomic_read(&phys_enc->pending_kickoff_cnt),
  488. reset_status ? SDE_EVTLOG_ERROR : 0,
  489. flush_register, event,
  490. atomic_read(&phys_enc->pending_retire_fence_cnt),
  491. intf_status.frame_count, intf_status.line_count,
  492. fence_ready);
  493. /* Signal any waiting atomic commit thread */
  494. wake_up_all(&phys_enc->pending_kickoff_wq);
  495. SDE_ATRACE_END("vblank_irq");
  496. }
  497. static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
  498. {
  499. struct sde_encoder_phys *phys_enc = arg;
  500. if (!phys_enc)
  501. return;
  502. if (phys_enc->parent_ops.handle_underrun_virt)
  503. phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
  504. phys_enc);
  505. }
  506. static void _sde_encoder_phys_vid_setup_irq_hw_idx(
  507. struct sde_encoder_phys *phys_enc)
  508. {
  509. struct sde_encoder_irq *irq;
  510. /*
  511. * Initialize irq->hw_idx only when irq is not registered.
  512. * Prevent invalidating irq->irq_idx as modeset may be
  513. * called many times during dfps.
  514. */
  515. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  516. if (irq->irq_idx < 0)
  517. irq->hw_idx = phys_enc->intf_idx;
  518. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  519. if (irq->irq_idx < 0)
  520. irq->hw_idx = phys_enc->intf_idx;
  521. }
  522. static void sde_encoder_phys_vid_cont_splash_mode_set(
  523. struct sde_encoder_phys *phys_enc,
  524. struct drm_display_mode *adj_mode)
  525. {
  526. if (!phys_enc || !adj_mode) {
  527. SDE_ERROR("invalid args\n");
  528. return;
  529. }
  530. phys_enc->cached_mode = *adj_mode;
  531. phys_enc->enable_state = SDE_ENC_ENABLED;
  532. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  533. }
  534. static void sde_encoder_phys_vid_mode_set(
  535. struct sde_encoder_phys *phys_enc,
  536. struct drm_display_mode *mode,
  537. struct drm_display_mode *adj_mode, bool *reinit_mixers)
  538. {
  539. struct sde_rm *rm;
  540. struct sde_rm_hw_iter iter;
  541. int i, instance;
  542. struct sde_encoder_phys_vid *vid_enc;
  543. if (!phys_enc || !phys_enc->sde_kms) {
  544. SDE_ERROR("invalid encoder/kms\n");
  545. return;
  546. }
  547. rm = &phys_enc->sde_kms->rm;
  548. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  549. if (adj_mode) {
  550. phys_enc->cached_mode = *adj_mode;
  551. drm_mode_debug_printmodeline(adj_mode);
  552. SDE_DEBUG_VIDENC(vid_enc, "caching mode:\n");
  553. }
  554. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  555. /* Retrieve previously allocated HW Resources. Shouldn't fail */
  556. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  557. for (i = 0; i <= instance; i++) {
  558. if (sde_rm_get_hw(rm, &iter)) {
  559. if (phys_enc->hw_ctl && phys_enc->hw_ctl != to_sde_hw_ctl(iter.hw)) {
  560. *reinit_mixers = true;
  561. SDE_EVT32(phys_enc->hw_ctl->idx,
  562. to_sde_hw_ctl(iter.hw)->idx);
  563. }
  564. phys_enc->hw_ctl = to_sde_hw_ctl(iter.hw);
  565. }
  566. }
  567. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  568. SDE_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
  569. PTR_ERR(phys_enc->hw_ctl));
  570. phys_enc->hw_ctl = NULL;
  571. return;
  572. }
  573. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_INTF);
  574. for (i = 0; i <= instance; i++) {
  575. if (sde_rm_get_hw(rm, &iter))
  576. phys_enc->hw_intf = to_sde_hw_intf(iter.hw);
  577. }
  578. if (IS_ERR_OR_NULL(phys_enc->hw_intf)) {
  579. SDE_ERROR_VIDENC(vid_enc, "failed to init intf: %ld\n",
  580. PTR_ERR(phys_enc->hw_intf));
  581. phys_enc->hw_intf = NULL;
  582. return;
  583. }
  584. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  585. phys_enc->kickoff_timeout_ms =
  586. sde_encoder_helper_get_kickoff_timeout_ms(phys_enc->parent);
  587. }
  588. static int sde_encoder_phys_vid_control_vblank_irq(
  589. struct sde_encoder_phys *phys_enc,
  590. bool enable)
  591. {
  592. int ret = 0;
  593. struct sde_encoder_phys_vid *vid_enc;
  594. int refcount;
  595. if (!phys_enc) {
  596. SDE_ERROR("invalid encoder\n");
  597. return -EINVAL;
  598. }
  599. mutex_lock(phys_enc->vblank_ctl_lock);
  600. refcount = atomic_read(&phys_enc->vblank_refcount);
  601. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  602. /* Slave encoders don't report vblank */
  603. if (!sde_encoder_phys_vid_is_master(phys_enc))
  604. goto end;
  605. /* protect against negative */
  606. if (!enable && refcount == 0) {
  607. ret = -EINVAL;
  608. goto end;
  609. }
  610. SDE_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
  611. __builtin_return_address(0),
  612. enable, atomic_read(&phys_enc->vblank_refcount));
  613. SDE_EVT32(DRMID(phys_enc->parent), enable,
  614. atomic_read(&phys_enc->vblank_refcount));
  615. if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) {
  616. ret = sde_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
  617. if (ret)
  618. atomic_dec_return(&phys_enc->vblank_refcount);
  619. } else if (!enable &&
  620. atomic_dec_return(&phys_enc->vblank_refcount) == 0) {
  621. ret = sde_encoder_helper_unregister_irq(phys_enc,
  622. INTR_IDX_VSYNC);
  623. if (ret)
  624. atomic_inc_return(&phys_enc->vblank_refcount);
  625. }
  626. end:
  627. if (ret) {
  628. SDE_ERROR_VIDENC(vid_enc,
  629. "control vblank irq error %d, enable %d\n",
  630. ret, enable);
  631. SDE_EVT32(DRMID(phys_enc->parent),
  632. phys_enc->hw_intf->idx - INTF_0,
  633. enable, refcount, SDE_EVTLOG_ERROR);
  634. }
  635. mutex_unlock(phys_enc->vblank_ctl_lock);
  636. return ret;
  637. }
  638. static bool sde_encoder_phys_vid_wait_dma_trigger(
  639. struct sde_encoder_phys *phys_enc)
  640. {
  641. struct sde_encoder_phys_vid *vid_enc;
  642. struct sde_hw_intf *intf;
  643. struct sde_hw_ctl *ctl;
  644. struct intf_status status;
  645. if (!phys_enc) {
  646. SDE_ERROR("invalid encoder\n");
  647. return false;
  648. }
  649. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  650. intf = phys_enc->hw_intf;
  651. ctl = phys_enc->hw_ctl;
  652. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  653. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  654. phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
  655. return false;
  656. }
  657. if (!intf->ops.get_status)
  658. return false;
  659. intf->ops.get_status(intf, &status);
  660. /* if interface is not enabled, return true to wait for dma trigger */
  661. return status.is_en ? false : true;
  662. }
  663. static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
  664. {
  665. struct msm_drm_private *priv;
  666. struct sde_encoder_phys_vid *vid_enc;
  667. struct sde_hw_intf *intf;
  668. struct sde_hw_ctl *ctl;
  669. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  670. !phys_enc->parent->dev->dev_private ||
  671. !phys_enc->sde_kms) {
  672. SDE_ERROR("invalid encoder/device\n");
  673. return;
  674. }
  675. priv = phys_enc->parent->dev->dev_private;
  676. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  677. intf = phys_enc->hw_intf;
  678. ctl = phys_enc->hw_ctl;
  679. if (!phys_enc->hw_intf || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
  680. SDE_ERROR("invalid hw_intf %d hw_ctl %d hw_pp %d\n",
  681. !phys_enc->hw_intf, !phys_enc->hw_ctl,
  682. !phys_enc->hw_pp);
  683. return;
  684. }
  685. if (!ctl->ops.update_bitmask) {
  686. SDE_ERROR("invalid hw_ctl ops %d\n", ctl->idx);
  687. return;
  688. }
  689. SDE_DEBUG_VIDENC(vid_enc, "\n");
  690. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  691. return;
  692. if (!phys_enc->cont_splash_enabled)
  693. sde_encoder_helper_split_config(phys_enc,
  694. phys_enc->hw_intf->idx);
  695. sde_encoder_phys_vid_setup_timing_engine(phys_enc);
  696. /*
  697. * For cases where both the interfaces are connected to same ctl,
  698. * set the flush bit for both master and slave.
  699. * For single flush cases (dual-ctl or pp-split), skip setting the
  700. * flush bit for the slave intf, since both intfs use same ctl
  701. * and HW will only flush the master.
  702. */
  703. if (!test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  704. sde_encoder_phys_needs_single_flush(phys_enc) &&
  705. !sde_encoder_phys_vid_is_master(phys_enc))
  706. goto skip_flush;
  707. /**
  708. * skip flushing intf during cont. splash handoff since bootloader
  709. * has already enabled the hardware and is single buffered.
  710. */
  711. if (phys_enc->cont_splash_enabled) {
  712. SDE_DEBUG_VIDENC(vid_enc,
  713. "skipping intf flush bit set as cont. splash is enabled\n");
  714. goto skip_flush;
  715. }
  716. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF, intf->idx, 1);
  717. if (phys_enc->hw_pp->merge_3d)
  718. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,
  719. phys_enc->hw_pp->merge_3d->idx, 1);
  720. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  721. phys_enc->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  722. phys_enc->comp_ratio)
  723. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH, intf->idx, 1);
  724. skip_flush:
  725. SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",
  726. ctl->idx - CTL_0, intf->idx);
  727. SDE_EVT32(DRMID(phys_enc->parent),
  728. atomic_read(&phys_enc->pending_retire_fence_cnt));
  729. /* ctl_flush & timing engine enable will be triggered by framework */
  730. if (phys_enc->enable_state == SDE_ENC_DISABLED)
  731. phys_enc->enable_state = SDE_ENC_ENABLING;
  732. }
  733. static void sde_encoder_phys_vid_destroy(struct sde_encoder_phys *phys_enc)
  734. {
  735. struct sde_encoder_phys_vid *vid_enc;
  736. if (!phys_enc) {
  737. SDE_ERROR("invalid encoder\n");
  738. return;
  739. }
  740. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  741. SDE_DEBUG_VIDENC(vid_enc, "\n");
  742. kfree(vid_enc);
  743. }
  744. static void sde_encoder_phys_vid_get_hw_resources(
  745. struct sde_encoder_phys *phys_enc,
  746. struct sde_encoder_hw_resources *hw_res,
  747. struct drm_connector_state *conn_state)
  748. {
  749. struct sde_encoder_phys_vid *vid_enc;
  750. if (!phys_enc || !hw_res) {
  751. SDE_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
  752. !phys_enc, !hw_res, !conn_state);
  753. return;
  754. }
  755. if ((phys_enc->intf_idx - INTF_0) >= INTF_MAX) {
  756. SDE_ERROR("invalid intf idx:%d\n", phys_enc->intf_idx);
  757. return;
  758. }
  759. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  760. SDE_DEBUG_VIDENC(vid_enc, "\n");
  761. hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
  762. }
  763. static int _sde_encoder_phys_vid_wait_for_vblank(
  764. struct sde_encoder_phys *phys_enc, bool notify)
  765. {
  766. struct sde_encoder_wait_info wait_info = {0};
  767. int ret = 0, new_cnt;
  768. u32 event = SDE_ENCODER_FRAME_EVENT_ERROR |
  769. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE |
  770. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  771. struct drm_connector *conn;
  772. struct sde_hw_ctl *hw_ctl;
  773. u32 flush_register = 0xebad;
  774. bool timeout = false;
  775. if (!phys_enc || !phys_enc->hw_ctl) {
  776. pr_err("invalid encoder\n");
  777. return -EINVAL;
  778. }
  779. hw_ctl = phys_enc->hw_ctl;
  780. conn = phys_enc->connector;
  781. wait_info.wq = &phys_enc->pending_kickoff_wq;
  782. wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
  783. wait_info.timeout_ms = phys_enc->kickoff_timeout_ms;
  784. /* Wait for kickoff to complete */
  785. ret = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
  786. &wait_info);
  787. /*
  788. * if hwfencing enabled, try again to wait for up to the extended timeout time in
  789. * increments as long as fence has not been signaled.
  790. */
  791. if (ret == -ETIMEDOUT && phys_enc->sde_kms->catalog->hw_fence_rev)
  792. ret = sde_encoder_helper_hw_fence_extended_wait(phys_enc, phys_enc->hw_ctl,
  793. &wait_info, INTR_IDX_VSYNC);
  794. if (ret == -ETIMEDOUT) {
  795. new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
  796. timeout = true;
  797. /*
  798. * Reset ret when flush register is consumed. This handles a race condition between
  799. * irq wait timeout handler reading the register status and the actual IRQ handler
  800. */
  801. if (hw_ctl->ops.get_flush_register)
  802. flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
  803. if (!flush_register)
  804. ret = 0;
  805. /* if we timeout after the extended wait, reset mixers and do sw override */
  806. if (ret && phys_enc->sde_kms->catalog->hw_fence_rev)
  807. sde_encoder_helper_hw_fence_sw_override(phys_enc, hw_ctl);
  808. SDE_EVT32(DRMID(phys_enc->parent), new_cnt, flush_register, ret,
  809. SDE_EVTLOG_FUNC_CASE1);
  810. }
  811. if (notify && timeout && atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)
  812. && phys_enc->parent_ops.handle_frame_done) {
  813. phys_enc->parent_ops.handle_frame_done(phys_enc->parent, phys_enc, event);
  814. /* notify only on actual timeout cases */
  815. if ((ret == -ETIMEDOUT) && sde_encoder_recovery_events_enabled(phys_enc->parent))
  816. sde_connector_event_notify(conn, DRM_EVENT_SDE_HW_RECOVERY,
  817. sizeof(uint8_t), SDE_RECOVERY_HARD_RESET);
  818. }
  819. SDE_EVT32(DRMID(phys_enc->parent), event, notify, timeout, ret,
  820. ret ? SDE_EVTLOG_FATAL : 0, SDE_EVTLOG_FUNC_EXIT);
  821. if (!ret)
  822. sde_encoder_clear_fence_error_in_progress(phys_enc);
  823. return ret;
  824. }
  825. static int sde_encoder_phys_vid_wait_for_vblank(
  826. struct sde_encoder_phys *phys_enc)
  827. {
  828. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, true);
  829. }
  830. static void sde_encoder_phys_vid_update_txq(struct sde_encoder_phys *phys_enc)
  831. {
  832. struct sde_encoder_virt *sde_enc;
  833. if (!phys_enc)
  834. return;
  835. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  836. if (!sde_enc)
  837. return;
  838. sde_encoder_helper_update_out_fence_txq(sde_enc, true);
  839. }
  840. static int sde_encoder_phys_vid_wait_for_commit_done(
  841. struct sde_encoder_phys *phys_enc)
  842. {
  843. int rc;
  844. rc = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, true);
  845. if (rc)
  846. sde_encoder_helper_phys_reset(phys_enc);
  847. /* Update TxQ for the incoming frame */
  848. sde_encoder_phys_vid_update_txq(phys_enc);
  849. return rc;
  850. }
  851. static int sde_encoder_phys_vid_wait_for_vblank_no_notify(
  852. struct sde_encoder_phys *phys_enc)
  853. {
  854. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  855. }
  856. static int sde_encoder_phys_vid_prepare_for_kickoff(
  857. struct sde_encoder_phys *phys_enc,
  858. struct sde_encoder_kickoff_params *params)
  859. {
  860. struct sde_encoder_phys_vid *vid_enc;
  861. struct sde_hw_ctl *ctl;
  862. bool recovery_events;
  863. struct drm_connector *conn;
  864. int rc;
  865. int irq_enable;
  866. if (!phys_enc || !params || !phys_enc->hw_ctl) {
  867. SDE_ERROR("invalid encoder/parameters\n");
  868. return -EINVAL;
  869. }
  870. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  871. phys_enc->kickoff_timeout_ms =
  872. sde_encoder_helper_get_kickoff_timeout_ms(phys_enc->parent);
  873. ctl = phys_enc->hw_ctl;
  874. if (!ctl->ops.wait_reset_status)
  875. return 0;
  876. conn = phys_enc->connector;
  877. recovery_events = sde_encoder_recovery_events_enabled(
  878. phys_enc->parent);
  879. /*
  880. * hw supports hardware initiated ctl reset, so before we kickoff a new
  881. * frame, need to check and wait for hw initiated ctl reset completion
  882. */
  883. rc = ctl->ops.wait_reset_status(ctl);
  884. if (rc) {
  885. SDE_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
  886. ctl->idx, rc);
  887. ++vid_enc->error_count;
  888. /* to avoid flooding, only log first time, and "dead" time */
  889. if (vid_enc->error_count == 1) {
  890. SDE_EVT32(DRMID(phys_enc->parent), SDE_EVTLOG_FATAL);
  891. mutex_lock(phys_enc->vblank_ctl_lock);
  892. irq_enable = atomic_read(&phys_enc->vblank_refcount);
  893. if (irq_enable)
  894. sde_encoder_helper_unregister_irq(
  895. phys_enc, INTR_IDX_VSYNC);
  896. SDE_DBG_DUMP(SDE_DBG_BUILT_IN_ALL);
  897. if (irq_enable)
  898. sde_encoder_helper_register_irq(
  899. phys_enc, INTR_IDX_VSYNC);
  900. mutex_unlock(phys_enc->vblank_ctl_lock);
  901. }
  902. /*
  903. * if the recovery event is registered by user, don't panic
  904. * trigger panic on first timeout if no listener registered
  905. */
  906. if (recovery_events)
  907. sde_connector_event_notify(conn, DRM_EVENT_SDE_HW_RECOVERY,
  908. sizeof(uint8_t), SDE_RECOVERY_CAPTURE);
  909. else
  910. SDE_DBG_DUMP(0x0, "panic");
  911. /* request a ctl reset before the next flush */
  912. phys_enc->enable_state = SDE_ENC_ERR_NEEDS_HW_RESET;
  913. } else {
  914. if (recovery_events && vid_enc->error_count)
  915. sde_connector_event_notify(conn,
  916. DRM_EVENT_SDE_HW_RECOVERY,
  917. sizeof(uint8_t),
  918. SDE_RECOVERY_SUCCESS);
  919. vid_enc->error_count = 0;
  920. }
  921. return rc;
  922. }
  923. static void sde_encoder_phys_vid_single_vblank_wait(
  924. struct sde_encoder_phys *phys_enc)
  925. {
  926. int ret;
  927. struct sde_encoder_phys_vid *vid_enc
  928. = to_sde_encoder_phys_vid(phys_enc);
  929. /*
  930. * Wait for a vsync so we know the ENABLE=0 latched before
  931. * the (connector) source of the vsync's gets disabled,
  932. * otherwise we end up in a funny state if we re-enable
  933. * before the disable latches, which results that some of
  934. * the settings changes for the new modeset (like new
  935. * scanout buffer) don't latch properly..
  936. */
  937. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  938. if (ret) {
  939. SDE_ERROR_VIDENC(vid_enc,
  940. "failed to enable vblank irq: %d\n",
  941. ret);
  942. SDE_EVT32(DRMID(phys_enc->parent),
  943. phys_enc->hw_intf->idx - INTF_0, ret,
  944. SDE_EVTLOG_FUNC_CASE1,
  945. SDE_EVTLOG_ERROR);
  946. } else {
  947. ret = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  948. if (ret) {
  949. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  950. SDE_ERROR_VIDENC(vid_enc,
  951. "failure waiting for disable: %d\n",
  952. ret);
  953. SDE_EVT32(DRMID(phys_enc->parent),
  954. phys_enc->hw_intf->idx - INTF_0, ret,
  955. SDE_EVTLOG_FUNC_CASE2,
  956. SDE_EVTLOG_ERROR);
  957. }
  958. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  959. }
  960. }
  961. static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
  962. {
  963. struct msm_drm_private *priv;
  964. struct sde_encoder_phys_vid *vid_enc;
  965. unsigned long lock_flags;
  966. struct intf_status intf_status = {0};
  967. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  968. !phys_enc->parent->dev->dev_private) {
  969. SDE_ERROR("invalid encoder/device\n");
  970. return;
  971. }
  972. priv = phys_enc->parent->dev->dev_private;
  973. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  974. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  975. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  976. !phys_enc->hw_intf, !phys_enc->hw_ctl);
  977. return;
  978. }
  979. SDE_DEBUG_VIDENC(vid_enc, "\n");
  980. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  981. return;
  982. else if (!sde_encoder_phys_vid_is_master(phys_enc))
  983. goto exit;
  984. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  985. SDE_ERROR("already disabled\n");
  986. return;
  987. }
  988. if (sde_in_trusted_vm(phys_enc->sde_kms))
  989. goto exit;
  990. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  991. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
  992. sde_encoder_phys_inc_pending(phys_enc);
  993. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  994. if (phys_enc->hw_intf->ops.reset_counter)
  995. phys_enc->hw_intf->ops.reset_counter(phys_enc->hw_intf);
  996. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  997. if (phys_enc->hw_intf->ops.get_status)
  998. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  999. &intf_status);
  1000. if (intf_status.is_en) {
  1001. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  1002. sde_encoder_phys_inc_pending(phys_enc);
  1003. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  1004. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  1005. }
  1006. sde_encoder_helper_phys_disable(phys_enc, NULL);
  1007. exit:
  1008. SDE_EVT32(DRMID(phys_enc->parent),
  1009. atomic_read(&phys_enc->pending_retire_fence_cnt));
  1010. phys_enc->vfp_cached = 0;
  1011. phys_enc->enable_state = SDE_ENC_DISABLED;
  1012. }
  1013. static int sde_encoder_phys_vid_poll_for_active_region(struct sde_encoder_phys *phys_enc)
  1014. {
  1015. struct sde_encoder_phys_vid *vid_enc;
  1016. struct intf_timing_params *timing;
  1017. u32 line_cnt, v_inactive, poll_time_us, trial = 0;
  1018. if (!phys_enc || !phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
  1019. return -EINVAL;
  1020. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1021. timing = &vid_enc->timing_params;
  1022. /* if programmable fetch is not enabled return early or if it is not a DSI interface*/
  1023. if (!programmable_fetch_get_num_lines(vid_enc, timing) ||
  1024. phys_enc->hw_intf->cap->type != INTF_DSI)
  1025. return 0;
  1026. poll_time_us = DIV_ROUND_UP(1000000, timing->vrefresh) / MAX_POLL_CNT;
  1027. v_inactive = timing->v_front_porch + timing->v_back_porch + timing->vsync_pulse_width;
  1028. do {
  1029. usleep_range(poll_time_us, poll_time_us + 5);
  1030. line_cnt = phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
  1031. trial++;
  1032. } while ((trial < MAX_POLL_CNT) && (line_cnt < v_inactive));
  1033. return (trial >= MAX_POLL_CNT) ? -ETIMEDOUT : 0;
  1034. }
  1035. static void sde_encoder_phys_vid_handle_post_kickoff(
  1036. struct sde_encoder_phys *phys_enc)
  1037. {
  1038. unsigned long lock_flags;
  1039. struct sde_encoder_phys_vid *vid_enc;
  1040. u32 avr_mode;
  1041. u32 ret;
  1042. if (!phys_enc) {
  1043. SDE_ERROR("invalid encoder\n");
  1044. return;
  1045. }
  1046. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1047. SDE_DEBUG_VIDENC(vid_enc, "enable_state %d\n", phys_enc->enable_state);
  1048. /*
  1049. * Video mode must flush CTL before enabling timing engine
  1050. * Video encoders need to turn on their interfaces now
  1051. */
  1052. if (phys_enc->enable_state == SDE_ENC_ENABLING) {
  1053. if (sde_encoder_phys_vid_is_master(phys_enc)) {
  1054. SDE_EVT32(DRMID(phys_enc->parent),
  1055. phys_enc->hw_intf->idx - INTF_0);
  1056. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  1057. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf,
  1058. 1);
  1059. spin_unlock_irqrestore(phys_enc->enc_spinlock,
  1060. lock_flags);
  1061. ret = sde_encoder_phys_vid_poll_for_active_region(phys_enc);
  1062. if (ret)
  1063. SDE_DEBUG_VIDENC(vid_enc, "poll for active failed ret:%d\n", ret);
  1064. }
  1065. phys_enc->enable_state = SDE_ENC_ENABLED;
  1066. }
  1067. avr_mode = sde_connector_get_qsync_mode(phys_enc->connector);
  1068. if (avr_mode && vid_enc->base.hw_intf->ops.avr_trigger) {
  1069. vid_enc->base.hw_intf->ops.avr_trigger(vid_enc->base.hw_intf);
  1070. SDE_EVT32(DRMID(phys_enc->parent),
  1071. phys_enc->hw_intf->idx - INTF_0,
  1072. SDE_EVTLOG_FUNC_CASE9);
  1073. }
  1074. }
  1075. static void sde_encoder_phys_vid_prepare_for_commit(
  1076. struct sde_encoder_phys *phys_enc)
  1077. {
  1078. struct sde_connector_state *c_state;
  1079. if (!phys_enc || !phys_enc->parent) {
  1080. SDE_ERROR("invalid encoder parameters\n");
  1081. return;
  1082. }
  1083. if (phys_enc->connector && phys_enc->connector->state) {
  1084. c_state = to_sde_connector_state(phys_enc->connector->state);
  1085. if (!c_state) {
  1086. SDE_ERROR("invalid connector state\n");
  1087. return;
  1088. }
  1089. if (!msm_is_mode_seamless_vrr(&c_state->msm_mode)
  1090. && sde_connector_is_qsync_updated(phys_enc->connector))
  1091. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  1092. }
  1093. }
  1094. static void sde_encoder_phys_vid_irq_control(struct sde_encoder_phys *phys_enc,
  1095. bool enable)
  1096. {
  1097. struct sde_encoder_phys_vid *vid_enc;
  1098. int ret;
  1099. if (!phys_enc)
  1100. return;
  1101. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1102. SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  1103. enable, atomic_read(&phys_enc->vblank_refcount));
  1104. if (enable) {
  1105. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  1106. if (ret)
  1107. return;
  1108. sde_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
  1109. } else {
  1110. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  1111. sde_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
  1112. }
  1113. }
  1114. static int sde_encoder_phys_vid_get_line_count(
  1115. struct sde_encoder_phys *phys_enc)
  1116. {
  1117. if (!phys_enc)
  1118. return -EINVAL;
  1119. if (!sde_encoder_phys_vid_is_master(phys_enc))
  1120. return -EINVAL;
  1121. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
  1122. return -EINVAL;
  1123. return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
  1124. }
  1125. static u32 sde_encoder_phys_vid_get_underrun_line_count(
  1126. struct sde_encoder_phys *phys_enc)
  1127. {
  1128. u32 underrun_linecount = 0xebadebad;
  1129. u32 intf_intr_status = 0xebadebad;
  1130. struct intf_status intf_status = {0};
  1131. if (!phys_enc)
  1132. return -EINVAL;
  1133. if (!sde_encoder_phys_vid_is_master(phys_enc) || !phys_enc->hw_intf)
  1134. return -EINVAL;
  1135. if (phys_enc->hw_intf->ops.get_status)
  1136. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  1137. &intf_status);
  1138. if (phys_enc->hw_intf->ops.get_underrun_line_count)
  1139. underrun_linecount =
  1140. phys_enc->hw_intf->ops.get_underrun_line_count(
  1141. phys_enc->hw_intf);
  1142. if (phys_enc->hw_intf->ops.get_intr_status)
  1143. intf_intr_status = phys_enc->hw_intf->ops.get_intr_status(
  1144. phys_enc->hw_intf);
  1145. SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
  1146. intf_status.frame_count, intf_status.line_count,
  1147. intf_intr_status);
  1148. return underrun_linecount;
  1149. }
  1150. static int sde_encoder_phys_vid_wait_for_active(
  1151. struct sde_encoder_phys *phys_enc)
  1152. {
  1153. struct drm_display_mode mode;
  1154. struct sde_encoder_phys_vid *vid_enc;
  1155. u32 ln_cnt, min_ln_cnt, active_lns_cnt;
  1156. u32 retry = MAX_POLL_CNT;
  1157. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1158. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) {
  1159. SDE_ERROR_VIDENC(vid_enc, "invalid vid_enc params\n");
  1160. return -EINVAL;
  1161. }
  1162. mode = phys_enc->cached_mode;
  1163. min_ln_cnt = (mode.vtotal - mode.vsync_start) +
  1164. (mode.vsync_end - mode.vsync_start);
  1165. active_lns_cnt = mode.vdisplay;
  1166. while (retry) {
  1167. ln_cnt = phys_enc->hw_intf->ops.get_line_count(
  1168. phys_enc->hw_intf);
  1169. if ((ln_cnt >= min_ln_cnt) &&
  1170. (ln_cnt < (active_lns_cnt + min_ln_cnt))) {
  1171. SDE_DEBUG_VIDENC(vid_enc,
  1172. "Needed lines left line_cnt=%d\n",
  1173. ln_cnt);
  1174. return 0;
  1175. }
  1176. SDE_ERROR_VIDENC(vid_enc, "line count is less. line_cnt = %d\n", ln_cnt);
  1177. udelay(POLL_TIME_USEC_FOR_LN_CNT);
  1178. retry--;
  1179. }
  1180. return -EINVAL;
  1181. }
  1182. void sde_encoder_phys_vid_add_enc_to_minidump(struct sde_encoder_phys *phys_enc)
  1183. {
  1184. struct sde_encoder_phys_vid *vid_enc;
  1185. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1186. sde_mini_dump_add_va_region("sde_enc_phys_vid", sizeof(*vid_enc), vid_enc);
  1187. }
  1188. static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
  1189. {
  1190. ops->is_master = sde_encoder_phys_vid_is_master;
  1191. ops->mode_set = sde_encoder_phys_vid_mode_set;
  1192. ops->cont_splash_mode_set = sde_encoder_phys_vid_cont_splash_mode_set;
  1193. ops->mode_fixup = sde_encoder_phys_vid_mode_fixup;
  1194. ops->enable = sde_encoder_phys_vid_enable;
  1195. ops->disable = sde_encoder_phys_vid_disable;
  1196. ops->destroy = sde_encoder_phys_vid_destroy;
  1197. ops->get_hw_resources = sde_encoder_phys_vid_get_hw_resources;
  1198. ops->control_vblank_irq = sde_encoder_phys_vid_control_vblank_irq;
  1199. ops->wait_for_commit_done = sde_encoder_phys_vid_wait_for_commit_done;
  1200. ops->wait_for_vblank = sde_encoder_phys_vid_wait_for_vblank_no_notify;
  1201. ops->wait_for_tx_complete = sde_encoder_phys_vid_wait_for_vblank;
  1202. ops->irq_control = sde_encoder_phys_vid_irq_control;
  1203. ops->prepare_for_kickoff = sde_encoder_phys_vid_prepare_for_kickoff;
  1204. ops->handle_post_kickoff = sde_encoder_phys_vid_handle_post_kickoff;
  1205. ops->needs_single_flush = sde_encoder_phys_needs_single_flush;
  1206. ops->setup_misr = sde_encoder_helper_setup_misr;
  1207. ops->collect_misr = sde_encoder_helper_collect_misr;
  1208. ops->trigger_flush = sde_encoder_helper_trigger_flush;
  1209. ops->hw_reset = sde_encoder_helper_hw_reset;
  1210. ops->get_line_count = sde_encoder_phys_vid_get_line_count;
  1211. ops->wait_dma_trigger = sde_encoder_phys_vid_wait_dma_trigger;
  1212. ops->wait_for_active = sde_encoder_phys_vid_wait_for_active;
  1213. ops->prepare_commit = sde_encoder_phys_vid_prepare_for_commit;
  1214. ops->get_underrun_line_count =
  1215. sde_encoder_phys_vid_get_underrun_line_count;
  1216. ops->add_to_minidump = sde_encoder_phys_vid_add_enc_to_minidump;
  1217. }
  1218. struct sde_encoder_phys *sde_encoder_phys_vid_init(
  1219. struct sde_enc_phys_init_params *p)
  1220. {
  1221. struct sde_encoder_phys *phys_enc = NULL;
  1222. struct sde_encoder_phys_vid *vid_enc = NULL;
  1223. struct sde_hw_mdp *hw_mdp;
  1224. struct sde_encoder_irq *irq;
  1225. int i, ret = 0;
  1226. if (!p) {
  1227. ret = -EINVAL;
  1228. goto fail;
  1229. }
  1230. vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
  1231. if (!vid_enc) {
  1232. ret = -ENOMEM;
  1233. goto fail;
  1234. }
  1235. phys_enc = &vid_enc->base;
  1236. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1237. if (IS_ERR_OR_NULL(hw_mdp)) {
  1238. ret = PTR_ERR(hw_mdp);
  1239. SDE_ERROR("failed to get mdptop\n");
  1240. goto fail;
  1241. }
  1242. phys_enc->hw_mdptop = hw_mdp;
  1243. phys_enc->intf_idx = p->intf_idx;
  1244. SDE_DEBUG_VIDENC(vid_enc, "\n");
  1245. sde_encoder_phys_vid_init_ops(&phys_enc->ops);
  1246. phys_enc->parent = p->parent;
  1247. phys_enc->parent_ops = p->parent_ops;
  1248. phys_enc->sde_kms = p->sde_kms;
  1249. phys_enc->split_role = p->split_role;
  1250. phys_enc->intf_mode = INTF_MODE_VIDEO;
  1251. phys_enc->enc_spinlock = p->enc_spinlock;
  1252. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1253. phys_enc->comp_type = p->comp_type;
  1254. phys_enc->kickoff_timeout_ms = DEFAULT_KICKOFF_TIMEOUT_MS;
  1255. for (i = 0; i < INTR_IDX_MAX; i++) {
  1256. irq = &phys_enc->irq[i];
  1257. INIT_LIST_HEAD(&irq->cb.list);
  1258. irq->irq_idx = -EINVAL;
  1259. irq->hw_idx = -EINVAL;
  1260. irq->cb.arg = phys_enc;
  1261. }
  1262. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  1263. irq->name = "vsync_irq";
  1264. irq->intr_type = SDE_IRQ_TYPE_INTF_VSYNC;
  1265. irq->intr_idx = INTR_IDX_VSYNC;
  1266. irq->cb.func = sde_encoder_phys_vid_vblank_irq;
  1267. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  1268. irq->name = "underrun";
  1269. irq->intr_type = SDE_IRQ_TYPE_INTF_UNDER_RUN;
  1270. irq->intr_idx = INTR_IDX_UNDERRUN;
  1271. irq->cb.func = sde_encoder_phys_vid_underrun_irq;
  1272. atomic_set(&phys_enc->vblank_refcount, 0);
  1273. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  1274. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1275. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1276. phys_enc->enable_state = SDE_ENC_DISABLED;
  1277. SDE_DEBUG_VIDENC(vid_enc, "created intf idx:%d\n", p->intf_idx);
  1278. return phys_enc;
  1279. fail:
  1280. SDE_ERROR("failed to create encoder\n");
  1281. if (vid_enc)
  1282. sde_encoder_phys_vid_destroy(phys_enc);
  1283. return ERR_PTR(ret);
  1284. }