hal_be_generic_api.h 117 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include "txmon_tlvs.h"
  27. /*
  28. * Debug macro to print the TLV header tag
  29. */
  30. #define SHOW_DEFINED(x) do {} while (0)
  31. #if defined(QCA_MONITOR_2_0_SUPPORT) && !defined(TX_MONITOR_WORD_MASK)
  32. typedef struct tx_fes_setup hal_tx_fes_setup_t;
  33. typedef struct tx_peer_entry hal_tx_peer_entry_t;
  34. typedef struct tx_queue_extension hal_tx_queue_ext_t;
  35. typedef struct tx_msdu_start hal_tx_msdu_start_t;
  36. typedef struct tx_mpdu_start hal_tx_mpdu_start_t;
  37. typedef struct tx_fes_status_end hal_tx_fes_status_end_t;
  38. typedef struct response_end_status hal_response_end_status_t;
  39. typedef struct tx_fes_status_prot hal_tx_fes_status_prot_t;
  40. typedef struct pcu_ppdu_setup_init hal_pcu_ppdu_setup_t;
  41. #endif
  42. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  43. static inline void
  44. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  45. struct hal_tx_completion_status *ts)
  46. {
  47. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  48. BUFFER_TIMESTAMP);
  49. }
  50. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  51. static inline void
  52. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  53. struct hal_tx_completion_status *ts)
  54. {
  55. }
  56. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  57. /**
  58. * hal_tx_comp_get_status_generic_be() - TQM Release reason
  59. * @desc: WBM descriptor
  60. * @ts1: completion ring Tx status
  61. * @hal: hal_soc
  62. *
  63. * This function will parse the WBM completion descriptor and populate in
  64. * HAL structure
  65. *
  66. * Return: none
  67. */
  68. static inline void
  69. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  70. struct hal_soc *hal)
  71. {
  72. uint8_t rate_stats_valid = 0;
  73. uint32_t rate_stats = 0;
  74. struct hal_tx_completion_status *ts =
  75. (struct hal_tx_completion_status *)ts1;
  76. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  77. TQM_STATUS_NUMBER);
  78. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  79. ACK_FRAME_RSSI);
  80. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  81. FIRST_MSDU);
  82. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  83. LAST_MSDU);
  84. #if 0
  85. // TODO - This has to be calculated form first and last msdu
  86. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  87. WBM2SW_COMPLETION_RING_TX,
  88. MSDU_PART_OF_AMSDU);
  89. #endif
  90. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  91. SW_PEER_ID);
  92. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  93. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  94. TRANSMIT_COUNT);
  95. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  96. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  97. TX_RATE_STATS_INFO_VALID, rate_stats);
  98. ts->valid = rate_stats_valid;
  99. if (rate_stats_valid) {
  100. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  101. rate_stats);
  102. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  103. TRANSMIT_PKT_TYPE, rate_stats);
  104. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  105. TRANSMIT_STBC, rate_stats);
  106. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  107. rate_stats);
  108. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  109. rate_stats);
  110. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  111. rate_stats);
  112. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  113. rate_stats);
  114. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  115. rate_stats);
  116. }
  117. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  118. ts->status = hal_tx_comp_get_release_reason(
  119. desc,
  120. hal_soc_to_hal_soc_handle(hal));
  121. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  122. TX_RATE_STATS_INFO_TX_RATE_STATS);
  123. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  124. }
  125. /**
  126. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  127. * @soc: HAL SoC context
  128. * @map: PCP-TID mapping table
  129. *
  130. * PCP are mapped to 8 TID values using TID values programmed
  131. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  132. * The mapping register has TID mapping for 8 PCP values
  133. *
  134. * Return: none
  135. */
  136. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  137. {
  138. uint32_t addr, value;
  139. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  140. MAC_TCL_REG_REG_BASE);
  141. value = (map[0] |
  142. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  143. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  144. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  145. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  146. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  147. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  148. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  149. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  150. }
  151. /**
  152. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  153. * value received from user-space
  154. * @soc: HAL SoC context
  155. * @pcp: pcp value
  156. * @tid : tid value
  157. *
  158. * Return: void
  159. */
  160. static void
  161. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  162. uint8_t pcp, uint8_t tid)
  163. {
  164. uint32_t addr, value, regval;
  165. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  166. MAC_TCL_REG_REG_BASE);
  167. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  168. /* Read back previous PCP TID config and update
  169. * with new config.
  170. */
  171. regval = HAL_REG_READ(soc, addr);
  172. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  173. regval |= value;
  174. HAL_REG_WRITE(soc, addr,
  175. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  176. }
  177. /**
  178. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  179. * @soc: HAL SoC context
  180. * @value: priority value
  181. *
  182. * Return: void
  183. */
  184. static
  185. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  186. {
  187. uint32_t addr;
  188. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  189. MAC_TCL_REG_REG_BASE);
  190. HAL_REG_WRITE(soc, addr,
  191. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  192. }
  193. /**
  194. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  195. * @rx_pkt_tlv_size: TLV size for regular RX packets
  196. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  197. *
  198. * Return: size of rx pkt tlv before the actual data
  199. */
  200. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  201. uint16_t *rx_mon_pkt_tlv_size)
  202. {
  203. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  204. /* For now mon pkt tlv is same as rx pkt tlv */
  205. *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN;
  206. }
  207. /**
  208. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  209. * @rx_fst: Pointer to the Rx Flow Search Table
  210. * @hal_hash: HAL 5 tuple hash
  211. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  212. *
  213. * Return: Success/Failure
  214. */
  215. static void *
  216. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  217. uint8_t *flow_tuple_info)
  218. {
  219. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  220. void *hal_fse = NULL;
  221. struct hal_flow_tuple_info *tuple_info
  222. = (struct hal_flow_tuple_info *)flow_tuple_info;
  223. hal_fse = (uint8_t *)fst->base_vaddr +
  224. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  225. if (!hal_fse || !tuple_info)
  226. return NULL;
  227. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  228. return NULL;
  229. tuple_info->src_ip_127_96 =
  230. qdf_ntohl(HAL_GET_FLD(hal_fse,
  231. RX_FLOW_SEARCH_ENTRY,
  232. SRC_IP_127_96));
  233. tuple_info->src_ip_95_64 =
  234. qdf_ntohl(HAL_GET_FLD(hal_fse,
  235. RX_FLOW_SEARCH_ENTRY,
  236. SRC_IP_95_64));
  237. tuple_info->src_ip_63_32 =
  238. qdf_ntohl(HAL_GET_FLD(hal_fse,
  239. RX_FLOW_SEARCH_ENTRY,
  240. SRC_IP_63_32));
  241. tuple_info->src_ip_31_0 =
  242. qdf_ntohl(HAL_GET_FLD(hal_fse,
  243. RX_FLOW_SEARCH_ENTRY,
  244. SRC_IP_31_0));
  245. tuple_info->dest_ip_127_96 =
  246. qdf_ntohl(HAL_GET_FLD(hal_fse,
  247. RX_FLOW_SEARCH_ENTRY,
  248. DEST_IP_127_96));
  249. tuple_info->dest_ip_95_64 =
  250. qdf_ntohl(HAL_GET_FLD(hal_fse,
  251. RX_FLOW_SEARCH_ENTRY,
  252. DEST_IP_95_64));
  253. tuple_info->dest_ip_63_32 =
  254. qdf_ntohl(HAL_GET_FLD(hal_fse,
  255. RX_FLOW_SEARCH_ENTRY,
  256. DEST_IP_63_32));
  257. tuple_info->dest_ip_31_0 =
  258. qdf_ntohl(HAL_GET_FLD(hal_fse,
  259. RX_FLOW_SEARCH_ENTRY,
  260. DEST_IP_31_0));
  261. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  262. RX_FLOW_SEARCH_ENTRY,
  263. DEST_PORT);
  264. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  265. RX_FLOW_SEARCH_ENTRY,
  266. SRC_PORT);
  267. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  268. RX_FLOW_SEARCH_ENTRY,
  269. L4_PROTOCOL);
  270. return hal_fse;
  271. }
  272. /**
  273. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  274. * @rx_fst: Pointer to the Rx Flow Search Table
  275. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  276. *
  277. * Return: Success/Failure
  278. */
  279. static QDF_STATUS
  280. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  281. {
  282. uint8_t *fse = (uint8_t *)hal_rx_fse;
  283. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  284. return QDF_STATUS_E_NOENT;
  285. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  286. return QDF_STATUS_SUCCESS;
  287. }
  288. /**
  289. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  290. *
  291. * Return: size of each entry/flow in Rx FST
  292. */
  293. static inline uint32_t
  294. hal_rx_fst_get_fse_size_be(void)
  295. {
  296. return HAL_RX_FST_ENTRY_SIZE;
  297. }
  298. /*
  299. * TX MONITOR
  300. */
  301. #ifdef QCA_MONITOR_2_0_SUPPORT
  302. /**
  303. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  304. * @tx_tlv_hdr: pointer to TLV header
  305. *
  306. * Return: bool based on tlv tag matches monitor buffer address tlv
  307. */
  308. static inline bool
  309. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  310. {
  311. uint32_t tlv_tag;
  312. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  313. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  314. return true;
  315. return false;
  316. }
  317. /**
  318. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  319. * @tx_tlv: pointer to TLV header
  320. * @packet_info: place holder for packet info
  321. *
  322. * Return: Address to void
  323. */
  324. static inline void
  325. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  326. {
  327. struct hal_mon_packet_info *pkt_info;
  328. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  329. pkt_info = (struct hal_mon_packet_info *)packet_info;
  330. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  331. (addr->buffer_virt_addr_31_0));
  332. pkt_info->dma_length = addr->dma_length + 1;
  333. pkt_info->msdu_continuation = addr->msdu_continuation;
  334. pkt_info->truncated = addr->truncated;
  335. }
  336. /**
  337. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  338. *
  339. * @tx_tlv: pointer to tx_fes_setup tlv header
  340. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  341. *
  342. * Return: void
  343. */
  344. static inline void
  345. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  346. struct hal_tx_ppdu_info *tx_ppdu_info)
  347. {
  348. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  349. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  350. if (tx_ppdu_info->num_users == 0)
  351. tx_ppdu_info->num_users = 1;
  352. TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  353. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  354. }
  355. /**
  356. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  357. *
  358. * @tx_tlv: pointer to tx_fes_setup tlv header
  359. *
  360. * Return: number of users
  361. */
  362. static inline uint8_t
  363. hal_txmon_get_num_users(void *tx_tlv)
  364. {
  365. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  366. return tx_fes_setup->number_of_users;
  367. }
  368. /**
  369. * hal_txmon_parse_tx_fes_status_end() - parse tx_fes_status_end tlv
  370. *
  371. * @tx_tlv: pointer to tx_fes_status_end tlv header
  372. * @ppdu_info: pointer to hal_tx_ppdu_info
  373. * @tx_status_info: pointer to hal_tx_status_info
  374. *
  375. * Return: void
  376. */
  377. static inline void
  378. hal_txmon_parse_tx_fes_status_end(void *tx_tlv,
  379. struct hal_tx_ppdu_info *ppdu_info,
  380. struct hal_tx_status_info *tx_status_info)
  381. {
  382. hal_tx_fes_status_end_t *tx_fes_end = (hal_tx_fes_status_end_t *)tx_tlv;
  383. if (tx_fes_end->phytx_abort_request_info_valid) {
  384. TXMON_STATUS_INFO(tx_status_info, phy_abort_reason) =
  385. tx_fes_end->phytx_abort_request_info_details.phytx_abort_reason;
  386. TXMON_STATUS_INFO(tx_status_info, phy_abort_user_number) =
  387. tx_fes_end->phytx_abort_request_info_details.user_number;
  388. }
  389. TXMON_STATUS_INFO(tx_status_info,
  390. response_type) = tx_fes_end->response_type;
  391. TXMON_STATUS_INFO(tx_status_info,
  392. r2r_to_follow) = tx_fes_end->r2r_end_status_to_follow;
  393. /* update phy timestamp to ppdu timestamp */
  394. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  395. (tx_fes_end->start_of_frame_timestamp_15_0 |
  396. tx_fes_end->start_of_frame_timestamp_31_16 <<
  397. HAL_TX_LSB(TX_FES_STATUS_END, START_OF_FRAME_TIMESTAMP_31_16));
  398. }
  399. /**
  400. * hal_txmon_parse_response_end_status() - parse response_end_status tlv
  401. *
  402. * @tx_tlv: pointer to response_end_status tlv header
  403. * @ppdu_info: pointer to hal_tx_ppdu_info
  404. * @tx_status_info: pointer to hal_tx_status_info
  405. *
  406. * Return: void
  407. */
  408. static inline void
  409. hal_txmon_parse_response_end_status(void *tx_tlv,
  410. struct hal_tx_ppdu_info *ppdu_info,
  411. struct hal_tx_status_info *tx_status_info)
  412. {
  413. hal_response_end_status_t *resp_end_status = NULL;
  414. resp_end_status = (hal_response_end_status_t *)tx_tlv;
  415. TXMON_HAL_STATUS(ppdu_info, bw) = resp_end_status->coex_based_tx_bw;
  416. TXMON_STATUS_INFO(tx_status_info, generated_response) =
  417. resp_end_status->generated_response;
  418. TXMON_STATUS_INFO(tx_status_info, mba_count) =
  419. resp_end_status->mba_user_count;
  420. TXMON_STATUS_INFO(tx_status_info, mba_fake_bitmap_count) =
  421. resp_end_status->mba_fake_bitmap_count;
  422. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  423. (resp_end_status->start_of_frame_timestamp_15_0 |
  424. (resp_end_status->start_of_frame_timestamp_31_16 << 16));
  425. }
  426. /**
  427. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  428. *
  429. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  430. * @data_status_info: pointer to data hal_tx_status_info
  431. * @prot_status_info: pointer to protection hal_tx_status_info
  432. *
  433. * Return: void
  434. */
  435. static inline void
  436. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  437. struct hal_tx_status_info *data_status_info,
  438. struct hal_tx_status_info *prot_status_info)
  439. {
  440. hal_pcu_ppdu_setup_t *pcu_init = (hal_pcu_ppdu_setup_t *)tx_tlv;
  441. prot_status_info->protection_addr =
  442. pcu_init->use_address_fields_for_protection;
  443. /* protection frame address 1 */
  444. *(uint32_t *)&prot_status_info->addr1[0] =
  445. pcu_init->protection_frame_ad1_31_0;
  446. *(uint32_t *)&prot_status_info->addr1[4] =
  447. pcu_init->protection_frame_ad1_47_32;
  448. /* protection frame address 2 */
  449. *(uint32_t *)&prot_status_info->addr2[0] =
  450. pcu_init->protection_frame_ad2_15_0;
  451. *(uint32_t *)&prot_status_info->addr2[2] =
  452. pcu_init->protection_frame_ad2_47_16;
  453. /* protection frame address 3 */
  454. *(uint32_t *)&prot_status_info->addr3[0] =
  455. pcu_init->protection_frame_ad3_31_0;
  456. *(uint32_t *)&prot_status_info->addr3[4] =
  457. pcu_init->protection_frame_ad3_47_32;
  458. /* protection frame address 4 */
  459. *(uint32_t *)&prot_status_info->addr4[0] =
  460. pcu_init->protection_frame_ad4_15_0;
  461. *(uint32_t *)&prot_status_info->addr4[2] =
  462. pcu_init->protection_frame_ad4_47_16;
  463. }
  464. /**
  465. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  466. *
  467. * @tx_tlv: pointer to peer_entry tlv header
  468. * @user_id: user_id
  469. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  470. * @tx_status_info: pointer to hal_tx_status_info
  471. *
  472. * Return: void
  473. */
  474. static inline void
  475. hal_txmon_parse_peer_entry(void *tx_tlv,
  476. uint8_t user_id,
  477. struct hal_tx_ppdu_info *tx_ppdu_info,
  478. struct hal_tx_status_info *tx_status_info)
  479. {
  480. hal_tx_peer_entry_t *peer_entry = (hal_tx_peer_entry_t *)tx_tlv;
  481. *(uint32_t *)&tx_status_info->addr1[0] =
  482. peer_entry->mac_addr_a_31_0;
  483. *(uint32_t *)&tx_status_info->addr1[4] =
  484. peer_entry->mac_addr_a_47_32;
  485. *(uint32_t *)&tx_status_info->addr2[0] =
  486. peer_entry->mac_addr_b_15_0;
  487. *(uint32_t *)&tx_status_info->addr2[2] =
  488. peer_entry->mac_addr_b_47_16;
  489. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  490. peer_entry->sw_peer_id;
  491. }
  492. /**
  493. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  494. *
  495. * @tx_tlv: pointer to queue exten tlv header
  496. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  497. *
  498. * Return: void
  499. */
  500. static inline void
  501. hal_txmon_parse_queue_exten(void *tx_tlv,
  502. struct hal_tx_ppdu_info *tx_ppdu_info)
  503. {
  504. hal_tx_queue_ext_t *queue_ext = (hal_tx_queue_ext_t *)tx_tlv;
  505. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = queue_ext->frame_ctl;
  506. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  507. }
  508. /**
  509. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  510. *
  511. * @tx_tlv: pointer to mpdu start tlv header
  512. * @user_id: user id
  513. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  514. *
  515. * Return: void
  516. */
  517. static inline void
  518. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  519. struct hal_tx_ppdu_info *tx_ppdu_info)
  520. {
  521. hal_tx_mpdu_start_t *mpdu_start = (hal_tx_mpdu_start_t *)tx_tlv;
  522. TXMON_HAL_USER(tx_ppdu_info, user_id, start_seq) =
  523. mpdu_start->mpdu_sequence_number;
  524. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  525. }
  526. /**
  527. * hal_txmon_parse_msdu_start() - parse msdu start tlv
  528. *
  529. * @tx_tlv: pointer to msdu start tlv header
  530. * @user_id: user id
  531. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  532. *
  533. * Return: void
  534. */
  535. static inline void
  536. hal_txmon_parse_msdu_start(void *tx_tlv, uint8_t user_id,
  537. struct hal_tx_ppdu_info *tx_ppdu_info)
  538. {
  539. }
  540. /**
  541. * hal_txmon_parse_tx_fes_status_prot() - parse tx_fes_status_prot tlv
  542. *
  543. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  544. * @ppdu_info: pointer to hal_tx_ppdu_info
  545. * @tx_status_info: pointer to hal_tx_status_info
  546. *
  547. * Return: void
  548. */
  549. static inline void
  550. hal_txmon_parse_tx_fes_status_prot(void *tx_tlv,
  551. struct hal_tx_ppdu_info *ppdu_info,
  552. struct hal_tx_status_info *tx_status_info)
  553. {
  554. hal_tx_fes_status_prot_t *fes_prot = (hal_tx_fes_status_prot_t *)tx_tlv;
  555. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  556. (fes_prot->start_of_frame_timestamp_15_0 |
  557. fes_prot->start_of_frame_timestamp_31_16 << 15);
  558. }
  559. /**
  560. * get_ru_offset_from_start_index() - api to get ru offset from ru index
  561. *
  562. * @ru_size: RU size
  563. * @start_idx: Start index
  564. *
  565. * Return: uint8_t ru allocation offset
  566. */
  567. static inline
  568. uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx)
  569. {
  570. uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = {
  571. {0, 0, 0, 0, 0, 0, 0},
  572. {1, 0, 0, 0, 0, 0, 0},
  573. {2, 1, 0, 0, 0, 0, 0},
  574. {3, 1, 0, 0, 0, 0, 0},
  575. {4, 0, 0, 0, 0, 0, 0},
  576. {5, 2, 1, 0, 0, 0, 0},
  577. {6, 2, 1, 0, 0, 0, 0},
  578. {7, 3, 1, 0, 0, 0, 0},
  579. {8, 3, 1, 0, 0, 0, 0},
  580. {9, 4, 2, 1, 0, 0, 0},
  581. {10, 4, 2, 1, 0, 0, 0},
  582. {11, 5, 2, 1, 0, 0, 0},
  583. {12, 5, 2, 1, 0, 0, 0},
  584. {13, 0, 0, 1, 0, 0, 0},
  585. {14, 6, 3, 1, 0, 0, 0},
  586. {15, 6, 3, 1, 0, 0, 0},
  587. {16, 7, 3, 1, 0, 0, 0},
  588. {17, 7, 3, 1, 0, 0, 0},
  589. {18, 0, 0, 0, 0, 0, 0},
  590. {19, 8, 4, 2, 1, 0, 0},
  591. {20, 8, 4, 2, 1, 0, 0},
  592. {21, 9, 4, 2, 1, 0, 0},
  593. {22, 9, 4, 2, 1, 0, 0},
  594. {23, 0, 0, 2, 1, 0, 0},
  595. {24, 10, 5, 2, 1, 0, 0},
  596. {25, 10, 5, 2, 1, 0, 0},
  597. {26, 11, 5, 2, 1, 0, 0},
  598. {27, 11, 5, 2, 1, 0, 0},
  599. {28, 12, 6, 3, 1, 0, 0},
  600. {29, 12, 6, 3, 1, 0, 0},
  601. {30, 13, 6, 3, 1, 0, 0},
  602. {31, 13, 6, 3, 1, 0, 0},
  603. {32, 0, 0, 3, 1, 0, 0},
  604. {33, 14, 7, 3, 1, 0, 0},
  605. {34, 14, 7, 3, 1, 0, 0},
  606. {35, 15, 7, 3, 1, 0, 0},
  607. {36, 15, 7, 3, 1, 0, 0},
  608. };
  609. if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX)
  610. return 0;
  611. return ru_alloc_offset[start_idx][ru_size];
  612. }
  613. /**
  614. * hal_txmon_parse_fw2sw() - parse firmware to software tlv
  615. *
  616. * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header
  617. * @type: place where this tlv is generated
  618. * @status_info: pointer to hal_tx_status_info
  619. *
  620. * Return: void
  621. */
  622. static inline void
  623. hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type,
  624. struct hal_tx_status_info *status_info)
  625. {
  626. uint32_t *msg = (uint32_t *)tx_tlv;
  627. switch (type) {
  628. case TXMON_FW2SW_TYPE_FES_SETUP:
  629. {
  630. uint32_t schedule_id;
  631. uint16_t c_freq1;
  632. uint16_t c_freq2;
  633. uint16_t freq_mhz;
  634. uint8_t phy_mode;
  635. c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg);
  636. c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg);
  637. msg++;
  638. phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg);
  639. freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg);
  640. msg++;
  641. schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg);
  642. TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1;
  643. TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2;
  644. TXMON_STATUS_INFO(status_info, freq) = freq_mhz;
  645. TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode;
  646. TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id;
  647. break;
  648. }
  649. case TXMON_FW2SW_TYPE_FES_SETUP_USER:
  650. {
  651. break;
  652. }
  653. case TXMON_FW2SW_TYPE_FES_SETUP_EXT:
  654. {
  655. break;
  656. }
  657. };
  658. }
  659. /**
  660. * hal_txmon_parse_u_sig_hdr() - parse u_sig header information from tlv
  661. *
  662. * @tx_tlv: pointer to mactx_u_sig_eht_su_mu/tb tlv
  663. * @ppdu_info: pointer to hal_tx_ppdu_info
  664. *
  665. * Return: void
  666. */
  667. static inline void
  668. hal_txmon_parse_u_sig_hdr(void *tx_tlv, struct hal_tx_ppdu_info *ppdu_info)
  669. {
  670. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)tx_tlv;
  671. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  672. uint8_t bad_usig_crc;
  673. bad_usig_crc = HAL_TX_DESC_GET_64(tx_tlv,
  674. MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS,
  675. CRC) ? 0 : 1;
  676. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  677. QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN |
  678. QDF_MON_STATUS_USIG_BW_KNOWN |
  679. QDF_MON_STATUS_USIG_UL_DL_KNOWN |
  680. QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN |
  681. QDF_MON_STATUS_USIG_TXOP_KNOWN;
  682. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  683. (usig_1->phy_version <<
  684. QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT);
  685. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  686. (usig_1->bw << QDF_MON_STATUS_USIG_BW_SHIFT);
  687. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  688. (usig_1->ul_dl << QDF_MON_STATUS_USIG_UL_DL_SHIFT);
  689. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  690. (usig_1->bss_color <<
  691. QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT);
  692. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  693. (usig_1->txop << QDF_MON_STATUS_USIG_TXOP_SHIFT);
  694. TXMON_HAL_STATUS(ppdu_info, usig_common) |= bad_usig_crc;
  695. TXMON_HAL_STATUS(ppdu_info, bw) = usig_1->bw;
  696. TXMON_HAL_STATUS(ppdu_info, usig_flags) = 1;
  697. }
  698. /**
  699. * hal_txmon_populate_he_data_per_user() - populate he data per user
  700. *
  701. * @usr: pointer to hal_txmon_user_desc_per_user
  702. * @user_id: user index
  703. * @ppdu_info: pointer to hal_tx_ppdu_info
  704. *
  705. * Return: void
  706. */
  707. static inline void
  708. hal_txmon_populate_he_data_per_user(struct hal_txmon_user_desc_per_user *usr,
  709. uint32_t user_id,
  710. struct hal_tx_ppdu_info *ppdu_info)
  711. {
  712. uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, he_data1);
  713. uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, he_data2);
  714. uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, he_data3);
  715. uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, he_data5);
  716. uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, he_data6);
  717. /* populate */
  718. /* BEAM CHANGE */
  719. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  720. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  721. he_data5 |= (!!usr->user_bf_type << QDF_MON_STATUS_TXBF_SHIFT);
  722. he_data3 |= (!!usr->user_bf_type << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  723. /* UL/DL known */
  724. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  725. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  726. /* MCS */
  727. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  728. he_data3 |= (usr->mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  729. /* DCM */
  730. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  731. he_data3 |= (usr->dcm << QDF_MON_STATUS_DCM_SHIFT);
  732. /* LDPC EXTRA SYMB */
  733. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  734. he_data3 |= (usr->ldpc_extra_symbol <<
  735. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  736. /* RU offset and RU */
  737. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  738. he_data2 |= (get_ru_offset_from_start_index(usr->ru_size,
  739. usr->ru_start_index) <<
  740. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  741. /* Data BW and RU allocation */
  742. if (usr->ru_size < HAL_MAX_RU_INDEX) {
  743. /* update bandwidth if it is full bandwidth */
  744. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  745. he_data5 = (he_data5 & 0xFFF0) | (4 + usr->ru_size);
  746. }
  747. he_data6 |= (usr->nss & 0xF);
  748. TXMON_HAL_USER(ppdu_info, user_id, mcs) = usr->mcs;
  749. /* update stack variable to ppdu_info */
  750. TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1;
  751. TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2;
  752. TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3;
  753. TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5;
  754. TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6;
  755. }
  756. /**
  757. * hal_txmon_get_user_desc_per_user() - get mactx user desc per user from tlv
  758. *
  759. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  760. * @usr: pointer to hal_txmon_user_desc_per_user
  761. *
  762. * Return: void
  763. */
  764. static inline void
  765. hal_txmon_get_user_desc_per_user(void *tx_tlv,
  766. struct hal_txmon_user_desc_per_user *usr)
  767. {
  768. usr->psdu_length = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  769. PSDU_LENGTH);
  770. usr->ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  771. MACTX_USER_DESC_PER_USER,
  772. RU_START_INDEX);
  773. usr->ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  774. RU_SIZE);
  775. usr->ofdma_mu_mimo_enabled =
  776. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  777. OFDMA_MU_MIMO_ENABLED);
  778. usr->nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  779. NSS) + 1;
  780. usr->stream_offset = HAL_TX_DESC_GET_64(tx_tlv,
  781. MACTX_USER_DESC_PER_USER,
  782. STREAM_OFFSET);
  783. usr->mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  784. usr->dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  785. usr->fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  786. FEC_TYPE);
  787. usr->user_bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  788. USER_BF_TYPE);
  789. usr->drop_user_cbf = HAL_TX_DESC_GET_64(tx_tlv,
  790. MACTX_USER_DESC_PER_USER,
  791. DROP_USER_CBF);
  792. usr->ldpc_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  793. MACTX_USER_DESC_PER_USER,
  794. LDPC_EXTRA_SYMBOL);
  795. usr->force_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  796. MACTX_USER_DESC_PER_USER,
  797. FORCE_EXTRA_SYMBOL);
  798. usr->sw_peer_id = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  799. SW_PEER_ID);
  800. }
  801. /**
  802. * hal_txmon_populate_eht_sig_per_user() - populate eht sig user information
  803. *
  804. * @usr: pointer to hal_txmon_user_desc_per_user
  805. * @user_id: user index
  806. * @ppdu_info: pointer to hal_tx_ppdu_info
  807. *
  808. * Return: void
  809. */
  810. static inline void
  811. hal_txmon_populate_eht_sig_per_user(struct hal_txmon_user_desc_per_user *usr,
  812. uint32_t user_id,
  813. struct hal_tx_ppdu_info *ppdu_info)
  814. {
  815. uint32_t eht_known = 0;
  816. uint32_t eht_data[6] = {0};
  817. uint8_t i = 0;
  818. eht_known = QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN;
  819. eht_data[0] |= (usr->ldpc_extra_symbol <<
  820. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT);
  821. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  822. for (i = 0; i < 6; i++)
  823. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  824. }
  825. /**
  826. * hal_txmon_parse_user_desc_per_user() - parse mactx user desc per user
  827. *
  828. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  829. * @user_id: user index
  830. * @ppdu_info: pointer to hal_tx_ppdu_info
  831. *
  832. * Return: void
  833. */
  834. static inline void
  835. hal_txmon_parse_user_desc_per_user(void *tx_tlv, uint32_t user_id,
  836. struct hal_tx_ppdu_info *ppdu_info)
  837. {
  838. struct hal_txmon_user_desc_per_user usr_info = {0};
  839. hal_txmon_get_user_desc_per_user(tx_tlv, &usr_info);
  840. /* based on preamble type populate user desc user info */
  841. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  842. hal_txmon_populate_he_data_per_user(&usr_info,
  843. user_id, ppdu_info);
  844. hal_txmon_populate_eht_sig_per_user(&usr_info, user_id, ppdu_info);
  845. }
  846. /**
  847. * hal_txmon_get_user_desc_common() - update hal_txmon_usr_desc_common from tlv
  848. *
  849. * @tx_tlv: pointer to mactx_user_desc_common tlv
  850. * @usr_common: pointer to hal_txmon_usr_desc_common
  851. *
  852. * Return: void
  853. */
  854. static inline void
  855. hal_txmon_get_user_desc_common(void *tx_tlv,
  856. struct hal_txmon_usr_desc_common *usr_common)
  857. {
  858. usr_common->ltf_size =
  859. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, LTF_SIZE);
  860. usr_common->pkt_extn_pe =
  861. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  862. PACKET_EXTENSION_PE_DISAMBIGUITY);
  863. usr_common->a_factor =
  864. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  865. PACKET_EXTENSION_A_FACTOR);
  866. usr_common->center_ru_0 =
  867. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_0);
  868. usr_common->center_ru_1 =
  869. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_1);
  870. usr_common->num_ltf_symbols =
  871. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  872. NUM_LTF_SYMBOLS);
  873. usr_common->doppler_indication =
  874. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  875. DOPPLER_INDICATION);
  876. usr_common->spatial_reuse =
  877. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  878. SPATIAL_REUSE);
  879. usr_common->ru_channel_0[0] =
  880. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  881. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0);
  882. usr_common->ru_channel_0[1] =
  883. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  884. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1);
  885. usr_common->ru_channel_0[2] =
  886. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  887. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2);
  888. usr_common->ru_channel_0[3] =
  889. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  890. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3);
  891. usr_common->ru_channel_0[4] =
  892. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  893. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0);
  894. usr_common->ru_channel_0[5] =
  895. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  896. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1);
  897. usr_common->ru_channel_0[6] =
  898. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  899. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2);
  900. usr_common->ru_channel_0[7] =
  901. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  902. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3);
  903. usr_common->ru_channel_1[0] =
  904. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  905. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0);
  906. usr_common->ru_channel_1[1] =
  907. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  908. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1);
  909. usr_common->ru_channel_1[2] =
  910. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  911. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2);
  912. usr_common->ru_channel_1[3] =
  913. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  914. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3);
  915. usr_common->ru_channel_1[4] =
  916. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  917. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0);
  918. usr_common->ru_channel_1[5] =
  919. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  920. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1);
  921. usr_common->ru_channel_1[6] =
  922. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  923. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2);
  924. usr_common->ru_channel_1[7] =
  925. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  926. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3);
  927. }
  928. /**
  929. * hal_txmon_populate_he_data_common() - populate he data common information
  930. *
  931. * @usr_common: pointer to hal_txmon_usr_desc_common
  932. * @user_id: user index
  933. * @ppdu_info: pointer to hal_tx_ppdu_info
  934. *
  935. * Return: void
  936. */
  937. static inline void
  938. hal_txmon_populate_he_data_common(struct hal_txmon_usr_desc_common *usr_common,
  939. uint32_t user_id,
  940. struct hal_tx_ppdu_info *ppdu_info)
  941. {
  942. /* HE data 1 */
  943. TXMON_HAL_USER(ppdu_info,
  944. user_id, he_data1) |= QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  945. /* HE data 2 */
  946. TXMON_HAL_USER(ppdu_info, user_id,
  947. he_data2) |= (QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  948. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN);
  949. /* HE data 5 */
  950. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  951. (usr_common->pkt_extn_pe <<
  952. QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) |
  953. (usr_common->a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) |
  954. ((1 + usr_common->ltf_size) <<
  955. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) |
  956. (usr_common->num_ltf_symbols <<
  957. QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  958. /* HE data 6 */
  959. TXMON_HAL_USER(ppdu_info, user_id,
  960. he_data6) |= (usr_common->doppler_indication <<
  961. QDF_MON_STATUS_DOPPLER_SHIFT);
  962. }
  963. /**
  964. * hal_txmon_populate_he_mu_common() - populate he mu common information
  965. *
  966. * @usr_common: pointer to hal_txmon_usr_desc_common
  967. * @user_id: user index
  968. * @ppdu_info: pointer to hal_tx_ppdu_info
  969. *
  970. * Return: void
  971. */
  972. static inline void
  973. hal_txmon_populate_he_mu_common(struct hal_txmon_usr_desc_common *usr_common,
  974. uint32_t user_id,
  975. struct hal_tx_ppdu_info *ppdu_info)
  976. {
  977. uint16_t he_mu_flag_1 = 0;
  978. uint16_t he_mu_flag_2 = 0;
  979. uint16_t i = 0;
  980. he_mu_flag_1 |= (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  981. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  982. ((usr_common->center_ru_0 <<
  983. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) &
  984. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE));
  985. he_mu_flag_2 |= ((usr_common->center_ru_1 <<
  986. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) &
  987. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE);
  988. for (i = 0; i < usr_common->num_users; i++) {
  989. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  990. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  991. /* channel 1 */
  992. TXMON_HAL_USER(ppdu_info, i, he_RU[0]) =
  993. usr_common->ru_channel_0[0];
  994. TXMON_HAL_USER(ppdu_info, i, he_RU[1]) =
  995. usr_common->ru_channel_0[1];
  996. TXMON_HAL_USER(ppdu_info, i, he_RU[2]) =
  997. usr_common->ru_channel_0[2];
  998. TXMON_HAL_USER(ppdu_info, i, he_RU[3]) =
  999. usr_common->ru_channel_0[3];
  1000. /* channel 2 */
  1001. TXMON_HAL_USER(ppdu_info, i, he_RU[4]) =
  1002. usr_common->ru_channel_1[0];
  1003. TXMON_HAL_USER(ppdu_info, i, he_RU[5]) =
  1004. usr_common->ru_channel_1[1];
  1005. TXMON_HAL_USER(ppdu_info, i, he_RU[6]) =
  1006. usr_common->ru_channel_1[2];
  1007. TXMON_HAL_USER(ppdu_info, i, he_RU[7]) =
  1008. usr_common->ru_channel_1[3];
  1009. }
  1010. }
  1011. /**
  1012. * hal_txmon_populate_eht_sig_common() - populate eht sig common information
  1013. *
  1014. * @usr_common: pointer to hal_txmon_usr_desc_common
  1015. * @user_id: user index
  1016. * @ppdu_info: pointer to hal_tx_ppdu_info
  1017. *
  1018. * Return: void
  1019. */
  1020. static inline void
  1021. hal_txmon_populate_eht_sig_common(struct hal_txmon_usr_desc_common *usr_common,
  1022. uint32_t user_id,
  1023. struct hal_tx_ppdu_info *ppdu_info)
  1024. {
  1025. uint32_t eht_known = 0;
  1026. uint32_t eht_data[9] = {0};
  1027. uint8_t num_ru_allocation_known = 0;
  1028. uint8_t i = 0;
  1029. eht_known = (QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1030. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1031. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN |
  1032. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN |
  1033. QDF_MON_STATUS_EHT_DISREARD_KNOWN);
  1034. eht_data[0] |= (usr_common->spatial_reuse <<
  1035. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1036. eht_data[0] |= (usr_common->num_ltf_symbols <<
  1037. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1038. eht_data[0] |= (usr_common->a_factor <<
  1039. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT);
  1040. eht_data[0] |= (usr_common->pkt_extn_pe <<
  1041. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT);
  1042. eht_data[0] |= (0xF << QDF_MON_STATUS_EHT_DISREGARD_SHIFT);
  1043. switch (TXMON_HAL_STATUS(ppdu_info, bw)) {
  1044. case HAL_EHT_BW_320_2:
  1045. case HAL_EHT_BW_320_1:
  1046. num_ru_allocation_known += 4;
  1047. eht_data[3] |= (usr_common->ru_channel_0[7] <<
  1048. QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT);
  1049. eht_data[3] |= (usr_common->ru_channel_0[6] <<
  1050. QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT);
  1051. eht_data[3] |= (usr_common->ru_channel_0[5] <<
  1052. QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT);
  1053. eht_data[2] |= (usr_common->ru_channel_0[4] <<
  1054. QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT);
  1055. fallthrough;
  1056. case HAL_EHT_BW_160:
  1057. num_ru_allocation_known += 2;
  1058. eht_data[2] |= (usr_common->ru_channel_0[3] <<
  1059. QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT);
  1060. eht_data[2] |= (usr_common->ru_channel_0[2] <<
  1061. QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT);
  1062. fallthrough;
  1063. case HAL_EHT_BW_80:
  1064. num_ru_allocation_known += 1;
  1065. eht_data[1] |= (usr_common->ru_channel_0[1] <<
  1066. QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT);
  1067. fallthrough;
  1068. case HAL_EHT_BW_40:
  1069. case HAL_EHT_BW_20:
  1070. num_ru_allocation_known += 1;
  1071. eht_data[1] |= (usr_common->ru_channel_0[0] <<
  1072. QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT);
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. eht_known |= (num_ru_allocation_known <<
  1078. QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
  1079. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  1080. for (i = 0; i < 4; i++)
  1081. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  1082. }
  1083. /**
  1084. * hal_txmon_parse_user_desc_common() - parse mactx user desc common tlv
  1085. *
  1086. * @tx_tlv: pointer to mactx_user_desc_common tlv
  1087. * @user_id: user index
  1088. * @ppdu_info: pointer to hal_tx_ppdu_info
  1089. *
  1090. * Return: void
  1091. */
  1092. static inline void
  1093. hal_txmon_parse_user_desc_common(void *tx_tlv, uint32_t user_id,
  1094. struct hal_tx_ppdu_info *ppdu_info)
  1095. {
  1096. struct hal_txmon_usr_desc_common usr_common = {0};
  1097. usr_common.num_users = TXMON_HAL(ppdu_info, num_users);
  1098. hal_txmon_get_user_desc_common(tx_tlv, &usr_common);
  1099. TXMON_HAL_STATUS(ppdu_info,
  1100. he_mu_flags) = IS_MULTI_USERS(usr_common.num_users);
  1101. switch (TXMON_HAL_STATUS(ppdu_info, preamble_type)) {
  1102. case TXMON_PKT_TYPE_11AX:
  1103. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  1104. hal_txmon_populate_he_data_common(&usr_common,
  1105. user_id, ppdu_info);
  1106. if (TXMON_HAL_STATUS(ppdu_info, he_mu_flags))
  1107. hal_txmon_populate_he_mu_common(&usr_common,
  1108. user_id, ppdu_info);
  1109. break;
  1110. case TXMON_PKT_TYPE_11BE:
  1111. hal_txmon_populate_eht_sig_common(&usr_common,
  1112. user_id, ppdu_info);
  1113. break;
  1114. }
  1115. }
  1116. /**
  1117. * hal_txmon_parse_eht_sig_non_mumimo_user_info() - parse eht sig non mumimo tlv
  1118. *
  1119. * @tx_tlv: pointer to hal_eht_sig_non_mu_mimo_user_info
  1120. * @user_id: user index
  1121. * @ppdu_info: pointer to hal_tx_ppdu_info
  1122. *
  1123. * Return: void
  1124. */
  1125. static inline void
  1126. hal_txmon_parse_eht_sig_non_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1127. struct hal_tx_ppdu_info *ppdu_info)
  1128. {
  1129. struct hal_eht_sig_non_mu_mimo_user_info *user_info;
  1130. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1131. user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tx_tlv;
  1132. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1133. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1134. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1135. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1136. QDF_MON_STATUS_EHT_USER_NSS_KNOWN |
  1137. QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN;
  1138. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1139. (user_info->sta_id <<
  1140. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1141. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1142. (user_info->mcs <<
  1143. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1144. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1145. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1146. (user_info->nss <<
  1147. QDF_MON_STATUS_EHT_USER_NSS_SHIFT);
  1148. TXMON_HAL_STATUS(ppdu_info, nss) = user_info->nss + 1;
  1149. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1150. (user_info->beamformed <<
  1151. QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT);
  1152. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1153. (user_info->coding <<
  1154. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1155. /* TODO: CRC */
  1156. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1157. }
  1158. /**
  1159. * hal_txmon_parse_eht_sig_mumimo_user_info() - parse eht sig mumimo tlv
  1160. *
  1161. * @tx_tlv: pointer to hal_eht_sig_mu_mimo_user_info
  1162. * @user_id: user index
  1163. * @ppdu_info: pointer to hal_tx_ppdu_info
  1164. *
  1165. * Return: void
  1166. */
  1167. static inline void
  1168. hal_txmon_parse_eht_sig_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1169. struct hal_tx_ppdu_info *ppdu_info)
  1170. {
  1171. struct hal_eht_sig_mu_mimo_user_info *user_info;
  1172. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1173. user_info = (struct hal_eht_sig_mu_mimo_user_info *)tx_tlv;
  1174. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1175. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1176. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1177. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1178. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN;
  1179. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1180. (user_info->sta_id <<
  1181. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1182. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1183. (user_info->mcs <<
  1184. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1185. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1186. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1187. (user_info->coding <<
  1188. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1189. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1190. (user_info->spatial_coding <<
  1191. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT);
  1192. /* TODO: CRC */
  1193. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1194. }
  1195. /**
  1196. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  1197. * from start of fes window
  1198. *
  1199. * @tx_tlv_hdr: pointer to TLV header
  1200. * @num_users: reference to number of user
  1201. *
  1202. * Return: status
  1203. */
  1204. static inline uint32_t
  1205. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  1206. {
  1207. uint32_t tlv_tag, user_id, tlv_len;
  1208. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1209. void *tx_tlv;
  1210. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1211. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  1212. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  1213. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1214. /* window starts with either initiator or response */
  1215. switch (tlv_tag) {
  1216. case WIFITX_FES_SETUP_E:
  1217. {
  1218. *num_users = hal_txmon_get_num_users(tx_tlv);
  1219. if (*num_users == 0)
  1220. *num_users = 1;
  1221. tlv_status = HAL_MON_TX_FES_SETUP;
  1222. break;
  1223. }
  1224. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  1225. {
  1226. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  1227. RX_RESPONSE_REQUIRED_INFO,
  1228. RESPONSE_STA_COUNT);
  1229. if (*num_users == 0)
  1230. *num_users = 1;
  1231. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1232. break;
  1233. }
  1234. };
  1235. return tlv_status;
  1236. }
  1237. /**
  1238. * hal_txmon_get_word_mask_generic_be() - api to get word mask for tx monitor
  1239. * @wmask: pointer to hal_txmon_word_mask_config_t
  1240. *
  1241. * Return: void
  1242. */
  1243. static inline
  1244. void hal_txmon_get_word_mask_generic_be(void *wmask)
  1245. {
  1246. hal_txmon_word_mask_config_t *word_mask = NULL;
  1247. word_mask = (hal_txmon_word_mask_config_t *)wmask;
  1248. qdf_mem_set(word_mask, sizeof(hal_txmon_word_mask_config_t), 0xFF);
  1249. word_mask->compaction_enable = 0;
  1250. }
  1251. /**
  1252. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  1253. * @data_info: populate dp_ppdu_info data
  1254. * @prot_info: populate dp_ppdu_info protection
  1255. * @tlv_tag: Tag
  1256. *
  1257. * Return: dp_tx_ppdu_info pointer
  1258. */
  1259. static inline void *
  1260. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  1261. {
  1262. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  1263. switch (tlv_tag) {
  1264. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  1265. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1266. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  1267. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  1268. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  1269. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  1270. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  1271. case WIFITX_DATA_E:/* DOWNSTREAM */
  1272. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1273. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1274. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1275. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1276. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1277. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1278. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1279. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1280. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1281. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1282. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1283. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1284. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1285. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1286. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  1287. {
  1288. return data_info;
  1289. }
  1290. }
  1291. /*
  1292. * check current prot_tlv_status is start protection
  1293. * check current tlv_tag is either start protection or end protection
  1294. */
  1295. if (TXMON_HAL(prot_ppdu_info,
  1296. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  1297. return prot_info;
  1298. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  1299. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  1300. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  1301. return prot_info;
  1302. }
  1303. return data_info;
  1304. }
  1305. /**
  1306. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  1307. * @data_ppdu_info: hal_txmon data ppdu info
  1308. * @prot_ppdu_info: hal_txmon prot ppdu info
  1309. * @data_status_info: pointer to data status info
  1310. * @prot_status_info: pointer to prot status info
  1311. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  1312. * @status_frag: qdf_frag_t buffer
  1313. *
  1314. * Return: status
  1315. */
  1316. static inline uint32_t
  1317. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  1318. void *prot_ppdu_info,
  1319. void *data_status_info,
  1320. void *prot_status_info,
  1321. void *tx_tlv_hdr,
  1322. qdf_frag_t status_frag)
  1323. {
  1324. struct hal_tx_ppdu_info *ppdu_info;
  1325. struct hal_tx_status_info *tx_status_info;
  1326. struct hal_mon_packet_info *packet_info = NULL;
  1327. uint32_t tlv_tag, user_id, tlv_len, tlv_user_id;
  1328. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1329. void *tx_tlv;
  1330. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  1331. tlv_user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr);
  1332. tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr);
  1333. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1334. /* parse tlv and populate tx_ppdu_info */
  1335. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  1336. prot_ppdu_info, tlv_tag);
  1337. tx_status_info = (ppdu_info->is_data ? data_status_info :
  1338. prot_status_info);
  1339. user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id);
  1340. switch (tlv_tag) {
  1341. /* start of initiator FES window */
  1342. case WIFITX_FES_SETUP_E:/* DOWNSTREAM - COMPACTION */
  1343. {
  1344. /* initiator PPDU window start */
  1345. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  1346. status = HAL_MON_TX_FES_SETUP;
  1347. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  1348. break;
  1349. }
  1350. /* end of initiator FES window */
  1351. case WIFITX_FES_STATUS_END_E:/* UPSTREAM - COMPACTION */
  1352. {
  1353. hal_txmon_parse_tx_fes_status_end(tx_tlv, ppdu_info,
  1354. tx_status_info);
  1355. status = HAL_MON_TX_FES_STATUS_END;
  1356. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  1357. break;
  1358. }
  1359. /* response window open */
  1360. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  1361. {
  1362. /* response PPDU window start */
  1363. uint32_t ppdu_id = 0;
  1364. uint8_t reception_type = 0;
  1365. uint8_t response_sta_count = 0;
  1366. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1367. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  1368. RX_RESPONSE_REQUIRED_INFO,
  1369. PHY_PPDU_ID);
  1370. reception_type =
  1371. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1372. SU_OR_UPLINK_MU_RECEPTION);
  1373. response_sta_count =
  1374. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1375. RESPONSE_STA_COUNT);
  1376. /* get mac address */
  1377. *(uint32_t *)&tx_status_info->addr1[0] =
  1378. HAL_TX_DESC_GET_64(tx_tlv,
  1379. RX_RESPONSE_REQUIRED_INFO,
  1380. ADDR1_31_0);
  1381. *(uint32_t *)&tx_status_info->addr1[4] =
  1382. HAL_TX_DESC_GET_64(tx_tlv,
  1383. RX_RESPONSE_REQUIRED_INFO,
  1384. ADDR1_47_32);
  1385. *(uint32_t *)&tx_status_info->addr2[0] =
  1386. HAL_TX_DESC_GET_64(tx_tlv,
  1387. RX_RESPONSE_REQUIRED_INFO,
  1388. ADDR2_15_0);
  1389. *(uint32_t *)&tx_status_info->addr2[2] =
  1390. HAL_TX_DESC_GET_64(tx_tlv,
  1391. RX_RESPONSE_REQUIRED_INFO,
  1392. ADDR2_47_16);
  1393. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  1394. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  1395. if (response_sta_count == 0)
  1396. response_sta_count = 1;
  1397. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  1398. if (reception_type)
  1399. TXMON_STATUS_INFO(tx_status_info,
  1400. transmission_type) =
  1401. TXMON_SU_TRANSMISSION;
  1402. else
  1403. TXMON_STATUS_INFO(tx_status_info,
  1404. transmission_type) =
  1405. TXMON_MU_TRANSMISSION;
  1406. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  1407. break;
  1408. }
  1409. /* Response window close */
  1410. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM - COMPACTION */
  1411. {
  1412. /* response PPDU window end */
  1413. hal_txmon_parse_response_end_status(tx_tlv, ppdu_info,
  1414. tx_status_info);
  1415. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  1416. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  1417. break;
  1418. }
  1419. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1420. {
  1421. SHOW_DEFINED(WIFITX_FLUSH_E);
  1422. break;
  1423. }
  1424. /* Downstream tlv */
  1425. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM - COMPACTION */
  1426. {
  1427. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  1428. prot_status_info);
  1429. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  1430. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  1431. break;
  1432. }
  1433. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM - COMPACTION */
  1434. {
  1435. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  1436. ppdu_info, tx_status_info);
  1437. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  1438. break;
  1439. }
  1440. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM - COMPACTION */
  1441. {
  1442. status = HAL_MON_TX_QUEUE_EXTENSION;
  1443. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  1444. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  1445. break;
  1446. }
  1447. /* payload and data frame handling */
  1448. case WIFITX_MPDU_START_E:/* DOWNSTREAM - COMPACTION */
  1449. {
  1450. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  1451. status = HAL_MON_TX_MPDU_START;
  1452. SHOW_DEFINED(WIFITX_MPDU_START_E);
  1453. break;
  1454. }
  1455. case WIFITX_MSDU_START_E:/* DOWNSTREAM - COMPACTION */
  1456. {
  1457. hal_txmon_parse_msdu_start(tx_tlv, user_id, ppdu_info);
  1458. /* we expect frame to be 802.11 frame type */
  1459. status = HAL_MON_TX_MSDU_START;
  1460. SHOW_DEFINED(WIFITX_MSDU_START_E);
  1461. break;
  1462. }
  1463. case WIFITX_DATA_E:/* DOWNSTREAM */
  1464. {
  1465. status = HAL_MON_TX_DATA;
  1466. /*
  1467. * TODO: do we need a conversion api to convert
  1468. * user_id from hw to get host user_index
  1469. */
  1470. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1471. TXMON_STATUS_INFO(tx_status_info,
  1472. buffer) = (void *)status_frag;
  1473. TXMON_STATUS_INFO(tx_status_info,
  1474. offset) = ((void *)tx_tlv -
  1475. (void *)status_frag);
  1476. TXMON_STATUS_INFO(tx_status_info,
  1477. length) = tlv_len;
  1478. /*
  1479. * reference of the status buffer will be held in
  1480. * dp_tx_update_ppdu_info_status()
  1481. */
  1482. status = HAL_MON_TX_DATA;
  1483. SHOW_DEFINED(WIFITX_DATA_E);
  1484. break;
  1485. }
  1486. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1487. {
  1488. packet_info = &ppdu_info->packet_info;
  1489. status = HAL_MON_TX_BUFFER_ADDR;
  1490. /*
  1491. * TODO: do we need a conversion api to convert
  1492. * user_id from hw to get host user_index
  1493. */
  1494. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1495. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  1496. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  1497. break;
  1498. }
  1499. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1500. {
  1501. /* no tlv content */
  1502. SHOW_DEFINED(WIFITX_MPDU_END_E);
  1503. break;
  1504. }
  1505. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1506. {
  1507. /* no tlv content */
  1508. SHOW_DEFINED(WIFITX_MSDU_END_E);
  1509. break;
  1510. }
  1511. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1512. {
  1513. /* no tlv content */
  1514. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  1515. break;
  1516. }
  1517. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1518. {
  1519. /* no tlv content */
  1520. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  1521. break;
  1522. }
  1523. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1524. {
  1525. /*
  1526. * transmitting power
  1527. * minimum transmitting power
  1528. * desired nss
  1529. * tx chain mask
  1530. * desired bw
  1531. * duration of transmit and response
  1532. *
  1533. * since most of the field we are deriving from other tlv
  1534. * we don't need to enable this in our tlv.
  1535. */
  1536. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  1537. break;
  1538. }
  1539. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1540. {
  1541. /* user tlv */
  1542. /*
  1543. * All Tx monitor will have 802.11 hdr
  1544. * we don't need to enable this TLV
  1545. */
  1546. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  1547. break;
  1548. }
  1549. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1550. {
  1551. /*
  1552. * no tlv content
  1553. *
  1554. * TLV that indicates to TXPCU that preamble phase for the NDP
  1555. * frame transmission is now over
  1556. */
  1557. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  1558. break;
  1559. }
  1560. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1561. {
  1562. /*
  1563. * no tlv content
  1564. *
  1565. * TLV indicates to the SCH that all timing critical TLV
  1566. * has been passed on to the transmit path
  1567. */
  1568. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  1569. break;
  1570. }
  1571. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1572. {
  1573. /*
  1574. * Loopback specific setup info - not needed for Tx monitor
  1575. */
  1576. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  1577. break;
  1578. }
  1579. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1580. {
  1581. /*
  1582. * no tlv content
  1583. *
  1584. * TLV indicates that other modules besides the scheduler can
  1585. * now also start generating TLV's
  1586. * prevent colliding or generating TLV's out of order
  1587. */
  1588. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1589. break;
  1590. }
  1591. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1592. {
  1593. /*
  1594. * no tlv content
  1595. *
  1596. * TLV indicates to SCH that a burst of MPDU info will
  1597. * start to come in over the TLV
  1598. */
  1599. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1600. break;
  1601. }
  1602. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1603. {
  1604. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1605. break;
  1606. }
  1607. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1608. {
  1609. /*
  1610. * no tlv content
  1611. *
  1612. * TLV indicates END of all TLV's within the scheduler TLV
  1613. */
  1614. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1615. break;
  1616. }
  1617. /* Upstream tlv */
  1618. case WIFIPDG_TX_REQ_E:
  1619. {
  1620. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1621. break;
  1622. }
  1623. case WIFITX_FES_STATUS_START_E:
  1624. {
  1625. /*
  1626. * TLV indicating that first transmission on the medium
  1627. */
  1628. uint8_t medium_prot_type = 0;
  1629. status = HAL_MON_TX_FES_STATUS_START;
  1630. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1631. TX_FES_STATUS_START,
  1632. MEDIUM_PROT_TYPE);
  1633. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1634. /* update what type of medium protection frame */
  1635. TXMON_STATUS_INFO(tx_status_info,
  1636. medium_prot_type) = medium_prot_type;
  1637. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1638. break;
  1639. }
  1640. case WIFITX_FES_STATUS_PROT_E:/* UPSTREAM - COMPACTION */
  1641. {
  1642. hal_txmon_parse_tx_fes_status_prot(tx_tlv, ppdu_info,
  1643. tx_status_info);
  1644. status = HAL_MON_TX_FES_STATUS_PROT;
  1645. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1646. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1647. break;
  1648. }
  1649. case WIFITX_FES_STATUS_START_PROT_E:
  1650. {
  1651. uint64_t tsft_64;
  1652. uint32_t response_type;
  1653. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1654. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1655. /* timestamp */
  1656. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1657. TX_FES_STATUS_START_PROT,
  1658. PROT_TIMESTAMP_LOWER_32);
  1659. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1660. TX_FES_STATUS_START_PROT,
  1661. PROT_TIMESTAMP_UPPER_32) << 32);
  1662. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1663. TX_FES_STATUS_START_PROT,
  1664. RESPONSE_TYPE);
  1665. TXMON_STATUS_INFO(tx_status_info,
  1666. response_type) = response_type;
  1667. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1668. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1669. break;
  1670. }
  1671. case WIFIPROT_TX_END_E:
  1672. {
  1673. /*
  1674. * no tlv content
  1675. *
  1676. * generated by TXPCU the moment that protection frame
  1677. * transmission has finished on the medium
  1678. */
  1679. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1680. break;
  1681. }
  1682. case WIFITX_FES_STATUS_START_PPDU_E:
  1683. {
  1684. uint64_t tsft_64;
  1685. uint8_t ndp_frame;
  1686. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1687. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1688. TX_FES_STATUS_START_PPDU,
  1689. PPDU_TIMESTAMP_LOWER_32);
  1690. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1691. TX_FES_STATUS_START_PPDU,
  1692. PPDU_TIMESTAMP_UPPER_32) << 32);
  1693. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1694. TX_FES_STATUS_START_PPDU,
  1695. NDP_FRAME);
  1696. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1697. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1698. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1699. break;
  1700. }
  1701. case WIFITX_FES_STATUS_USER_PPDU_E:
  1702. {
  1703. /* user tlv */
  1704. uint16_t duration;
  1705. uint8_t transmitted_tid;
  1706. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1707. TX_FES_STATUS_USER_PPDU,
  1708. DURATION);
  1709. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1710. TX_FES_STATUS_USER_PPDU,
  1711. TRANSMITTED_TID);
  1712. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1713. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1714. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1715. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1716. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1717. break;
  1718. }
  1719. case WIFIPPDU_TX_END_E:
  1720. {
  1721. /*
  1722. * no tlv content
  1723. *
  1724. * generated by TXPCU the moment that PPDU transmission has
  1725. * finished on the medium
  1726. */
  1727. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1728. break;
  1729. }
  1730. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1731. {
  1732. /*
  1733. * TLV contains the FES transmit result of the each
  1734. * of the MAC users. TLV are forwarded to HWSCH
  1735. */
  1736. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1737. break;
  1738. }
  1739. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1740. {
  1741. /* user tlv */
  1742. /*
  1743. * TLV generated by RXPCU and provide information related to
  1744. * the received BA or ACK frame
  1745. */
  1746. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1747. break;
  1748. }
  1749. case WIFITX_FES_STATUS_1K_BA_E:
  1750. {
  1751. /* user tlv */
  1752. /*
  1753. * TLV generated by RXPCU and providing information related
  1754. * to the received BA frame in case of 512/1024 bitmaps
  1755. */
  1756. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1757. break;
  1758. }
  1759. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1760. {
  1761. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1762. break;
  1763. }
  1764. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1765. {
  1766. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1767. break;
  1768. }
  1769. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1770. {
  1771. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1772. break;
  1773. }
  1774. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1775. {
  1776. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1777. break;
  1778. }
  1779. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1780. {
  1781. /*
  1782. * RXPCU generates this TLV when it receives a response frame
  1783. * that TXPCU pre-announced it was waiting for and in
  1784. * RXPCU_SETUP TLV, TLV generated before the
  1785. * RECEIVED_RESPONSE_INFO TLV.
  1786. *
  1787. * received info user fields are there which is not needed
  1788. * for TX monitor
  1789. */
  1790. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1791. break;
  1792. }
  1793. case WIFITXPCU_BUFFER_STATUS_E:
  1794. {
  1795. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1796. break;
  1797. }
  1798. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1799. {
  1800. /*
  1801. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1802. * for TX monitor we aren't interested in this tlv
  1803. */
  1804. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1805. break;
  1806. }
  1807. case WIFITXDMA_STOP_REQUEST_E:
  1808. {
  1809. /*
  1810. * no tlv content
  1811. *
  1812. * TLV is destined to TXDMA and informs TXDMA to stop
  1813. * pushing data into the transmit path.
  1814. */
  1815. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1816. break;
  1817. }
  1818. case WIFITX_CBF_INFO_E:
  1819. {
  1820. /*
  1821. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1822. * TXPCU to respond the CBF frame
  1823. *
  1824. * compressed beamforming pkt doesn't has mac header
  1825. * Tx monitor not interested in this pkt.
  1826. */
  1827. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1828. break;
  1829. }
  1830. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1831. {
  1832. /*
  1833. * no tlv content
  1834. *
  1835. * TLV indicates that TXPCU has finished generating the
  1836. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1837. */
  1838. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1839. break;
  1840. }
  1841. case WIFIPDG_RESPONSE_E:
  1842. {
  1843. /*
  1844. * most of the feilds are already covered in
  1845. * other TLV
  1846. * This is generated by TX_PCU to PDG to calculate
  1847. * all the PHY header info.
  1848. *
  1849. * some useful fields like min transmit power,
  1850. * rate used for transmitting packet is present.
  1851. */
  1852. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1853. break;
  1854. }
  1855. case WIFIPDG_TRIG_RESPONSE_E:
  1856. {
  1857. /* no tlv content */
  1858. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1859. break;
  1860. }
  1861. case WIFIRECEIVED_TRIGGER_INFO_E:
  1862. {
  1863. /*
  1864. * TLV generated by RXPCU to inform the scheduler that
  1865. * a trigger frame has been received
  1866. */
  1867. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1868. break;
  1869. }
  1870. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1871. {
  1872. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1873. break;
  1874. }
  1875. case WIFIRX_FRAME_BITMAP_ACK_E:
  1876. {
  1877. /* user tlv */
  1878. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1879. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1880. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1881. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1882. HAL_TX_DESC_GET_64(tx_tlv,
  1883. RX_FRAME_BITMAP_ACK,
  1884. NO_BITMAP_AVAILABLE);
  1885. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1886. HAL_TX_DESC_GET_64(tx_tlv,
  1887. RX_FRAME_BITMAP_ACK,
  1888. EXPLICIT_ACK);
  1889. /*
  1890. * get mac address, since address is received frame
  1891. * change the order and store it
  1892. */
  1893. *(uint32_t *)&tx_status_info->addr2[0] =
  1894. HAL_TX_DESC_GET_64(tx_tlv,
  1895. RX_FRAME_BITMAP_ACK,
  1896. ADDR1_31_0);
  1897. *(uint32_t *)&tx_status_info->addr2[4] =
  1898. HAL_TX_DESC_GET_64(tx_tlv,
  1899. RX_FRAME_BITMAP_ACK,
  1900. ADDR1_47_32);
  1901. *(uint32_t *)&tx_status_info->addr1[0] =
  1902. HAL_TX_DESC_GET_64(tx_tlv,
  1903. RX_FRAME_BITMAP_ACK,
  1904. ADDR2_15_0);
  1905. *(uint32_t *)&tx_status_info->addr1[2] =
  1906. HAL_TX_DESC_GET_64(tx_tlv,
  1907. RX_FRAME_BITMAP_ACK,
  1908. ADDR2_47_16);
  1909. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  1910. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  1911. EXPLICT_ACK_TYPE);
  1912. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1913. HAL_TX_DESC_GET_64(tx_tlv,
  1914. RX_FRAME_BITMAP_ACK,
  1915. BA_TID);
  1916. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1917. HAL_TX_DESC_GET_64(tx_tlv,
  1918. RX_FRAME_BITMAP_ACK,
  1919. STA_FULL_AID);
  1920. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1921. HAL_TX_DESC_GET_64(tx_tlv,
  1922. RX_FRAME_BITMAP_ACK,
  1923. BA_TS_SEQ);
  1924. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1925. HAL_TX_DESC_GET_64(tx_tlv,
  1926. RX_FRAME_BITMAP_ACK,
  1927. BA_TS_CTRL);
  1928. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1929. HAL_TX_DESC_GET_64(tx_tlv,
  1930. RX_FRAME_BITMAP_ACK,
  1931. BA_BITMAP_SIZE);
  1932. /* ba bitmap */
  1933. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1934. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1935. RX_FRAME_BITMAP_ACK,
  1936. BA_TS_BITMAP_31_0, 0), 32);
  1937. break;
  1938. }
  1939. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  1940. {
  1941. /* user tlv */
  1942. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  1943. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  1944. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1945. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1946. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  1947. BA_BITMAP_SIZE));
  1948. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1949. HAL_TX_DESC_GET_64(tx_tlv,
  1950. RX_FRAME_1K_BITMAP_ACK,
  1951. BA_TID);
  1952. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1953. HAL_TX_DESC_GET_64(tx_tlv,
  1954. RX_FRAME_1K_BITMAP_ACK,
  1955. STA_FULL_AID);
  1956. /* get mac address */
  1957. *(uint32_t *)&tx_status_info->addr1[0] =
  1958. HAL_TX_DESC_GET_64(tx_tlv,
  1959. RX_FRAME_1K_BITMAP_ACK,
  1960. ADDR1_31_0);
  1961. *(uint32_t *)&tx_status_info->addr1[4] =
  1962. HAL_TX_DESC_GET_64(tx_tlv,
  1963. RX_FRAME_1K_BITMAP_ACK,
  1964. ADDR1_47_32);
  1965. *(uint32_t *)&tx_status_info->addr2[0] =
  1966. HAL_TX_DESC_GET_64(tx_tlv,
  1967. RX_FRAME_1K_BITMAP_ACK,
  1968. ADDR2_15_0);
  1969. *(uint32_t *)&tx_status_info->addr2[2] =
  1970. HAL_TX_DESC_GET_64(tx_tlv,
  1971. RX_FRAME_1K_BITMAP_ACK,
  1972. ADDR2_47_16);
  1973. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1974. HAL_TX_DESC_GET_64(tx_tlv,
  1975. RX_FRAME_1K_BITMAP_ACK,
  1976. BA_TS_SEQ);
  1977. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1978. HAL_TX_DESC_GET_64(tx_tlv,
  1979. RX_FRAME_1K_BITMAP_ACK,
  1980. BA_TS_CTRL);
  1981. /* memcpy ba bitmap */
  1982. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1983. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1984. RX_FRAME_1K_BITMAP_ACK,
  1985. BA_TS_BITMAP_31_0, 0),
  1986. 4 << TXMON_HAL_USER(ppdu_info,
  1987. user_id, ba_bitmap_sz));
  1988. break;
  1989. }
  1990. case WIFIRESPONSE_START_STATUS_E:
  1991. {
  1992. /*
  1993. * TLV indicates which HW response the TXPCU
  1994. * started generating
  1995. *
  1996. * HW generated frames like
  1997. * ACK frame - handled
  1998. * CTS frame - handled
  1999. * BA frame - handled
  2000. * MBA frame - handled
  2001. * CBF frame - no frame header
  2002. * Trigger response - TODO
  2003. * NDP LMR - no frame header
  2004. */
  2005. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  2006. break;
  2007. }
  2008. case WIFIRX_START_PARAM_E:
  2009. {
  2010. /*
  2011. * RXPCU send this TLV after PHY RX detected a frame
  2012. * in the medium
  2013. *
  2014. * TX monitor not interested in this TLV
  2015. */
  2016. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  2017. break;
  2018. }
  2019. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  2020. {
  2021. /*
  2022. * early indication of pkt type and mcs rate
  2023. * already captured in other tlv
  2024. */
  2025. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  2026. break;
  2027. }
  2028. case WIFIRX_PM_INFO_E:
  2029. {
  2030. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  2031. break;
  2032. }
  2033. /* Active window */
  2034. case WIFITX_FLUSH_REQ_E:
  2035. {
  2036. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  2037. break;
  2038. }
  2039. case WIFICOEX_TX_STATUS_E:
  2040. {
  2041. /* duration are retrieved from coex tx status */
  2042. uint16_t duration;
  2043. uint8_t status_reason;
  2044. status = HAL_MON_COEX_TX_STATUS;
  2045. duration = HAL_TX_DESC_GET_64(tx_tlv,
  2046. COEX_TX_STATUS,
  2047. CURRENT_TX_DURATION);
  2048. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  2049. COEX_TX_STATUS,
  2050. TX_STATUS_REASON);
  2051. /* update duration */
  2052. if (status_reason == COEX_FES_TX_START ||
  2053. status_reason == COEX_RESPONSE_TX_START)
  2054. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  2055. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  2056. break;
  2057. }
  2058. case WIFIR2R_STATUS_END_E:
  2059. {
  2060. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  2061. break;
  2062. }
  2063. case WIFIRX_PREAMBLE_E:
  2064. {
  2065. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  2066. break;
  2067. }
  2068. case WIFIMACTX_SERVICE_E:
  2069. {
  2070. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  2071. break;
  2072. }
  2073. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  2074. {
  2075. struct hal_mon_usig_hdr *usig = NULL;
  2076. struct hal_mon_usig_mu *usig_mu = NULL;
  2077. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2078. usig_mu = &usig->usig_2.mu;
  2079. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2080. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2081. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2082. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2083. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2084. QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN |
  2085. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN |
  2086. QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN |
  2087. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN |
  2088. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN |
  2089. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2090. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2091. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2092. (0x1F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2093. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2094. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT);
  2095. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2096. (usig_mu->ppdu_type_comp_mode <<
  2097. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2098. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2099. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2100. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2101. (usig_mu->punc_ch_info <<
  2102. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT);
  2103. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2104. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT);
  2105. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2106. (usig_mu->eht_sig_mcs <<
  2107. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT);
  2108. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2109. (usig_mu->num_eht_sig_sym <<
  2110. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT);
  2111. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2112. (usig_mu->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2113. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2114. (usig_mu->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2115. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  2116. break;
  2117. }
  2118. case WIFIMACTX_U_SIG_EHT_TB_E:
  2119. {
  2120. struct hal_mon_usig_hdr *usig = NULL;
  2121. struct hal_mon_usig_tb *usig_tb = NULL;
  2122. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2123. usig_tb = &usig->usig_2.tb;
  2124. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2125. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2126. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2127. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2128. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2129. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN |
  2130. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN |
  2131. QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN |
  2132. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2133. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2134. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2135. (0x3F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2136. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2137. (usig_tb->ppdu_type_comp_mode <<
  2138. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2139. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2140. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2141. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2142. (usig_tb->spatial_reuse_1 <<
  2143. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT);
  2144. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2145. (usig_tb->spatial_reuse_2 <<
  2146. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT);
  2147. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2148. (0x1F << QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT);
  2149. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2150. (usig_tb->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2151. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2152. (usig_tb->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2153. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  2154. break;
  2155. }
  2156. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  2157. {
  2158. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2159. ppdu_info);
  2160. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2161. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  2162. break;
  2163. }
  2164. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  2165. {
  2166. hal_txmon_parse_eht_sig_mumimo_user_info(tx_tlv, user_id,
  2167. ppdu_info);
  2168. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2169. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  2170. break;
  2171. }
  2172. case WIFIMACTX_EHT_SIG_USR_SU_E:
  2173. {
  2174. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2175. ppdu_info);
  2176. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2177. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  2178. /* TODO: no radiotap info available */
  2179. break;
  2180. }
  2181. case WIFIMACTX_HE_SIG_A_SU_E:
  2182. {
  2183. uint16_t he_mu_flag_1 = 0;
  2184. uint16_t he_mu_flag_2 = 0;
  2185. uint16_t num_users = 0;
  2186. uint8_t mcs_of_sig_b = 0;
  2187. uint8_t dcm_of_sig_b = 0;
  2188. uint8_t sig_a_bw = 0;
  2189. uint8_t i = 0;
  2190. uint8_t bss_color_id;
  2191. uint8_t coding;
  2192. uint8_t stbc;
  2193. uint8_t a_factor;
  2194. uint8_t pe_disambiguity;
  2195. uint8_t txbf;
  2196. uint8_t txbw;
  2197. uint8_t txop;
  2198. status = HAL_MON_MACTX_HE_SIG_A_SU;
  2199. num_users = TXMON_HAL(ppdu_info, num_users);
  2200. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2201. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2202. TRANSMIT_MCS);
  2203. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2204. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2205. DCM);
  2206. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2207. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2208. TRANSMIT_BW);
  2209. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2210. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2211. BSS_COLOR_ID);
  2212. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2213. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2214. CODING);
  2215. stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2216. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2217. STBC);
  2218. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  2219. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2220. PACKET_EXTENSION_A_FACTOR);
  2221. pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv,
  2222. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2223. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2224. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2225. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2226. TXBF);
  2227. txbw = HAL_TX_DESC_GET_64(tx_tlv,
  2228. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2229. TRANSMIT_BW);
  2230. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2231. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2232. TXOP_DURATION);
  2233. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2234. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2235. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2236. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2237. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2238. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  2239. /* MCS */
  2240. he_mu_flag_1 |= mcs_of_sig_b <<
  2241. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2242. /* DCM */
  2243. he_mu_flag_1 |= dcm_of_sig_b <<
  2244. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2245. /* bandwidth */
  2246. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2247. he_mu_flag_2 |= sig_a_bw <<
  2248. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2249. TXMON_HAL_STATUS(ppdu_info,
  2250. he_mu_flags) = IS_MULTI_USERS(num_users);
  2251. for (i = 0; i < num_users; i++) {
  2252. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2253. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2254. }
  2255. /* HE data 1 */
  2256. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2257. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2258. QDF_MON_STATUS_HE_CODING_KNOWN;
  2259. /* HE data 2 */
  2260. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2261. QDF_MON_STATUS_TXBF_KNOWN |
  2262. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2263. QDF_MON_STATUS_TXOP_KNOWN |
  2264. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2265. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2266. /* HE data 3 */
  2267. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2268. bss_color_id |
  2269. (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) |
  2270. (coding << QDF_MON_STATUS_CODING_SHIFT) |
  2271. (stbc << QDF_MON_STATUS_STBC_SHIFT);
  2272. /* HE data 6 */
  2273. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2274. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2275. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  2276. break;
  2277. }
  2278. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  2279. {
  2280. uint16_t he_mu_flag_1 = 0;
  2281. uint16_t he_mu_flag_2 = 0;
  2282. uint16_t num_users = 0;
  2283. uint8_t bss_color_id;
  2284. uint8_t txop;
  2285. uint8_t mcs_of_sig_b = 0;
  2286. uint8_t dcm_of_sig_b = 0;
  2287. uint8_t sig_a_bw = 0;
  2288. uint8_t num_sig_b_symb = 0;
  2289. uint8_t comp_mode_sig_b = 0;
  2290. uint8_t punc_bw = 0;
  2291. uint8_t i = 0;
  2292. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  2293. num_users = TXMON_HAL(ppdu_info, num_users);
  2294. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2295. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2296. MCS_OF_SIG_B);
  2297. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2298. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2299. DCM_OF_SIG_B);
  2300. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2301. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2302. TRANSMIT_BW);
  2303. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  2304. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2305. NUM_SIG_B_SYMBOLS);
  2306. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2307. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2308. COMP_MODE_SIG_B);
  2309. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2310. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2311. BSS_COLOR_ID);
  2312. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2313. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2314. TXOP_DURATION);
  2315. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2316. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2317. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  2318. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2319. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2320. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2321. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  2322. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  2323. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  2324. /* MCS */
  2325. he_mu_flag_1 |= mcs_of_sig_b <<
  2326. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2327. /* DCM */
  2328. he_mu_flag_1 |= dcm_of_sig_b <<
  2329. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2330. /* Compression */
  2331. he_mu_flag_2 |= comp_mode_sig_b <<
  2332. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2333. /* bandwidth */
  2334. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2335. he_mu_flag_2 |= sig_a_bw <<
  2336. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2337. he_mu_flag_2 |= comp_mode_sig_b <<
  2338. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2339. /* number of symbol */
  2340. he_mu_flag_2 |= num_sig_b_symb <<
  2341. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  2342. /* puncture bw */
  2343. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  2344. punc_bw = sig_a_bw;
  2345. he_mu_flag_2 |=
  2346. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  2347. /* copy per user info to all user */
  2348. TXMON_HAL_STATUS(ppdu_info,
  2349. he_mu_flags) = IS_MULTI_USERS(num_users);
  2350. for (i = 0; i < num_users; i++) {
  2351. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2352. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2353. }
  2354. /* HE data 1 */
  2355. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2356. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN;
  2357. /* HE data 2 */
  2358. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2359. QDF_MON_STATUS_TXOP_KNOWN;
  2360. /* HE data 3 */
  2361. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id;
  2362. /* HE data 6 */
  2363. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2364. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2365. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  2366. break;
  2367. }
  2368. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  2369. {
  2370. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  2371. break;
  2372. }
  2373. case WIFIMACTX_HE_SIG_B1_MU_E:
  2374. {
  2375. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  2376. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  2377. break;
  2378. }
  2379. case WIFIMACTX_HE_SIG_B2_MU_E:
  2380. {
  2381. /* user tlv */
  2382. uint16_t sta_id = 0;
  2383. uint16_t sta_spatial_config = 0;
  2384. uint8_t sta_mcs = 0;
  2385. uint8_t coding = 0;
  2386. uint8_t nss = 0;
  2387. uint8_t user_order = 0;
  2388. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  2389. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2390. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2391. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2392. STA_ID);
  2393. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  2394. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2395. STA_SPATIAL_CONFIG);
  2396. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2397. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2398. STA_MCS);
  2399. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2400. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2401. STA_CODING);
  2402. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2403. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2404. NSTS) + 1;
  2405. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2406. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2407. USER_ORDER);
  2408. /* HE data 1 */
  2409. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2410. QDF_MON_STATUS_HE_MCS_KNOWN |
  2411. QDF_MON_STATUS_HE_CODING_KNOWN;
  2412. /* HE data 2 */
  2413. /* HE data 3 */
  2414. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2415. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2416. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2417. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2418. coding << QDF_MON_STATUS_CODING_SHIFT;
  2419. /* HE data 4 */
  2420. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2421. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2422. /* HE data 5 */
  2423. /* HE data 6 */
  2424. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2425. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2426. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  2427. break;
  2428. }
  2429. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  2430. {
  2431. /* user tlv */
  2432. uint8_t *he_sig_b2_ofdma_info = NULL;
  2433. uint16_t sta_id = 0;
  2434. uint8_t nss = 0;
  2435. uint8_t txbf = 0;
  2436. uint8_t sta_mcs = 0;
  2437. uint8_t sta_dcm = 0;
  2438. uint8_t coding = 0;
  2439. uint8_t user_order = 0;
  2440. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  2441. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2442. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  2443. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2444. STA_ID);
  2445. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2446. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2447. STA_ID);
  2448. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2449. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2450. NSTS);
  2451. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2452. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2453. TXBF);
  2454. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2455. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2456. STA_MCS);
  2457. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  2458. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2459. STA_DCM);
  2460. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2461. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2462. STA_CODING);
  2463. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2464. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2465. USER_ORDER);
  2466. /* HE data 1 */
  2467. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2468. QDF_MON_STATUS_HE_MCS_KNOWN |
  2469. QDF_MON_STATUS_HE_CODING_KNOWN |
  2470. QDF_MON_STATUS_HE_DCM_KNOWN;
  2471. /* HE data 2 */
  2472. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2473. QDF_MON_STATUS_TXBF_KNOWN;
  2474. /* HE data 3 */
  2475. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2476. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2477. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2478. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2479. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  2480. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2481. coding << QDF_MON_STATUS_CODING_SHIFT;
  2482. /* HE data 4 */
  2483. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2484. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2485. /* HE data 5 */
  2486. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  2487. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  2488. /* HE data 6 */
  2489. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2490. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2491. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  2492. break;
  2493. }
  2494. case WIFIMACTX_L_SIG_A_E:
  2495. {
  2496. uint8_t *l_sig_a_info = NULL;
  2497. uint8_t rate = 0;
  2498. status = HAL_MON_MACTX_L_SIG_A;
  2499. l_sig_a_info = (uint8_t *)tx_tlv +
  2500. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2501. RATE);
  2502. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2503. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2504. RATE);
  2505. switch (rate) {
  2506. case 8:
  2507. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  2508. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2509. break;
  2510. case 9:
  2511. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  2512. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2513. break;
  2514. case 10:
  2515. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  2516. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2517. break;
  2518. case 11:
  2519. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  2520. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2521. break;
  2522. case 12:
  2523. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  2524. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2525. break;
  2526. case 13:
  2527. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  2528. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2529. break;
  2530. case 14:
  2531. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  2532. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2533. break;
  2534. case 15:
  2535. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  2536. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  2537. break;
  2538. default:
  2539. break;
  2540. }
  2541. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  2542. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2543. TXMON_HAL_STATUS(ppdu_info,
  2544. l_sig_a_info) = *((uint32_t *)l_sig_a_info);
  2545. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  2546. break;
  2547. }
  2548. case WIFIMACTX_L_SIG_B_E:
  2549. {
  2550. uint8_t *l_sig_b_info = NULL;
  2551. uint8_t rate = 0;
  2552. status = HAL_MON_MACTX_L_SIG_B;
  2553. l_sig_b_info = (uint8_t *)tx_tlv +
  2554. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2555. RATE);
  2556. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2557. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2558. RATE);
  2559. switch (rate) {
  2560. case 1:
  2561. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  2562. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2563. break;
  2564. case 2:
  2565. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  2566. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2567. break;
  2568. case 3:
  2569. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  2570. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2571. break;
  2572. case 4:
  2573. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  2574. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2575. break;
  2576. case 5:
  2577. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  2578. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2579. break;
  2580. case 6:
  2581. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  2582. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2583. break;
  2584. case 7:
  2585. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  2586. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2587. break;
  2588. default:
  2589. break;
  2590. }
  2591. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  2592. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2593. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  2594. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  2595. break;
  2596. }
  2597. case WIFIMACTX_HT_SIG_E:
  2598. {
  2599. uint8_t mcs = 0;
  2600. uint8_t bw = 0;
  2601. uint8_t is_stbc = 0;
  2602. uint8_t coding = 0;
  2603. uint8_t gi = 0;
  2604. status = HAL_MON_MACTX_HT_SIG;
  2605. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  2606. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  2607. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  2608. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  2609. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  2610. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2611. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2612. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  2613. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  2614. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  2615. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2616. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2617. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  2618. break;
  2619. }
  2620. case WIFIMACTX_VHT_SIG_A_E:
  2621. {
  2622. uint8_t bandwidth = 0;
  2623. uint8_t is_stbc = 0;
  2624. uint8_t group_id = 0;
  2625. uint32_t nss_comb = 0;
  2626. uint8_t nss_su = 0;
  2627. uint8_t nss_mu[4] = {0};
  2628. uint8_t sgi = 0;
  2629. uint8_t coding = 0;
  2630. uint8_t mcs = 0;
  2631. uint8_t beamformed = 0;
  2632. uint8_t partial_aid = 0;
  2633. status = HAL_MON_MACTX_VHT_SIG_A;
  2634. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  2635. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2636. BANDWIDTH);
  2637. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2638. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2639. STBC);
  2640. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  2641. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2642. GROUP_ID);
  2643. /* nss_comb is su nss, MU nss and partial AID */
  2644. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  2645. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2646. N_STS);
  2647. /* if it is SU */
  2648. nss_su = (nss_comb & 0x7) + 1;
  2649. /* partial aid - applicable only for SU */
  2650. partial_aid = (nss_comb >> 3) & 0x1F;
  2651. /* if it is MU */
  2652. nss_mu[0] = (nss_comb & 0x7) + 1;
  2653. nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1;
  2654. nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1;
  2655. nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1;
  2656. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  2657. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2658. GI_SETTING);
  2659. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2660. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2661. SU_MU_CODING);
  2662. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2663. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2664. MCS);
  2665. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  2666. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2667. BEAMFORMED);
  2668. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2669. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2670. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  2671. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  2672. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2673. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2674. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  2675. if (group_id == 0 || group_id == 63) {
  2676. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2677. HAL_RX_TYPE_SU;
  2678. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2679. TXMON_HAL_STATUS(ppdu_info, nss) =
  2680. nss_su & VHT_SIG_SU_NSS_MASK;
  2681. TXMON_HAL_USER(ppdu_info, user_id,
  2682. vht_flag_values3[0]) = ((mcs << 4) |
  2683. nss_su);
  2684. } else {
  2685. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2686. HAL_RX_TYPE_MU_MIMO;
  2687. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2688. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  2689. nss_su & VHT_SIG_SU_NSS_MASK;
  2690. TXMON_HAL_USER(ppdu_info, user_id,
  2691. vht_flag_values3[0]) = ((mcs << 4) |
  2692. nss_su);
  2693. TXMON_HAL_USER(ppdu_info, user_id,
  2694. vht_flag_values3[1]) = ((mcs << 4) |
  2695. nss_mu[1]);
  2696. TXMON_HAL_USER(ppdu_info, user_id,
  2697. vht_flag_values3[2]) = ((mcs << 4) |
  2698. nss_mu[2]);
  2699. TXMON_HAL_USER(ppdu_info, user_id,
  2700. vht_flag_values3[3]) = ((mcs << 4) |
  2701. nss_mu[3]);
  2702. }
  2703. /* TODO: loop over multiple user */
  2704. TXMON_HAL_USER(ppdu_info, user_id,
  2705. vht_flag_values2) = bandwidth;
  2706. TXMON_HAL_USER(ppdu_info, user_id,
  2707. vht_flag_values4) = coding;
  2708. TXMON_HAL_USER(ppdu_info, user_id,
  2709. vht_flag_values5) = group_id;
  2710. TXMON_HAL_USER(ppdu_info, user_id,
  2711. vht_flag_values6) = partial_aid;
  2712. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  2713. break;
  2714. }
  2715. case WIFIMACTX_VHT_SIG_B_MU160_E:
  2716. {
  2717. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  2718. break;
  2719. }
  2720. case WIFIMACTX_VHT_SIG_B_MU80_E:
  2721. {
  2722. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  2723. break;
  2724. }
  2725. case WIFIMACTX_VHT_SIG_B_MU40_E:
  2726. {
  2727. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  2728. break;
  2729. }
  2730. case WIFIMACTX_VHT_SIG_B_MU20_E:
  2731. {
  2732. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  2733. break;
  2734. }
  2735. case WIFIMACTX_VHT_SIG_B_SU160_E:
  2736. {
  2737. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  2738. break;
  2739. }
  2740. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2741. {
  2742. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2743. break;
  2744. }
  2745. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2746. {
  2747. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2748. break;
  2749. }
  2750. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2751. {
  2752. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2753. break;
  2754. }
  2755. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2756. {
  2757. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2758. break;
  2759. }
  2760. case WIFIMACTX_USER_DESC_PER_USER_E:
  2761. {
  2762. hal_txmon_parse_user_desc_per_user(tx_tlv, user_id, ppdu_info);
  2763. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2764. break;
  2765. }
  2766. case WIFIMACTX_USER_DESC_COMMON_E:
  2767. {
  2768. hal_txmon_parse_user_desc_common(tx_tlv, user_id, ppdu_info);
  2769. /* copy per user info to all user */
  2770. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2771. break;
  2772. }
  2773. case WIFIMACTX_PHY_DESC_E:
  2774. {
  2775. /* pkt_type - preamble type */
  2776. uint32_t pkt_type = 0;
  2777. uint8_t bandwidth = 0;
  2778. uint8_t is_stbc = 0;
  2779. uint8_t is_triggered = 0;
  2780. uint8_t gi = 0;
  2781. uint8_t he_ppdu_subtype = 0;
  2782. uint32_t ltf_size = 0;
  2783. uint32_t he_data1 = 0;
  2784. uint32_t he_data2 = 0;
  2785. uint32_t he_data3 = 0;
  2786. uint32_t he_data5 = 0;
  2787. uint16_t he_mu_flag_1 = 0;
  2788. uint16_t he_mu_flag_2 = 0;
  2789. uint16_t num_users = 0;
  2790. uint8_t i = 0;
  2791. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2792. status = HAL_MON_MACTX_PHY_DESC;
  2793. num_users = TXMON_HAL(ppdu_info, num_users);
  2794. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2795. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2796. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2797. TRIGGERED);
  2798. if (!is_triggered) {
  2799. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2800. BANDWIDTH);
  2801. } else {
  2802. /*
  2803. * is_triggered, bw is minimum of AP pkt bw
  2804. * or STA bw
  2805. */
  2806. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2807. AP_PKT_BW);
  2808. }
  2809. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2810. CP_SETTING);
  2811. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2812. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2813. HE_PPDU_SUBTYPE);
  2814. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2815. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2816. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2817. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2818. switch (ppdu_info->rx_status.preamble_type) {
  2819. case TXMON_PKT_TYPE_11N_MM:
  2820. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2821. TXMON_HAL_STATUS(ppdu_info,
  2822. rtap_flags) |= HT_SGI_PRESENT;
  2823. break;
  2824. case TXMON_PKT_TYPE_11AC:
  2825. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2826. break;
  2827. case TXMON_PKT_TYPE_11AX:
  2828. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2829. break;
  2830. default:
  2831. break;
  2832. }
  2833. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2834. break;
  2835. /* update he flags */
  2836. /* PPDU FORMAT */
  2837. switch (he_ppdu_subtype) {
  2838. case TXMON_HE_SUBTYPE_SU:
  2839. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2840. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2841. break;
  2842. case TXMON_HE_SUBTYPE_TRIG:
  2843. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2844. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2845. break;
  2846. case TXMON_HE_SUBTYPE_MU:
  2847. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2848. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2849. break;
  2850. case TXMON_HE_SUBTYPE_EXT_SU:
  2851. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2852. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2853. break;
  2854. };
  2855. /* STBC */
  2856. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2857. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2858. /* GI */
  2859. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2860. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2861. /* Data BW and RU allocation */
  2862. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2863. he_data5 = (he_data5 & 0xFFF0) | bandwidth;
  2864. he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2865. he_data5 |= ((1 + ltf_size) <<
  2866. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT);
  2867. TXMON_HAL_STATUS(ppdu_info,
  2868. he_mu_flags) = IS_MULTI_USERS(num_users);
  2869. /* MAC TX PHY DESC is not a user tlv */
  2870. for (i = 0; i < num_users; i++) {
  2871. TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1;
  2872. TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2;
  2873. TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3;
  2874. TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5;
  2875. /* HE MU flags */
  2876. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2877. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2878. }
  2879. break;
  2880. }
  2881. case WIFICOEX_RX_STATUS_E:
  2882. {
  2883. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2884. break;
  2885. }
  2886. case WIFIRX_PPDU_ACK_REPORT_E:
  2887. {
  2888. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2889. break;
  2890. }
  2891. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2892. {
  2893. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2894. break;
  2895. }
  2896. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2897. {
  2898. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2899. break;
  2900. }
  2901. case WIFITXPCU_PHYTX_DEBUG32_E:
  2902. {
  2903. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  2904. break;
  2905. }
  2906. case WIFITXPCU_PREAMBLE_DONE_E:
  2907. {
  2908. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  2909. break;
  2910. }
  2911. case WIFIRX_PHY_SLEEP_E:
  2912. {
  2913. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  2914. break;
  2915. }
  2916. case WIFIRX_FRAME_BITMAP_REQ_E:
  2917. {
  2918. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  2919. break;
  2920. }
  2921. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  2922. {
  2923. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  2924. break;
  2925. }
  2926. case WIFIRX_TRIG_INFO_E:
  2927. {
  2928. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  2929. break;
  2930. }
  2931. case WIFIEXPECTED_RESPONSE_E:
  2932. {
  2933. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  2934. break;
  2935. }
  2936. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  2937. {
  2938. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  2939. break;
  2940. }
  2941. case WIFIFW2SW_MON_E:
  2942. {
  2943. /* parse fw2sw tlv */
  2944. hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info);
  2945. status = HAL_MON_TX_FW2SW;
  2946. SHOW_DEFINED(WIFIFW2SW_MON_E);
  2947. break;
  2948. }
  2949. }
  2950. return status;
  2951. }
  2952. #endif /* QCA_MONITOR_2_0_SUPPORT */
  2953. #ifdef REO_SHARED_QREF_TABLE_EN
  2954. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  2955. {
  2956. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2957. uint32_t reg_val = 0;
  2958. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2959. * of 37 peer/tids
  2960. */
  2961. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  2962. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  2963. HAL_REG_WRITE(hal,
  2964. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2965. reg_val);
  2966. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2967. * of 37 peer/tids
  2968. */
  2969. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  2970. HAL_REG_WRITE(hal,
  2971. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2972. reg_val);
  2973. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  2974. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  2975. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  2976. }
  2977. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  2978. * LUT shared by SW and HW at the index given by peer id
  2979. * and tid.
  2980. *
  2981. * @hal_soc: hal soc pointer
  2982. * @reo_qref_addr: pointer to index pointed to be peer_id
  2983. * and tid
  2984. * @tid: tid queue number
  2985. * @hw_qdesc_paddr: reo queue addr
  2986. */
  2987. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  2988. uint16_t peer_id,
  2989. int tid,
  2990. qdf_dma_addr_t hw_qdesc_paddr)
  2991. {
  2992. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2993. struct rx_reo_queue_reference *reo_qref;
  2994. uint32_t peer_tid_idx;
  2995. /* Plug hw_desc_addr in Host reo queue reference table */
  2996. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  2997. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  2998. DP_MAX_TIDS) + tid;
  2999. reo_qref = (struct rx_reo_queue_reference *)
  3000. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  3001. } else {
  3002. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  3003. reo_qref = (struct rx_reo_queue_reference *)
  3004. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  3005. }
  3006. reo_qref->rx_reo_queue_desc_addr_31_0 =
  3007. hw_qdesc_paddr & 0xffffffff;
  3008. reo_qref->rx_reo_queue_desc_addr_39_32 =
  3009. (hw_qdesc_paddr & 0xff00000000) >> 32;
  3010. if (hw_qdesc_paddr != 0)
  3011. reo_qref->receive_queue_number = tid;
  3012. else
  3013. reo_qref->receive_queue_number = 0;
  3014. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  3015. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  3016. "rx_reo_queue_desc_addr_31_0: %x,"
  3017. "rx_reo_queue_desc_addr_39_32: %x",
  3018. (void *)hw_qdesc_paddr, tid, reo_qref,
  3019. reo_qref->rx_reo_queue_desc_addr_31_0,
  3020. reo_qref->rx_reo_queue_desc_addr_39_32);
  3021. }
  3022. #ifdef BIG_ENDIAN_HOST
  3023. static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
  3024. {
  3025. HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3026. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, GXI_SWAP, 1) |
  3027. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
  3028. }
  3029. #else
  3030. static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
  3031. {
  3032. HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3033. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
  3034. }
  3035. #endif
  3036. /**
  3037. * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue
  3038. * reference table shared between SW and HW and initialize in Qdesc Base0
  3039. * base1 registers provided by HW.
  3040. *
  3041. * @hal_soc_hdl: HAL Soc handle
  3042. * @reo_qref: REO queue reference table
  3043. *
  3044. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  3045. */
  3046. static QDF_STATUS
  3047. hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl,
  3048. struct reo_queue_ref_table *reo_qref)
  3049. {
  3050. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3051. reo_qref->reo_qref_table_en = 1;
  3052. reo_qref->mlo_reo_qref_table_vaddr =
  3053. (uint64_t *)qdf_mem_alloc_consistent(
  3054. hal->qdf_dev, hal->qdf_dev->dev,
  3055. REO_QUEUE_REF_ML_TABLE_SIZE,
  3056. &reo_qref->mlo_reo_qref_table_paddr);
  3057. if (!reo_qref->mlo_reo_qref_table_vaddr)
  3058. return QDF_STATUS_E_NOMEM;
  3059. reo_qref->non_mlo_reo_qref_table_vaddr =
  3060. (uint64_t *)qdf_mem_alloc_consistent(
  3061. hal->qdf_dev, hal->qdf_dev->dev,
  3062. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  3063. &reo_qref->non_mlo_reo_qref_table_paddr);
  3064. if (!reo_qref->non_mlo_reo_qref_table_vaddr) {
  3065. qdf_mem_free_consistent(
  3066. hal->qdf_dev, hal->qdf_dev->dev,
  3067. REO_QUEUE_REF_ML_TABLE_SIZE,
  3068. reo_qref->mlo_reo_qref_table_vaddr,
  3069. reo_qref->mlo_reo_qref_table_paddr,
  3070. 0);
  3071. reo_qref->mlo_reo_qref_table_vaddr = NULL;
  3072. return QDF_STATUS_E_NOMEM;
  3073. }
  3074. hal_verbose_debug("MLO table start paddr:%pK,"
  3075. "Non-MLO table start paddr:%pK,"
  3076. "MLO table start vaddr: %pK,"
  3077. "Non MLO table start vaddr: %pK",
  3078. (void *)reo_qref->mlo_reo_qref_table_paddr,
  3079. (void *)reo_qref->non_mlo_reo_qref_table_paddr,
  3080. reo_qref->mlo_reo_qref_table_vaddr,
  3081. reo_qref->non_mlo_reo_qref_table_vaddr);
  3082. return QDF_STATUS_SUCCESS;
  3083. }
  3084. /**
  3085. * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and
  3086. * write start addr of MLO and Non MLO table in HW
  3087. *
  3088. * @hal_soc_hdl: HAL Soc handle
  3089. * @qref_reset: reset qref LUT
  3090. *
  3091. * Return: None
  3092. */
  3093. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
  3094. int qref_reset)
  3095. {
  3096. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3097. if (qref_reset) {
  3098. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  3099. REO_QUEUE_REF_ML_TABLE_SIZE);
  3100. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  3101. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  3102. }
  3103. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  3104. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  3105. * upper 32bits only
  3106. */
  3107. HAL_REG_WRITE(hal,
  3108. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3109. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  3110. HAL_REG_WRITE(hal,
  3111. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3112. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  3113. hal_reo_shared_qaddr_enable(hal);
  3114. HAL_REG_WRITE(hal,
  3115. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  3116. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  3117. 0x1fff));
  3118. }
  3119. /**
  3120. * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue
  3121. * reference table shared between SW and HW
  3122. *
  3123. * @hal_soc_hdl: HAL Soc handle
  3124. *
  3125. * Return: None
  3126. */
  3127. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  3128. {
  3129. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3130. HAL_REG_WRITE(hal,
  3131. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3132. 0);
  3133. HAL_REG_WRITE(hal,
  3134. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3135. 0);
  3136. }
  3137. #endif
  3138. /**
  3139. * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing
  3140. * @hal_soc_hdl: HAL SoC context
  3141. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  3142. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  3143. *
  3144. * Return: void
  3145. */
  3146. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  3147. static inline void
  3148. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3149. enum hal_tx_vdev_mismatch_notify
  3150. config)
  3151. {
  3152. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3153. uint32_t reg_addr, reg_val = 0;
  3154. uint32_t val = 0;
  3155. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3156. val = HAL_REG_READ(hal_soc, reg_addr);
  3157. /* reset the corresponding bits in register */
  3158. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  3159. /* set config value */
  3160. reg_val = val | (config <<
  3161. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  3162. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3163. }
  3164. #else
  3165. static inline void
  3166. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3167. enum hal_tx_vdev_mismatch_notify
  3168. config)
  3169. {
  3170. }
  3171. #endif
  3172. /**
  3173. * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing
  3174. * @hal_soc_hdl: HAL SoC context
  3175. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  3176. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  3177. *
  3178. * Return: void
  3179. */
  3180. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  3181. defined(WLAN_MCAST_MLO)
  3182. static inline void
  3183. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3184. hal_soc_handle_t hal_soc_hdl,
  3185. enum hal_tx_mcast_mlo_reinject_notify config)
  3186. {
  3187. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3188. uint32_t reg_addr, reg_val = 0;
  3189. uint32_t val = 0;
  3190. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3191. val = HAL_REG_READ(hal_soc, reg_addr);
  3192. /* reset the corresponding bits in register */
  3193. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  3194. /* set config value */
  3195. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  3196. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3197. }
  3198. #else
  3199. static inline void
  3200. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3201. hal_soc_handle_t hal_soc_hdl,
  3202. enum hal_tx_mcast_mlo_reinject_notify config)
  3203. {
  3204. }
  3205. #endif
  3206. /**
  3207. * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout
  3208. *
  3209. * @hal_soc_hdl: Opaque HAL SOC handle
  3210. * @ac: Access category
  3211. * @value: window size to get
  3212. */
  3213. static inline
  3214. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3215. uint8_t ac, uint32_t *value)
  3216. {
  3217. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3218. switch (ac) {
  3219. case WME_AC_BE:
  3220. *value = HAL_REG_READ(soc,
  3221. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3222. REO_REG_REG_BASE)) / 1000;
  3223. break;
  3224. case WME_AC_BK:
  3225. *value = HAL_REG_READ(soc,
  3226. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3227. REO_REG_REG_BASE)) / 1000;
  3228. break;
  3229. case WME_AC_VI:
  3230. *value = HAL_REG_READ(soc,
  3231. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3232. REO_REG_REG_BASE)) / 1000;
  3233. break;
  3234. case WME_AC_VO:
  3235. *value = HAL_REG_READ(soc,
  3236. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3237. REO_REG_REG_BASE)) / 1000;
  3238. break;
  3239. default:
  3240. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3241. "Invalid AC: %d\n", ac);
  3242. }
  3243. }
  3244. /**
  3245. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  3246. * buffer list provided
  3247. *
  3248. * @soc: Opaque HAL SOC handle
  3249. * @scatter_bufs_base_paddr: Array of physical base addresses
  3250. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  3251. * @num_scatter_bufs: Number of scatter buffers in the above lists
  3252. * @scatter_buf_size: Size of each scatter buffer
  3253. * @last_buf_end_offset: Offset to the last entry
  3254. * @num_entries: Total entries of all scatter bufs
  3255. *
  3256. * Return: None
  3257. */
  3258. static inline void
  3259. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  3260. qdf_dma_addr_t scatter_bufs_base_paddr[],
  3261. void *scatter_bufs_base_vaddr[],
  3262. uint32_t num_scatter_bufs,
  3263. uint32_t scatter_buf_size,
  3264. uint32_t last_buf_end_offset,
  3265. uint32_t num_entries)
  3266. {
  3267. int i;
  3268. uint32_t *prev_buf_link_ptr = NULL;
  3269. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  3270. uint32_t val;
  3271. /* Link the scatter buffers */
  3272. for (i = 0; i < num_scatter_bufs; i++) {
  3273. if (i > 0) {
  3274. prev_buf_link_ptr[0] =
  3275. scatter_bufs_base_paddr[i] & 0xffffffff;
  3276. prev_buf_link_ptr[1] = HAL_SM(
  3277. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3278. BASE_ADDRESS_39_32,
  3279. ((uint64_t)(scatter_bufs_base_paddr[i])
  3280. >> 32)) | HAL_SM(
  3281. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3282. ADDRESS_MATCH_TAG,
  3283. ADDRESS_MATCH_TAG_VAL);
  3284. }
  3285. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  3286. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  3287. }
  3288. /* TBD: Register programming partly based on MLD & the rest based on
  3289. * inputs from HW team. Not complete yet.
  3290. */
  3291. reg_scatter_buf_size = (scatter_buf_size -
  3292. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  3293. reg_tot_scatter_buf_size = ((scatter_buf_size -
  3294. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  3295. HAL_REG_WRITE(soc,
  3296. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  3297. WBM_REG_REG_BASE),
  3298. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  3299. reg_scatter_buf_size) |
  3300. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  3301. 0x1));
  3302. HAL_REG_WRITE(soc,
  3303. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  3304. WBM_REG_REG_BASE),
  3305. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  3306. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  3307. reg_tot_scatter_buf_size));
  3308. HAL_REG_WRITE(soc,
  3309. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  3310. WBM_REG_REG_BASE),
  3311. scatter_bufs_base_paddr[0] & 0xffffffff);
  3312. HAL_REG_WRITE(soc,
  3313. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3314. WBM_REG_REG_BASE),
  3315. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  3316. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  3317. HAL_REG_WRITE(soc,
  3318. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3319. WBM_REG_REG_BASE),
  3320. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3321. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  3322. >> 32)) |
  3323. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3324. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  3325. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  3326. * with the upper bits of link pointer. The above write sets this field
  3327. * to zero and we are also setting the upper bits of link pointers to
  3328. * zero while setting up the link list of scatter buffers above
  3329. */
  3330. /* Setup head and tail pointers for the idle list */
  3331. HAL_REG_WRITE(soc,
  3332. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3333. WBM_REG_REG_BASE),
  3334. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  3335. HAL_REG_WRITE(soc,
  3336. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  3337. WBM_REG_REG_BASE),
  3338. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3339. BUFFER_ADDRESS_39_32,
  3340. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  3341. >> 32)) |
  3342. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3343. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  3344. HAL_REG_WRITE(soc,
  3345. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3346. WBM_REG_REG_BASE),
  3347. scatter_bufs_base_paddr[0] & 0xffffffff);
  3348. HAL_REG_WRITE(soc,
  3349. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  3350. WBM_REG_REG_BASE),
  3351. scatter_bufs_base_paddr[0] & 0xffffffff);
  3352. HAL_REG_WRITE(soc,
  3353. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  3354. WBM_REG_REG_BASE),
  3355. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3356. BUFFER_ADDRESS_39_32,
  3357. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  3358. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3359. TAIL_POINTER_OFFSET, 0));
  3360. HAL_REG_WRITE(soc,
  3361. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  3362. WBM_REG_REG_BASE),
  3363. 2 * num_entries);
  3364. /* Set RING_ID_DISABLE */
  3365. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  3366. /*
  3367. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  3368. * check the presence of the bit before toggling it.
  3369. */
  3370. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  3371. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  3372. #endif
  3373. HAL_REG_WRITE(soc,
  3374. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  3375. val);
  3376. }
  3377. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3378. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  3379. #endif
  3380. /**
  3381. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  3382. * for REO/WBM
  3383. * @hal_soc_hdl: HAL soc handle
  3384. * @cc_cfg: structure pointer for HW cookie conversion configuration
  3385. *
  3386. * Return: None
  3387. */
  3388. static inline
  3389. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  3390. struct hal_hw_cc_config *cc_cfg)
  3391. {
  3392. uint32_t reg_addr, reg_val = 0;
  3393. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3394. /* REO CFG */
  3395. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  3396. reg_val = cc_cfg->lut_base_addr_31_0;
  3397. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3398. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  3399. reg_val = 0;
  3400. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3401. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  3402. cc_cfg->cc_global_en);
  3403. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3404. SW_COOKIE_CONVERT_ENABLE,
  3405. cc_cfg->cc_global_en);
  3406. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3407. PAGE_ALIGNMENT,
  3408. cc_cfg->page_4k_align);
  3409. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3410. COOKIE_OFFSET_MSB,
  3411. cc_cfg->cookie_offset_msb);
  3412. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3413. COOKIE_PAGE_MSB,
  3414. cc_cfg->cookie_page_msb);
  3415. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3416. CMEM_LUT_BASE_ADDR_39_32,
  3417. cc_cfg->lut_base_addr_39_32);
  3418. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3419. /* WBM CFG */
  3420. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  3421. reg_val = cc_cfg->lut_base_addr_31_0;
  3422. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3423. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  3424. reg_val = 0;
  3425. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3426. PAGE_ALIGNMENT,
  3427. cc_cfg->page_4k_align);
  3428. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3429. COOKIE_OFFSET_MSB,
  3430. cc_cfg->cookie_offset_msb);
  3431. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3432. COOKIE_PAGE_MSB,
  3433. cc_cfg->cookie_page_msb);
  3434. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3435. CMEM_LUT_BASE_ADDR_39_32,
  3436. cc_cfg->lut_base_addr_39_32);
  3437. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3438. /*
  3439. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  3440. */
  3441. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  3442. reg_val = 0;
  3443. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3444. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  3445. cc_cfg->cc_global_en);
  3446. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3447. WBM2SW6_COOKIE_CONVERSION_EN,
  3448. cc_cfg->wbm2sw6_cc_en);
  3449. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3450. WBM2SW5_COOKIE_CONVERSION_EN,
  3451. cc_cfg->wbm2sw5_cc_en);
  3452. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3453. WBM2SW4_COOKIE_CONVERSION_EN,
  3454. cc_cfg->wbm2sw4_cc_en);
  3455. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3456. WBM2SW3_COOKIE_CONVERSION_EN,
  3457. cc_cfg->wbm2sw3_cc_en);
  3458. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3459. WBM2SW2_COOKIE_CONVERSION_EN,
  3460. cc_cfg->wbm2sw2_cc_en);
  3461. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3462. WBM2SW1_COOKIE_CONVERSION_EN,
  3463. cc_cfg->wbm2sw1_cc_en);
  3464. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3465. WBM2SW0_COOKIE_CONVERSION_EN,
  3466. cc_cfg->wbm2sw0_cc_en);
  3467. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3468. WBM2FW_COOKIE_CONVERSION_EN,
  3469. cc_cfg->wbm2fw_cc_en);
  3470. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3471. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  3472. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  3473. reg_val = 0;
  3474. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3475. COOKIE_DEBUG_SEL,
  3476. cc_cfg->cc_global_en);
  3477. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3478. COOKIE_CONV_INDICATION_EN,
  3479. cc_cfg->cc_global_en);
  3480. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3481. ERROR_PATH_COOKIE_CONV_EN,
  3482. cc_cfg->error_path_cookie_conv_en);
  3483. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3484. RELEASE_PATH_COOKIE_CONV_EN,
  3485. cc_cfg->release_path_cookie_conv_en);
  3486. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3487. #endif
  3488. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3489. /*
  3490. * To enable indication for HW cookie conversion done or not for
  3491. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  3492. * bit spare_control[15] should be set.
  3493. */
  3494. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  3495. reg_val = HAL_REG_READ(soc, reg_addr);
  3496. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  3497. SPARE_CONTROL,
  3498. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  3499. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3500. #endif
  3501. }
  3502. /**
  3503. * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout
  3504. * @hal_soc_hdl: Opaque HAL SOC handle
  3505. * @ac: Access category
  3506. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  3507. * @value: Input value to set
  3508. */
  3509. static inline
  3510. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3511. uint8_t ac, uint32_t value)
  3512. {
  3513. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3514. switch (ac) {
  3515. case WME_AC_BE:
  3516. HAL_REG_WRITE(soc,
  3517. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3518. REO_REG_REG_BASE),
  3519. value * 1000);
  3520. break;
  3521. case WME_AC_BK:
  3522. HAL_REG_WRITE(soc,
  3523. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3524. REO_REG_REG_BASE),
  3525. value * 1000);
  3526. break;
  3527. case WME_AC_VI:
  3528. HAL_REG_WRITE(soc,
  3529. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3530. REO_REG_REG_BASE),
  3531. value * 1000);
  3532. break;
  3533. case WME_AC_VO:
  3534. HAL_REG_WRITE(soc,
  3535. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3536. REO_REG_REG_BASE),
  3537. value * 1000);
  3538. break;
  3539. default:
  3540. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3541. "Invalid AC: %d\n", ac);
  3542. }
  3543. }
  3544. /**
  3545. * hal_tx_populate_bank_register_be() - populate the bank register with
  3546. * the software configs.
  3547. * @hal_soc_hdl: HAL soc handle
  3548. * @config: bank config
  3549. * @bank_id: bank id to be configured
  3550. *
  3551. * Returns: None
  3552. */
  3553. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  3554. static inline void
  3555. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3556. union hal_tx_bank_config *config,
  3557. uint8_t bank_id)
  3558. {
  3559. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3560. uint32_t reg_addr, reg_val = 0;
  3561. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3562. bank_id);
  3563. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3564. reg_val |= (config->encap_type <<
  3565. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3566. reg_val |= (config->encrypt_type <<
  3567. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3568. reg_val |= (config->src_buffer_swap <<
  3569. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3570. reg_val |= (config->link_meta_swap <<
  3571. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3572. reg_val |= (config->index_lookup_enable <<
  3573. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3574. reg_val |= (config->addrx_en <<
  3575. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3576. reg_val |= (config->addry_en <<
  3577. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3578. reg_val |= (config->mesh_enable <<
  3579. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3580. reg_val |= (config->vdev_id_check_en <<
  3581. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3582. reg_val |= (config->pmac_id <<
  3583. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3584. reg_val |= (config->mcast_pkt_ctrl <<
  3585. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  3586. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3587. }
  3588. #else
  3589. static inline void
  3590. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3591. union hal_tx_bank_config *config,
  3592. uint8_t bank_id)
  3593. {
  3594. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3595. uint32_t reg_addr, reg_val = 0;
  3596. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3597. bank_id);
  3598. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3599. reg_val |= (config->encap_type <<
  3600. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3601. reg_val |= (config->encrypt_type <<
  3602. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3603. reg_val |= (config->src_buffer_swap <<
  3604. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3605. reg_val |= (config->link_meta_swap <<
  3606. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3607. reg_val |= (config->index_lookup_enable <<
  3608. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3609. reg_val |= (config->addrx_en <<
  3610. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3611. reg_val |= (config->addry_en <<
  3612. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3613. reg_val |= (config->mesh_enable <<
  3614. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3615. reg_val |= (config->vdev_id_check_en <<
  3616. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3617. reg_val |= (config->pmac_id <<
  3618. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3619. reg_val |= (config->dscp_tid_map_id <<
  3620. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  3621. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3622. }
  3623. #endif
  3624. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  3625. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  3626. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  3627. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  3628. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  3629. /**
  3630. * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value
  3631. * @hal_soc_hdl: HAL SoC context
  3632. * @vdev_id: vdev identifier
  3633. * @mcast_ctrl_val: mcast ctrl value for this VAP
  3634. *
  3635. * Return: void
  3636. */
  3637. static inline void
  3638. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3639. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3640. {
  3641. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3642. uint32_t reg_addr, reg_val = 0;
  3643. uint32_t val;
  3644. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  3645. uint8_t index_in_reg =
  3646. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  3647. reg_addr =
  3648. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  3649. reg_idx);
  3650. val = HAL_REG_READ(hal_soc, reg_addr);
  3651. /* mask out other stored value */
  3652. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  3653. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  3654. reg_val = val |
  3655. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  3656. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  3657. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3658. }
  3659. #else
  3660. static inline void
  3661. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3662. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3663. {
  3664. }
  3665. #endif
  3666. #endif /* _HAL_BE_GENERIC_API_H_ */