dp_tx.c 165 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  115. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  116. {
  117. enum dp_tx_event_type type;
  118. if (flags & DP_TX_DESC_FLAG_FLUSH)
  119. type = DP_TX_DESC_FLUSH;
  120. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  121. type = DP_TX_COMP_UNMAP_ERR;
  122. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  123. type = DP_TX_COMP_UNMAP;
  124. else
  125. type = DP_TX_DESC_UNMAP;
  126. return type;
  127. }
  128. static inline void
  129. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  130. qdf_nbuf_t skb, uint32_t sw_cookie,
  131. enum dp_tx_event_type type)
  132. {
  133. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  134. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  135. struct dp_tx_desc_event *entry;
  136. uint32_t idx;
  137. uint16_t slot;
  138. switch (type) {
  139. case DP_TX_COMP_UNMAP:
  140. case DP_TX_COMP_UNMAP_ERR:
  141. case DP_TX_COMP_MSDU_EXT:
  142. if (qdf_unlikely(!tx_comp_history->allocated))
  143. return;
  144. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  145. &slot,
  146. DP_TX_COMP_HIST_SLOT_SHIFT,
  147. DP_TX_COMP_HIST_PER_SLOT_MAX,
  148. DP_TX_COMP_HISTORY_SIZE);
  149. entry = &tx_comp_history->entry[slot][idx];
  150. break;
  151. case DP_TX_DESC_MAP:
  152. case DP_TX_DESC_UNMAP:
  153. case DP_TX_DESC_COOKIE:
  154. case DP_TX_DESC_FLUSH:
  155. if (qdf_unlikely(!tx_tcl_history->allocated))
  156. return;
  157. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  158. &slot,
  159. DP_TX_TCL_HIST_SLOT_SHIFT,
  160. DP_TX_TCL_HIST_PER_SLOT_MAX,
  161. DP_TX_TCL_HISTORY_SIZE);
  162. entry = &tx_tcl_history->entry[slot][idx];
  163. break;
  164. default:
  165. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  166. return;
  167. }
  168. entry->skb = skb;
  169. entry->paddr = paddr;
  170. entry->sw_cookie = sw_cookie;
  171. entry->type = type;
  172. entry->ts = qdf_get_log_timestamp();
  173. }
  174. static inline void
  175. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  176. struct qdf_tso_seg_elem_t *tso_seg,
  177. qdf_nbuf_t skb, uint32_t sw_cookie,
  178. enum dp_tx_event_type type)
  179. {
  180. int i;
  181. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  182. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  183. skb, sw_cookie, type);
  184. }
  185. if (!tso_seg->next)
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  187. skb, 0xFFFFFFFF, type);
  188. }
  189. static inline void
  190. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  191. qdf_nbuf_t skb, uint32_t sw_cookie,
  192. enum dp_tx_event_type type)
  193. {
  194. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  195. uint32_t num_segs = tso_info.num_segs;
  196. while (num_segs) {
  197. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  198. curr_seg = curr_seg->next;
  199. num_segs--;
  200. }
  201. }
  202. #else
  203. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  204. {
  205. return DP_TX_DESC_INVAL_EVT;
  206. }
  207. static inline void
  208. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  209. qdf_nbuf_t skb, uint32_t sw_cookie,
  210. enum dp_tx_event_type type)
  211. {
  212. }
  213. static inline void
  214. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  215. struct qdf_tso_seg_elem_t *tso_seg,
  216. qdf_nbuf_t skb, uint32_t sw_cookie,
  217. enum dp_tx_event_type type)
  218. {
  219. }
  220. static inline void
  221. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  222. qdf_nbuf_t skb, uint32_t sw_cookie,
  223. enum dp_tx_event_type type)
  224. {
  225. }
  226. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  227. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  228. /**
  229. * dp_is_tput_high() - Check if throughput is high
  230. *
  231. * @soc - core txrx main context
  232. *
  233. * The current function is based of the RTPM tput policy variable where RTPM is
  234. * avoided based on throughput.
  235. */
  236. static inline int dp_is_tput_high(struct dp_soc *soc)
  237. {
  238. return dp_get_rtpm_tput_policy_requirement(soc);
  239. }
  240. #if defined(FEATURE_TSO)
  241. /**
  242. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  243. *
  244. * @soc - core txrx main context
  245. * @seg_desc - tso segment descriptor
  246. * @num_seg_desc - tso number segment descriptor
  247. */
  248. static void dp_tx_tso_unmap_segment(
  249. struct dp_soc *soc,
  250. struct qdf_tso_seg_elem_t *seg_desc,
  251. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  252. {
  253. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  254. if (qdf_unlikely(!seg_desc)) {
  255. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  256. __func__, __LINE__);
  257. qdf_assert(0);
  258. } else if (qdf_unlikely(!num_seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else {
  263. bool is_last_seg;
  264. /* no tso segment left to do dma unmap */
  265. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  266. return;
  267. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  268. true : false;
  269. qdf_nbuf_unmap_tso_segment(soc->osdev,
  270. seg_desc, is_last_seg);
  271. num_seg_desc->num_seg.tso_cmn_num_seg--;
  272. }
  273. }
  274. /**
  275. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  276. * back to the freelist
  277. *
  278. * @soc - soc device handle
  279. * @tx_desc - Tx software descriptor
  280. */
  281. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  282. struct dp_tx_desc_s *tx_desc)
  283. {
  284. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  285. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  286. dp_tx_err("SO desc is NULL!");
  287. qdf_assert(0);
  288. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  289. dp_tx_err("TSO num desc is NULL!");
  290. qdf_assert(0);
  291. } else {
  292. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  293. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  294. msdu_ext_desc->tso_num_desc;
  295. /* Add the tso num segment into the free list */
  296. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  297. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  298. tx_desc->msdu_ext_desc->
  299. tso_num_desc);
  300. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  301. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  302. }
  303. /* Add the tso segment into the free list*/
  304. dp_tx_tso_desc_free(soc,
  305. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  306. tso_desc);
  307. tx_desc->msdu_ext_desc->tso_desc = NULL;
  308. }
  309. }
  310. #else
  311. static void dp_tx_tso_unmap_segment(
  312. struct dp_soc *soc,
  313. struct qdf_tso_seg_elem_t *seg_desc,
  314. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  315. {
  316. }
  317. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  318. struct dp_tx_desc_s *tx_desc)
  319. {
  320. }
  321. #endif
  322. /**
  323. * dp_tx_desc_release() - Release Tx Descriptor
  324. * @tx_desc : Tx Descriptor
  325. * @desc_pool_id: Descriptor Pool ID
  326. *
  327. * Deallocate all resources attached to Tx descriptor and free the Tx
  328. * descriptor.
  329. *
  330. * Return:
  331. */
  332. void
  333. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  334. {
  335. struct dp_pdev *pdev = tx_desc->pdev;
  336. struct dp_soc *soc;
  337. uint8_t comp_status = 0;
  338. qdf_assert(pdev);
  339. soc = pdev->soc;
  340. dp_tx_outstanding_dec(pdev);
  341. if (tx_desc->msdu_ext_desc) {
  342. if (tx_desc->frm_type == dp_tx_frm_tso)
  343. dp_tx_tso_desc_release(soc, tx_desc);
  344. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  345. dp_tx_me_free_buf(tx_desc->pdev,
  346. tx_desc->msdu_ext_desc->me_buffer);
  347. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  348. }
  349. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  350. qdf_atomic_dec(&soc->num_tx_exception);
  351. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  352. tx_desc->buffer_src)
  353. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  354. soc->hal_soc);
  355. else
  356. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  357. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  358. tx_desc->id, comp_status,
  359. qdf_atomic_read(&pdev->num_tx_outstanding));
  360. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  361. return;
  362. }
  363. /**
  364. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  365. * @vdev: DP vdev Handle
  366. * @nbuf: skb
  367. * @msdu_info: msdu_info required to create HTT metadata
  368. *
  369. * Prepares and fills HTT metadata in the frame pre-header for special frames
  370. * that should be transmitted using varying transmit parameters.
  371. * There are 2 VDEV modes that currently needs this special metadata -
  372. * 1) Mesh Mode
  373. * 2) DSRC Mode
  374. *
  375. * Return: HTT metadata size
  376. *
  377. */
  378. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  379. struct dp_tx_msdu_info_s *msdu_info)
  380. {
  381. uint32_t *meta_data = msdu_info->meta_data;
  382. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  383. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  384. uint8_t htt_desc_size;
  385. /* Size rounded of multiple of 8 bytes */
  386. uint8_t htt_desc_size_aligned;
  387. uint8_t *hdr = NULL;
  388. /*
  389. * Metadata - HTT MSDU Extension header
  390. */
  391. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  392. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  393. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  394. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  395. meta_data[0]) ||
  396. msdu_info->exception_fw) {
  397. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  398. htt_desc_size_aligned)) {
  399. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  400. htt_desc_size_aligned);
  401. if (!nbuf) {
  402. /*
  403. * qdf_nbuf_realloc_headroom won't do skb_clone
  404. * as skb_realloc_headroom does. so, no free is
  405. * needed here.
  406. */
  407. DP_STATS_INC(vdev,
  408. tx_i.dropped.headroom_insufficient,
  409. 1);
  410. qdf_print(" %s[%d] skb_realloc_headroom failed",
  411. __func__, __LINE__);
  412. return 0;
  413. }
  414. }
  415. /* Fill and add HTT metaheader */
  416. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  417. if (!hdr) {
  418. dp_tx_err("Error in filling HTT metadata");
  419. return 0;
  420. }
  421. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  422. } else if (vdev->opmode == wlan_op_mode_ocb) {
  423. /* Todo - Add support for DSRC */
  424. }
  425. return htt_desc_size_aligned;
  426. }
  427. /**
  428. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  429. * @tso_seg: TSO segment to process
  430. * @ext_desc: Pointer to MSDU extension descriptor
  431. *
  432. * Return: void
  433. */
  434. #if defined(FEATURE_TSO)
  435. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  436. void *ext_desc)
  437. {
  438. uint8_t num_frag;
  439. uint32_t tso_flags;
  440. /*
  441. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  442. * tcp_flag_mask
  443. *
  444. * Checksum enable flags are set in TCL descriptor and not in Extension
  445. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  446. */
  447. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  448. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  449. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  450. tso_seg->tso_flags.ip_len);
  451. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  452. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  453. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  454. uint32_t lo = 0;
  455. uint32_t hi = 0;
  456. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  457. (tso_seg->tso_frags[num_frag].length));
  458. qdf_dmaaddr_to_32s(
  459. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  460. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  461. tso_seg->tso_frags[num_frag].length);
  462. }
  463. return;
  464. }
  465. #else
  466. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  467. void *ext_desc)
  468. {
  469. return;
  470. }
  471. #endif
  472. #if defined(FEATURE_TSO)
  473. /**
  474. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  475. * allocated and free them
  476. *
  477. * @soc: soc handle
  478. * @free_seg: list of tso segments
  479. * @msdu_info: msdu descriptor
  480. *
  481. * Return - void
  482. */
  483. static void dp_tx_free_tso_seg_list(
  484. struct dp_soc *soc,
  485. struct qdf_tso_seg_elem_t *free_seg,
  486. struct dp_tx_msdu_info_s *msdu_info)
  487. {
  488. struct qdf_tso_seg_elem_t *next_seg;
  489. while (free_seg) {
  490. next_seg = free_seg->next;
  491. dp_tx_tso_desc_free(soc,
  492. msdu_info->tx_queue.desc_pool_id,
  493. free_seg);
  494. free_seg = next_seg;
  495. }
  496. }
  497. /**
  498. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  499. * allocated and free them
  500. *
  501. * @soc: soc handle
  502. * @free_num_seg: list of tso number segments
  503. * @msdu_info: msdu descriptor
  504. * Return - void
  505. */
  506. static void dp_tx_free_tso_num_seg_list(
  507. struct dp_soc *soc,
  508. struct qdf_tso_num_seg_elem_t *free_num_seg,
  509. struct dp_tx_msdu_info_s *msdu_info)
  510. {
  511. struct qdf_tso_num_seg_elem_t *next_num_seg;
  512. while (free_num_seg) {
  513. next_num_seg = free_num_seg->next;
  514. dp_tso_num_seg_free(soc,
  515. msdu_info->tx_queue.desc_pool_id,
  516. free_num_seg);
  517. free_num_seg = next_num_seg;
  518. }
  519. }
  520. /**
  521. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  522. * do dma unmap for each segment
  523. *
  524. * @soc: soc handle
  525. * @free_seg: list of tso segments
  526. * @num_seg_desc: tso number segment descriptor
  527. *
  528. * Return - void
  529. */
  530. static void dp_tx_unmap_tso_seg_list(
  531. struct dp_soc *soc,
  532. struct qdf_tso_seg_elem_t *free_seg,
  533. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  534. {
  535. struct qdf_tso_seg_elem_t *next_seg;
  536. if (qdf_unlikely(!num_seg_desc)) {
  537. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  538. return;
  539. }
  540. while (free_seg) {
  541. next_seg = free_seg->next;
  542. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  543. free_seg = next_seg;
  544. }
  545. }
  546. #ifdef FEATURE_TSO_STATS
  547. /**
  548. * dp_tso_get_stats_idx: Retrieve the tso packet id
  549. * @pdev - pdev handle
  550. *
  551. * Return: id
  552. */
  553. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  554. {
  555. uint32_t stats_idx;
  556. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  557. % CDP_MAX_TSO_PACKETS);
  558. return stats_idx;
  559. }
  560. #else
  561. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  562. {
  563. return 0;
  564. }
  565. #endif /* FEATURE_TSO_STATS */
  566. /**
  567. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  568. * free the tso segments descriptor and
  569. * tso num segments descriptor
  570. *
  571. * @soc: soc handle
  572. * @msdu_info: msdu descriptor
  573. * @tso_seg_unmap: flag to show if dma unmap is necessary
  574. *
  575. * Return - void
  576. */
  577. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  578. struct dp_tx_msdu_info_s *msdu_info,
  579. bool tso_seg_unmap)
  580. {
  581. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  582. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  583. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  584. tso_info->tso_num_seg_list;
  585. /* do dma unmap for each segment */
  586. if (tso_seg_unmap)
  587. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  588. /* free all tso number segment descriptor though looks only have 1 */
  589. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  590. /* free all tso segment descriptor */
  591. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  592. }
  593. /**
  594. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  595. * @vdev: virtual device handle
  596. * @msdu: network buffer
  597. * @msdu_info: meta data associated with the msdu
  598. *
  599. * Return: QDF_STATUS_SUCCESS success
  600. */
  601. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  602. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  603. {
  604. struct qdf_tso_seg_elem_t *tso_seg;
  605. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  606. struct dp_soc *soc = vdev->pdev->soc;
  607. struct dp_pdev *pdev = vdev->pdev;
  608. struct qdf_tso_info_t *tso_info;
  609. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  610. tso_info = &msdu_info->u.tso_info;
  611. tso_info->curr_seg = NULL;
  612. tso_info->tso_seg_list = NULL;
  613. tso_info->num_segs = num_seg;
  614. msdu_info->frm_type = dp_tx_frm_tso;
  615. tso_info->tso_num_seg_list = NULL;
  616. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  617. while (num_seg) {
  618. tso_seg = dp_tx_tso_desc_alloc(
  619. soc, msdu_info->tx_queue.desc_pool_id);
  620. if (tso_seg) {
  621. tso_seg->next = tso_info->tso_seg_list;
  622. tso_info->tso_seg_list = tso_seg;
  623. num_seg--;
  624. } else {
  625. dp_err_rl("Failed to alloc tso seg desc");
  626. DP_STATS_INC_PKT(vdev->pdev,
  627. tso_stats.tso_no_mem_dropped, 1,
  628. qdf_nbuf_len(msdu));
  629. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  630. return QDF_STATUS_E_NOMEM;
  631. }
  632. }
  633. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  634. tso_num_seg = dp_tso_num_seg_alloc(soc,
  635. msdu_info->tx_queue.desc_pool_id);
  636. if (tso_num_seg) {
  637. tso_num_seg->next = tso_info->tso_num_seg_list;
  638. tso_info->tso_num_seg_list = tso_num_seg;
  639. } else {
  640. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  641. __func__);
  642. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  643. return QDF_STATUS_E_NOMEM;
  644. }
  645. msdu_info->num_seg =
  646. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  647. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  648. msdu_info->num_seg);
  649. if (!(msdu_info->num_seg)) {
  650. /*
  651. * Free allocated TSO seg desc and number seg desc,
  652. * do unmap for segments if dma map has done.
  653. */
  654. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  655. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  656. return QDF_STATUS_E_INVAL;
  657. }
  658. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  659. msdu, 0, DP_TX_DESC_MAP);
  660. tso_info->curr_seg = tso_info->tso_seg_list;
  661. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  662. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  663. msdu, msdu_info->num_seg);
  664. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  665. tso_info->msdu_stats_idx);
  666. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  667. return QDF_STATUS_SUCCESS;
  668. }
  669. #else
  670. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  671. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  672. {
  673. return QDF_STATUS_E_NOMEM;
  674. }
  675. #endif
  676. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  677. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  678. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  679. /**
  680. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  681. * @vdev: DP Vdev handle
  682. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  683. * @desc_pool_id: Descriptor Pool ID
  684. *
  685. * Return:
  686. */
  687. static
  688. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  689. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  690. {
  691. uint8_t i;
  692. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  693. struct dp_tx_seg_info_s *seg_info;
  694. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  695. struct dp_soc *soc = vdev->pdev->soc;
  696. /* Allocate an extension descriptor */
  697. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  698. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  699. if (!msdu_ext_desc) {
  700. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  701. return NULL;
  702. }
  703. if (msdu_info->exception_fw &&
  704. qdf_unlikely(vdev->mesh_vdev)) {
  705. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  706. &msdu_info->meta_data[0],
  707. sizeof(struct htt_tx_msdu_desc_ext2_t));
  708. qdf_atomic_inc(&soc->num_tx_exception);
  709. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  710. }
  711. switch (msdu_info->frm_type) {
  712. case dp_tx_frm_sg:
  713. case dp_tx_frm_me:
  714. case dp_tx_frm_raw:
  715. seg_info = msdu_info->u.sg_info.curr_seg;
  716. /* Update the buffer pointers in MSDU Extension Descriptor */
  717. for (i = 0; i < seg_info->frag_cnt; i++) {
  718. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  719. seg_info->frags[i].paddr_lo,
  720. seg_info->frags[i].paddr_hi,
  721. seg_info->frags[i].len);
  722. }
  723. break;
  724. case dp_tx_frm_tso:
  725. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  726. &cached_ext_desc[0]);
  727. break;
  728. default:
  729. break;
  730. }
  731. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  732. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  733. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  734. msdu_ext_desc->vaddr);
  735. return msdu_ext_desc;
  736. }
  737. /**
  738. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  739. *
  740. * @skb: skb to be traced
  741. * @msdu_id: msdu_id of the packet
  742. * @vdev_id: vdev_id of the packet
  743. *
  744. * Return: None
  745. */
  746. #ifdef DP_DISABLE_TX_PKT_TRACE
  747. static void dp_tx_trace_pkt(struct dp_soc *soc,
  748. qdf_nbuf_t skb, uint16_t msdu_id,
  749. uint8_t vdev_id)
  750. {
  751. }
  752. #else
  753. static void dp_tx_trace_pkt(struct dp_soc *soc,
  754. qdf_nbuf_t skb, uint16_t msdu_id,
  755. uint8_t vdev_id)
  756. {
  757. if (dp_is_tput_high(soc))
  758. return;
  759. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  760. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  761. DPTRACE(qdf_dp_trace_ptr(skb,
  762. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  763. QDF_TRACE_DEFAULT_PDEV_ID,
  764. qdf_nbuf_data_addr(skb),
  765. sizeof(qdf_nbuf_data(skb)),
  766. msdu_id, vdev_id, 0));
  767. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  768. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  769. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  770. msdu_id, QDF_TX));
  771. }
  772. #endif
  773. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  774. /**
  775. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  776. * exception by the upper layer (OS_IF)
  777. * @soc: DP soc handle
  778. * @nbuf: packet to be transmitted
  779. *
  780. * Returns: 1 if the packet is marked as exception,
  781. * 0, if the packet is not marked as exception.
  782. */
  783. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  784. qdf_nbuf_t nbuf)
  785. {
  786. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  787. }
  788. #else
  789. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  790. qdf_nbuf_t nbuf)
  791. {
  792. return 0;
  793. }
  794. #endif
  795. #ifdef DP_TRAFFIC_END_INDICATION
  796. /**
  797. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  798. * as indication to fw to inform that
  799. * data stream has ended
  800. * @vdev: DP vdev handle
  801. * @nbuf: original buffer from network stack
  802. *
  803. * Return: NULL on failure,
  804. * nbuf on success
  805. */
  806. static inline qdf_nbuf_t
  807. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  808. qdf_nbuf_t nbuf)
  809. {
  810. /* Packet length should be enough to copy upto L3 header */
  811. uint8_t end_nbuf_len = 64;
  812. uint8_t htt_desc_size_aligned;
  813. uint8_t htt_desc_size;
  814. qdf_nbuf_t end_nbuf;
  815. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  816. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  817. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  818. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  819. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  820. if (!end_nbuf) {
  821. end_nbuf = qdf_nbuf_alloc(NULL,
  822. (htt_desc_size_aligned +
  823. end_nbuf_len),
  824. htt_desc_size_aligned,
  825. 8, false);
  826. if (!end_nbuf) {
  827. dp_err("Packet allocation failed");
  828. goto out;
  829. }
  830. } else {
  831. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  832. }
  833. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  834. end_nbuf_len);
  835. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  836. return end_nbuf;
  837. }
  838. out:
  839. return NULL;
  840. }
  841. /**
  842. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  843. * via exception path.
  844. * @vdev: DP vdev handle
  845. * @end_nbuf: skb to send as indication
  846. * @msdu_info: msdu_info of original nbuf
  847. * @peer_id: peer id
  848. *
  849. * Return: None
  850. */
  851. static inline void
  852. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  853. qdf_nbuf_t end_nbuf,
  854. struct dp_tx_msdu_info_s *msdu_info,
  855. uint16_t peer_id)
  856. {
  857. struct dp_tx_msdu_info_s e_msdu_info = {0};
  858. qdf_nbuf_t nbuf;
  859. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  860. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  861. e_msdu_info.tx_queue = msdu_info->tx_queue;
  862. e_msdu_info.tid = msdu_info->tid;
  863. e_msdu_info.exception_fw = 1;
  864. desc_ext->host_tx_desc_pool = 1;
  865. desc_ext->traffic_end_indication = 1;
  866. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  867. peer_id, NULL);
  868. if (nbuf) {
  869. dp_err("Traffic end indication packet tx failed");
  870. qdf_nbuf_free(nbuf);
  871. }
  872. }
  873. /**
  874. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  875. * mark it trafic end indication
  876. * packet.
  877. * @tx_desc: Tx descriptor pointer
  878. * @msdu_info: msdu_info structure pointer
  879. *
  880. * Return: None
  881. */
  882. static inline void
  883. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  884. struct dp_tx_msdu_info_s *msdu_info)
  885. {
  886. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  887. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  888. if (qdf_unlikely(desc_ext->traffic_end_indication))
  889. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  890. }
  891. /**
  892. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  893. * freeing which are associated
  894. * with traffic end indication
  895. * flagged descriptor.
  896. * @soc: dp soc handle
  897. * @desc: Tx descriptor pointer
  898. * @nbuf: buffer pointer
  899. *
  900. * Return: True if packet gets enqueued else false
  901. */
  902. static bool
  903. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  904. struct dp_tx_desc_s *desc,
  905. qdf_nbuf_t nbuf)
  906. {
  907. struct dp_vdev *vdev = NULL;
  908. if (qdf_unlikely((desc->flags &
  909. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  910. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  911. DP_MOD_ID_TX_COMP);
  912. if (vdev) {
  913. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  914. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  915. return true;
  916. }
  917. }
  918. return false;
  919. }
  920. /**
  921. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  922. * enable/disable status
  923. * @vdev: dp vdev handle
  924. *
  925. * Return: True if feature is enable else false
  926. */
  927. static inline bool
  928. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  929. {
  930. return qdf_unlikely(vdev->traffic_end_ind_en);
  931. }
  932. static inline qdf_nbuf_t
  933. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  934. struct dp_tx_msdu_info_s *msdu_info,
  935. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  936. {
  937. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  938. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  939. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  940. if (qdf_unlikely(end_nbuf))
  941. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  942. msdu_info, peer_id);
  943. return nbuf;
  944. }
  945. #else
  946. static inline qdf_nbuf_t
  947. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  948. qdf_nbuf_t nbuf)
  949. {
  950. return NULL;
  951. }
  952. static inline void
  953. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  954. qdf_nbuf_t end_nbuf,
  955. struct dp_tx_msdu_info_s *msdu_info,
  956. uint16_t peer_id)
  957. {}
  958. static inline void
  959. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  960. struct dp_tx_msdu_info_s *msdu_info)
  961. {}
  962. static inline bool
  963. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  964. struct dp_tx_desc_s *desc,
  965. qdf_nbuf_t nbuf)
  966. {
  967. return false;
  968. }
  969. static inline bool
  970. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  971. {
  972. return false;
  973. }
  974. static inline qdf_nbuf_t
  975. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  976. struct dp_tx_msdu_info_s *msdu_info,
  977. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  978. {
  979. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  980. }
  981. #endif
  982. /**
  983. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  984. * @vdev: DP vdev handle
  985. * @nbuf: skb
  986. * @desc_pool_id: Descriptor pool ID
  987. * @meta_data: Metadata to the fw
  988. * @tx_exc_metadata: Handle that holds exception path metadata
  989. * Allocate and prepare Tx descriptor with msdu information.
  990. *
  991. * Return: Pointer to Tx Descriptor on success,
  992. * NULL on failure
  993. */
  994. static
  995. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  996. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  997. struct dp_tx_msdu_info_s *msdu_info,
  998. struct cdp_tx_exception_metadata *tx_exc_metadata)
  999. {
  1000. uint8_t align_pad;
  1001. uint8_t is_exception = 0;
  1002. uint8_t htt_hdr_size;
  1003. struct dp_tx_desc_s *tx_desc;
  1004. struct dp_pdev *pdev = vdev->pdev;
  1005. struct dp_soc *soc = pdev->soc;
  1006. if (dp_tx_limit_check(vdev))
  1007. return NULL;
  1008. /* Allocate software Tx descriptor */
  1009. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1010. if (qdf_unlikely(!tx_desc)) {
  1011. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1012. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1013. return NULL;
  1014. }
  1015. dp_tx_outstanding_inc(pdev);
  1016. /* Initialize the SW tx descriptor */
  1017. tx_desc->nbuf = nbuf;
  1018. tx_desc->frm_type = dp_tx_frm_std;
  1019. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1020. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1021. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1022. tx_desc->vdev_id = vdev->vdev_id;
  1023. tx_desc->pdev = pdev;
  1024. tx_desc->msdu_ext_desc = NULL;
  1025. tx_desc->pkt_offset = 0;
  1026. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1027. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1028. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1029. if (qdf_unlikely(vdev->multipass_en)) {
  1030. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1031. goto failure;
  1032. }
  1033. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1034. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1035. is_exception = 1;
  1036. /*
  1037. * For special modes (vdev_type == ocb or mesh), data frames should be
  1038. * transmitted using varying transmit parameters (tx spec) which include
  1039. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1040. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1041. * These frames are sent as exception packets to firmware.
  1042. *
  1043. * HW requirement is that metadata should always point to a
  1044. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1045. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1046. * to get 8-byte aligned start address along with align_pad added
  1047. *
  1048. * |-----------------------------|
  1049. * | |
  1050. * |-----------------------------| <-----Buffer Pointer Address given
  1051. * | | ^ in HW descriptor (aligned)
  1052. * | HTT Metadata | |
  1053. * | | |
  1054. * | | | Packet Offset given in descriptor
  1055. * | | |
  1056. * |-----------------------------| |
  1057. * | Alignment Pad | v
  1058. * |-----------------------------| <----- Actual buffer start address
  1059. * | SKB Data | (Unaligned)
  1060. * | |
  1061. * | |
  1062. * | |
  1063. * | |
  1064. * | |
  1065. * |-----------------------------|
  1066. */
  1067. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1068. (vdev->opmode == wlan_op_mode_ocb) ||
  1069. (tx_exc_metadata &&
  1070. tx_exc_metadata->is_tx_sniffer)) {
  1071. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1072. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1073. DP_STATS_INC(vdev,
  1074. tx_i.dropped.headroom_insufficient, 1);
  1075. goto failure;
  1076. }
  1077. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1078. dp_tx_err("qdf_nbuf_push_head failed");
  1079. goto failure;
  1080. }
  1081. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1082. msdu_info);
  1083. if (htt_hdr_size == 0)
  1084. goto failure;
  1085. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1086. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1088. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1089. msdu_info);
  1090. is_exception = 1;
  1091. tx_desc->length -= tx_desc->pkt_offset;
  1092. }
  1093. #if !TQM_BYPASS_WAR
  1094. if (is_exception || tx_exc_metadata)
  1095. #endif
  1096. {
  1097. /* Temporary WAR due to TQM VP issues */
  1098. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1099. qdf_atomic_inc(&soc->num_tx_exception);
  1100. }
  1101. return tx_desc;
  1102. failure:
  1103. dp_tx_desc_release(tx_desc, desc_pool_id);
  1104. return NULL;
  1105. }
  1106. /**
  1107. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1108. * @vdev: DP vdev handle
  1109. * @nbuf: skb
  1110. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1111. * @desc_pool_id : Descriptor Pool ID
  1112. *
  1113. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1114. * information. For frames wth fragments, allocate and prepare
  1115. * an MSDU extension descriptor
  1116. *
  1117. * Return: Pointer to Tx Descriptor on success,
  1118. * NULL on failure
  1119. */
  1120. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1121. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1122. uint8_t desc_pool_id)
  1123. {
  1124. struct dp_tx_desc_s *tx_desc;
  1125. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1126. struct dp_pdev *pdev = vdev->pdev;
  1127. struct dp_soc *soc = pdev->soc;
  1128. if (dp_tx_limit_check(vdev))
  1129. return NULL;
  1130. /* Allocate software Tx descriptor */
  1131. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1132. if (!tx_desc) {
  1133. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1134. return NULL;
  1135. }
  1136. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1137. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1138. dp_tx_outstanding_inc(pdev);
  1139. /* Initialize the SW tx descriptor */
  1140. tx_desc->nbuf = nbuf;
  1141. tx_desc->frm_type = msdu_info->frm_type;
  1142. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1143. tx_desc->vdev_id = vdev->vdev_id;
  1144. tx_desc->pdev = pdev;
  1145. tx_desc->pkt_offset = 0;
  1146. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1147. /* Handle scattered frames - TSO/SG/ME */
  1148. /* Allocate and prepare an extension descriptor for scattered frames */
  1149. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1150. if (!msdu_ext_desc) {
  1151. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1152. goto failure;
  1153. }
  1154. #if TQM_BYPASS_WAR
  1155. /* Temporary WAR due to TQM VP issues */
  1156. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1157. qdf_atomic_inc(&soc->num_tx_exception);
  1158. #endif
  1159. if (qdf_unlikely(msdu_info->exception_fw))
  1160. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1161. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1162. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1163. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1164. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1165. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1166. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1167. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1168. else
  1169. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1170. return tx_desc;
  1171. failure:
  1172. dp_tx_desc_release(tx_desc, desc_pool_id);
  1173. return NULL;
  1174. }
  1175. /**
  1176. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1177. * @vdev: DP vdev handle
  1178. * @nbuf: buffer pointer
  1179. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1180. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1181. * descriptor
  1182. *
  1183. * Return:
  1184. */
  1185. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1186. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1187. {
  1188. qdf_nbuf_t curr_nbuf = NULL;
  1189. uint16_t total_len = 0;
  1190. qdf_dma_addr_t paddr;
  1191. int32_t i;
  1192. int32_t mapped_buf_num = 0;
  1193. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1194. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1195. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1196. /* Continue only if frames are of DATA type */
  1197. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1198. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1199. dp_tx_debug("Pkt. recd is of not data type");
  1200. goto error;
  1201. }
  1202. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1203. if (vdev->raw_mode_war &&
  1204. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1205. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1206. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1207. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1208. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1209. /*
  1210. * Number of nbuf's must not exceed the size of the frags
  1211. * array in seg_info.
  1212. */
  1213. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1214. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1215. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1216. goto error;
  1217. }
  1218. if (QDF_STATUS_SUCCESS !=
  1219. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1220. curr_nbuf,
  1221. QDF_DMA_TO_DEVICE,
  1222. curr_nbuf->len)) {
  1223. dp_tx_err("%s dma map error ", __func__);
  1224. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1225. goto error;
  1226. }
  1227. /* Update the count of mapped nbuf's */
  1228. mapped_buf_num++;
  1229. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1230. seg_info->frags[i].paddr_lo = paddr;
  1231. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1232. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1233. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1234. total_len += qdf_nbuf_len(curr_nbuf);
  1235. }
  1236. seg_info->frag_cnt = i;
  1237. seg_info->total_len = total_len;
  1238. seg_info->next = NULL;
  1239. sg_info->curr_seg = seg_info;
  1240. msdu_info->frm_type = dp_tx_frm_raw;
  1241. msdu_info->num_seg = 1;
  1242. return nbuf;
  1243. error:
  1244. i = 0;
  1245. while (nbuf) {
  1246. curr_nbuf = nbuf;
  1247. if (i < mapped_buf_num) {
  1248. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1249. QDF_DMA_TO_DEVICE,
  1250. curr_nbuf->len);
  1251. i++;
  1252. }
  1253. nbuf = qdf_nbuf_next(nbuf);
  1254. qdf_nbuf_free(curr_nbuf);
  1255. }
  1256. return NULL;
  1257. }
  1258. /**
  1259. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1260. * @soc: DP soc handle
  1261. * @nbuf: Buffer pointer
  1262. *
  1263. * unmap the chain of nbufs that belong to this RAW frame.
  1264. *
  1265. * Return: None
  1266. */
  1267. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1268. qdf_nbuf_t nbuf)
  1269. {
  1270. qdf_nbuf_t cur_nbuf = nbuf;
  1271. do {
  1272. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1273. QDF_DMA_TO_DEVICE,
  1274. cur_nbuf->len);
  1275. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1276. } while (cur_nbuf);
  1277. }
  1278. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1279. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1280. qdf_nbuf_t nbuf)
  1281. {
  1282. qdf_nbuf_t nbuf_local;
  1283. struct dp_vdev *vdev_local = vdev_hdl;
  1284. do {
  1285. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1286. break;
  1287. nbuf_local = nbuf;
  1288. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1289. htt_cmn_pkt_type_raw))
  1290. break;
  1291. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1292. break;
  1293. else if (qdf_nbuf_is_tso((nbuf_local)))
  1294. break;
  1295. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1296. (nbuf_local),
  1297. NULL, 1, 0);
  1298. } while (0);
  1299. }
  1300. #endif
  1301. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1302. /**
  1303. * dp_tx_update_stats() - Update soc level tx stats
  1304. * @soc: DP soc handle
  1305. * @tx_desc: TX descriptor reference
  1306. * @ring_id: TCL ring id
  1307. *
  1308. * Returns: none
  1309. */
  1310. void dp_tx_update_stats(struct dp_soc *soc,
  1311. struct dp_tx_desc_s *tx_desc,
  1312. uint8_t ring_id)
  1313. {
  1314. uint32_t stats_len = 0;
  1315. if (tx_desc->frm_type == dp_tx_frm_tso)
  1316. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1317. else
  1318. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1319. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1320. }
  1321. int
  1322. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1323. struct dp_tx_desc_s *tx_desc,
  1324. uint8_t tid,
  1325. struct dp_tx_msdu_info_s *msdu_info,
  1326. uint8_t ring_id)
  1327. {
  1328. struct dp_swlm *swlm = &soc->swlm;
  1329. union swlm_data swlm_query_data;
  1330. struct dp_swlm_tcl_data tcl_data;
  1331. QDF_STATUS status;
  1332. int ret;
  1333. if (!swlm->is_enabled)
  1334. return msdu_info->skip_hp_update;
  1335. tcl_data.nbuf = tx_desc->nbuf;
  1336. tcl_data.tid = tid;
  1337. tcl_data.ring_id = ring_id;
  1338. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1339. tcl_data.pkt_len =
  1340. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1341. } else {
  1342. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1343. }
  1344. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1345. swlm_query_data.tcl_data = &tcl_data;
  1346. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1347. if (QDF_IS_STATUS_ERROR(status)) {
  1348. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1349. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1350. return 0;
  1351. }
  1352. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1353. if (ret) {
  1354. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1355. } else {
  1356. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1357. }
  1358. return ret;
  1359. }
  1360. void
  1361. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1362. int coalesce)
  1363. {
  1364. if (coalesce)
  1365. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1366. else
  1367. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1368. }
  1369. static inline void
  1370. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1371. {
  1372. if (((i + 1) < msdu_info->num_seg))
  1373. msdu_info->skip_hp_update = 1;
  1374. else
  1375. msdu_info->skip_hp_update = 0;
  1376. }
  1377. static inline void
  1378. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1379. {
  1380. hal_ring_handle_t hal_ring_hdl =
  1381. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1382. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1383. dp_err("Fillmore: SRNG access start failed");
  1384. return;
  1385. }
  1386. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1387. }
  1388. static inline void
  1389. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1390. QDF_STATUS status,
  1391. struct dp_tx_msdu_info_s *msdu_info)
  1392. {
  1393. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1394. dp_flush_tcp_hp(soc,
  1395. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1396. }
  1397. }
  1398. #else
  1399. static inline void
  1400. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1401. {
  1402. }
  1403. static inline void
  1404. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1405. QDF_STATUS status,
  1406. struct dp_tx_msdu_info_s *msdu_info)
  1407. {
  1408. }
  1409. #endif
  1410. #ifdef FEATURE_RUNTIME_PM
  1411. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1412. {
  1413. int ret;
  1414. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1415. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1416. return ret;
  1417. }
  1418. /**
  1419. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1420. * @soc: Datapath soc handle
  1421. * @hal_ring_hdl: HAL ring handle
  1422. * @coalesce: Coalesce the current write or not
  1423. *
  1424. * Wrapper for HAL ring access end for data transmission for
  1425. * FEATURE_RUNTIME_PM
  1426. *
  1427. * Returns: none
  1428. */
  1429. void
  1430. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1431. hal_ring_handle_t hal_ring_hdl,
  1432. int coalesce)
  1433. {
  1434. int ret;
  1435. /*
  1436. * Avoid runtime get and put APIs under high throughput scenarios.
  1437. */
  1438. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1439. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1440. return;
  1441. }
  1442. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1443. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1444. if (hif_system_pm_state_check(soc->hif_handle) ||
  1445. qdf_unlikely(soc->is_tx_pause)) {
  1446. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1447. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1448. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1449. } else {
  1450. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1451. }
  1452. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1453. } else {
  1454. dp_runtime_get(soc);
  1455. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1456. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1457. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1458. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1459. dp_runtime_put(soc);
  1460. }
  1461. }
  1462. #else
  1463. #ifdef DP_POWER_SAVE
  1464. void
  1465. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1466. hal_ring_handle_t hal_ring_hdl,
  1467. int coalesce)
  1468. {
  1469. if (hif_system_pm_state_check(soc->hif_handle) ||
  1470. qdf_unlikely(soc->is_tx_pause)) {
  1471. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1472. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1473. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1474. } else {
  1475. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1476. }
  1477. }
  1478. #endif
  1479. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1480. {
  1481. return 0;
  1482. }
  1483. #endif
  1484. /**
  1485. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1486. * @vdev: DP vdev handle
  1487. * @nbuf: skb
  1488. *
  1489. * Extract the DSCP or PCP information from frame and map into TID value.
  1490. *
  1491. * Return: void
  1492. */
  1493. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1494. struct dp_tx_msdu_info_s *msdu_info)
  1495. {
  1496. uint8_t tos = 0, dscp_tid_override = 0;
  1497. uint8_t *hdr_ptr, *L3datap;
  1498. uint8_t is_mcast = 0;
  1499. qdf_ether_header_t *eh = NULL;
  1500. qdf_ethervlan_header_t *evh = NULL;
  1501. uint16_t ether_type;
  1502. qdf_llc_t *llcHdr;
  1503. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1504. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1505. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1506. eh = (qdf_ether_header_t *)nbuf->data;
  1507. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1508. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1509. } else {
  1510. qdf_dot3_qosframe_t *qos_wh =
  1511. (qdf_dot3_qosframe_t *) nbuf->data;
  1512. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1513. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1514. return;
  1515. }
  1516. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1517. ether_type = eh->ether_type;
  1518. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1519. /*
  1520. * Check if packet is dot3 or eth2 type.
  1521. */
  1522. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1523. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1524. sizeof(*llcHdr));
  1525. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1526. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1527. sizeof(*llcHdr);
  1528. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1529. + sizeof(*llcHdr) +
  1530. sizeof(qdf_net_vlanhdr_t));
  1531. } else {
  1532. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1533. sizeof(*llcHdr);
  1534. }
  1535. } else {
  1536. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1537. evh = (qdf_ethervlan_header_t *) eh;
  1538. ether_type = evh->ether_type;
  1539. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1540. }
  1541. }
  1542. /*
  1543. * Find priority from IP TOS DSCP field
  1544. */
  1545. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1546. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1547. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1548. /* Only for unicast frames */
  1549. if (!is_mcast) {
  1550. /* send it on VO queue */
  1551. msdu_info->tid = DP_VO_TID;
  1552. }
  1553. } else {
  1554. /*
  1555. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1556. * from TOS byte.
  1557. */
  1558. tos = ip->ip_tos;
  1559. dscp_tid_override = 1;
  1560. }
  1561. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1562. /* TODO
  1563. * use flowlabel
  1564. *igmpmld cases to be handled in phase 2
  1565. */
  1566. unsigned long ver_pri_flowlabel;
  1567. unsigned long pri;
  1568. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1569. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1570. DP_IPV6_PRIORITY_SHIFT;
  1571. tos = pri;
  1572. dscp_tid_override = 1;
  1573. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1574. msdu_info->tid = DP_VO_TID;
  1575. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1576. /* Only for unicast frames */
  1577. if (!is_mcast) {
  1578. /* send ucast arp on VO queue */
  1579. msdu_info->tid = DP_VO_TID;
  1580. }
  1581. }
  1582. /*
  1583. * Assign all MCAST packets to BE
  1584. */
  1585. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1586. if (is_mcast) {
  1587. tos = 0;
  1588. dscp_tid_override = 1;
  1589. }
  1590. }
  1591. if (dscp_tid_override == 1) {
  1592. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1593. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1594. }
  1595. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1596. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1597. return;
  1598. }
  1599. /**
  1600. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1601. * @vdev: DP vdev handle
  1602. * @nbuf: skb
  1603. *
  1604. * Software based TID classification is required when more than 2 DSCP-TID
  1605. * mapping tables are needed.
  1606. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1607. *
  1608. * Return: void
  1609. */
  1610. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1611. struct dp_tx_msdu_info_s *msdu_info)
  1612. {
  1613. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1614. /*
  1615. * skip_sw_tid_classification flag will set in below cases-
  1616. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1617. * 2. hlos_tid_override enabled for vdev
  1618. * 3. mesh mode enabled for vdev
  1619. */
  1620. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1621. /* Update tid in msdu_info from skb priority */
  1622. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1623. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1624. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1625. if (tid == DP_TX_INVALID_QOS_TAG)
  1626. return;
  1627. msdu_info->tid = tid;
  1628. return;
  1629. }
  1630. return;
  1631. }
  1632. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1633. }
  1634. #ifdef FEATURE_WLAN_TDLS
  1635. /**
  1636. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1637. * @soc: datapath SOC
  1638. * @vdev: datapath vdev
  1639. * @tx_desc: TX descriptor
  1640. *
  1641. * Return: None
  1642. */
  1643. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1644. struct dp_vdev *vdev,
  1645. struct dp_tx_desc_s *tx_desc)
  1646. {
  1647. if (vdev) {
  1648. if (vdev->is_tdls_frame) {
  1649. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1650. vdev->is_tdls_frame = false;
  1651. }
  1652. }
  1653. }
  1654. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1655. {
  1656. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1657. switch (soc->arch_id) {
  1658. case CDP_ARCH_TYPE_LI:
  1659. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1660. break;
  1661. case CDP_ARCH_TYPE_BE:
  1662. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1663. break;
  1664. default:
  1665. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1666. QDF_BUG(0);
  1667. }
  1668. return tx_status;
  1669. }
  1670. /**
  1671. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1672. * @soc: dp_soc handle
  1673. * @tx_desc: TX descriptor
  1674. * @vdev: datapath vdev handle
  1675. *
  1676. * Return: None
  1677. */
  1678. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1679. struct dp_tx_desc_s *tx_desc)
  1680. {
  1681. uint8_t tx_status = 0;
  1682. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1683. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1684. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1685. DP_MOD_ID_TDLS);
  1686. if (qdf_unlikely(!vdev)) {
  1687. dp_err_rl("vdev is null!");
  1688. goto error;
  1689. }
  1690. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1691. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1692. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1693. if (vdev->tx_non_std_data_callback.func) {
  1694. qdf_nbuf_set_next(nbuf, NULL);
  1695. vdev->tx_non_std_data_callback.func(
  1696. vdev->tx_non_std_data_callback.ctxt,
  1697. nbuf, tx_status);
  1698. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1699. return;
  1700. } else {
  1701. dp_err_rl("callback func is null");
  1702. }
  1703. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1704. error:
  1705. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1706. qdf_nbuf_free(nbuf);
  1707. }
  1708. /**
  1709. * dp_tx_msdu_single_map() - do nbuf map
  1710. * @vdev: DP vdev handle
  1711. * @tx_desc: DP TX descriptor pointer
  1712. * @nbuf: skb pointer
  1713. *
  1714. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1715. * operation done in other component.
  1716. *
  1717. * Return: QDF_STATUS
  1718. */
  1719. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1720. struct dp_tx_desc_s *tx_desc,
  1721. qdf_nbuf_t nbuf)
  1722. {
  1723. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1724. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1725. nbuf,
  1726. QDF_DMA_TO_DEVICE,
  1727. nbuf->len);
  1728. else
  1729. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1730. QDF_DMA_TO_DEVICE);
  1731. }
  1732. #else
  1733. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1734. struct dp_vdev *vdev,
  1735. struct dp_tx_desc_s *tx_desc)
  1736. {
  1737. }
  1738. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1739. struct dp_tx_desc_s *tx_desc)
  1740. {
  1741. }
  1742. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1743. struct dp_tx_desc_s *tx_desc,
  1744. qdf_nbuf_t nbuf)
  1745. {
  1746. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1747. nbuf,
  1748. QDF_DMA_TO_DEVICE,
  1749. nbuf->len);
  1750. }
  1751. #endif
  1752. static inline
  1753. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1754. struct dp_tx_desc_s *tx_desc,
  1755. qdf_nbuf_t nbuf)
  1756. {
  1757. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1758. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1759. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1760. return 0;
  1761. return qdf_nbuf_mapped_paddr_get(nbuf);
  1762. }
  1763. static inline
  1764. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1765. {
  1766. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1767. desc->nbuf,
  1768. desc->dma_addr,
  1769. QDF_DMA_TO_DEVICE,
  1770. desc->length);
  1771. }
  1772. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1773. static inline
  1774. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1775. struct dp_tx_desc_s *tx_desc,
  1776. qdf_nbuf_t nbuf)
  1777. {
  1778. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1779. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1780. (void *)(nbuf->data + nbuf->len));
  1781. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1782. } else {
  1783. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1784. }
  1785. }
  1786. static inline
  1787. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1788. struct dp_tx_desc_s *desc)
  1789. {
  1790. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1791. return dp_tx_nbuf_unmap_regular(soc, desc);
  1792. }
  1793. #else
  1794. static inline
  1795. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1796. struct dp_tx_desc_s *tx_desc,
  1797. qdf_nbuf_t nbuf)
  1798. {
  1799. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1800. }
  1801. static inline
  1802. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1803. struct dp_tx_desc_s *desc)
  1804. {
  1805. return dp_tx_nbuf_unmap_regular(soc, desc);
  1806. }
  1807. #endif
  1808. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1809. static inline
  1810. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1811. {
  1812. dp_tx_nbuf_unmap(soc, desc);
  1813. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1814. }
  1815. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1816. {
  1817. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1818. dp_tx_nbuf_unmap(soc, desc);
  1819. }
  1820. #else
  1821. static inline
  1822. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1823. {
  1824. }
  1825. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1826. {
  1827. dp_tx_nbuf_unmap(soc, desc);
  1828. }
  1829. #endif
  1830. #ifdef MESH_MODE_SUPPORT
  1831. /**
  1832. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1833. * @soc: datapath SOC
  1834. * @vdev: datapath vdev
  1835. * @tx_desc: TX descriptor
  1836. *
  1837. * Return: None
  1838. */
  1839. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1840. struct dp_vdev *vdev,
  1841. struct dp_tx_desc_s *tx_desc)
  1842. {
  1843. if (qdf_unlikely(vdev->mesh_vdev))
  1844. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1845. }
  1846. /**
  1847. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1848. * @soc: dp_soc handle
  1849. * @tx_desc: TX descriptor
  1850. * @delayed_free: delay the nbuf free
  1851. *
  1852. * Return: nbuf to be freed late
  1853. */
  1854. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1855. struct dp_tx_desc_s *tx_desc,
  1856. bool delayed_free)
  1857. {
  1858. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1859. struct dp_vdev *vdev = NULL;
  1860. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1861. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1862. if (vdev)
  1863. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1864. if (delayed_free)
  1865. return nbuf;
  1866. qdf_nbuf_free(nbuf);
  1867. } else {
  1868. if (vdev && vdev->osif_tx_free_ext) {
  1869. vdev->osif_tx_free_ext((nbuf));
  1870. } else {
  1871. if (delayed_free)
  1872. return nbuf;
  1873. qdf_nbuf_free(nbuf);
  1874. }
  1875. }
  1876. if (vdev)
  1877. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1878. return NULL;
  1879. }
  1880. #else
  1881. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1882. struct dp_vdev *vdev,
  1883. struct dp_tx_desc_s *tx_desc)
  1884. {
  1885. }
  1886. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1887. struct dp_tx_desc_s *tx_desc,
  1888. bool delayed_free)
  1889. {
  1890. return NULL;
  1891. }
  1892. #endif
  1893. /**
  1894. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1895. * @vdev: DP vdev handle
  1896. * @nbuf: skb
  1897. *
  1898. * Return: 1 if frame needs to be dropped else 0
  1899. */
  1900. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1901. {
  1902. struct dp_pdev *pdev = NULL;
  1903. struct dp_ast_entry *src_ast_entry = NULL;
  1904. struct dp_ast_entry *dst_ast_entry = NULL;
  1905. struct dp_soc *soc = NULL;
  1906. qdf_assert(vdev);
  1907. pdev = vdev->pdev;
  1908. qdf_assert(pdev);
  1909. soc = pdev->soc;
  1910. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1911. (soc, dstmac, vdev->pdev->pdev_id);
  1912. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1913. (soc, srcmac, vdev->pdev->pdev_id);
  1914. if (dst_ast_entry && src_ast_entry) {
  1915. if (dst_ast_entry->peer_id ==
  1916. src_ast_entry->peer_id)
  1917. return 1;
  1918. }
  1919. return 0;
  1920. }
  1921. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1922. defined(WLAN_MCAST_MLO)
  1923. /* MLO peer id for reinject*/
  1924. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1925. /* MLO vdev id inc offset */
  1926. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1927. static inline void
  1928. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1929. {
  1930. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1931. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1932. qdf_atomic_inc(&soc->num_tx_exception);
  1933. }
  1934. }
  1935. static inline void
  1936. dp_tx_update_mcast_param(uint16_t peer_id,
  1937. uint16_t *htt_tcl_metadata,
  1938. struct dp_vdev *vdev,
  1939. struct dp_tx_msdu_info_s *msdu_info)
  1940. {
  1941. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1942. *htt_tcl_metadata = 0;
  1943. DP_TX_TCL_METADATA_TYPE_SET(
  1944. *htt_tcl_metadata,
  1945. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1946. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1947. msdu_info->gsn);
  1948. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1949. if (qdf_unlikely(vdev->nawds_enabled))
  1950. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1951. *htt_tcl_metadata, 1);
  1952. } else {
  1953. msdu_info->vdev_id = vdev->vdev_id;
  1954. }
  1955. }
  1956. #else
  1957. static inline void
  1958. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1959. {
  1960. }
  1961. static inline void
  1962. dp_tx_update_mcast_param(uint16_t peer_id,
  1963. uint16_t *htt_tcl_metadata,
  1964. struct dp_vdev *vdev,
  1965. struct dp_tx_msdu_info_s *msdu_info)
  1966. {
  1967. }
  1968. #endif
  1969. /**
  1970. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1971. * @vdev: DP vdev handle
  1972. * @nbuf: skb
  1973. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1974. * @meta_data: Metadata to the fw
  1975. * @tx_q: Tx queue to be used for this Tx frame
  1976. * @peer_id: peer_id of the peer in case of NAWDS frames
  1977. * @tx_exc_metadata: Handle that holds exception path metadata
  1978. *
  1979. * Return: NULL on success,
  1980. * nbuf when it fails to send
  1981. */
  1982. qdf_nbuf_t
  1983. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1984. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1985. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1986. {
  1987. struct dp_pdev *pdev = vdev->pdev;
  1988. struct dp_soc *soc = pdev->soc;
  1989. struct dp_tx_desc_s *tx_desc;
  1990. QDF_STATUS status;
  1991. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1992. uint16_t htt_tcl_metadata = 0;
  1993. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1994. uint8_t tid = msdu_info->tid;
  1995. struct cdp_tid_tx_stats *tid_stats = NULL;
  1996. qdf_dma_addr_t paddr;
  1997. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1998. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1999. msdu_info, tx_exc_metadata);
  2000. if (!tx_desc) {
  2001. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2002. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2003. drop_code = TX_DESC_ERR;
  2004. goto fail_return;
  2005. }
  2006. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2007. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2008. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2009. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2010. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2011. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2012. DP_TCL_METADATA_TYPE_PEER_BASED);
  2013. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2014. peer_id);
  2015. dp_tx_bypass_reinjection(soc, tx_desc);
  2016. } else
  2017. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2018. if (msdu_info->exception_fw)
  2019. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2020. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2021. !pdev->enhanced_stats_en);
  2022. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2023. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2024. if (!paddr) {
  2025. /* Handle failure */
  2026. dp_err("qdf_nbuf_map failed");
  2027. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2028. drop_code = TX_DMA_MAP_ERR;
  2029. goto release_desc;
  2030. }
  2031. tx_desc->dma_addr = paddr;
  2032. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2033. tx_desc->id, DP_TX_DESC_MAP);
  2034. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2035. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2036. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2037. htt_tcl_metadata,
  2038. tx_exc_metadata, msdu_info);
  2039. if (status != QDF_STATUS_SUCCESS) {
  2040. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2041. tx_desc, tx_q->ring_id);
  2042. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2043. tx_desc->id, DP_TX_DESC_UNMAP);
  2044. dp_tx_nbuf_unmap(soc, tx_desc);
  2045. drop_code = TX_HW_ENQUEUE;
  2046. goto release_desc;
  2047. }
  2048. return NULL;
  2049. release_desc:
  2050. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2051. fail_return:
  2052. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2053. tid_stats = &pdev->stats.tid_stats.
  2054. tid_tx_stats[tx_q->ring_id][tid];
  2055. tid_stats->swdrop_cnt[drop_code]++;
  2056. return nbuf;
  2057. }
  2058. /**
  2059. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2060. * @soc: Soc handle
  2061. * @desc: software Tx descriptor to be processed
  2062. * @delayed_free: defer freeing of nbuf
  2063. *
  2064. * Return: nbuf to be freed later
  2065. */
  2066. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2067. bool delayed_free)
  2068. {
  2069. qdf_nbuf_t nbuf = desc->nbuf;
  2070. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2071. /* nbuf already freed in vdev detach path */
  2072. if (!nbuf)
  2073. return NULL;
  2074. /* If it is TDLS mgmt, don't unmap or free the frame */
  2075. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2076. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2077. return NULL;
  2078. }
  2079. /* 0 : MSDU buffer, 1 : MLE */
  2080. if (desc->msdu_ext_desc) {
  2081. /* TSO free */
  2082. if (hal_tx_ext_desc_get_tso_enable(
  2083. desc->msdu_ext_desc->vaddr)) {
  2084. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2085. desc->id, DP_TX_COMP_MSDU_EXT);
  2086. dp_tx_tso_seg_history_add(soc,
  2087. desc->msdu_ext_desc->tso_desc,
  2088. desc->nbuf, desc->id, type);
  2089. /* unmap eash TSO seg before free the nbuf */
  2090. dp_tx_tso_unmap_segment(soc,
  2091. desc->msdu_ext_desc->tso_desc,
  2092. desc->msdu_ext_desc->
  2093. tso_num_desc);
  2094. goto nbuf_free;
  2095. }
  2096. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2097. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2098. qdf_dma_addr_t iova;
  2099. uint32_t frag_len;
  2100. uint32_t i;
  2101. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2102. QDF_DMA_TO_DEVICE,
  2103. qdf_nbuf_headlen(nbuf));
  2104. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2105. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2106. &iova,
  2107. &frag_len);
  2108. if (!iova || !frag_len)
  2109. break;
  2110. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2111. QDF_DMA_TO_DEVICE);
  2112. }
  2113. goto nbuf_free;
  2114. }
  2115. }
  2116. /* If it's ME frame, dont unmap the cloned nbuf's */
  2117. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2118. goto nbuf_free;
  2119. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2120. dp_tx_unmap(soc, desc);
  2121. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2122. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2123. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2124. return NULL;
  2125. nbuf_free:
  2126. if (delayed_free)
  2127. return nbuf;
  2128. qdf_nbuf_free(nbuf);
  2129. return NULL;
  2130. }
  2131. /**
  2132. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2133. * @soc: DP soc handle
  2134. * @nbuf: skb
  2135. * @msdu_info: MSDU info
  2136. *
  2137. * Return: None
  2138. */
  2139. static inline void
  2140. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2141. struct dp_tx_msdu_info_s *msdu_info)
  2142. {
  2143. uint32_t cur_idx;
  2144. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2145. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2146. qdf_nbuf_headlen(nbuf));
  2147. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2148. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2149. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2150. seg->frags[cur_idx].paddr_hi) << 32),
  2151. seg->frags[cur_idx].len,
  2152. QDF_DMA_TO_DEVICE);
  2153. }
  2154. /**
  2155. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2156. * @vdev: DP vdev handle
  2157. * @nbuf: skb
  2158. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2159. *
  2160. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2161. *
  2162. * Return: NULL on success,
  2163. * nbuf when it fails to send
  2164. */
  2165. #if QDF_LOCK_STATS
  2166. noinline
  2167. #else
  2168. #endif
  2169. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2170. struct dp_tx_msdu_info_s *msdu_info)
  2171. {
  2172. uint32_t i;
  2173. struct dp_pdev *pdev = vdev->pdev;
  2174. struct dp_soc *soc = pdev->soc;
  2175. struct dp_tx_desc_s *tx_desc;
  2176. bool is_cce_classified = false;
  2177. QDF_STATUS status;
  2178. uint16_t htt_tcl_metadata = 0;
  2179. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2180. struct cdp_tid_tx_stats *tid_stats = NULL;
  2181. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2182. if (msdu_info->frm_type == dp_tx_frm_me)
  2183. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2184. i = 0;
  2185. /* Print statement to track i and num_seg */
  2186. /*
  2187. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2188. * descriptors using information in msdu_info
  2189. */
  2190. while (i < msdu_info->num_seg) {
  2191. /*
  2192. * Setup Tx descriptor for an MSDU, and MSDU extension
  2193. * descriptor
  2194. */
  2195. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2196. tx_q->desc_pool_id);
  2197. if (!tx_desc) {
  2198. if (msdu_info->frm_type == dp_tx_frm_me) {
  2199. prep_desc_fail++;
  2200. dp_tx_me_free_buf(pdev,
  2201. (void *)(msdu_info->u.sg_info
  2202. .curr_seg->frags[0].vaddr));
  2203. if (prep_desc_fail == msdu_info->num_seg) {
  2204. /*
  2205. * Unmap is needed only if descriptor
  2206. * preparation failed for all segments.
  2207. */
  2208. qdf_nbuf_unmap(soc->osdev,
  2209. msdu_info->u.sg_info.
  2210. curr_seg->nbuf,
  2211. QDF_DMA_TO_DEVICE);
  2212. }
  2213. /*
  2214. * Free the nbuf for the current segment
  2215. * and make it point to the next in the list.
  2216. * For me, there are as many segments as there
  2217. * are no of clients.
  2218. */
  2219. qdf_nbuf_free(msdu_info->u.sg_info
  2220. .curr_seg->nbuf);
  2221. if (msdu_info->u.sg_info.curr_seg->next) {
  2222. msdu_info->u.sg_info.curr_seg =
  2223. msdu_info->u.sg_info
  2224. .curr_seg->next;
  2225. nbuf = msdu_info->u.sg_info
  2226. .curr_seg->nbuf;
  2227. }
  2228. i++;
  2229. continue;
  2230. }
  2231. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2232. dp_tx_tso_seg_history_add(
  2233. soc,
  2234. msdu_info->u.tso_info.curr_seg,
  2235. nbuf, 0, DP_TX_DESC_UNMAP);
  2236. dp_tx_tso_unmap_segment(soc,
  2237. msdu_info->u.tso_info.
  2238. curr_seg,
  2239. msdu_info->u.tso_info.
  2240. tso_num_seg_list);
  2241. if (msdu_info->u.tso_info.curr_seg->next) {
  2242. msdu_info->u.tso_info.curr_seg =
  2243. msdu_info->u.tso_info.curr_seg->next;
  2244. i++;
  2245. continue;
  2246. }
  2247. }
  2248. if (msdu_info->frm_type == dp_tx_frm_sg)
  2249. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2250. goto done;
  2251. }
  2252. if (msdu_info->frm_type == dp_tx_frm_me) {
  2253. tx_desc->msdu_ext_desc->me_buffer =
  2254. (struct dp_tx_me_buf_t *)msdu_info->
  2255. u.sg_info.curr_seg->frags[0].vaddr;
  2256. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2257. }
  2258. if (is_cce_classified)
  2259. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2260. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2261. if (msdu_info->exception_fw) {
  2262. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2263. }
  2264. dp_tx_is_hp_update_required(i, msdu_info);
  2265. /*
  2266. * For frames with multiple segments (TSO, ME), jump to next
  2267. * segment.
  2268. */
  2269. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2270. if (msdu_info->u.tso_info.curr_seg->next) {
  2271. msdu_info->u.tso_info.curr_seg =
  2272. msdu_info->u.tso_info.curr_seg->next;
  2273. /*
  2274. * If this is a jumbo nbuf, then increment the
  2275. * number of nbuf users for each additional
  2276. * segment of the msdu. This will ensure that
  2277. * the skb is freed only after receiving tx
  2278. * completion for all segments of an nbuf
  2279. */
  2280. qdf_nbuf_inc_users(nbuf);
  2281. /* Check with MCL if this is needed */
  2282. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2283. */
  2284. }
  2285. }
  2286. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2287. &htt_tcl_metadata,
  2288. vdev,
  2289. msdu_info);
  2290. /*
  2291. * Enqueue the Tx MSDU descriptor to HW for transmit
  2292. */
  2293. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2294. htt_tcl_metadata,
  2295. NULL, msdu_info);
  2296. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2297. if (status != QDF_STATUS_SUCCESS) {
  2298. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2299. tx_desc, tx_q->ring_id);
  2300. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2301. tid_stats = &pdev->stats.tid_stats.
  2302. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2303. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2304. if (msdu_info->frm_type == dp_tx_frm_me) {
  2305. hw_enq_fail++;
  2306. if (hw_enq_fail == msdu_info->num_seg) {
  2307. /*
  2308. * Unmap is needed only if enqueue
  2309. * failed for all segments.
  2310. */
  2311. qdf_nbuf_unmap(soc->osdev,
  2312. msdu_info->u.sg_info.
  2313. curr_seg->nbuf,
  2314. QDF_DMA_TO_DEVICE);
  2315. }
  2316. /*
  2317. * Free the nbuf for the current segment
  2318. * and make it point to the next in the list.
  2319. * For me, there are as many segments as there
  2320. * are no of clients.
  2321. */
  2322. qdf_nbuf_free(msdu_info->u.sg_info
  2323. .curr_seg->nbuf);
  2324. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2325. if (msdu_info->u.sg_info.curr_seg->next) {
  2326. msdu_info->u.sg_info.curr_seg =
  2327. msdu_info->u.sg_info
  2328. .curr_seg->next;
  2329. nbuf = msdu_info->u.sg_info
  2330. .curr_seg->nbuf;
  2331. } else
  2332. break;
  2333. i++;
  2334. continue;
  2335. }
  2336. /*
  2337. * For TSO frames, the nbuf users increment done for
  2338. * the current segment has to be reverted, since the
  2339. * hw enqueue for this segment failed
  2340. */
  2341. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2342. msdu_info->u.tso_info.curr_seg) {
  2343. /*
  2344. * unmap and free current,
  2345. * retransmit remaining segments
  2346. */
  2347. dp_tx_comp_free_buf(soc, tx_desc, false);
  2348. i++;
  2349. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2350. continue;
  2351. }
  2352. if (msdu_info->frm_type == dp_tx_frm_sg)
  2353. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2354. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2355. goto done;
  2356. }
  2357. /*
  2358. * TODO
  2359. * if tso_info structure can be modified to have curr_seg
  2360. * as first element, following 2 blocks of code (for TSO and SG)
  2361. * can be combined into 1
  2362. */
  2363. /*
  2364. * For Multicast-Unicast converted packets,
  2365. * each converted frame (for a client) is represented as
  2366. * 1 segment
  2367. */
  2368. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2369. (msdu_info->frm_type == dp_tx_frm_me)) {
  2370. if (msdu_info->u.sg_info.curr_seg->next) {
  2371. msdu_info->u.sg_info.curr_seg =
  2372. msdu_info->u.sg_info.curr_seg->next;
  2373. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2374. } else
  2375. break;
  2376. }
  2377. i++;
  2378. }
  2379. nbuf = NULL;
  2380. done:
  2381. return nbuf;
  2382. }
  2383. /**
  2384. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2385. * for SG frames
  2386. * @vdev: DP vdev handle
  2387. * @nbuf: skb
  2388. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2389. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2390. *
  2391. * Return: NULL on success,
  2392. * nbuf when it fails to send
  2393. */
  2394. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2395. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2396. {
  2397. uint32_t cur_frag, nr_frags, i;
  2398. qdf_dma_addr_t paddr;
  2399. struct dp_tx_sg_info_s *sg_info;
  2400. sg_info = &msdu_info->u.sg_info;
  2401. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2402. if (QDF_STATUS_SUCCESS !=
  2403. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2404. QDF_DMA_TO_DEVICE,
  2405. qdf_nbuf_headlen(nbuf))) {
  2406. dp_tx_err("dma map error");
  2407. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2408. qdf_nbuf_free(nbuf);
  2409. return NULL;
  2410. }
  2411. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2412. seg_info->frags[0].paddr_lo = paddr;
  2413. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2414. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2415. seg_info->frags[0].vaddr = (void *) nbuf;
  2416. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2417. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2418. nbuf, 0,
  2419. QDF_DMA_TO_DEVICE,
  2420. cur_frag)) {
  2421. dp_tx_err("frag dma map error");
  2422. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2423. goto map_err;
  2424. }
  2425. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2426. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2427. seg_info->frags[cur_frag + 1].paddr_hi =
  2428. ((uint64_t) paddr) >> 32;
  2429. seg_info->frags[cur_frag + 1].len =
  2430. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2431. }
  2432. seg_info->frag_cnt = (cur_frag + 1);
  2433. seg_info->total_len = qdf_nbuf_len(nbuf);
  2434. seg_info->next = NULL;
  2435. sg_info->curr_seg = seg_info;
  2436. msdu_info->frm_type = dp_tx_frm_sg;
  2437. msdu_info->num_seg = 1;
  2438. return nbuf;
  2439. map_err:
  2440. /* restore paddr into nbuf before calling unmap */
  2441. qdf_nbuf_mapped_paddr_set(nbuf,
  2442. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2443. ((uint64_t)
  2444. seg_info->frags[0].paddr_hi) << 32));
  2445. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2446. QDF_DMA_TO_DEVICE,
  2447. seg_info->frags[0].len);
  2448. for (i = 1; i <= cur_frag; i++) {
  2449. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2450. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2451. seg_info->frags[i].paddr_hi) << 32),
  2452. seg_info->frags[i].len,
  2453. QDF_DMA_TO_DEVICE);
  2454. }
  2455. qdf_nbuf_free(nbuf);
  2456. return NULL;
  2457. }
  2458. /**
  2459. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2460. * @vdev: DP vdev handle
  2461. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2462. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2463. *
  2464. * Return: NULL on failure,
  2465. * nbuf when extracted successfully
  2466. */
  2467. static
  2468. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2469. struct dp_tx_msdu_info_s *msdu_info,
  2470. uint16_t ppdu_cookie)
  2471. {
  2472. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2473. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2474. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2475. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2476. (msdu_info->meta_data[5], 1);
  2477. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2478. (msdu_info->meta_data[5], 1);
  2479. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2480. (msdu_info->meta_data[6], ppdu_cookie);
  2481. msdu_info->exception_fw = 1;
  2482. msdu_info->is_tx_sniffer = 1;
  2483. }
  2484. #ifdef MESH_MODE_SUPPORT
  2485. /**
  2486. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2487. and prepare msdu_info for mesh frames.
  2488. * @vdev: DP vdev handle
  2489. * @nbuf: skb
  2490. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2491. *
  2492. * Return: NULL on failure,
  2493. * nbuf when extracted successfully
  2494. */
  2495. static
  2496. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2497. struct dp_tx_msdu_info_s *msdu_info)
  2498. {
  2499. struct meta_hdr_s *mhdr;
  2500. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2501. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2502. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2503. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2504. msdu_info->exception_fw = 0;
  2505. goto remove_meta_hdr;
  2506. }
  2507. msdu_info->exception_fw = 1;
  2508. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2509. meta_data->host_tx_desc_pool = 1;
  2510. meta_data->update_peer_cache = 1;
  2511. meta_data->learning_frame = 1;
  2512. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2513. meta_data->power = mhdr->power;
  2514. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2515. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2516. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2517. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2518. meta_data->dyn_bw = 1;
  2519. meta_data->valid_pwr = 1;
  2520. meta_data->valid_mcs_mask = 1;
  2521. meta_data->valid_nss_mask = 1;
  2522. meta_data->valid_preamble_type = 1;
  2523. meta_data->valid_retries = 1;
  2524. meta_data->valid_bw_info = 1;
  2525. }
  2526. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2527. meta_data->encrypt_type = 0;
  2528. meta_data->valid_encrypt_type = 1;
  2529. meta_data->learning_frame = 0;
  2530. }
  2531. meta_data->valid_key_flags = 1;
  2532. meta_data->key_flags = (mhdr->keyix & 0x3);
  2533. remove_meta_hdr:
  2534. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2535. dp_tx_err("qdf_nbuf_pull_head failed");
  2536. qdf_nbuf_free(nbuf);
  2537. return NULL;
  2538. }
  2539. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2540. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2541. " tid %d to_fw %d",
  2542. msdu_info->meta_data[0],
  2543. msdu_info->meta_data[1],
  2544. msdu_info->meta_data[2],
  2545. msdu_info->meta_data[3],
  2546. msdu_info->meta_data[4],
  2547. msdu_info->meta_data[5],
  2548. msdu_info->tid, msdu_info->exception_fw);
  2549. return nbuf;
  2550. }
  2551. #else
  2552. static
  2553. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2554. struct dp_tx_msdu_info_s *msdu_info)
  2555. {
  2556. return nbuf;
  2557. }
  2558. #endif
  2559. /**
  2560. * dp_check_exc_metadata() - Checks if parameters are valid
  2561. * @tx_exc - holds all exception path parameters
  2562. *
  2563. * Returns true when all the parameters are valid else false
  2564. *
  2565. */
  2566. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2567. {
  2568. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2569. HTT_INVALID_TID);
  2570. bool invalid_encap_type =
  2571. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2572. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2573. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2574. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2575. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2576. tx_exc->ppdu_cookie == 0);
  2577. if (tx_exc->is_intrabss_fwd)
  2578. return true;
  2579. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2580. invalid_cookie) {
  2581. return false;
  2582. }
  2583. return true;
  2584. }
  2585. #ifdef ATH_SUPPORT_IQUE
  2586. /**
  2587. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2588. * @vdev: vdev handle
  2589. * @nbuf: skb
  2590. *
  2591. * Return: true on success,
  2592. * false on failure
  2593. */
  2594. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2595. {
  2596. qdf_ether_header_t *eh;
  2597. /* Mcast to Ucast Conversion*/
  2598. if (qdf_likely(!vdev->mcast_enhancement_en))
  2599. return true;
  2600. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2601. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2602. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2603. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2604. qdf_nbuf_set_next(nbuf, NULL);
  2605. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2606. qdf_nbuf_len(nbuf));
  2607. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2608. QDF_STATUS_SUCCESS) {
  2609. return false;
  2610. }
  2611. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2612. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2613. QDF_STATUS_SUCCESS) {
  2614. return false;
  2615. }
  2616. }
  2617. }
  2618. return true;
  2619. }
  2620. #else
  2621. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2622. {
  2623. return true;
  2624. }
  2625. #endif
  2626. /**
  2627. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2628. * @nbuf: qdf_nbuf_t
  2629. * @vdev: struct dp_vdev *
  2630. *
  2631. * Allow packet for processing only if it is for peer client which is
  2632. * connected with same vap. Drop packet if client is connected to
  2633. * different vap.
  2634. *
  2635. * Return: QDF_STATUS
  2636. */
  2637. static inline QDF_STATUS
  2638. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2639. {
  2640. struct dp_ast_entry *dst_ast_entry = NULL;
  2641. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2642. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2643. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2644. return QDF_STATUS_SUCCESS;
  2645. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2646. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2647. eh->ether_dhost,
  2648. vdev->vdev_id);
  2649. /* If there is no ast entry, return failure */
  2650. if (qdf_unlikely(!dst_ast_entry)) {
  2651. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2652. return QDF_STATUS_E_FAILURE;
  2653. }
  2654. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2655. return QDF_STATUS_SUCCESS;
  2656. }
  2657. /**
  2658. * dp_tx_nawds_handler() - NAWDS handler
  2659. *
  2660. * @soc: DP soc handle
  2661. * @vdev_id: id of DP vdev handle
  2662. * @msdu_info: msdu_info required to create HTT metadata
  2663. * @nbuf: skb
  2664. *
  2665. * This API transfers the multicast frames with the peer id
  2666. * on NAWDS enabled peer.
  2667. * Return: none
  2668. */
  2669. static inline
  2670. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2671. struct dp_tx_msdu_info_s *msdu_info,
  2672. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2673. {
  2674. struct dp_peer *peer = NULL;
  2675. qdf_nbuf_t nbuf_clone = NULL;
  2676. uint16_t peer_id = DP_INVALID_PEER;
  2677. struct dp_txrx_peer *txrx_peer;
  2678. /* This check avoids pkt forwarding which is entered
  2679. * in the ast table but still doesn't have valid peerid.
  2680. */
  2681. if (sa_peer_id == HTT_INVALID_PEER)
  2682. return;
  2683. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2684. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2685. txrx_peer = dp_get_txrx_peer(peer);
  2686. if (!txrx_peer)
  2687. continue;
  2688. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2689. peer_id = peer->peer_id;
  2690. if (!dp_peer_is_primary_link_peer(peer))
  2691. continue;
  2692. /* Multicast packets needs to be
  2693. * dropped in case of intra bss forwarding
  2694. */
  2695. if (sa_peer_id == txrx_peer->peer_id) {
  2696. dp_tx_debug("multicast packet");
  2697. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2698. tx.nawds_mcast_drop,
  2699. 1);
  2700. continue;
  2701. }
  2702. nbuf_clone = qdf_nbuf_clone(nbuf);
  2703. if (!nbuf_clone) {
  2704. QDF_TRACE(QDF_MODULE_ID_DP,
  2705. QDF_TRACE_LEVEL_ERROR,
  2706. FL("nbuf clone failed"));
  2707. break;
  2708. }
  2709. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2710. msdu_info, peer_id,
  2711. NULL);
  2712. if (nbuf_clone) {
  2713. dp_tx_debug("pkt send failed");
  2714. qdf_nbuf_free(nbuf_clone);
  2715. } else {
  2716. if (peer_id != DP_INVALID_PEER)
  2717. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2718. tx.nawds_mcast,
  2719. 1, qdf_nbuf_len(nbuf));
  2720. }
  2721. }
  2722. }
  2723. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2724. }
  2725. /**
  2726. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2727. * @soc: DP soc handle
  2728. * @vdev_id: id of DP vdev handle
  2729. * @nbuf: skb
  2730. * @tx_exc_metadata: Handle that holds exception path meta data
  2731. *
  2732. * Entry point for Core Tx layer (DP_TX) invoked from
  2733. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2734. *
  2735. * Return: NULL on success,
  2736. * nbuf when it fails to send
  2737. */
  2738. qdf_nbuf_t
  2739. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2740. qdf_nbuf_t nbuf,
  2741. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2742. {
  2743. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2744. qdf_ether_header_t *eh = NULL;
  2745. struct dp_tx_msdu_info_s msdu_info;
  2746. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2747. DP_MOD_ID_TX_EXCEPTION);
  2748. if (qdf_unlikely(!vdev))
  2749. goto fail;
  2750. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2751. if (!tx_exc_metadata)
  2752. goto fail;
  2753. msdu_info.tid = tx_exc_metadata->tid;
  2754. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2755. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2756. QDF_MAC_ADDR_REF(nbuf->data));
  2757. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2758. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2759. dp_tx_err("Invalid parameters in exception path");
  2760. goto fail;
  2761. }
  2762. /* for peer based metadata check if peer is valid */
  2763. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2764. struct dp_peer *peer = NULL;
  2765. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2766. tx_exc_metadata->peer_id,
  2767. DP_MOD_ID_TX_EXCEPTION);
  2768. if (qdf_unlikely(!peer)) {
  2769. DP_STATS_INC(vdev,
  2770. tx_i.dropped.invalid_peer_id_in_exc_path,
  2771. 1);
  2772. goto fail;
  2773. }
  2774. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2775. }
  2776. /* Basic sanity checks for unsupported packets */
  2777. /* MESH mode */
  2778. if (qdf_unlikely(vdev->mesh_vdev)) {
  2779. dp_tx_err("Mesh mode is not supported in exception path");
  2780. goto fail;
  2781. }
  2782. /*
  2783. * Classify the frame and call corresponding
  2784. * "prepare" function which extracts the segment (TSO)
  2785. * and fragmentation information (for TSO , SG, ME, or Raw)
  2786. * into MSDU_INFO structure which is later used to fill
  2787. * SW and HW descriptors.
  2788. */
  2789. if (qdf_nbuf_is_tso(nbuf)) {
  2790. dp_verbose_debug("TSO frame %pK", vdev);
  2791. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2792. qdf_nbuf_len(nbuf));
  2793. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2794. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2795. qdf_nbuf_len(nbuf));
  2796. goto fail;
  2797. }
  2798. goto send_multiple;
  2799. }
  2800. /* SG */
  2801. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2802. struct dp_tx_seg_info_s seg_info = {0};
  2803. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2804. if (!nbuf)
  2805. goto fail;
  2806. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2807. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2808. qdf_nbuf_len(nbuf));
  2809. goto send_multiple;
  2810. }
  2811. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2812. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2813. qdf_nbuf_len(nbuf));
  2814. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2815. tx_exc_metadata->ppdu_cookie);
  2816. }
  2817. /*
  2818. * Get HW Queue to use for this frame.
  2819. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2820. * dedicated for data and 1 for command.
  2821. * "queue_id" maps to one hardware ring.
  2822. * With each ring, we also associate a unique Tx descriptor pool
  2823. * to minimize lock contention for these resources.
  2824. */
  2825. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2826. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2827. if (qdf_unlikely(vdev->nawds_enabled)) {
  2828. /*
  2829. * This is a multicast packet
  2830. */
  2831. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2832. tx_exc_metadata->peer_id);
  2833. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2834. 1, qdf_nbuf_len(nbuf));
  2835. }
  2836. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2837. DP_INVALID_PEER, NULL);
  2838. } else {
  2839. /*
  2840. * Check exception descriptors
  2841. */
  2842. if (dp_tx_exception_limit_check(vdev))
  2843. goto fail;
  2844. /* Single linear frame */
  2845. /*
  2846. * If nbuf is a simple linear frame, use send_single function to
  2847. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2848. * SRNG. There is no need to setup a MSDU extension descriptor.
  2849. */
  2850. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2851. tx_exc_metadata->peer_id,
  2852. tx_exc_metadata);
  2853. }
  2854. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2855. return nbuf;
  2856. send_multiple:
  2857. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2858. fail:
  2859. if (vdev)
  2860. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2861. dp_verbose_debug("pkt send failed");
  2862. return nbuf;
  2863. }
  2864. /**
  2865. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2866. * in exception path in special case to avoid regular exception path chk.
  2867. * @soc: DP soc handle
  2868. * @vdev_id: id of DP vdev handle
  2869. * @nbuf: skb
  2870. * @tx_exc_metadata: Handle that holds exception path meta data
  2871. *
  2872. * Entry point for Core Tx layer (DP_TX) invoked from
  2873. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2874. *
  2875. * Return: NULL on success,
  2876. * nbuf when it fails to send
  2877. */
  2878. qdf_nbuf_t
  2879. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2880. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2881. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2882. {
  2883. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2884. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2885. DP_MOD_ID_TX_EXCEPTION);
  2886. if (qdf_unlikely(!vdev))
  2887. goto fail;
  2888. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2889. == QDF_STATUS_E_FAILURE)) {
  2890. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2891. goto fail;
  2892. }
  2893. /* Unref count as it will agin be taken inside dp_tx_exception */
  2894. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2895. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2896. fail:
  2897. if (vdev)
  2898. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2899. dp_verbose_debug("pkt send failed");
  2900. return nbuf;
  2901. }
  2902. /**
  2903. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2904. * @soc: DP soc handle
  2905. * @vdev_id: DP vdev handle
  2906. * @nbuf: skb
  2907. *
  2908. * Entry point for Core Tx layer (DP_TX) invoked from
  2909. * hard_start_xmit in OSIF/HDD
  2910. *
  2911. * Return: NULL on success,
  2912. * nbuf when it fails to send
  2913. */
  2914. #ifdef MESH_MODE_SUPPORT
  2915. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2916. qdf_nbuf_t nbuf)
  2917. {
  2918. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2919. struct meta_hdr_s *mhdr;
  2920. qdf_nbuf_t nbuf_mesh = NULL;
  2921. qdf_nbuf_t nbuf_clone = NULL;
  2922. struct dp_vdev *vdev;
  2923. uint8_t no_enc_frame = 0;
  2924. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2925. if (!nbuf_mesh) {
  2926. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2927. "qdf_nbuf_unshare failed");
  2928. return nbuf;
  2929. }
  2930. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2931. if (!vdev) {
  2932. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2933. "vdev is NULL for vdev_id %d", vdev_id);
  2934. return nbuf;
  2935. }
  2936. nbuf = nbuf_mesh;
  2937. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2938. if ((vdev->sec_type != cdp_sec_type_none) &&
  2939. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2940. no_enc_frame = 1;
  2941. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2942. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2943. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2944. !no_enc_frame) {
  2945. nbuf_clone = qdf_nbuf_clone(nbuf);
  2946. if (!nbuf_clone) {
  2947. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2948. "qdf_nbuf_clone failed");
  2949. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2950. return nbuf;
  2951. }
  2952. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2953. }
  2954. if (nbuf_clone) {
  2955. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2956. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2957. } else {
  2958. qdf_nbuf_free(nbuf_clone);
  2959. }
  2960. }
  2961. if (no_enc_frame)
  2962. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2963. else
  2964. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2965. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2966. if ((!nbuf) && no_enc_frame) {
  2967. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2968. }
  2969. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2970. return nbuf;
  2971. }
  2972. #else
  2973. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2974. qdf_nbuf_t nbuf)
  2975. {
  2976. return dp_tx_send(soc, vdev_id, nbuf);
  2977. }
  2978. #endif
  2979. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2980. static inline
  2981. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2982. {
  2983. if (nbuf) {
  2984. qdf_prefetch(&nbuf->len);
  2985. qdf_prefetch(&nbuf->data);
  2986. }
  2987. }
  2988. #else
  2989. static inline
  2990. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2991. {
  2992. }
  2993. #endif
  2994. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2995. /*
  2996. * dp_tx_drop() - Drop the frame on a given VAP
  2997. * @soc: DP soc handle
  2998. * @vdev_id: id of DP vdev handle
  2999. * @nbuf: skb
  3000. *
  3001. * Drop all the incoming packets
  3002. *
  3003. * Return: nbuf
  3004. *
  3005. */
  3006. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3007. qdf_nbuf_t nbuf)
  3008. {
  3009. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3010. struct dp_vdev *vdev = NULL;
  3011. vdev = soc->vdev_id_map[vdev_id];
  3012. if (qdf_unlikely(!vdev))
  3013. return nbuf;
  3014. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3015. return nbuf;
  3016. }
  3017. /*
  3018. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3019. * @soc: DP soc handle
  3020. * @vdev_id: id of DP vdev handle
  3021. * @nbuf: skb
  3022. * @tx_exc_metadata: Handle that holds exception path meta data
  3023. *
  3024. * Drop all the incoming packets
  3025. *
  3026. * Return: nbuf
  3027. *
  3028. */
  3029. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3030. qdf_nbuf_t nbuf,
  3031. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3032. {
  3033. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3034. }
  3035. #endif
  3036. /*
  3037. * dp_tx_send() - Transmit a frame on a given VAP
  3038. * @soc: DP soc handle
  3039. * @vdev_id: id of DP vdev handle
  3040. * @nbuf: skb
  3041. *
  3042. * Entry point for Core Tx layer (DP_TX) invoked from
  3043. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3044. * cases
  3045. *
  3046. * Return: NULL on success,
  3047. * nbuf when it fails to send
  3048. */
  3049. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3050. qdf_nbuf_t nbuf)
  3051. {
  3052. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3053. uint16_t peer_id = HTT_INVALID_PEER;
  3054. /*
  3055. * doing a memzero is causing additional function call overhead
  3056. * so doing static stack clearing
  3057. */
  3058. struct dp_tx_msdu_info_s msdu_info = {0};
  3059. struct dp_vdev *vdev = NULL;
  3060. qdf_nbuf_t end_nbuf = NULL;
  3061. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3062. return nbuf;
  3063. /*
  3064. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3065. * this in per packet path.
  3066. *
  3067. * As in this path vdev memory is already protected with netdev
  3068. * tx lock
  3069. */
  3070. vdev = soc->vdev_id_map[vdev_id];
  3071. if (qdf_unlikely(!vdev))
  3072. return nbuf;
  3073. /*
  3074. * Set Default Host TID value to invalid TID
  3075. * (TID override disabled)
  3076. */
  3077. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3078. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3079. if (qdf_unlikely(vdev->mesh_vdev)) {
  3080. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3081. &msdu_info);
  3082. if (!nbuf_mesh) {
  3083. dp_verbose_debug("Extracting mesh metadata failed");
  3084. return nbuf;
  3085. }
  3086. nbuf = nbuf_mesh;
  3087. }
  3088. /*
  3089. * Get HW Queue to use for this frame.
  3090. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3091. * dedicated for data and 1 for command.
  3092. * "queue_id" maps to one hardware ring.
  3093. * With each ring, we also associate a unique Tx descriptor pool
  3094. * to minimize lock contention for these resources.
  3095. */
  3096. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3097. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3098. 1);
  3099. /*
  3100. * TCL H/W supports 2 DSCP-TID mapping tables.
  3101. * Table 1 - Default DSCP-TID mapping table
  3102. * Table 2 - 1 DSCP-TID override table
  3103. *
  3104. * If we need a different DSCP-TID mapping for this vap,
  3105. * call tid_classify to extract DSCP/ToS from frame and
  3106. * map to a TID and store in msdu_info. This is later used
  3107. * to fill in TCL Input descriptor (per-packet TID override).
  3108. */
  3109. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3110. /*
  3111. * Classify the frame and call corresponding
  3112. * "prepare" function which extracts the segment (TSO)
  3113. * and fragmentation information (for TSO , SG, ME, or Raw)
  3114. * into MSDU_INFO structure which is later used to fill
  3115. * SW and HW descriptors.
  3116. */
  3117. if (qdf_nbuf_is_tso(nbuf)) {
  3118. dp_verbose_debug("TSO frame %pK", vdev);
  3119. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3120. qdf_nbuf_len(nbuf));
  3121. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3122. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3123. qdf_nbuf_len(nbuf));
  3124. return nbuf;
  3125. }
  3126. goto send_multiple;
  3127. }
  3128. /* SG */
  3129. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3130. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3131. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3132. return nbuf;
  3133. } else {
  3134. struct dp_tx_seg_info_s seg_info = {0};
  3135. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3136. &msdu_info);
  3137. if (!nbuf)
  3138. return NULL;
  3139. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3140. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3141. qdf_nbuf_len(nbuf));
  3142. goto send_multiple;
  3143. }
  3144. }
  3145. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3146. return NULL;
  3147. /* RAW */
  3148. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3149. struct dp_tx_seg_info_s seg_info = {0};
  3150. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3151. if (!nbuf)
  3152. return NULL;
  3153. dp_verbose_debug("Raw frame %pK", vdev);
  3154. goto send_multiple;
  3155. }
  3156. if (qdf_unlikely(vdev->nawds_enabled)) {
  3157. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3158. qdf_nbuf_data(nbuf);
  3159. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3160. uint16_t sa_peer_id = DP_INVALID_PEER;
  3161. if (!soc->ast_offload_support) {
  3162. struct dp_ast_entry *ast_entry = NULL;
  3163. qdf_spin_lock_bh(&soc->ast_lock);
  3164. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3165. (soc,
  3166. (uint8_t *)(eh->ether_shost),
  3167. vdev->pdev->pdev_id);
  3168. if (ast_entry)
  3169. sa_peer_id = ast_entry->peer_id;
  3170. qdf_spin_unlock_bh(&soc->ast_lock);
  3171. }
  3172. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3173. sa_peer_id);
  3174. }
  3175. peer_id = DP_INVALID_PEER;
  3176. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3177. 1, qdf_nbuf_len(nbuf));
  3178. }
  3179. /* Single linear frame */
  3180. /*
  3181. * If nbuf is a simple linear frame, use send_single function to
  3182. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3183. * SRNG. There is no need to setup a MSDU extension descriptor.
  3184. */
  3185. dp_tx_prefetch_nbuf_data(nbuf);
  3186. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3187. peer_id, end_nbuf);
  3188. return nbuf;
  3189. send_multiple:
  3190. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3191. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3192. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3193. return nbuf;
  3194. }
  3195. /**
  3196. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3197. * case to vaoid check in perpkt path.
  3198. * @soc: DP soc handle
  3199. * @vdev_id: id of DP vdev handle
  3200. * @nbuf: skb
  3201. *
  3202. * Entry point for Core Tx layer (DP_TX) invoked from
  3203. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3204. * with special condition to avoid per pkt check in dp_tx_send
  3205. *
  3206. * Return: NULL on success,
  3207. * nbuf when it fails to send
  3208. */
  3209. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3210. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3211. {
  3212. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3213. struct dp_vdev *vdev = NULL;
  3214. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3215. return nbuf;
  3216. /*
  3217. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3218. * this in per packet path.
  3219. *
  3220. * As in this path vdev memory is already protected with netdev
  3221. * tx lock
  3222. */
  3223. vdev = soc->vdev_id_map[vdev_id];
  3224. if (qdf_unlikely(!vdev))
  3225. return nbuf;
  3226. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3227. == QDF_STATUS_E_FAILURE)) {
  3228. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3229. return nbuf;
  3230. }
  3231. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3232. }
  3233. #ifdef UMAC_SUPPORT_PROXY_ARP
  3234. /**
  3235. * dp_tx_proxy_arp() - Tx proxy arp handler
  3236. * @vdev: datapath vdev handle
  3237. * @buf: sk buffer
  3238. *
  3239. * Return: status
  3240. */
  3241. static inline
  3242. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3243. {
  3244. if (vdev->osif_proxy_arp)
  3245. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3246. /*
  3247. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3248. * osif_proxy_arp has a valid function pointer assigned
  3249. * to it
  3250. */
  3251. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3252. return QDF_STATUS_NOT_INITIALIZED;
  3253. }
  3254. #else
  3255. /**
  3256. * dp_tx_proxy_arp() - Tx proxy arp handler
  3257. * @vdev: datapath vdev handle
  3258. * @buf: sk buffer
  3259. *
  3260. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3261. * is not defined.
  3262. *
  3263. * Return: status
  3264. */
  3265. static inline
  3266. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3267. {
  3268. return QDF_STATUS_SUCCESS;
  3269. }
  3270. #endif
  3271. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3272. #ifdef WLAN_MCAST_MLO
  3273. static bool
  3274. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3275. struct dp_tx_desc_s *tx_desc,
  3276. qdf_nbuf_t nbuf,
  3277. uint8_t reinject_reason)
  3278. {
  3279. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3280. if (soc->arch_ops.dp_tx_mcast_handler)
  3281. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3282. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3283. return true;
  3284. }
  3285. return false;
  3286. }
  3287. #else /* WLAN_MCAST_MLO */
  3288. static inline bool
  3289. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3290. struct dp_tx_desc_s *tx_desc,
  3291. qdf_nbuf_t nbuf,
  3292. uint8_t reinject_reason)
  3293. {
  3294. return false;
  3295. }
  3296. #endif /* WLAN_MCAST_MLO */
  3297. #else
  3298. static inline bool
  3299. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3300. struct dp_tx_desc_s *tx_desc,
  3301. qdf_nbuf_t nbuf,
  3302. uint8_t reinject_reason)
  3303. {
  3304. return false;
  3305. }
  3306. #endif
  3307. /**
  3308. * dp_tx_reinject_handler() - Tx Reinject Handler
  3309. * @soc: datapath soc handle
  3310. * @vdev: datapath vdev handle
  3311. * @tx_desc: software descriptor head pointer
  3312. * @status : Tx completion status from HTT descriptor
  3313. * @reinject_reason : reinject reason from HTT descriptor
  3314. *
  3315. * This function reinjects frames back to Target.
  3316. * Todo - Host queue needs to be added
  3317. *
  3318. * Return: none
  3319. */
  3320. void dp_tx_reinject_handler(struct dp_soc *soc,
  3321. struct dp_vdev *vdev,
  3322. struct dp_tx_desc_s *tx_desc,
  3323. uint8_t *status,
  3324. uint8_t reinject_reason)
  3325. {
  3326. struct dp_peer *peer = NULL;
  3327. uint32_t peer_id = HTT_INVALID_PEER;
  3328. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3329. qdf_nbuf_t nbuf_copy = NULL;
  3330. struct dp_tx_msdu_info_s msdu_info;
  3331. #ifdef WDS_VENDOR_EXTENSION
  3332. int is_mcast = 0, is_ucast = 0;
  3333. int num_peers_3addr = 0;
  3334. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3335. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3336. #endif
  3337. struct dp_txrx_peer *txrx_peer;
  3338. qdf_assert(vdev);
  3339. dp_tx_debug("Tx reinject path");
  3340. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3341. qdf_nbuf_len(tx_desc->nbuf));
  3342. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3343. return;
  3344. #ifdef WDS_VENDOR_EXTENSION
  3345. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3346. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3347. } else {
  3348. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3349. }
  3350. is_ucast = !is_mcast;
  3351. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3352. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3353. txrx_peer = dp_get_txrx_peer(peer);
  3354. if (!txrx_peer || txrx_peer->bss_peer)
  3355. continue;
  3356. /* Detect wds peers that use 3-addr framing for mcast.
  3357. * if there are any, the bss_peer is used to send the
  3358. * the mcast frame using 3-addr format. all wds enabled
  3359. * peers that use 4-addr framing for mcast frames will
  3360. * be duplicated and sent as 4-addr frames below.
  3361. */
  3362. if (!txrx_peer->wds_enabled ||
  3363. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3364. num_peers_3addr = 1;
  3365. break;
  3366. }
  3367. }
  3368. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3369. #endif
  3370. if (qdf_unlikely(vdev->mesh_vdev)) {
  3371. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3372. } else {
  3373. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3374. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3375. txrx_peer = dp_get_txrx_peer(peer);
  3376. if (!txrx_peer)
  3377. continue;
  3378. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3379. #ifdef WDS_VENDOR_EXTENSION
  3380. /*
  3381. * . if 3-addr STA, then send on BSS Peer
  3382. * . if Peer WDS enabled and accept 4-addr mcast,
  3383. * send mcast on that peer only
  3384. * . if Peer WDS enabled and accept 4-addr ucast,
  3385. * send ucast on that peer only
  3386. */
  3387. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3388. (txrx_peer->wds_enabled &&
  3389. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3390. (is_ucast &&
  3391. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3392. #else
  3393. (txrx_peer->bss_peer &&
  3394. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3395. #endif
  3396. peer_id = DP_INVALID_PEER;
  3397. nbuf_copy = qdf_nbuf_copy(nbuf);
  3398. if (!nbuf_copy) {
  3399. dp_tx_debug("nbuf copy failed");
  3400. break;
  3401. }
  3402. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3403. dp_tx_get_queue(vdev, nbuf,
  3404. &msdu_info.tx_queue);
  3405. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3406. nbuf_copy,
  3407. &msdu_info,
  3408. peer_id,
  3409. NULL);
  3410. if (nbuf_copy) {
  3411. dp_tx_debug("pkt send failed");
  3412. qdf_nbuf_free(nbuf_copy);
  3413. }
  3414. }
  3415. }
  3416. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3417. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3418. QDF_DMA_TO_DEVICE, nbuf->len);
  3419. qdf_nbuf_free(nbuf);
  3420. }
  3421. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3422. }
  3423. /**
  3424. * dp_tx_inspect_handler() - Tx Inspect Handler
  3425. * @soc: datapath soc handle
  3426. * @vdev: datapath vdev handle
  3427. * @tx_desc: software descriptor head pointer
  3428. * @status : Tx completion status from HTT descriptor
  3429. *
  3430. * Handles Tx frames sent back to Host for inspection
  3431. * (ProxyARP)
  3432. *
  3433. * Return: none
  3434. */
  3435. void dp_tx_inspect_handler(struct dp_soc *soc,
  3436. struct dp_vdev *vdev,
  3437. struct dp_tx_desc_s *tx_desc,
  3438. uint8_t *status)
  3439. {
  3440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3441. "%s Tx inspect path",
  3442. __func__);
  3443. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3444. qdf_nbuf_len(tx_desc->nbuf));
  3445. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3446. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3447. }
  3448. #ifdef MESH_MODE_SUPPORT
  3449. /**
  3450. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3451. * in mesh meta header
  3452. * @tx_desc: software descriptor head pointer
  3453. * @ts: pointer to tx completion stats
  3454. * Return: none
  3455. */
  3456. static
  3457. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3458. struct hal_tx_completion_status *ts)
  3459. {
  3460. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3461. if (!tx_desc->msdu_ext_desc) {
  3462. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3463. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3464. "netbuf %pK offset %d",
  3465. netbuf, tx_desc->pkt_offset);
  3466. return;
  3467. }
  3468. }
  3469. }
  3470. #else
  3471. static
  3472. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3473. struct hal_tx_completion_status *ts)
  3474. {
  3475. }
  3476. #endif
  3477. #ifdef CONFIG_SAWF
  3478. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3479. struct dp_vdev *vdev,
  3480. struct dp_txrx_peer *txrx_peer,
  3481. struct dp_tx_desc_s *tx_desc,
  3482. struct hal_tx_completion_status *ts,
  3483. uint8_t tid)
  3484. {
  3485. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3486. ts, tid);
  3487. }
  3488. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3489. uint32_t nw_delay,
  3490. uint32_t sw_delay,
  3491. uint32_t hw_delay)
  3492. {
  3493. dp_peer_tid_delay_avg(tx_delay,
  3494. nw_delay,
  3495. sw_delay,
  3496. hw_delay);
  3497. }
  3498. #else
  3499. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3500. struct dp_vdev *vdev,
  3501. struct dp_txrx_peer *txrx_peer,
  3502. struct dp_tx_desc_s *tx_desc,
  3503. struct hal_tx_completion_status *ts,
  3504. uint8_t tid)
  3505. {
  3506. }
  3507. static inline void
  3508. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3509. uint32_t nw_delay, uint32_t sw_delay,
  3510. uint32_t hw_delay)
  3511. {
  3512. }
  3513. #endif
  3514. #ifdef QCA_PEER_EXT_STATS
  3515. #ifdef WLAN_CONFIG_TX_DELAY
  3516. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3517. struct dp_tx_desc_s *tx_desc,
  3518. struct hal_tx_completion_status *ts,
  3519. struct dp_vdev *vdev)
  3520. {
  3521. struct dp_soc *soc = vdev->pdev->soc;
  3522. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3523. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3524. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3525. if (!ts->valid)
  3526. return;
  3527. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3528. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3529. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3530. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3531. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3532. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3533. &fwhw_transmit_delay))
  3534. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3535. fwhw_transmit_delay);
  3536. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3537. fwhw_transmit_delay);
  3538. }
  3539. #else
  3540. /*
  3541. * dp_tx_compute_tid_delay() - Compute per TID delay
  3542. * @stats: Per TID delay stats
  3543. * @tx_desc: Software Tx descriptor
  3544. * @ts: Tx completion status
  3545. * @vdev: vdev
  3546. *
  3547. * Compute the software enqueue and hw enqueue delays and
  3548. * update the respective histograms
  3549. *
  3550. * Return: void
  3551. */
  3552. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3553. struct dp_tx_desc_s *tx_desc,
  3554. struct hal_tx_completion_status *ts,
  3555. struct dp_vdev *vdev)
  3556. {
  3557. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3558. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3559. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3560. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3561. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3562. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3563. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3564. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3565. timestamp_hw_enqueue);
  3566. /*
  3567. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3568. */
  3569. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3570. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3571. }
  3572. #endif
  3573. /*
  3574. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3575. * @txrx_peer: DP peer context
  3576. * @tx_desc: Tx software descriptor
  3577. * @tid: Transmission ID
  3578. * @ring_id: Rx CPU context ID/CPU_ID
  3579. *
  3580. * Update the peer extended stats. These are enhanced other
  3581. * delay stats per msdu level.
  3582. *
  3583. * Return: void
  3584. */
  3585. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3586. struct dp_tx_desc_s *tx_desc,
  3587. struct hal_tx_completion_status *ts,
  3588. uint8_t ring_id)
  3589. {
  3590. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3591. struct dp_soc *soc = NULL;
  3592. struct dp_peer_delay_stats *delay_stats = NULL;
  3593. uint8_t tid;
  3594. soc = pdev->soc;
  3595. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3596. return;
  3597. tid = ts->tid;
  3598. delay_stats = txrx_peer->delay_stats;
  3599. qdf_assert(delay_stats);
  3600. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3601. /*
  3602. * For non-TID packets use the TID 9
  3603. */
  3604. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3605. tid = CDP_MAX_DATA_TIDS - 1;
  3606. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3607. tx_desc, ts, txrx_peer->vdev);
  3608. }
  3609. #else
  3610. static inline
  3611. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3612. struct dp_tx_desc_s *tx_desc,
  3613. struct hal_tx_completion_status *ts,
  3614. uint8_t ring_id)
  3615. {
  3616. }
  3617. #endif
  3618. #ifdef HW_TX_DELAY_STATS_ENABLE
  3619. /**
  3620. * dp_update_tx_delay_stats() - update the delay stats
  3621. * @vdev: vdev handle
  3622. * @delay: delay in ms or us based on the flag delay_in_us
  3623. * @tid: tid value
  3624. * @mode: type of tx delay mode
  3625. * @ring id: ring number
  3626. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3627. *
  3628. * Return: none
  3629. */
  3630. static inline
  3631. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3632. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3633. {
  3634. struct cdp_tid_tx_stats *tstats =
  3635. &vdev->stats.tid_tx_stats[ring_id][tid];
  3636. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3637. delay_in_us);
  3638. }
  3639. #else
  3640. static inline
  3641. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3642. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3643. {
  3644. struct cdp_tid_tx_stats *tstats =
  3645. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3646. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3647. delay_in_us);
  3648. }
  3649. #endif
  3650. /**
  3651. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3652. * to pass in correct fields
  3653. *
  3654. * @vdev: pdev handle
  3655. * @tx_desc: tx descriptor
  3656. * @tid: tid value
  3657. * @ring_id: TCL or WBM ring number for transmit path
  3658. * Return: none
  3659. */
  3660. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3661. uint8_t tid, uint8_t ring_id)
  3662. {
  3663. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3664. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3665. uint32_t fwhw_transmit_delay_us;
  3666. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3667. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3668. return;
  3669. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3670. fwhw_transmit_delay_us =
  3671. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3672. qdf_ktime_to_us(tx_desc->timestamp);
  3673. /*
  3674. * Delay between packet enqueued to HW and Tx completion in us
  3675. */
  3676. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3677. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3678. ring_id, true);
  3679. /*
  3680. * For MCL, only enqueue to completion delay is required
  3681. * so return if the vdev flag is enabled.
  3682. */
  3683. return;
  3684. }
  3685. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3686. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3687. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3688. timestamp_hw_enqueue);
  3689. /*
  3690. * Delay between packet enqueued to HW and Tx completion in ms
  3691. */
  3692. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3693. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3694. false);
  3695. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3696. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3697. interframe_delay = (uint32_t)(timestamp_ingress -
  3698. vdev->prev_tx_enq_tstamp);
  3699. /*
  3700. * Delay in software enqueue
  3701. */
  3702. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3703. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3704. false);
  3705. /*
  3706. * Update interframe delay stats calculated at hardstart receive point.
  3707. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3708. * interframe delay will not be calculate correctly for 1st frame.
  3709. * On the other side, this will help in avoiding extra per packet check
  3710. * of !vdev->prev_tx_enq_tstamp.
  3711. */
  3712. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3713. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3714. false);
  3715. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3716. }
  3717. #ifdef DISABLE_DP_STATS
  3718. static
  3719. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3720. struct dp_txrx_peer *txrx_peer)
  3721. {
  3722. }
  3723. #else
  3724. static inline void
  3725. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3726. {
  3727. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3728. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3729. if (subtype != QDF_PROTO_INVALID)
  3730. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3731. 1);
  3732. }
  3733. #endif
  3734. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3735. #ifdef DP_PEER_EXTENDED_API
  3736. static inline uint8_t
  3737. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3738. {
  3739. return txrx_peer->mpdu_retry_threshold;
  3740. }
  3741. #else
  3742. static inline uint8_t
  3743. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3744. {
  3745. return 0;
  3746. }
  3747. #endif
  3748. /**
  3749. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3750. *
  3751. * @ts: Tx compltion status
  3752. * @txrx_peer: datapath txrx_peer handle
  3753. *
  3754. * Return: void
  3755. */
  3756. static inline void
  3757. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3758. struct dp_txrx_peer *txrx_peer)
  3759. {
  3760. uint8_t mcs, pkt_type, dst_mcs_idx;
  3761. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3762. mcs = ts->mcs;
  3763. pkt_type = ts->pkt_type;
  3764. /* do HW to SW pkt type conversion */
  3765. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3766. hal_2_dp_pkt_type_map[pkt_type]);
  3767. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3768. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3769. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3770. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3771. 1);
  3772. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3773. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3774. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3775. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3776. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3777. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3778. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3779. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3780. if (ts->first_msdu) {
  3781. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3782. ts->transmit_cnt > 1);
  3783. if (!retry_threshold)
  3784. return;
  3785. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3786. qdf_do_div(ts->transmit_cnt,
  3787. retry_threshold),
  3788. ts->transmit_cnt > retry_threshold);
  3789. }
  3790. }
  3791. #else
  3792. static inline void
  3793. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3794. struct dp_txrx_peer *txrx_peer)
  3795. {
  3796. }
  3797. #endif
  3798. /**
  3799. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3800. * per wbm ring
  3801. *
  3802. * @tx_desc: software descriptor head pointer
  3803. * @ts: Tx completion status
  3804. * @peer: peer handle
  3805. * @ring_id: ring number
  3806. *
  3807. * Return: None
  3808. */
  3809. static inline void
  3810. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3811. struct hal_tx_completion_status *ts,
  3812. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3813. {
  3814. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3815. uint8_t tid = ts->tid;
  3816. uint32_t length;
  3817. struct cdp_tid_tx_stats *tid_stats;
  3818. if (!pdev)
  3819. return;
  3820. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3821. tid = CDP_MAX_DATA_TIDS - 1;
  3822. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3823. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3824. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3825. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3826. return;
  3827. }
  3828. length = qdf_nbuf_len(tx_desc->nbuf);
  3829. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3830. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3831. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3832. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3833. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3834. tid_stats->tqm_status_cnt[ts->status]++;
  3835. }
  3836. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3837. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3838. ts->transmit_cnt > 1);
  3839. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3840. 1, ts->transmit_cnt > 2);
  3841. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3842. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3843. ts->msdu_part_of_amsdu);
  3844. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3845. !ts->msdu_part_of_amsdu);
  3846. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3847. qdf_system_ticks();
  3848. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3849. return;
  3850. }
  3851. /*
  3852. * tx_failed is ideally supposed to be updated from HTT ppdu
  3853. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3854. * hw limitation there are no completions for failed cases.
  3855. * Hence updating tx_failed from data path. Please note that
  3856. * if tx_failed is fixed to be from ppdu, then this has to be
  3857. * removed
  3858. */
  3859. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3860. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3861. ts->transmit_cnt > DP_RETRY_COUNT);
  3862. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3863. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3864. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3865. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3866. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3867. length);
  3868. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3869. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3870. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3871. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3872. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3873. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3874. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3875. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3876. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3877. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3878. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3879. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3880. tx.dropped.fw_rem_queue_disable, 1);
  3881. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3882. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3883. tx.dropped.fw_rem_no_match, 1);
  3884. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3885. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3886. tx.dropped.drop_threshold, 1);
  3887. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3888. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3889. tx.dropped.drop_link_desc_na, 1);
  3890. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3891. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3892. tx.dropped.invalid_drop, 1);
  3893. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3894. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3895. tx.dropped.mcast_vdev_drop, 1);
  3896. } else {
  3897. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3898. }
  3899. }
  3900. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3901. /**
  3902. * dp_tx_flow_pool_lock() - take flow pool lock
  3903. * @soc: core txrx main context
  3904. * @tx_desc: tx desc
  3905. *
  3906. * Return: None
  3907. */
  3908. static inline
  3909. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3910. struct dp_tx_desc_s *tx_desc)
  3911. {
  3912. struct dp_tx_desc_pool_s *pool;
  3913. uint8_t desc_pool_id;
  3914. desc_pool_id = tx_desc->pool_id;
  3915. pool = &soc->tx_desc[desc_pool_id];
  3916. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3917. }
  3918. /**
  3919. * dp_tx_flow_pool_unlock() - release flow pool lock
  3920. * @soc: core txrx main context
  3921. * @tx_desc: tx desc
  3922. *
  3923. * Return: None
  3924. */
  3925. static inline
  3926. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3927. struct dp_tx_desc_s *tx_desc)
  3928. {
  3929. struct dp_tx_desc_pool_s *pool;
  3930. uint8_t desc_pool_id;
  3931. desc_pool_id = tx_desc->pool_id;
  3932. pool = &soc->tx_desc[desc_pool_id];
  3933. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3934. }
  3935. #else
  3936. static inline
  3937. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3938. {
  3939. }
  3940. static inline
  3941. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3942. {
  3943. }
  3944. #endif
  3945. /**
  3946. * dp_tx_notify_completion() - Notify tx completion for this desc
  3947. * @soc: core txrx main context
  3948. * @vdev: datapath vdev handle
  3949. * @tx_desc: tx desc
  3950. * @netbuf: buffer
  3951. * @status: tx status
  3952. *
  3953. * Return: none
  3954. */
  3955. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3956. struct dp_vdev *vdev,
  3957. struct dp_tx_desc_s *tx_desc,
  3958. qdf_nbuf_t netbuf,
  3959. uint8_t status)
  3960. {
  3961. void *osif_dev;
  3962. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3963. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3964. qdf_assert(tx_desc);
  3965. if (!vdev ||
  3966. !vdev->osif_vdev) {
  3967. return;
  3968. }
  3969. osif_dev = vdev->osif_vdev;
  3970. tx_compl_cbk = vdev->tx_comp;
  3971. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3972. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3973. if (tx_compl_cbk)
  3974. tx_compl_cbk(netbuf, osif_dev, flag);
  3975. }
  3976. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3977. * @pdev: pdev handle
  3978. * @tid: tid value
  3979. * @txdesc_ts: timestamp from txdesc
  3980. * @ppdu_id: ppdu id
  3981. *
  3982. * Return: none
  3983. */
  3984. #ifdef FEATURE_PERPKT_INFO
  3985. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3986. struct dp_txrx_peer *txrx_peer,
  3987. uint8_t tid,
  3988. uint64_t txdesc_ts,
  3989. uint32_t ppdu_id)
  3990. {
  3991. uint64_t delta_ms;
  3992. struct cdp_tx_sojourn_stats *sojourn_stats;
  3993. struct dp_peer *primary_link_peer = NULL;
  3994. struct dp_soc *link_peer_soc = NULL;
  3995. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3996. return;
  3997. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3998. tid >= CDP_DATA_TID_MAX))
  3999. return;
  4000. if (qdf_unlikely(!pdev->sojourn_buf))
  4001. return;
  4002. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4003. txrx_peer->peer_id,
  4004. DP_MOD_ID_TX_COMP);
  4005. if (qdf_unlikely(!primary_link_peer))
  4006. return;
  4007. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4008. qdf_nbuf_data(pdev->sojourn_buf);
  4009. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4010. sojourn_stats->cookie = (void *)
  4011. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4012. primary_link_peer);
  4013. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4014. txdesc_ts;
  4015. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4016. delta_ms);
  4017. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4018. sojourn_stats->num_msdus[tid] = 1;
  4019. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4020. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4021. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4022. pdev->sojourn_buf, HTT_INVALID_PEER,
  4023. WDI_NO_VAL, pdev->pdev_id);
  4024. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4025. sojourn_stats->num_msdus[tid] = 0;
  4026. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4027. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4028. }
  4029. #else
  4030. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4031. struct dp_txrx_peer *txrx_peer,
  4032. uint8_t tid,
  4033. uint64_t txdesc_ts,
  4034. uint32_t ppdu_id)
  4035. {
  4036. }
  4037. #endif
  4038. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4039. /**
  4040. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4041. * @soc: dp_soc handle
  4042. * @desc: Tx Descriptor
  4043. * @ts: HAL Tx completion descriptor contents
  4044. *
  4045. * This function is used to send tx completion to packet capture
  4046. */
  4047. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4048. struct dp_tx_desc_s *desc,
  4049. struct hal_tx_completion_status *ts)
  4050. {
  4051. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4052. desc, ts->peer_id,
  4053. WDI_NO_VAL, desc->pdev->pdev_id);
  4054. }
  4055. #endif
  4056. /**
  4057. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4058. * @soc: DP Soc handle
  4059. * @tx_desc: software Tx descriptor
  4060. * @ts : Tx completion status from HAL/HTT descriptor
  4061. *
  4062. * Return: none
  4063. */
  4064. void
  4065. dp_tx_comp_process_desc(struct dp_soc *soc,
  4066. struct dp_tx_desc_s *desc,
  4067. struct hal_tx_completion_status *ts,
  4068. struct dp_txrx_peer *txrx_peer)
  4069. {
  4070. uint64_t time_latency = 0;
  4071. uint16_t peer_id = DP_INVALID_PEER_ID;
  4072. /*
  4073. * m_copy/tx_capture modes are not supported for
  4074. * scatter gather packets
  4075. */
  4076. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4077. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4078. qdf_ktime_to_ms(desc->timestamp));
  4079. }
  4080. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4081. if (dp_tx_pkt_tracepoints_enabled())
  4082. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4083. desc->msdu_ext_desc ?
  4084. desc->msdu_ext_desc->tso_desc : NULL,
  4085. qdf_ktime_to_ms(desc->timestamp));
  4086. if (!(desc->msdu_ext_desc)) {
  4087. dp_tx_enh_unmap(soc, desc);
  4088. if (txrx_peer)
  4089. peer_id = txrx_peer->peer_id;
  4090. if (QDF_STATUS_SUCCESS ==
  4091. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4092. return;
  4093. }
  4094. if (QDF_STATUS_SUCCESS ==
  4095. dp_get_completion_indication_for_stack(soc,
  4096. desc->pdev,
  4097. txrx_peer, ts,
  4098. desc->nbuf,
  4099. time_latency)) {
  4100. dp_send_completion_to_stack(soc,
  4101. desc->pdev,
  4102. ts->peer_id,
  4103. ts->ppdu_id,
  4104. desc->nbuf);
  4105. return;
  4106. }
  4107. }
  4108. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4109. dp_tx_comp_free_buf(soc, desc, false);
  4110. }
  4111. #ifdef DISABLE_DP_STATS
  4112. /**
  4113. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4114. * @soc: core txrx main context
  4115. * @tx_desc: tx desc
  4116. * @status: tx status
  4117. *
  4118. * Return: none
  4119. */
  4120. static inline
  4121. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4122. struct dp_vdev *vdev,
  4123. struct dp_tx_desc_s *tx_desc,
  4124. uint8_t status)
  4125. {
  4126. }
  4127. #else
  4128. static inline
  4129. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4130. struct dp_vdev *vdev,
  4131. struct dp_tx_desc_s *tx_desc,
  4132. uint8_t status)
  4133. {
  4134. void *osif_dev;
  4135. ol_txrx_stats_rx_fp stats_cbk;
  4136. uint8_t pkt_type;
  4137. qdf_assert(tx_desc);
  4138. if (!vdev ||
  4139. !vdev->osif_vdev ||
  4140. !vdev->stats_cb)
  4141. return;
  4142. osif_dev = vdev->osif_vdev;
  4143. stats_cbk = vdev->stats_cb;
  4144. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4145. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4146. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4147. &pkt_type);
  4148. }
  4149. #endif
  4150. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4151. QDF_STATUS
  4152. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4153. uint32_t delta_tsf,
  4154. uint32_t *delay_us)
  4155. {
  4156. uint32_t buffer_ts;
  4157. uint32_t delay;
  4158. if (!delay_us)
  4159. return QDF_STATUS_E_INVAL;
  4160. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4161. if (!ts->valid)
  4162. return QDF_STATUS_E_INVAL;
  4163. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4164. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4165. * valid up to 29 bits.
  4166. */
  4167. buffer_ts = ts->buffer_timestamp << 10;
  4168. delay = ts->tsf - buffer_ts - delta_tsf;
  4169. if (qdf_unlikely(delay & 0x80000000)) {
  4170. dp_err_rl("delay = 0x%x (-ve)\n"
  4171. "release_src = %d\n"
  4172. "ppdu_id = 0x%x\n"
  4173. "peer_id = 0x%x\n"
  4174. "tid = 0x%x\n"
  4175. "release_reason = %d\n"
  4176. "tsf = %u (0x%x)\n"
  4177. "buffer_timestamp = %u (0x%x)\n"
  4178. "delta_tsf = %u (0x%x)\n",
  4179. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4180. ts->tid, ts->status, ts->tsf, ts->tsf,
  4181. ts->buffer_timestamp, ts->buffer_timestamp,
  4182. delta_tsf, delta_tsf);
  4183. delay = 0;
  4184. goto end;
  4185. }
  4186. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4187. if (delay > 0x1000000) {
  4188. dp_info_rl("----------------------\n"
  4189. "Tx completion status:\n"
  4190. "----------------------\n"
  4191. "release_src = %d\n"
  4192. "ppdu_id = 0x%x\n"
  4193. "release_reason = %d\n"
  4194. "tsf = %u (0x%x)\n"
  4195. "buffer_timestamp = %u (0x%x)\n"
  4196. "delta_tsf = %u (0x%x)\n",
  4197. ts->release_src, ts->ppdu_id, ts->status,
  4198. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4199. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4200. return QDF_STATUS_E_FAILURE;
  4201. }
  4202. end:
  4203. *delay_us = delay;
  4204. return QDF_STATUS_SUCCESS;
  4205. }
  4206. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4207. uint32_t delta_tsf)
  4208. {
  4209. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4210. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4211. DP_MOD_ID_CDP);
  4212. if (!vdev) {
  4213. dp_err_rl("vdev %d does not exist", vdev_id);
  4214. return;
  4215. }
  4216. vdev->delta_tsf = delta_tsf;
  4217. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4218. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4219. }
  4220. #endif
  4221. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4222. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4223. uint8_t vdev_id, bool enable)
  4224. {
  4225. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4226. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4227. DP_MOD_ID_CDP);
  4228. if (!vdev) {
  4229. dp_err_rl("vdev %d does not exist", vdev_id);
  4230. return QDF_STATUS_E_FAILURE;
  4231. }
  4232. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4233. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4234. return QDF_STATUS_SUCCESS;
  4235. }
  4236. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4237. uint32_t *val)
  4238. {
  4239. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4240. struct dp_vdev *vdev;
  4241. uint32_t delay_accum;
  4242. uint32_t pkts_accum;
  4243. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4244. if (!vdev) {
  4245. dp_err_rl("vdev %d does not exist", vdev_id);
  4246. return QDF_STATUS_E_FAILURE;
  4247. }
  4248. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4249. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4250. return QDF_STATUS_E_FAILURE;
  4251. }
  4252. /* Average uplink delay based on current accumulated values */
  4253. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4254. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4255. *val = delay_accum / pkts_accum;
  4256. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4257. delay_accum, pkts_accum);
  4258. /* Reset accumulated values to 0 */
  4259. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4260. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4261. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4262. return QDF_STATUS_SUCCESS;
  4263. }
  4264. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4265. struct hal_tx_completion_status *ts)
  4266. {
  4267. uint32_t ul_delay;
  4268. if (qdf_unlikely(!vdev)) {
  4269. dp_info_rl("vdev is null or delete in progrss");
  4270. return;
  4271. }
  4272. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4273. return;
  4274. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4275. vdev->delta_tsf,
  4276. &ul_delay)))
  4277. return;
  4278. ul_delay /= 1000; /* in unit of ms */
  4279. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4280. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4281. }
  4282. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4283. static inline
  4284. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4285. struct hal_tx_completion_status *ts)
  4286. {
  4287. }
  4288. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4289. /**
  4290. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4291. * @soc: DP soc handle
  4292. * @tx_desc: software descriptor head pointer
  4293. * @ts: Tx completion status
  4294. * @txrx_peer: txrx peer handle
  4295. * @ring_id: ring number
  4296. *
  4297. * Return: none
  4298. */
  4299. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4300. struct dp_tx_desc_s *tx_desc,
  4301. struct hal_tx_completion_status *ts,
  4302. struct dp_txrx_peer *txrx_peer,
  4303. uint8_t ring_id)
  4304. {
  4305. uint32_t length;
  4306. qdf_ether_header_t *eh;
  4307. struct dp_vdev *vdev = NULL;
  4308. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4309. enum qdf_dp_tx_rx_status dp_status;
  4310. if (!nbuf) {
  4311. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4312. goto out;
  4313. }
  4314. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4315. length = qdf_nbuf_len(nbuf);
  4316. dp_status = dp_tx_hw_to_qdf(ts->status);
  4317. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4318. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4319. QDF_TRACE_DEFAULT_PDEV_ID,
  4320. qdf_nbuf_data_addr(nbuf),
  4321. sizeof(qdf_nbuf_data(nbuf)),
  4322. tx_desc->id, ts->status, dp_status));
  4323. dp_tx_comp_debug("-------------------- \n"
  4324. "Tx Completion Stats: \n"
  4325. "-------------------- \n"
  4326. "ack_frame_rssi = %d \n"
  4327. "first_msdu = %d \n"
  4328. "last_msdu = %d \n"
  4329. "msdu_part_of_amsdu = %d \n"
  4330. "rate_stats valid = %d \n"
  4331. "bw = %d \n"
  4332. "pkt_type = %d \n"
  4333. "stbc = %d \n"
  4334. "ldpc = %d \n"
  4335. "sgi = %d \n"
  4336. "mcs = %d \n"
  4337. "ofdma = %d \n"
  4338. "tones_in_ru = %d \n"
  4339. "tsf = %d \n"
  4340. "ppdu_id = %d \n"
  4341. "transmit_cnt = %d \n"
  4342. "tid = %d \n"
  4343. "peer_id = %d\n"
  4344. "tx_status = %d\n",
  4345. ts->ack_frame_rssi, ts->first_msdu,
  4346. ts->last_msdu, ts->msdu_part_of_amsdu,
  4347. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4348. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4349. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4350. ts->transmit_cnt, ts->tid, ts->peer_id,
  4351. ts->status);
  4352. /* Update SoC level stats */
  4353. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4354. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4355. if (!txrx_peer) {
  4356. dp_info_rl("peer is null or deletion in progress");
  4357. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4358. goto out;
  4359. }
  4360. vdev = txrx_peer->vdev;
  4361. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4362. dp_tx_update_uplink_delay(soc, vdev, ts);
  4363. /* check tx complete notification */
  4364. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4365. dp_tx_notify_completion(soc, vdev, tx_desc,
  4366. nbuf, ts->status);
  4367. /* Update per-packet stats for mesh mode */
  4368. if (qdf_unlikely(vdev->mesh_vdev) &&
  4369. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4370. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4371. /* Update peer level stats */
  4372. if (qdf_unlikely(txrx_peer->bss_peer &&
  4373. vdev->opmode == wlan_op_mode_ap)) {
  4374. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4375. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4376. length);
  4377. if (txrx_peer->vdev->tx_encap_type ==
  4378. htt_cmn_pkt_type_ethernet &&
  4379. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4380. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4381. tx.bcast, 1,
  4382. length);
  4383. }
  4384. }
  4385. } else {
  4386. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4387. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4388. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4389. 1, length);
  4390. if (qdf_unlikely(txrx_peer->in_twt)) {
  4391. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4392. tx.tx_success_twt,
  4393. 1, length);
  4394. }
  4395. }
  4396. }
  4397. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4398. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4399. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4400. ts, ts->tid);
  4401. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4402. #ifdef QCA_SUPPORT_RDK_STATS
  4403. if (soc->peerstats_enabled)
  4404. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4405. qdf_ktime_to_ms(tx_desc->timestamp),
  4406. ts->ppdu_id);
  4407. #endif
  4408. out:
  4409. return;
  4410. }
  4411. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4412. defined(QCA_ENHANCED_STATS_SUPPORT)
  4413. /*
  4414. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4415. * @txrx_peer: Datapath txrx_peer handle
  4416. * @length: Length of the packet
  4417. * @tx_status: Tx status from TQM/FW
  4418. * @update: enhanced flag value present in dp_pdev
  4419. *
  4420. * Return: none
  4421. */
  4422. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4423. uint32_t length, uint8_t tx_status,
  4424. bool update)
  4425. {
  4426. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4427. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4428. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4429. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4430. }
  4431. }
  4432. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4433. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4434. uint32_t length, uint8_t tx_status,
  4435. bool update)
  4436. {
  4437. if (!txrx_peer->hw_txrx_stats_en) {
  4438. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4439. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4440. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4441. }
  4442. }
  4443. #else
  4444. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4445. uint32_t length, uint8_t tx_status,
  4446. bool update)
  4447. {
  4448. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4449. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4450. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4451. }
  4452. #endif
  4453. /*
  4454. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4455. * @nbuf: skb buffer
  4456. *
  4457. * Return: none
  4458. */
  4459. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4460. static inline
  4461. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4462. {
  4463. qdf_nbuf_t nbuf = NULL;
  4464. if (next)
  4465. nbuf = next->nbuf;
  4466. if (nbuf) {
  4467. /* prefetch skb->next and first few bytes of skb->cb */
  4468. qdf_prefetch(next->shinfo_addr);
  4469. qdf_prefetch(nbuf);
  4470. /* prefetch skb fields present in different cachelines */
  4471. qdf_prefetch(&nbuf->len);
  4472. qdf_prefetch(&nbuf->users);
  4473. }
  4474. }
  4475. #else
  4476. static inline
  4477. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4478. {
  4479. }
  4480. #endif
  4481. /**
  4482. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4483. * @soc: core txrx main context
  4484. * @desc: software descriptor
  4485. *
  4486. * Return: true when packet is reinjected
  4487. */
  4488. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4489. defined(WLAN_MCAST_MLO)
  4490. static inline bool
  4491. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4492. {
  4493. struct dp_vdev *vdev = NULL;
  4494. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4495. if (!soc->arch_ops.dp_tx_mcast_handler)
  4496. return false;
  4497. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4498. DP_MOD_ID_REINJECT);
  4499. if (qdf_unlikely(!vdev)) {
  4500. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4501. desc->id);
  4502. return false;
  4503. }
  4504. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4505. qdf_nbuf_len(desc->nbuf));
  4506. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4507. dp_tx_desc_release(desc, desc->pool_id);
  4508. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4509. return true;
  4510. }
  4511. return false;
  4512. }
  4513. #else
  4514. static inline bool
  4515. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4516. {
  4517. return false;
  4518. }
  4519. #endif
  4520. /**
  4521. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4522. * @soc: core txrx main context
  4523. * @comp_head: software descriptor head pointer
  4524. * @ring_id: ring number
  4525. *
  4526. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4527. * and release the software descriptors after processing is complete
  4528. *
  4529. * Return: none
  4530. */
  4531. static void
  4532. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4533. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4534. {
  4535. struct dp_tx_desc_s *desc;
  4536. struct dp_tx_desc_s *next;
  4537. struct hal_tx_completion_status ts;
  4538. struct dp_txrx_peer *txrx_peer = NULL;
  4539. uint16_t peer_id = DP_INVALID_PEER;
  4540. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4541. desc = comp_head;
  4542. while (desc) {
  4543. next = desc->next;
  4544. dp_tx_prefetch_next_nbuf_data(next);
  4545. if (peer_id != desc->peer_id) {
  4546. if (txrx_peer)
  4547. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4548. DP_MOD_ID_TX_COMP);
  4549. peer_id = desc->peer_id;
  4550. txrx_peer =
  4551. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4552. &txrx_ref_handle,
  4553. DP_MOD_ID_TX_COMP);
  4554. }
  4555. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4556. desc = next;
  4557. continue;
  4558. }
  4559. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4560. struct dp_pdev *pdev = desc->pdev;
  4561. if (qdf_likely(txrx_peer))
  4562. dp_tx_update_peer_basic_stats(txrx_peer,
  4563. desc->length,
  4564. desc->tx_status,
  4565. false);
  4566. qdf_assert(pdev);
  4567. dp_tx_outstanding_dec(pdev);
  4568. /*
  4569. * Calling a QDF WRAPPER here is creating signifcant
  4570. * performance impact so avoided the wrapper call here
  4571. */
  4572. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4573. desc->id, DP_TX_COMP_UNMAP);
  4574. dp_tx_nbuf_unmap(soc, desc);
  4575. qdf_nbuf_free_simple(desc->nbuf);
  4576. dp_tx_desc_free(soc, desc, desc->pool_id);
  4577. desc = next;
  4578. continue;
  4579. }
  4580. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4581. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4582. ring_id);
  4583. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4584. dp_tx_desc_release(desc, desc->pool_id);
  4585. desc = next;
  4586. }
  4587. if (txrx_peer)
  4588. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4589. }
  4590. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4591. static inline
  4592. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4593. int max_reap_limit)
  4594. {
  4595. bool limit_hit = false;
  4596. limit_hit =
  4597. (num_reaped >= max_reap_limit) ? true : false;
  4598. if (limit_hit)
  4599. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4600. return limit_hit;
  4601. }
  4602. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4603. {
  4604. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4605. }
  4606. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4607. {
  4608. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4609. return cfg->tx_comp_loop_pkt_limit;
  4610. }
  4611. #else
  4612. static inline
  4613. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4614. int max_reap_limit)
  4615. {
  4616. return false;
  4617. }
  4618. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4619. {
  4620. return false;
  4621. }
  4622. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4623. {
  4624. return 0;
  4625. }
  4626. #endif
  4627. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4628. static inline int
  4629. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4630. int *max_reap_limit)
  4631. {
  4632. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4633. max_reap_limit);
  4634. }
  4635. #else
  4636. static inline int
  4637. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4638. int *max_reap_limit)
  4639. {
  4640. return 0;
  4641. }
  4642. #endif
  4643. #ifdef DP_TX_TRACKING
  4644. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4645. {
  4646. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4647. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4648. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4649. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4650. }
  4651. }
  4652. #endif
  4653. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4654. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4655. uint32_t quota)
  4656. {
  4657. void *tx_comp_hal_desc;
  4658. void *last_prefetched_hw_desc = NULL;
  4659. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4660. hal_soc_handle_t hal_soc;
  4661. uint8_t buffer_src;
  4662. struct dp_tx_desc_s *tx_desc = NULL;
  4663. struct dp_tx_desc_s *head_desc = NULL;
  4664. struct dp_tx_desc_s *tail_desc = NULL;
  4665. uint32_t num_processed = 0;
  4666. uint32_t count;
  4667. uint32_t num_avail_for_reap = 0;
  4668. bool force_break = false;
  4669. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4670. int max_reap_limit, ring_near_full;
  4671. DP_HIST_INIT();
  4672. more_data:
  4673. hal_soc = soc->hal_soc;
  4674. /* Re-initialize local variables to be re-used */
  4675. head_desc = NULL;
  4676. tail_desc = NULL;
  4677. count = 0;
  4678. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4679. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4680. &max_reap_limit);
  4681. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4682. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4683. return 0;
  4684. }
  4685. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4686. if (num_avail_for_reap >= quota)
  4687. num_avail_for_reap = quota;
  4688. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4689. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4690. hal_ring_hdl,
  4691. num_avail_for_reap);
  4692. /* Find head descriptor from completion ring */
  4693. while (qdf_likely(num_avail_for_reap--)) {
  4694. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4695. if (qdf_unlikely(!tx_comp_hal_desc))
  4696. break;
  4697. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4698. tx_comp_hal_desc);
  4699. /* If this buffer was not released by TQM or FW, then it is not
  4700. * Tx completion indication, assert */
  4701. if (qdf_unlikely(buffer_src !=
  4702. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4703. (qdf_unlikely(buffer_src !=
  4704. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4705. uint8_t wbm_internal_error;
  4706. dp_err_rl(
  4707. "Tx comp release_src != TQM | FW but from %d",
  4708. buffer_src);
  4709. hal_dump_comp_desc(tx_comp_hal_desc);
  4710. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4711. /* When WBM sees NULL buffer_addr_info in any of
  4712. * ingress rings it sends an error indication,
  4713. * with wbm_internal_error=1, to a specific ring.
  4714. * The WBM2SW ring used to indicate these errors is
  4715. * fixed in HW, and that ring is being used as Tx
  4716. * completion ring. These errors are not related to
  4717. * Tx completions, and should just be ignored
  4718. */
  4719. wbm_internal_error = hal_get_wbm_internal_error(
  4720. hal_soc,
  4721. tx_comp_hal_desc);
  4722. if (wbm_internal_error) {
  4723. dp_err_rl("Tx comp wbm_internal_error!!");
  4724. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4725. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4726. buffer_src)
  4727. dp_handle_wbm_internal_error(
  4728. soc,
  4729. tx_comp_hal_desc,
  4730. hal_tx_comp_get_buffer_type(
  4731. tx_comp_hal_desc));
  4732. } else {
  4733. dp_err_rl("Tx comp wbm_internal_error false");
  4734. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4735. }
  4736. continue;
  4737. }
  4738. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4739. tx_comp_hal_desc,
  4740. &tx_desc);
  4741. if (!tx_desc) {
  4742. dp_err("unable to retrieve tx_desc!");
  4743. QDF_BUG(0);
  4744. continue;
  4745. }
  4746. tx_desc->buffer_src = buffer_src;
  4747. /*
  4748. * If the release source is FW, process the HTT status
  4749. */
  4750. if (qdf_unlikely(buffer_src ==
  4751. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4752. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4753. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4754. htt_tx_status);
  4755. /* Collect hw completion contents */
  4756. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4757. &tx_desc->comp, 1);
  4758. soc->arch_ops.dp_tx_process_htt_completion(
  4759. soc,
  4760. tx_desc,
  4761. htt_tx_status,
  4762. ring_id);
  4763. } else {
  4764. tx_desc->tx_status =
  4765. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4766. tx_desc->buffer_src = buffer_src;
  4767. /*
  4768. * If the fast completion mode is enabled extended
  4769. * metadata from descriptor is not copied
  4770. */
  4771. if (qdf_likely(tx_desc->flags &
  4772. DP_TX_DESC_FLAG_SIMPLE))
  4773. goto add_to_pool;
  4774. /*
  4775. * If the descriptor is already freed in vdev_detach,
  4776. * continue to next descriptor
  4777. */
  4778. if (qdf_unlikely
  4779. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4780. !tx_desc->flags)) {
  4781. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4782. tx_desc->id);
  4783. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4784. dp_tx_desc_check_corruption(tx_desc);
  4785. continue;
  4786. }
  4787. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4788. dp_tx_comp_info_rl("pdev in down state %d",
  4789. tx_desc->id);
  4790. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4791. dp_tx_comp_free_buf(soc, tx_desc, false);
  4792. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4793. goto next_desc;
  4794. }
  4795. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4796. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4797. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4798. tx_desc->flags, tx_desc->id);
  4799. qdf_assert_always(0);
  4800. }
  4801. /* Collect hw completion contents */
  4802. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4803. &tx_desc->comp, 1);
  4804. add_to_pool:
  4805. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4806. /* First ring descriptor on the cycle */
  4807. if (!head_desc) {
  4808. head_desc = tx_desc;
  4809. tail_desc = tx_desc;
  4810. }
  4811. tail_desc->next = tx_desc;
  4812. tx_desc->next = NULL;
  4813. tail_desc = tx_desc;
  4814. }
  4815. next_desc:
  4816. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4817. /*
  4818. * Processed packet count is more than given quota
  4819. * stop to processing
  4820. */
  4821. count++;
  4822. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4823. num_avail_for_reap,
  4824. hal_ring_hdl,
  4825. &last_prefetched_hw_desc,
  4826. &last_prefetched_sw_desc);
  4827. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4828. break;
  4829. }
  4830. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4831. /* Process the reaped descriptors */
  4832. if (head_desc)
  4833. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4834. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4835. /*
  4836. * If we are processing in near-full condition, there are 3 scenario
  4837. * 1) Ring entries has reached critical state
  4838. * 2) Ring entries are still near high threshold
  4839. * 3) Ring entries are below the safe level
  4840. *
  4841. * One more loop will move te state to normal processing and yield
  4842. */
  4843. if (ring_near_full)
  4844. goto more_data;
  4845. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4846. if (num_processed >= quota)
  4847. force_break = true;
  4848. if (!force_break &&
  4849. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4850. hal_ring_hdl)) {
  4851. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4852. if (!hif_exec_should_yield(soc->hif_handle,
  4853. int_ctx->dp_intr_id))
  4854. goto more_data;
  4855. }
  4856. }
  4857. DP_TX_HIST_STATS_PER_PDEV();
  4858. return num_processed;
  4859. }
  4860. #ifdef FEATURE_WLAN_TDLS
  4861. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4862. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4863. {
  4864. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4865. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4866. DP_MOD_ID_TDLS);
  4867. if (!vdev) {
  4868. dp_err("vdev handle for id %d is NULL", vdev_id);
  4869. return NULL;
  4870. }
  4871. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4872. vdev->is_tdls_frame = true;
  4873. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4874. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4875. }
  4876. #endif
  4877. /**
  4878. * dp_tx_vdev_attach() - attach vdev to dp tx
  4879. * @vdev: virtual device instance
  4880. *
  4881. * Return: QDF_STATUS_SUCCESS: success
  4882. * QDF_STATUS_E_RESOURCES: Error return
  4883. */
  4884. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4885. {
  4886. int pdev_id;
  4887. /*
  4888. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4889. */
  4890. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4891. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4892. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4893. vdev->vdev_id);
  4894. pdev_id =
  4895. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4896. vdev->pdev->pdev_id);
  4897. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4898. /*
  4899. * Set HTT Extension Valid bit to 0 by default
  4900. */
  4901. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4902. dp_tx_vdev_update_search_flags(vdev);
  4903. return QDF_STATUS_SUCCESS;
  4904. }
  4905. #ifndef FEATURE_WDS
  4906. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4907. {
  4908. return false;
  4909. }
  4910. #endif
  4911. /**
  4912. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4913. * @vdev: virtual device instance
  4914. *
  4915. * Return: void
  4916. *
  4917. */
  4918. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4919. {
  4920. struct dp_soc *soc = vdev->pdev->soc;
  4921. /*
  4922. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4923. * for TDLS link
  4924. *
  4925. * Enable AddrY (SA based search) only for non-WDS STA and
  4926. * ProxySTA VAP (in HKv1) modes.
  4927. *
  4928. * In all other VAP modes, only DA based search should be
  4929. * enabled
  4930. */
  4931. if (vdev->opmode == wlan_op_mode_sta &&
  4932. vdev->tdls_link_connected)
  4933. vdev->hal_desc_addr_search_flags =
  4934. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4935. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4936. !dp_tx_da_search_override(vdev))
  4937. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4938. else
  4939. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4940. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4941. vdev->search_type = soc->sta_mode_search_policy;
  4942. else
  4943. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4944. }
  4945. static inline bool
  4946. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4947. struct dp_vdev *vdev,
  4948. struct dp_tx_desc_s *tx_desc)
  4949. {
  4950. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4951. return false;
  4952. /*
  4953. * if vdev is given, then only check whether desc
  4954. * vdev match. if vdev is NULL, then check whether
  4955. * desc pdev match.
  4956. */
  4957. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4958. (tx_desc->pdev == pdev);
  4959. }
  4960. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4961. /**
  4962. * dp_tx_desc_flush() - release resources associated
  4963. * to TX Desc
  4964. *
  4965. * @dp_pdev: Handle to DP pdev structure
  4966. * @vdev: virtual device instance
  4967. * NULL: no specific Vdev is required and check all allcated TX desc
  4968. * on this pdev.
  4969. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4970. *
  4971. * @force_free:
  4972. * true: flush the TX desc.
  4973. * false: only reset the Vdev in each allocated TX desc
  4974. * that associated to current Vdev.
  4975. *
  4976. * This function will go through the TX desc pool to flush
  4977. * the outstanding TX data or reset Vdev to NULL in associated TX
  4978. * Desc.
  4979. */
  4980. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4981. bool force_free)
  4982. {
  4983. uint8_t i;
  4984. uint32_t j;
  4985. uint32_t num_desc, page_id, offset;
  4986. uint16_t num_desc_per_page;
  4987. struct dp_soc *soc = pdev->soc;
  4988. struct dp_tx_desc_s *tx_desc = NULL;
  4989. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4990. if (!vdev && !force_free) {
  4991. dp_err("Reset TX desc vdev, Vdev param is required!");
  4992. return;
  4993. }
  4994. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4995. tx_desc_pool = &soc->tx_desc[i];
  4996. if (!(tx_desc_pool->pool_size) ||
  4997. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4998. !(tx_desc_pool->desc_pages.cacheable_pages))
  4999. continue;
  5000. /*
  5001. * Add flow pool lock protection in case pool is freed
  5002. * due to all tx_desc is recycled when handle TX completion.
  5003. * this is not necessary when do force flush as:
  5004. * a. double lock will happen if dp_tx_desc_release is
  5005. * also trying to acquire it.
  5006. * b. dp interrupt has been disabled before do force TX desc
  5007. * flush in dp_pdev_deinit().
  5008. */
  5009. if (!force_free)
  5010. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5011. num_desc = tx_desc_pool->pool_size;
  5012. num_desc_per_page =
  5013. tx_desc_pool->desc_pages.num_element_per_page;
  5014. for (j = 0; j < num_desc; j++) {
  5015. page_id = j / num_desc_per_page;
  5016. offset = j % num_desc_per_page;
  5017. if (qdf_unlikely(!(tx_desc_pool->
  5018. desc_pages.cacheable_pages)))
  5019. break;
  5020. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5021. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5022. /*
  5023. * Free TX desc if force free is
  5024. * required, otherwise only reset vdev
  5025. * in this TX desc.
  5026. */
  5027. if (force_free) {
  5028. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5029. dp_tx_comp_free_buf(soc, tx_desc,
  5030. false);
  5031. dp_tx_desc_release(tx_desc, i);
  5032. } else {
  5033. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5034. }
  5035. }
  5036. }
  5037. if (!force_free)
  5038. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5039. }
  5040. }
  5041. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5042. /**
  5043. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5044. *
  5045. * @soc: Handle to DP soc structure
  5046. * @tx_desc: pointer of one TX desc
  5047. * @desc_pool_id: TX Desc pool id
  5048. */
  5049. static inline void
  5050. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5051. uint8_t desc_pool_id)
  5052. {
  5053. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5054. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5055. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5056. }
  5057. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5058. bool force_free)
  5059. {
  5060. uint8_t i, num_pool;
  5061. uint32_t j;
  5062. uint32_t num_desc, page_id, offset;
  5063. uint16_t num_desc_per_page;
  5064. struct dp_soc *soc = pdev->soc;
  5065. struct dp_tx_desc_s *tx_desc = NULL;
  5066. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5067. if (!vdev && !force_free) {
  5068. dp_err("Reset TX desc vdev, Vdev param is required!");
  5069. return;
  5070. }
  5071. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5072. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5073. for (i = 0; i < num_pool; i++) {
  5074. tx_desc_pool = &soc->tx_desc[i];
  5075. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5076. continue;
  5077. num_desc_per_page =
  5078. tx_desc_pool->desc_pages.num_element_per_page;
  5079. for (j = 0; j < num_desc; j++) {
  5080. page_id = j / num_desc_per_page;
  5081. offset = j % num_desc_per_page;
  5082. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5083. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5084. if (force_free) {
  5085. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5086. dp_tx_comp_free_buf(soc, tx_desc,
  5087. false);
  5088. dp_tx_desc_release(tx_desc, i);
  5089. } else {
  5090. dp_tx_desc_reset_vdev(soc, tx_desc,
  5091. i);
  5092. }
  5093. }
  5094. }
  5095. }
  5096. }
  5097. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5098. /**
  5099. * dp_tx_vdev_detach() - detach vdev from dp tx
  5100. * @vdev: virtual device instance
  5101. *
  5102. * Return: QDF_STATUS_SUCCESS: success
  5103. * QDF_STATUS_E_RESOURCES: Error return
  5104. */
  5105. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5106. {
  5107. struct dp_pdev *pdev = vdev->pdev;
  5108. /* Reset TX desc associated to this Vdev as NULL */
  5109. dp_tx_desc_flush(pdev, vdev, false);
  5110. return QDF_STATUS_SUCCESS;
  5111. }
  5112. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5113. /* Pools will be allocated dynamically */
  5114. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5115. int num_desc)
  5116. {
  5117. uint8_t i;
  5118. for (i = 0; i < num_pool; i++) {
  5119. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5120. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5121. }
  5122. return QDF_STATUS_SUCCESS;
  5123. }
  5124. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5125. uint32_t num_desc)
  5126. {
  5127. return QDF_STATUS_SUCCESS;
  5128. }
  5129. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5130. {
  5131. }
  5132. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5133. {
  5134. uint8_t i;
  5135. for (i = 0; i < num_pool; i++)
  5136. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5137. }
  5138. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5139. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5140. uint32_t num_desc)
  5141. {
  5142. uint8_t i, count;
  5143. /* Allocate software Tx descriptor pools */
  5144. for (i = 0; i < num_pool; i++) {
  5145. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5147. FL("Tx Desc Pool alloc %d failed %pK"),
  5148. i, soc);
  5149. goto fail;
  5150. }
  5151. }
  5152. return QDF_STATUS_SUCCESS;
  5153. fail:
  5154. for (count = 0; count < i; count++)
  5155. dp_tx_desc_pool_free(soc, count);
  5156. return QDF_STATUS_E_NOMEM;
  5157. }
  5158. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5159. uint32_t num_desc)
  5160. {
  5161. uint8_t i;
  5162. for (i = 0; i < num_pool; i++) {
  5163. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5165. FL("Tx Desc Pool init %d failed %pK"),
  5166. i, soc);
  5167. return QDF_STATUS_E_NOMEM;
  5168. }
  5169. }
  5170. return QDF_STATUS_SUCCESS;
  5171. }
  5172. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5173. {
  5174. uint8_t i;
  5175. for (i = 0; i < num_pool; i++)
  5176. dp_tx_desc_pool_deinit(soc, i);
  5177. }
  5178. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5179. {
  5180. uint8_t i;
  5181. for (i = 0; i < num_pool; i++)
  5182. dp_tx_desc_pool_free(soc, i);
  5183. }
  5184. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5185. /**
  5186. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5187. * @soc: core txrx main context
  5188. * @num_pool: number of pools
  5189. *
  5190. */
  5191. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5192. {
  5193. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5194. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5195. }
  5196. /**
  5197. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5198. * @soc: core txrx main context
  5199. * @num_pool: number of pools
  5200. *
  5201. */
  5202. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5203. {
  5204. dp_tx_tso_desc_pool_free(soc, num_pool);
  5205. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5206. }
  5207. /**
  5208. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5209. * @soc: core txrx main context
  5210. *
  5211. * This function frees all tx related descriptors as below
  5212. * 1. Regular TX descriptors (static pools)
  5213. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5214. * 3. TSO descriptors
  5215. *
  5216. */
  5217. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5218. {
  5219. uint8_t num_pool;
  5220. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5221. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5222. dp_tx_ext_desc_pool_free(soc, num_pool);
  5223. dp_tx_delete_static_pools(soc, num_pool);
  5224. }
  5225. /**
  5226. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5227. * @soc: core txrx main context
  5228. *
  5229. * This function de-initializes all tx related descriptors as below
  5230. * 1. Regular TX descriptors (static pools)
  5231. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5232. * 3. TSO descriptors
  5233. *
  5234. */
  5235. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5236. {
  5237. uint8_t num_pool;
  5238. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5239. dp_tx_flow_control_deinit(soc);
  5240. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5241. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5242. dp_tx_deinit_static_pools(soc, num_pool);
  5243. }
  5244. /**
  5245. * dp_tso_attach() - TSO attach handler
  5246. * @txrx_soc: Opaque Dp handle
  5247. *
  5248. * Reserve TSO descriptor buffers
  5249. *
  5250. * Return: QDF_STATUS_E_FAILURE on failure or
  5251. * QDF_STATUS_SUCCESS on success
  5252. */
  5253. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5254. uint8_t num_pool,
  5255. uint32_t num_desc)
  5256. {
  5257. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5258. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5259. return QDF_STATUS_E_FAILURE;
  5260. }
  5261. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5262. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5263. num_pool, soc);
  5264. return QDF_STATUS_E_FAILURE;
  5265. }
  5266. return QDF_STATUS_SUCCESS;
  5267. }
  5268. /**
  5269. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5270. * @soc: DP soc handle
  5271. * @num_pool: Number of pools
  5272. * @num_desc: Number of descriptors
  5273. *
  5274. * Initialize TSO descriptor pools
  5275. *
  5276. * Return: QDF_STATUS_E_FAILURE on failure or
  5277. * QDF_STATUS_SUCCESS on success
  5278. */
  5279. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5280. uint8_t num_pool,
  5281. uint32_t num_desc)
  5282. {
  5283. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5284. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5285. return QDF_STATUS_E_FAILURE;
  5286. }
  5287. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5288. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5289. num_pool, soc);
  5290. return QDF_STATUS_E_FAILURE;
  5291. }
  5292. return QDF_STATUS_SUCCESS;
  5293. }
  5294. /**
  5295. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5296. * @soc: core txrx main context
  5297. *
  5298. * This function allocates memory for following descriptor pools
  5299. * 1. regular sw tx descriptor pools (static pools)
  5300. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5301. * 3. TSO descriptor pools
  5302. *
  5303. * Return: QDF_STATUS_SUCCESS: success
  5304. * QDF_STATUS_E_RESOURCES: Error return
  5305. */
  5306. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5307. {
  5308. uint8_t num_pool;
  5309. uint32_t num_desc;
  5310. uint32_t num_ext_desc;
  5311. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5312. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5313. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5314. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5315. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5316. __func__, num_pool, num_desc);
  5317. if ((num_pool > MAX_TXDESC_POOLS) ||
  5318. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5319. goto fail1;
  5320. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5321. goto fail1;
  5322. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5323. goto fail2;
  5324. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5325. return QDF_STATUS_SUCCESS;
  5326. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5327. goto fail3;
  5328. return QDF_STATUS_SUCCESS;
  5329. fail3:
  5330. dp_tx_ext_desc_pool_free(soc, num_pool);
  5331. fail2:
  5332. dp_tx_delete_static_pools(soc, num_pool);
  5333. fail1:
  5334. return QDF_STATUS_E_RESOURCES;
  5335. }
  5336. /**
  5337. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5338. * @soc: core txrx main context
  5339. *
  5340. * This function initializes the following TX descriptor pools
  5341. * 1. regular sw tx descriptor pools (static pools)
  5342. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5343. * 3. TSO descriptor pools
  5344. *
  5345. * Return: QDF_STATUS_SUCCESS: success
  5346. * QDF_STATUS_E_RESOURCES: Error return
  5347. */
  5348. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5349. {
  5350. uint8_t num_pool;
  5351. uint32_t num_desc;
  5352. uint32_t num_ext_desc;
  5353. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5354. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5355. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5356. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5357. goto fail1;
  5358. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5359. goto fail2;
  5360. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5361. return QDF_STATUS_SUCCESS;
  5362. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5363. goto fail3;
  5364. dp_tx_flow_control_init(soc);
  5365. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5366. return QDF_STATUS_SUCCESS;
  5367. fail3:
  5368. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5369. fail2:
  5370. dp_tx_deinit_static_pools(soc, num_pool);
  5371. fail1:
  5372. return QDF_STATUS_E_RESOURCES;
  5373. }
  5374. /**
  5375. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5376. * @txrx_soc: dp soc handle
  5377. *
  5378. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5379. * QDF_STATUS_E_FAILURE
  5380. */
  5381. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5382. {
  5383. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5384. uint8_t num_pool;
  5385. uint32_t num_desc;
  5386. uint32_t num_ext_desc;
  5387. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5388. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5389. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5390. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5391. return QDF_STATUS_E_FAILURE;
  5392. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5393. return QDF_STATUS_E_FAILURE;
  5394. return QDF_STATUS_SUCCESS;
  5395. }
  5396. /**
  5397. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5398. * @txrx_soc: dp soc handle
  5399. *
  5400. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5401. */
  5402. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5403. {
  5404. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5405. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5406. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5407. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5408. return QDF_STATUS_SUCCESS;
  5409. }
  5410. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5411. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5412. enum qdf_pkt_timestamp_index index, uint64_t time,
  5413. qdf_nbuf_t nbuf)
  5414. {
  5415. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5416. uint64_t tsf_time;
  5417. if (vdev->get_tsf_time) {
  5418. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5419. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5420. }
  5421. }
  5422. }
  5423. void dp_pkt_get_timestamp(uint64_t *time)
  5424. {
  5425. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5426. *time = qdf_get_log_timestamp();
  5427. }
  5428. #endif