sde_crtc.c 173 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. #define SKIP_STAGING_PIPE_ZPOS 255
  85. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  86. {
  87. struct msm_drm_private *priv;
  88. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  89. SDE_ERROR("invalid crtc\n");
  90. return NULL;
  91. }
  92. priv = crtc->dev->dev_private;
  93. if (!priv || !priv->kms) {
  94. SDE_ERROR("invalid kms\n");
  95. return NULL;
  96. }
  97. return to_sde_kms(priv->kms);
  98. }
  99. /**
  100. * sde_crtc_calc_fps() - Calculates fps value.
  101. * @sde_crtc : CRTC structure
  102. *
  103. * This function is called at frame done. It counts the number
  104. * of frames done for every 1 sec. Stores the value in measured_fps.
  105. * measured_fps value is 10 times the calculated fps value.
  106. * For example, measured_fps= 594 for calculated fps of 59.4
  107. */
  108. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  109. {
  110. ktime_t current_time_us;
  111. u64 fps, diff_us;
  112. current_time_us = ktime_get();
  113. diff_us = (u64)ktime_us_delta(current_time_us,
  114. sde_crtc->fps_info.last_sampled_time_us);
  115. sde_crtc->fps_info.frame_count++;
  116. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  117. /* Multiplying with 10 to get fps in floating point */
  118. fps = ((u64)sde_crtc->fps_info.frame_count)
  119. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  120. do_div(fps, diff_us);
  121. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  122. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  123. sde_crtc->base.base.id, (unsigned int)fps/10,
  124. (unsigned int)fps%10);
  125. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  126. sde_crtc->fps_info.frame_count = 0;
  127. }
  128. if (!sde_crtc->fps_info.time_buf)
  129. return;
  130. /**
  131. * Array indexing is based on sliding window algorithm.
  132. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  133. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  134. * counter loops around and comes back to the first index to store
  135. * the next ktime.
  136. */
  137. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  138. ktime_get();
  139. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  140. }
  141. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  142. {
  143. if (!sde_crtc)
  144. return;
  145. }
  146. #ifdef CONFIG_DEBUG_FS
  147. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  148. {
  149. struct sde_crtc *sde_crtc;
  150. u64 fps_int, fps_float;
  151. ktime_t current_time_us;
  152. u64 fps, diff_us;
  153. if (!s || !s->private) {
  154. SDE_ERROR("invalid input param(s)\n");
  155. return -EAGAIN;
  156. }
  157. sde_crtc = s->private;
  158. current_time_us = ktime_get();
  159. diff_us = (u64)ktime_us_delta(current_time_us,
  160. sde_crtc->fps_info.last_sampled_time_us);
  161. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  162. /* Multiplying with 10 to get fps in floating point */
  163. fps = ((u64)sde_crtc->fps_info.frame_count)
  164. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  165. do_div(fps, diff_us);
  166. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  167. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  168. sde_crtc->fps_info.frame_count = 0;
  169. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  170. sde_crtc->base.base.id, (unsigned int)fps/10,
  171. (unsigned int)fps%10);
  172. }
  173. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  174. fps_float = do_div(fps_int, 10);
  175. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  176. return 0;
  177. }
  178. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  179. {
  180. return single_open(file, _sde_debugfs_fps_status_show,
  181. inode->i_private);
  182. }
  183. #endif
  184. static ssize_t fps_periodicity_ms_store(struct device *device,
  185. struct device_attribute *attr, const char *buf, size_t count)
  186. {
  187. struct drm_crtc *crtc;
  188. struct sde_crtc *sde_crtc;
  189. int res;
  190. /* Base of the input */
  191. int cnt = 10;
  192. if (!device || !buf) {
  193. SDE_ERROR("invalid input param(s)\n");
  194. return -EAGAIN;
  195. }
  196. crtc = dev_get_drvdata(device);
  197. if (!crtc)
  198. return -EINVAL;
  199. sde_crtc = to_sde_crtc(crtc);
  200. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  201. if (res < 0)
  202. return res;
  203. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  204. sde_crtc->fps_info.fps_periodic_duration =
  205. DEFAULT_FPS_PERIOD_1_SEC;
  206. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  207. MAX_FPS_PERIOD_5_SECONDS)
  208. sde_crtc->fps_info.fps_periodic_duration =
  209. MAX_FPS_PERIOD_5_SECONDS;
  210. else
  211. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  212. return count;
  213. }
  214. static ssize_t fps_periodicity_ms_show(struct device *device,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct drm_crtc *crtc;
  218. struct sde_crtc *sde_crtc;
  219. if (!device || !buf) {
  220. SDE_ERROR("invalid input param(s)\n");
  221. return -EAGAIN;
  222. }
  223. crtc = dev_get_drvdata(device);
  224. if (!crtc)
  225. return -EINVAL;
  226. sde_crtc = to_sde_crtc(crtc);
  227. return scnprintf(buf, PAGE_SIZE, "%d\n",
  228. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  229. }
  230. static ssize_t measured_fps_show(struct device *device,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct drm_crtc *crtc;
  234. struct sde_crtc *sde_crtc;
  235. uint64_t fps_int, fps_decimal;
  236. u64 fps = 0, frame_count = 0;
  237. ktime_t current_time;
  238. int i = 0, current_time_index;
  239. u64 diff_us;
  240. if (!device || !buf) {
  241. SDE_ERROR("invalid input param(s)\n");
  242. return -EAGAIN;
  243. }
  244. crtc = dev_get_drvdata(device);
  245. if (!crtc) {
  246. scnprintf(buf, PAGE_SIZE, "fps information not available");
  247. return -EINVAL;
  248. }
  249. sde_crtc = to_sde_crtc(crtc);
  250. if (!sde_crtc->fps_info.time_buf) {
  251. scnprintf(buf, PAGE_SIZE,
  252. "timebuf null - fps information not available");
  253. return -EINVAL;
  254. }
  255. /**
  256. * Whenever the time_index counter comes to zero upon decrementing,
  257. * it is set to the last index since it is the next index that we
  258. * should check for calculating the buftime.
  259. */
  260. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  261. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  262. current_time = ktime_get();
  263. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  264. u64 ptime = (u64)ktime_to_us(current_time);
  265. u64 buftime = (u64)ktime_to_us(
  266. sde_crtc->fps_info.time_buf[current_time_index]);
  267. diff_us = (u64)ktime_us_delta(current_time,
  268. sde_crtc->fps_info.time_buf[current_time_index]);
  269. if (ptime > buftime && diff_us >= (u64)
  270. sde_crtc->fps_info.fps_periodic_duration) {
  271. /* Multiplying with 10 to get fps in floating point */
  272. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  273. do_div(fps, diff_us);
  274. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  275. SDE_DEBUG("measured fps: %d\n",
  276. sde_crtc->fps_info.measured_fps);
  277. break;
  278. }
  279. current_time_index = (current_time_index == 0) ?
  280. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  281. SDE_DEBUG("current time index: %d\n", current_time_index);
  282. frame_count++;
  283. }
  284. if (i == MAX_FRAME_COUNT) {
  285. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  286. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  287. diff_us = (u64)ktime_us_delta(current_time,
  288. sde_crtc->fps_info.time_buf[current_time_index]);
  289. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  290. /* Multiplying with 10 to get fps in floating point */
  291. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  292. do_div(fps, diff_us);
  293. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  294. }
  295. }
  296. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  297. fps_decimal = do_div(fps_int, 10);
  298. return scnprintf(buf, PAGE_SIZE,
  299. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  300. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  301. }
  302. static ssize_t vsync_event_show(struct device *device,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct drm_crtc *crtc;
  306. struct sde_crtc *sde_crtc;
  307. if (!device || !buf) {
  308. SDE_ERROR("invalid input param(s)\n");
  309. return -EAGAIN;
  310. }
  311. crtc = dev_get_drvdata(device);
  312. sde_crtc = to_sde_crtc(crtc);
  313. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  314. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  315. }
  316. static DEVICE_ATTR_RO(vsync_event);
  317. static DEVICE_ATTR_RO(measured_fps);
  318. static DEVICE_ATTR_RW(fps_periodicity_ms);
  319. static struct attribute *sde_crtc_dev_attrs[] = {
  320. &dev_attr_vsync_event.attr,
  321. &dev_attr_measured_fps.attr,
  322. &dev_attr_fps_periodicity_ms.attr,
  323. NULL
  324. };
  325. static const struct attribute_group sde_crtc_attr_group = {
  326. .attrs = sde_crtc_dev_attrs,
  327. };
  328. static const struct attribute_group *sde_crtc_attr_groups[] = {
  329. &sde_crtc_attr_group,
  330. NULL,
  331. };
  332. static void sde_crtc_destroy(struct drm_crtc *crtc)
  333. {
  334. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  335. SDE_DEBUG("\n");
  336. if (!crtc)
  337. return;
  338. if (sde_crtc->vsync_event_sf)
  339. sysfs_put(sde_crtc->vsync_event_sf);
  340. if (sde_crtc->sysfs_dev)
  341. device_unregister(sde_crtc->sysfs_dev);
  342. if (sde_crtc->blob_info)
  343. drm_property_blob_put(sde_crtc->blob_info);
  344. msm_property_destroy(&sde_crtc->property_info);
  345. sde_cp_crtc_destroy_properties(crtc);
  346. sde_fence_deinit(sde_crtc->output_fence);
  347. _sde_crtc_deinit_events(sde_crtc);
  348. drm_crtc_cleanup(crtc);
  349. mutex_destroy(&sde_crtc->crtc_lock);
  350. kfree(sde_crtc);
  351. }
  352. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  353. const struct drm_display_mode *mode,
  354. struct drm_display_mode *adjusted_mode)
  355. {
  356. SDE_DEBUG("\n");
  357. sde_cp_mode_switch_prop_dirty(crtc);
  358. if ((msm_is_mode_seamless(adjusted_mode) ||
  359. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  360. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  361. (!crtc->enabled)) {
  362. SDE_ERROR("crtc state prevents seamless transition\n");
  363. return false;
  364. }
  365. return true;
  366. }
  367. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  368. struct sde_plane_state *pstate, struct sde_format *format)
  369. {
  370. uint32_t blend_op, fg_alpha, bg_alpha;
  371. uint32_t blend_type;
  372. struct sde_hw_mixer *lm = mixer->hw_lm;
  373. /* default to opaque blending */
  374. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  375. bg_alpha = 0xFF - fg_alpha;
  376. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  377. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  378. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  379. switch (blend_type) {
  380. case SDE_DRM_BLEND_OP_OPAQUE:
  381. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  382. SDE_BLEND_BG_ALPHA_BG_CONST;
  383. break;
  384. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  385. if (format->alpha_enable) {
  386. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  387. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  388. if (fg_alpha != 0xff) {
  389. bg_alpha = fg_alpha;
  390. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  391. SDE_BLEND_BG_INV_MOD_ALPHA;
  392. } else {
  393. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  394. }
  395. }
  396. break;
  397. case SDE_DRM_BLEND_OP_COVERAGE:
  398. if (format->alpha_enable) {
  399. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  400. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  401. if (fg_alpha != 0xff) {
  402. bg_alpha = fg_alpha;
  403. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  404. SDE_BLEND_BG_MOD_ALPHA |
  405. SDE_BLEND_BG_INV_MOD_ALPHA;
  406. } else {
  407. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  408. }
  409. }
  410. break;
  411. case SDE_DRM_BLEND_OP_SKIP:
  412. SDE_ERROR("skip the blending for plane\n");
  413. return;
  414. default:
  415. /* do nothing */
  416. break;
  417. }
  418. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  419. bg_alpha, blend_op);
  420. SDE_DEBUG(
  421. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  422. (char *) &format->base.pixel_format,
  423. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  424. }
  425. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  426. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  427. struct sde_hw_dim_layer *dim_layer)
  428. {
  429. struct sde_crtc_state *cstate;
  430. struct sde_hw_mixer *lm;
  431. struct sde_hw_dim_layer split_dim_layer;
  432. int i;
  433. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  434. SDE_DEBUG("empty dim_layer\n");
  435. return;
  436. }
  437. cstate = to_sde_crtc_state(crtc->state);
  438. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  439. dim_layer->flags, dim_layer->stage);
  440. split_dim_layer.stage = dim_layer->stage;
  441. split_dim_layer.color_fill = dim_layer->color_fill;
  442. /*
  443. * traverse through the layer mixers attached to crtc and find the
  444. * intersecting dim layer rect in each LM and program accordingly.
  445. */
  446. for (i = 0; i < sde_crtc->num_mixers; i++) {
  447. split_dim_layer.flags = dim_layer->flags;
  448. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  449. &split_dim_layer.rect);
  450. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  451. /*
  452. * no extra programming required for non-intersecting
  453. * layer mixers with INCLUSIVE dim layer
  454. */
  455. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  456. continue;
  457. /*
  458. * program the other non-intersecting layer mixers with
  459. * INCLUSIVE dim layer of full size for uniformity
  460. * with EXCLUSIVE dim layer config.
  461. */
  462. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  463. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  464. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  465. sizeof(split_dim_layer.rect));
  466. } else {
  467. split_dim_layer.rect.x =
  468. split_dim_layer.rect.x -
  469. cstate->lm_roi[i].x;
  470. split_dim_layer.rect.y =
  471. split_dim_layer.rect.y -
  472. cstate->lm_roi[i].y;
  473. }
  474. SDE_EVT32_VERBOSE(DRMID(crtc),
  475. cstate->lm_roi[i].x,
  476. cstate->lm_roi[i].y,
  477. cstate->lm_roi[i].w,
  478. cstate->lm_roi[i].h,
  479. dim_layer->rect.x,
  480. dim_layer->rect.y,
  481. dim_layer->rect.w,
  482. dim_layer->rect.h,
  483. split_dim_layer.rect.x,
  484. split_dim_layer.rect.y,
  485. split_dim_layer.rect.w,
  486. split_dim_layer.rect.h);
  487. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  488. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  489. split_dim_layer.rect.w, split_dim_layer.rect.h);
  490. lm = mixer[i].hw_lm;
  491. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  492. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  493. }
  494. }
  495. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  496. const struct sde_rect **crtc_roi)
  497. {
  498. struct sde_crtc_state *crtc_state;
  499. if (!state || !crtc_roi)
  500. return;
  501. crtc_state = to_sde_crtc_state(state);
  502. *crtc_roi = &crtc_state->crtc_roi;
  503. }
  504. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  505. {
  506. struct sde_crtc_state *cstate;
  507. struct sde_crtc *sde_crtc;
  508. if (!state || !state->crtc)
  509. return false;
  510. sde_crtc = to_sde_crtc(state->crtc);
  511. cstate = to_sde_crtc_state(state);
  512. return msm_property_is_dirty(&sde_crtc->property_info,
  513. &cstate->property_state, CRTC_PROP_ROI_V1);
  514. }
  515. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  516. void __user *usr_ptr)
  517. {
  518. struct drm_crtc *crtc;
  519. struct sde_crtc_state *cstate;
  520. struct sde_drm_roi_v1 roi_v1;
  521. int i;
  522. if (!state) {
  523. SDE_ERROR("invalid args\n");
  524. return -EINVAL;
  525. }
  526. cstate = to_sde_crtc_state(state);
  527. crtc = cstate->base.crtc;
  528. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  529. if (!usr_ptr) {
  530. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  531. return 0;
  532. }
  533. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  534. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  535. return -EINVAL;
  536. }
  537. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  538. if (roi_v1.num_rects == 0) {
  539. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  540. return 0;
  541. }
  542. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  543. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  544. roi_v1.num_rects);
  545. return -EINVAL;
  546. }
  547. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  548. for (i = 0; i < roi_v1.num_rects; ++i) {
  549. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  550. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  551. DRMID(crtc), i,
  552. cstate->user_roi_list.roi[i].x1,
  553. cstate->user_roi_list.roi[i].y1,
  554. cstate->user_roi_list.roi[i].x2,
  555. cstate->user_roi_list.roi[i].y2);
  556. SDE_EVT32_VERBOSE(DRMID(crtc),
  557. cstate->user_roi_list.roi[i].x1,
  558. cstate->user_roi_list.roi[i].y1,
  559. cstate->user_roi_list.roi[i].x2,
  560. cstate->user_roi_list.roi[i].y2);
  561. }
  562. return 0;
  563. }
  564. static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state)
  565. {
  566. int i;
  567. struct sde_crtc_state *cstate;
  568. bool is_3dmux_dsc = false;
  569. cstate = to_sde_crtc_state(state);
  570. for (i = 0; i < cstate->num_connectors; i++) {
  571. struct drm_connector *conn = cstate->connectors[i];
  572. if (sde_connector_get_topology_name(conn) ==
  573. SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC)
  574. is_3dmux_dsc = true;
  575. }
  576. return is_3dmux_dsc;
  577. }
  578. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  579. struct drm_crtc_state *state)
  580. {
  581. struct drm_connector *conn;
  582. struct drm_connector_state *conn_state;
  583. struct sde_crtc *sde_crtc;
  584. struct sde_crtc_state *crtc_state;
  585. struct sde_rect *crtc_roi;
  586. struct msm_mode_info mode_info;
  587. int i = 0;
  588. int rc;
  589. bool is_crtc_roi_dirty;
  590. bool is_any_conn_roi_dirty;
  591. if (!crtc || !state)
  592. return -EINVAL;
  593. sde_crtc = to_sde_crtc(crtc);
  594. crtc_state = to_sde_crtc_state(state);
  595. crtc_roi = &crtc_state->crtc_roi;
  596. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  597. is_any_conn_roi_dirty = false;
  598. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  599. struct sde_connector *sde_conn;
  600. struct sde_connector_state *sde_conn_state;
  601. struct sde_rect conn_roi;
  602. if (!conn_state || conn_state->crtc != crtc)
  603. continue;
  604. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  605. if (rc) {
  606. SDE_ERROR("failed to get mode info\n");
  607. return -EINVAL;
  608. }
  609. sde_conn = to_sde_connector(conn_state->connector);
  610. sde_conn_state = to_sde_connector_state(conn_state);
  611. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  612. msm_property_is_dirty(
  613. &sde_conn->property_info,
  614. &sde_conn_state->property_state,
  615. CONNECTOR_PROP_ROI_V1);
  616. if (!mode_info.roi_caps.enabled)
  617. continue;
  618. /*
  619. * current driver only supports same connector and crtc size,
  620. * but if support for different sizes is added, driver needs
  621. * to check the connector roi here to make sure is full screen
  622. * for dsc 3d-mux topology that doesn't support partial update.
  623. */
  624. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  625. sizeof(crtc_state->user_roi_list))) {
  626. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  627. sde_crtc->name);
  628. return -EINVAL;
  629. }
  630. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  631. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  632. conn_roi.x, conn_roi.y,
  633. conn_roi.w, conn_roi.h);
  634. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  635. conn_roi.x, conn_roi.y,
  636. conn_roi.w, conn_roi.h);
  637. }
  638. /*
  639. * Check against CRTC ROI and Connector ROI not being updated together.
  640. * This restriction should be relaxed when Connector ROI scaling is
  641. * supported.
  642. */
  643. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  644. SDE_ERROR("connector/crtc rois not updated together\n");
  645. return -EINVAL;
  646. }
  647. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  648. /* clear the ROI to null if it matches full screen anyways */
  649. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  650. crtc_roi->w == state->adjusted_mode.hdisplay &&
  651. crtc_roi->h == state->adjusted_mode.vdisplay)
  652. memset(crtc_roi, 0, sizeof(*crtc_roi));
  653. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  654. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  655. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  656. crtc_roi->h);
  657. return 0;
  658. }
  659. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  660. struct drm_crtc_state *state)
  661. {
  662. struct sde_crtc *sde_crtc;
  663. struct sde_crtc_state *crtc_state;
  664. struct drm_connector *conn;
  665. struct drm_connector_state *conn_state;
  666. int i;
  667. if (!crtc || !state)
  668. return -EINVAL;
  669. sde_crtc = to_sde_crtc(crtc);
  670. crtc_state = to_sde_crtc_state(state);
  671. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  672. return 0;
  673. /* partial update active, check if autorefresh is also requested */
  674. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  675. uint64_t autorefresh;
  676. if (!conn_state || conn_state->crtc != crtc)
  677. continue;
  678. autorefresh = sde_connector_get_property(conn_state,
  679. CONNECTOR_PROP_AUTOREFRESH);
  680. if (autorefresh) {
  681. SDE_ERROR(
  682. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  683. sde_crtc->name, autorefresh);
  684. return -EINVAL;
  685. }
  686. }
  687. return 0;
  688. }
  689. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  690. struct drm_crtc_state *state, int lm_idx)
  691. {
  692. struct sde_crtc *sde_crtc;
  693. struct sde_crtc_state *crtc_state;
  694. const struct sde_rect *crtc_roi;
  695. const struct sde_rect *lm_bounds;
  696. struct sde_rect *lm_roi;
  697. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  698. return -EINVAL;
  699. sde_crtc = to_sde_crtc(crtc);
  700. crtc_state = to_sde_crtc_state(state);
  701. crtc_roi = &crtc_state->crtc_roi;
  702. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  703. lm_roi = &crtc_state->lm_roi[lm_idx];
  704. if (sde_kms_rect_is_null(crtc_roi))
  705. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  706. else
  707. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  708. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  709. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  710. /*
  711. * partial update is not supported with 3dmux dsc or dest scaler.
  712. * hence, crtc roi must match the mixer dimensions.
  713. */
  714. if (crtc_state->num_ds_enabled ||
  715. _sde_crtc_setup_is_3dmux_dsc(state)) {
  716. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  717. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  718. return -EINVAL;
  719. }
  720. }
  721. /* if any dimension is zero, clear all dimensions for clarity */
  722. if (sde_kms_rect_is_null(lm_roi))
  723. memset(lm_roi, 0, sizeof(*lm_roi));
  724. return 0;
  725. }
  726. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  727. struct drm_crtc_state *state)
  728. {
  729. struct sde_crtc *sde_crtc;
  730. struct sde_crtc_state *crtc_state;
  731. u32 disp_bitmask = 0;
  732. int i;
  733. if (!crtc || !state) {
  734. pr_err("Invalid crtc or state\n");
  735. return 0;
  736. }
  737. sde_crtc = to_sde_crtc(crtc);
  738. crtc_state = to_sde_crtc_state(state);
  739. /* pingpong split: one ROI, one LM, two physical displays */
  740. if (crtc_state->is_ppsplit) {
  741. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  742. struct sde_rect *roi = &crtc_state->lm_roi[0];
  743. if (sde_kms_rect_is_null(roi))
  744. disp_bitmask = 0;
  745. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  746. disp_bitmask = BIT(0); /* left only */
  747. else if (roi->x >= lm_split_width)
  748. disp_bitmask = BIT(1); /* right only */
  749. else
  750. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  751. } else {
  752. for (i = 0; i < sde_crtc->num_mixers; i++) {
  753. if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i]))
  754. disp_bitmask |= BIT(i);
  755. }
  756. }
  757. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  758. return disp_bitmask;
  759. }
  760. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  761. struct drm_crtc_state *state)
  762. {
  763. struct sde_crtc *sde_crtc;
  764. struct sde_crtc_state *crtc_state;
  765. const struct sde_rect *roi[CRTC_DUAL_MIXERS];
  766. if (!crtc || !state)
  767. return -EINVAL;
  768. sde_crtc = to_sde_crtc(crtc);
  769. crtc_state = to_sde_crtc_state(state);
  770. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  771. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  772. sde_crtc->name, sde_crtc->num_mixers);
  773. return -EINVAL;
  774. }
  775. /*
  776. * If using pingpong split: one ROI, one LM, two physical displays
  777. * then the ROI must be centered on the panel split boundary and
  778. * be of equal width across the split.
  779. */
  780. if (crtc_state->is_ppsplit) {
  781. u16 panel_split_width;
  782. u32 display_mask;
  783. roi[0] = &crtc_state->lm_roi[0];
  784. if (sde_kms_rect_is_null(roi[0]))
  785. return 0;
  786. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  787. if (display_mask != (BIT(0) | BIT(1)))
  788. return 0;
  789. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  790. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  791. SDE_ERROR("%s: roi x %d w %d split %d\n",
  792. sde_crtc->name, roi[0]->x, roi[0]->w,
  793. panel_split_width);
  794. return -EINVAL;
  795. }
  796. return 0;
  797. }
  798. /*
  799. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  800. * LMs and be of equal width.
  801. */
  802. if (sde_crtc->num_mixers < 2)
  803. return 0;
  804. roi[0] = &crtc_state->lm_roi[0];
  805. roi[1] = &crtc_state->lm_roi[1];
  806. /* if one of the roi is null it's a left/right-only update */
  807. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  808. return 0;
  809. /* check lm rois are equal width & first roi ends at 2nd roi */
  810. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  811. SDE_ERROR(
  812. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  813. sde_crtc->name, roi[0]->x, roi[0]->w,
  814. roi[1]->x, roi[1]->w);
  815. return -EINVAL;
  816. }
  817. return 0;
  818. }
  819. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  820. struct drm_crtc_state *state)
  821. {
  822. struct sde_crtc *sde_crtc;
  823. struct sde_crtc_state *crtc_state;
  824. const struct sde_rect *crtc_roi;
  825. const struct drm_plane_state *pstate;
  826. struct drm_plane *plane;
  827. if (!crtc || !state)
  828. return -EINVAL;
  829. /*
  830. * Reject commit if a Plane CRTC destination coordinates fall outside
  831. * the partial CRTC ROI. LM output is determined via connector ROIs,
  832. * if they are specified, not Plane CRTC ROIs.
  833. */
  834. sde_crtc = to_sde_crtc(crtc);
  835. crtc_state = to_sde_crtc_state(state);
  836. crtc_roi = &crtc_state->crtc_roi;
  837. if (sde_kms_rect_is_null(crtc_roi))
  838. return 0;
  839. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  840. struct sde_rect plane_roi, intersection;
  841. if (IS_ERR_OR_NULL(pstate)) {
  842. int rc = PTR_ERR(pstate);
  843. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  844. sde_crtc->name, plane->base.id, rc);
  845. return rc;
  846. }
  847. plane_roi.x = pstate->crtc_x;
  848. plane_roi.y = pstate->crtc_y;
  849. plane_roi.w = pstate->crtc_w;
  850. plane_roi.h = pstate->crtc_h;
  851. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  852. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  853. SDE_ERROR(
  854. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  855. sde_crtc->name, plane->base.id,
  856. plane_roi.x, plane_roi.y,
  857. plane_roi.w, plane_roi.h,
  858. crtc_roi->x, crtc_roi->y,
  859. crtc_roi->w, crtc_roi->h);
  860. return -E2BIG;
  861. }
  862. }
  863. return 0;
  864. }
  865. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  866. struct drm_crtc_state *state)
  867. {
  868. struct sde_crtc *sde_crtc;
  869. struct sde_crtc_state *sde_crtc_state;
  870. struct msm_mode_info mode_info;
  871. int rc, lm_idx, i;
  872. if (!crtc || !state)
  873. return -EINVAL;
  874. memset(&mode_info, 0, sizeof(mode_info));
  875. sde_crtc = to_sde_crtc(crtc);
  876. sde_crtc_state = to_sde_crtc_state(state);
  877. /*
  878. * check connector array cached at modeset time since incoming atomic
  879. * state may not include any connectors if they aren't modified
  880. */
  881. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  882. struct drm_connector *conn = sde_crtc_state->connectors[i];
  883. if (!conn || !conn->state)
  884. continue;
  885. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  886. if (rc) {
  887. SDE_ERROR("failed to get mode info\n");
  888. return -EINVAL;
  889. }
  890. if (!mode_info.roi_caps.enabled)
  891. continue;
  892. if (sde_crtc_state->user_roi_list.num_rects >
  893. mode_info.roi_caps.num_roi) {
  894. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  895. sde_crtc_state->user_roi_list.num_rects,
  896. mode_info.roi_caps.num_roi);
  897. return -E2BIG;
  898. }
  899. rc = _sde_crtc_set_crtc_roi(crtc, state);
  900. if (rc)
  901. return rc;
  902. rc = _sde_crtc_check_autorefresh(crtc, state);
  903. if (rc)
  904. return rc;
  905. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  906. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  907. if (rc)
  908. return rc;
  909. }
  910. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  911. if (rc)
  912. return rc;
  913. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  914. if (rc)
  915. return rc;
  916. }
  917. return 0;
  918. }
  919. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  920. {
  921. struct sde_crtc *sde_crtc;
  922. struct sde_crtc_state *crtc_state;
  923. const struct sde_rect *lm_roi;
  924. struct sde_hw_mixer *hw_lm;
  925. int lm_idx, lm_horiz_position;
  926. if (!crtc)
  927. return;
  928. sde_crtc = to_sde_crtc(crtc);
  929. crtc_state = to_sde_crtc_state(crtc->state);
  930. lm_horiz_position = 0;
  931. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  932. struct sde_hw_mixer_cfg cfg;
  933. lm_roi = &crtc_state->lm_roi[lm_idx];
  934. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  935. SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx,
  936. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  937. if (sde_kms_rect_is_null(lm_roi))
  938. continue;
  939. hw_lm->cfg.out_width = lm_roi->w;
  940. hw_lm->cfg.out_height = lm_roi->h;
  941. hw_lm->cfg.right_mixer = lm_horiz_position;
  942. cfg.out_width = lm_roi->w;
  943. cfg.out_height = lm_roi->h;
  944. cfg.right_mixer = lm_horiz_position++;
  945. cfg.flags = 0;
  946. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  947. }
  948. }
  949. struct plane_state {
  950. struct sde_plane_state *sde_pstate;
  951. const struct drm_plane_state *drm_pstate;
  952. int stage;
  953. u32 pipe_id;
  954. };
  955. static int pstate_cmp(const void *a, const void *b)
  956. {
  957. struct plane_state *pa = (struct plane_state *)a;
  958. struct plane_state *pb = (struct plane_state *)b;
  959. int rc = 0;
  960. int pa_zpos, pb_zpos;
  961. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  962. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  963. if (pa_zpos != pb_zpos)
  964. rc = pa_zpos - pb_zpos;
  965. else
  966. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  967. return rc;
  968. }
  969. /*
  970. * validate and set source split:
  971. * use pstates sorted by stage to check planes on same stage
  972. * we assume that all pipes are in source split so its valid to compare
  973. * without taking into account left/right mixer placement
  974. */
  975. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  976. struct plane_state *pstates, int cnt)
  977. {
  978. struct plane_state *prv_pstate, *cur_pstate;
  979. struct sde_rect left_rect, right_rect;
  980. struct sde_kms *sde_kms;
  981. int32_t left_pid, right_pid;
  982. int32_t stage;
  983. int i, rc = 0;
  984. sde_kms = _sde_crtc_get_kms(crtc);
  985. if (!sde_kms || !sde_kms->catalog) {
  986. SDE_ERROR("invalid parameters\n");
  987. return -EINVAL;
  988. }
  989. for (i = 1; i < cnt; i++) {
  990. prv_pstate = &pstates[i - 1];
  991. cur_pstate = &pstates[i];
  992. if (prv_pstate->stage != cur_pstate->stage)
  993. continue;
  994. stage = cur_pstate->stage;
  995. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  996. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  997. prv_pstate->drm_pstate->crtc_y,
  998. prv_pstate->drm_pstate->crtc_w,
  999. prv_pstate->drm_pstate->crtc_h, false);
  1000. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1001. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1002. cur_pstate->drm_pstate->crtc_y,
  1003. cur_pstate->drm_pstate->crtc_w,
  1004. cur_pstate->drm_pstate->crtc_h, false);
  1005. if (right_rect.x < left_rect.x) {
  1006. swap(left_pid, right_pid);
  1007. swap(left_rect, right_rect);
  1008. swap(prv_pstate, cur_pstate);
  1009. }
  1010. /*
  1011. * - planes are enumerated in pipe-priority order such that
  1012. * planes with lower drm_id must be left-most in a shared
  1013. * blend-stage when using source split.
  1014. * - planes in source split must be contiguous in width
  1015. * - planes in source split must have same dest yoff and height
  1016. */
  1017. if ((right_pid < left_pid) &&
  1018. !sde_kms->catalog->pipe_order_type) {
  1019. SDE_ERROR(
  1020. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1021. stage, left_pid, right_pid);
  1022. return -EINVAL;
  1023. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1024. SDE_ERROR(
  1025. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1026. stage, left_rect.x, left_rect.w,
  1027. right_rect.x, right_rect.w);
  1028. return -EINVAL;
  1029. } else if ((left_rect.y != right_rect.y) ||
  1030. (left_rect.h != right_rect.h)) {
  1031. SDE_ERROR(
  1032. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1033. stage, left_rect.y, left_rect.h,
  1034. right_rect.y, right_rect.h);
  1035. return -EINVAL;
  1036. }
  1037. }
  1038. return rc;
  1039. }
  1040. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1041. struct plane_state *pstates, int cnt)
  1042. {
  1043. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1044. struct sde_kms *sde_kms;
  1045. struct sde_rect left_rect, right_rect;
  1046. int32_t left_pid, right_pid;
  1047. int32_t stage;
  1048. int i;
  1049. sde_kms = _sde_crtc_get_kms(crtc);
  1050. if (!sde_kms || !sde_kms->catalog) {
  1051. SDE_ERROR("invalid parameters\n");
  1052. return;
  1053. }
  1054. if (!sde_kms->catalog->pipe_order_type)
  1055. return;
  1056. for (i = 0; i < cnt; i++) {
  1057. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1058. cur_pstate = &pstates[i];
  1059. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1060. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)) {
  1061. /*
  1062. * reset if prv or nxt pipes are not in the same stage
  1063. * as the cur pipe
  1064. */
  1065. if ((!nxt_pstate)
  1066. || (nxt_pstate->stage != cur_pstate->stage))
  1067. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1068. continue;
  1069. }
  1070. stage = cur_pstate->stage;
  1071. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1072. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1073. prv_pstate->drm_pstate->crtc_y,
  1074. prv_pstate->drm_pstate->crtc_w,
  1075. prv_pstate->drm_pstate->crtc_h, false);
  1076. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1077. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1078. cur_pstate->drm_pstate->crtc_y,
  1079. cur_pstate->drm_pstate->crtc_w,
  1080. cur_pstate->drm_pstate->crtc_h, false);
  1081. if (right_rect.x < left_rect.x) {
  1082. swap(left_pid, right_pid);
  1083. swap(left_rect, right_rect);
  1084. swap(prv_pstate, cur_pstate);
  1085. }
  1086. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1087. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1088. }
  1089. for (i = 0; i < cnt; i++) {
  1090. cur_pstate = &pstates[i];
  1091. sde_plane_setup_src_split_order(
  1092. cur_pstate->drm_pstate->plane,
  1093. cur_pstate->sde_pstate->multirect_index,
  1094. cur_pstate->sde_pstate->pipe_order_flags);
  1095. }
  1096. }
  1097. static void __sde_crtc_assign_active_cfg(struct sde_crtc *sdecrtc,
  1098. struct drm_plane *plane)
  1099. {
  1100. u8 found = 0;
  1101. int i;
  1102. for (i = 0; i < SDE_STAGE_MAX; i++) {
  1103. if (sdecrtc->active_cfg.stage[i][0] == SSPP_NONE) {
  1104. found = 1;
  1105. break;
  1106. }
  1107. }
  1108. if (!found) {
  1109. SDE_ERROR("All active configs are allocated\n");
  1110. return;
  1111. }
  1112. sdecrtc->active_cfg.stage[i][0] = sde_plane_pipe(plane);
  1113. }
  1114. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1115. int num_mixers, struct plane_state *pstates, int cnt)
  1116. {
  1117. int i, lm_idx;
  1118. struct sde_format *format;
  1119. bool blend_stage[SDE_STAGE_MAX] = { false };
  1120. u32 blend_type;
  1121. for (i = cnt - 1; i >= 0; i--) {
  1122. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1123. PLANE_PROP_BLEND_OP);
  1124. /* stage has already been programmed or BLEND_OP_SKIP type */
  1125. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1126. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1127. continue;
  1128. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1129. format = to_sde_format(msm_framebuffer_format(
  1130. pstates[i].sde_pstate->base.fb));
  1131. if (!format) {
  1132. SDE_ERROR("invalid format\n");
  1133. return;
  1134. }
  1135. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1136. pstates[i].sde_pstate, format);
  1137. blend_stage[pstates[i].sde_pstate->stage] = true;
  1138. }
  1139. }
  1140. }
  1141. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1142. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1143. struct sde_crtc_mixer *mixer)
  1144. {
  1145. struct drm_plane *plane;
  1146. struct drm_framebuffer *fb;
  1147. struct drm_plane_state *state;
  1148. struct sde_crtc_state *cstate;
  1149. struct sde_plane_state *pstate = NULL;
  1150. struct plane_state *pstates = NULL;
  1151. struct sde_format *format;
  1152. struct sde_hw_ctl *ctl;
  1153. struct sde_hw_mixer *lm;
  1154. struct sde_hw_stage_cfg *stage_cfg;
  1155. struct sde_rect plane_crtc_roi;
  1156. uint32_t stage_idx, lm_idx;
  1157. int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 };
  1158. int i, cnt = 0;
  1159. bool bg_alpha_enable = false;
  1160. u32 blend_type;
  1161. if (!sde_crtc || !crtc->state || !mixer) {
  1162. SDE_ERROR("invalid sde_crtc or mixer\n");
  1163. return;
  1164. }
  1165. ctl = mixer->hw_ctl;
  1166. lm = mixer->hw_lm;
  1167. stage_cfg = &sde_crtc->stage_cfg;
  1168. cstate = to_sde_crtc_state(crtc->state);
  1169. pstates = kcalloc(SDE_PSTATES_MAX,
  1170. sizeof(struct plane_state), GFP_KERNEL);
  1171. if (!pstates)
  1172. return;
  1173. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1174. state = plane->state;
  1175. if (!state)
  1176. continue;
  1177. plane_crtc_roi.x = state->crtc_x;
  1178. plane_crtc_roi.y = state->crtc_y;
  1179. plane_crtc_roi.w = state->crtc_w;
  1180. plane_crtc_roi.h = state->crtc_h;
  1181. pstate = to_sde_plane_state(state);
  1182. fb = state->fb;
  1183. sde_plane_ctl_flush(plane, ctl, true);
  1184. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1185. crtc->base.id,
  1186. pstate->stage,
  1187. plane->base.id,
  1188. sde_plane_pipe(plane) - SSPP_VIG0,
  1189. state->fb ? state->fb->base.id : -1);
  1190. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1191. if (!format) {
  1192. SDE_ERROR("invalid format\n");
  1193. goto end;
  1194. }
  1195. blend_type = sde_plane_get_property(pstate,
  1196. PLANE_PROP_BLEND_OP);
  1197. if (blend_type == SDE_DRM_BLEND_OP_SKIP) {
  1198. __sde_crtc_assign_active_cfg(sde_crtc, plane);
  1199. } else {
  1200. if (pstate->stage == SDE_STAGE_BASE &&
  1201. format->alpha_enable)
  1202. bg_alpha_enable = true;
  1203. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1204. state->fb ? state->fb->base.id : -1,
  1205. state->src_x >> 16, state->src_y >> 16,
  1206. state->src_w >> 16, state->src_h >> 16,
  1207. state->crtc_x, state->crtc_y,
  1208. state->crtc_w, state->crtc_h,
  1209. pstate->rotation);
  1210. stage_idx = zpos_cnt[pstate->stage]++;
  1211. stage_cfg->stage[pstate->stage][stage_idx] =
  1212. sde_plane_pipe(plane);
  1213. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1214. pstate->multirect_index;
  1215. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1216. sde_plane_pipe(plane) - SSPP_VIG0,
  1217. pstate->stage,
  1218. pstate->multirect_index,
  1219. pstate->multirect_mode,
  1220. format->base.pixel_format,
  1221. fb ? fb->modifier : 0);
  1222. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1223. lm_idx++) {
  1224. if (bg_alpha_enable && !format->alpha_enable)
  1225. mixer[lm_idx].mixer_op_mode = 0;
  1226. else
  1227. mixer[lm_idx].mixer_op_mode |=
  1228. 1 << pstate->stage;
  1229. }
  1230. }
  1231. if (cnt >= SDE_PSTATES_MAX)
  1232. continue;
  1233. pstates[cnt].sde_pstate = pstate;
  1234. pstates[cnt].drm_pstate = state;
  1235. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1236. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1237. else
  1238. pstates[cnt].stage = sde_plane_get_property(
  1239. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1240. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1241. cnt++;
  1242. }
  1243. /* blend config update */
  1244. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1245. pstates, cnt);
  1246. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1247. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1248. if (lm && lm->ops.setup_dim_layer) {
  1249. cstate = to_sde_crtc_state(crtc->state);
  1250. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1251. for (i = 0; i < cstate->num_dim_layers; i++)
  1252. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1253. mixer, &cstate->dim_layer[i]);
  1254. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1255. }
  1256. }
  1257. _sde_crtc_program_lm_output_roi(crtc);
  1258. end:
  1259. kfree(pstates);
  1260. }
  1261. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1262. struct drm_crtc *crtc)
  1263. {
  1264. struct sde_crtc *sde_crtc;
  1265. struct sde_crtc_state *cstate;
  1266. struct drm_encoder *drm_enc;
  1267. bool is_right_only;
  1268. bool encoder_in_dsc_merge = false;
  1269. if (!crtc || !crtc->state)
  1270. return;
  1271. sde_crtc = to_sde_crtc(crtc);
  1272. cstate = to_sde_crtc_state(crtc->state);
  1273. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS)
  1274. return;
  1275. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1276. crtc->state->encoder_mask) {
  1277. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1278. encoder_in_dsc_merge = true;
  1279. break;
  1280. }
  1281. }
  1282. /**
  1283. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1284. * This is due to two reasons:
  1285. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1286. * the left DSC must be used, right DSC cannot be used alone.
  1287. * For right-only partial update, this means swap layer mixers to map
  1288. * Left LM to Right INTF. On later HW this was relaxed.
  1289. * - In DSC Merge mode, the physical encoder has already registered
  1290. * PP0 as the master, to switch to right-only we would have to
  1291. * reprogram to be driven by PP1 instead.
  1292. * To support both cases, we prefer to support the mixer swap solution.
  1293. */
  1294. if (!encoder_in_dsc_merge)
  1295. return;
  1296. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1297. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1298. if (is_right_only && !sde_crtc->mixers_swapped) {
  1299. /* right-only update swap mixers */
  1300. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1301. sde_crtc->mixers_swapped = true;
  1302. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1303. /* left-only or full update, swap back */
  1304. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1305. sde_crtc->mixers_swapped = false;
  1306. }
  1307. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1308. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1309. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1310. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1311. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1312. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1313. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1314. }
  1315. /**
  1316. * _sde_crtc_blend_setup - configure crtc mixers
  1317. * @crtc: Pointer to drm crtc structure
  1318. * @old_state: Pointer to old crtc state
  1319. * @add_planes: Whether or not to add planes to mixers
  1320. */
  1321. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1322. struct drm_crtc_state *old_state, bool add_planes)
  1323. {
  1324. struct sde_crtc *sde_crtc;
  1325. struct sde_crtc_state *sde_crtc_state;
  1326. struct sde_crtc_mixer *mixer;
  1327. struct sde_hw_ctl *ctl;
  1328. struct sde_hw_mixer *lm;
  1329. struct sde_ctl_flush_cfg cfg = {0,};
  1330. int i;
  1331. if (!crtc)
  1332. return;
  1333. sde_crtc = to_sde_crtc(crtc);
  1334. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1335. mixer = sde_crtc->mixers;
  1336. SDE_DEBUG("%s\n", sde_crtc->name);
  1337. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1338. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1339. return;
  1340. }
  1341. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1342. if (!mixer[i].hw_lm) {
  1343. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1344. return;
  1345. }
  1346. mixer[i].mixer_op_mode = 0;
  1347. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1348. sde_crtc_state->dirty)) {
  1349. /* clear dim_layer settings */
  1350. lm = mixer[i].hw_lm;
  1351. if (lm->ops.clear_dim_layer)
  1352. lm->ops.clear_dim_layer(lm);
  1353. }
  1354. }
  1355. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1356. /* initialize stage cfg */
  1357. memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
  1358. memset(&sde_crtc->active_cfg, 0, sizeof(sde_crtc->active_cfg));
  1359. if (add_planes)
  1360. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1361. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1362. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1363. ctl = mixer[i].hw_ctl;
  1364. lm = mixer[i].hw_lm;
  1365. if (sde_kms_rect_is_null(lm_roi)) {
  1366. SDE_DEBUG(
  1367. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1368. sde_crtc->name, lm->idx - LM_0,
  1369. ctl->idx - CTL_0);
  1370. continue;
  1371. }
  1372. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1373. /* stage config flush mask */
  1374. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1375. ctl->ops.get_pending_flush(ctl, &cfg);
  1376. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1377. mixer[i].hw_lm->idx - LM_0,
  1378. mixer[i].mixer_op_mode,
  1379. ctl->idx - CTL_0,
  1380. cfg.pending_flush_mask);
  1381. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1382. &sde_crtc->stage_cfg, &sde_crtc->active_cfg);
  1383. }
  1384. _sde_crtc_program_lm_output_roi(crtc);
  1385. }
  1386. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1387. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1388. {
  1389. struct drm_plane *plane;
  1390. struct sde_plane_state *sde_pstate;
  1391. uint32_t mode = 0;
  1392. int rc;
  1393. if (!crtc) {
  1394. SDE_ERROR("invalid state\n");
  1395. return -EINVAL;
  1396. }
  1397. *fb_ns = 0;
  1398. *fb_sec = 0;
  1399. *fb_sec_dir = 0;
  1400. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1401. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1402. rc = PTR_ERR(plane);
  1403. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1404. DRMID(crtc), DRMID(plane), rc);
  1405. return rc;
  1406. }
  1407. sde_pstate = to_sde_plane_state(plane->state);
  1408. mode = sde_plane_get_property(sde_pstate,
  1409. PLANE_PROP_FB_TRANSLATION_MODE);
  1410. switch (mode) {
  1411. case SDE_DRM_FB_NON_SEC:
  1412. (*fb_ns)++;
  1413. break;
  1414. case SDE_DRM_FB_SEC:
  1415. (*fb_sec)++;
  1416. break;
  1417. case SDE_DRM_FB_SEC_DIR_TRANS:
  1418. (*fb_sec_dir)++;
  1419. break;
  1420. default:
  1421. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1422. DRMID(plane), mode);
  1423. return -EINVAL;
  1424. }
  1425. }
  1426. return 0;
  1427. }
  1428. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1429. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1430. {
  1431. struct drm_plane *plane;
  1432. const struct drm_plane_state *pstate;
  1433. struct sde_plane_state *sde_pstate;
  1434. uint32_t mode = 0;
  1435. int rc;
  1436. if (!state) {
  1437. SDE_ERROR("invalid state\n");
  1438. return -EINVAL;
  1439. }
  1440. *fb_ns = 0;
  1441. *fb_sec = 0;
  1442. *fb_sec_dir = 0;
  1443. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1444. if (IS_ERR_OR_NULL(pstate)) {
  1445. rc = PTR_ERR(pstate);
  1446. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1447. DRMID(state->crtc), DRMID(plane), rc);
  1448. return rc;
  1449. }
  1450. sde_pstate = to_sde_plane_state(pstate);
  1451. mode = sde_plane_get_property(sde_pstate,
  1452. PLANE_PROP_FB_TRANSLATION_MODE);
  1453. switch (mode) {
  1454. case SDE_DRM_FB_NON_SEC:
  1455. (*fb_ns)++;
  1456. break;
  1457. case SDE_DRM_FB_SEC:
  1458. (*fb_sec)++;
  1459. break;
  1460. case SDE_DRM_FB_SEC_DIR_TRANS:
  1461. (*fb_sec_dir)++;
  1462. break;
  1463. default:
  1464. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1465. DRMID(plane), mode);
  1466. return -EINVAL;
  1467. }
  1468. }
  1469. return 0;
  1470. }
  1471. static void _sde_drm_fb_sec_dir_trans(
  1472. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1473. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1474. {
  1475. /* secure display usecase */
  1476. if ((smmu_state->state == ATTACHED)
  1477. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1478. smmu_state->state = catalog->sui_ns_allowed ?
  1479. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1480. smmu_state->secure_level = secure_level;
  1481. smmu_state->transition_type = PRE_COMMIT;
  1482. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1483. if (old_valid_fb)
  1484. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1485. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1486. if (catalog->sui_misr_supported)
  1487. smmu_state->sui_misr_state =
  1488. SUI_MISR_ENABLE_REQ;
  1489. /* secure camera usecase */
  1490. } else if (smmu_state->state == ATTACHED) {
  1491. smmu_state->state = DETACH_SEC_REQ;
  1492. smmu_state->secure_level = secure_level;
  1493. smmu_state->transition_type = PRE_COMMIT;
  1494. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1495. }
  1496. }
  1497. static void _sde_drm_fb_transactions(
  1498. struct sde_kms_smmu_state_data *smmu_state,
  1499. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1500. int *ops)
  1501. {
  1502. if (((smmu_state->state == DETACHED)
  1503. || (smmu_state->state == DETACH_ALL_REQ))
  1504. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1505. && ((smmu_state->state == DETACHED_SEC)
  1506. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1507. smmu_state->state = catalog->sui_ns_allowed ?
  1508. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1509. smmu_state->transition_type = post_commit ?
  1510. POST_COMMIT : PRE_COMMIT;
  1511. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1512. if (old_valid_fb)
  1513. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1514. if (catalog->sui_misr_supported)
  1515. smmu_state->sui_misr_state =
  1516. SUI_MISR_DISABLE_REQ;
  1517. } else if ((smmu_state->state == DETACHED_SEC)
  1518. || (smmu_state->state == DETACH_SEC_REQ)) {
  1519. smmu_state->state = ATTACH_SEC_REQ;
  1520. smmu_state->transition_type = post_commit ?
  1521. POST_COMMIT : PRE_COMMIT;
  1522. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1523. if (old_valid_fb)
  1524. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1525. }
  1526. }
  1527. /**
  1528. * sde_crtc_get_secure_transition_ops - determines the operations that
  1529. * need to be performed before transitioning to secure state
  1530. * This function should be called after swapping the new state
  1531. * @crtc: Pointer to drm crtc structure
  1532. * Returns the bitmask of operations need to be performed, -Error in
  1533. * case of error cases
  1534. */
  1535. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1536. struct drm_crtc_state *old_crtc_state,
  1537. bool old_valid_fb)
  1538. {
  1539. struct drm_plane *plane;
  1540. struct drm_encoder *encoder;
  1541. struct sde_crtc *sde_crtc;
  1542. struct sde_kms *sde_kms;
  1543. struct sde_mdss_cfg *catalog;
  1544. struct sde_kms_smmu_state_data *smmu_state;
  1545. uint32_t translation_mode = 0, secure_level;
  1546. int ops = 0;
  1547. bool post_commit = false;
  1548. if (!crtc || !crtc->state) {
  1549. SDE_ERROR("invalid crtc\n");
  1550. return -EINVAL;
  1551. }
  1552. sde_kms = _sde_crtc_get_kms(crtc);
  1553. if (!sde_kms)
  1554. return -EINVAL;
  1555. smmu_state = &sde_kms->smmu_state;
  1556. smmu_state->prev_state = smmu_state->state;
  1557. smmu_state->prev_secure_level = smmu_state->secure_level;
  1558. sde_crtc = to_sde_crtc(crtc);
  1559. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1560. catalog = sde_kms->catalog;
  1561. /*
  1562. * SMMU operations need to be delayed in case of video mode panels
  1563. * when switching back to non_secure mode
  1564. */
  1565. drm_for_each_encoder_mask(encoder, crtc->dev,
  1566. crtc->state->encoder_mask) {
  1567. if (sde_encoder_is_dsi_display(encoder))
  1568. post_commit |= sde_encoder_check_curr_mode(encoder,
  1569. MSM_DISPLAY_VIDEO_MODE);
  1570. }
  1571. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1572. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1573. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1574. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1575. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1576. if (!plane->state)
  1577. continue;
  1578. translation_mode = sde_plane_get_property(
  1579. to_sde_plane_state(plane->state),
  1580. PLANE_PROP_FB_TRANSLATION_MODE);
  1581. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1582. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1583. DRMID(crtc), translation_mode);
  1584. return -EINVAL;
  1585. }
  1586. /* we can break if we find sec_dir plane */
  1587. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1588. break;
  1589. }
  1590. mutex_lock(&sde_kms->secure_transition_lock);
  1591. switch (translation_mode) {
  1592. case SDE_DRM_FB_SEC_DIR_TRANS:
  1593. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1594. catalog, old_valid_fb, &ops);
  1595. break;
  1596. case SDE_DRM_FB_SEC:
  1597. case SDE_DRM_FB_NON_SEC:
  1598. _sde_drm_fb_transactions(smmu_state, catalog,
  1599. old_valid_fb, post_commit, &ops);
  1600. break;
  1601. default:
  1602. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1603. DRMID(crtc), translation_mode);
  1604. ops = -EINVAL;
  1605. }
  1606. /* log only during actual transition times */
  1607. if (ops) {
  1608. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1609. DRMID(crtc), smmu_state->state,
  1610. secure_level, smmu_state->secure_level,
  1611. smmu_state->transition_type, ops);
  1612. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1613. smmu_state->state, smmu_state->transition_type,
  1614. smmu_state->secure_level, old_valid_fb,
  1615. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1616. }
  1617. mutex_unlock(&sde_kms->secure_transition_lock);
  1618. return ops;
  1619. }
  1620. /**
  1621. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1622. * LUTs are configured only once during boot
  1623. * @sde_crtc: Pointer to sde crtc
  1624. * @cstate: Pointer to sde crtc state
  1625. */
  1626. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1627. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1628. {
  1629. struct sde_hw_scaler3_lut_cfg *cfg;
  1630. struct sde_kms *sde_kms;
  1631. u32 *lut_data = NULL;
  1632. size_t len = 0;
  1633. int ret = 0;
  1634. if (!sde_crtc || !cstate) {
  1635. SDE_ERROR("invalid args\n");
  1636. return -EINVAL;
  1637. }
  1638. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1639. if (!sde_kms)
  1640. return -EINVAL;
  1641. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1642. return 0;
  1643. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1644. &cstate->property_state, &len, lut_idx);
  1645. if (!lut_data || !len) {
  1646. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1647. lut_idx, lut_data, len);
  1648. lut_data = NULL;
  1649. len = 0;
  1650. }
  1651. cfg = &cstate->scl3_lut_cfg;
  1652. switch (lut_idx) {
  1653. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1654. cfg->dir_lut = lut_data;
  1655. cfg->dir_len = len;
  1656. break;
  1657. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1658. cfg->cir_lut = lut_data;
  1659. cfg->cir_len = len;
  1660. break;
  1661. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1662. cfg->sep_lut = lut_data;
  1663. cfg->sep_len = len;
  1664. break;
  1665. default:
  1666. ret = -EINVAL;
  1667. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1668. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1669. break;
  1670. }
  1671. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1672. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1673. cfg->is_configured);
  1674. return ret;
  1675. }
  1676. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1677. {
  1678. struct sde_crtc *sde_crtc;
  1679. if (!crtc) {
  1680. SDE_ERROR("invalid crtc\n");
  1681. return;
  1682. }
  1683. sde_crtc = to_sde_crtc(crtc);
  1684. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1685. }
  1686. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1687. {
  1688. int i;
  1689. /**
  1690. * Check if sufficient hw resources are
  1691. * available as per target caps & topology
  1692. */
  1693. if (!sde_crtc) {
  1694. SDE_ERROR("invalid argument\n");
  1695. return -EINVAL;
  1696. }
  1697. if (!sde_crtc->num_mixers ||
  1698. sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1699. SDE_ERROR("%s: invalid number mixers: %d\n",
  1700. sde_crtc->name, sde_crtc->num_mixers);
  1701. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1702. SDE_EVTLOG_ERROR);
  1703. return -EINVAL;
  1704. }
  1705. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1706. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1707. || !sde_crtc->mixers[i].hw_ds) {
  1708. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1709. sde_crtc->name, i);
  1710. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1711. i, sde_crtc->mixers[i].hw_lm,
  1712. sde_crtc->mixers[i].hw_ctl,
  1713. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1714. return -EINVAL;
  1715. }
  1716. }
  1717. return 0;
  1718. }
  1719. /**
  1720. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1721. * @crtc: Pointer to drm crtc
  1722. */
  1723. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1724. {
  1725. struct sde_crtc *sde_crtc;
  1726. struct sde_crtc_state *cstate;
  1727. struct sde_hw_mixer *hw_lm;
  1728. struct sde_hw_ctl *hw_ctl;
  1729. struct sde_hw_ds *hw_ds;
  1730. struct sde_hw_ds_cfg *cfg;
  1731. struct sde_kms *kms;
  1732. u32 op_mode = 0;
  1733. u32 lm_idx = 0, num_mixers = 0;
  1734. int i, count = 0;
  1735. if (!crtc)
  1736. return;
  1737. sde_crtc = to_sde_crtc(crtc);
  1738. cstate = to_sde_crtc_state(crtc->state);
  1739. kms = _sde_crtc_get_kms(crtc);
  1740. num_mixers = sde_crtc->num_mixers;
  1741. count = cstate->num_ds;
  1742. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1743. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1744. cstate->num_ds_enabled);
  1745. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1746. SDE_DEBUG("no change in settings, skip commit\n");
  1747. } else if (!kms || !kms->catalog) {
  1748. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1749. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1750. SDE_DEBUG("dest scaler feature not supported\n");
  1751. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1752. //do nothing
  1753. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1754. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1755. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1756. } else {
  1757. for (i = 0; i < count; i++) {
  1758. cfg = &cstate->ds_cfg[i];
  1759. if (!cfg->flags)
  1760. continue;
  1761. lm_idx = cfg->idx;
  1762. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1763. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1764. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1765. /* Setup op mode - Dual/single */
  1766. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1767. op_mode |= BIT(hw_ds->idx - DS_0);
  1768. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1769. op_mode |= (cstate->num_ds_enabled ==
  1770. CRTC_DUAL_MIXERS) ?
  1771. SDE_DS_OP_MODE_DUAL : 0;
  1772. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1773. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1774. }
  1775. /* Setup scaler */
  1776. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1777. (cfg->flags &
  1778. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1779. if (hw_ds->ops.setup_scaler)
  1780. hw_ds->ops.setup_scaler(hw_ds,
  1781. &cfg->scl3_cfg,
  1782. &cstate->scl3_lut_cfg);
  1783. }
  1784. /*
  1785. * Dest scaler shares the flush bit of the LM in control
  1786. */
  1787. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1788. hw_ctl->ops.update_bitmask_mixer(
  1789. hw_ctl, hw_lm->idx, 1);
  1790. }
  1791. }
  1792. }
  1793. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1794. {
  1795. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1796. struct sde_crtc *sde_crtc;
  1797. struct msm_drm_private *priv;
  1798. struct sde_crtc_frame_event *fevent;
  1799. struct sde_kms_frame_event_cb_data *cb_data;
  1800. struct drm_plane *plane;
  1801. u32 ubwc_error;
  1802. unsigned long flags;
  1803. u32 crtc_id;
  1804. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  1805. if (!data) {
  1806. SDE_ERROR("invalid parameters\n");
  1807. return;
  1808. }
  1809. crtc = cb_data->crtc;
  1810. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1811. SDE_ERROR("invalid parameters\n");
  1812. return;
  1813. }
  1814. sde_crtc = to_sde_crtc(crtc);
  1815. priv = crtc->dev->dev_private;
  1816. crtc_id = drm_crtc_index(crtc);
  1817. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1818. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1819. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1820. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1821. struct sde_crtc_frame_event, list);
  1822. if (fevent)
  1823. list_del_init(&fevent->list);
  1824. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1825. if (!fevent) {
  1826. SDE_ERROR("crtc%d event %d overflow\n",
  1827. crtc->base.id, event);
  1828. SDE_EVT32(DRMID(crtc), event);
  1829. return;
  1830. }
  1831. /* log and clear plane ubwc errors if any */
  1832. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1833. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1834. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1835. drm_for_each_plane_mask(plane, crtc->dev,
  1836. sde_crtc->plane_mask_old) {
  1837. ubwc_error = sde_plane_get_ubwc_error(plane);
  1838. if (ubwc_error) {
  1839. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1840. ubwc_error, SDE_EVTLOG_ERROR);
  1841. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1842. DRMID(crtc), DRMID(plane),
  1843. ubwc_error);
  1844. sde_plane_clear_ubwc_error(plane);
  1845. }
  1846. }
  1847. }
  1848. fevent->event = event;
  1849. fevent->crtc = crtc;
  1850. fevent->connector = cb_data->connector;
  1851. fevent->ts = ktime_get();
  1852. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1853. }
  1854. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1855. struct drm_crtc_state *old_state)
  1856. {
  1857. struct drm_device *dev;
  1858. struct sde_crtc *sde_crtc;
  1859. struct sde_crtc_state *cstate;
  1860. struct drm_connector *conn;
  1861. struct drm_encoder *encoder;
  1862. struct drm_connector_list_iter conn_iter;
  1863. if (!crtc || !crtc->state) {
  1864. SDE_ERROR("invalid crtc\n");
  1865. return;
  1866. }
  1867. dev = crtc->dev;
  1868. sde_crtc = to_sde_crtc(crtc);
  1869. cstate = to_sde_crtc_state(crtc->state);
  1870. SDE_EVT32_VERBOSE(DRMID(crtc));
  1871. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1872. /* identify connectors attached to this crtc */
  1873. cstate->num_connectors = 0;
  1874. drm_connector_list_iter_begin(dev, &conn_iter);
  1875. drm_for_each_connector_iter(conn, &conn_iter)
  1876. if (conn->state && conn->state->crtc == crtc &&
  1877. cstate->num_connectors < MAX_CONNECTORS) {
  1878. encoder = conn->state->best_encoder;
  1879. if (encoder)
  1880. sde_encoder_register_frame_event_callback(
  1881. encoder,
  1882. sde_crtc_frame_event_cb,
  1883. crtc);
  1884. cstate->connectors[cstate->num_connectors++] = conn;
  1885. sde_connector_prepare_fence(conn);
  1886. }
  1887. drm_connector_list_iter_end(&conn_iter);
  1888. /* prepare main output fence */
  1889. sde_fence_prepare(sde_crtc->output_fence);
  1890. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1891. }
  1892. /**
  1893. * sde_crtc_complete_flip - signal pending page_flip events
  1894. * Any pending vblank events are added to the vblank_event_list
  1895. * so that the next vblank interrupt shall signal them.
  1896. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1897. * This API signals any pending PAGE_FLIP events requested through
  1898. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1899. * if file!=NULL, this is preclose potential cancel-flip path
  1900. * @crtc: Pointer to drm crtc structure
  1901. * @file: Pointer to drm file
  1902. */
  1903. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1904. struct drm_file *file)
  1905. {
  1906. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1907. struct drm_device *dev = crtc->dev;
  1908. struct drm_pending_vblank_event *event;
  1909. unsigned long flags;
  1910. spin_lock_irqsave(&dev->event_lock, flags);
  1911. event = sde_crtc->event;
  1912. if (!event)
  1913. goto end;
  1914. /*
  1915. * if regular vblank case (!file) or if cancel-flip from
  1916. * preclose on file that requested flip, then send the
  1917. * event:
  1918. */
  1919. if (!file || (event->base.file_priv == file)) {
  1920. sde_crtc->event = NULL;
  1921. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1922. sde_crtc->name, event);
  1923. SDE_EVT32_VERBOSE(DRMID(crtc));
  1924. drm_crtc_send_vblank_event(crtc, event);
  1925. }
  1926. end:
  1927. spin_unlock_irqrestore(&dev->event_lock, flags);
  1928. }
  1929. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1930. struct drm_crtc_state *cstate)
  1931. {
  1932. struct drm_encoder *encoder;
  1933. if (!crtc || !crtc->dev || !cstate) {
  1934. SDE_ERROR("invalid crtc\n");
  1935. return INTF_MODE_NONE;
  1936. }
  1937. drm_for_each_encoder_mask(encoder, crtc->dev,
  1938. cstate->encoder_mask) {
  1939. /* continue if copy encoder is encountered */
  1940. if (sde_encoder_in_clone_mode(encoder))
  1941. continue;
  1942. return sde_encoder_get_intf_mode(encoder);
  1943. }
  1944. return INTF_MODE_NONE;
  1945. }
  1946. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1947. {
  1948. struct drm_encoder *encoder;
  1949. if (!crtc || !crtc->dev) {
  1950. SDE_ERROR("invalid crtc\n");
  1951. return INTF_MODE_NONE;
  1952. }
  1953. drm_for_each_encoder(encoder, crtc->dev)
  1954. if ((encoder->crtc == crtc)
  1955. && !sde_encoder_in_cont_splash(encoder))
  1956. return sde_encoder_get_fps(encoder);
  1957. return 0;
  1958. }
  1959. static void sde_crtc_vblank_cb(void *data)
  1960. {
  1961. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1962. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1963. /* keep statistics on vblank callback - with auto reset via debugfs */
  1964. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  1965. sde_crtc->vblank_cb_time = ktime_get();
  1966. else
  1967. sde_crtc->vblank_cb_count++;
  1968. sde_crtc->vblank_last_cb_time = ktime_get();
  1969. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  1970. drm_crtc_handle_vblank(crtc);
  1971. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  1972. SDE_EVT32_VERBOSE(DRMID(crtc));
  1973. }
  1974. static void _sde_crtc_retire_event(struct drm_connector *connector,
  1975. ktime_t ts, enum sde_fence_event fence_event)
  1976. {
  1977. if (!connector) {
  1978. SDE_ERROR("invalid param\n");
  1979. return;
  1980. }
  1981. SDE_ATRACE_BEGIN("signal_retire_fence");
  1982. sde_connector_complete_commit(connector, ts, fence_event);
  1983. SDE_ATRACE_END("signal_retire_fence");
  1984. }
  1985. static void sde_crtc_frame_event_work(struct kthread_work *work)
  1986. {
  1987. struct msm_drm_private *priv;
  1988. struct sde_crtc_frame_event *fevent;
  1989. struct drm_crtc *crtc;
  1990. struct sde_crtc *sde_crtc;
  1991. struct sde_kms *sde_kms;
  1992. unsigned long flags;
  1993. bool in_clone_mode = false;
  1994. if (!work) {
  1995. SDE_ERROR("invalid work handle\n");
  1996. return;
  1997. }
  1998. fevent = container_of(work, struct sde_crtc_frame_event, work);
  1999. if (!fevent->crtc || !fevent->crtc->state) {
  2000. SDE_ERROR("invalid crtc\n");
  2001. return;
  2002. }
  2003. crtc = fevent->crtc;
  2004. sde_crtc = to_sde_crtc(crtc);
  2005. sde_kms = _sde_crtc_get_kms(crtc);
  2006. if (!sde_kms) {
  2007. SDE_ERROR("invalid kms handle\n");
  2008. return;
  2009. }
  2010. priv = sde_kms->dev->dev_private;
  2011. SDE_ATRACE_BEGIN("crtc_frame_event");
  2012. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2013. ktime_to_ns(fevent->ts));
  2014. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2015. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2016. true : false;
  2017. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2018. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2019. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2020. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2021. /* this should not happen */
  2022. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2023. crtc->base.id,
  2024. ktime_to_ns(fevent->ts),
  2025. atomic_read(&sde_crtc->frame_pending));
  2026. SDE_EVT32(DRMID(crtc), fevent->event,
  2027. SDE_EVTLOG_FUNC_CASE1);
  2028. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2029. /* release bandwidth and other resources */
  2030. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2031. crtc->base.id,
  2032. ktime_to_ns(fevent->ts));
  2033. SDE_EVT32(DRMID(crtc), fevent->event,
  2034. SDE_EVTLOG_FUNC_CASE2);
  2035. sde_core_perf_crtc_release_bw(crtc);
  2036. } else {
  2037. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2038. SDE_EVTLOG_FUNC_CASE3);
  2039. }
  2040. }
  2041. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2042. SDE_ATRACE_BEGIN("signal_release_fence");
  2043. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2044. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2045. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2046. SDE_ATRACE_END("signal_release_fence");
  2047. }
  2048. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2049. /* this api should be called without spin_lock */
  2050. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2051. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2052. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2053. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2054. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2055. crtc->base.id, ktime_to_ns(fevent->ts));
  2056. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  2057. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2058. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  2059. SDE_ATRACE_END("crtc_frame_event");
  2060. }
  2061. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2062. struct drm_crtc_state *old_state)
  2063. {
  2064. struct sde_crtc *sde_crtc;
  2065. if (!crtc || !crtc->state) {
  2066. SDE_ERROR("invalid crtc\n");
  2067. return;
  2068. }
  2069. sde_crtc = to_sde_crtc(crtc);
  2070. SDE_EVT32_VERBOSE(DRMID(crtc));
  2071. sde_core_perf_crtc_update(crtc, 0, false);
  2072. }
  2073. /**
  2074. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2075. * @cstate: Pointer to sde crtc state
  2076. */
  2077. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2078. {
  2079. if (!cstate) {
  2080. SDE_ERROR("invalid cstate\n");
  2081. return;
  2082. }
  2083. cstate->input_fence_timeout_ns =
  2084. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2085. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2086. }
  2087. /**
  2088. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2089. * @cstate: Pointer to sde crtc state
  2090. */
  2091. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2092. {
  2093. u32 i;
  2094. if (!cstate)
  2095. return;
  2096. for (i = 0; i < cstate->num_dim_layers; i++)
  2097. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2098. cstate->num_dim_layers = 0;
  2099. }
  2100. /**
  2101. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2102. * @cstate: Pointer to sde crtc state
  2103. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2104. */
  2105. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2106. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2107. {
  2108. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2109. struct sde_drm_dim_layer_cfg *user_cfg;
  2110. struct sde_hw_dim_layer *dim_layer;
  2111. u32 count, i;
  2112. struct sde_kms *kms;
  2113. if (!crtc || !cstate) {
  2114. SDE_ERROR("invalid crtc or cstate\n");
  2115. return;
  2116. }
  2117. dim_layer = cstate->dim_layer;
  2118. if (!usr_ptr) {
  2119. /* usr_ptr is null when setting the default property value */
  2120. _sde_crtc_clear_dim_layers_v1(cstate);
  2121. SDE_DEBUG("dim_layer data removed\n");
  2122. goto clear;
  2123. }
  2124. kms = _sde_crtc_get_kms(crtc);
  2125. if (!kms || !kms->catalog) {
  2126. SDE_ERROR("invalid kms\n");
  2127. return;
  2128. }
  2129. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2130. SDE_ERROR("failed to copy dim_layer data\n");
  2131. return;
  2132. }
  2133. count = dim_layer_v1.num_layers;
  2134. if (count > SDE_MAX_DIM_LAYERS) {
  2135. SDE_ERROR("invalid number of dim_layers:%d", count);
  2136. return;
  2137. }
  2138. /* populate from user space */
  2139. cstate->num_dim_layers = count;
  2140. for (i = 0; i < count; i++) {
  2141. user_cfg = &dim_layer_v1.layer_cfg[i];
  2142. dim_layer[i].flags = user_cfg->flags;
  2143. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2144. user_cfg->stage : user_cfg->stage +
  2145. SDE_STAGE_0;
  2146. dim_layer[i].rect.x = user_cfg->rect.x1;
  2147. dim_layer[i].rect.y = user_cfg->rect.y1;
  2148. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2149. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2150. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2151. user_cfg->color_fill.color_0,
  2152. user_cfg->color_fill.color_1,
  2153. user_cfg->color_fill.color_2,
  2154. user_cfg->color_fill.color_3,
  2155. };
  2156. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2157. i, dim_layer[i].flags, dim_layer[i].stage);
  2158. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2159. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2160. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2161. dim_layer[i].color_fill.color_0,
  2162. dim_layer[i].color_fill.color_1,
  2163. dim_layer[i].color_fill.color_2,
  2164. dim_layer[i].color_fill.color_3);
  2165. }
  2166. clear:
  2167. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2168. }
  2169. /**
  2170. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2171. * @sde_crtc : Pointer to sde crtc
  2172. * @cstate : Pointer to sde crtc state
  2173. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2174. */
  2175. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2176. struct sde_crtc_state *cstate,
  2177. void __user *usr_ptr)
  2178. {
  2179. struct sde_drm_dest_scaler_data ds_data;
  2180. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2181. struct sde_drm_scaler_v2 scaler_v2;
  2182. void __user *scaler_v2_usr;
  2183. int i, count;
  2184. if (!sde_crtc || !cstate) {
  2185. SDE_ERROR("invalid sde_crtc/state\n");
  2186. return -EINVAL;
  2187. }
  2188. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2189. if (!usr_ptr) {
  2190. SDE_DEBUG("ds data removed\n");
  2191. return 0;
  2192. }
  2193. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2194. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2195. sde_crtc->name);
  2196. return -EINVAL;
  2197. }
  2198. count = ds_data.num_dest_scaler;
  2199. if (!count) {
  2200. SDE_DEBUG("no ds data available\n");
  2201. return 0;
  2202. }
  2203. if (count > SDE_MAX_DS_COUNT) {
  2204. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2205. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2206. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2207. return -EINVAL;
  2208. }
  2209. /* Populate from user space */
  2210. for (i = 0; i < count; i++) {
  2211. ds_cfg_usr = &ds_data.ds_cfg[i];
  2212. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2213. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2214. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2215. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2216. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2217. if (ds_cfg_usr->scaler_cfg) {
  2218. scaler_v2_usr =
  2219. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2220. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2221. sizeof(scaler_v2))) {
  2222. SDE_ERROR("%s:scaler: copy from user failed\n",
  2223. sde_crtc->name);
  2224. return -EINVAL;
  2225. }
  2226. }
  2227. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2228. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2229. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2230. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2231. scaler_v2.dst_width, scaler_v2.dst_height);
  2232. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2233. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2234. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2235. scaler_v2.dst_width, scaler_v2.dst_height);
  2236. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2237. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2238. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2239. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2240. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2241. ds_cfg_usr->lm_height);
  2242. }
  2243. cstate->num_ds = count;
  2244. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2245. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2246. return 0;
  2247. }
  2248. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2249. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2250. u32 prev_lm_width, u32 prev_lm_height)
  2251. {
  2252. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2253. || !cfg->lm_width || !cfg->lm_height) {
  2254. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2255. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2256. hdisplay, mode->vdisplay);
  2257. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2258. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2259. return -E2BIG;
  2260. }
  2261. if (!prev_lm_width && !prev_lm_height) {
  2262. prev_lm_width = cfg->lm_width;
  2263. prev_lm_height = cfg->lm_height;
  2264. } else {
  2265. if (cfg->lm_width != prev_lm_width ||
  2266. cfg->lm_height != prev_lm_height) {
  2267. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2268. crtc->base.id, cfg->lm_width,
  2269. cfg->lm_height, prev_lm_width,
  2270. prev_lm_height);
  2271. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2272. cfg->lm_height, prev_lm_width,
  2273. prev_lm_height, SDE_EVTLOG_ERROR);
  2274. return -EINVAL;
  2275. }
  2276. }
  2277. return 0;
  2278. }
  2279. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2280. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2281. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2282. u32 max_in_width, u32 max_out_width)
  2283. {
  2284. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2285. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2286. /**
  2287. * Scaler src and dst width shouldn't exceed the maximum
  2288. * width limitation. Also, if there is no partial update
  2289. * dst width and height must match display resolution.
  2290. */
  2291. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2292. cfg->scl3_cfg.dst_width > max_out_width ||
  2293. !cfg->scl3_cfg.src_width[0] ||
  2294. !cfg->scl3_cfg.dst_width ||
  2295. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2296. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2297. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2298. SDE_ERROR("crtc%d: ", crtc->base.id);
  2299. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2300. cfg->scl3_cfg.src_width[0],
  2301. cfg->scl3_cfg.dst_width,
  2302. cfg->scl3_cfg.dst_height,
  2303. hdisplay, mode->vdisplay);
  2304. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2305. sde_crtc->num_mixers, cfg->flags,
  2306. hw_ds->idx - DS_0);
  2307. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2308. cfg->scl3_cfg.enable,
  2309. cfg->scl3_cfg.de.enable);
  2310. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2311. cfg->scl3_cfg.de.enable, cfg->flags,
  2312. max_in_width, max_out_width,
  2313. cfg->scl3_cfg.src_width[0],
  2314. cfg->scl3_cfg.dst_width,
  2315. cfg->scl3_cfg.dst_height, hdisplay,
  2316. mode->vdisplay, sde_crtc->num_mixers,
  2317. SDE_EVTLOG_ERROR);
  2318. cfg->flags &=
  2319. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2320. cfg->flags &=
  2321. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2322. return -EINVAL;
  2323. }
  2324. }
  2325. return 0;
  2326. }
  2327. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2328. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2329. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2330. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2331. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2332. u32 max_out_width)
  2333. {
  2334. int i, ret;
  2335. u32 lm_idx;
  2336. for (i = 0; i < cstate->num_ds; i++) {
  2337. cfg = &cstate->ds_cfg[i];
  2338. lm_idx = cfg->idx;
  2339. /**
  2340. * Validate against topology
  2341. * No of dest scalers should match the num of mixers
  2342. * unless it is partial update left only/right only use case
  2343. */
  2344. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2345. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2346. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2347. crtc->base.id, i, lm_idx, cfg->flags);
  2348. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2349. SDE_EVTLOG_ERROR);
  2350. return -EINVAL;
  2351. }
  2352. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2353. if (!max_in_width && !max_out_width) {
  2354. max_in_width = hw_ds->scl->top->maxinputwidth;
  2355. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2356. if (cstate->num_ds == CRTC_DUAL_MIXERS)
  2357. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2358. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2359. max_in_width, max_out_width, cstate->num_ds);
  2360. }
  2361. /* Check LM width and height */
  2362. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2363. prev_lm_width, prev_lm_height);
  2364. if (ret)
  2365. return ret;
  2366. /* Check scaler data */
  2367. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2368. hw_ds, cfg, hdisplay,
  2369. max_in_width, max_out_width);
  2370. if (ret)
  2371. return ret;
  2372. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2373. (*num_ds_enable)++;
  2374. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2375. hw_ds->idx - DS_0, cfg->flags);
  2376. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2377. }
  2378. return 0;
  2379. }
  2380. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2381. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2382. u32 num_ds_enable)
  2383. {
  2384. int i;
  2385. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2386. cstate->num_ds_enabled, num_ds_enable);
  2387. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2388. cstate->num_ds, cstate->dirty[0]);
  2389. if (cstate->num_ds_enabled != num_ds_enable) {
  2390. /* Disabling destination scaler */
  2391. if (!num_ds_enable) {
  2392. for (i = 0; i < cstate->num_ds; i++) {
  2393. cfg = &cstate->ds_cfg[i];
  2394. cfg->idx = i;
  2395. /* Update scaler settings in disable case */
  2396. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2397. cfg->scl3_cfg.enable = 0;
  2398. cfg->scl3_cfg.de.enable = 0;
  2399. }
  2400. }
  2401. cstate->num_ds_enabled = num_ds_enable;
  2402. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2403. } else {
  2404. if (!cstate->num_ds_enabled)
  2405. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2406. }
  2407. }
  2408. /**
  2409. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2410. * @crtc : Pointer to drm crtc
  2411. * @state : Pointer to drm crtc state
  2412. */
  2413. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2414. struct drm_crtc_state *state)
  2415. {
  2416. struct sde_crtc *sde_crtc;
  2417. struct sde_crtc_state *cstate;
  2418. struct drm_display_mode *mode;
  2419. struct sde_kms *kms;
  2420. struct sde_hw_ds *hw_ds = NULL;
  2421. struct sde_hw_ds_cfg *cfg = NULL;
  2422. u32 ret = 0;
  2423. u32 num_ds_enable = 0, hdisplay = 0;
  2424. u32 max_in_width = 0, max_out_width = 0;
  2425. u32 prev_lm_width = 0, prev_lm_height = 0;
  2426. if (!crtc || !state)
  2427. return -EINVAL;
  2428. sde_crtc = to_sde_crtc(crtc);
  2429. cstate = to_sde_crtc_state(state);
  2430. kms = _sde_crtc_get_kms(crtc);
  2431. mode = &state->adjusted_mode;
  2432. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2433. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2434. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2435. return 0;
  2436. }
  2437. if (!kms || !kms->catalog) {
  2438. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2439. return -EINVAL;
  2440. }
  2441. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2442. SDE_DEBUG("dest scaler feature not supported\n");
  2443. return 0;
  2444. }
  2445. if (!sde_crtc->num_mixers) {
  2446. SDE_DEBUG("mixers not allocated\n");
  2447. return 0;
  2448. }
  2449. ret = _sde_validate_hw_resources(sde_crtc);
  2450. if (ret)
  2451. goto err;
  2452. /**
  2453. * No of dest scalers shouldn't exceed hw ds block count and
  2454. * also, match the num of mixers unless it is partial update
  2455. * left only/right only use case - currently PU + DS is not supported
  2456. */
  2457. if (cstate->num_ds > kms->catalog->ds_count ||
  2458. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2459. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2460. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2461. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2462. cstate->ds_cfg[0].flags);
  2463. ret = -EINVAL;
  2464. goto err;
  2465. }
  2466. /**
  2467. * Check if DS needs to be enabled or disabled
  2468. * In case of enable, validate the data
  2469. */
  2470. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2471. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2472. cstate->num_ds, cstate->ds_cfg[0].flags);
  2473. goto disable;
  2474. }
  2475. /* Display resolution */
  2476. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2477. /* Validate the DS data */
  2478. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2479. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2480. prev_lm_width, prev_lm_height,
  2481. max_in_width, max_out_width);
  2482. if (ret)
  2483. goto err;
  2484. disable:
  2485. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2486. num_ds_enable);
  2487. return 0;
  2488. err:
  2489. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2490. return ret;
  2491. }
  2492. /**
  2493. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2494. * @crtc: Pointer to CRTC object
  2495. */
  2496. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2497. {
  2498. struct drm_plane *plane = NULL;
  2499. uint32_t wait_ms = 1;
  2500. ktime_t kt_end, kt_wait;
  2501. int rc = 0;
  2502. SDE_DEBUG("\n");
  2503. if (!crtc || !crtc->state) {
  2504. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2505. return;
  2506. }
  2507. /* use monotonic timer to limit total fence wait time */
  2508. kt_end = ktime_add_ns(ktime_get(),
  2509. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2510. /*
  2511. * Wait for fences sequentially, as all of them need to be signalled
  2512. * before we can proceed.
  2513. *
  2514. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2515. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2516. * that each plane can check its fence status and react appropriately
  2517. * if its fence has timed out. Call input fence wait multiple times if
  2518. * fence wait is interrupted due to interrupt call.
  2519. */
  2520. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2521. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2522. do {
  2523. kt_wait = ktime_sub(kt_end, ktime_get());
  2524. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2525. wait_ms = ktime_to_ms(kt_wait);
  2526. else
  2527. wait_ms = 0;
  2528. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2529. } while (wait_ms && rc == -ERESTARTSYS);
  2530. }
  2531. SDE_ATRACE_END("plane_wait_input_fence");
  2532. }
  2533. static void _sde_crtc_setup_mixer_for_encoder(
  2534. struct drm_crtc *crtc,
  2535. struct drm_encoder *enc)
  2536. {
  2537. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2538. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2539. struct sde_rm *rm = &sde_kms->rm;
  2540. struct sde_crtc_mixer *mixer;
  2541. struct sde_hw_ctl *last_valid_ctl = NULL;
  2542. int i;
  2543. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2544. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2545. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2546. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2547. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2548. /* Set up all the mixers and ctls reserved by this encoder */
  2549. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2550. mixer = &sde_crtc->mixers[i];
  2551. if (!sde_rm_get_hw(rm, &lm_iter))
  2552. break;
  2553. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2554. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2555. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2556. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2557. mixer->hw_lm->idx - LM_0);
  2558. mixer->hw_ctl = last_valid_ctl;
  2559. } else {
  2560. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2561. last_valid_ctl = mixer->hw_ctl;
  2562. sde_crtc->num_ctls++;
  2563. }
  2564. /* Shouldn't happen, mixers are always >= ctls */
  2565. if (!mixer->hw_ctl) {
  2566. SDE_ERROR("no valid ctls found for lm %d\n",
  2567. mixer->hw_lm->idx - LM_0);
  2568. return;
  2569. }
  2570. /* Dspp may be null */
  2571. (void) sde_rm_get_hw(rm, &dspp_iter);
  2572. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2573. /* DS may be null */
  2574. (void) sde_rm_get_hw(rm, &ds_iter);
  2575. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2576. mixer->encoder = enc;
  2577. sde_crtc->num_mixers++;
  2578. SDE_DEBUG("setup mixer %d: lm %d\n",
  2579. i, mixer->hw_lm->idx - LM_0);
  2580. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2581. i, mixer->hw_ctl->idx - CTL_0);
  2582. if (mixer->hw_ds)
  2583. SDE_DEBUG("setup mixer %d: ds %d\n",
  2584. i, mixer->hw_ds->idx - DS_0);
  2585. }
  2586. }
  2587. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2588. {
  2589. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2590. struct drm_encoder *enc;
  2591. sde_crtc->num_ctls = 0;
  2592. sde_crtc->num_mixers = 0;
  2593. sde_crtc->mixers_swapped = false;
  2594. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2595. mutex_lock(&sde_crtc->crtc_lock);
  2596. /* Check for mixers on all encoders attached to this crtc */
  2597. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2598. if (enc->crtc != crtc)
  2599. continue;
  2600. /* avoid overwriting mixers info from a copy encoder */
  2601. if (sde_encoder_in_clone_mode(enc))
  2602. continue;
  2603. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2604. }
  2605. mutex_unlock(&sde_crtc->crtc_lock);
  2606. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2607. }
  2608. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2609. {
  2610. int i;
  2611. struct sde_crtc_state *cstate;
  2612. cstate = to_sde_crtc_state(state);
  2613. cstate->is_ppsplit = false;
  2614. for (i = 0; i < cstate->num_connectors; i++) {
  2615. struct drm_connector *conn = cstate->connectors[i];
  2616. if (sde_connector_get_topology_name(conn) ==
  2617. SDE_RM_TOPOLOGY_PPSPLIT)
  2618. cstate->is_ppsplit = true;
  2619. }
  2620. }
  2621. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2622. struct drm_crtc_state *state)
  2623. {
  2624. struct sde_crtc *sde_crtc;
  2625. struct sde_crtc_state *cstate;
  2626. struct drm_display_mode *adj_mode;
  2627. u32 crtc_split_width;
  2628. int i;
  2629. if (!crtc || !state) {
  2630. SDE_ERROR("invalid args\n");
  2631. return;
  2632. }
  2633. sde_crtc = to_sde_crtc(crtc);
  2634. cstate = to_sde_crtc_state(state);
  2635. adj_mode = &state->adjusted_mode;
  2636. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2637. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2638. cstate->lm_bounds[i].x = crtc_split_width * i;
  2639. cstate->lm_bounds[i].y = 0;
  2640. cstate->lm_bounds[i].w = crtc_split_width;
  2641. cstate->lm_bounds[i].h =
  2642. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2643. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2644. sizeof(cstate->lm_roi[i]));
  2645. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2646. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2647. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2648. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2649. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2650. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2651. }
  2652. drm_mode_debug_printmodeline(adj_mode);
  2653. }
  2654. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2655. {
  2656. struct sde_crtc_mixer mixer;
  2657. /*
  2658. * Use mixer[0] to get hw_ctl which will use ops to clear
  2659. * all blendstages. Clear all blendstages will iterate through
  2660. * all mixers.
  2661. */
  2662. if (sde_crtc->num_mixers) {
  2663. mixer = sde_crtc->mixers[0];
  2664. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2665. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2666. }
  2667. }
  2668. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2669. struct drm_crtc_state *old_state)
  2670. {
  2671. struct sde_crtc *sde_crtc;
  2672. struct drm_encoder *encoder;
  2673. struct drm_device *dev;
  2674. struct sde_kms *sde_kms;
  2675. struct sde_splash_display *splash_display;
  2676. bool cont_splash_enabled = false;
  2677. size_t i;
  2678. if (!crtc) {
  2679. SDE_ERROR("invalid crtc\n");
  2680. return;
  2681. }
  2682. if (!crtc->state->enable) {
  2683. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2684. crtc->base.id, crtc->state->enable);
  2685. return;
  2686. }
  2687. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2688. SDE_ERROR("power resource is not enabled\n");
  2689. return;
  2690. }
  2691. sde_kms = _sde_crtc_get_kms(crtc);
  2692. if (!sde_kms)
  2693. return;
  2694. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2695. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2696. sde_crtc = to_sde_crtc(crtc);
  2697. dev = crtc->dev;
  2698. if (!sde_crtc->num_mixers) {
  2699. _sde_crtc_setup_mixers(crtc);
  2700. _sde_crtc_setup_is_ppsplit(crtc->state);
  2701. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2702. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2703. }
  2704. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2705. if (encoder->crtc != crtc)
  2706. continue;
  2707. /* encoder will trigger pending mask now */
  2708. sde_encoder_trigger_kickoff_pending(encoder);
  2709. }
  2710. /* update performance setting */
  2711. sde_core_perf_crtc_update(crtc, 1, false);
  2712. /*
  2713. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2714. * it means we are trying to flush a CRTC whose state is disabled:
  2715. * nothing else needs to be done.
  2716. */
  2717. if (unlikely(!sde_crtc->num_mixers))
  2718. goto end;
  2719. _sde_crtc_blend_setup(crtc, old_state, true);
  2720. _sde_crtc_dest_scaler_setup(crtc);
  2721. /* cancel the idle notify delayed work */
  2722. if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2723. MSM_DISPLAY_VIDEO_MODE) &&
  2724. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
  2725. SDE_DEBUG("idle notify work cancelled\n");
  2726. /*
  2727. * Since CP properties use AXI buffer to program the
  2728. * HW, check if context bank is in attached state,
  2729. * apply color processing properties only if
  2730. * smmu state is attached,
  2731. */
  2732. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2733. splash_display = &sde_kms->splash_data.splash_display[i];
  2734. if (splash_display->cont_splash_enabled &&
  2735. splash_display->encoder &&
  2736. crtc == splash_display->encoder->crtc)
  2737. cont_splash_enabled = true;
  2738. }
  2739. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2740. (cont_splash_enabled || sde_crtc->enabled))
  2741. sde_cp_crtc_apply_properties(crtc);
  2742. /*
  2743. * PP_DONE irq is only used by command mode for now.
  2744. * It is better to request pending before FLUSH and START trigger
  2745. * to make sure no pp_done irq missed.
  2746. * This is safe because no pp_done will happen before SW trigger
  2747. * in command mode.
  2748. */
  2749. end:
  2750. SDE_ATRACE_END("crtc_atomic_begin");
  2751. }
  2752. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2753. struct drm_crtc_state *old_crtc_state)
  2754. {
  2755. struct drm_encoder *encoder;
  2756. struct sde_crtc *sde_crtc;
  2757. struct drm_device *dev;
  2758. struct drm_plane *plane;
  2759. struct msm_drm_private *priv;
  2760. struct msm_drm_thread *event_thread;
  2761. struct sde_crtc_state *cstate;
  2762. struct sde_kms *sde_kms;
  2763. int idle_time = 0;
  2764. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2765. SDE_ERROR("invalid crtc\n");
  2766. return;
  2767. }
  2768. if (!crtc->state->enable) {
  2769. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2770. crtc->base.id, crtc->state->enable);
  2771. return;
  2772. }
  2773. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2774. SDE_ERROR("power resource is not enabled\n");
  2775. return;
  2776. }
  2777. sde_kms = _sde_crtc_get_kms(crtc);
  2778. if (!sde_kms) {
  2779. SDE_ERROR("invalid kms\n");
  2780. return;
  2781. }
  2782. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2783. sde_crtc = to_sde_crtc(crtc);
  2784. cstate = to_sde_crtc_state(crtc->state);
  2785. dev = crtc->dev;
  2786. priv = dev->dev_private;
  2787. if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  2788. SDE_ERROR("invalid crtc index[%d]\n", crtc->index);
  2789. return;
  2790. }
  2791. event_thread = &priv->event_thread[crtc->index];
  2792. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2793. /*
  2794. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2795. * it means we are trying to flush a CRTC whose state is disabled:
  2796. * nothing else needs to be done.
  2797. */
  2798. if (unlikely(!sde_crtc->num_mixers))
  2799. return;
  2800. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2801. /*
  2802. * For planes without commit update, drm framework will not add
  2803. * those planes to current state since hardware update is not
  2804. * required. However, if those planes were power collapsed since
  2805. * last commit cycle, driver has to restore the hardware state
  2806. * of those planes explicitly here prior to plane flush.
  2807. * Also use this iteration to see if any plane requires cache,
  2808. * so during the perf update driver can activate/deactivate
  2809. * the cache accordingly.
  2810. */
  2811. sde_crtc->new_perf.llcc_active = false;
  2812. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2813. sde_plane_restore(plane);
  2814. if (sde_plane_is_cache_required(plane))
  2815. sde_crtc->new_perf.llcc_active = true;
  2816. }
  2817. /* wait for acquire fences before anything else is done */
  2818. _sde_crtc_wait_for_fences(crtc);
  2819. /* schedule the idle notify delayed work */
  2820. if (idle_time && sde_encoder_check_curr_mode(
  2821. sde_crtc->mixers[0].encoder,
  2822. MSM_DISPLAY_VIDEO_MODE)) {
  2823. kthread_queue_delayed_work(&event_thread->worker,
  2824. &sde_crtc->idle_notify_work,
  2825. msecs_to_jiffies(idle_time));
  2826. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2827. }
  2828. if (!cstate->rsc_update) {
  2829. drm_for_each_encoder_mask(encoder, dev,
  2830. crtc->state->encoder_mask) {
  2831. cstate->rsc_client =
  2832. sde_encoder_get_rsc_client(encoder);
  2833. }
  2834. cstate->rsc_update = true;
  2835. }
  2836. /*
  2837. * Final plane updates: Give each plane a chance to complete all
  2838. * required writes/flushing before crtc's "flush
  2839. * everything" call below.
  2840. */
  2841. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2842. if (sde_kms->smmu_state.transition_error)
  2843. sde_plane_set_error(plane, true);
  2844. sde_plane_flush(plane);
  2845. }
  2846. /* Kickoff will be scheduled by outer layer */
  2847. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2848. }
  2849. /**
  2850. * sde_crtc_destroy_state - state destroy hook
  2851. * @crtc: drm CRTC
  2852. * @state: CRTC state object to release
  2853. */
  2854. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2855. struct drm_crtc_state *state)
  2856. {
  2857. struct sde_crtc *sde_crtc;
  2858. struct sde_crtc_state *cstate;
  2859. struct drm_encoder *enc;
  2860. struct sde_kms *sde_kms;
  2861. if (!crtc || !state) {
  2862. SDE_ERROR("invalid argument(s)\n");
  2863. return;
  2864. }
  2865. sde_crtc = to_sde_crtc(crtc);
  2866. cstate = to_sde_crtc_state(state);
  2867. sde_kms = _sde_crtc_get_kms(crtc);
  2868. if (!sde_kms) {
  2869. SDE_ERROR("invalid sde_kms\n");
  2870. return;
  2871. }
  2872. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2873. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2874. sde_rm_release(&sde_kms->rm, enc, true);
  2875. __drm_atomic_helper_crtc_destroy_state(state);
  2876. /* destroy value helper */
  2877. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2878. &cstate->property_state);
  2879. }
  2880. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2881. {
  2882. struct sde_crtc *sde_crtc;
  2883. int i;
  2884. if (!crtc) {
  2885. SDE_ERROR("invalid argument\n");
  2886. return -EINVAL;
  2887. }
  2888. sde_crtc = to_sde_crtc(crtc);
  2889. if (!atomic_read(&sde_crtc->frame_pending)) {
  2890. SDE_DEBUG("no frames pending\n");
  2891. return 0;
  2892. }
  2893. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2894. /*
  2895. * flush all the event thread work to make sure all the
  2896. * FRAME_EVENTS from encoder are propagated to crtc
  2897. */
  2898. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2899. if (list_empty(&sde_crtc->frame_events[i].list))
  2900. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2901. }
  2902. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2903. return 0;
  2904. }
  2905. /**
  2906. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2907. * @crtc: Pointer to crtc structure
  2908. */
  2909. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2910. {
  2911. struct drm_plane *plane;
  2912. struct drm_plane_state *state;
  2913. struct sde_crtc *sde_crtc;
  2914. struct sde_crtc_mixer *mixer;
  2915. struct sde_hw_ctl *ctl;
  2916. if (!crtc)
  2917. return;
  2918. sde_crtc = to_sde_crtc(crtc);
  2919. mixer = sde_crtc->mixers;
  2920. if (!mixer)
  2921. return;
  2922. ctl = mixer->hw_ctl;
  2923. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2924. state = plane->state;
  2925. if (!state)
  2926. continue;
  2927. /* clear plane flush bitmask */
  2928. sde_plane_ctl_flush(plane, ctl, false);
  2929. }
  2930. }
  2931. /**
  2932. * sde_crtc_reset_hw - attempt hardware reset on errors
  2933. * @crtc: Pointer to DRM crtc instance
  2934. * @old_state: Pointer to crtc state for previous commit
  2935. * @recovery_events: Whether or not recovery events are enabled
  2936. * Returns: Zero if current commit should still be attempted
  2937. */
  2938. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  2939. bool recovery_events)
  2940. {
  2941. struct drm_plane *plane_halt[MAX_PLANES];
  2942. struct drm_plane *plane;
  2943. struct drm_encoder *encoder;
  2944. struct sde_crtc *sde_crtc;
  2945. struct sde_crtc_state *cstate;
  2946. struct sde_hw_ctl *ctl;
  2947. signed int i, plane_count;
  2948. int rc;
  2949. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  2950. return -EINVAL;
  2951. sde_crtc = to_sde_crtc(crtc);
  2952. cstate = to_sde_crtc_state(crtc->state);
  2953. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  2954. /* optionally generate a panic instead of performing a h/w reset */
  2955. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  2956. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2957. ctl = sde_crtc->mixers[i].hw_ctl;
  2958. if (!ctl || !ctl->ops.reset)
  2959. continue;
  2960. rc = ctl->ops.reset(ctl);
  2961. if (rc) {
  2962. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  2963. crtc->base.id, ctl->idx - CTL_0);
  2964. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  2965. SDE_EVTLOG_ERROR);
  2966. break;
  2967. }
  2968. }
  2969. /* Early out if simple ctl reset succeeded */
  2970. if (i == sde_crtc->num_ctls)
  2971. return 0;
  2972. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  2973. /* force all components in the system into reset at the same time */
  2974. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2975. ctl = sde_crtc->mixers[i].hw_ctl;
  2976. if (!ctl || !ctl->ops.hard_reset)
  2977. continue;
  2978. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  2979. ctl->ops.hard_reset(ctl, true);
  2980. }
  2981. plane_count = 0;
  2982. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  2983. if (plane_count >= ARRAY_SIZE(plane_halt))
  2984. break;
  2985. plane_halt[plane_count++] = plane;
  2986. sde_plane_halt_requests(plane, true);
  2987. sde_plane_set_revalidate(plane, true);
  2988. }
  2989. /* provide safe "border color only" commit configuration for later */
  2990. _sde_crtc_remove_pipe_flush(crtc);
  2991. _sde_crtc_blend_setup(crtc, old_state, false);
  2992. /* take h/w components out of reset */
  2993. for (i = plane_count - 1; i >= 0; --i)
  2994. sde_plane_halt_requests(plane_halt[i], false);
  2995. /* attempt to poll for start of frame cycle before reset release */
  2996. list_for_each_entry(encoder,
  2997. &crtc->dev->mode_config.encoder_list, head) {
  2998. if (encoder->crtc != crtc)
  2999. continue;
  3000. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3001. sde_encoder_poll_line_counts(encoder);
  3002. }
  3003. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3004. ctl = sde_crtc->mixers[i].hw_ctl;
  3005. if (!ctl || !ctl->ops.hard_reset)
  3006. continue;
  3007. ctl->ops.hard_reset(ctl, false);
  3008. }
  3009. list_for_each_entry(encoder,
  3010. &crtc->dev->mode_config.encoder_list, head) {
  3011. if (encoder->crtc != crtc)
  3012. continue;
  3013. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3014. sde_encoder_kickoff(encoder, false);
  3015. }
  3016. /* panic the device if VBIF is not in good state */
  3017. return !recovery_events ? 0 : -EAGAIN;
  3018. }
  3019. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3020. struct drm_crtc_state *old_state)
  3021. {
  3022. struct drm_encoder *encoder;
  3023. struct drm_device *dev;
  3024. struct sde_crtc *sde_crtc;
  3025. struct msm_drm_private *priv;
  3026. struct sde_kms *sde_kms;
  3027. struct sde_crtc_state *cstate;
  3028. bool is_error = false;
  3029. unsigned long flags;
  3030. enum sde_crtc_idle_pc_state idle_pc_state;
  3031. struct sde_encoder_kickoff_params params = { 0 };
  3032. if (!crtc) {
  3033. SDE_ERROR("invalid argument\n");
  3034. return;
  3035. }
  3036. dev = crtc->dev;
  3037. sde_crtc = to_sde_crtc(crtc);
  3038. sde_kms = _sde_crtc_get_kms(crtc);
  3039. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3040. SDE_ERROR("invalid argument\n");
  3041. return;
  3042. }
  3043. priv = sde_kms->dev->dev_private;
  3044. cstate = to_sde_crtc_state(crtc->state);
  3045. /*
  3046. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3047. * it means we are trying to start a CRTC whose state is disabled:
  3048. * nothing else needs to be done.
  3049. */
  3050. if (unlikely(!sde_crtc->num_mixers))
  3051. return;
  3052. SDE_ATRACE_BEGIN("crtc_commit");
  3053. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3054. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3055. if (encoder->crtc != crtc)
  3056. continue;
  3057. /*
  3058. * Encoder will flush/start now, unless it has a tx pending.
  3059. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3060. */
  3061. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3062. crtc->state);
  3063. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3064. sde_crtc->needs_hw_reset = true;
  3065. if (idle_pc_state != IDLE_PC_NONE)
  3066. sde_encoder_control_idle_pc(encoder,
  3067. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3068. }
  3069. /*
  3070. * Optionally attempt h/w recovery if any errors were detected while
  3071. * preparing for the kickoff
  3072. */
  3073. if (sde_crtc->needs_hw_reset) {
  3074. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3075. if (sde_crtc->frame_trigger_mode
  3076. != FRAME_DONE_WAIT_POSTED_START &&
  3077. sde_crtc_reset_hw(crtc, old_state,
  3078. params.recovery_events_enabled))
  3079. is_error = true;
  3080. sde_crtc->needs_hw_reset = false;
  3081. }
  3082. sde_crtc_calc_fps(sde_crtc);
  3083. SDE_ATRACE_BEGIN("flush_event_thread");
  3084. _sde_crtc_flush_event_thread(crtc);
  3085. SDE_ATRACE_END("flush_event_thread");
  3086. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3087. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3088. /* acquire bandwidth and other resources */
  3089. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3090. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3091. } else {
  3092. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3093. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3094. }
  3095. sde_crtc->play_count++;
  3096. sde_vbif_clear_errors(sde_kms);
  3097. if (is_error) {
  3098. _sde_crtc_remove_pipe_flush(crtc);
  3099. _sde_crtc_blend_setup(crtc, old_state, false);
  3100. }
  3101. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3102. if (encoder->crtc != crtc)
  3103. continue;
  3104. sde_encoder_kickoff(encoder, false);
  3105. }
  3106. /* store the event after frame trigger */
  3107. if (sde_crtc->event) {
  3108. WARN_ON(sde_crtc->event);
  3109. } else {
  3110. spin_lock_irqsave(&dev->event_lock, flags);
  3111. sde_crtc->event = crtc->state->event;
  3112. spin_unlock_irqrestore(&dev->event_lock, flags);
  3113. }
  3114. SDE_ATRACE_END("crtc_commit");
  3115. }
  3116. /**
  3117. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3118. * @sde_crtc: Pointer to sde crtc structure
  3119. * @enable: Whether to enable/disable vblanks
  3120. *
  3121. * @Return: error code
  3122. */
  3123. static int _sde_crtc_vblank_enable_no_lock(
  3124. struct sde_crtc *sde_crtc, bool enable)
  3125. {
  3126. struct drm_crtc *crtc;
  3127. struct drm_encoder *enc;
  3128. if (!sde_crtc) {
  3129. SDE_ERROR("invalid crtc\n");
  3130. return -EINVAL;
  3131. }
  3132. crtc = &sde_crtc->base;
  3133. if (enable) {
  3134. int ret;
  3135. /* drop lock since power crtc cb may try to re-acquire lock */
  3136. mutex_unlock(&sde_crtc->crtc_lock);
  3137. ret = pm_runtime_get_sync(crtc->dev->dev);
  3138. mutex_lock(&sde_crtc->crtc_lock);
  3139. if (ret < 0)
  3140. return ret;
  3141. drm_for_each_encoder_mask(enc, crtc->dev,
  3142. crtc->state->encoder_mask) {
  3143. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3144. sde_crtc->enabled);
  3145. sde_encoder_register_vblank_callback(enc,
  3146. sde_crtc_vblank_cb, (void *)crtc);
  3147. }
  3148. } else {
  3149. drm_for_each_encoder_mask(enc, crtc->dev,
  3150. crtc->state->encoder_mask) {
  3151. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3152. sde_crtc->enabled);
  3153. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3154. }
  3155. /* drop lock since power crtc cb may try to re-acquire lock */
  3156. mutex_unlock(&sde_crtc->crtc_lock);
  3157. pm_runtime_put_sync(crtc->dev->dev);
  3158. mutex_lock(&sde_crtc->crtc_lock);
  3159. }
  3160. return 0;
  3161. }
  3162. /**
  3163. * sde_crtc_duplicate_state - state duplicate hook
  3164. * @crtc: Pointer to drm crtc structure
  3165. * @Returns: Pointer to new drm_crtc_state structure
  3166. */
  3167. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3168. {
  3169. struct sde_crtc *sde_crtc;
  3170. struct sde_crtc_state *cstate, *old_cstate;
  3171. if (!crtc || !crtc->state) {
  3172. SDE_ERROR("invalid argument(s)\n");
  3173. return NULL;
  3174. }
  3175. sde_crtc = to_sde_crtc(crtc);
  3176. old_cstate = to_sde_crtc_state(crtc->state);
  3177. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3178. if (!cstate) {
  3179. SDE_ERROR("failed to allocate state\n");
  3180. return NULL;
  3181. }
  3182. /* duplicate value helper */
  3183. msm_property_duplicate_state(&sde_crtc->property_info,
  3184. old_cstate, cstate,
  3185. &cstate->property_state, cstate->property_values);
  3186. /* clear destination scaler dirty bit */
  3187. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3188. /* duplicate base helper */
  3189. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3190. return &cstate->base;
  3191. }
  3192. /**
  3193. * sde_crtc_reset - reset hook for CRTCs
  3194. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3195. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3196. * @crtc: Pointer to drm crtc structure
  3197. */
  3198. static void sde_crtc_reset(struct drm_crtc *crtc)
  3199. {
  3200. struct sde_crtc *sde_crtc;
  3201. struct sde_crtc_state *cstate;
  3202. if (!crtc) {
  3203. SDE_ERROR("invalid crtc\n");
  3204. return;
  3205. }
  3206. /* revert suspend actions, if necessary */
  3207. if (!sde_crtc_is_reset_required(crtc)) {
  3208. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3209. return;
  3210. }
  3211. /* remove previous state, if present */
  3212. if (crtc->state) {
  3213. sde_crtc_destroy_state(crtc, crtc->state);
  3214. crtc->state = 0;
  3215. }
  3216. sde_crtc = to_sde_crtc(crtc);
  3217. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3218. if (!cstate) {
  3219. SDE_ERROR("failed to allocate state\n");
  3220. return;
  3221. }
  3222. /* reset value helper */
  3223. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3224. &cstate->property_state,
  3225. cstate->property_values);
  3226. _sde_crtc_set_input_fence_timeout(cstate);
  3227. cstate->base.crtc = crtc;
  3228. crtc->state = &cstate->base;
  3229. }
  3230. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3231. {
  3232. struct drm_crtc *crtc = arg;
  3233. struct sde_crtc *sde_crtc;
  3234. struct sde_crtc_state *cstate;
  3235. struct drm_plane *plane;
  3236. struct drm_encoder *encoder;
  3237. u32 power_on;
  3238. unsigned long flags;
  3239. struct sde_crtc_irq_info *node = NULL;
  3240. int ret = 0;
  3241. struct drm_event event;
  3242. if (!crtc) {
  3243. SDE_ERROR("invalid crtc\n");
  3244. return;
  3245. }
  3246. sde_crtc = to_sde_crtc(crtc);
  3247. cstate = to_sde_crtc_state(crtc->state);
  3248. mutex_lock(&sde_crtc->crtc_lock);
  3249. SDE_EVT32(DRMID(crtc), event_type);
  3250. switch (event_type) {
  3251. case SDE_POWER_EVENT_POST_ENABLE:
  3252. /* restore encoder; crtc will be programmed during commit */
  3253. drm_for_each_encoder_mask(encoder, crtc->dev,
  3254. crtc->state->encoder_mask) {
  3255. sde_encoder_virt_restore(encoder);
  3256. }
  3257. /* restore UIDLE */
  3258. sde_core_perf_crtc_update_uidle(crtc, true);
  3259. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3260. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3261. ret = 0;
  3262. if (node->func)
  3263. ret = node->func(crtc, true, &node->irq);
  3264. if (ret)
  3265. SDE_ERROR("%s failed to enable event %x\n",
  3266. sde_crtc->name, node->event);
  3267. }
  3268. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3269. sde_cp_crtc_post_ipc(crtc);
  3270. break;
  3271. case SDE_POWER_EVENT_PRE_DISABLE:
  3272. drm_for_each_encoder_mask(encoder, crtc->dev,
  3273. crtc->state->encoder_mask) {
  3274. /*
  3275. * disable the vsync source after updating the
  3276. * rsc state. rsc state update might have vsync wait
  3277. * and vsync source must be disabled after it.
  3278. * It will avoid generating any vsync from this point
  3279. * till mode-2 entry. It is SW workaround for HW
  3280. * limitation and should not be removed without
  3281. * checking the updated design.
  3282. */
  3283. sde_encoder_control_te(encoder, false);
  3284. }
  3285. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3286. node = NULL;
  3287. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3288. ret = 0;
  3289. if (node->func)
  3290. ret = node->func(crtc, false, &node->irq);
  3291. if (ret)
  3292. SDE_ERROR("%s failed to disable event %x\n",
  3293. sde_crtc->name, node->event);
  3294. }
  3295. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3296. sde_cp_crtc_pre_ipc(crtc);
  3297. break;
  3298. case SDE_POWER_EVENT_POST_DISABLE:
  3299. /*
  3300. * set revalidate flag in planes, so it will be re-programmed
  3301. * in the next frame update
  3302. */
  3303. drm_atomic_crtc_for_each_plane(plane, crtc)
  3304. sde_plane_set_revalidate(plane, true);
  3305. sde_cp_crtc_suspend(crtc);
  3306. /* reconfigure everything on next frame update */
  3307. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3308. event.type = DRM_EVENT_SDE_POWER;
  3309. event.length = sizeof(power_on);
  3310. power_on = 0;
  3311. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3312. (u8 *)&power_on);
  3313. break;
  3314. default:
  3315. SDE_DEBUG("event:%d not handled\n", event_type);
  3316. break;
  3317. }
  3318. mutex_unlock(&sde_crtc->crtc_lock);
  3319. }
  3320. static void sde_crtc_disable(struct drm_crtc *crtc)
  3321. {
  3322. struct sde_kms *sde_kms;
  3323. struct sde_crtc *sde_crtc;
  3324. struct sde_crtc_state *cstate;
  3325. struct drm_encoder *encoder;
  3326. struct msm_drm_private *priv;
  3327. unsigned long flags;
  3328. struct sde_crtc_irq_info *node = NULL;
  3329. struct drm_event event;
  3330. u32 power_on;
  3331. bool in_cont_splash = false;
  3332. int ret, i;
  3333. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3334. SDE_ERROR("invalid crtc\n");
  3335. return;
  3336. }
  3337. sde_kms = _sde_crtc_get_kms(crtc);
  3338. if (!sde_kms) {
  3339. SDE_ERROR("invalid kms\n");
  3340. return;
  3341. }
  3342. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3343. SDE_ERROR("power resource is not enabled\n");
  3344. return;
  3345. }
  3346. sde_crtc = to_sde_crtc(crtc);
  3347. cstate = to_sde_crtc_state(crtc->state);
  3348. priv = crtc->dev->dev_private;
  3349. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3350. drm_crtc_vblank_off(crtc);
  3351. mutex_lock(&sde_crtc->crtc_lock);
  3352. SDE_EVT32_VERBOSE(DRMID(crtc));
  3353. /* update color processing on suspend */
  3354. event.type = DRM_EVENT_CRTC_POWER;
  3355. event.length = sizeof(u32);
  3356. sde_cp_crtc_suspend(crtc);
  3357. power_on = 0;
  3358. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3359. (u8 *)&power_on);
  3360. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3361. _sde_crtc_flush_event_thread(crtc);
  3362. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3363. crtc->state->active, crtc->state->enable);
  3364. sde_crtc->enabled = false;
  3365. /* Try to disable uidle */
  3366. sde_core_perf_crtc_update_uidle(crtc, false);
  3367. if (atomic_read(&sde_crtc->frame_pending)) {
  3368. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3369. atomic_read(&sde_crtc->frame_pending));
  3370. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3371. SDE_EVTLOG_FUNC_CASE2);
  3372. sde_core_perf_crtc_release_bw(crtc);
  3373. atomic_set(&sde_crtc->frame_pending, 0);
  3374. }
  3375. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3376. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3377. ret = 0;
  3378. if (node->func)
  3379. ret = node->func(crtc, false, &node->irq);
  3380. if (ret)
  3381. SDE_ERROR("%s failed to disable event %x\n",
  3382. sde_crtc->name, node->event);
  3383. }
  3384. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3385. drm_for_each_encoder_mask(encoder, crtc->dev,
  3386. crtc->state->encoder_mask) {
  3387. if (sde_encoder_in_cont_splash(encoder)) {
  3388. in_cont_splash = true;
  3389. break;
  3390. }
  3391. }
  3392. /* avoid clk/bw downvote if cont-splash is enabled */
  3393. if (!in_cont_splash)
  3394. sde_core_perf_crtc_update(crtc, 0, true);
  3395. drm_for_each_encoder_mask(encoder, crtc->dev,
  3396. crtc->state->encoder_mask) {
  3397. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3398. cstate->rsc_client = NULL;
  3399. cstate->rsc_update = false;
  3400. /*
  3401. * reset idle power-collapse to original state during suspend;
  3402. * user-mode will change the state on resume, if required
  3403. */
  3404. if (sde_kms->catalog->has_idle_pc)
  3405. sde_encoder_control_idle_pc(encoder, true);
  3406. }
  3407. if (sde_crtc->power_event)
  3408. sde_power_handle_unregister_event(&priv->phandle,
  3409. sde_crtc->power_event);
  3410. /**
  3411. * All callbacks are unregistered and frame done waits are complete
  3412. * at this point. No buffers are accessed by hardware.
  3413. * reset the fence timeline if crtc will not be enabled for this commit
  3414. */
  3415. if (!crtc->state->active || !crtc->state->enable) {
  3416. sde_fence_signal(sde_crtc->output_fence,
  3417. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3418. for (i = 0; i < cstate->num_connectors; ++i)
  3419. sde_connector_commit_reset(cstate->connectors[i],
  3420. ktime_get());
  3421. }
  3422. _sde_crtc_clear_all_blend_stages(sde_crtc);
  3423. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3424. sde_crtc->num_mixers = 0;
  3425. sde_crtc->mixers_swapped = false;
  3426. /* disable clk & bw control until clk & bw properties are set */
  3427. cstate->bw_control = false;
  3428. cstate->bw_split_vote = false;
  3429. mutex_unlock(&sde_crtc->crtc_lock);
  3430. }
  3431. static void sde_crtc_enable(struct drm_crtc *crtc,
  3432. struct drm_crtc_state *old_crtc_state)
  3433. {
  3434. struct sde_crtc *sde_crtc;
  3435. struct drm_encoder *encoder;
  3436. struct msm_drm_private *priv;
  3437. unsigned long flags;
  3438. struct sde_crtc_irq_info *node = NULL;
  3439. struct drm_event event;
  3440. u32 power_on;
  3441. int ret, i;
  3442. struct sde_crtc_state *cstate;
  3443. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3444. SDE_ERROR("invalid crtc\n");
  3445. return;
  3446. }
  3447. priv = crtc->dev->dev_private;
  3448. cstate = to_sde_crtc_state(crtc->state);
  3449. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3450. SDE_ERROR("power resource is not enabled\n");
  3451. return;
  3452. }
  3453. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3454. SDE_EVT32_VERBOSE(DRMID(crtc));
  3455. sde_crtc = to_sde_crtc(crtc);
  3456. /*
  3457. * Avoid drm_crtc_vblank_on during seamless DMS case
  3458. * when CRTC is already in enabled state
  3459. */
  3460. if (!sde_crtc->enabled)
  3461. drm_crtc_vblank_on(crtc);
  3462. mutex_lock(&sde_crtc->crtc_lock);
  3463. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3464. /*
  3465. * Try to enable uidle (if possible), we do this before the call
  3466. * to return early during seamless dms mode, so any fps
  3467. * change is also consider to enable/disable UIDLE
  3468. */
  3469. sde_core_perf_crtc_update_uidle(crtc, true);
  3470. /* return early if crtc is already enabled, do this after UIDLE check */
  3471. if (sde_crtc->enabled) {
  3472. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3473. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3474. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3475. sde_crtc->name);
  3476. else
  3477. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3478. mutex_unlock(&sde_crtc->crtc_lock);
  3479. return;
  3480. }
  3481. drm_for_each_encoder_mask(encoder, crtc->dev,
  3482. crtc->state->encoder_mask) {
  3483. sde_encoder_register_frame_event_callback(encoder,
  3484. sde_crtc_frame_event_cb, crtc);
  3485. }
  3486. sde_crtc->enabled = true;
  3487. /* update color processing on resume */
  3488. event.type = DRM_EVENT_CRTC_POWER;
  3489. event.length = sizeof(u32);
  3490. sde_cp_crtc_resume(crtc);
  3491. power_on = 1;
  3492. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3493. (u8 *)&power_on);
  3494. mutex_unlock(&sde_crtc->crtc_lock);
  3495. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3496. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3497. ret = 0;
  3498. if (node->func)
  3499. ret = node->func(crtc, true, &node->irq);
  3500. if (ret)
  3501. SDE_ERROR("%s failed to enable event %x\n",
  3502. sde_crtc->name, node->event);
  3503. }
  3504. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3505. sde_crtc->power_event = sde_power_handle_register_event(
  3506. &priv->phandle,
  3507. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3508. SDE_POWER_EVENT_PRE_DISABLE,
  3509. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3510. /* Enable ESD thread */
  3511. for (i = 0; i < cstate->num_connectors; i++)
  3512. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3513. }
  3514. /* no input validation - caller API has all the checks */
  3515. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3516. struct plane_state pstates[], int cnt)
  3517. {
  3518. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3519. struct drm_display_mode *mode = &state->adjusted_mode;
  3520. const struct drm_plane_state *pstate;
  3521. struct sde_plane_state *sde_pstate;
  3522. int rc = 0, i;
  3523. /* Check dim layer rect bounds and stage */
  3524. for (i = 0; i < cstate->num_dim_layers; i++) {
  3525. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3526. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3527. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3528. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3529. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3530. (!cstate->dim_layer[i].rect.w) ||
  3531. (!cstate->dim_layer[i].rect.h)) {
  3532. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3533. cstate->dim_layer[i].rect.x,
  3534. cstate->dim_layer[i].rect.y,
  3535. cstate->dim_layer[i].rect.w,
  3536. cstate->dim_layer[i].rect.h,
  3537. cstate->dim_layer[i].stage);
  3538. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3539. mode->vdisplay);
  3540. rc = -E2BIG;
  3541. goto end;
  3542. }
  3543. }
  3544. /* log all src and excl_rect, useful for debugging */
  3545. for (i = 0; i < cnt; i++) {
  3546. pstate = pstates[i].drm_pstate;
  3547. sde_pstate = to_sde_plane_state(pstate);
  3548. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3549. pstate->plane->base.id, pstates[i].stage,
  3550. pstate->crtc_x, pstate->crtc_y,
  3551. pstate->crtc_w, pstate->crtc_h,
  3552. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3553. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3554. }
  3555. end:
  3556. return rc;
  3557. }
  3558. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3559. struct drm_crtc_state *state, struct plane_state pstates[],
  3560. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3561. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3562. {
  3563. struct drm_plane *plane;
  3564. int i;
  3565. if (secure == SDE_DRM_SEC_ONLY) {
  3566. /*
  3567. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3568. * - fb_sec_dir is for secure camera preview and
  3569. * secure display use case
  3570. * - fb_sec is for secure video playback
  3571. * - fb_ns is for normal non secure use cases
  3572. */
  3573. if (fb_ns || fb_sec) {
  3574. SDE_ERROR(
  3575. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3576. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3577. return -EINVAL;
  3578. }
  3579. /*
  3580. * - only one blending stage is allowed in sec_crtc
  3581. * - validate if pipe is allowed for sec-ui updates
  3582. */
  3583. for (i = 1; i < cnt; i++) {
  3584. if (!pstates[i].drm_pstate
  3585. || !pstates[i].drm_pstate->plane) {
  3586. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3587. DRMID(crtc), i);
  3588. return -EINVAL;
  3589. }
  3590. plane = pstates[i].drm_pstate->plane;
  3591. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3592. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3593. DRMID(crtc), plane->base.id);
  3594. return -EINVAL;
  3595. } else if (pstates[i].stage != pstates[i-1].stage) {
  3596. SDE_ERROR(
  3597. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3598. DRMID(crtc), i, pstates[i].stage,
  3599. i-1, pstates[i-1].stage);
  3600. return -EINVAL;
  3601. }
  3602. }
  3603. /* check if all the dim_layers are in the same stage */
  3604. for (i = 1; i < cstate->num_dim_layers; i++) {
  3605. if (cstate->dim_layer[i].stage !=
  3606. cstate->dim_layer[i-1].stage) {
  3607. SDE_ERROR(
  3608. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3609. DRMID(crtc),
  3610. i, cstate->dim_layer[i].stage,
  3611. i-1, cstate->dim_layer[i-1].stage);
  3612. return -EINVAL;
  3613. }
  3614. }
  3615. /*
  3616. * if secure-ui supported blendstage is specified,
  3617. * - fail empty commit
  3618. * - validate dim_layer or plane is staged in the supported
  3619. * blendstage
  3620. */
  3621. if (sde_kms->catalog->sui_supported_blendstage) {
  3622. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3623. cstate->dim_layer[0].stage;
  3624. if (!sde_kms->catalog->has_base_layer)
  3625. sec_stage -= SDE_STAGE_0;
  3626. if ((!cnt && !cstate->num_dim_layers) ||
  3627. (sde_kms->catalog->sui_supported_blendstage
  3628. != sec_stage)) {
  3629. SDE_ERROR(
  3630. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3631. DRMID(crtc), cnt,
  3632. cstate->num_dim_layers, sec_stage);
  3633. return -EINVAL;
  3634. }
  3635. }
  3636. }
  3637. return 0;
  3638. }
  3639. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3640. struct drm_crtc_state *state, int fb_sec_dir)
  3641. {
  3642. struct drm_encoder *encoder;
  3643. int encoder_cnt = 0;
  3644. if (fb_sec_dir) {
  3645. drm_for_each_encoder_mask(encoder, crtc->dev,
  3646. state->encoder_mask)
  3647. encoder_cnt++;
  3648. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3649. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3650. DRMID(crtc), encoder_cnt);
  3651. return -EINVAL;
  3652. }
  3653. }
  3654. return 0;
  3655. }
  3656. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3657. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3658. int fb_ns, int fb_sec, int fb_sec_dir)
  3659. {
  3660. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3661. struct drm_encoder *encoder;
  3662. int is_video_mode = false;
  3663. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3664. if (sde_encoder_is_dsi_display(encoder))
  3665. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3666. MSM_DISPLAY_VIDEO_MODE);
  3667. }
  3668. /*
  3669. * In video mode check for null commit before transition
  3670. * from secure to non secure and vice versa
  3671. */
  3672. if (is_video_mode && smmu_state &&
  3673. state->plane_mask && crtc->state->plane_mask &&
  3674. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3675. (secure == SDE_DRM_SEC_ONLY))) ||
  3676. (fb_ns && ((smmu_state->state == DETACHED) ||
  3677. (smmu_state->state == DETACH_ALL_REQ))) ||
  3678. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3679. (smmu_state->state == DETACH_SEC_REQ)) &&
  3680. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3681. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3682. smmu_state->state, smmu_state->secure_level,
  3683. secure, crtc->state->plane_mask, state->plane_mask);
  3684. SDE_ERROR(
  3685. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3686. DRMID(crtc), secure, smmu_state->state,
  3687. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3688. return -EINVAL;
  3689. }
  3690. return 0;
  3691. }
  3692. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  3693. struct drm_crtc_state *state, uint32_t fb_sec)
  3694. {
  3695. bool conn_secure = false, is_wb = false;
  3696. struct drm_connector *conn;
  3697. struct drm_connector_state *conn_state;
  3698. int i;
  3699. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  3700. if (conn_state && conn_state->crtc == crtc) {
  3701. if (conn->connector_type ==
  3702. DRM_MODE_CONNECTOR_VIRTUAL)
  3703. is_wb = true;
  3704. if (sde_connector_get_property(conn_state,
  3705. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  3706. SDE_DRM_FB_SEC)
  3707. conn_secure = true;
  3708. }
  3709. }
  3710. /*
  3711. * If any input buffers are secure for wb,
  3712. * the output buffer must also be secure.
  3713. */
  3714. if (is_wb && fb_sec && !conn_secure) {
  3715. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  3716. DRMID(crtc), fb_sec, conn_secure);
  3717. return -EINVAL;
  3718. }
  3719. return 0;
  3720. }
  3721. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3722. struct drm_crtc_state *state, struct plane_state pstates[],
  3723. int cnt)
  3724. {
  3725. struct sde_crtc_state *cstate;
  3726. struct sde_kms *sde_kms;
  3727. uint32_t secure;
  3728. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3729. int rc;
  3730. if (!crtc || !state) {
  3731. SDE_ERROR("invalid arguments\n");
  3732. return -EINVAL;
  3733. }
  3734. sde_kms = _sde_crtc_get_kms(crtc);
  3735. if (!sde_kms || !sde_kms->catalog) {
  3736. SDE_ERROR("invalid kms\n");
  3737. return -EINVAL;
  3738. }
  3739. cstate = to_sde_crtc_state(state);
  3740. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3741. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3742. &fb_sec, &fb_sec_dir);
  3743. if (rc)
  3744. return rc;
  3745. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3746. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3747. if (rc)
  3748. return rc;
  3749. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  3750. if (rc)
  3751. return rc;
  3752. /*
  3753. * secure_crtc is not allowed in a shared toppolgy
  3754. * across different encoders.
  3755. */
  3756. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3757. if (rc)
  3758. return rc;
  3759. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3760. secure, fb_ns, fb_sec, fb_sec_dir);
  3761. if (rc)
  3762. return rc;
  3763. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3764. return 0;
  3765. }
  3766. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3767. struct drm_crtc_state *state,
  3768. struct drm_display_mode *mode,
  3769. struct plane_state *pstates,
  3770. struct drm_plane *plane,
  3771. struct sde_multirect_plane_states *multirect_plane,
  3772. int *cnt)
  3773. {
  3774. struct sde_crtc *sde_crtc;
  3775. struct sde_crtc_state *cstate;
  3776. const struct drm_plane_state *pstate;
  3777. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3778. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3779. int inc_sde_stage = 0;
  3780. struct sde_kms *kms;
  3781. sde_crtc = to_sde_crtc(crtc);
  3782. cstate = to_sde_crtc_state(state);
  3783. kms = _sde_crtc_get_kms(crtc);
  3784. if (!kms || !kms->catalog) {
  3785. SDE_ERROR("invalid kms\n");
  3786. return -EINVAL;
  3787. }
  3788. memset(pipe_staged, 0, sizeof(pipe_staged));
  3789. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3790. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3791. if (cstate->num_ds_enabled)
  3792. mixer_width = mixer_width * cstate->num_ds_enabled;
  3793. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3794. if (IS_ERR_OR_NULL(pstate)) {
  3795. rc = PTR_ERR(pstate);
  3796. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3797. sde_crtc->name, plane->base.id, rc);
  3798. return rc;
  3799. }
  3800. if (*cnt >= SDE_PSTATES_MAX)
  3801. continue;
  3802. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3803. pstates[*cnt].drm_pstate = pstate;
  3804. pstates[*cnt].stage = sde_plane_get_property(
  3805. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3806. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3807. if (!kms->catalog->has_base_layer)
  3808. inc_sde_stage = SDE_STAGE_0;
  3809. /* check dim layer stage with every plane */
  3810. for (i = 0; i < cstate->num_dim_layers; i++) {
  3811. if (cstate->dim_layer[i].stage ==
  3812. (pstates[*cnt].stage + inc_sde_stage)) {
  3813. SDE_ERROR(
  3814. "plane:%d/dim_layer:%i-same stage:%d\n",
  3815. plane->base.id, i,
  3816. cstate->dim_layer[i].stage);
  3817. return -EINVAL;
  3818. }
  3819. }
  3820. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3821. multirect_plane[multirect_count].r0 =
  3822. pipe_staged[pstates[*cnt].pipe_id];
  3823. multirect_plane[multirect_count].r1 = pstate;
  3824. multirect_count++;
  3825. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3826. } else {
  3827. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3828. }
  3829. (*cnt)++;
  3830. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3831. mode->vdisplay) ||
  3832. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3833. mode->hdisplay)) {
  3834. SDE_ERROR("invalid vertical/horizontal destination\n");
  3835. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3836. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3837. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3838. return -E2BIG;
  3839. }
  3840. if (cstate->num_ds_enabled &&
  3841. ((pstate->crtc_h > mixer_height) ||
  3842. (pstate->crtc_w > mixer_width))) {
  3843. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3844. pstate->crtc_w, pstate->crtc_h,
  3845. mixer_width, mixer_height);
  3846. return -E2BIG;
  3847. }
  3848. }
  3849. for (i = 1; i < SSPP_MAX; i++) {
  3850. if (pipe_staged[i]) {
  3851. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3852. SDE_ERROR(
  3853. "r1 only virt plane:%d not supported\n",
  3854. pipe_staged[i]->plane->base.id);
  3855. return -EINVAL;
  3856. }
  3857. sde_plane_clear_multirect(pipe_staged[i]);
  3858. }
  3859. }
  3860. for (i = 0; i < multirect_count; i++) {
  3861. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3862. SDE_ERROR(
  3863. "multirect validation failed for planes (%d - %d)\n",
  3864. multirect_plane[i].r0->plane->base.id,
  3865. multirect_plane[i].r1->plane->base.id);
  3866. return -EINVAL;
  3867. }
  3868. }
  3869. return rc;
  3870. }
  3871. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3872. struct sde_crtc *sde_crtc,
  3873. struct plane_state *pstates,
  3874. struct sde_crtc_state *cstate,
  3875. struct drm_display_mode *mode,
  3876. int cnt)
  3877. {
  3878. int rc = 0, i, z_pos;
  3879. u32 zpos_cnt = 0;
  3880. struct drm_crtc *crtc;
  3881. struct sde_kms *kms;
  3882. crtc = &sde_crtc->base;
  3883. kms = _sde_crtc_get_kms(crtc);
  3884. if (!kms || !kms->catalog) {
  3885. SDE_ERROR("Invalid kms\n");
  3886. return -EINVAL;
  3887. }
  3888. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  3889. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  3890. if (rc)
  3891. return rc;
  3892. if (!sde_is_custom_client()) {
  3893. int stage_old = pstates[0].stage;
  3894. z_pos = 0;
  3895. for (i = 0; i < cnt; i++) {
  3896. if (stage_old != pstates[i].stage)
  3897. ++z_pos;
  3898. stage_old = pstates[i].stage;
  3899. pstates[i].stage = z_pos;
  3900. }
  3901. }
  3902. z_pos = -1;
  3903. for (i = 0; i < cnt; i++) {
  3904. /* reset counts at every new blend stage */
  3905. if (pstates[i].stage != z_pos) {
  3906. zpos_cnt = 0;
  3907. z_pos = pstates[i].stage;
  3908. }
  3909. /* verify z_pos setting before using it */
  3910. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  3911. SDE_ERROR("> %d plane stages assigned\n",
  3912. SDE_STAGE_MAX - SDE_STAGE_0);
  3913. return -EINVAL;
  3914. } else if (zpos_cnt == 2) {
  3915. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  3916. return -EINVAL;
  3917. } else {
  3918. zpos_cnt++;
  3919. }
  3920. if (!kms->catalog->has_base_layer)
  3921. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  3922. else
  3923. pstates[i].sde_pstate->stage = z_pos;
  3924. SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
  3925. }
  3926. return rc;
  3927. }
  3928. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  3929. struct drm_crtc_state *state,
  3930. struct plane_state *pstates,
  3931. struct sde_multirect_plane_states *multirect_plane)
  3932. {
  3933. struct sde_crtc *sde_crtc;
  3934. struct sde_crtc_state *cstate;
  3935. struct sde_kms *kms;
  3936. struct drm_plane *plane = NULL;
  3937. struct drm_display_mode *mode;
  3938. int rc = 0, cnt = 0;
  3939. kms = _sde_crtc_get_kms(crtc);
  3940. if (!kms || !kms->catalog) {
  3941. SDE_ERROR("invalid parameters\n");
  3942. return -EINVAL;
  3943. }
  3944. sde_crtc = to_sde_crtc(crtc);
  3945. cstate = to_sde_crtc_state(state);
  3946. mode = &state->adjusted_mode;
  3947. /* get plane state for all drm planes associated with crtc state */
  3948. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  3949. plane, multirect_plane, &cnt);
  3950. if (rc)
  3951. return rc;
  3952. /* assign mixer stages based on sorted zpos property */
  3953. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  3954. if (rc)
  3955. return rc;
  3956. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  3957. if (rc)
  3958. return rc;
  3959. /*
  3960. * validate and set source split:
  3961. * use pstates sorted by stage to check planes on same stage
  3962. * we assume that all pipes are in source split so its valid to compare
  3963. * without taking into account left/right mixer placement
  3964. */
  3965. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  3966. if (rc)
  3967. return rc;
  3968. return 0;
  3969. }
  3970. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  3971. struct drm_crtc_state *state)
  3972. {
  3973. struct drm_device *dev;
  3974. struct sde_crtc *sde_crtc;
  3975. struct plane_state *pstates = NULL;
  3976. struct sde_crtc_state *cstate;
  3977. struct drm_display_mode *mode;
  3978. int rc = 0;
  3979. struct sde_multirect_plane_states *multirect_plane = NULL;
  3980. struct drm_connector *conn;
  3981. struct drm_connector_list_iter conn_iter;
  3982. if (!crtc) {
  3983. SDE_ERROR("invalid crtc\n");
  3984. return -EINVAL;
  3985. }
  3986. dev = crtc->dev;
  3987. sde_crtc = to_sde_crtc(crtc);
  3988. cstate = to_sde_crtc_state(state);
  3989. if (!state->enable || !state->active) {
  3990. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  3991. crtc->base.id, state->enable, state->active);
  3992. goto end;
  3993. }
  3994. pstates = kcalloc(SDE_PSTATES_MAX,
  3995. sizeof(struct plane_state), GFP_KERNEL);
  3996. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  3997. sizeof(struct sde_multirect_plane_states),
  3998. GFP_KERNEL);
  3999. if (!pstates || !multirect_plane) {
  4000. rc = -ENOMEM;
  4001. goto end;
  4002. }
  4003. mode = &state->adjusted_mode;
  4004. SDE_DEBUG("%s: check", sde_crtc->name);
  4005. /* force a full mode set if active state changed */
  4006. if (state->active_changed)
  4007. state->mode_changed = true;
  4008. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4009. if (rc) {
  4010. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4011. crtc->base.id, rc);
  4012. goto end;
  4013. }
  4014. /* identify connectors attached to this crtc */
  4015. cstate->num_connectors = 0;
  4016. drm_connector_list_iter_begin(dev, &conn_iter);
  4017. drm_for_each_connector_iter(conn, &conn_iter)
  4018. if (conn->state && conn->state->crtc == crtc &&
  4019. cstate->num_connectors < MAX_CONNECTORS) {
  4020. cstate->connectors[cstate->num_connectors++] = conn;
  4021. }
  4022. drm_connector_list_iter_end(&conn_iter);
  4023. _sde_crtc_setup_is_ppsplit(state);
  4024. _sde_crtc_setup_lm_bounds(crtc, state);
  4025. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4026. multirect_plane);
  4027. if (rc) {
  4028. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4029. goto end;
  4030. }
  4031. rc = sde_core_perf_crtc_check(crtc, state);
  4032. if (rc) {
  4033. SDE_ERROR("crtc%d failed performance check %d\n",
  4034. crtc->base.id, rc);
  4035. goto end;
  4036. }
  4037. rc = _sde_crtc_check_rois(crtc, state);
  4038. if (rc) {
  4039. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4040. goto end;
  4041. }
  4042. rc = sde_cp_crtc_check_properties(crtc, state);
  4043. if (rc) {
  4044. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4045. crtc->base.id, rc);
  4046. goto end;
  4047. }
  4048. end:
  4049. kfree(pstates);
  4050. kfree(multirect_plane);
  4051. return rc;
  4052. }
  4053. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4054. {
  4055. struct sde_crtc *sde_crtc;
  4056. int ret;
  4057. if (!crtc) {
  4058. SDE_ERROR("invalid crtc\n");
  4059. return -EINVAL;
  4060. }
  4061. sde_crtc = to_sde_crtc(crtc);
  4062. mutex_lock(&sde_crtc->crtc_lock);
  4063. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  4064. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  4065. if (ret)
  4066. SDE_ERROR("%s vblank enable failed: %d\n",
  4067. sde_crtc->name, ret);
  4068. mutex_unlock(&sde_crtc->crtc_lock);
  4069. return 0;
  4070. }
  4071. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4072. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4073. {
  4074. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4075. catalog->mdp[0].has_dest_scaler);
  4076. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4077. catalog->ds_count);
  4078. if (catalog->ds[0].top) {
  4079. sde_kms_info_add_keyint(info,
  4080. "max_dest_scaler_input_width",
  4081. catalog->ds[0].top->maxinputwidth);
  4082. sde_kms_info_add_keyint(info,
  4083. "max_dest_scaler_output_width",
  4084. catalog->ds[0].top->maxoutputwidth);
  4085. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4086. catalog->ds[0].top->maxupscale);
  4087. }
  4088. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4089. msm_property_install_volatile_range(
  4090. &sde_crtc->property_info, "dest_scaler",
  4091. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4092. msm_property_install_blob(&sde_crtc->property_info,
  4093. "ds_lut_ed", 0,
  4094. CRTC_PROP_DEST_SCALER_LUT_ED);
  4095. msm_property_install_blob(&sde_crtc->property_info,
  4096. "ds_lut_cir", 0,
  4097. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4098. msm_property_install_blob(&sde_crtc->property_info,
  4099. "ds_lut_sep", 0,
  4100. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4101. } else if (catalog->ds[0].features
  4102. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4103. msm_property_install_volatile_range(
  4104. &sde_crtc->property_info, "dest_scaler",
  4105. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4106. }
  4107. }
  4108. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4109. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4110. struct sde_kms_info *info)
  4111. {
  4112. msm_property_install_range(&sde_crtc->property_info,
  4113. "core_clk", 0x0, 0, U64_MAX,
  4114. sde_kms->perf.max_core_clk_rate,
  4115. CRTC_PROP_CORE_CLK);
  4116. msm_property_install_range(&sde_crtc->property_info,
  4117. "core_ab", 0x0, 0, U64_MAX,
  4118. catalog->perf.max_bw_high * 1000ULL,
  4119. CRTC_PROP_CORE_AB);
  4120. msm_property_install_range(&sde_crtc->property_info,
  4121. "core_ib", 0x0, 0, U64_MAX,
  4122. catalog->perf.max_bw_high * 1000ULL,
  4123. CRTC_PROP_CORE_IB);
  4124. msm_property_install_range(&sde_crtc->property_info,
  4125. "llcc_ab", 0x0, 0, U64_MAX,
  4126. catalog->perf.max_bw_high * 1000ULL,
  4127. CRTC_PROP_LLCC_AB);
  4128. msm_property_install_range(&sde_crtc->property_info,
  4129. "llcc_ib", 0x0, 0, U64_MAX,
  4130. catalog->perf.max_bw_high * 1000ULL,
  4131. CRTC_PROP_LLCC_IB);
  4132. msm_property_install_range(&sde_crtc->property_info,
  4133. "dram_ab", 0x0, 0, U64_MAX,
  4134. catalog->perf.max_bw_high * 1000ULL,
  4135. CRTC_PROP_DRAM_AB);
  4136. msm_property_install_range(&sde_crtc->property_info,
  4137. "dram_ib", 0x0, 0, U64_MAX,
  4138. catalog->perf.max_bw_high * 1000ULL,
  4139. CRTC_PROP_DRAM_IB);
  4140. msm_property_install_range(&sde_crtc->property_info,
  4141. "rot_prefill_bw", 0, 0, U64_MAX,
  4142. catalog->perf.max_bw_high * 1000ULL,
  4143. CRTC_PROP_ROT_PREFILL_BW);
  4144. msm_property_install_range(&sde_crtc->property_info,
  4145. "rot_clk", 0, 0, U64_MAX,
  4146. sde_kms->perf.max_core_clk_rate,
  4147. CRTC_PROP_ROT_CLK);
  4148. if (catalog->perf.max_bw_low)
  4149. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4150. catalog->perf.max_bw_low * 1000LL);
  4151. if (catalog->perf.max_bw_high)
  4152. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4153. catalog->perf.max_bw_high * 1000LL);
  4154. if (catalog->perf.min_core_ib)
  4155. sde_kms_info_add_keyint(info, "min_core_ib",
  4156. catalog->perf.min_core_ib * 1000LL);
  4157. if (catalog->perf.min_llcc_ib)
  4158. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4159. catalog->perf.min_llcc_ib * 1000LL);
  4160. if (catalog->perf.min_dram_ib)
  4161. sde_kms_info_add_keyint(info, "min_dram_ib",
  4162. catalog->perf.min_dram_ib * 1000LL);
  4163. if (sde_kms->perf.max_core_clk_rate)
  4164. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4165. sde_kms->perf.max_core_clk_rate);
  4166. }
  4167. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4168. struct sde_mdss_cfg *catalog)
  4169. {
  4170. int i, j;
  4171. sde_kms_info_reset(info);
  4172. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4173. sde_kms_info_add_keyint(info, "max_linewidth",
  4174. catalog->max_mixer_width);
  4175. sde_kms_info_add_keyint(info, "max_blendstages",
  4176. catalog->max_mixer_blendstages);
  4177. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
  4178. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4179. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
  4180. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4181. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
  4182. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4183. sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
  4184. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4185. catalog->macrotile_mode);
  4186. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4187. catalog->mdp[0].highest_bank_bit);
  4188. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4189. catalog->mdp[0].ubwc_swizzle);
  4190. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4191. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4192. else
  4193. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4194. if (sde_is_custom_client()) {
  4195. /* No support for SMART_DMA_V1 yet */
  4196. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4197. sde_kms_info_add_keystr(info,
  4198. "smart_dma_rev", "smart_dma_v2");
  4199. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4200. sde_kms_info_add_keystr(info,
  4201. "smart_dma_rev", "smart_dma_v2p5");
  4202. }
  4203. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4204. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4205. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4206. if (catalog->uidle_cfg.uidle_rev)
  4207. sde_kms_info_add_keyint(info, "has_uidle",
  4208. true);
  4209. for (i = 0; i < catalog->limit_count; i++) {
  4210. sde_kms_info_add_keyint(info,
  4211. catalog->limit_cfg[i].name,
  4212. catalog->limit_cfg[i].lmt_case_cnt);
  4213. for (j = 0; j < catalog->limit_cfg[i].lmt_case_cnt; j++) {
  4214. sde_kms_info_add_keyint(info,
  4215. catalog->limit_cfg[i].vector_cfg[j].usecase,
  4216. catalog->limit_cfg[i].vector_cfg[j].value);
  4217. }
  4218. if (!strcmp(catalog->limit_cfg[i].name,
  4219. "sspp_linewidth_usecases"))
  4220. sde_kms_info_add_keyint(info,
  4221. "sspp_linewidth_values",
  4222. catalog->limit_cfg[i].lmt_vec_cnt);
  4223. else if (!strcmp(catalog->limit_cfg[i].name,
  4224. "sde_bwlimit_usecases"))
  4225. sde_kms_info_add_keyint(info,
  4226. "sde_bwlimit_values",
  4227. catalog->limit_cfg[i].lmt_vec_cnt);
  4228. for (j = 0; j < catalog->limit_cfg[i].lmt_vec_cnt; j++) {
  4229. sde_kms_info_add_keyint(info, "limit_usecase",
  4230. catalog->limit_cfg[i].value_cfg[j].use_concur);
  4231. sde_kms_info_add_keyint(info, "limit_value",
  4232. catalog->limit_cfg[i].value_cfg[j].value);
  4233. }
  4234. }
  4235. sde_kms_info_add_keystr(info, "core_ib_ff",
  4236. catalog->perf.core_ib_ff);
  4237. sde_kms_info_add_keystr(info, "core_clk_ff",
  4238. catalog->perf.core_clk_ff);
  4239. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4240. catalog->perf.comp_ratio_rt);
  4241. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4242. catalog->perf.comp_ratio_nrt);
  4243. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4244. catalog->perf.dest_scale_prefill_lines);
  4245. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4246. catalog->perf.undersized_prefill_lines);
  4247. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4248. catalog->perf.macrotile_prefill_lines);
  4249. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4250. catalog->perf.yuv_nv12_prefill_lines);
  4251. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4252. catalog->perf.linear_prefill_lines);
  4253. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4254. catalog->perf.downscaling_prefill_lines);
  4255. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4256. catalog->perf.xtra_prefill_lines);
  4257. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4258. catalog->perf.amortizable_threshold);
  4259. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4260. catalog->perf.min_prefill_lines);
  4261. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4262. catalog->perf.num_mnoc_ports);
  4263. sde_kms_info_add_keyint(info, "axi_bus_width",
  4264. catalog->perf.axi_bus_width);
  4265. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4266. catalog->sui_supported_blendstage);
  4267. if (catalog->ubwc_bw_calc_version)
  4268. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4269. catalog->ubwc_bw_calc_version);
  4270. }
  4271. /**
  4272. * sde_crtc_install_properties - install all drm properties for crtc
  4273. * @crtc: Pointer to drm crtc structure
  4274. */
  4275. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4276. struct sde_mdss_cfg *catalog)
  4277. {
  4278. struct sde_crtc *sde_crtc;
  4279. struct sde_kms_info *info;
  4280. struct sde_kms *sde_kms;
  4281. static const struct drm_prop_enum_list e_secure_level[] = {
  4282. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4283. {SDE_DRM_SEC_ONLY, "sec_only"},
  4284. };
  4285. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4286. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4287. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4288. };
  4289. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4290. {IDLE_PC_NONE, "idle_pc_none"},
  4291. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4292. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4293. };
  4294. SDE_DEBUG("\n");
  4295. if (!crtc || !catalog) {
  4296. SDE_ERROR("invalid crtc or catalog\n");
  4297. return;
  4298. }
  4299. sde_crtc = to_sde_crtc(crtc);
  4300. sde_kms = _sde_crtc_get_kms(crtc);
  4301. if (!sde_kms) {
  4302. SDE_ERROR("invalid argument\n");
  4303. return;
  4304. }
  4305. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4306. if (!info) {
  4307. SDE_ERROR("failed to allocate info memory\n");
  4308. return;
  4309. }
  4310. sde_crtc_setup_capabilities_blob(info, catalog);
  4311. msm_property_install_range(&sde_crtc->property_info,
  4312. "input_fence_timeout", 0x0, 0,
  4313. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4314. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4315. msm_property_install_volatile_range(&sde_crtc->property_info,
  4316. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4317. msm_property_install_range(&sde_crtc->property_info,
  4318. "output_fence_offset", 0x0, 0, 1, 0,
  4319. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4320. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4321. msm_property_install_range(&sde_crtc->property_info,
  4322. "idle_time", 0, 0, U64_MAX, 0,
  4323. CRTC_PROP_IDLE_TIMEOUT);
  4324. if (catalog->has_idle_pc)
  4325. msm_property_install_enum(&sde_crtc->property_info,
  4326. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4327. ARRAY_SIZE(e_idle_pc_state),
  4328. CRTC_PROP_IDLE_PC_STATE);
  4329. if (catalog->has_cwb_support)
  4330. msm_property_install_enum(&sde_crtc->property_info,
  4331. "capture_mode", 0, 0, e_cwb_data_points,
  4332. ARRAY_SIZE(e_cwb_data_points),
  4333. CRTC_PROP_CAPTURE_OUTPUT);
  4334. msm_property_install_volatile_range(&sde_crtc->property_info,
  4335. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4336. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4337. 0x0, 0, e_secure_level,
  4338. ARRAY_SIZE(e_secure_level),
  4339. CRTC_PROP_SECURITY_LEVEL);
  4340. if (catalog->has_dim_layer) {
  4341. msm_property_install_volatile_range(&sde_crtc->property_info,
  4342. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4343. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4344. SDE_MAX_DIM_LAYERS);
  4345. }
  4346. if (catalog->mdp[0].has_dest_scaler)
  4347. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4348. info);
  4349. if (catalog->dspp_count && catalog->rc_count)
  4350. sde_kms_info_add_keyint(info, "rc_mem_size",
  4351. catalog->dspp[0].sblk->rc.mem_total_size);
  4352. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4353. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4354. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4355. catalog->has_base_layer);
  4356. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4357. info->data, SDE_KMS_INFO_DATALEN(info),
  4358. CRTC_PROP_INFO);
  4359. kfree(info);
  4360. }
  4361. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4362. const struct drm_crtc_state *state, uint64_t *val)
  4363. {
  4364. struct sde_crtc *sde_crtc;
  4365. struct sde_crtc_state *cstate;
  4366. uint32_t offset;
  4367. bool is_vid = false;
  4368. struct drm_encoder *encoder;
  4369. sde_crtc = to_sde_crtc(crtc);
  4370. cstate = to_sde_crtc_state(state);
  4371. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4372. if (sde_encoder_check_curr_mode(encoder,
  4373. MSM_DISPLAY_VIDEO_MODE))
  4374. is_vid = true;
  4375. if (is_vid)
  4376. break;
  4377. }
  4378. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4379. /*
  4380. * Increment trigger offset for vidoe mode alone as its release fence
  4381. * can be triggered only after the next frame-update. For cmd mode &
  4382. * virtual displays the release fence for the current frame can be
  4383. * triggered right after PP_DONE/WB_DONE interrupt
  4384. */
  4385. if (is_vid)
  4386. offset++;
  4387. /*
  4388. * Hwcomposer now queries the fences using the commit list in atomic
  4389. * commit ioctl. The offset should be set to next timeline
  4390. * which will be incremented during the prepare commit phase
  4391. */
  4392. offset++;
  4393. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4394. }
  4395. /**
  4396. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4397. * @crtc: Pointer to drm crtc structure
  4398. * @state: Pointer to drm crtc state structure
  4399. * @property: Pointer to targeted drm property
  4400. * @val: Updated property value
  4401. * @Returns: Zero on success
  4402. */
  4403. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4404. struct drm_crtc_state *state,
  4405. struct drm_property *property,
  4406. uint64_t val)
  4407. {
  4408. struct sde_crtc *sde_crtc;
  4409. struct sde_crtc_state *cstate;
  4410. int idx, ret;
  4411. uint64_t fence_user_fd;
  4412. uint64_t __user prev_user_fd;
  4413. if (!crtc || !state || !property) {
  4414. SDE_ERROR("invalid argument(s)\n");
  4415. return -EINVAL;
  4416. }
  4417. sde_crtc = to_sde_crtc(crtc);
  4418. cstate = to_sde_crtc_state(state);
  4419. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4420. /* check with cp property system first */
  4421. ret = sde_cp_crtc_set_property(crtc, property, val);
  4422. if (ret != -ENOENT)
  4423. goto exit;
  4424. /* if not handled by cp, check msm_property system */
  4425. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4426. &cstate->property_state, property, val);
  4427. if (ret)
  4428. goto exit;
  4429. idx = msm_property_index(&sde_crtc->property_info, property);
  4430. switch (idx) {
  4431. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4432. _sde_crtc_set_input_fence_timeout(cstate);
  4433. break;
  4434. case CRTC_PROP_DIM_LAYER_V1:
  4435. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4436. (void __user *)(uintptr_t)val);
  4437. break;
  4438. case CRTC_PROP_ROI_V1:
  4439. ret = _sde_crtc_set_roi_v1(state,
  4440. (void __user *)(uintptr_t)val);
  4441. break;
  4442. case CRTC_PROP_DEST_SCALER:
  4443. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4444. (void __user *)(uintptr_t)val);
  4445. break;
  4446. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4447. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4448. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4449. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4450. break;
  4451. case CRTC_PROP_CORE_CLK:
  4452. case CRTC_PROP_CORE_AB:
  4453. case CRTC_PROP_CORE_IB:
  4454. cstate->bw_control = true;
  4455. break;
  4456. case CRTC_PROP_LLCC_AB:
  4457. case CRTC_PROP_LLCC_IB:
  4458. case CRTC_PROP_DRAM_AB:
  4459. case CRTC_PROP_DRAM_IB:
  4460. cstate->bw_control = true;
  4461. cstate->bw_split_vote = true;
  4462. break;
  4463. case CRTC_PROP_OUTPUT_FENCE:
  4464. if (!val)
  4465. goto exit;
  4466. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4467. sizeof(uint64_t));
  4468. if (ret) {
  4469. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4470. ret = -EFAULT;
  4471. goto exit;
  4472. }
  4473. /*
  4474. * client is expected to reset the property to -1 before
  4475. * requesting for the release fence
  4476. */
  4477. if (prev_user_fd == -1) {
  4478. ret = _sde_crtc_get_output_fence(crtc, state,
  4479. &fence_user_fd);
  4480. if (ret) {
  4481. SDE_ERROR("fence create failed rc:%d\n", ret);
  4482. goto exit;
  4483. }
  4484. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4485. &fence_user_fd, sizeof(uint64_t));
  4486. if (ret) {
  4487. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4488. put_unused_fd(fence_user_fd);
  4489. ret = -EFAULT;
  4490. goto exit;
  4491. }
  4492. }
  4493. break;
  4494. default:
  4495. /* nothing to do */
  4496. break;
  4497. }
  4498. exit:
  4499. if (ret) {
  4500. if (ret != -EPERM)
  4501. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4502. crtc->name, DRMID(property),
  4503. property->name, ret);
  4504. else
  4505. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4506. crtc->name, DRMID(property),
  4507. property->name, ret);
  4508. } else {
  4509. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4510. property->base.id, val);
  4511. }
  4512. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4513. return ret;
  4514. }
  4515. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  4516. {
  4517. struct drm_plane *plane;
  4518. struct drm_plane_state *state;
  4519. struct sde_plane_state *pstate;
  4520. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4521. state = plane->state;
  4522. if (!state)
  4523. continue;
  4524. pstate = to_sde_plane_state(state);
  4525. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  4526. }
  4527. }
  4528. /**
  4529. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4530. * @crtc: Pointer to drm crtc structure
  4531. * @state: Pointer to drm crtc state structure
  4532. * @property: Pointer to targeted drm property
  4533. * @val: Pointer to variable for receiving property value
  4534. * @Returns: Zero on success
  4535. */
  4536. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4537. const struct drm_crtc_state *state,
  4538. struct drm_property *property,
  4539. uint64_t *val)
  4540. {
  4541. struct sde_crtc *sde_crtc;
  4542. struct sde_crtc_state *cstate;
  4543. int ret = -EINVAL, i;
  4544. if (!crtc || !state) {
  4545. SDE_ERROR("invalid argument(s)\n");
  4546. goto end;
  4547. }
  4548. sde_crtc = to_sde_crtc(crtc);
  4549. cstate = to_sde_crtc_state(state);
  4550. i = msm_property_index(&sde_crtc->property_info, property);
  4551. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4552. *val = ~0;
  4553. ret = 0;
  4554. } else {
  4555. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4556. &cstate->property_state, property, val);
  4557. if (ret)
  4558. ret = sde_cp_crtc_get_property(crtc, property, val);
  4559. }
  4560. if (ret)
  4561. DRM_ERROR("get property failed\n");
  4562. end:
  4563. return ret;
  4564. }
  4565. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4566. struct drm_crtc_state *crtc_state)
  4567. {
  4568. struct sde_crtc *sde_crtc;
  4569. struct sde_crtc_state *cstate;
  4570. struct drm_property *drm_prop;
  4571. enum msm_mdp_crtc_property prop_idx;
  4572. if (!crtc || !crtc_state) {
  4573. SDE_ERROR("invalid params\n");
  4574. return -EINVAL;
  4575. }
  4576. sde_crtc = to_sde_crtc(crtc);
  4577. cstate = to_sde_crtc_state(crtc_state);
  4578. sde_cp_crtc_clear(crtc);
  4579. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4580. uint64_t val = cstate->property_values[prop_idx].value;
  4581. uint64_t def;
  4582. int ret;
  4583. drm_prop = msm_property_index_to_drm_property(
  4584. &sde_crtc->property_info, prop_idx);
  4585. if (!drm_prop) {
  4586. /* not all props will be installed, based on caps */
  4587. SDE_DEBUG("%s: invalid property index %d\n",
  4588. sde_crtc->name, prop_idx);
  4589. continue;
  4590. }
  4591. def = msm_property_get_default(&sde_crtc->property_info,
  4592. prop_idx);
  4593. if (val == def)
  4594. continue;
  4595. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4596. sde_crtc->name, drm_prop->name, prop_idx, val,
  4597. def);
  4598. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4599. def);
  4600. if (ret) {
  4601. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4602. sde_crtc->name, prop_idx, ret);
  4603. continue;
  4604. }
  4605. }
  4606. return 0;
  4607. }
  4608. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4609. {
  4610. struct sde_crtc *sde_crtc;
  4611. struct sde_crtc_mixer *m;
  4612. int i;
  4613. if (!crtc) {
  4614. SDE_ERROR("invalid argument\n");
  4615. return;
  4616. }
  4617. sde_crtc = to_sde_crtc(crtc);
  4618. sde_crtc->misr_enable_sui = enable;
  4619. sde_crtc->misr_frame_count = frame_count;
  4620. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4621. m = &sde_crtc->mixers[i];
  4622. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4623. continue;
  4624. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4625. }
  4626. }
  4627. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4628. struct sde_crtc_misr_info *crtc_misr_info)
  4629. {
  4630. struct sde_crtc *sde_crtc;
  4631. struct sde_kms *sde_kms;
  4632. if (!crtc_misr_info) {
  4633. SDE_ERROR("invalid misr info\n");
  4634. return;
  4635. }
  4636. crtc_misr_info->misr_enable = false;
  4637. crtc_misr_info->misr_frame_count = 0;
  4638. if (!crtc) {
  4639. SDE_ERROR("invalid crtc\n");
  4640. return;
  4641. }
  4642. sde_kms = _sde_crtc_get_kms(crtc);
  4643. if (!sde_kms) {
  4644. SDE_ERROR("invalid sde_kms\n");
  4645. return;
  4646. }
  4647. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4648. return;
  4649. sde_crtc = to_sde_crtc(crtc);
  4650. crtc_misr_info->misr_enable =
  4651. sde_crtc->misr_enable_debugfs ? true : false;
  4652. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4653. }
  4654. #ifdef CONFIG_DEBUG_FS
  4655. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4656. {
  4657. struct sde_crtc *sde_crtc;
  4658. struct sde_plane_state *pstate = NULL;
  4659. struct sde_crtc_mixer *m;
  4660. struct drm_crtc *crtc;
  4661. struct drm_plane *plane;
  4662. struct drm_display_mode *mode;
  4663. struct drm_framebuffer *fb;
  4664. struct drm_plane_state *state;
  4665. struct sde_crtc_state *cstate;
  4666. int i, out_width, out_height;
  4667. if (!s || !s->private)
  4668. return -EINVAL;
  4669. sde_crtc = s->private;
  4670. crtc = &sde_crtc->base;
  4671. cstate = to_sde_crtc_state(crtc->state);
  4672. mutex_lock(&sde_crtc->crtc_lock);
  4673. mode = &crtc->state->adjusted_mode;
  4674. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4675. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4676. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4677. mode->hdisplay, mode->vdisplay);
  4678. seq_puts(s, "\n");
  4679. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4680. m = &sde_crtc->mixers[i];
  4681. if (!m->hw_lm)
  4682. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4683. else if (!m->hw_ctl)
  4684. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4685. else
  4686. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4687. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4688. out_width, out_height);
  4689. }
  4690. seq_puts(s, "\n");
  4691. for (i = 0; i < cstate->num_dim_layers; i++) {
  4692. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4693. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4694. i, dim_layer->stage, dim_layer->flags);
  4695. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4696. dim_layer->rect.x, dim_layer->rect.y,
  4697. dim_layer->rect.w, dim_layer->rect.h);
  4698. seq_printf(s,
  4699. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4700. dim_layer->color_fill.color_0,
  4701. dim_layer->color_fill.color_1,
  4702. dim_layer->color_fill.color_2,
  4703. dim_layer->color_fill.color_3);
  4704. seq_puts(s, "\n");
  4705. }
  4706. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4707. pstate = to_sde_plane_state(plane->state);
  4708. state = plane->state;
  4709. if (!pstate || !state)
  4710. continue;
  4711. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4712. plane->base.id, pstate->stage, pstate->rotation);
  4713. if (plane->state->fb) {
  4714. fb = plane->state->fb;
  4715. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4716. fb->base.id, (char *) &fb->format->format,
  4717. fb->width, fb->height);
  4718. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4719. seq_printf(s, "cpp[%d]:%u ",
  4720. i, fb->format->cpp[i]);
  4721. seq_puts(s, "\n\t");
  4722. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4723. seq_puts(s, "\n");
  4724. seq_puts(s, "\t");
  4725. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4726. seq_printf(s, "pitches[%d]:%8u ", i,
  4727. fb->pitches[i]);
  4728. seq_puts(s, "\n");
  4729. seq_puts(s, "\t");
  4730. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4731. seq_printf(s, "offsets[%d]:%8u ", i,
  4732. fb->offsets[i]);
  4733. seq_puts(s, "\n");
  4734. }
  4735. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4736. state->src_x >> 16, state->src_y >> 16,
  4737. state->src_w >> 16, state->src_h >> 16);
  4738. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4739. state->crtc_x, state->crtc_y, state->crtc_w,
  4740. state->crtc_h);
  4741. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4742. pstate->multirect_mode, pstate->multirect_index);
  4743. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4744. pstate->excl_rect.x, pstate->excl_rect.y,
  4745. pstate->excl_rect.w, pstate->excl_rect.h);
  4746. seq_puts(s, "\n");
  4747. }
  4748. if (sde_crtc->vblank_cb_count) {
  4749. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4750. u32 diff_ms = ktime_to_ms(diff);
  4751. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4752. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4753. seq_printf(s,
  4754. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4755. fps, sde_crtc->vblank_cb_count,
  4756. ktime_to_ms(diff), sde_crtc->play_count);
  4757. /* reset time & count for next measurement */
  4758. sde_crtc->vblank_cb_count = 0;
  4759. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4760. }
  4761. mutex_unlock(&sde_crtc->crtc_lock);
  4762. return 0;
  4763. }
  4764. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4765. {
  4766. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4767. }
  4768. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4769. const char __user *user_buf, size_t count, loff_t *ppos)
  4770. {
  4771. struct drm_crtc *crtc;
  4772. struct sde_crtc *sde_crtc;
  4773. int rc;
  4774. char buf[MISR_BUFF_SIZE + 1];
  4775. u32 frame_count, enable;
  4776. size_t buff_copy;
  4777. struct sde_kms *sde_kms;
  4778. if (!file || !file->private_data)
  4779. return -EINVAL;
  4780. sde_crtc = file->private_data;
  4781. crtc = &sde_crtc->base;
  4782. sde_kms = _sde_crtc_get_kms(crtc);
  4783. if (!sde_kms) {
  4784. SDE_ERROR("invalid sde_kms\n");
  4785. return -EINVAL;
  4786. }
  4787. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4788. if (copy_from_user(buf, user_buf, buff_copy)) {
  4789. SDE_ERROR("buffer copy failed\n");
  4790. return -EINVAL;
  4791. }
  4792. buf[buff_copy] = 0; /* end of string */
  4793. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4794. return -EINVAL;
  4795. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4796. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4797. DRMID(crtc));
  4798. return -EINVAL;
  4799. }
  4800. rc = pm_runtime_get_sync(crtc->dev->dev);
  4801. if (rc < 0)
  4802. return rc;
  4803. sde_crtc->misr_enable_debugfs = enable;
  4804. sde_crtc_misr_setup(crtc, enable, frame_count);
  4805. pm_runtime_put_sync(crtc->dev->dev);
  4806. return count;
  4807. }
  4808. static ssize_t _sde_crtc_misr_read(struct file *file,
  4809. char __user *user_buff, size_t count, loff_t *ppos)
  4810. {
  4811. struct drm_crtc *crtc;
  4812. struct sde_crtc *sde_crtc;
  4813. struct sde_kms *sde_kms;
  4814. struct sde_crtc_mixer *m;
  4815. int i = 0, rc;
  4816. ssize_t len = 0;
  4817. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4818. if (*ppos)
  4819. return 0;
  4820. if (!file || !file->private_data)
  4821. return -EINVAL;
  4822. sde_crtc = file->private_data;
  4823. crtc = &sde_crtc->base;
  4824. sde_kms = _sde_crtc_get_kms(crtc);
  4825. if (!sde_kms)
  4826. return -EINVAL;
  4827. rc = pm_runtime_get_sync(crtc->dev->dev);
  4828. if (rc < 0)
  4829. return rc;
  4830. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4831. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  4832. goto end;
  4833. }
  4834. if (!sde_crtc->misr_enable_debugfs) {
  4835. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4836. "disabled\n");
  4837. goto buff_check;
  4838. }
  4839. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4840. u32 misr_value = 0;
  4841. m = &sde_crtc->mixers[i];
  4842. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  4843. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4844. "invalid\n");
  4845. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  4846. continue;
  4847. }
  4848. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  4849. if (rc) {
  4850. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4851. "invalid\n");
  4852. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  4853. DRMID(crtc), rc);
  4854. continue;
  4855. } else {
  4856. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4857. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  4858. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4859. "0x%x\n", misr_value);
  4860. }
  4861. }
  4862. buff_check:
  4863. if (count <= len) {
  4864. len = 0;
  4865. goto end;
  4866. }
  4867. if (copy_to_user(user_buff, buf, len)) {
  4868. len = -EFAULT;
  4869. goto end;
  4870. }
  4871. *ppos += len; /* increase offset */
  4872. end:
  4873. pm_runtime_put_sync(crtc->dev->dev);
  4874. return len;
  4875. }
  4876. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  4877. static int __prefix ## _open(struct inode *inode, struct file *file) \
  4878. { \
  4879. return single_open(file, __prefix ## _show, inode->i_private); \
  4880. } \
  4881. static const struct file_operations __prefix ## _fops = { \
  4882. .owner = THIS_MODULE, \
  4883. .open = __prefix ## _open, \
  4884. .release = single_release, \
  4885. .read = seq_read, \
  4886. .llseek = seq_lseek, \
  4887. }
  4888. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  4889. {
  4890. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  4891. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4892. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4893. int i;
  4894. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  4895. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  4896. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  4897. crtc->state));
  4898. seq_printf(s, "core_clk_rate: %llu\n",
  4899. sde_crtc->cur_perf.core_clk_rate);
  4900. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  4901. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  4902. seq_printf(s, "bw_ctl[%s]: %llu\n",
  4903. sde_power_handle_get_dbus_name(i),
  4904. sde_crtc->cur_perf.bw_ctl[i]);
  4905. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  4906. sde_power_handle_get_dbus_name(i),
  4907. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  4908. }
  4909. return 0;
  4910. }
  4911. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  4912. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  4913. {
  4914. struct drm_crtc *crtc;
  4915. struct drm_plane *plane;
  4916. struct drm_connector *conn;
  4917. struct drm_mode_object *drm_obj;
  4918. struct sde_crtc *sde_crtc;
  4919. struct sde_crtc_state *cstate;
  4920. struct sde_fence_context *ctx;
  4921. struct drm_connector_list_iter conn_iter;
  4922. struct drm_device *dev;
  4923. if (!s || !s->private)
  4924. return -EINVAL;
  4925. sde_crtc = s->private;
  4926. crtc = &sde_crtc->base;
  4927. dev = crtc->dev;
  4928. cstate = to_sde_crtc_state(crtc->state);
  4929. /* Dump input fence info */
  4930. seq_puts(s, "===Input fence===\n");
  4931. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4932. struct sde_plane_state *pstate;
  4933. struct dma_fence *fence;
  4934. pstate = to_sde_plane_state(plane->state);
  4935. if (!pstate)
  4936. continue;
  4937. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  4938. pstate->stage);
  4939. fence = pstate->input_fence;
  4940. if (fence)
  4941. sde_fence_list_dump(fence, &s);
  4942. }
  4943. /* Dump release fence info */
  4944. seq_puts(s, "\n");
  4945. seq_puts(s, "===Release fence===\n");
  4946. ctx = sde_crtc->output_fence;
  4947. drm_obj = &crtc->base;
  4948. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4949. seq_puts(s, "\n");
  4950. /* Dump retire fence info */
  4951. seq_puts(s, "===Retire fence===\n");
  4952. drm_connector_list_iter_begin(dev, &conn_iter);
  4953. drm_for_each_connector_iter(conn, &conn_iter)
  4954. if (conn->state && conn->state->crtc == crtc &&
  4955. cstate->num_connectors < MAX_CONNECTORS) {
  4956. struct sde_connector *c_conn;
  4957. c_conn = to_sde_connector(conn);
  4958. ctx = c_conn->retire_fence;
  4959. drm_obj = &conn->base;
  4960. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4961. }
  4962. drm_connector_list_iter_end(&conn_iter);
  4963. seq_puts(s, "\n");
  4964. return 0;
  4965. }
  4966. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  4967. {
  4968. return single_open(file, _sde_debugfs_fence_status_show,
  4969. inode->i_private);
  4970. }
  4971. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  4972. {
  4973. struct sde_crtc *sde_crtc;
  4974. struct sde_kms *sde_kms;
  4975. static const struct file_operations debugfs_status_fops = {
  4976. .open = _sde_debugfs_status_open,
  4977. .read = seq_read,
  4978. .llseek = seq_lseek,
  4979. .release = single_release,
  4980. };
  4981. static const struct file_operations debugfs_misr_fops = {
  4982. .open = simple_open,
  4983. .read = _sde_crtc_misr_read,
  4984. .write = _sde_crtc_misr_setup,
  4985. };
  4986. static const struct file_operations debugfs_fps_fops = {
  4987. .open = _sde_debugfs_fps_status,
  4988. .read = seq_read,
  4989. };
  4990. static const struct file_operations debugfs_fence_fops = {
  4991. .open = _sde_debugfs_fence_status,
  4992. .read = seq_read,
  4993. };
  4994. if (!crtc)
  4995. return -EINVAL;
  4996. sde_crtc = to_sde_crtc(crtc);
  4997. sde_kms = _sde_crtc_get_kms(crtc);
  4998. if (!sde_kms)
  4999. return -EINVAL;
  5000. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5001. crtc->dev->primary->debugfs_root);
  5002. if (!sde_crtc->debugfs_root)
  5003. return -ENOMEM;
  5004. /* don't error check these */
  5005. debugfs_create_file("status", 0400,
  5006. sde_crtc->debugfs_root,
  5007. sde_crtc, &debugfs_status_fops);
  5008. debugfs_create_file("state", 0400,
  5009. sde_crtc->debugfs_root,
  5010. &sde_crtc->base,
  5011. &sde_crtc_debugfs_state_fops);
  5012. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5013. sde_crtc, &debugfs_misr_fops);
  5014. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5015. sde_crtc, &debugfs_fps_fops);
  5016. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5017. sde_crtc, &debugfs_fence_fops);
  5018. return 0;
  5019. }
  5020. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5021. {
  5022. struct sde_crtc *sde_crtc;
  5023. if (!crtc)
  5024. return;
  5025. sde_crtc = to_sde_crtc(crtc);
  5026. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5027. }
  5028. #else
  5029. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5030. {
  5031. return 0;
  5032. }
  5033. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5034. {
  5035. }
  5036. #endif /* CONFIG_DEBUG_FS */
  5037. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5038. {
  5039. return _sde_crtc_init_debugfs(crtc);
  5040. }
  5041. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5042. {
  5043. _sde_crtc_destroy_debugfs(crtc);
  5044. }
  5045. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5046. .set_config = drm_atomic_helper_set_config,
  5047. .destroy = sde_crtc_destroy,
  5048. .page_flip = drm_atomic_helper_page_flip,
  5049. .atomic_set_property = sde_crtc_atomic_set_property,
  5050. .atomic_get_property = sde_crtc_atomic_get_property,
  5051. .reset = sde_crtc_reset,
  5052. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5053. .atomic_destroy_state = sde_crtc_destroy_state,
  5054. .late_register = sde_crtc_late_register,
  5055. .early_unregister = sde_crtc_early_unregister,
  5056. };
  5057. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5058. .mode_fixup = sde_crtc_mode_fixup,
  5059. .disable = sde_crtc_disable,
  5060. .atomic_enable = sde_crtc_enable,
  5061. .atomic_check = sde_crtc_atomic_check,
  5062. .atomic_begin = sde_crtc_atomic_begin,
  5063. .atomic_flush = sde_crtc_atomic_flush,
  5064. };
  5065. static void _sde_crtc_event_cb(struct kthread_work *work)
  5066. {
  5067. struct sde_crtc_event *event;
  5068. struct sde_crtc *sde_crtc;
  5069. unsigned long irq_flags;
  5070. if (!work) {
  5071. SDE_ERROR("invalid work item\n");
  5072. return;
  5073. }
  5074. event = container_of(work, struct sde_crtc_event, kt_work);
  5075. /* set sde_crtc to NULL for static work structures */
  5076. sde_crtc = event->sde_crtc;
  5077. if (!sde_crtc)
  5078. return;
  5079. if (event->cb_func)
  5080. event->cb_func(&sde_crtc->base, event->usr);
  5081. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5082. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5083. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5084. }
  5085. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5086. void (*func)(struct drm_crtc *crtc, void *usr),
  5087. void *usr, bool color_processing_event)
  5088. {
  5089. unsigned long irq_flags;
  5090. struct sde_crtc *sde_crtc;
  5091. struct msm_drm_private *priv;
  5092. struct sde_crtc_event *event = NULL;
  5093. u32 crtc_id;
  5094. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5095. SDE_ERROR("invalid parameters\n");
  5096. return -EINVAL;
  5097. }
  5098. sde_crtc = to_sde_crtc(crtc);
  5099. priv = crtc->dev->dev_private;
  5100. crtc_id = drm_crtc_index(crtc);
  5101. /*
  5102. * Obtain an event struct from the private cache. This event
  5103. * queue may be called from ISR contexts, so use a private
  5104. * cache to avoid calling any memory allocation functions.
  5105. */
  5106. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5107. if (!list_empty(&sde_crtc->event_free_list)) {
  5108. event = list_first_entry(&sde_crtc->event_free_list,
  5109. struct sde_crtc_event, list);
  5110. list_del_init(&event->list);
  5111. }
  5112. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5113. if (!event)
  5114. return -ENOMEM;
  5115. /* populate event node */
  5116. event->sde_crtc = sde_crtc;
  5117. event->cb_func = func;
  5118. event->usr = usr;
  5119. /* queue new event request */
  5120. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5121. if (color_processing_event)
  5122. kthread_queue_work(&priv->pp_event_worker,
  5123. &event->kt_work);
  5124. else
  5125. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5126. &event->kt_work);
  5127. return 0;
  5128. }
  5129. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5130. {
  5131. int i, rc = 0;
  5132. if (!sde_crtc) {
  5133. SDE_ERROR("invalid crtc\n");
  5134. return -EINVAL;
  5135. }
  5136. spin_lock_init(&sde_crtc->event_lock);
  5137. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5138. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5139. list_add_tail(&sde_crtc->event_cache[i].list,
  5140. &sde_crtc->event_free_list);
  5141. return rc;
  5142. }
  5143. /*
  5144. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5145. */
  5146. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5147. {
  5148. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5149. idle_notify_work.work);
  5150. struct drm_crtc *crtc;
  5151. struct drm_event event;
  5152. int ret = 0;
  5153. if (!sde_crtc) {
  5154. SDE_ERROR("invalid sde crtc\n");
  5155. } else {
  5156. crtc = &sde_crtc->base;
  5157. event.type = DRM_EVENT_IDLE_NOTIFY;
  5158. event.length = sizeof(u32);
  5159. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  5160. &event, (u8 *)&ret);
  5161. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5162. }
  5163. }
  5164. /* initialize crtc */
  5165. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5166. {
  5167. struct drm_crtc *crtc = NULL;
  5168. struct sde_crtc *sde_crtc = NULL;
  5169. struct msm_drm_private *priv = NULL;
  5170. struct sde_kms *kms = NULL;
  5171. int i, rc;
  5172. priv = dev->dev_private;
  5173. kms = to_sde_kms(priv->kms);
  5174. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5175. if (!sde_crtc)
  5176. return ERR_PTR(-ENOMEM);
  5177. crtc = &sde_crtc->base;
  5178. crtc->dev = dev;
  5179. mutex_init(&sde_crtc->crtc_lock);
  5180. spin_lock_init(&sde_crtc->spin_lock);
  5181. atomic_set(&sde_crtc->frame_pending, 0);
  5182. sde_crtc->enabled = false;
  5183. /* Below parameters are for fps calculation for sysfs node */
  5184. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5185. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5186. sizeof(ktime_t), GFP_KERNEL);
  5187. if (!sde_crtc->fps_info.time_buf)
  5188. SDE_ERROR("invalid buffer\n");
  5189. else
  5190. memset(sde_crtc->fps_info.time_buf, 0,
  5191. sizeof(*(sde_crtc->fps_info.time_buf)));
  5192. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5193. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5194. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5195. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5196. list_add(&sde_crtc->frame_events[i].list,
  5197. &sde_crtc->frame_event_list);
  5198. kthread_init_work(&sde_crtc->frame_events[i].work,
  5199. sde_crtc_frame_event_work);
  5200. }
  5201. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5202. NULL);
  5203. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5204. /* save user friendly CRTC name for later */
  5205. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5206. /* initialize event handling */
  5207. rc = _sde_crtc_init_events(sde_crtc);
  5208. if (rc) {
  5209. drm_crtc_cleanup(crtc);
  5210. kfree(sde_crtc);
  5211. return ERR_PTR(rc);
  5212. }
  5213. /* initialize output fence support */
  5214. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5215. if (IS_ERR(sde_crtc->output_fence)) {
  5216. rc = PTR_ERR(sde_crtc->output_fence);
  5217. SDE_ERROR("failed to init fence, %d\n", rc);
  5218. drm_crtc_cleanup(crtc);
  5219. kfree(sde_crtc);
  5220. return ERR_PTR(rc);
  5221. }
  5222. /* create CRTC properties */
  5223. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5224. priv->crtc_property, sde_crtc->property_data,
  5225. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5226. sizeof(struct sde_crtc_state));
  5227. sde_crtc_install_properties(crtc, kms->catalog);
  5228. /* Install color processing properties */
  5229. sde_cp_crtc_init(crtc);
  5230. sde_cp_crtc_install_properties(crtc);
  5231. sde_crtc->cur_perf.llcc_active = false;
  5232. sde_crtc->new_perf.llcc_active = false;
  5233. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5234. __sde_crtc_idle_notify_work);
  5235. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5236. crtc->base.id,
  5237. sde_crtc->new_perf.llcc_active,
  5238. sde_crtc->cur_perf.llcc_active);
  5239. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5240. return crtc;
  5241. }
  5242. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5243. {
  5244. struct sde_crtc *sde_crtc;
  5245. int rc = 0;
  5246. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5247. SDE_ERROR("invalid input param(s)\n");
  5248. rc = -EINVAL;
  5249. goto end;
  5250. }
  5251. sde_crtc = to_sde_crtc(crtc);
  5252. sde_crtc->sysfs_dev = device_create_with_groups(
  5253. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5254. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5255. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5256. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5257. PTR_ERR(sde_crtc->sysfs_dev));
  5258. if (!sde_crtc->sysfs_dev)
  5259. rc = -EINVAL;
  5260. else
  5261. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5262. goto end;
  5263. }
  5264. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5265. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5266. if (!sde_crtc->vsync_event_sf)
  5267. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5268. crtc->base.id);
  5269. end:
  5270. return rc;
  5271. }
  5272. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5273. struct drm_crtc *crtc_drm, u32 event)
  5274. {
  5275. struct sde_crtc *crtc = NULL;
  5276. struct sde_crtc_irq_info *node;
  5277. unsigned long flags;
  5278. bool found = false;
  5279. int ret, i = 0;
  5280. bool add_event = false;
  5281. crtc = to_sde_crtc(crtc_drm);
  5282. spin_lock_irqsave(&crtc->spin_lock, flags);
  5283. list_for_each_entry(node, &crtc->user_event_list, list) {
  5284. if (node->event == event) {
  5285. found = true;
  5286. break;
  5287. }
  5288. }
  5289. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5290. /* event already enabled */
  5291. if (found)
  5292. return 0;
  5293. node = NULL;
  5294. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5295. if (custom_events[i].event == event &&
  5296. custom_events[i].func) {
  5297. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5298. if (!node)
  5299. return -ENOMEM;
  5300. INIT_LIST_HEAD(&node->list);
  5301. INIT_LIST_HEAD(&node->irq.list);
  5302. node->func = custom_events[i].func;
  5303. node->event = event;
  5304. node->state = IRQ_NOINIT;
  5305. spin_lock_init(&node->state_lock);
  5306. break;
  5307. }
  5308. }
  5309. if (!node) {
  5310. SDE_ERROR("unsupported event %x\n", event);
  5311. return -EINVAL;
  5312. }
  5313. ret = 0;
  5314. if (crtc_drm->enabled) {
  5315. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5316. if (ret < 0) {
  5317. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5318. kfree(node);
  5319. return ret;
  5320. }
  5321. INIT_LIST_HEAD(&node->irq.list);
  5322. mutex_lock(&crtc->crtc_lock);
  5323. ret = node->func(crtc_drm, true, &node->irq);
  5324. if (!ret) {
  5325. spin_lock_irqsave(&crtc->spin_lock, flags);
  5326. list_add_tail(&node->list, &crtc->user_event_list);
  5327. add_event = true;
  5328. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5329. }
  5330. mutex_unlock(&crtc->crtc_lock);
  5331. pm_runtime_put_sync(crtc_drm->dev->dev);
  5332. }
  5333. if (add_event)
  5334. return 0;
  5335. if (!ret) {
  5336. spin_lock_irqsave(&crtc->spin_lock, flags);
  5337. list_add_tail(&node->list, &crtc->user_event_list);
  5338. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5339. } else {
  5340. kfree(node);
  5341. }
  5342. return ret;
  5343. }
  5344. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5345. struct drm_crtc *crtc_drm, u32 event)
  5346. {
  5347. struct sde_crtc *crtc = NULL;
  5348. struct sde_crtc_irq_info *node = NULL;
  5349. unsigned long flags;
  5350. bool found = false;
  5351. int ret;
  5352. crtc = to_sde_crtc(crtc_drm);
  5353. spin_lock_irqsave(&crtc->spin_lock, flags);
  5354. list_for_each_entry(node, &crtc->user_event_list, list) {
  5355. if (node->event == event) {
  5356. list_del_init(&node->list);
  5357. found = true;
  5358. break;
  5359. }
  5360. }
  5361. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5362. /* event already disabled */
  5363. if (!found)
  5364. return 0;
  5365. /**
  5366. * crtc is disabled interrupts are cleared remove from the list,
  5367. * no need to disable/de-register.
  5368. */
  5369. if (!crtc_drm->enabled) {
  5370. kfree(node);
  5371. return 0;
  5372. }
  5373. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5374. if (ret < 0) {
  5375. SDE_ERROR("failed to enable power resource %d\n", ret);
  5376. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5377. kfree(node);
  5378. return ret;
  5379. }
  5380. ret = node->func(crtc_drm, false, &node->irq);
  5381. if (ret) {
  5382. spin_lock_irqsave(&crtc->spin_lock, flags);
  5383. list_add_tail(&node->list, &crtc->user_event_list);
  5384. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5385. } else {
  5386. kfree(node);
  5387. }
  5388. pm_runtime_put_sync(crtc_drm->dev->dev);
  5389. return ret;
  5390. }
  5391. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5392. struct drm_crtc *crtc_drm, u32 event, bool en)
  5393. {
  5394. struct sde_crtc *crtc = NULL;
  5395. int ret;
  5396. crtc = to_sde_crtc(crtc_drm);
  5397. if (!crtc || !kms || !kms->dev) {
  5398. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5399. kms, ((kms) ? (kms->dev) : NULL));
  5400. return -EINVAL;
  5401. }
  5402. if (en)
  5403. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5404. else
  5405. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5406. return ret;
  5407. }
  5408. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5409. bool en, struct sde_irq_callback *irq)
  5410. {
  5411. return 0;
  5412. }
  5413. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5414. struct sde_irq_callback *noirq)
  5415. {
  5416. /*
  5417. * IRQ object noirq is not being used here since there is
  5418. * no crtc irq from pm event.
  5419. */
  5420. return 0;
  5421. }
  5422. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5423. bool en, struct sde_irq_callback *irq)
  5424. {
  5425. return 0;
  5426. }
  5427. /**
  5428. * sde_crtc_update_cont_splash_settings - update mixer settings
  5429. * and initial clk during device bootup for cont_splash use case
  5430. * @crtc: Pointer to drm crtc structure
  5431. */
  5432. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5433. {
  5434. struct sde_kms *kms = NULL;
  5435. struct msm_drm_private *priv;
  5436. struct sde_crtc *sde_crtc;
  5437. u64 rate;
  5438. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5439. SDE_ERROR("invalid crtc\n");
  5440. return;
  5441. }
  5442. priv = crtc->dev->dev_private;
  5443. kms = to_sde_kms(priv->kms);
  5444. if (!kms || !kms->catalog) {
  5445. SDE_ERROR("invalid parameters\n");
  5446. return;
  5447. }
  5448. _sde_crtc_setup_mixers(crtc);
  5449. crtc->enabled = true;
  5450. /* update core clk value for initial state with cont-splash */
  5451. sde_crtc = to_sde_crtc(crtc);
  5452. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5453. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5454. rate : kms->perf.max_core_clk_rate;
  5455. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5456. }