wcd939x.c 147 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <sound/soc.h>
  14. #include <sound/tlv.h>
  15. #include <soc/soundwire.h>
  16. #include <linux/regmap.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <asoc/msm-cdc-supply.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <linux/qti-regmap-debugfs.h>
  24. #include "wcd939x-registers.h"
  25. #include "wcd939x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #include "wcd939x-reg-masks.h"
  29. #include "wcd939x-reg-shifts.h"
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD939X_VARIANT_ENTRY_SIZE 32
  32. #define WCD939X_VERSION_1_0 1
  33. #define WCD939X_VERSION_ENTRY_SIZE 32
  34. #define ADC_MODE_VAL_HIFI 0x01
  35. #define ADC_MODE_VAL_LO_HIF 0x02
  36. #define ADC_MODE_VAL_NORMAL 0x03
  37. #define ADC_MODE_VAL_LP 0x05
  38. #define ADC_MODE_VAL_ULP1 0x09
  39. #define ADC_MODE_VAL_ULP2 0x0B
  40. #define NUM_ATTEMPTS 5
  41. #define COMP_MAX_COEFF 25
  42. #define HPH_MODE_MAX 4
  43. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  44. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  45. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  46. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  47. #define WCD939X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  48. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  49. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  50. SNDRV_PCM_RATE_384000)
  51. /* Fractional Rates */
  52. #define WCD939X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  53. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  54. #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  55. SNDRV_PCM_FMTBIT_S24_LE |\
  56. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  57. #define REG_FIELD_VALUE(register_name, field_name, value) \
  58. WCD939X_##register_name, FIELD_MASK(register_name, field_name), \
  59. value << FIELD_SHIFT(register_name, field_name)
  60. #define WCD939X_COMP_OFFSET \
  61. (WCD939X_R_BASE - WCD939X_COMPANDER_HPHL_BASE)
  62. #define WCD939X_XTALK_OFFSET \
  63. (WCD939X_HPHR_RX_PATH_SEC0 - WCD939X_HPHL_RX_PATH_SEC0)
  64. static struct comp_coeff_val
  65. comp_coeff_table [HPH_MODE_MAX][COMP_MAX_COEFF] = {
  66. {
  67. {0x40, 0x00},
  68. {0x4C, 0x00},
  69. {0x5A, 0x00},
  70. {0x6B, 0x00},
  71. {0x7F, 0x00},
  72. {0x97, 0x00},
  73. {0xB3, 0x00},
  74. {0xD5, 0x00},
  75. {0xFD, 0x00},
  76. {0x2D, 0x01},
  77. {0x66, 0x01},
  78. {0xA7, 0x01},
  79. {0xF8, 0x01},
  80. {0x57, 0x02},
  81. {0xC7, 0x02},
  82. {0x4B, 0x03},
  83. {0xE9, 0x03},
  84. {0xA3, 0x04},
  85. {0x7D, 0x05},
  86. {0x90, 0x06},
  87. {0xD1, 0x07},
  88. {0x49, 0x09},
  89. {0x00, 0x0B},
  90. {0x01, 0x0D},
  91. {0x59, 0x0F},
  92. },
  93. {
  94. /*HPH_HIFI, HPH_LOHIFI, HPH_LP*/
  95. {0x40, 0x00},
  96. {0x4C, 0x00},
  97. {0x5A, 0x00},
  98. {0x6B, 0x00},
  99. {0x80, 0x00},
  100. {0x98, 0x00},
  101. {0xB4, 0x00},
  102. {0xD5, 0x00},
  103. {0xFE, 0x00},
  104. {0x2E, 0x01},
  105. {0x66, 0x01},
  106. {0xA9, 0x01},
  107. {0xF8, 0x01},
  108. {0x56, 0x02},
  109. {0xC4, 0x02},
  110. {0x4F, 0x03},
  111. {0xF0, 0x03},
  112. {0xAE, 0x04},
  113. {0x8B, 0x05},
  114. {0x8E, 0x06},
  115. {0xBC, 0x07},
  116. {0x56, 0x09},
  117. {0x0F, 0x0B},
  118. {0x13, 0x0D},
  119. {0x6F, 0x0F},
  120. },
  121. };
  122. enum {
  123. CODEC_TX = 0,
  124. CODEC_RX,
  125. };
  126. enum {
  127. WCD_ADC1 = 0,
  128. WCD_ADC2,
  129. WCD_ADC3,
  130. WCD_ADC4,
  131. ALLOW_BUCK_DISABLE,
  132. HPH_COMP_DELAY,
  133. HPH_PA_DELAY,
  134. AMIC2_BCS_ENABLE,
  135. WCD_SUPPLIES_LPM_MODE,
  136. WCD_ADC1_MODE,
  137. WCD_ADC2_MODE,
  138. WCD_ADC3_MODE,
  139. WCD_ADC4_MODE,
  140. };
  141. enum {
  142. ADC_MODE_INVALID = 0,
  143. ADC_MODE_HIFI,
  144. ADC_MODE_LO_HIF,
  145. ADC_MODE_NORMAL,
  146. ADC_MODE_LP,
  147. ADC_MODE_ULP1,
  148. ADC_MODE_ULP2,
  149. };
  150. static u8 tx_mode_bit[] = {
  151. [ADC_MODE_INVALID] = 0x00,
  152. [ADC_MODE_HIFI] = 0x01,
  153. [ADC_MODE_LO_HIF] = 0x02,
  154. [ADC_MODE_NORMAL] = 0x04,
  155. [ADC_MODE_LP] = 0x08,
  156. [ADC_MODE_ULP1] = 0x10,
  157. [ADC_MODE_ULP2] = 0x20,
  158. };
  159. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  160. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  161. static int wcd939x_handle_post_irq(void *data);
  162. static int wcd939x_reset(struct device *dev);
  163. static int wcd939x_reset_low(struct device *dev);
  164. static int wcd939x_get_adc_mode(int val);
  165. static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
  166. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  167. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  168. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  169. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  170. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
  171. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
  172. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
  173. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
  174. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
  175. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
  176. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
  177. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  178. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  179. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
  180. REGMAP_IRQ_REG(WCD939X_IRQ_LDORT_SCD_INT, 2, 0x01),
  181. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  182. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  183. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  184. };
  185. static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
  186. .name = "wcd939x",
  187. .irqs = wcd939x_irqs,
  188. .num_irqs = ARRAY_SIZE(wcd939x_irqs),
  189. .num_regs = 3,
  190. .status_base = WCD939X_INTR_STATUS_0,
  191. .mask_base = WCD939X_INTR_MASK_0,
  192. .type_base = WCD939X_INTR_LEVEL_0,
  193. .ack_base = WCD939X_INTR_CLEAR_0,
  194. .use_ack = 1,
  195. .runtime_pm = false,
  196. .handle_post_irq = wcd939x_handle_post_irq,
  197. .irq_drv_data = NULL,
  198. };
  199. static int wcd939x_handle_post_irq(void *data)
  200. {
  201. struct wcd939x_priv *wcd939x = data;
  202. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  203. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_0, &sts1);
  204. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_1, &sts2);
  205. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_2, &sts3);
  206. wcd939x->tx_swr_dev->slave_irq_pending =
  207. ((sts1 || sts2 || sts3) ? true : false);
  208. return IRQ_HANDLED;
  209. }
  210. int wcd939x_load_compander_coeff(struct snd_soc_component *component,
  211. u16 lsb_reg, u16 msb_reg,
  212. struct comp_coeff_val *comp_coeff_table,
  213. u16 arr_size)
  214. {
  215. int i = 0;
  216. /* Load Compander Coeff */
  217. for (i = 0; i < arr_size; i++) {
  218. snd_soc_component_write(component, lsb_reg,
  219. comp_coeff_table[i].lsb);
  220. snd_soc_component_write(component, msb_reg,
  221. comp_coeff_table[i].msb);
  222. }
  223. return 0;
  224. }
  225. EXPORT_SYMBOL(wcd939x_load_compander_coeff);
  226. static int wcd939x_hph_compander_get(struct snd_kcontrol *kcontrol,
  227. struct snd_ctl_elem_value *ucontrol)
  228. {
  229. struct snd_soc_component *component =
  230. snd_soc_kcontrol_component(kcontrol);
  231. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  232. int compander = ((struct soc_multi_mixer_control *)
  233. kcontrol->private_value)->shift;
  234. ucontrol->value.integer.value[0] = wcd939x->compander_enabled[compander];
  235. return 0;
  236. }
  237. static int wcd939x_hph_compander_put(struct snd_kcontrol *kcontrol,
  238. struct snd_ctl_elem_value *ucontrol)
  239. {
  240. struct snd_soc_component *component =
  241. snd_soc_kcontrol_component(kcontrol);
  242. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  243. int compander = ((struct soc_multi_mixer_control *)
  244. kcontrol->private_value)->shift;
  245. int value = ucontrol->value.integer.value[0];
  246. if (value < WCD939X_HPH_MAX && value >= 0)
  247. wcd939x->compander_enabled[compander] = value;
  248. else {
  249. dev_err(component->dev, "%s: Invalid comp value = %d\n", __func__, value);
  250. return -EINVAL;
  251. }
  252. dev_dbg(component->dev, "%s: Compander %d value %d\n",
  253. __func__, wcd939x->compander_enabled[compander], value);
  254. return 0;
  255. }
  256. static int wcd939x_hph_xtalk_put(struct snd_kcontrol *kcontrol,
  257. struct snd_ctl_elem_value *ucontrol)
  258. {
  259. struct snd_soc_component *component =
  260. snd_soc_kcontrol_component(kcontrol);
  261. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  262. int xtalk = ((struct soc_multi_mixer_control *)
  263. kcontrol->private_value)->shift;
  264. int value = ucontrol->value.integer.value[0];
  265. if (value < WCD939X_HPH_MAX && value >= 0)
  266. wcd939x->xtalk_enabled[xtalk] = value;
  267. else {
  268. dev_err(component->dev, "%s: Invalid xtalk value = %d\n", __func__, value);
  269. return -EINVAL;
  270. }
  271. dev_dbg(component->dev, "%s: xtalk %d value %d\n",
  272. __func__, wcd939x->xtalk_enabled[xtalk], value);
  273. return 0;
  274. }
  275. static int wcd939x_hph_xtalk_get(struct snd_kcontrol *kcontrol,
  276. struct snd_ctl_elem_value *ucontrol)
  277. {
  278. struct snd_soc_component *component =
  279. snd_soc_kcontrol_component(kcontrol);
  280. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  281. int xtalk = ((struct soc_multi_mixer_control *)
  282. kcontrol->private_value)->shift;
  283. ucontrol->value.integer.value[0] = wcd939x->xtalk_enabled[xtalk];
  284. return 0;
  285. }
  286. static int wcd939x_hph_pcm_enable_put(struct snd_kcontrol *kcontrol,
  287. struct snd_ctl_elem_value *ucontrol)
  288. {
  289. struct snd_soc_component *component =
  290. snd_soc_kcontrol_component(kcontrol);
  291. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  292. wcd939x->hph_pcm_enabled = ucontrol->value.integer.value[0];
  293. dev_dbg(component->dev, "%s: pcm enabled %d \n",
  294. __func__, wcd939x->hph_pcm_enabled);
  295. return 0;
  296. }
  297. static int wcd939x_hph_pcm_enable_get(struct snd_kcontrol *kcontrol,
  298. struct snd_ctl_elem_value *ucontrol)
  299. {
  300. struct snd_soc_component *component =
  301. snd_soc_kcontrol_component(kcontrol);
  302. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  303. ucontrol->value.integer.value[0] = wcd939x->hph_pcm_enabled;
  304. return 0;
  305. }
  306. static int wcd939x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  307. {
  308. int ret = 0;
  309. int bank = 0;
  310. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  311. if (ret)
  312. return -EINVAL;
  313. return ((bank & 0x40) ? 1: 0);
  314. }
  315. static int wcd939x_get_clk_rate(int mode)
  316. {
  317. int rate;
  318. switch (mode) {
  319. case ADC_MODE_ULP2:
  320. rate = SWR_CLK_RATE_0P6MHZ;
  321. break;
  322. case ADC_MODE_ULP1:
  323. rate = SWR_CLK_RATE_1P2MHZ;
  324. break;
  325. case ADC_MODE_LP:
  326. rate = SWR_CLK_RATE_4P8MHZ;
  327. break;
  328. case ADC_MODE_NORMAL:
  329. case ADC_MODE_LO_HIF:
  330. case ADC_MODE_HIFI:
  331. case ADC_MODE_INVALID:
  332. default:
  333. rate = SWR_CLK_RATE_9P6MHZ;
  334. break;
  335. }
  336. return rate;
  337. }
  338. static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component,
  339. int rate, int bank)
  340. {
  341. u8 mask = (bank ? 0xF0 : 0x0F);
  342. u8 val = 0;
  343. switch (rate) {
  344. case SWR_CLK_RATE_0P6MHZ:
  345. val = (bank ? 0x60 : 0x06);
  346. break;
  347. case SWR_CLK_RATE_1P2MHZ:
  348. val = (bank ? 0x50 : 0x05);
  349. break;
  350. case SWR_CLK_RATE_2P4MHZ:
  351. val = (bank ? 0x30 : 0x03);
  352. break;
  353. case SWR_CLK_RATE_4P8MHZ:
  354. val = (bank ? 0x10 : 0x01);
  355. break;
  356. case SWR_CLK_RATE_9P6MHZ:
  357. default:
  358. val = 0x00;
  359. break;
  360. }
  361. snd_soc_component_update_bits(component,
  362. WCD939X_SWR_TX_CLK_RATE,
  363. mask, val);
  364. return 0;
  365. }
  366. static int wcd939x_init_reg(struct snd_soc_component *component)
  367. {
  368. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  369. if (!wcd939x->hph_pcm_enabled)
  370. snd_soc_component_update_bits(component,
  371. REG_FIELD_VALUE(VBG_FINE_ADJ, VBG_FINE_ADJ, 0x04));
  372. snd_soc_component_update_bits(component,
  373. REG_FIELD_VALUE(BIAS, ANALOG_BIAS_EN, 0x01));
  374. snd_soc_component_update_bits(component,
  375. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x01));
  376. /* 10 msec delay as per HW requirement */
  377. usleep_range(10000, 10010);
  378. snd_soc_component_update_bits(component,
  379. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x00));
  380. snd_soc_component_update_bits(component,
  381. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x15));
  382. snd_soc_component_update_bits(component,
  383. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x15));
  384. snd_soc_component_update_bits(component,
  385. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, SPARE_BITS, 0x02));
  386. snd_soc_component_update_bits(component,
  387. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  388. snd_soc_component_update_bits(component,
  389. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_SCBIAS_ULP0P6M, 0x1));
  390. snd_soc_component_update_bits(component,
  391. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_STG2CASC_ULP, 0x4));
  392. snd_soc_component_update_bits(component,
  393. REG_FIELD_VALUE(TXFE_ICTRL_STG2MAIN_ULP, ICTRL_STG2MAIN_ULP, 0x08));
  394. snd_soc_component_update_bits(component,
  395. REG_FIELD_VALUE(TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  396. snd_soc_component_update_bits(component,
  397. REG_FIELD_VALUE(MICB2_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  398. snd_soc_component_update_bits(component,
  399. REG_FIELD_VALUE(MICB3_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  400. snd_soc_component_update_bits(component,
  401. REG_FIELD_VALUE(MICB4_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  402. snd_soc_component_update_bits(component,
  403. REG_FIELD_VALUE(TEST_BLK_EN2, TXFE2_MBHC_CLKRST_EN, 0x00));
  404. snd_soc_component_update_bits(component,
  405. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x01));
  406. snd_soc_component_update_bits(component,
  407. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x01));
  408. snd_soc_component_write(component, WCD939X_CFG0, 0x05);
  409. return 0;
  410. }
  411. static int wcd939x_set_port_params(struct snd_soc_component *component,
  412. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  413. u8 *ch_mask, u32 *ch_rate,
  414. u8 *port_type, u8 path)
  415. {
  416. int i, j;
  417. u8 num_ports = 0;
  418. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  419. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  420. switch (path) {
  421. case CODEC_RX:
  422. map = &wcd939x->rx_port_mapping;
  423. num_ports = wcd939x->num_rx_ports;
  424. break;
  425. case CODEC_TX:
  426. map = &wcd939x->tx_port_mapping;
  427. num_ports = wcd939x->num_tx_ports;
  428. break;
  429. default:
  430. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  431. __func__, path);
  432. return -EINVAL;
  433. }
  434. for (i = 0; i <= num_ports; i++) {
  435. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  436. if ((*map)[i][j].slave_port_type == slv_prt_type)
  437. goto found;
  438. }
  439. }
  440. found:
  441. if (i > num_ports || j == MAX_CH_PER_PORT) {
  442. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  443. __func__, slv_prt_type);
  444. return -EINVAL;
  445. }
  446. *port_id = i;
  447. *num_ch = (*map)[i][j].num_ch;
  448. *ch_mask = (*map)[i][j].ch_mask;
  449. *ch_rate = (*map)[i][j].ch_rate;
  450. *port_type = (*map)[i][j].master_port_type;
  451. return 0;
  452. }
  453. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  454. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  455. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  456. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  457. static int wcd939x_parse_port_params(struct device *dev,
  458. char *prop, u8 path)
  459. {
  460. u32 *dt_array, map_size, max_uc;
  461. int ret = 0;
  462. u32 cnt = 0;
  463. u32 i, j;
  464. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  465. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  466. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  467. switch (path) {
  468. case CODEC_TX:
  469. map = &wcd939x->tx_port_params;
  470. map_uc = &wcd939x->swr_tx_port_params;
  471. break;
  472. default:
  473. ret = -EINVAL;
  474. goto err_port_map;
  475. }
  476. if (!of_find_property(dev->of_node, prop,
  477. &map_size)) {
  478. dev_err(dev, "missing port mapping prop %s\n", prop);
  479. ret = -EINVAL;
  480. goto err_port_map;
  481. }
  482. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  483. if (max_uc != SWR_UC_MAX) {
  484. dev_err(dev, "%s: port params not provided for all usecases\n",
  485. __func__);
  486. ret = -EINVAL;
  487. goto err_port_map;
  488. }
  489. dt_array = kzalloc(map_size, GFP_KERNEL);
  490. if (!dt_array) {
  491. ret = -ENOMEM;
  492. goto err_alloc;
  493. }
  494. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  495. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  496. if (ret) {
  497. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  498. __func__, prop);
  499. goto err_pdata_fail;
  500. }
  501. for (i = 0; i < max_uc; i++) {
  502. for (j = 0; j < SWR_NUM_PORTS; j++) {
  503. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  504. (*map)[i][j].offset1 = dt_array[cnt];
  505. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  506. }
  507. (*map_uc)[i].pp = &(*map)[i][0];
  508. }
  509. kfree(dt_array);
  510. return 0;
  511. err_pdata_fail:
  512. kfree(dt_array);
  513. err_alloc:
  514. err_port_map:
  515. return ret;
  516. }
  517. static int wcd939x_parse_port_mapping(struct device *dev,
  518. char *prop, u8 path)
  519. {
  520. u32 *dt_array, map_size, map_length;
  521. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  522. u32 slave_port_type, master_port_type;
  523. u32 i, ch_iter = 0;
  524. int ret = 0;
  525. u8 *num_ports = NULL;
  526. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  527. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  528. switch (path) {
  529. case CODEC_RX:
  530. map = &wcd939x->rx_port_mapping;
  531. num_ports = &wcd939x->num_rx_ports;
  532. break;
  533. case CODEC_TX:
  534. map = &wcd939x->tx_port_mapping;
  535. num_ports = &wcd939x->num_tx_ports;
  536. break;
  537. default:
  538. dev_err(dev, "%s Invalid path selected %u\n",
  539. __func__, path);
  540. return -EINVAL;
  541. }
  542. if (!of_find_property(dev->of_node, prop,
  543. &map_size)) {
  544. dev_err(dev, "missing port mapping prop %s\n", prop);
  545. ret = -EINVAL;
  546. goto err_port_map;
  547. }
  548. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  549. dt_array = kzalloc(map_size, GFP_KERNEL);
  550. if (!dt_array) {
  551. ret = -ENOMEM;
  552. goto err_alloc;
  553. }
  554. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  555. NUM_SWRS_DT_PARAMS * map_length);
  556. if (ret) {
  557. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  558. __func__, prop);
  559. goto err_pdata_fail;
  560. }
  561. for (i = 0; i < map_length; i++) {
  562. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  563. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  564. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  565. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  566. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  567. if (port_num != old_port_num)
  568. ch_iter = 0;
  569. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  570. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  571. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  572. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  573. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  574. old_port_num = port_num;
  575. }
  576. *num_ports = port_num;
  577. kfree(dt_array);
  578. return 0;
  579. err_pdata_fail:
  580. kfree(dt_array);
  581. err_alloc:
  582. err_port_map:
  583. return ret;
  584. }
  585. static int wcd939x_tx_connect_port(struct snd_soc_component *component,
  586. u8 slv_port_type, int clk_rate,
  587. u8 enable)
  588. {
  589. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  590. u8 port_id, num_ch, ch_mask;
  591. u8 ch_type = 0;
  592. u32 ch_rate;
  593. int slave_ch_idx;
  594. u8 num_port = 1;
  595. int ret = 0;
  596. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  597. &num_ch, &ch_mask, &ch_rate,
  598. &ch_type, CODEC_TX);
  599. if (ret)
  600. return ret;
  601. if (clk_rate)
  602. ch_rate = clk_rate;
  603. slave_ch_idx = wcd939x_slave_get_slave_ch_val(slv_port_type);
  604. if (slave_ch_idx != -EINVAL)
  605. ch_type = wcd939x->tx_master_ch_map[slave_ch_idx];
  606. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  607. __func__, slave_ch_idx, ch_type);
  608. if (enable)
  609. ret = swr_connect_port(wcd939x->tx_swr_dev, &port_id,
  610. num_port, &ch_mask, &ch_rate,
  611. &num_ch, &ch_type);
  612. else
  613. ret = swr_disconnect_port(wcd939x->tx_swr_dev, &port_id,
  614. num_port, &ch_mask, &ch_type);
  615. return ret;
  616. }
  617. static int wcd939x_rx_connect_port(struct snd_soc_component *component,
  618. u8 slv_port_type, u8 enable)
  619. {
  620. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  621. u8 port_id, num_ch, ch_mask, port_type;
  622. u32 ch_rate;
  623. u8 num_port = 1;
  624. int ret = 0;
  625. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  626. &num_ch, &ch_mask, &ch_rate,
  627. &port_type, CODEC_RX);
  628. if (ret)
  629. return ret;
  630. if (enable)
  631. ret = swr_connect_port(wcd939x->rx_swr_dev, &port_id,
  632. num_port, &ch_mask, &ch_rate,
  633. &num_ch, &port_type);
  634. else
  635. ret = swr_disconnect_port(wcd939x->rx_swr_dev, &port_id,
  636. num_port, &ch_mask, &port_type);
  637. return ret;
  638. }
  639. static int wcd939x_rx_clk_enable(struct snd_soc_component *component)
  640. {
  641. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  642. if (wcd939x->rx_clk_cnt == 0) {
  643. snd_soc_component_update_bits(component,
  644. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x01));
  645. /*Analog path clock controls*/
  646. snd_soc_component_update_bits(component,
  647. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x01));
  648. snd_soc_component_update_bits(component,
  649. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x01));
  650. snd_soc_component_update_bits(component,
  651. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x01));
  652. /*Digital path clock controls*/
  653. snd_soc_component_update_bits(component,
  654. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
  655. snd_soc_component_update_bits(component,
  656. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x01));
  657. snd_soc_component_update_bits(component,
  658. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x01));
  659. if (wcd939x->hph_pcm_enabled) {
  660. snd_soc_component_update_bits(component,
  661. REG_FIELD_VALUE(PA_GAIN_CTL_L, RX_SUPPLY_LEVEL, 0x01));
  662. snd_soc_component_update_bits(component,
  663. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0x02));
  664. }
  665. }
  666. wcd939x->rx_clk_cnt++;
  667. return 0;
  668. }
  669. static int wcd939x_rx_clk_disable(struct snd_soc_component *component)
  670. {
  671. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  672. wcd939x->rx_clk_cnt--;
  673. if (wcd939x->rx_clk_cnt == 0) {
  674. snd_soc_component_update_bits(component,
  675. REG_FIELD_VALUE(RX_SUPPLIES, VNEG_EN, 0x00));
  676. snd_soc_component_update_bits(component,
  677. REG_FIELD_VALUE(RX_SUPPLIES, VPOS_EN, 0x00));
  678. snd_soc_component_update_bits(component,
  679. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x00));
  680. snd_soc_component_update_bits(component,
  681. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x00));
  682. snd_soc_component_update_bits(component,
  683. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
  684. snd_soc_component_update_bits(component,
  685. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x00));
  686. snd_soc_component_update_bits(component,
  687. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x00));
  688. snd_soc_component_update_bits(component,
  689. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x00));
  690. snd_soc_component_update_bits(component,
  691. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x00));
  692. }
  693. return 0;
  694. }
  695. /*
  696. * wcd939x_soc_get_mbhc: get wcd939x_mbhc handle of corresponding component
  697. * @component: handle to snd_soc_component *
  698. *
  699. * return wcd939x_mbhc handle or error code in case of failure
  700. */
  701. struct wcd939x_mbhc *wcd939x_soc_get_mbhc(struct snd_soc_component *component)
  702. {
  703. struct wcd939x_priv *wcd939x;
  704. if (!component) {
  705. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  706. return NULL;
  707. }
  708. wcd939x = snd_soc_component_get_drvdata(component);
  709. if (!wcd939x) {
  710. pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
  711. return NULL;
  712. }
  713. return wcd939x->mbhc;
  714. }
  715. EXPORT_SYMBOL(wcd939x_soc_get_mbhc);
  716. static int wcd939x_config_power_mode(struct snd_soc_component *component,
  717. int event, int index, int mode)
  718. {
  719. switch (event) {
  720. case SND_SOC_DAPM_POST_PMU:
  721. if (mode == CLS_H_ULP) {
  722. if (index == WCD939X_HPHL) {
  723. snd_soc_component_update_bits(component,
  724. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x21));
  725. snd_soc_component_update_bits(component,
  726. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x30));
  727. snd_soc_component_update_bits(component,
  728. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x3F));
  729. snd_soc_component_update_bits(component,
  730. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x48));
  731. snd_soc_component_update_bits(component,
  732. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x0C));
  733. } else if (index == WCD939X_HPHR) {
  734. snd_soc_component_update_bits(component,
  735. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x21));
  736. snd_soc_component_update_bits(component,
  737. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x30));
  738. snd_soc_component_update_bits(component,
  739. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x3F));
  740. snd_soc_component_update_bits(component,
  741. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x48));
  742. snd_soc_component_update_bits(component,
  743. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x0C));
  744. }
  745. } else {
  746. if (index == WCD939X_HPHL) {
  747. snd_soc_component_update_bits(component,
  748. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x1E));
  749. snd_soc_component_update_bits(component,
  750. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x2A));
  751. snd_soc_component_update_bits(component,
  752. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x36));
  753. snd_soc_component_update_bits(component,
  754. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x3C));
  755. snd_soc_component_update_bits(component,
  756. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x00));
  757. } else if (index == WCD939X_HPHR) {
  758. snd_soc_component_update_bits(component,
  759. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x1E));
  760. snd_soc_component_update_bits(component,
  761. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x2A));
  762. snd_soc_component_update_bits(component,
  763. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x36));
  764. snd_soc_component_update_bits(component,
  765. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x2C));
  766. snd_soc_component_update_bits(component,
  767. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x00));
  768. }
  769. }
  770. }
  771. return 0;
  772. }
  773. static int wcd939x_enable_hph_pcm_index(struct snd_soc_component *component,
  774. int event, int hph)
  775. {
  776. struct wcd939x_priv *wcd939x = NULL;
  777. if (!component) {
  778. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  779. return -EINVAL;
  780. }
  781. wcd939x = snd_soc_component_get_drvdata(component);
  782. if (!wcd939x->hph_pcm_enabled)
  783. return 0;
  784. switch (event) {
  785. case SND_SOC_DAPM_POST_PMU:
  786. if (hph == WCD939X_HPHL) {
  787. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  788. snd_soc_component_update_bits(component,
  789. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  790. RX_DC_DROOP_COEFF_SEL, 0x2));
  791. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  792. snd_soc_component_update_bits(component,
  793. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  794. RX_DC_DROOP_COEFF_SEL, 0x3));
  795. snd_soc_component_update_bits(component,
  796. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  797. DLY_ZN_EN, 0x1));
  798. snd_soc_component_update_bits(component,
  799. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  800. INT_EN, 0x3));
  801. } else if (hph == WCD939X_HPHR) {
  802. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  803. snd_soc_component_update_bits(component,
  804. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  805. RX_DC_DROOP_COEFF_SEL, 0x2));
  806. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  807. snd_soc_component_update_bits(component,
  808. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  809. RX_DC_DROOP_COEFF_SEL, 0x3));
  810. snd_soc_component_update_bits(component,
  811. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  812. DLY_ZN_EN, 0x1));
  813. snd_soc_component_update_bits(component,
  814. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  815. INT_EN, 0x3));
  816. }
  817. break;
  818. case SND_SOC_DAPM_POST_PMD:
  819. break;
  820. }
  821. return 0;
  822. }
  823. static int wcd939x_config_compander(struct snd_soc_component *component,
  824. int event, int compander_indx)
  825. {
  826. u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
  827. u16 comp_ctl7_reg = 0, comp_ctl0_reg = 0;
  828. u16 comp_en_mask_val = 0;
  829. struct wcd939x_priv *wcd939x;
  830. int hph_mode;
  831. if (compander_indx >= WCD939X_HPH_MAX || compander_indx < 0) {
  832. pr_err_ratelimited("%s: Invalid compander value: %d\n",
  833. __func__, compander_indx);
  834. return -EINVAL;
  835. }
  836. if (!component) {
  837. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  838. return -EINVAL;
  839. }
  840. wcd939x = snd_soc_component_get_drvdata(component);
  841. if (!wcd939x->compander_enabled[compander_indx])
  842. return 0;
  843. hph_mode = wcd939x->hph_mode;
  844. dev_dbg(component->dev, "%s compander_index = %d hph mode = %d\n",
  845. __func__, compander_indx, wcd939x->hph_mode);
  846. if (compander_indx == WCD939X_HPHL) {
  847. comp_coeff_lsb_reg = WCD939X_HPHL_COMP_WR_LSB;
  848. comp_coeff_msb_reg = WCD939X_HPHL_COMP_WR_MSB;
  849. comp_en_mask_val = 1 << 1;
  850. } else if (compander_indx == WCD939X_HPHR) {
  851. comp_coeff_lsb_reg = WCD939X_HPHR_COMP_WR_LSB;
  852. comp_coeff_msb_reg = WCD939X_HPHR_COMP_WR_MSB;
  853. comp_en_mask_val = 1 << 0;
  854. } else {
  855. return 0;
  856. }
  857. comp_ctl0_reg = WCD939X_CTL0 + (compander_indx * WCD939X_COMP_OFFSET);
  858. comp_ctl7_reg = WCD939X_CTL7 + (compander_indx * WCD939X_COMP_OFFSET);
  859. if (SND_SOC_DAPM_EVENT_ON(event)){
  860. snd_soc_component_update_bits(component,
  861. comp_ctl7_reg, 0x1E, 0x00);
  862. /* Enable compander clock*/
  863. snd_soc_component_update_bits(component,
  864. comp_ctl0_reg , 0x01, 0x01);
  865. /* 250us sleep required as per HW Sequence */
  866. usleep_range(250, 260);
  867. snd_soc_component_update_bits(component,
  868. comp_ctl0_reg , 0x02, 0x01);
  869. snd_soc_component_update_bits(component,
  870. comp_ctl0_reg , 0x02, 0x00);
  871. /* Compander coeff values are same for below modes */
  872. if (wcd939x->hph_mode == CLS_H_HIFI || wcd939x->hph_mode == CLS_H_LOHIFI
  873. || wcd939x->hph_mode == CLS_H_LP)
  874. hph_mode = 1;
  875. else if (wcd939x->hph_mode == CLS_H_ULP)
  876. hph_mode = 0;
  877. wcd939x_load_compander_coeff(component, comp_coeff_lsb_reg,
  878. comp_coeff_msb_reg, comp_coeff_table[hph_mode],
  879. COMP_MAX_COEFF);
  880. /* Enable compander*/
  881. snd_soc_component_update_bits(component,
  882. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, comp_en_mask_val);
  883. } if (SND_SOC_DAPM_EVENT_OFF(event)) {
  884. snd_soc_component_update_bits(component,
  885. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, 0x00);
  886. snd_soc_component_update_bits(component,
  887. comp_ctl0_reg , 0x01, 0x00);
  888. }
  889. return 0;
  890. }
  891. static int wcd939x_config_xtalk(struct snd_soc_component *component,
  892. int event, int xtalk_indx)
  893. {
  894. u16 xtalk_sec0 = 0, xtalk_sec1 = 0, xtalk_sec2 = 0, xtalk_sec3 = 0;
  895. struct wcd939x_priv *wcd939x = NULL;
  896. if (!component) {
  897. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  898. return -EINVAL;
  899. }
  900. wcd939x = snd_soc_component_get_drvdata(component);
  901. if (!wcd939x->xtalk_enabled[xtalk_indx])
  902. return 0;
  903. dev_dbg(component->dev, "%s xtalk_indx = %d event = %d\n",
  904. __func__, xtalk_indx, event);
  905. switch(event) {
  906. case SND_SOC_DAPM_PRE_PMU:
  907. xtalk_sec0 = WCD939X_HPHL_RX_PATH_SEC0 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  908. xtalk_sec1 = WCD939X_HPHL_RX_PATH_SEC1 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  909. xtalk_sec2 = WCD939X_HPHL_RX_PATH_SEC2 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  910. xtalk_sec3 = WCD939X_HPHL_RX_PATH_SEC3 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  911. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF, 0xFE);
  912. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F, 0x06);
  913. snd_soc_component_update_bits(component, xtalk_sec3, 0xFF, 0x4F);
  914. snd_soc_component_update_bits(component, xtalk_sec2, 0x1F, 0x11);
  915. break;
  916. case SND_SOC_DAPM_POST_PMU:
  917. /* enable xtalk for L and R channels*/
  918. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  919. 0x0F, 0x0F);
  920. break;
  921. case SND_SOC_DAPM_POST_PMD:
  922. /* Disable Xtalk for L and R channels*/
  923. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  924. 0x00, 0x00);
  925. break;
  926. }
  927. return 0;
  928. }
  929. static int wcd939x_rx_mux(struct snd_soc_dapm_widget *w,
  930. struct snd_kcontrol *kcontrol,
  931. int event)
  932. {
  933. int hph_mode = 0;
  934. struct wcd939x_priv *wcd939x = NULL;
  935. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  936. wcd939x = snd_soc_component_get_drvdata(component);
  937. hph_mode = wcd939x->hph_mode;
  938. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  939. __func__, event, w->shift, w->name);
  940. switch (event) {
  941. case SND_SOC_DAPM_PRE_PMU:
  942. wcd939x_rx_clk_enable(component);
  943. if (wcd939x->hph_pcm_enabled)
  944. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  945. wcd939x_config_compander(component, event, w->shift);
  946. wcd939x_config_xtalk(component, event, w->shift);
  947. break;
  948. case SND_SOC_DAPM_POST_PMU:
  949. wcd939x_config_xtalk(component, event, w->shift);
  950. /*TBD: need to revisit , for both L & R we are updating, but in QCRG only once*/
  951. if (wcd939x->hph_pcm_enabled)
  952. snd_soc_component_update_bits(component,
  953. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x1));
  954. wcd939x_enable_hph_pcm_index(component, event, w->shift);
  955. break;
  956. case SND_SOC_DAPM_POST_PMD:
  957. wcd939x_config_xtalk(component, event, w->shift);
  958. wcd939x_config_compander(component, event, w->shift);
  959. wcd939x_rx_clk_disable(component);
  960. break;
  961. }
  962. return 0;
  963. }
  964. static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  965. struct snd_kcontrol *kcontrol,
  966. int event)
  967. {
  968. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  969. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  970. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  971. w->name, event);
  972. switch (event) {
  973. case SND_SOC_DAPM_PRE_PMU:
  974. if (!wcd939x->hph_pcm_enabled)
  975. snd_soc_component_update_bits(component,
  976. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  977. snd_soc_component_update_bits(component,
  978. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x01));
  979. break;
  980. case SND_SOC_DAPM_POST_PMU:
  981. snd_soc_component_update_bits(component,
  982. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x1D));
  983. if (!wcd939x->hph_pcm_enabled) {
  984. if (wcd939x->comp1_enable) {
  985. snd_soc_component_update_bits(component,
  986. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  987. /* 5msec compander delay as per HW requirement */
  988. if (!wcd939x->comp2_enable ||
  989. (snd_soc_component_read(component,
  990. WCD939X_CDC_COMP_CTL_0) & 0x01))
  991. usleep_range(5000, 5010);
  992. snd_soc_component_update_bits(component,
  993. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  994. } else {
  995. snd_soc_component_update_bits(component,
  996. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
  997. snd_soc_component_update_bits(component,
  998. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x01));
  999. }
  1000. }
  1001. if (wcd939x->hph_pcm_enabled)
  1002. snd_soc_component_update_bits(component,
  1003. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1004. break;
  1005. case SND_SOC_DAPM_POST_PMD:
  1006. snd_soc_component_update_bits(component,
  1007. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x01));
  1008. snd_soc_component_update_bits(component,
  1009. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x00));
  1010. break;
  1011. }
  1012. return 0;
  1013. }
  1014. static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1015. struct snd_kcontrol *kcontrol,
  1016. int event)
  1017. {
  1018. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1019. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1020. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1021. w->name, event);
  1022. switch (event) {
  1023. case SND_SOC_DAPM_PRE_PMU:
  1024. if (!wcd939x->hph_pcm_enabled)
  1025. snd_soc_component_update_bits(component,
  1026. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1027. snd_soc_component_update_bits(component,
  1028. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x01));
  1029. break;
  1030. case SND_SOC_DAPM_POST_PMU:
  1031. snd_soc_component_update_bits(component,
  1032. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x1D));
  1033. if (!wcd939x->hph_pcm_enabled) {
  1034. if (wcd939x->comp1_enable) {
  1035. snd_soc_component_update_bits(component,
  1036. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x01));
  1037. /* 5msec compander delay as per HW requirement */
  1038. if (!wcd939x->comp2_enable ||
  1039. (snd_soc_component_read(component,
  1040. WCD939X_CDC_COMP_CTL_0) & 0x02))
  1041. usleep_range(5000, 5010);
  1042. snd_soc_component_update_bits(component,
  1043. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1044. } else {
  1045. snd_soc_component_update_bits(component,
  1046. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x00));
  1047. snd_soc_component_update_bits(component,
  1048. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x01));
  1049. }
  1050. }
  1051. break;
  1052. case SND_SOC_DAPM_POST_PMD:
  1053. snd_soc_component_update_bits(component,
  1054. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
  1055. snd_soc_component_update_bits(component,
  1056. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x00));
  1057. break;
  1058. }
  1059. return 0;
  1060. }
  1061. static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1062. struct snd_kcontrol *kcontrol,
  1063. int event)
  1064. {
  1065. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1066. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1067. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1068. w->name, event);
  1069. switch (event) {
  1070. case SND_SOC_DAPM_PRE_PMU:
  1071. snd_soc_component_update_bits(component,
  1072. REG_FIELD_VALUE(CDC_EAR_GAIN_CTL, EAR_EN, 0x01));
  1073. snd_soc_component_update_bits(component,
  1074. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
  1075. if (wcd939x->comp1_enable)
  1076. snd_soc_component_update_bits(component,
  1077. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  1078. /* 5 msec delay as per HW requirement */
  1079. usleep_range(5000, 5010);
  1080. if (wcd939x->flyback_cur_det_disable == 0)
  1081. snd_soc_component_update_bits(component,
  1082. REG_FIELD_VALUE(EN, EN_CUR_DET, 0x00));
  1083. wcd939x->flyback_cur_det_disable++;
  1084. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1085. WCD_CLSH_EVENT_PRE_DAC,
  1086. WCD_CLSH_STATE_EAR,
  1087. wcd939x->hph_mode);
  1088. break;
  1089. case SND_SOC_DAPM_POST_PMD:
  1090. snd_soc_component_update_bits(component,
  1091. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  1092. snd_soc_component_update_bits(component,
  1093. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
  1094. if (wcd939x->comp1_enable)
  1095. snd_soc_component_update_bits(component,
  1096. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
  1097. snd_soc_component_update_bits(component,
  1098. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
  1099. snd_soc_component_update_bits(component,
  1100. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x01));
  1101. break;
  1102. };
  1103. return 0;
  1104. }
  1105. static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1106. struct snd_kcontrol *kcontrol,
  1107. int event)
  1108. {
  1109. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1110. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1111. int ret = 0;
  1112. int hph_mode = wcd939x->hph_mode;
  1113. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1114. w->name, event);
  1115. switch (event) {
  1116. case SND_SOC_DAPM_PRE_PMU:
  1117. if (wcd939x->ldoh)
  1118. snd_soc_component_update_bits(component,
  1119. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1120. if (wcd939x->update_wcd_event)
  1121. wcd939x->update_wcd_event(wcd939x->handle,
  1122. SLV_BOLERO_EVT_RX_MUTE,
  1123. (WCD_RX2 << 0x10 | 0x1));
  1124. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1125. wcd939x->rx_swr_dev->dev_num,
  1126. true);
  1127. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1128. WCD_CLSH_EVENT_PRE_DAC,
  1129. WCD_CLSH_STATE_HPHR,
  1130. hph_mode);
  1131. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  1132. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1133. hph_mode == CLS_H_ULP) {
  1134. if (!wcd939x->hph_pcm_enabled)
  1135. snd_soc_component_update_bits(component,
  1136. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1137. }
  1138. snd_soc_component_update_bits(component,
  1139. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x01));
  1140. wcd_clsh_set_hph_mode(component, hph_mode);
  1141. /* update Mode for LOHIFI */
  1142. if (hph_mode == CLS_H_LOHIFI)
  1143. snd_soc_component_update_bits(component,
  1144. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1145. /* 100 usec delay as per HW requirement */
  1146. usleep_range(100, 110);
  1147. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1148. snd_soc_component_update_bits(component,
  1149. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x03));
  1150. break;
  1151. case SND_SOC_DAPM_POST_PMU:
  1152. /*
  1153. * 7ms sleep is required if compander is enabled as per
  1154. * HW requirement. If compander is disabled, then
  1155. * 20ms delay is required.
  1156. */
  1157. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1158. if (!wcd939x->comp2_enable)
  1159. usleep_range(20000, 20100);
  1160. else
  1161. usleep_range(7000, 7100);
  1162. if (hph_mode == CLS_H_LP ||
  1163. hph_mode == CLS_H_LOHIFI ||
  1164. hph_mode == CLS_H_ULP)
  1165. if (!wcd939x->hph_pcm_enabled)
  1166. snd_soc_component_update_bits(component,
  1167. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1168. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1169. }
  1170. snd_soc_component_update_bits(component,
  1171. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1172. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1173. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1174. snd_soc_component_update_bits(component,
  1175. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1176. if (wcd939x->update_wcd_event)
  1177. wcd939x->update_wcd_event(wcd939x->handle,
  1178. SLV_BOLERO_EVT_RX_MUTE,
  1179. (WCD_RX2 << 0x10));
  1180. /*Enable PDM INT for PDM data path only*/
  1181. if (!wcd939x->hph_pcm_enabled)
  1182. wcd_enable_irq(&wcd939x->irq_info,
  1183. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1184. break;
  1185. case SND_SOC_DAPM_PRE_PMD:
  1186. if (wcd939x->update_wcd_event)
  1187. wcd939x->update_wcd_event(wcd939x->handle,
  1188. SLV_BOLERO_EVT_RX_MUTE,
  1189. (WCD_RX2 << 0x10 | 0x1));
  1190. wcd_disable_irq(&wcd939x->irq_info,
  1191. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1192. if (wcd939x->update_wcd_event && wcd939x->comp2_enable)
  1193. wcd939x->update_wcd_event(wcd939x->handle,
  1194. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1195. (WCD_RX2 << 0x10));
  1196. /*
  1197. * 7ms sleep is required if compander is enabled as per
  1198. * HW requirement. If compander is disabled, then
  1199. * 20ms delay is required.
  1200. */
  1201. if (!wcd939x->comp2_enable)
  1202. usleep_range(20000, 20100);
  1203. else
  1204. usleep_range(7000, 7100);
  1205. snd_soc_component_update_bits(component,
  1206. REG_FIELD_VALUE(HPH, HPHR_ENABLE, 0x00));
  1207. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1208. WCD_EVENT_PRE_HPHR_PA_OFF,
  1209. &wcd939x->mbhc->wcd_mbhc);
  1210. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1211. break;
  1212. case SND_SOC_DAPM_POST_PMD:
  1213. /*
  1214. * 7ms sleep is required if compander is enabled as per
  1215. * HW requirement. If compander is disabled, then
  1216. * 20ms delay is required.
  1217. */
  1218. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1219. if (!wcd939x->comp2_enable)
  1220. usleep_range(20000, 20100);
  1221. else
  1222. usleep_range(7000, 7100);
  1223. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1224. }
  1225. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1226. WCD_EVENT_POST_HPHR_PA_OFF,
  1227. &wcd939x->mbhc->wcd_mbhc);
  1228. snd_soc_component_update_bits(component,
  1229. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x00));
  1230. snd_soc_component_update_bits(component,
  1231. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x00));
  1232. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1233. WCD_CLSH_EVENT_POST_PA,
  1234. WCD_CLSH_STATE_HPHR,
  1235. hph_mode);
  1236. if (wcd939x->ldoh)
  1237. snd_soc_component_update_bits(component,
  1238. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1239. break;
  1240. };
  1241. return ret;
  1242. }
  1243. static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1244. struct snd_kcontrol *kcontrol,
  1245. int event)
  1246. {
  1247. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1248. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1249. int ret = 0;
  1250. int hph_mode = wcd939x->hph_mode;
  1251. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1252. w->name, event);
  1253. switch (event) {
  1254. case SND_SOC_DAPM_PRE_PMU:
  1255. if (wcd939x->ldoh)
  1256. snd_soc_component_update_bits(component,
  1257. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1258. if (wcd939x->update_wcd_event)
  1259. wcd939x->update_wcd_event(wcd939x->handle,
  1260. SLV_BOLERO_EVT_RX_MUTE,
  1261. (WCD_RX1 << 0x10 | 0x01));
  1262. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1263. wcd939x->rx_swr_dev->dev_num,
  1264. true);
  1265. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1266. WCD_CLSH_EVENT_PRE_DAC,
  1267. WCD_CLSH_STATE_HPHL,
  1268. hph_mode);
  1269. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  1270. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1271. hph_mode == CLS_H_ULP) {
  1272. if (!wcd939x->hph_pcm_enabled)
  1273. snd_soc_component_update_bits(component,
  1274. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1275. }
  1276. snd_soc_component_update_bits(component,
  1277. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x01));
  1278. wcd_clsh_set_hph_mode(component, hph_mode);
  1279. /* update Mode for LOHIFI */
  1280. if (hph_mode == CLS_H_LOHIFI)
  1281. snd_soc_component_update_bits(component,
  1282. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1283. /* 100 usec delay as per HW requirement */
  1284. usleep_range(100, 110);
  1285. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1286. snd_soc_component_update_bits(component,
  1287. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1288. break;
  1289. case SND_SOC_DAPM_POST_PMU:
  1290. /*
  1291. * 7ms sleep is required if compander is enabled as per
  1292. * HW requirement. If compander is disabled, then
  1293. * 20ms delay is required.
  1294. */
  1295. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1296. if (!wcd939x->comp1_enable)
  1297. usleep_range(20000, 20100);
  1298. else
  1299. usleep_range(7000, 7100);
  1300. if (hph_mode == CLS_H_LP ||
  1301. hph_mode == CLS_H_LOHIFI ||
  1302. hph_mode == CLS_H_ULP)
  1303. if (!wcd939x->hph_pcm_enabled)
  1304. snd_soc_component_update_bits(component,
  1305. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1306. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1307. }
  1308. snd_soc_component_update_bits(component,
  1309. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1310. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1311. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1312. snd_soc_component_update_bits(component,
  1313. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1314. if (wcd939x->update_wcd_event)
  1315. wcd939x->update_wcd_event(wcd939x->handle,
  1316. SLV_BOLERO_EVT_RX_MUTE,
  1317. (WCD_RX1 << 0x10));
  1318. /*Enable PDM INT for PDM data path only*/
  1319. if (!wcd939x->hph_pcm_enabled)
  1320. wcd_enable_irq(&wcd939x->irq_info,
  1321. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1322. break;
  1323. case SND_SOC_DAPM_PRE_PMD:
  1324. if (wcd939x->update_wcd_event)
  1325. wcd939x->update_wcd_event(wcd939x->handle,
  1326. SLV_BOLERO_EVT_RX_MUTE,
  1327. (WCD_RX1 << 0x10 | 0x1));
  1328. wcd_disable_irq(&wcd939x->irq_info,
  1329. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1330. if (wcd939x->update_wcd_event && wcd939x->comp1_enable)
  1331. wcd939x->update_wcd_event(wcd939x->handle,
  1332. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1333. (WCD_RX1 << 0x10));
  1334. /*
  1335. * 7ms sleep is required if compander is enabled as per
  1336. * HW requirement. If compander is disabled, then
  1337. * 20ms delay is required.
  1338. */
  1339. if (!wcd939x->comp1_enable)
  1340. usleep_range(20000, 20100);
  1341. else
  1342. usleep_range(7000, 7100);
  1343. snd_soc_component_update_bits(component,
  1344. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  1345. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1346. WCD_EVENT_PRE_HPHL_PA_OFF,
  1347. &wcd939x->mbhc->wcd_mbhc);
  1348. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1349. break;
  1350. case SND_SOC_DAPM_POST_PMD:
  1351. /*
  1352. * 7ms sleep is required if compander is enabled as per
  1353. * HW requirement. If compander is disabled, then
  1354. * 20ms delay is required.
  1355. */
  1356. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1357. if (!wcd939x->comp1_enable)
  1358. usleep_range(21000, 21100);
  1359. else
  1360. usleep_range(7000, 7100);
  1361. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1362. }
  1363. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1364. WCD_EVENT_POST_HPHL_PA_OFF,
  1365. &wcd939x->mbhc->wcd_mbhc);
  1366. snd_soc_component_update_bits(component,
  1367. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x00));
  1368. snd_soc_component_update_bits(component,
  1369. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1370. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1371. WCD_CLSH_EVENT_POST_PA,
  1372. WCD_CLSH_STATE_HPHL,
  1373. hph_mode);
  1374. if (wcd939x->ldoh)
  1375. snd_soc_component_update_bits(component,
  1376. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1377. break;
  1378. };
  1379. return ret;
  1380. }
  1381. static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1382. struct snd_kcontrol *kcontrol,
  1383. int event)
  1384. {
  1385. struct snd_soc_component *component =
  1386. snd_soc_dapm_to_component(w->dapm);
  1387. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1388. int hph_mode = wcd939x->hph_mode;
  1389. int ret = 0;
  1390. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1391. w->name, event);
  1392. switch (event) {
  1393. case SND_SOC_DAPM_PRE_PMU:
  1394. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1395. wcd939x->rx_swr_dev->dev_num,
  1396. true);
  1397. /*
  1398. * Enable watchdog interrupt for HPHL
  1399. */
  1400. snd_soc_component_update_bits(component,
  1401. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1402. if (!wcd939x->comp1_enable)
  1403. snd_soc_component_update_bits(component,
  1404. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x01));
  1405. break;
  1406. case SND_SOC_DAPM_POST_PMU:
  1407. /* 6 msec delay as per HW requirement */
  1408. usleep_range(6000, 6010);
  1409. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1410. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1411. snd_soc_component_update_bits(component,
  1412. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1413. if (wcd939x->update_wcd_event)
  1414. wcd939x->update_wcd_event(wcd939x->handle,
  1415. SLV_BOLERO_EVT_RX_MUTE,
  1416. (WCD_RX1 << 0x10));
  1417. wcd_enable_irq(&wcd939x->irq_info,
  1418. WCD939X_IRQ_EAR_PDM_WD_INT);
  1419. break;
  1420. case SND_SOC_DAPM_PRE_PMD:
  1421. wcd_disable_irq(&wcd939x->irq_info,
  1422. WCD939X_IRQ_EAR_PDM_WD_INT);
  1423. if (wcd939x->update_wcd_event)
  1424. wcd939x->update_wcd_event(wcd939x->handle,
  1425. SLV_BOLERO_EVT_RX_MUTE,
  1426. (WCD_RX1 << 0x10 | 0x1));
  1427. break;
  1428. case SND_SOC_DAPM_POST_PMD:
  1429. if (!wcd939x->comp1_enable)
  1430. snd_soc_component_update_bits(component,
  1431. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
  1432. /* 7 msec delay as per HW requirement */
  1433. usleep_range(7000, 7010);
  1434. snd_soc_component_update_bits(component,
  1435. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1436. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1437. WCD_CLSH_EVENT_POST_PA,
  1438. WCD_CLSH_STATE_EAR,
  1439. hph_mode);
  1440. wcd939x->flyback_cur_det_disable--;
  1441. if (wcd939x->flyback_cur_det_disable == 0)
  1442. snd_soc_component_update_bits(component,
  1443. REG_FIELD_VALUE(EN, EN_CUR_DET, 0x01));
  1444. break;
  1445. };
  1446. return ret;
  1447. }
  1448. static int wcd939x_enable_clsh(struct snd_soc_dapm_widget *w,
  1449. struct snd_kcontrol *kcontrol,
  1450. int event)
  1451. {
  1452. struct snd_soc_component *component =
  1453. snd_soc_dapm_to_component(w->dapm);
  1454. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1455. int mode = wcd939x->hph_mode;
  1456. int ret = 0;
  1457. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1458. w->name, event);
  1459. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1460. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1461. wcd939x_rx_connect_port(component, CLSH,
  1462. SND_SOC_DAPM_EVENT_ON(event));
  1463. }
  1464. if (SND_SOC_DAPM_EVENT_OFF(event))
  1465. ret = swr_slvdev_datapath_control(
  1466. wcd939x->rx_swr_dev,
  1467. wcd939x->rx_swr_dev->dev_num,
  1468. false);
  1469. return ret;
  1470. }
  1471. static int wcd939x_enable_rx1(struct snd_soc_dapm_widget *w,
  1472. struct snd_kcontrol *kcontrol,
  1473. int event)
  1474. {
  1475. struct snd_soc_component *component =
  1476. snd_soc_dapm_to_component(w->dapm);
  1477. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1478. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1479. w->name, event);
  1480. switch (event) {
  1481. case SND_SOC_DAPM_PRE_PMU:
  1482. if (wcd939x->hph_pcm_enabled)
  1483. wcd939x_rx_connect_port(component, HIFI_PCM_L, true);
  1484. else {
  1485. wcd939x_rx_connect_port(component, HPH_L, true);
  1486. if (wcd939x->comp1_enable)
  1487. wcd939x_rx_connect_port(component, COMP_L, true);
  1488. }
  1489. break;
  1490. case SND_SOC_DAPM_POST_PMD:
  1491. if (wcd939x->hph_pcm_enabled)
  1492. wcd939x_rx_connect_port(component, HIFI_PCM_L, false);
  1493. else {
  1494. wcd939x_rx_connect_port(component, HPH_L, false);
  1495. if (wcd939x->comp1_enable)
  1496. wcd939x_rx_connect_port(component, COMP_L, false);
  1497. }
  1498. break;
  1499. };
  1500. return 0;
  1501. }
  1502. static int wcd939x_enable_rx2(struct snd_soc_dapm_widget *w,
  1503. struct snd_kcontrol *kcontrol, int event)
  1504. {
  1505. struct snd_soc_component *component =
  1506. snd_soc_dapm_to_component(w->dapm);
  1507. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1508. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1509. w->name, event);
  1510. switch (event) {
  1511. case SND_SOC_DAPM_PRE_PMU:
  1512. if (wcd939x->hph_pcm_enabled)
  1513. wcd939x_rx_connect_port(component, HIFI_PCM_R, true);
  1514. else {
  1515. wcd939x_rx_connect_port(component, HPH_R, true);
  1516. if (wcd939x->comp2_enable)
  1517. wcd939x_rx_connect_port(component, COMP_R, true);
  1518. }
  1519. break;
  1520. case SND_SOC_DAPM_POST_PMD:
  1521. if (wcd939x->hph_pcm_enabled)
  1522. wcd939x_rx_connect_port(component, HIFI_PCM_R, false);
  1523. else {
  1524. wcd939x_rx_connect_port(component, HPH_R, false);
  1525. if (wcd939x->comp2_enable)
  1526. wcd939x_rx_connect_port(component, COMP_R, false);
  1527. }
  1528. break;
  1529. };
  1530. return 0;
  1531. }
  1532. static int wcd939x_enable_rx3(struct snd_soc_dapm_widget *w,
  1533. struct snd_kcontrol *kcontrol,
  1534. int event)
  1535. {
  1536. struct snd_soc_component *component =
  1537. snd_soc_dapm_to_component(w->dapm);
  1538. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1539. w->name, event);
  1540. switch (event) {
  1541. case SND_SOC_DAPM_PRE_PMU:
  1542. wcd939x_rx_connect_port(component, LO, true);
  1543. break;
  1544. case SND_SOC_DAPM_POST_PMD:
  1545. wcd939x_rx_connect_port(component, LO, false);
  1546. /* 6 msec delay as per HW requirement */
  1547. usleep_range(6000, 6010);
  1548. break;
  1549. }
  1550. return 0;
  1551. }
  1552. static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1553. struct snd_kcontrol *kcontrol,
  1554. int event)
  1555. {
  1556. struct snd_soc_component *component =
  1557. snd_soc_dapm_to_component(w->dapm);
  1558. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1559. u16 dmic_clk_reg, dmic_clk_en_reg;
  1560. s32 *dmic_clk_cnt;
  1561. u8 dmic_ctl_shift = 0;
  1562. u8 dmic_clk_shift = 0;
  1563. u8 dmic_clk_mask = 0;
  1564. u16 dmic2_left_en = 0;
  1565. int ret = 0;
  1566. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1567. w->name, event);
  1568. switch (w->shift) {
  1569. case 0:
  1570. case 1:
  1571. dmic_clk_cnt = &(wcd939x->dmic_0_1_clk_cnt);
  1572. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1573. dmic_clk_en_reg = WCD939X_CDC_DMIC1_CTL;
  1574. dmic_clk_mask = 0x0F;
  1575. dmic_clk_shift = 0x00;
  1576. dmic_ctl_shift = 0x00;
  1577. break;
  1578. case 2:
  1579. dmic2_left_en = WCD939X_CDC_DMIC2_CTL;
  1580. fallthrough;
  1581. case 3:
  1582. dmic_clk_cnt = &(wcd939x->dmic_2_3_clk_cnt);
  1583. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1584. dmic_clk_en_reg = WCD939X_CDC_DMIC2_CTL;
  1585. dmic_clk_mask = 0xF0;
  1586. dmic_clk_shift = 0x04;
  1587. dmic_ctl_shift = 0x01;
  1588. break;
  1589. case 4:
  1590. case 5:
  1591. dmic_clk_cnt = &(wcd939x->dmic_4_5_clk_cnt);
  1592. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1593. dmic_clk_en_reg = WCD939X_CDC_DMIC3_CTL;
  1594. dmic_clk_mask = 0x0F;
  1595. dmic_clk_shift = 0x00;
  1596. dmic_ctl_shift = 0x02;
  1597. break;
  1598. case 6:
  1599. case 7:
  1600. dmic_clk_cnt = &(wcd939x->dmic_6_7_clk_cnt);
  1601. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1602. dmic_clk_en_reg = WCD939X_CDC_DMIC4_CTL;
  1603. dmic_clk_mask = 0xF0;
  1604. dmic_clk_shift = 0x04;
  1605. dmic_ctl_shift = 0x03;
  1606. break;
  1607. default:
  1608. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1609. __func__);
  1610. return -EINVAL;
  1611. };
  1612. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1613. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1614. switch (event) {
  1615. case SND_SOC_DAPM_PRE_PMU:
  1616. snd_soc_component_update_bits(component,
  1617. WCD939X_CDC_AMIC_CTL,
  1618. (0x01 << dmic_ctl_shift), 0x00);
  1619. /* 250us sleep as per HW requirement */
  1620. usleep_range(250, 260);
  1621. if (dmic2_left_en)
  1622. snd_soc_component_update_bits(component,
  1623. dmic2_left_en, 0x80, 0x80);
  1624. /* Setting DMIC clock rate to 2.4MHz */
  1625. snd_soc_component_update_bits(component,
  1626. dmic_clk_reg, dmic_clk_mask,
  1627. (0x03 << dmic_clk_shift));
  1628. snd_soc_component_update_bits(component,
  1629. dmic_clk_en_reg, 0x08, 0x08);
  1630. /* enable clock scaling */
  1631. snd_soc_component_update_bits(component,
  1632. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  1633. snd_soc_component_update_bits(component,
  1634. REG_FIELD_VALUE(CDC_DMIC_CTL, DMIC_DIV_BAK_EN, 0x01));
  1635. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1636. wcd939x->tx_swr_dev->dev_num,
  1637. true);
  1638. break;
  1639. case SND_SOC_DAPM_POST_PMD:
  1640. wcd939x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1641. false);
  1642. snd_soc_component_update_bits(component,
  1643. WCD939X_CDC_AMIC_CTL,
  1644. (0x01 << dmic_ctl_shift),
  1645. (0x01 << dmic_ctl_shift));
  1646. if (dmic2_left_en)
  1647. snd_soc_component_update_bits(component,
  1648. dmic2_left_en, 0x80, 0x00);
  1649. snd_soc_component_update_bits(component,
  1650. dmic_clk_en_reg, 0x08, 0x00);
  1651. break;
  1652. };
  1653. return ret;
  1654. }
  1655. /*
  1656. * wcd939x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1657. * @micb_mv: micbias in mv
  1658. *
  1659. * return register value converted
  1660. */
  1661. int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
  1662. {
  1663. /* min micbias voltage is 1V and maximum is 2.85V */
  1664. if (micb_mv < 1000 || micb_mv > 2850) {
  1665. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1666. return -EINVAL;
  1667. }
  1668. return (micb_mv - 1000) / 50;
  1669. }
  1670. EXPORT_SYMBOL(wcd939x_get_micb_vout_ctl_val);
  1671. /*
  1672. * wcd939x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1673. * @component: handle to snd_soc_component *
  1674. * @req_volt: micbias voltage to be set
  1675. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1676. *
  1677. * return 0 if adjustment is success or error code in case of failure
  1678. */
  1679. int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1680. int req_volt, int micb_num)
  1681. {
  1682. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1683. int cur_vout_ctl, req_vout_ctl;
  1684. int micb_reg, micb_val, micb_en;
  1685. int ret = 0;
  1686. switch (micb_num) {
  1687. case MIC_BIAS_1:
  1688. micb_reg = WCD939X_MICB1;
  1689. break;
  1690. case MIC_BIAS_2:
  1691. micb_reg = WCD939X_MICB2;
  1692. break;
  1693. case MIC_BIAS_3:
  1694. micb_reg = WCD939X_MICB3;
  1695. break;
  1696. case MIC_BIAS_4:
  1697. micb_reg = WCD939X_MICB4;
  1698. break;
  1699. default:
  1700. return -EINVAL;
  1701. }
  1702. mutex_lock(&wcd939x->micb_lock);
  1703. /*
  1704. * If requested micbias voltage is same as current micbias
  1705. * voltage, then just return. Otherwise, adjust voltage as
  1706. * per requested value. If micbias is already enabled, then
  1707. * to avoid slow micbias ramp-up or down enable pull-up
  1708. * momentarily, change the micbias value and then re-enable
  1709. * micbias.
  1710. */
  1711. micb_val = snd_soc_component_read(component, micb_reg);
  1712. micb_en = (micb_val & 0xC0) >> 6;
  1713. cur_vout_ctl = micb_val & 0x3F;
  1714. req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
  1715. if (req_vout_ctl < 0) {
  1716. ret = -EINVAL;
  1717. goto exit;
  1718. }
  1719. if (cur_vout_ctl == req_vout_ctl) {
  1720. ret = 0;
  1721. goto exit;
  1722. }
  1723. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1724. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1725. req_volt, micb_en);
  1726. if (micb_en == 0x1)
  1727. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1728. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1729. if (micb_en == 0x1) {
  1730. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1731. /*
  1732. * Add 2ms delay as per HW requirement after enabling
  1733. * micbias
  1734. */
  1735. usleep_range(2000, 2100);
  1736. }
  1737. exit:
  1738. mutex_unlock(&wcd939x->micb_lock);
  1739. return ret;
  1740. }
  1741. EXPORT_SYMBOL(wcd939x_mbhc_micb_adjust_voltage);
  1742. static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1743. struct snd_kcontrol *kcontrol,
  1744. int event)
  1745. {
  1746. struct snd_soc_component *component =
  1747. snd_soc_dapm_to_component(w->dapm);
  1748. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1749. int ret = 0;
  1750. int bank = 0;
  1751. u8 mode = 0;
  1752. int i = 0;
  1753. int rate = 0;
  1754. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  1755. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  1756. /* power mode is applicable only to analog mics */
  1757. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1758. /* Get channel rate */
  1759. rate = wcd939x_get_clk_rate(wcd939x->tx_mode[w->shift - ADC1]);
  1760. }
  1761. switch (event) {
  1762. case SND_SOC_DAPM_PRE_PMU:
  1763. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1764. if (w->shift == ADC2 &&
  1765. (((snd_soc_component_read(component, WCD939X_TX_CH12_MUX) &
  1766. 0x38) >> 3) == 0x2)) {
  1767. if (!wcd939x->bcs_dis) {
  1768. wcd939x_tx_connect_port(component, MBHC,
  1769. SWR_CLK_RATE_4P8MHZ, true);
  1770. set_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  1771. }
  1772. }
  1773. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1774. set_bit(w->shift - ADC1, &wcd939x->status_mask);
  1775. wcd939x_tx_connect_port(component, w->shift, rate,
  1776. true);
  1777. } else {
  1778. wcd939x_tx_connect_port(component, w->shift,
  1779. SWR_CLK_RATE_2P4MHZ, true);
  1780. }
  1781. break;
  1782. case SND_SOC_DAPM_POST_PMD:
  1783. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1784. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1785. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  1786. clear_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  1787. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1788. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  1789. clear_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  1790. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1791. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  1792. clear_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  1793. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1794. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  1795. clear_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  1796. }
  1797. }
  1798. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1799. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  1800. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  1801. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  1802. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  1803. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  1804. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  1805. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  1806. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  1807. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  1808. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  1809. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  1810. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  1811. if (mode != 0) {
  1812. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1813. if (mode & (1 << i)) {
  1814. i++;
  1815. break;
  1816. }
  1817. }
  1818. }
  1819. rate = wcd939x_get_clk_rate(i);
  1820. if (wcd939x->adc_count) {
  1821. rate = (wcd939x->adc_count * rate);
  1822. if (rate > SWR_CLK_RATE_9P6MHZ)
  1823. rate = SWR_CLK_RATE_9P6MHZ;
  1824. }
  1825. wcd939x_set_swr_clk_rate(component, rate, bank);
  1826. }
  1827. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1828. wcd939x->tx_swr_dev->dev_num,
  1829. false);
  1830. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1831. wcd939x_set_swr_clk_rate(component, rate, !bank);
  1832. break;
  1833. };
  1834. return ret;
  1835. }
  1836. static int wcd939x_get_adc_mode(int val)
  1837. {
  1838. int ret = 0;
  1839. switch (val) {
  1840. case ADC_MODE_INVALID:
  1841. ret = ADC_MODE_VAL_NORMAL;
  1842. break;
  1843. case ADC_MODE_HIFI:
  1844. ret = ADC_MODE_VAL_HIFI;
  1845. break;
  1846. case ADC_MODE_LO_HIF:
  1847. ret = ADC_MODE_VAL_LO_HIF;
  1848. break;
  1849. case ADC_MODE_NORMAL:
  1850. ret = ADC_MODE_VAL_NORMAL;
  1851. break;
  1852. case ADC_MODE_LP:
  1853. ret = ADC_MODE_VAL_LP;
  1854. break;
  1855. case ADC_MODE_ULP1:
  1856. ret = ADC_MODE_VAL_ULP1;
  1857. break;
  1858. case ADC_MODE_ULP2:
  1859. ret = ADC_MODE_VAL_ULP2;
  1860. break;
  1861. default:
  1862. ret = -EINVAL;
  1863. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1864. break;
  1865. }
  1866. return ret;
  1867. }
  1868. int wcd939x_tx_channel_config(struct snd_soc_component *component,
  1869. int channel, int mode)
  1870. {
  1871. int reg = WCD939X_TX_CH2, mask = 0, val = 0;
  1872. int ret = 0;
  1873. switch (channel) {
  1874. case 0:
  1875. reg = WCD939X_TX_CH2;
  1876. mask = 0x40;
  1877. break;
  1878. case 1:
  1879. reg = WCD939X_TX_CH2;
  1880. mask = 0x20;
  1881. break;
  1882. case 2:
  1883. reg = WCD939X_TX_CH4;
  1884. mask = 0x40;
  1885. break;
  1886. case 3:
  1887. reg = WCD939X_TX_CH4;
  1888. mask = 0x20;
  1889. break;
  1890. default:
  1891. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  1892. ret = -EINVAL;
  1893. break;
  1894. }
  1895. if (!mode)
  1896. val = 0x00;
  1897. else
  1898. val = mask;
  1899. if (!ret)
  1900. snd_soc_component_update_bits(component, reg, mask, val);
  1901. return ret;
  1902. }
  1903. static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1904. struct snd_kcontrol *kcontrol,
  1905. int event){
  1906. struct snd_soc_component *component =
  1907. snd_soc_dapm_to_component(w->dapm);
  1908. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1909. int clk_rate = 0, ret = 0;
  1910. int mode = 0, i = 0, bank = 0;
  1911. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1912. w->name, event);
  1913. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  1914. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  1915. switch (event) {
  1916. case SND_SOC_DAPM_PRE_PMU:
  1917. wcd939x->adc_count++;
  1918. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  1919. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  1920. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  1921. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  1922. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  1923. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  1924. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  1925. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  1926. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  1927. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  1928. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  1929. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  1930. if (mode != 0) {
  1931. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1932. if (mode & (1 << i)) {
  1933. i++;
  1934. break;
  1935. }
  1936. }
  1937. }
  1938. clk_rate = wcd939x_get_clk_rate(i);
  1939. /* clk_rate depends on number of paths getting enabled */
  1940. clk_rate = (wcd939x->adc_count * clk_rate);
  1941. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1942. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1943. wcd939x_set_swr_clk_rate(component, clk_rate, bank);
  1944. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1945. wcd939x->tx_swr_dev->dev_num,
  1946. true);
  1947. wcd939x_set_swr_clk_rate(component, clk_rate, !bank);
  1948. break;
  1949. case SND_SOC_DAPM_POST_PMD:
  1950. wcd939x->adc_count--;
  1951. if (wcd939x->adc_count < 0)
  1952. wcd939x->adc_count = 0;
  1953. wcd939x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1954. if (w->shift + ADC1 == ADC2 &&
  1955. test_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask)) {
  1956. wcd939x_tx_connect_port(component, MBHC, 0,
  1957. false);
  1958. clear_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  1959. }
  1960. break;
  1961. };
  1962. return ret;
  1963. }
  1964. void wcd939x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1965. bool bcs_disable)
  1966. {
  1967. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1968. if (wcd939x->update_wcd_event) {
  1969. if (bcs_disable)
  1970. wcd939x->update_wcd_event(wcd939x->handle,
  1971. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1972. else
  1973. wcd939x->update_wcd_event(wcd939x->handle,
  1974. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1975. }
  1976. }
  1977. static int wcd939x_enable_req(struct snd_soc_dapm_widget *w,
  1978. struct snd_kcontrol *kcontrol, int event)
  1979. {
  1980. struct snd_soc_component *component =
  1981. snd_soc_dapm_to_component(w->dapm);
  1982. struct wcd939x_priv *wcd939x =
  1983. snd_soc_component_get_drvdata(component);
  1984. int ret = 0;
  1985. u8 mode = 0;
  1986. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1987. w->name, event);
  1988. switch (event) {
  1989. case SND_SOC_DAPM_PRE_PMU:
  1990. snd_soc_component_update_bits(component,
  1991. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x01));
  1992. snd_soc_component_update_bits(component,
  1993. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  1994. snd_soc_component_update_bits(component,
  1995. REG_FIELD_VALUE(CDC_REQ_CTL, FS_RATE_4P8, 0x01));
  1996. snd_soc_component_update_bits(component,
  1997. REG_FIELD_VALUE(CDC_REQ_CTL, NO_NOTCH, 0x00));
  1998. ret = wcd939x_tx_channel_config(component, w->shift, 1);
  1999. mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
  2000. if (mode < 0) {
  2001. dev_info_ratelimited(component->dev,
  2002. "%s: invalid mode, setting to normal mode\n",
  2003. __func__);
  2004. mode = ADC_MODE_VAL_NORMAL;
  2005. }
  2006. switch (w->shift) {
  2007. case 0:
  2008. snd_soc_component_update_bits(component,
  2009. WCD939X_CDC_TX_ANA_MODE_0_1, 0x0F,
  2010. mode);
  2011. snd_soc_component_update_bits(component,
  2012. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x01));
  2013. break;
  2014. case 1:
  2015. snd_soc_component_update_bits(component,
  2016. WCD939X_CDC_TX_ANA_MODE_0_1, 0xF0,
  2017. mode << 4);
  2018. snd_soc_component_update_bits(component,
  2019. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x01));
  2020. break;
  2021. case 2:
  2022. snd_soc_component_update_bits(component,
  2023. WCD939X_CDC_TX_ANA_MODE_2_3, 0x0F,
  2024. mode);
  2025. snd_soc_component_update_bits(component,
  2026. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x01));
  2027. break;
  2028. case 3:
  2029. snd_soc_component_update_bits(component,
  2030. WCD939X_CDC_TX_ANA_MODE_2_3, 0xF0,
  2031. mode << 4);
  2032. snd_soc_component_update_bits(component,
  2033. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x01));
  2034. break;
  2035. default:
  2036. break;
  2037. }
  2038. ret |= wcd939x_tx_channel_config(component, w->shift, 0);
  2039. break;
  2040. case SND_SOC_DAPM_POST_PMD:
  2041. switch (w->shift) {
  2042. case 0:
  2043. snd_soc_component_update_bits(component,
  2044. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD0_MODE, 0x00));
  2045. snd_soc_component_update_bits(component,
  2046. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x00));
  2047. break;
  2048. case 1:
  2049. snd_soc_component_update_bits(component,
  2050. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD1_MODE, 0x00));
  2051. snd_soc_component_update_bits(component,
  2052. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x00));
  2053. break;
  2054. case 2:
  2055. snd_soc_component_update_bits(component,
  2056. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD2_MODE, 0x00));
  2057. snd_soc_component_update_bits(component,
  2058. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x00));
  2059. break;
  2060. case 3:
  2061. snd_soc_component_update_bits(component,
  2062. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD3_MODE, 0x00));
  2063. snd_soc_component_update_bits(component,
  2064. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x00));
  2065. break;
  2066. default:
  2067. break;
  2068. }
  2069. if (wcd939x->adc_count == 0) {
  2070. snd_soc_component_update_bits(component,
  2071. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x00));
  2072. snd_soc_component_update_bits(component,
  2073. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x00));
  2074. }
  2075. break;
  2076. };
  2077. return ret;
  2078. }
  2079. int wcd939x_micbias_control(struct snd_soc_component *component,
  2080. int micb_num, int req, bool is_dapm)
  2081. {
  2082. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2083. int micb_index = micb_num - 1;
  2084. u16 micb_reg;
  2085. int pre_off_event = 0, post_off_event = 0;
  2086. int post_on_event = 0, post_dapm_off = 0;
  2087. int post_dapm_on = 0;
  2088. int ret = 0;
  2089. if ((micb_index < 0) || (micb_index > WCD939X_MAX_MICBIAS - 1)) {
  2090. dev_err_ratelimited(component->dev,
  2091. "%s: Invalid micbias index, micb_ind:%d\n",
  2092. __func__, micb_index);
  2093. return -EINVAL;
  2094. }
  2095. if (NULL == wcd939x) {
  2096. dev_err_ratelimited(component->dev,
  2097. "%s: wcd939x private data is NULL\n", __func__);
  2098. return -EINVAL;
  2099. }
  2100. switch (micb_num) {
  2101. case MIC_BIAS_1:
  2102. micb_reg = WCD939X_MICB1;
  2103. break;
  2104. case MIC_BIAS_2:
  2105. micb_reg = WCD939X_MICB2;
  2106. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  2107. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  2108. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  2109. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  2110. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  2111. break;
  2112. case MIC_BIAS_3:
  2113. micb_reg = WCD939X_MICB3;
  2114. break;
  2115. case MIC_BIAS_4:
  2116. micb_reg = WCD939X_MICB4;
  2117. break;
  2118. default:
  2119. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  2120. __func__, micb_num);
  2121. return -EINVAL;
  2122. };
  2123. mutex_lock(&wcd939x->micb_lock);
  2124. switch (req) {
  2125. case MICB_PULLUP_ENABLE:
  2126. if (!wcd939x->dev_up) {
  2127. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2128. __func__, req);
  2129. ret = -ENODEV;
  2130. goto done;
  2131. }
  2132. wcd939x->pullup_ref[micb_index]++;
  2133. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2134. (wcd939x->micb_ref[micb_index] == 0))
  2135. snd_soc_component_update_bits(component, micb_reg,
  2136. 0xC0, 0x80);
  2137. break;
  2138. case MICB_PULLUP_DISABLE:
  2139. if (wcd939x->pullup_ref[micb_index] > 0)
  2140. wcd939x->pullup_ref[micb_index]--;
  2141. if (!wcd939x->dev_up) {
  2142. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2143. __func__, req);
  2144. ret = -ENODEV;
  2145. goto done;
  2146. }
  2147. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2148. (wcd939x->micb_ref[micb_index] == 0))
  2149. snd_soc_component_update_bits(component, micb_reg,
  2150. 0xC0, 0x00);
  2151. break;
  2152. case MICB_ENABLE:
  2153. if (!wcd939x->dev_up) {
  2154. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2155. __func__, req);
  2156. ret = -ENODEV;
  2157. goto done;
  2158. }
  2159. wcd939x->micb_ref[micb_index]++;
  2160. if (wcd939x->micb_ref[micb_index] == 1) {
  2161. snd_soc_component_update_bits(component,
  2162. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD3_CLK_EN, 0x01));
  2163. snd_soc_component_update_bits(component,
  2164. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD2_CLK_EN, 0x01));
  2165. snd_soc_component_update_bits(component,
  2166. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD1_CLK_EN, 0x01));
  2167. snd_soc_component_update_bits(component,
  2168. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD0_CLK_EN, 0x01));
  2169. snd_soc_component_update_bits(component,
  2170. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2171. snd_soc_component_update_bits(component,
  2172. REG_FIELD_VALUE(CDC_ANA_TX_CLK_CTL, ANA_TXSCBIAS_CLK_EN, 0x01));
  2173. snd_soc_component_update_bits(component,
  2174. REG_FIELD_VALUE(TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2175. snd_soc_component_update_bits(component,
  2176. REG_FIELD_VALUE(MICB2_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2177. snd_soc_component_update_bits(component,
  2178. REG_FIELD_VALUE(MICB3_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2179. snd_soc_component_update_bits(component,
  2180. REG_FIELD_VALUE(MICB4_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2181. snd_soc_component_update_bits(component,
  2182. micb_reg, 0xC0, 0x40);
  2183. if (post_on_event)
  2184. blocking_notifier_call_chain(
  2185. &wcd939x->mbhc->notifier,
  2186. post_on_event,
  2187. &wcd939x->mbhc->wcd_mbhc);
  2188. }
  2189. if (is_dapm && post_dapm_on && wcd939x->mbhc)
  2190. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2191. post_dapm_on,
  2192. &wcd939x->mbhc->wcd_mbhc);
  2193. break;
  2194. case MICB_DISABLE:
  2195. if (wcd939x->micb_ref[micb_index] > 0)
  2196. wcd939x->micb_ref[micb_index]--;
  2197. if (!wcd939x->dev_up) {
  2198. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2199. __func__, req);
  2200. ret = -ENODEV;
  2201. goto done;
  2202. }
  2203. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2204. (wcd939x->pullup_ref[micb_index] > 0))
  2205. snd_soc_component_update_bits(component, micb_reg,
  2206. 0xC0, 0x80);
  2207. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2208. (wcd939x->pullup_ref[micb_index] == 0)) {
  2209. if (pre_off_event && wcd939x->mbhc)
  2210. blocking_notifier_call_chain(
  2211. &wcd939x->mbhc->notifier,
  2212. pre_off_event,
  2213. &wcd939x->mbhc->wcd_mbhc);
  2214. snd_soc_component_update_bits(component, micb_reg,
  2215. 0xC0, 0x00);
  2216. if (post_off_event && wcd939x->mbhc)
  2217. blocking_notifier_call_chain(
  2218. &wcd939x->mbhc->notifier,
  2219. post_off_event,
  2220. &wcd939x->mbhc->wcd_mbhc);
  2221. }
  2222. if (is_dapm && post_dapm_off && wcd939x->mbhc)
  2223. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2224. post_dapm_off,
  2225. &wcd939x->mbhc->wcd_mbhc);
  2226. break;
  2227. };
  2228. dev_dbg(component->dev,
  2229. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2230. __func__, micb_num, wcd939x->micb_ref[micb_index],
  2231. wcd939x->pullup_ref[micb_index]);
  2232. done:
  2233. mutex_unlock(&wcd939x->micb_lock);
  2234. return ret;
  2235. }
  2236. EXPORT_SYMBOL(wcd939x_micbias_control);
  2237. static int wcd939x_get_logical_addr(struct swr_device *swr_dev)
  2238. {
  2239. int ret = 0;
  2240. uint8_t devnum = 0;
  2241. int num_retry = NUM_ATTEMPTS;
  2242. do {
  2243. /* retry after 1ms */
  2244. usleep_range(1000, 1010);
  2245. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2246. } while (ret && --num_retry);
  2247. if (ret)
  2248. dev_err_ratelimited(&swr_dev->dev,
  2249. "%s get devnum %d for dev addr %llx failed\n",
  2250. __func__, devnum, swr_dev->addr);
  2251. swr_dev->dev_num = devnum;
  2252. return 0;
  2253. }
  2254. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2255. struct wcd_mbhc_config *mbhc_cfg)
  2256. {
  2257. if (mbhc_cfg->enable_usbc_analog) {
  2258. if (!(snd_soc_component_read(component, WCD939X_MBHC_MECH)
  2259. & 0x20))
  2260. return true;
  2261. }
  2262. return false;
  2263. }
  2264. int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *component,
  2265. struct notifier_block *nblock,
  2266. bool enable)
  2267. {
  2268. struct wcd939x_priv *wcd939x_priv;
  2269. if(NULL == component) {
  2270. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2271. return -EINVAL;
  2272. }
  2273. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2274. wcd939x_priv->notify_swr_dmic = enable;
  2275. if (enable)
  2276. return blocking_notifier_chain_register(&wcd939x_priv->notifier,
  2277. nblock);
  2278. else
  2279. return blocking_notifier_chain_unregister(
  2280. &wcd939x_priv->notifier, nblock);
  2281. }
  2282. EXPORT_SYMBOL(wcd939x_swr_dmic_register_notifier);
  2283. static int wcd939x_event_notify(struct notifier_block *block,
  2284. unsigned long val,
  2285. void *data)
  2286. {
  2287. u16 event = (val & 0xffff);
  2288. int ret = 0;
  2289. int rx_clk_type;
  2290. struct wcd939x_priv *wcd939x = dev_get_drvdata((struct device *)data);
  2291. struct snd_soc_component *component = wcd939x->component;
  2292. struct wcd_mbhc *mbhc;
  2293. switch (event) {
  2294. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2295. if (test_bit(WCD_ADC1, &wcd939x->status_mask)) {
  2296. snd_soc_component_update_bits(component,
  2297. REG_FIELD_VALUE(TX_CH2, HPF1_INIT, 0x00));
  2298. set_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  2299. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  2300. }
  2301. if (test_bit(WCD_ADC2, &wcd939x->status_mask)) {
  2302. snd_soc_component_update_bits(component,
  2303. REG_FIELD_VALUE(TX_CH2, HPF2_INIT, 0x00));
  2304. set_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  2305. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  2306. }
  2307. if (test_bit(WCD_ADC3, &wcd939x->status_mask)) {
  2308. snd_soc_component_update_bits(component,
  2309. REG_FIELD_VALUE(TX_CH4, HPF3_INIT, 0x00));
  2310. set_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  2311. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  2312. }
  2313. if (test_bit(WCD_ADC4, &wcd939x->status_mask)) {
  2314. snd_soc_component_update_bits(component,
  2315. REG_FIELD_VALUE(TX_CH4, HPF4_INIT, 0x00));
  2316. set_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  2317. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  2318. }
  2319. break;
  2320. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2321. snd_soc_component_update_bits(component,
  2322. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  2323. snd_soc_component_update_bits(component,
  2324. REG_FIELD_VALUE(HPH, HPHR_ENABLE , 0x00));
  2325. snd_soc_component_update_bits(component,
  2326. REG_FIELD_VALUE(EAR, ENABLE, 0x00));
  2327. break;
  2328. case BOLERO_SLV_EVT_SSR_DOWN:
  2329. wcd939x->dev_up = false;
  2330. if(wcd939x->notify_swr_dmic)
  2331. blocking_notifier_call_chain(&wcd939x->notifier,
  2332. WCD939X_EVT_SSR_DOWN,
  2333. NULL);
  2334. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2335. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2336. wcd939x->usbc_hs_status = get_usbc_hs_status(component,
  2337. mbhc->mbhc_cfg);
  2338. wcd939x_mbhc_ssr_down(wcd939x->mbhc, component);
  2339. wcd939x_reset_low(wcd939x->dev);
  2340. break;
  2341. case BOLERO_SLV_EVT_SSR_UP:
  2342. wcd939x_reset(wcd939x->dev);
  2343. /* allow reset to take effect */
  2344. usleep_range(10000, 10010);
  2345. wcd939x_get_logical_addr(wcd939x->tx_swr_dev);
  2346. wcd939x_get_logical_addr(wcd939x->rx_swr_dev);
  2347. wcd939x_init_reg(component);
  2348. regcache_mark_dirty(wcd939x->regmap);
  2349. regcache_sync(wcd939x->regmap);
  2350. /* Initialize MBHC module */
  2351. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2352. ret = wcd939x_mbhc_post_ssr_init(wcd939x->mbhc, component);
  2353. if (ret) {
  2354. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2355. __func__);
  2356. } else {
  2357. wcd939x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2358. }
  2359. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2360. wcd939x->dev_up = true;
  2361. if(wcd939x->notify_swr_dmic)
  2362. blocking_notifier_call_chain(&wcd939x->notifier,
  2363. WCD939X_EVT_SSR_UP,
  2364. NULL);
  2365. if (wcd939x->usbc_hs_status)
  2366. mdelay(500);
  2367. break;
  2368. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2369. snd_soc_component_update_bits(component,
  2370. WCD939X_TOP_CLK_CFG, 0x06,
  2371. ((val >> 0x10) << 0x01));
  2372. rx_clk_type = (val >> 0x10);
  2373. switch(rx_clk_type) {
  2374. case RX_CLK_12P288MHZ:
  2375. wcd939x->rx_clk_config = RX_CLK_12P288MHZ;
  2376. break;
  2377. case RX_CLK_11P2896MHZ:
  2378. wcd939x->rx_clk_config = RX_CLK_11P2896MHZ;
  2379. break;
  2380. default:
  2381. wcd939x->rx_clk_config = RX_CLK_9P6MHZ;
  2382. break;
  2383. }
  2384. dev_dbg(component->dev, "%s: rx clk config %d\n", __func__, wcd939x->rx_clk_config);
  2385. break;
  2386. default:
  2387. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2388. break;
  2389. }
  2390. return 0;
  2391. }
  2392. static int __wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2393. int event)
  2394. {
  2395. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2396. int micb_num;
  2397. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2398. __func__, w->name, event);
  2399. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2400. micb_num = MIC_BIAS_1;
  2401. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2402. micb_num = MIC_BIAS_2;
  2403. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2404. micb_num = MIC_BIAS_3;
  2405. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2406. micb_num = MIC_BIAS_4;
  2407. else
  2408. return -EINVAL;
  2409. switch (event) {
  2410. case SND_SOC_DAPM_PRE_PMU:
  2411. wcd939x_micbias_control(component, micb_num,
  2412. MICB_ENABLE, true);
  2413. break;
  2414. case SND_SOC_DAPM_POST_PMU:
  2415. /* 1 msec delay as per HW requirement */
  2416. usleep_range(1000, 1100);
  2417. break;
  2418. case SND_SOC_DAPM_POST_PMD:
  2419. wcd939x_micbias_control(component, micb_num,
  2420. MICB_DISABLE, true);
  2421. break;
  2422. };
  2423. return 0;
  2424. }
  2425. static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2426. struct snd_kcontrol *kcontrol,
  2427. int event)
  2428. {
  2429. return __wcd939x_codec_enable_micbias(w, event);
  2430. }
  2431. static int __wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2432. int event)
  2433. {
  2434. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2435. int micb_num;
  2436. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2437. __func__, w->name, event);
  2438. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2439. micb_num = MIC_BIAS_1;
  2440. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2441. micb_num = MIC_BIAS_2;
  2442. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2443. micb_num = MIC_BIAS_3;
  2444. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2445. micb_num = MIC_BIAS_4;
  2446. else
  2447. return -EINVAL;
  2448. switch (event) {
  2449. case SND_SOC_DAPM_PRE_PMU:
  2450. wcd939x_micbias_control(component, micb_num,
  2451. MICB_PULLUP_ENABLE, true);
  2452. break;
  2453. case SND_SOC_DAPM_POST_PMU:
  2454. /* 1 msec delay as per HW requirement */
  2455. usleep_range(1000, 1100);
  2456. break;
  2457. case SND_SOC_DAPM_POST_PMD:
  2458. wcd939x_micbias_control(component, micb_num,
  2459. MICB_PULLUP_DISABLE, true);
  2460. break;
  2461. };
  2462. return 0;
  2463. }
  2464. static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2465. struct snd_kcontrol *kcontrol,
  2466. int event)
  2467. {
  2468. return __wcd939x_codec_enable_micbias_pullup(w, event);
  2469. }
  2470. static int wcd939x_wakeup(void *handle, bool enable)
  2471. {
  2472. struct wcd939x_priv *priv;
  2473. int ret = 0;
  2474. if (!handle) {
  2475. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2476. return -EINVAL;
  2477. }
  2478. priv = (struct wcd939x_priv *)handle;
  2479. if (!priv->tx_swr_dev) {
  2480. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2481. return -EINVAL;
  2482. }
  2483. mutex_lock(&priv->wakeup_lock);
  2484. if (enable)
  2485. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2486. else
  2487. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2488. mutex_unlock(&priv->wakeup_lock);
  2489. return ret;
  2490. }
  2491. static int wcd939x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2492. struct snd_kcontrol *kcontrol,
  2493. int event)
  2494. {
  2495. int ret = 0;
  2496. struct snd_soc_component *component =
  2497. snd_soc_dapm_to_component(w->dapm);
  2498. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2499. switch (event) {
  2500. case SND_SOC_DAPM_PRE_PMU:
  2501. wcd939x_wakeup(wcd939x, true);
  2502. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2503. wcd939x_wakeup(wcd939x, false);
  2504. break;
  2505. case SND_SOC_DAPM_POST_PMD:
  2506. wcd939x_wakeup(wcd939x, true);
  2507. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2508. wcd939x_wakeup(wcd939x, false);
  2509. break;
  2510. }
  2511. return ret;
  2512. }
  2513. static int wcd939x_enable_micbias(struct wcd939x_priv *wcd939x,
  2514. int micb_num, int req)
  2515. {
  2516. int micb_index = micb_num - 1;
  2517. u16 micb_reg;
  2518. if (NULL == wcd939x) {
  2519. pr_err_ratelimited("%s: wcd939x private data is NULL\n", __func__);
  2520. return -EINVAL;
  2521. }
  2522. switch (micb_num) {
  2523. case MIC_BIAS_1:
  2524. micb_reg = WCD939X_MICB1;
  2525. break;
  2526. case MIC_BIAS_2:
  2527. micb_reg = WCD939X_MICB2;
  2528. break;
  2529. case MIC_BIAS_3:
  2530. micb_reg = WCD939X_MICB3;
  2531. break;
  2532. case MIC_BIAS_4:
  2533. micb_reg = WCD939X_MICB4;
  2534. break;
  2535. default:
  2536. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2537. return -EINVAL;
  2538. };
  2539. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2540. __func__, req, micb_num, wcd939x->micb_ref[micb_index],
  2541. wcd939x->pullup_ref[micb_index]);
  2542. mutex_lock(&wcd939x->micb_lock);
  2543. switch (req) {
  2544. case MICB_ENABLE:
  2545. wcd939x->micb_ref[micb_index]++;
  2546. if (wcd939x->micb_ref[micb_index] == 1) {
  2547. regmap_update_bits(wcd939x->regmap,
  2548. WCD939X_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2549. regmap_update_bits(wcd939x->regmap,
  2550. WCD939X_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2551. regmap_update_bits(wcd939x->regmap,
  2552. WCD939X_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2553. regmap_update_bits(wcd939x->regmap,
  2554. WCD939X_TEST_CTL_2, 0x01, 0x01);
  2555. regmap_update_bits(wcd939x->regmap,
  2556. WCD939X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2557. regmap_update_bits(wcd939x->regmap,
  2558. WCD939X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2559. regmap_update_bits(wcd939x->regmap,
  2560. WCD939X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2561. regmap_update_bits(wcd939x->regmap,
  2562. micb_reg, 0xC0, 0x40);
  2563. regmap_update_bits(wcd939x->regmap, micb_reg, 0x3F, 0x10);
  2564. }
  2565. break;
  2566. case MICB_PULLUP_ENABLE:
  2567. wcd939x->pullup_ref[micb_index]++;
  2568. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2569. (wcd939x->micb_ref[micb_index] == 0))
  2570. regmap_update_bits(wcd939x->regmap, micb_reg,
  2571. 0xC0, 0x80);
  2572. break;
  2573. case MICB_PULLUP_DISABLE:
  2574. if (wcd939x->pullup_ref[micb_index] > 0)
  2575. wcd939x->pullup_ref[micb_index]--;
  2576. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2577. (wcd939x->micb_ref[micb_index] == 0))
  2578. regmap_update_bits(wcd939x->regmap, micb_reg,
  2579. 0xC0, 0x00);
  2580. break;
  2581. case MICB_DISABLE:
  2582. if (wcd939x->micb_ref[micb_index] > 0)
  2583. wcd939x->micb_ref[micb_index]--;
  2584. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2585. (wcd939x->pullup_ref[micb_index] > 0))
  2586. regmap_update_bits(wcd939x->regmap, micb_reg,
  2587. 0xC0, 0x80);
  2588. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2589. (wcd939x->pullup_ref[micb_index] == 0))
  2590. regmap_update_bits(wcd939x->regmap, micb_reg,
  2591. 0xC0, 0x00);
  2592. break;
  2593. };
  2594. mutex_unlock(&wcd939x->micb_lock);
  2595. return 0;
  2596. }
  2597. int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2598. int event, int micb_num)
  2599. {
  2600. struct wcd939x_priv *wcd939x_priv = NULL;
  2601. int ret = 0;
  2602. int micb_index = micb_num - 1;
  2603. if(NULL == component) {
  2604. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2605. return -EINVAL;
  2606. }
  2607. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2608. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2609. return -EINVAL;
  2610. }
  2611. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2612. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2613. return -EINVAL;
  2614. }
  2615. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2616. if (!wcd939x_priv->dev_up) {
  2617. if ((wcd939x_priv->pullup_ref[micb_index] > 0) &&
  2618. (event == SND_SOC_DAPM_POST_PMD)) {
  2619. wcd939x_priv->pullup_ref[micb_index]--;
  2620. ret = -ENODEV;
  2621. goto done;
  2622. }
  2623. }
  2624. switch (event) {
  2625. case SND_SOC_DAPM_PRE_PMU:
  2626. wcd939x_wakeup(wcd939x_priv, true);
  2627. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_ENABLE);
  2628. wcd939x_wakeup(wcd939x_priv, false);
  2629. break;
  2630. case SND_SOC_DAPM_POST_PMD:
  2631. wcd939x_wakeup(wcd939x_priv, true);
  2632. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_DISABLE);
  2633. wcd939x_wakeup(wcd939x_priv, false);
  2634. break;
  2635. }
  2636. done:
  2637. return ret;
  2638. }
  2639. EXPORT_SYMBOL(wcd939x_codec_force_enable_micbias_v2);
  2640. static inline int wcd939x_tx_path_get(const char *wname,
  2641. unsigned int *path_num)
  2642. {
  2643. int ret = 0;
  2644. char *widget_name = NULL;
  2645. char *w_name = NULL;
  2646. char *path_num_char = NULL;
  2647. char *path_name = NULL;
  2648. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2649. if (!widget_name)
  2650. return -EINVAL;
  2651. w_name = widget_name;
  2652. path_name = strsep(&widget_name, " ");
  2653. if (!path_name) {
  2654. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2655. __func__, widget_name);
  2656. ret = -EINVAL;
  2657. goto err;
  2658. }
  2659. path_num_char = strpbrk(path_name, "0123");
  2660. if (!path_num_char) {
  2661. pr_err_ratelimited("%s: tx path index not found\n",
  2662. __func__);
  2663. ret = -EINVAL;
  2664. goto err;
  2665. }
  2666. ret = kstrtouint(path_num_char, 10, path_num);
  2667. if (ret < 0)
  2668. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2669. __func__, w_name);
  2670. err:
  2671. kfree(w_name);
  2672. return ret;
  2673. }
  2674. static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2675. struct snd_ctl_elem_value *ucontrol)
  2676. {
  2677. struct snd_soc_component *component =
  2678. snd_soc_kcontrol_component(kcontrol);
  2679. struct wcd939x_priv *wcd939x = NULL;
  2680. int ret = 0;
  2681. unsigned int path = 0;
  2682. if (!component)
  2683. return -EINVAL;
  2684. wcd939x = snd_soc_component_get_drvdata(component);
  2685. if (!wcd939x)
  2686. return -EINVAL;
  2687. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2688. if (ret < 0)
  2689. return ret;
  2690. ucontrol->value.integer.value[0] = wcd939x->tx_mode[path];
  2691. return 0;
  2692. }
  2693. static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2694. struct snd_ctl_elem_value *ucontrol)
  2695. {
  2696. struct snd_soc_component *component =
  2697. snd_soc_kcontrol_component(kcontrol);
  2698. struct wcd939x_priv *wcd939x = NULL;
  2699. u32 mode_val;
  2700. unsigned int path = 0;
  2701. int ret = 0;
  2702. if (!component)
  2703. return -EINVAL;
  2704. wcd939x = snd_soc_component_get_drvdata(component);
  2705. if (!wcd939x)
  2706. return -EINVAL;
  2707. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2708. if (ret)
  2709. return ret;
  2710. mode_val = ucontrol->value.enumerated.item[0];
  2711. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2712. wcd939x->tx_mode[path] = mode_val;
  2713. return 0;
  2714. }
  2715. static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2716. struct snd_ctl_elem_value *ucontrol)
  2717. {
  2718. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2719. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2720. ucontrol->value.integer.value[0] = wcd939x->hph_mode;
  2721. return 0;
  2722. }
  2723. static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2724. struct snd_ctl_elem_value *ucontrol)
  2725. {
  2726. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2727. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2728. u32 mode_val;
  2729. mode_val = ucontrol->value.enumerated.item[0];
  2730. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2731. if (wcd939x->variant == WCD9390) {
  2732. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2733. dev_info_ratelimited(component->dev,
  2734. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2735. __func__);
  2736. mode_val = CLS_H_ULP;
  2737. }
  2738. }
  2739. if (mode_val == CLS_H_NORMAL) {
  2740. dev_info_ratelimited(component->dev,
  2741. "%s:Invalid HPH Mode, default to class_AB\n",
  2742. __func__);
  2743. mode_val = CLS_H_ULP;
  2744. }
  2745. wcd939x->hph_mode = mode_val;
  2746. return 0;
  2747. }
  2748. static int wcd939x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2749. struct snd_ctl_elem_value *ucontrol)
  2750. {
  2751. u8 ear_pa_gain = 0;
  2752. struct snd_soc_component *component =
  2753. snd_soc_kcontrol_component(kcontrol);
  2754. ear_pa_gain = snd_soc_component_read(component,
  2755. WCD939X_EAR_COMPANDER_CTL);
  2756. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2757. ucontrol->value.integer.value[0] = ear_pa_gain;
  2758. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2759. ear_pa_gain);
  2760. return 0;
  2761. }
  2762. static int wcd939x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2763. struct snd_ctl_elem_value *ucontrol)
  2764. {
  2765. u8 ear_pa_gain = 0;
  2766. struct snd_soc_component *component =
  2767. snd_soc_kcontrol_component(kcontrol);
  2768. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2769. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2770. __func__, ucontrol->value.integer.value[0]);
  2771. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2772. if (!wcd939x->comp1_enable) {
  2773. snd_soc_component_update_bits(component,
  2774. WCD939X_EAR_COMPANDER_CTL,
  2775. 0x7C, ear_pa_gain);
  2776. }
  2777. return 0;
  2778. }
  2779. /* wcd939x_codec_get_dev_num - returns swr device number
  2780. * @component: Codec instance
  2781. *
  2782. * Return: swr device number on success or negative error
  2783. * code on failure.
  2784. */
  2785. int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
  2786. {
  2787. struct wcd939x_priv *wcd939x;
  2788. if (!component)
  2789. return -EINVAL;
  2790. wcd939x = snd_soc_component_get_drvdata(component);
  2791. if (!wcd939x || !wcd939x->rx_swr_dev) {
  2792. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2793. return -EINVAL;
  2794. }
  2795. return wcd939x->rx_swr_dev->dev_num;
  2796. }
  2797. EXPORT_SYMBOL(wcd939x_codec_get_dev_num);
  2798. static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
  2799. struct snd_ctl_elem_value *ucontrol)
  2800. {
  2801. struct snd_soc_component *component =
  2802. snd_soc_kcontrol_component(kcontrol);
  2803. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2804. bool hphr;
  2805. struct soc_multi_mixer_control *mc;
  2806. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2807. hphr = mc->shift;
  2808. ucontrol->value.integer.value[0] = hphr ? wcd939x->comp2_enable :
  2809. wcd939x->comp1_enable;
  2810. return 0;
  2811. }
  2812. static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
  2813. struct snd_ctl_elem_value *ucontrol)
  2814. {
  2815. struct snd_soc_component *component =
  2816. snd_soc_kcontrol_component(kcontrol);
  2817. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2818. int value = ucontrol->value.integer.value[0];
  2819. bool hphr;
  2820. struct soc_multi_mixer_control *mc;
  2821. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2822. hphr = mc->shift;
  2823. if (hphr)
  2824. wcd939x->comp2_enable = value;
  2825. else
  2826. wcd939x->comp1_enable = value;
  2827. return 0;
  2828. }
  2829. static int wcd939x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2830. struct snd_kcontrol *kcontrol,
  2831. int event)
  2832. {
  2833. struct snd_soc_component *component =
  2834. snd_soc_dapm_to_component(w->dapm);
  2835. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2836. struct wcd939x_pdata *pdata = NULL;
  2837. int ret = 0;
  2838. pdata = dev_get_platdata(wcd939x->dev);
  2839. if (!pdata) {
  2840. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2841. return -EINVAL;
  2842. }
  2843. if (!msm_cdc_is_ondemand_supply(wcd939x->dev,
  2844. wcd939x->supplies,
  2845. pdata->regulator,
  2846. pdata->num_supplies,
  2847. "cdc-vdd-buck"))
  2848. return 0;
  2849. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2850. w->name, event);
  2851. switch (event) {
  2852. case SND_SOC_DAPM_PRE_PMU:
  2853. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  2854. dev_dbg(component->dev,
  2855. "%s: buck already in enabled state\n",
  2856. __func__);
  2857. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2858. return 0;
  2859. }
  2860. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  2861. wcd939x->supplies,
  2862. pdata->regulator,
  2863. pdata->num_supplies,
  2864. "cdc-vdd-buck");
  2865. if (ret == -EINVAL) {
  2866. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2867. __func__);
  2868. return ret;
  2869. }
  2870. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2871. /*
  2872. * 200us sleep is required after LDO is enabled as per
  2873. * HW requirement
  2874. */
  2875. usleep_range(200, 250);
  2876. break;
  2877. case SND_SOC_DAPM_POST_PMD:
  2878. set_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2879. break;
  2880. }
  2881. return 0;
  2882. }
  2883. static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
  2884. struct snd_ctl_elem_value *ucontrol)
  2885. {
  2886. struct snd_soc_component *component =
  2887. snd_soc_kcontrol_component(kcontrol);
  2888. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2889. ucontrol->value.integer.value[0] = wcd939x->ldoh;
  2890. return 0;
  2891. }
  2892. static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
  2893. struct snd_ctl_elem_value *ucontrol)
  2894. {
  2895. struct snd_soc_component *component =
  2896. snd_soc_kcontrol_component(kcontrol);
  2897. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2898. wcd939x->ldoh = ucontrol->value.integer.value[0];
  2899. return 0;
  2900. }
  2901. const char * const tx_master_ch_text[] = {
  2902. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  2903. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  2904. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  2905. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  2906. };
  2907. const struct soc_enum tx_master_ch_enum =
  2908. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2909. tx_master_ch_text);
  2910. static void wcd939x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2911. {
  2912. u8 ch_type = 0;
  2913. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2914. ch_type = ADC1;
  2915. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2916. ch_type = ADC2;
  2917. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2918. ch_type = ADC3;
  2919. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2920. ch_type = ADC4;
  2921. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2922. ch_type = DMIC0;
  2923. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2924. ch_type = DMIC1;
  2925. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2926. ch_type = MBHC;
  2927. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2928. ch_type = DMIC2;
  2929. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2930. ch_type = DMIC3;
  2931. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2932. ch_type = DMIC4;
  2933. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2934. ch_type = DMIC5;
  2935. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2936. ch_type = DMIC6;
  2937. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2938. ch_type = DMIC7;
  2939. else
  2940. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  2941. if (ch_type)
  2942. *ch_idx = wcd939x_slave_get_slave_ch_val(ch_type);
  2943. else
  2944. *ch_idx = -EINVAL;
  2945. }
  2946. static int wcd939x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2947. struct snd_ctl_elem_value *ucontrol)
  2948. {
  2949. struct snd_soc_component *component =
  2950. snd_soc_kcontrol_component(kcontrol);
  2951. struct wcd939x_priv *wcd939x = NULL;
  2952. int slave_ch_idx = -EINVAL;
  2953. if (component == NULL)
  2954. return -EINVAL;
  2955. wcd939x = snd_soc_component_get_drvdata(component);
  2956. if (wcd939x == NULL)
  2957. return -EINVAL;
  2958. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2959. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  2960. return -EINVAL;
  2961. ucontrol->value.integer.value[0] = wcd939x_slave_get_master_ch_val(
  2962. wcd939x->tx_master_ch_map[slave_ch_idx]);
  2963. return 0;
  2964. }
  2965. static int wcd939x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2966. struct snd_ctl_elem_value *ucontrol)
  2967. {
  2968. struct snd_soc_component *component =
  2969. snd_soc_kcontrol_component(kcontrol);
  2970. struct wcd939x_priv *wcd939x = NULL;
  2971. int slave_ch_idx = -EINVAL, idx = 0;
  2972. if (component == NULL)
  2973. return -EINVAL;
  2974. wcd939x = snd_soc_component_get_drvdata(component);
  2975. if (wcd939x == NULL)
  2976. return -EINVAL;
  2977. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2978. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  2979. return -EINVAL;
  2980. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2981. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2982. __func__, ucontrol->value.enumerated.item[0]);
  2983. idx = ucontrol->value.enumerated.item[0];
  2984. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  2985. return -EINVAL;
  2986. wcd939x->tx_master_ch_map[slave_ch_idx] = wcd939x_slave_get_master_ch(idx);
  2987. return 0;
  2988. }
  2989. static int wcd939x_bcs_get(struct snd_kcontrol *kcontrol,
  2990. struct snd_ctl_elem_value *ucontrol)
  2991. {
  2992. struct snd_soc_component *component =
  2993. snd_soc_kcontrol_component(kcontrol);
  2994. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2995. ucontrol->value.integer.value[0] = wcd939x->bcs_dis;
  2996. return 0;
  2997. }
  2998. static int wcd939x_bcs_put(struct snd_kcontrol *kcontrol,
  2999. struct snd_ctl_elem_value *ucontrol)
  3000. {
  3001. struct snd_soc_component *component =
  3002. snd_soc_kcontrol_component(kcontrol);
  3003. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3004. wcd939x->bcs_dis = ucontrol->value.integer.value[0];
  3005. return 0;
  3006. }
  3007. static const char * const tx_mode_mux_text_wcd9390[] = {
  3008. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3009. };
  3010. static const struct soc_enum tx_mode_mux_enum_wcd9390 =
  3011. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9390),
  3012. tx_mode_mux_text_wcd9390);
  3013. static const char * const tx_mode_mux_text[] = {
  3014. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3015. "ADC_ULP1", "ADC_ULP2",
  3016. };
  3017. static const struct soc_enum tx_mode_mux_enum =
  3018. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  3019. tx_mode_mux_text);
  3020. static const char * const rx_hph_mode_mux_text_wcd9390[] = {
  3021. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  3022. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  3023. "CLS_AB_LOHIFI",
  3024. };
  3025. static const char * const wcd939x_ear_pa_gain_text[] = {
  3026. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  3027. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  3028. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  3029. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  3030. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  3031. };
  3032. static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
  3033. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
  3034. rx_hph_mode_mux_text_wcd9390);
  3035. static SOC_ENUM_SINGLE_EXT_DECL(wcd939x_ear_pa_gain_enum,
  3036. wcd939x_ear_pa_gain_text);
  3037. static const char * const rx_hph_mode_mux_text[] = {
  3038. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  3039. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  3040. };
  3041. static const struct soc_enum rx_hph_mode_mux_enum =
  3042. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  3043. rx_hph_mode_mux_text);
  3044. static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
  3045. SOC_ENUM_EXT("EAR PA GAIN", wcd939x_ear_pa_gain_enum,
  3046. wcd939x_ear_pa_gain_get, wcd939x_ear_pa_gain_put),
  3047. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
  3048. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3049. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9390,
  3050. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3051. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9390,
  3052. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3053. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9390,
  3054. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3055. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9390,
  3056. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3057. };
  3058. static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
  3059. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  3060. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3061. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  3062. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3063. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  3064. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3065. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  3066. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3067. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  3068. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3069. };
  3070. static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
  3071. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  3072. wcd939x_get_compander, wcd939x_set_compander),
  3073. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  3074. wcd939x_get_compander, wcd939x_set_compander),
  3075. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  3076. wcd939x_ldoh_get, wcd939x_ldoh_put),
  3077. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  3078. wcd939x_bcs_get, wcd939x_bcs_put),
  3079. SOC_SINGLE_TLV("HPHL Volume", WCD939X_L_EN, 0, 20, 1, line_gain),
  3080. SOC_SINGLE_TLV("HPHR Volume", WCD939X_R_EN, 0, 20, 1, line_gain),
  3081. SOC_SINGLE_TLV("ADC1 Volume", WCD939X_TX_CH1, 0, 20, 0,
  3082. analog_gain),
  3083. SOC_SINGLE_TLV("ADC2 Volume", WCD939X_TX_CH2, 0, 20, 0,
  3084. analog_gain),
  3085. SOC_SINGLE_TLV("ADC3 Volume", WCD939X_TX_CH3, 0, 20, 0,
  3086. analog_gain),
  3087. SOC_SINGLE_TLV("ADC4 Volume", WCD939X_TX_CH4, 0, 20, 0,
  3088. analog_gain),
  3089. SOC_SINGLE_EXT("HPHL Compander", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3090. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3091. SOC_SINGLE_EXT("HPHR Compander", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3092. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3093. SOC_SINGLE_EXT("HPHL XTALK", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3094. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3095. SOC_SINGLE_EXT("HPHR XTALK", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3096. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3097. SOC_SINGLE_EXT("HPH PCM Enable", SND_SOC_NOPM, 0, 1, 0,
  3098. wcd939x_hph_pcm_enable_get, wcd939x_hph_pcm_enable_put),
  3099. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  3100. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3101. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  3102. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3103. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  3104. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3105. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  3106. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3107. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  3108. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3109. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  3110. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3111. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  3112. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3113. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  3114. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3115. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  3116. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3117. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  3118. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3119. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  3120. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3121. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  3122. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3123. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  3124. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3125. };
  3126. static const struct snd_kcontrol_new adc1_switch[] = {
  3127. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3128. };
  3129. static const struct snd_kcontrol_new adc2_switch[] = {
  3130. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3131. };
  3132. static const struct snd_kcontrol_new adc3_switch[] = {
  3133. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3134. };
  3135. static const struct snd_kcontrol_new adc4_switch[] = {
  3136. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3137. };
  3138. static const struct snd_kcontrol_new amic1_switch[] = {
  3139. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3140. };
  3141. static const struct snd_kcontrol_new amic2_switch[] = {
  3142. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3143. };
  3144. static const struct snd_kcontrol_new amic3_switch[] = {
  3145. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3146. };
  3147. static const struct snd_kcontrol_new amic4_switch[] = {
  3148. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3149. };
  3150. static const struct snd_kcontrol_new amic5_switch[] = {
  3151. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3152. };
  3153. static const struct snd_kcontrol_new va_amic1_switch[] = {
  3154. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3155. };
  3156. static const struct snd_kcontrol_new va_amic2_switch[] = {
  3157. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3158. };
  3159. static const struct snd_kcontrol_new va_amic3_switch[] = {
  3160. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3161. };
  3162. static const struct snd_kcontrol_new va_amic4_switch[] = {
  3163. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3164. };
  3165. static const struct snd_kcontrol_new va_amic5_switch[] = {
  3166. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3167. };
  3168. static const struct snd_kcontrol_new dmic1_switch[] = {
  3169. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3170. };
  3171. static const struct snd_kcontrol_new dmic2_switch[] = {
  3172. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3173. };
  3174. static const struct snd_kcontrol_new dmic3_switch[] = {
  3175. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3176. };
  3177. static const struct snd_kcontrol_new dmic4_switch[] = {
  3178. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3179. };
  3180. static const struct snd_kcontrol_new dmic5_switch[] = {
  3181. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3182. };
  3183. static const struct snd_kcontrol_new dmic6_switch[] = {
  3184. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3185. };
  3186. static const struct snd_kcontrol_new dmic7_switch[] = {
  3187. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3188. };
  3189. static const struct snd_kcontrol_new dmic8_switch[] = {
  3190. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3191. };
  3192. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  3193. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3194. };
  3195. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  3196. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3197. };
  3198. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  3199. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3200. };
  3201. static const char * const adc1_mux_text[] = {
  3202. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
  3203. };
  3204. static const struct soc_enum adc1_enum =
  3205. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT,
  3206. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  3207. static const struct snd_kcontrol_new tx_adc1_mux =
  3208. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  3209. static const char * const adc2_mux_text[] = {
  3210. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
  3211. };
  3212. static const struct soc_enum adc2_enum =
  3213. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT,
  3214. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  3215. static const struct snd_kcontrol_new tx_adc2_mux =
  3216. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  3217. static const char * const adc3_mux_text[] = {
  3218. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
  3219. };
  3220. static const struct soc_enum adc3_enum =
  3221. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT,
  3222. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  3223. static const struct snd_kcontrol_new tx_adc3_mux =
  3224. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  3225. static const char * const adc4_mux_text[] = {
  3226. "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
  3227. };
  3228. static const struct soc_enum adc4_enum =
  3229. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT,
  3230. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  3231. static const struct snd_kcontrol_new tx_adc4_mux =
  3232. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  3233. static const char * const rdac3_mux_text[] = {
  3234. "RX1", "RX3"
  3235. };
  3236. static const struct soc_enum rdac3_enum =
  3237. SOC_ENUM_SINGLE(WCD939X_CDC_EAR_PATH_CTL, 0,
  3238. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  3239. static const struct snd_kcontrol_new rx_rdac3_mux =
  3240. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  3241. static const char * const rx1_mux_text[] = {
  3242. "ZERO", "RX1 MUX"
  3243. };
  3244. static const struct soc_enum rx1_enum =
  3245. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx1_mux_text);
  3246. static const struct snd_kcontrol_new rx1_mux =
  3247. SOC_DAPM_ENUM("RX1 MUX Mux", rx1_enum);
  3248. static const char * const rx2_mux_text[] = {
  3249. "ZERO", "RX2 MUX"
  3250. };
  3251. static const struct soc_enum rx2_enum =
  3252. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx2_mux_text);
  3253. static const struct snd_kcontrol_new rx2_mux =
  3254. SOC_DAPM_ENUM("RX2 MUX Mux", rx2_enum);
  3255. static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
  3256. /*input widgets*/
  3257. SND_SOC_DAPM_INPUT("AMIC1"),
  3258. SND_SOC_DAPM_INPUT("AMIC2"),
  3259. SND_SOC_DAPM_INPUT("AMIC3"),
  3260. SND_SOC_DAPM_INPUT("AMIC4"),
  3261. SND_SOC_DAPM_INPUT("AMIC5"),
  3262. SND_SOC_DAPM_INPUT("VA AMIC1"),
  3263. SND_SOC_DAPM_INPUT("VA AMIC2"),
  3264. SND_SOC_DAPM_INPUT("VA AMIC3"),
  3265. SND_SOC_DAPM_INPUT("VA AMIC4"),
  3266. SND_SOC_DAPM_INPUT("VA AMIC5"),
  3267. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3268. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3269. SND_SOC_DAPM_INPUT("IN3_EAR"),
  3270. /*
  3271. * These dummy widgets are null connected to WCD939x dapm input and
  3272. * output widgets which are not actual path endpoints. This ensures
  3273. * dapm doesnt set these dapm input and output widgets as endpoints.
  3274. */
  3275. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  3276. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  3277. /*tx widgets*/
  3278. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  3279. wcd939x_codec_enable_adc,
  3280. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3281. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  3282. wcd939x_codec_enable_adc,
  3283. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3284. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  3285. wcd939x_codec_enable_adc,
  3286. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3287. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3288. wcd939x_codec_enable_adc,
  3289. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3290. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3291. wcd939x_codec_enable_dmic,
  3292. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3293. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3294. wcd939x_codec_enable_dmic,
  3295. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3296. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3297. wcd939x_codec_enable_dmic,
  3298. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3299. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3300. wcd939x_codec_enable_dmic,
  3301. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3302. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3303. wcd939x_codec_enable_dmic,
  3304. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3305. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3306. wcd939x_codec_enable_dmic,
  3307. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3308. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3309. wcd939x_codec_enable_dmic,
  3310. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3311. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3312. wcd939x_codec_enable_dmic,
  3313. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3314. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3315. NULL, 0, wcd939x_enable_req,
  3316. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3317. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3318. NULL, 0, wcd939x_enable_req,
  3319. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3320. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3321. NULL, 0, wcd939x_enable_req,
  3322. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3323. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3324. NULL, 0, wcd939x_enable_req,
  3325. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3326. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3327. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3328. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3329. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3330. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3331. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3332. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3333. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3334. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3335. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3336. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3337. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3338. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3339. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3340. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3341. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3342. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3343. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3344. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3345. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3346. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3347. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3348. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3349. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3350. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3351. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3352. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3353. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3354. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3355. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3356. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3357. &tx_adc1_mux),
  3358. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3359. &tx_adc2_mux),
  3360. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3361. &tx_adc3_mux),
  3362. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3363. &tx_adc4_mux),
  3364. /*tx mixers*/
  3365. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3366. adc1_switch, ARRAY_SIZE(adc1_switch),
  3367. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3368. SND_SOC_DAPM_POST_PMD),
  3369. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3370. adc2_switch, ARRAY_SIZE(adc2_switch),
  3371. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3372. SND_SOC_DAPM_POST_PMD),
  3373. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3374. ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
  3375. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3376. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3377. ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
  3378. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3379. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3380. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3381. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3382. SND_SOC_DAPM_POST_PMD),
  3383. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3384. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3385. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3386. SND_SOC_DAPM_POST_PMD),
  3387. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3388. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3389. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3390. SND_SOC_DAPM_POST_PMD),
  3391. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3392. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3393. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3394. SND_SOC_DAPM_POST_PMD),
  3395. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3396. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3397. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3398. SND_SOC_DAPM_POST_PMD),
  3399. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3400. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3401. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3402. SND_SOC_DAPM_POST_PMD),
  3403. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3404. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3405. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3406. SND_SOC_DAPM_POST_PMD),
  3407. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3408. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3409. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3410. SND_SOC_DAPM_POST_PMD),
  3411. /* micbias widgets*/
  3412. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3413. wcd939x_codec_enable_micbias,
  3414. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3415. SND_SOC_DAPM_POST_PMD),
  3416. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3417. wcd939x_codec_enable_micbias,
  3418. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3419. SND_SOC_DAPM_POST_PMD),
  3420. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3421. wcd939x_codec_enable_micbias,
  3422. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3423. SND_SOC_DAPM_POST_PMD),
  3424. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3425. wcd939x_codec_enable_micbias,
  3426. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3427. SND_SOC_DAPM_POST_PMD),
  3428. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3429. wcd939x_codec_force_enable_micbias,
  3430. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3431. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3432. wcd939x_codec_force_enable_micbias,
  3433. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3434. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3435. wcd939x_codec_force_enable_micbias,
  3436. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3437. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3438. wcd939x_codec_force_enable_micbias,
  3439. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3440. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3441. wcd939x_codec_enable_vdd_buck,
  3442. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3443. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3444. wcd939x_enable_clsh,
  3445. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3446. /*rx widgets*/
  3447. SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_EAR, 7, 0, NULL, 0,
  3448. wcd939x_codec_enable_ear_pa,
  3449. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3450. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3451. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_HPH, 7, 0, NULL, 0,
  3452. wcd939x_codec_enable_hphl_pa,
  3453. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3454. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3455. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_HPH, 6, 0, NULL, 0,
  3456. wcd939x_codec_enable_hphr_pa,
  3457. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3458. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3459. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3460. wcd939x_codec_hphl_dac_event,
  3461. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3462. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3463. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3464. wcd939x_codec_hphr_dac_event,
  3465. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3466. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3467. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3468. wcd939x_codec_ear_dac_event,
  3469. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3470. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3471. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3472. SND_SOC_DAPM_MUX_E("RX1 MUX", SND_SOC_NOPM, WCD_RX1, 0, &rx1_mux,
  3473. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3474. | SND_SOC_DAPM_POST_PMD),
  3475. SND_SOC_DAPM_MUX_E("RX2 MUX", SND_SOC_NOPM, WCD_RX2, 0, &rx2_mux,
  3476. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3477. | SND_SOC_DAPM_POST_PMD),
  3478. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3479. wcd939x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3480. SND_SOC_DAPM_POST_PMD),
  3481. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3482. wcd939x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3483. SND_SOC_DAPM_POST_PMD),
  3484. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3485. wcd939x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3486. SND_SOC_DAPM_POST_PMD),
  3487. /* rx mixer widgets*/
  3488. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3489. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3490. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3491. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3492. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3493. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3494. /*output widgets tx*/
  3495. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3496. /*output widgets rx*/
  3497. SND_SOC_DAPM_OUTPUT("EAR"),
  3498. SND_SOC_DAPM_OUTPUT("HPHL"),
  3499. SND_SOC_DAPM_OUTPUT("HPHR"),
  3500. /* micbias pull up widgets*/
  3501. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3502. wcd939x_codec_enable_micbias_pullup,
  3503. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3504. SND_SOC_DAPM_POST_PMD),
  3505. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3506. wcd939x_codec_enable_micbias_pullup,
  3507. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3508. SND_SOC_DAPM_POST_PMD),
  3509. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3510. wcd939x_codec_enable_micbias_pullup,
  3511. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3512. SND_SOC_DAPM_POST_PMD),
  3513. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3514. wcd939x_codec_enable_micbias_pullup,
  3515. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3516. SND_SOC_DAPM_POST_PMD),
  3517. };
  3518. static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
  3519. /*ADC-1 (channel-1)*/
  3520. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3521. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3522. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3523. {"ADC1 REQ", NULL, "ADC1"},
  3524. {"ADC1", NULL, "ADC1 MUX"},
  3525. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3526. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3527. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3528. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3529. {"ADC1 MUX", "CH1_AMIC5", "AMIC5_MIXER"},
  3530. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3531. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3532. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3533. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3534. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3535. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3536. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3537. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3538. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3539. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3540. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3541. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3542. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3543. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3544. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3545. /*ADC-2 (channel-2)*/
  3546. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3547. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3548. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3549. {"ADC2 REQ", NULL, "ADC2"},
  3550. {"ADC2", NULL, "ADC2 MUX"},
  3551. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3552. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3553. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3554. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3555. {"ADC2 MUX", "CH2_AMIC5", "AMIC5_MIXER"},
  3556. /*ADC-3 (channel-3)*/
  3557. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3558. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3559. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3560. {"ADC3 REQ", NULL, "ADC3"},
  3561. {"ADC3", NULL, "ADC3 MUX"},
  3562. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3563. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3564. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3565. {"ADC3 MUX", "CH3_AMIC5", "AMIC5_MIXER"},
  3566. /*ADC-4 (channel-4)*/
  3567. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3568. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3569. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3570. {"ADC4 REQ", NULL, "ADC4"},
  3571. {"ADC4", NULL, "ADC4 MUX"},
  3572. {"ADC4 MUX", "CH4_AMIC1", "AMIC1_MIXER"},
  3573. {"ADC4 MUX", "CH4_AMIC3", "AMIC3_MIXER"},
  3574. {"ADC4 MUX", "CH4_AMIC4", "AMIC4_MIXER"},
  3575. {"ADC4 MUX", "CH4_AMIC5", "AMIC5_MIXER"},
  3576. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3577. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3578. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3579. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3580. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3581. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3582. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3583. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3584. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3585. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3586. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3587. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3588. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3589. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3590. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3591. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3592. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3593. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3594. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3595. {"RX1 MUX", NULL, "IN1_HPHL"},
  3596. {"RX1", NULL, "RX1 MUX"},
  3597. {"RDAC1", NULL, "RX1"},
  3598. {"HPHL_RDAC", "Switch", "RDAC1"},
  3599. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3600. {"HPHL", NULL, "HPHL PGA"},
  3601. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3602. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3603. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3604. {"RX2 MUX", NULL, "IN2_HPHR"},
  3605. {"RX2", NULL, "RX2 MUX"},
  3606. {"RDAC2", NULL, "RX2"},
  3607. {"HPHR_RDAC", "Switch", "RDAC2"},
  3608. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3609. {"HPHR", NULL, "HPHR PGA"},
  3610. {"IN3_EAR", NULL, "WCD_RX_DUMMY"},
  3611. {"IN3_EAR", NULL, "VDD_BUCK"},
  3612. {"IN3_EAR", NULL, "CLS_H_PORT"},
  3613. {"RX3", NULL, "IN3_EAR"},
  3614. {"RDAC3_MUX", "RX3", "RX3"},
  3615. {"RDAC3_MUX", "RX1", "RX1"},
  3616. {"RDAC3", NULL, "RDAC3_MUX"},
  3617. {"EAR_RDAC", "Switch", "RDAC3"},
  3618. {"EAR PGA", NULL, "EAR_RDAC"},
  3619. {"EAR", NULL, "EAR PGA"},
  3620. };
  3621. static ssize_t wcd939x_version_read(struct snd_info_entry *entry,
  3622. void *file_private_data,
  3623. struct file *file,
  3624. char __user *buf, size_t count,
  3625. loff_t pos)
  3626. {
  3627. struct wcd939x_priv *priv;
  3628. char buffer[WCD939X_VERSION_ENTRY_SIZE];
  3629. int len = 0;
  3630. priv = (struct wcd939x_priv *) entry->private_data;
  3631. if (!priv) {
  3632. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3633. return -EINVAL;
  3634. }
  3635. switch (priv->version) {
  3636. case WCD939X_VERSION_1_0:
  3637. len = snprintf(buffer, sizeof(buffer), "WCD939X_1_0\n");
  3638. break;
  3639. default:
  3640. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3641. }
  3642. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3643. }
  3644. static struct snd_info_entry_ops wcd939x_info_ops = {
  3645. .read = wcd939x_version_read,
  3646. };
  3647. static ssize_t wcd939x_variant_read(struct snd_info_entry *entry,
  3648. void *file_private_data,
  3649. struct file *file,
  3650. char __user *buf, size_t count,
  3651. loff_t pos)
  3652. {
  3653. struct wcd939x_priv *priv;
  3654. char buffer[WCD939X_VARIANT_ENTRY_SIZE];
  3655. int len = 0;
  3656. priv = (struct wcd939x_priv *) entry->private_data;
  3657. if (!priv) {
  3658. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3659. return -EINVAL;
  3660. }
  3661. switch (priv->variant) {
  3662. case WCD9390:
  3663. len = snprintf(buffer, sizeof(buffer), "WCD9390\n");
  3664. break;
  3665. case WCD9395:
  3666. len = snprintf(buffer, sizeof(buffer), "WCD9395\n");
  3667. break;
  3668. default:
  3669. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3670. }
  3671. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3672. }
  3673. static struct snd_info_entry_ops wcd939x_variant_ops = {
  3674. .read = wcd939x_variant_read,
  3675. };
  3676. /*
  3677. * wcd939x_get_codec_variant
  3678. * @component: component instance
  3679. *
  3680. * Return: codec variant or -EINVAL in error.
  3681. */
  3682. int wcd939x_get_codec_variant(struct snd_soc_component *component)
  3683. {
  3684. struct wcd939x_priv *priv = NULL;
  3685. if (!component)
  3686. return -EINVAL;
  3687. priv = snd_soc_component_get_drvdata(component);
  3688. if (!priv) {
  3689. dev_err(component->dev,
  3690. "%s:wcd939x not probed\n", __func__);
  3691. return 0;
  3692. }
  3693. return priv->variant;
  3694. }
  3695. EXPORT_SYMBOL(wcd939x_get_codec_variant);
  3696. /*
  3697. * wcd939x_info_create_codec_entry - creates wcd939x module
  3698. * @codec_root: The parent directory
  3699. * @component: component instance
  3700. *
  3701. * Creates wcd939x module, variant and version entry under the given
  3702. * parent directory.
  3703. *
  3704. * Return: 0 on success or negative error code on failure.
  3705. */
  3706. int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3707. struct snd_soc_component *component)
  3708. {
  3709. struct snd_info_entry *version_entry;
  3710. struct snd_info_entry *variant_entry;
  3711. struct wcd939x_priv *priv;
  3712. struct snd_soc_card *card;
  3713. if (!codec_root || !component)
  3714. return -EINVAL;
  3715. priv = snd_soc_component_get_drvdata(component);
  3716. if (priv->entry) {
  3717. dev_dbg(priv->dev,
  3718. "%s:wcd939x module already created\n", __func__);
  3719. return 0;
  3720. }
  3721. card = component->card;
  3722. priv->entry = snd_info_create_module_entry(codec_root->module,
  3723. "wcd939x", codec_root);
  3724. if (!priv->entry) {
  3725. dev_dbg(component->dev, "%s: failed to create wcd939x entry\n",
  3726. __func__);
  3727. return -ENOMEM;
  3728. }
  3729. priv->entry->mode = S_IFDIR | 0555;
  3730. if (snd_info_register(priv->entry) < 0) {
  3731. snd_info_free_entry(priv->entry);
  3732. return -ENOMEM;
  3733. }
  3734. version_entry = snd_info_create_card_entry(card->snd_card,
  3735. "version",
  3736. priv->entry);
  3737. if (!version_entry) {
  3738. dev_dbg(component->dev, "%s: failed to create wcd939x version entry\n",
  3739. __func__);
  3740. snd_info_free_entry(priv->entry);
  3741. return -ENOMEM;
  3742. }
  3743. version_entry->private_data = priv;
  3744. version_entry->size = WCD939X_VERSION_ENTRY_SIZE;
  3745. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3746. version_entry->c.ops = &wcd939x_info_ops;
  3747. if (snd_info_register(version_entry) < 0) {
  3748. snd_info_free_entry(version_entry);
  3749. snd_info_free_entry(priv->entry);
  3750. return -ENOMEM;
  3751. }
  3752. priv->version_entry = version_entry;
  3753. variant_entry = snd_info_create_card_entry(card->snd_card,
  3754. "variant",
  3755. priv->entry);
  3756. if (!variant_entry) {
  3757. dev_dbg(component->dev, "%s: failed to create wcd939x variant entry\n",
  3758. __func__);
  3759. snd_info_free_entry(version_entry);
  3760. snd_info_free_entry(priv->entry);
  3761. return -ENOMEM;
  3762. }
  3763. variant_entry->private_data = priv;
  3764. variant_entry->size = WCD939X_VARIANT_ENTRY_SIZE;
  3765. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3766. variant_entry->c.ops = &wcd939x_variant_ops;
  3767. if (snd_info_register(variant_entry) < 0) {
  3768. snd_info_free_entry(variant_entry);
  3769. snd_info_free_entry(version_entry);
  3770. snd_info_free_entry(priv->entry);
  3771. return -ENOMEM;
  3772. }
  3773. priv->variant_entry = variant_entry;
  3774. return 0;
  3775. }
  3776. EXPORT_SYMBOL(wcd939x_info_create_codec_entry);
  3777. static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x,
  3778. struct wcd939x_pdata *pdata)
  3779. {
  3780. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3781. int rc = 0;
  3782. if (!pdata) {
  3783. dev_err(wcd939x->dev, "%s: NULL pdata\n", __func__);
  3784. return -ENODEV;
  3785. }
  3786. /* set micbias voltage */
  3787. vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3788. vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3789. vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3790. vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3791. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3792. vout_ctl_4 < 0) {
  3793. rc = -EINVAL;
  3794. goto done;
  3795. }
  3796. regmap_update_bits(wcd939x->regmap, WCD939X_MICB1, 0x3F,
  3797. vout_ctl_1);
  3798. regmap_update_bits(wcd939x->regmap, WCD939X_MICB2, 0x3F,
  3799. vout_ctl_2);
  3800. regmap_update_bits(wcd939x->regmap, WCD939X_MICB3, 0x3F,
  3801. vout_ctl_3);
  3802. regmap_update_bits(wcd939x->regmap, WCD939X_MICB4, 0x3F,
  3803. vout_ctl_4);
  3804. done:
  3805. return rc;
  3806. }
  3807. static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
  3808. {
  3809. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3810. struct snd_soc_dapm_context *dapm =
  3811. snd_soc_component_get_dapm(component);
  3812. int ret = -EINVAL;
  3813. dev_info(component->dev, "%s()\n", __func__);
  3814. wcd939x = snd_soc_component_get_drvdata(component);
  3815. if (!wcd939x)
  3816. return -EINVAL;
  3817. wcd939x->component = component;
  3818. snd_soc_component_init_regmap(component, wcd939x->regmap);
  3819. devm_regmap_qti_debugfs_register(&wcd939x->tx_swr_dev->dev, wcd939x->regmap);
  3820. /*Harmonium contains only one variant i.e wcd9395*/
  3821. wcd939x->variant = WCD9395;
  3822. wcd939x->fw_data = devm_kzalloc(component->dev,
  3823. sizeof(*(wcd939x->fw_data)),
  3824. GFP_KERNEL);
  3825. if (!wcd939x->fw_data) {
  3826. dev_err(component->dev, "Failed to allocate fw_data\n");
  3827. ret = -ENOMEM;
  3828. goto err;
  3829. }
  3830. set_bit(WCD9XXX_MBHC_CAL, wcd939x->fw_data->cal_bit);
  3831. ret = wcd_cal_create_hwdep(wcd939x->fw_data,
  3832. WCD9XXX_CODEC_HWDEP_NODE, component);
  3833. if (ret < 0) {
  3834. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3835. goto err_hwdep;
  3836. }
  3837. ret = wcd939x_mbhc_init(&wcd939x->mbhc, component, wcd939x->fw_data);
  3838. if (ret) {
  3839. pr_err("%s: mbhc initialization failed\n", __func__);
  3840. goto err_hwdep;
  3841. }
  3842. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Playback");
  3843. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Capture");
  3844. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3845. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3846. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3847. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3848. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3849. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3850. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3851. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3852. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3853. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3854. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3855. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3856. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3857. snd_soc_dapm_ignore_suspend(dapm, "IN3_EAR");
  3858. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3859. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3860. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3861. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3862. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3863. snd_soc_dapm_sync(dapm);
  3864. wcd_cls_h_init(&wcd939x->clsh_info);
  3865. wcd939x_init_reg(component);
  3866. if (wcd939x->variant == WCD9390) {
  3867. ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
  3868. ARRAY_SIZE(wcd9390_snd_controls));
  3869. if (ret < 0) {
  3870. dev_err(component->dev,
  3871. "%s: Failed to add snd ctrls for variant: %d\n",
  3872. __func__, wcd939x->variant);
  3873. goto err_hwdep;
  3874. }
  3875. }
  3876. if (wcd939x->variant == WCD9395) {
  3877. ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
  3878. ARRAY_SIZE(wcd9395_snd_controls));
  3879. if (ret < 0) {
  3880. dev_err(component->dev,
  3881. "%s: Failed to add snd ctrls for variant: %d\n",
  3882. __func__, wcd939x->variant);
  3883. goto err_hwdep;
  3884. }
  3885. }
  3886. wcd939x->version = WCD939X_VERSION_1_0;
  3887. /* Register event notifier */
  3888. wcd939x->nblock.notifier_call = wcd939x_event_notify;
  3889. if (wcd939x->register_notifier) {
  3890. ret = wcd939x->register_notifier(wcd939x->handle,
  3891. &wcd939x->nblock,
  3892. true);
  3893. if (ret) {
  3894. dev_err(component->dev,
  3895. "%s: Failed to register notifier %d\n",
  3896. __func__, ret);
  3897. return ret;
  3898. }
  3899. }
  3900. return ret;
  3901. err_hwdep:
  3902. wcd939x->fw_data = NULL;
  3903. err:
  3904. return ret;
  3905. }
  3906. static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
  3907. {
  3908. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3909. if (!wcd939x) {
  3910. dev_err(component->dev, "%s: wcd939x is already NULL\n",
  3911. __func__);
  3912. return;
  3913. }
  3914. if (wcd939x->register_notifier)
  3915. wcd939x->register_notifier(wcd939x->handle,
  3916. &wcd939x->nblock,
  3917. false);
  3918. }
  3919. static int wcd939x_soc_codec_suspend(struct snd_soc_component *component)
  3920. {
  3921. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3922. if (!wcd939x)
  3923. return 0;
  3924. wcd939x->dapm_bias_off = true;
  3925. return 0;
  3926. }
  3927. static int wcd939x_soc_codec_resume(struct snd_soc_component *component)
  3928. {
  3929. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3930. if (!wcd939x)
  3931. return 0;
  3932. wcd939x->dapm_bias_off = false;
  3933. return 0;
  3934. }
  3935. static struct snd_soc_component_driver soc_codec_dev_wcd939x = {
  3936. .name = WCD939X_DRV_NAME,
  3937. .probe = wcd939x_soc_codec_probe,
  3938. .remove = wcd939x_soc_codec_remove,
  3939. .controls = wcd939x_snd_controls,
  3940. .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
  3941. .dapm_widgets = wcd939x_dapm_widgets,
  3942. .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
  3943. .dapm_routes = wcd939x_audio_map,
  3944. .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
  3945. .suspend = wcd939x_soc_codec_suspend,
  3946. .resume = wcd939x_soc_codec_resume,
  3947. };
  3948. static int wcd939x_reset(struct device *dev)
  3949. {
  3950. struct wcd939x_priv *wcd939x = NULL;
  3951. int rc = 0;
  3952. int value = 0;
  3953. if (!dev)
  3954. return -ENODEV;
  3955. wcd939x = dev_get_drvdata(dev);
  3956. if (!wcd939x)
  3957. return -EINVAL;
  3958. if (!wcd939x->rst_np) {
  3959. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  3960. __func__);
  3961. return -EINVAL;
  3962. }
  3963. value = msm_cdc_pinctrl_get_state(wcd939x->rst_np);
  3964. if (value > 0)
  3965. return 0;
  3966. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  3967. if (rc) {
  3968. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  3969. __func__);
  3970. return rc;
  3971. }
  3972. /* 20us sleep required after pulling the reset gpio to LOW */
  3973. usleep_range(20, 30);
  3974. rc = msm_cdc_pinctrl_select_active_state(wcd939x->rst_np);
  3975. if (rc) {
  3976. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  3977. __func__);
  3978. return rc;
  3979. }
  3980. /* 20us sleep required after pulling the reset gpio to HIGH */
  3981. usleep_range(20, 30);
  3982. return rc;
  3983. }
  3984. static int wcd939x_read_of_property_u32(struct device *dev, const char *name,
  3985. u32 *val)
  3986. {
  3987. int rc = 0;
  3988. rc = of_property_read_u32(dev->of_node, name, val);
  3989. if (rc)
  3990. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3991. __func__, name, dev->of_node->full_name);
  3992. return rc;
  3993. }
  3994. static void wcd939x_dt_parse_micbias_info(struct device *dev,
  3995. struct wcd939x_micbias_setting *mb)
  3996. {
  3997. u32 prop_val = 0;
  3998. int rc = 0;
  3999. /* MB1 */
  4000. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  4001. NULL)) {
  4002. rc = wcd939x_read_of_property_u32(dev,
  4003. "qcom,cdc-micbias1-mv",
  4004. &prop_val);
  4005. if (!rc)
  4006. mb->micb1_mv = prop_val;
  4007. } else {
  4008. dev_info(dev, "%s: Micbias1 DT property not found\n",
  4009. __func__);
  4010. }
  4011. /* MB2 */
  4012. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  4013. NULL)) {
  4014. rc = wcd939x_read_of_property_u32(dev,
  4015. "qcom,cdc-micbias2-mv",
  4016. &prop_val);
  4017. if (!rc)
  4018. mb->micb2_mv = prop_val;
  4019. } else {
  4020. dev_info(dev, "%s: Micbias2 DT property not found\n",
  4021. __func__);
  4022. }
  4023. /* MB3 */
  4024. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  4025. NULL)) {
  4026. rc = wcd939x_read_of_property_u32(dev,
  4027. "qcom,cdc-micbias3-mv",
  4028. &prop_val);
  4029. if (!rc)
  4030. mb->micb3_mv = prop_val;
  4031. } else {
  4032. dev_info(dev, "%s: Micbias3 DT property not found\n",
  4033. __func__);
  4034. }
  4035. /* MB4 */
  4036. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  4037. NULL)) {
  4038. rc = wcd939x_read_of_property_u32(dev,
  4039. "qcom,cdc-micbias4-mv",
  4040. &prop_val);
  4041. if (!rc)
  4042. mb->micb4_mv = prop_val;
  4043. } else {
  4044. dev_info(dev, "%s: Micbias4 DT property not found\n",
  4045. __func__);
  4046. }
  4047. }
  4048. static int wcd939x_reset_low(struct device *dev)
  4049. {
  4050. struct wcd939x_priv *wcd939x = NULL;
  4051. int rc = 0;
  4052. if (!dev)
  4053. return -ENODEV;
  4054. wcd939x = dev_get_drvdata(dev);
  4055. if (!wcd939x)
  4056. return -EINVAL;
  4057. if (!wcd939x->rst_np) {
  4058. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4059. __func__);
  4060. return -EINVAL;
  4061. }
  4062. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4063. if (rc) {
  4064. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4065. __func__);
  4066. return rc;
  4067. }
  4068. /* 20us sleep required after pulling the reset gpio to LOW */
  4069. usleep_range(20, 30);
  4070. return rc;
  4071. }
  4072. struct wcd939x_pdata *wcd939x_populate_dt_data(struct device *dev)
  4073. {
  4074. struct wcd939x_pdata *pdata = NULL;
  4075. pdata = devm_kzalloc(dev, sizeof(struct wcd939x_pdata),
  4076. GFP_KERNEL);
  4077. if (!pdata)
  4078. return NULL;
  4079. pdata->rst_np = of_parse_phandle(dev->of_node,
  4080. "qcom,wcd-rst-gpio-node", 0);
  4081. if (!pdata->rst_np) {
  4082. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  4083. __func__, "qcom,wcd-rst-gpio-node",
  4084. dev->of_node->full_name);
  4085. return NULL;
  4086. }
  4087. /* Parse power supplies */
  4088. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  4089. &pdata->num_supplies);
  4090. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  4091. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  4092. __func__);
  4093. return NULL;
  4094. }
  4095. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  4096. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  4097. wcd939x_dt_parse_micbias_info(dev, &pdata->micbias);
  4098. return pdata;
  4099. }
  4100. static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
  4101. {
  4102. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  4103. __func__, irq);
  4104. return IRQ_HANDLED;
  4105. }
  4106. static struct snd_soc_dai_driver wcd939x_dai[] = {
  4107. {
  4108. .name = "wcd939x_cdc",
  4109. .playback = {
  4110. .stream_name = "WCD939X_AIF Playback",
  4111. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4112. .formats = WCD939X_FORMATS,
  4113. .rate_max = 384000,
  4114. .rate_min = 8000,
  4115. .channels_min = 1,
  4116. .channels_max = 4,
  4117. },
  4118. .capture = {
  4119. .stream_name = "WCD939X_AIF Capture",
  4120. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4121. .formats = WCD939X_FORMATS,
  4122. .rate_max = 384000,
  4123. .rate_min = 8000,
  4124. .channels_min = 1,
  4125. .channels_max = 4,
  4126. },
  4127. },
  4128. };
  4129. static int wcd939x_bind(struct device *dev)
  4130. {
  4131. int ret = 0, i = 0;
  4132. struct wcd939x_pdata *pdata = dev_get_platdata(dev);
  4133. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4134. /*
  4135. * Add 5msec delay to provide sufficient time for
  4136. * soundwire auto enumeration of slave devices as
  4137. * as per HW requirement.
  4138. */
  4139. usleep_range(5000, 5010);
  4140. ret = component_bind_all(dev, wcd939x);
  4141. if (ret) {
  4142. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  4143. __func__, ret);
  4144. return ret;
  4145. }
  4146. wcd939x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  4147. if (!wcd939x->rx_swr_dev) {
  4148. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  4149. __func__);
  4150. ret = -ENODEV;
  4151. goto err;
  4152. }
  4153. wcd939x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  4154. if (!wcd939x->tx_swr_dev) {
  4155. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  4156. __func__);
  4157. ret = -ENODEV;
  4158. goto err;
  4159. }
  4160. swr_init_port_params(wcd939x->tx_swr_dev, SWR_NUM_PORTS,
  4161. wcd939x->swr_tx_port_params);
  4162. wcd939x->regmap = devm_regmap_init_swr(wcd939x->tx_swr_dev,
  4163. &wcd939x_regmap_config);
  4164. if (!wcd939x->regmap) {
  4165. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  4166. __func__);
  4167. goto err;
  4168. }
  4169. /* Set all interupts as edge triggered */
  4170. for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
  4171. regmap_write(wcd939x->regmap,
  4172. (WCD939X_INTR_LEVEL_0 + i), 0);
  4173. wcd939x_regmap_irq_chip.irq_drv_data = wcd939x;
  4174. wcd939x->irq_info.wcd_regmap_irq_chip = &wcd939x_regmap_irq_chip;
  4175. wcd939x->irq_info.codec_name = "WCD939X";
  4176. wcd939x->irq_info.regmap = wcd939x->regmap;
  4177. wcd939x->irq_info.dev = dev;
  4178. ret = wcd_irq_init(&wcd939x->irq_info, &wcd939x->virq);
  4179. if (ret) {
  4180. dev_err_ratelimited(wcd939x->dev, "%s: IRQ init failed: %d\n",
  4181. __func__, ret);
  4182. goto err;
  4183. }
  4184. wcd939x->tx_swr_dev->slave_irq = wcd939x->virq;
  4185. ret = wcd939x_set_micbias_data(wcd939x, pdata);
  4186. if (ret < 0) {
  4187. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  4188. goto err_irq;
  4189. }
  4190. /* Request for watchdog interrupt */
  4191. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT,
  4192. "HPHR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4193. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT,
  4194. "HPHL PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4195. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT,
  4196. "EAR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4197. /* Disable watchdog interrupt for HPH and EAR */
  4198. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT);
  4199. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT);
  4200. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  4201. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
  4202. wcd939x_dai, ARRAY_SIZE(wcd939x_dai));
  4203. if (ret) {
  4204. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  4205. __func__);
  4206. goto err_irq;
  4207. }
  4208. wcd939x->dev_up = true;
  4209. return ret;
  4210. err_irq:
  4211. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4212. err:
  4213. component_unbind_all(dev, wcd939x);
  4214. return ret;
  4215. }
  4216. static void wcd939x_unbind(struct device *dev)
  4217. {
  4218. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4219. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT, NULL);
  4220. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT, NULL);
  4221. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT, NULL);
  4222. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4223. snd_soc_unregister_component(dev);
  4224. component_unbind_all(dev, wcd939x);
  4225. }
  4226. static const struct of_device_id wcd939x_dt_match[] = {
  4227. { .compatible = "qcom,wcd939x-codec", .data = "wcd939x"},
  4228. {}
  4229. };
  4230. static const struct component_master_ops wcd939x_comp_ops = {
  4231. .bind = wcd939x_bind,
  4232. .unbind = wcd939x_unbind,
  4233. };
  4234. static int wcd939x_compare_of(struct device *dev, void *data)
  4235. {
  4236. return dev->of_node == data;
  4237. }
  4238. static void wcd939x_release_of(struct device *dev, void *data)
  4239. {
  4240. of_node_put(data);
  4241. }
  4242. static int wcd939x_add_slave_components(struct device *dev,
  4243. struct component_match **matchptr)
  4244. {
  4245. struct device_node *np, *rx_node, *tx_node;
  4246. np = dev->of_node;
  4247. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  4248. if (!rx_node) {
  4249. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  4250. return -ENODEV;
  4251. }
  4252. of_node_get(rx_node);
  4253. component_match_add_release(dev, matchptr,
  4254. wcd939x_release_of,
  4255. wcd939x_compare_of,
  4256. rx_node);
  4257. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  4258. if (!tx_node) {
  4259. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  4260. return -ENODEV;
  4261. }
  4262. of_node_get(tx_node);
  4263. component_match_add_release(dev, matchptr,
  4264. wcd939x_release_of,
  4265. wcd939x_compare_of,
  4266. tx_node);
  4267. return 0;
  4268. }
  4269. static int wcd939x_probe(struct platform_device *pdev)
  4270. {
  4271. struct component_match *match = NULL;
  4272. struct wcd939x_priv *wcd939x = NULL;
  4273. struct wcd939x_pdata *pdata = NULL;
  4274. struct wcd_ctrl_platform_data *plat_data = NULL;
  4275. struct device *dev = &pdev->dev;
  4276. int ret;
  4277. wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
  4278. GFP_KERNEL);
  4279. if (!wcd939x)
  4280. return -ENOMEM;
  4281. dev_set_drvdata(dev, wcd939x);
  4282. wcd939x->dev = dev;
  4283. pdata = wcd939x_populate_dt_data(dev);
  4284. if (!pdata) {
  4285. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4286. return -EINVAL;
  4287. }
  4288. dev->platform_data = pdata;
  4289. wcd939x->rst_np = pdata->rst_np;
  4290. ret = msm_cdc_init_supplies(dev, &wcd939x->supplies,
  4291. pdata->regulator, pdata->num_supplies);
  4292. if (!wcd939x->supplies) {
  4293. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4294. __func__);
  4295. return ret;
  4296. }
  4297. plat_data = dev_get_platdata(dev->parent);
  4298. if (!plat_data) {
  4299. dev_err(dev, "%s: platform data from parent is NULL\n",
  4300. __func__);
  4301. return -EINVAL;
  4302. }
  4303. wcd939x->handle = (void *)plat_data->handle;
  4304. if (!wcd939x->handle) {
  4305. dev_err(dev, "%s: handle is NULL\n", __func__);
  4306. return -EINVAL;
  4307. }
  4308. wcd939x->update_wcd_event = plat_data->update_wcd_event;
  4309. if (!wcd939x->update_wcd_event) {
  4310. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4311. __func__);
  4312. return -EINVAL;
  4313. }
  4314. wcd939x->register_notifier = plat_data->register_notifier;
  4315. if (!wcd939x->register_notifier) {
  4316. dev_err(dev, "%s: register_notifier api is null!\n",
  4317. __func__);
  4318. return -EINVAL;
  4319. }
  4320. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd939x->supplies,
  4321. pdata->regulator,
  4322. pdata->num_supplies);
  4323. if (ret) {
  4324. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4325. __func__);
  4326. return ret;
  4327. }
  4328. ret = wcd939x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4329. CODEC_RX);
  4330. ret |= wcd939x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4331. CODEC_TX);
  4332. if (ret) {
  4333. dev_err(dev, "Failed to read port mapping\n");
  4334. goto err;
  4335. }
  4336. ret = wcd939x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4337. CODEC_TX);
  4338. if (ret) {
  4339. dev_err(dev, "Failed to read port params\n");
  4340. goto err;
  4341. }
  4342. mutex_init(&wcd939x->wakeup_lock);
  4343. mutex_init(&wcd939x->micb_lock);
  4344. ret = wcd939x_add_slave_components(dev, &match);
  4345. if (ret)
  4346. goto err_lock_init;
  4347. wcd939x_reset(dev);
  4348. wcd939x->wakeup = wcd939x_wakeup;
  4349. return component_master_add_with_match(dev,
  4350. &wcd939x_comp_ops, match);
  4351. err_lock_init:
  4352. mutex_destroy(&wcd939x->micb_lock);
  4353. mutex_destroy(&wcd939x->wakeup_lock);
  4354. err:
  4355. return ret;
  4356. }
  4357. static int wcd939x_remove(struct platform_device *pdev)
  4358. {
  4359. struct wcd939x_priv *wcd939x = NULL;
  4360. wcd939x = platform_get_drvdata(pdev);
  4361. component_master_del(&pdev->dev, &wcd939x_comp_ops);
  4362. mutex_destroy(&wcd939x->micb_lock);
  4363. mutex_destroy(&wcd939x->wakeup_lock);
  4364. dev_set_drvdata(&pdev->dev, NULL);
  4365. return 0;
  4366. }
  4367. #ifdef CONFIG_PM_SLEEP
  4368. static int wcd939x_suspend(struct device *dev)
  4369. {
  4370. struct wcd939x_priv *wcd939x = NULL;
  4371. int ret = 0;
  4372. struct wcd939x_pdata *pdata = NULL;
  4373. if (!dev)
  4374. return -ENODEV;
  4375. wcd939x = dev_get_drvdata(dev);
  4376. if (!wcd939x)
  4377. return -EINVAL;
  4378. pdata = dev_get_platdata(wcd939x->dev);
  4379. if (!pdata) {
  4380. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4381. return -EINVAL;
  4382. }
  4383. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  4384. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4385. wcd939x->supplies,
  4386. pdata->regulator,
  4387. pdata->num_supplies,
  4388. "cdc-vdd-buck");
  4389. if (ret == -EINVAL) {
  4390. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4391. __func__);
  4392. return 0;
  4393. }
  4394. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  4395. }
  4396. if (wcd939x->dapm_bias_off ||
  4397. (wcd939x->component &&
  4398. (snd_soc_component_get_bias_level(wcd939x->component) ==
  4399. SND_SOC_BIAS_OFF))) {
  4400. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4401. wcd939x->supplies,
  4402. pdata->regulator,
  4403. pdata->num_supplies,
  4404. true);
  4405. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4406. }
  4407. return 0;
  4408. }
  4409. static int wcd939x_resume(struct device *dev)
  4410. {
  4411. struct wcd939x_priv *wcd939x = NULL;
  4412. struct wcd939x_pdata *pdata = NULL;
  4413. if (!dev)
  4414. return -ENODEV;
  4415. wcd939x = dev_get_drvdata(dev);
  4416. if (!wcd939x)
  4417. return -EINVAL;
  4418. pdata = dev_get_platdata(wcd939x->dev);
  4419. if (!pdata) {
  4420. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4421. return -EINVAL;
  4422. }
  4423. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask)) {
  4424. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4425. wcd939x->supplies,
  4426. pdata->regulator,
  4427. pdata->num_supplies,
  4428. false);
  4429. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4430. }
  4431. return 0;
  4432. }
  4433. static const struct dev_pm_ops wcd939x_dev_pm_ops = {
  4434. .suspend_late = wcd939x_suspend,
  4435. .resume_early = wcd939x_resume,
  4436. };
  4437. #endif
  4438. static struct platform_driver wcd939x_codec_driver = {
  4439. .probe = wcd939x_probe,
  4440. .remove = wcd939x_remove,
  4441. .driver = {
  4442. .name = "wcd939x_codec",
  4443. .owner = THIS_MODULE,
  4444. .of_match_table = of_match_ptr(wcd939x_dt_match),
  4445. #ifdef CONFIG_PM_SLEEP
  4446. .pm = &wcd939x_dev_pm_ops,
  4447. #endif
  4448. .suppress_bind_attrs = true,
  4449. },
  4450. };
  4451. module_platform_driver(wcd939x_codec_driver);
  4452. MODULE_DESCRIPTION("WCD939X Codec driver");
  4453. MODULE_LICENSE("GPL v2");