wcd937x.c 99 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/regmap.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <asoc/wcdcal-hwdep.h>
  21. #include <asoc/msm-cdc-pinctrl.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include "wcd937x-registers.h"
  25. #include "wcd937x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #include <linux/qti-regmap-debugfs.h>
  29. #define WCD9370_VARIANT 0
  30. #define WCD9375_VARIANT 5
  31. #define WCD937X_VARIANT_ENTRY_SIZE 32
  32. #define NUM_SWRS_DT_PARAMS 5
  33. #define WCD937X_VERSION_1_0 1
  34. #define WCD937X_VERSION_ENTRY_SIZE 32
  35. #define EAR_RX_PATH_AUX 1
  36. #define NUM_ATTEMPTS 5
  37. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  38. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  39. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  40. SNDRV_PCM_RATE_384000)
  41. /* Fractional Rates */
  42. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  43. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  44. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  45. SNDRV_PCM_FMTBIT_S24_LE |\
  46. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  47. enum {
  48. CODEC_TX = 0,
  49. CODEC_RX,
  50. };
  51. enum {
  52. ALLOW_BUCK_DISABLE,
  53. HPH_COMP_DELAY,
  54. HPH_PA_DELAY,
  55. AMIC2_BCS_ENABLE,
  56. };
  57. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  58. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  59. static int wcd937x_handle_post_irq(void *data);
  60. static int wcd937x_reset(struct device *dev);
  61. static int wcd937x_reset_low(struct device *dev);
  62. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  81. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  82. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  83. };
  84. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  85. .name = "wcd937x",
  86. .irqs = wcd937x_irqs,
  87. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  88. .num_regs = 3,
  89. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  90. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  91. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  92. .use_ack = 1,
  93. //#if IS_ENABLED(CONFIG_AUDIO_QGKI)
  94. .clear_ack = 1,
  95. //#endif
  96. .mask_writeonly = 1,
  97. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  98. .runtime_pm = false,
  99. .handle_post_irq = wcd937x_handle_post_irq,
  100. .irq_drv_data = NULL,
  101. };
  102. static struct snd_soc_dai_driver wcd937x_dai[] = {
  103. {
  104. .name = "wcd937x_cdc",
  105. .playback = {
  106. .stream_name = "WCD937X_AIF Playback",
  107. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  108. .formats = WCD937X_FORMATS,
  109. .rate_max = 384000,
  110. .rate_min = 8000,
  111. .channels_min = 1,
  112. .channels_max = 4,
  113. },
  114. .capture = {
  115. .stream_name = "WCD937X_AIF Capture",
  116. .rates = WCD937X_RATES,
  117. .formats = WCD937X_FORMATS,
  118. .rate_max = 192000,
  119. .rate_min = 8000,
  120. .channels_min = 1,
  121. .channels_max = 4,
  122. },
  123. },
  124. };
  125. static int wcd937x_handle_post_irq(void *data)
  126. {
  127. struct wcd937x_priv *wcd937x = data;
  128. u32 status1 = 0, status2 = 0, status3 = 0;
  129. /* Clear the ACK registers. Temporary workaround.*/
  130. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0x0);
  131. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0x0);
  132. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0x0);
  133. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  134. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  135. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  136. wcd937x->tx_swr_dev->slave_irq_pending =
  137. ((status1 || status2 || status3) ? true : false);
  138. return IRQ_HANDLED;
  139. }
  140. static int wcd937x_init_reg(struct snd_soc_component *component)
  141. {
  142. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  143. 0x0E, 0x0E);
  144. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  145. 0x80, 0x80);
  146. usleep_range(1000, 1010);
  147. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  148. 0x40, 0x40);
  149. usleep_range(1000, 1010);
  150. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  151. 0x10, 0x00);
  152. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  153. 0xF0, 0x80);
  154. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  155. 0x80, 0x80);
  156. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  157. 0x40, 0x40);
  158. usleep_range(10000, 10010);
  159. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  160. 0x40, 0x00);
  161. snd_soc_component_update_bits(component,
  162. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  163. 0xFF, 0xD9);
  164. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  165. 0xFF, 0xFA);
  166. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  167. 0xFF, 0xFA);
  168. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  169. 0xFF, 0xFA);
  170. return 0;
  171. }
  172. static int wcd937x_set_port_params(struct snd_soc_component *component,
  173. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  174. u8 *ch_mask, u32 *ch_rate,
  175. u8 *port_type, u8 path)
  176. {
  177. int i, j;
  178. u8 num_ports = 0;
  179. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  180. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  181. switch (path) {
  182. case CODEC_RX:
  183. map = &wcd937x->rx_port_mapping;
  184. num_ports = wcd937x->num_rx_ports;
  185. break;
  186. case CODEC_TX:
  187. map = &wcd937x->tx_port_mapping;
  188. num_ports = wcd937x->num_tx_ports;
  189. break;
  190. default:
  191. dev_err(component->dev, "%s Invalid path selected %u\n",
  192. __func__, path);
  193. return -EINVAL;
  194. }
  195. for (i = 0; i <= num_ports; i++) {
  196. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  197. if ((*map)[i][j].slave_port_type == slv_prt_type)
  198. goto found;
  199. }
  200. }
  201. found:
  202. if (i > num_ports || j == MAX_CH_PER_PORT) {
  203. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  204. __func__, slv_prt_type);
  205. return -EINVAL;
  206. }
  207. *port_id = i;
  208. *num_ch = (*map)[i][j].num_ch;
  209. *ch_mask = (*map)[i][j].ch_mask;
  210. *ch_rate = (*map)[i][j].ch_rate;
  211. *port_type = (*map)[i][j].master_port_type;
  212. return 0;
  213. }
  214. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  215. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  216. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  217. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  218. static int wcd937x_parse_port_params(struct device *dev,
  219. char *prop, u8 path)
  220. {
  221. u32 *dt_array, map_size, max_uc;
  222. int ret = 0;
  223. u32 cnt = 0;
  224. u32 i, j;
  225. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  226. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  227. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  228. switch (path) {
  229. case CODEC_TX:
  230. map = &wcd937x->tx_port_params;
  231. map_uc = &wcd937x->swr_tx_port_params;
  232. break;
  233. default:
  234. ret = -EINVAL;
  235. goto err_port_map;
  236. }
  237. if (!of_find_property(dev->of_node, prop,
  238. &map_size)) {
  239. dev_err(dev, "missing port mapping prop %s\n", prop);
  240. ret = -EINVAL;
  241. goto err_port_map;
  242. }
  243. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  244. if (max_uc != SWR_UC_MAX) {
  245. dev_err(dev, "%s: port params not provided for all usecases\n",
  246. __func__);
  247. ret = -EINVAL;
  248. goto err_port_map;
  249. }
  250. dt_array = kzalloc(map_size, GFP_KERNEL);
  251. if (!dt_array) {
  252. ret = -ENOMEM;
  253. goto err_alloc;
  254. }
  255. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  256. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  257. if (ret) {
  258. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  259. __func__, prop);
  260. goto err_pdata_fail;
  261. }
  262. for (i = 0; i < max_uc; i++) {
  263. for (j = 0; j < SWR_NUM_PORTS; j++) {
  264. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  265. (*map)[i][j].offset1 = dt_array[cnt];
  266. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  267. }
  268. (*map_uc)[i].pp = &(*map)[i][0];
  269. }
  270. kfree(dt_array);
  271. return 0;
  272. err_pdata_fail:
  273. kfree(dt_array);
  274. err_alloc:
  275. err_port_map:
  276. return ret;
  277. }
  278. static int wcd937x_parse_port_mapping(struct device *dev,
  279. char *prop, u8 path)
  280. {
  281. u32 *dt_array, map_size, map_length;
  282. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  283. u32 slave_port_type, master_port_type;
  284. u32 i, ch_iter = 0;
  285. int ret = 0;
  286. u8 *num_ports = NULL;
  287. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  288. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  289. switch (path) {
  290. case CODEC_RX:
  291. map = &wcd937x->rx_port_mapping;
  292. num_ports = &wcd937x->num_rx_ports;
  293. break;
  294. case CODEC_TX:
  295. map = &wcd937x->tx_port_mapping;
  296. num_ports = &wcd937x->num_tx_ports;
  297. break;
  298. default:
  299. dev_err(dev, "%s Invalid path selected %u\n",
  300. __func__, path);
  301. return -EINVAL;
  302. }
  303. if (!of_find_property(dev->of_node, prop,
  304. &map_size)) {
  305. dev_err(dev, "missing port mapping prop %s\n", prop);
  306. ret = -EINVAL;
  307. goto err;
  308. }
  309. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  310. dt_array = kzalloc(map_size, GFP_KERNEL);
  311. if (!dt_array) {
  312. ret = -ENOMEM;
  313. goto err;
  314. }
  315. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  316. NUM_SWRS_DT_PARAMS * map_length);
  317. if (ret) {
  318. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  319. __func__, prop);
  320. ret = -EINVAL;
  321. goto err_pdata_fail;
  322. }
  323. for (i = 0; i < map_length; i++) {
  324. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  325. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  326. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  327. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  328. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  329. if (port_num != old_port_num)
  330. ch_iter = 0;
  331. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  332. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  333. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  334. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  335. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  336. old_port_num = port_num;
  337. }
  338. *num_ports = port_num;
  339. kfree(dt_array);
  340. return 0;
  341. err_pdata_fail:
  342. kfree(dt_array);
  343. err:
  344. return ret;
  345. }
  346. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  347. u8 slv_port_type, u8 enable)
  348. {
  349. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  350. u8 port_id;
  351. u8 num_ch;
  352. u8 ch_mask;
  353. u32 ch_rate;
  354. u8 ch_type = 0;
  355. int slave_ch_idx;
  356. u8 num_port = 1;
  357. int ret = 0;
  358. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  359. &num_ch, &ch_mask, &ch_rate,
  360. &ch_type, CODEC_TX);
  361. if (ret)
  362. return ret;
  363. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  364. if (slave_ch_idx != -EINVAL)
  365. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  366. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  367. __func__, slave_ch_idx, ch_type);
  368. if (enable)
  369. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  370. num_port, &ch_mask, &ch_rate,
  371. &num_ch, &ch_type);
  372. else
  373. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  374. num_port, &ch_mask, &ch_type);
  375. return ret;
  376. }
  377. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  378. u8 slv_port_type, u8 enable)
  379. {
  380. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  381. u8 port_id;
  382. u8 num_ch;
  383. u8 ch_mask;
  384. u32 ch_rate;
  385. u8 port_type;
  386. u8 num_port = 1;
  387. int ret = 0;
  388. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  389. &num_ch, &ch_mask, &ch_rate,
  390. &port_type, CODEC_RX);
  391. if (ret)
  392. return ret;
  393. if (enable)
  394. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  395. num_port, &ch_mask, &ch_rate,
  396. &num_ch, &port_type);
  397. else
  398. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  399. num_port, &ch_mask, &port_type);
  400. return ret;
  401. }
  402. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  403. {
  404. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  405. if (wcd937x->rx_clk_cnt == 0) {
  406. snd_soc_component_update_bits(component,
  407. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  408. snd_soc_component_update_bits(component,
  409. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  410. snd_soc_component_update_bits(component,
  411. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  412. snd_soc_component_update_bits(component,
  413. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  414. snd_soc_component_update_bits(component,
  415. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  416. snd_soc_component_update_bits(component,
  417. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  418. snd_soc_component_update_bits(component,
  419. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  420. }
  421. wcd937x->rx_clk_cnt++;
  422. return 0;
  423. }
  424. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  425. {
  426. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  427. if (wcd937x->rx_clk_cnt == 0) {
  428. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  429. return 0;
  430. }
  431. wcd937x->rx_clk_cnt--;
  432. if (wcd937x->rx_clk_cnt == 0) {
  433. snd_soc_component_update_bits(component,
  434. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  435. snd_soc_component_update_bits(component,
  436. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  437. 0x02, 0x00);
  438. snd_soc_component_update_bits(component,
  439. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  440. 0x01, 0x00);
  441. }
  442. return 0;
  443. }
  444. /*
  445. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  446. * @component: handle to snd_soc_component *
  447. *
  448. * return wcd937x_mbhc handle or error code in case of failure
  449. */
  450. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  451. {
  452. struct wcd937x_priv *wcd937x;
  453. if (!component) {
  454. pr_err("%s: Invalid params, NULL component\n", __func__);
  455. return NULL;
  456. }
  457. wcd937x = snd_soc_component_get_drvdata(component);
  458. if (!wcd937x) {
  459. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  460. return NULL;
  461. }
  462. return wcd937x->mbhc;
  463. }
  464. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  465. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  466. struct snd_kcontrol *kcontrol,
  467. int event)
  468. {
  469. struct snd_soc_component *component =
  470. snd_soc_dapm_to_component(w->dapm);
  471. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  472. int hph_mode = wcd937x->hph_mode;
  473. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  474. w->name, event);
  475. switch (event) {
  476. case SND_SOC_DAPM_PRE_PMU:
  477. wcd937x_rx_clk_enable(component);
  478. snd_soc_component_update_bits(component,
  479. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  480. 0x01, 0x01);
  481. snd_soc_component_update_bits(component,
  482. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  483. 0x04, 0x04);
  484. snd_soc_component_update_bits(component,
  485. WCD937X_HPH_RDAC_CLK_CTL1,
  486. 0x80, 0x00);
  487. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  488. break;
  489. case SND_SOC_DAPM_POST_PMU:
  490. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  491. snd_soc_component_update_bits(component,
  492. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  493. 0x0F, 0x02);
  494. else if (hph_mode == CLS_H_LOHIFI)
  495. snd_soc_component_update_bits(component,
  496. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  497. 0x0F, 0x06);
  498. if (wcd937x->comp1_enable) {
  499. snd_soc_component_update_bits(component,
  500. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  501. 0x02, 0x02);
  502. snd_soc_component_update_bits(component,
  503. WCD937X_HPH_L_EN, 0x20, 0x00);
  504. if (wcd937x->comp2_enable) {
  505. snd_soc_component_update_bits(component,
  506. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  507. 0x01, 0x01);
  508. snd_soc_component_update_bits(component,
  509. WCD937X_HPH_R_EN, 0x20, 0x00);
  510. }
  511. /*
  512. * 5ms sleep is required after COMP is enabled as per
  513. * HW requirement
  514. */
  515. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  516. usleep_range(5000, 5100);
  517. clear_bit(HPH_COMP_DELAY,
  518. &wcd937x->status_mask);
  519. }
  520. } else {
  521. snd_soc_component_update_bits(component,
  522. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  523. 0x02, 0x00);
  524. snd_soc_component_update_bits(component,
  525. WCD937X_HPH_L_EN, 0x20, 0x20);
  526. }
  527. snd_soc_component_update_bits(component,
  528. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  529. break;
  530. case SND_SOC_DAPM_POST_PMD:
  531. snd_soc_component_update_bits(component,
  532. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  533. 0x0F, 0x01);
  534. break;
  535. }
  536. return 0;
  537. }
  538. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  539. struct snd_kcontrol *kcontrol,
  540. int event)
  541. {
  542. struct snd_soc_component *component =
  543. snd_soc_dapm_to_component(w->dapm);
  544. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  545. int hph_mode = wcd937x->hph_mode;
  546. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  547. w->name, event);
  548. switch (event) {
  549. case SND_SOC_DAPM_PRE_PMU:
  550. wcd937x_rx_clk_enable(component);
  551. snd_soc_component_update_bits(component,
  552. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  553. snd_soc_component_update_bits(component,
  554. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  555. snd_soc_component_update_bits(component,
  556. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  557. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  558. break;
  559. case SND_SOC_DAPM_POST_PMU:
  560. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  561. snd_soc_component_update_bits(component,
  562. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  563. 0x0F, 0x02);
  564. else if (hph_mode == CLS_H_LOHIFI)
  565. snd_soc_component_update_bits(component,
  566. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  567. 0x0F, 0x06);
  568. if (wcd937x->comp2_enable) {
  569. snd_soc_component_update_bits(component,
  570. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  571. 0x01, 0x01);
  572. snd_soc_component_update_bits(component,
  573. WCD937X_HPH_R_EN, 0x20, 0x00);
  574. if (wcd937x->comp1_enable) {
  575. snd_soc_component_update_bits(component,
  576. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  577. 0x02, 0x02);
  578. snd_soc_component_update_bits(component,
  579. WCD937X_HPH_L_EN, 0x20, 0x00);
  580. }
  581. /*
  582. * 5ms sleep is required after COMP is enabled as per
  583. * HW requirement
  584. */
  585. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  586. usleep_range(5000, 5100);
  587. clear_bit(HPH_COMP_DELAY,
  588. &wcd937x->status_mask);
  589. }
  590. } else {
  591. snd_soc_component_update_bits(component,
  592. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  593. 0x01, 0x00);
  594. snd_soc_component_update_bits(component,
  595. WCD937X_HPH_R_EN, 0x20, 0x20);
  596. }
  597. snd_soc_component_update_bits(component,
  598. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  599. break;
  600. case SND_SOC_DAPM_POST_PMD:
  601. snd_soc_component_update_bits(component,
  602. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  603. 0x0F, 0x01);
  604. break;
  605. }
  606. return 0;
  607. }
  608. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  609. struct snd_kcontrol *kcontrol,
  610. int event)
  611. {
  612. struct snd_soc_component *component =
  613. snd_soc_dapm_to_component(w->dapm);
  614. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  615. int hph_mode = wcd937x->hph_mode;
  616. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  617. w->name, event);
  618. switch (event) {
  619. case SND_SOC_DAPM_PRE_PMU:
  620. wcd937x_rx_clk_enable(component);
  621. snd_soc_component_update_bits(component,
  622. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  623. 0x04, 0x04);
  624. snd_soc_component_update_bits(component,
  625. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  626. 0x01, 0x01);
  627. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  628. snd_soc_component_update_bits(component,
  629. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  630. 0x0F, 0x02);
  631. else if (hph_mode == CLS_H_LOHIFI)
  632. snd_soc_component_update_bits(component,
  633. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  634. 0x0F, 0x06);
  635. if (wcd937x->comp1_enable)
  636. snd_soc_component_update_bits(component,
  637. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  638. 0x02, 0x02);
  639. usleep_range(5000, 5010);
  640. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  641. 0x04, 0x00);
  642. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  643. WCD_CLSH_EVENT_PRE_DAC,
  644. WCD_CLSH_STATE_EAR,
  645. hph_mode);
  646. break;
  647. case SND_SOC_DAPM_POST_PMD:
  648. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  649. hph_mode == CLS_H_HIFI)
  650. snd_soc_component_update_bits(component,
  651. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  652. 0x0F, 0x01);
  653. if (wcd937x->comp1_enable)
  654. snd_soc_component_update_bits(component,
  655. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  656. 0x02, 0x00);
  657. break;
  658. };
  659. return 0;
  660. }
  661. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  662. struct snd_kcontrol *kcontrol,
  663. int event)
  664. {
  665. struct snd_soc_component *component =
  666. snd_soc_dapm_to_component(w->dapm);
  667. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  668. int hph_mode = wcd937x->hph_mode;
  669. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  670. w->name, event);
  671. switch (event) {
  672. case SND_SOC_DAPM_PRE_PMU:
  673. wcd937x_rx_clk_enable(component);
  674. snd_soc_component_update_bits(component,
  675. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  676. 0x04, 0x04);
  677. snd_soc_component_update_bits(component,
  678. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  679. 0x04, 0x04);
  680. snd_soc_component_update_bits(component,
  681. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  682. 0x01, 0x01);
  683. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  684. WCD_CLSH_EVENT_PRE_DAC,
  685. WCD_CLSH_STATE_AUX,
  686. hph_mode);
  687. break;
  688. case SND_SOC_DAPM_POST_PMD:
  689. snd_soc_component_update_bits(component,
  690. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  691. 0x04, 0x00);
  692. break;
  693. };
  694. return 0;
  695. }
  696. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  697. struct snd_kcontrol *kcontrol,
  698. int event)
  699. {
  700. struct snd_soc_component *component =
  701. snd_soc_dapm_to_component(w->dapm);
  702. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  703. int ret = 0;
  704. int hph_mode = wcd937x->hph_mode;
  705. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  706. w->name, event);
  707. switch (event) {
  708. case SND_SOC_DAPM_PRE_PMU:
  709. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  710. wcd937x->rx_swr_dev->dev_num,
  711. true);
  712. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  713. WCD_CLSH_EVENT_PRE_DAC,
  714. WCD_CLSH_STATE_HPHR,
  715. hph_mode);
  716. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  717. 0x10, 0x10);
  718. usleep_range(100, 110);
  719. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  720. snd_soc_component_update_bits(component,
  721. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  722. break;
  723. case SND_SOC_DAPM_POST_PMU:
  724. /*
  725. * 7ms sleep is required after PA is enabled as per
  726. * HW requirement. If compander is disabled, then
  727. * 20ms delay is required.
  728. */
  729. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  730. if (!wcd937x->comp2_enable)
  731. usleep_range(20000, 20100);
  732. else
  733. usleep_range(7000, 7100);
  734. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  735. }
  736. snd_soc_component_update_bits(component,
  737. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  738. 0x02, 0x02);
  739. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  740. snd_soc_component_update_bits(component,
  741. WCD937X_ANA_RX_SUPPLIES,
  742. 0x02, 0x02);
  743. if (wcd937x->update_wcd_event)
  744. wcd937x->update_wcd_event(wcd937x->handle,
  745. SLV_BOLERO_EVT_RX_MUTE,
  746. (WCD_RX2 << 0x10));
  747. wcd_enable_irq(&wcd937x->irq_info,
  748. WCD937X_IRQ_HPHR_PDM_WD_INT);
  749. break;
  750. case SND_SOC_DAPM_PRE_PMD:
  751. wcd_disable_irq(&wcd937x->irq_info,
  752. WCD937X_IRQ_HPHR_PDM_WD_INT);
  753. if (wcd937x->update_wcd_event)
  754. wcd937x->update_wcd_event(wcd937x->handle,
  755. SLV_BOLERO_EVT_RX_MUTE,
  756. (WCD_RX2 << 0x10 | 0x1));
  757. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  758. WCD_EVENT_PRE_HPHR_PA_OFF,
  759. &wcd937x->mbhc->wcd_mbhc);
  760. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  761. break;
  762. case SND_SOC_DAPM_POST_PMD:
  763. /*
  764. * 7ms sleep is required after PA is disabled as per
  765. * HW requirement. If compander is disabled, then
  766. * 20ms delay is required.
  767. */
  768. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  769. if (!wcd937x->comp2_enable)
  770. usleep_range(20000, 20100);
  771. else
  772. usleep_range(7000, 7100);
  773. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  774. }
  775. snd_soc_component_update_bits(component,
  776. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  777. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  778. WCD_EVENT_POST_HPHR_PA_OFF,
  779. &wcd937x->mbhc->wcd_mbhc);
  780. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  781. 0x10, 0x00);
  782. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  783. WCD_CLSH_EVENT_POST_PA,
  784. WCD_CLSH_STATE_HPHR,
  785. hph_mode);
  786. break;
  787. };
  788. return ret;
  789. }
  790. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  791. struct snd_kcontrol *kcontrol,
  792. int event)
  793. {
  794. struct snd_soc_component *component =
  795. snd_soc_dapm_to_component(w->dapm);
  796. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  797. int ret = 0;
  798. int hph_mode = wcd937x->hph_mode;
  799. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  800. w->name, event);
  801. switch (event) {
  802. case SND_SOC_DAPM_PRE_PMU:
  803. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  804. wcd937x->rx_swr_dev->dev_num,
  805. true);
  806. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  807. WCD_CLSH_EVENT_PRE_DAC,
  808. WCD_CLSH_STATE_HPHL,
  809. hph_mode);
  810. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  811. 0x20, 0x20);
  812. usleep_range(100, 110);
  813. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  814. snd_soc_component_update_bits(component,
  815. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  816. break;
  817. case SND_SOC_DAPM_POST_PMU:
  818. /*
  819. * 7ms sleep is required after PA is enabled as per
  820. * HW requirement. If compander is disabled, then
  821. * 20ms delay is required.
  822. */
  823. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  824. if (!wcd937x->comp1_enable)
  825. usleep_range(20000, 20100);
  826. else
  827. usleep_range(7000, 7100);
  828. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  829. }
  830. snd_soc_component_update_bits(component,
  831. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  832. 0x02, 0x02);
  833. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  834. snd_soc_component_update_bits(component,
  835. WCD937X_ANA_RX_SUPPLIES,
  836. 0x02, 0x02);
  837. if (wcd937x->update_wcd_event)
  838. wcd937x->update_wcd_event(wcd937x->handle,
  839. SLV_BOLERO_EVT_RX_MUTE,
  840. (WCD_RX1 << 0x10));
  841. wcd_enable_irq(&wcd937x->irq_info,
  842. WCD937X_IRQ_HPHL_PDM_WD_INT);
  843. break;
  844. case SND_SOC_DAPM_PRE_PMD:
  845. wcd_disable_irq(&wcd937x->irq_info,
  846. WCD937X_IRQ_HPHL_PDM_WD_INT);
  847. if (wcd937x->update_wcd_event)
  848. wcd937x->update_wcd_event(wcd937x->handle,
  849. SLV_BOLERO_EVT_RX_MUTE,
  850. (WCD_RX1 << 0x10 | 0x1));
  851. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  852. WCD_EVENT_PRE_HPHL_PA_OFF,
  853. &wcd937x->mbhc->wcd_mbhc);
  854. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  855. break;
  856. case SND_SOC_DAPM_POST_PMD:
  857. /*
  858. * 7ms sleep is required after PA is disabled as per
  859. * HW requirement. If compander is disabled, then
  860. * 20ms delay is required.
  861. */
  862. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  863. if (!wcd937x->comp1_enable)
  864. usleep_range(20000, 20100);
  865. else
  866. usleep_range(7000, 7100);
  867. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  868. }
  869. snd_soc_component_update_bits(component,
  870. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  871. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  872. WCD_EVENT_POST_HPHL_PA_OFF,
  873. &wcd937x->mbhc->wcd_mbhc);
  874. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  875. 0x20, 0x00);
  876. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  877. WCD_CLSH_EVENT_POST_PA,
  878. WCD_CLSH_STATE_HPHL,
  879. hph_mode);
  880. break;
  881. };
  882. return ret;
  883. }
  884. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  885. struct snd_kcontrol *kcontrol,
  886. int event)
  887. {
  888. struct snd_soc_component *component =
  889. snd_soc_dapm_to_component(w->dapm);
  890. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  891. int hph_mode = wcd937x->hph_mode;
  892. int ret = 0;
  893. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  894. w->name, event);
  895. switch (event) {
  896. case SND_SOC_DAPM_PRE_PMU:
  897. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  898. wcd937x->rx_swr_dev->dev_num,
  899. true);
  900. snd_soc_component_update_bits(component,
  901. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  902. break;
  903. case SND_SOC_DAPM_POST_PMU:
  904. usleep_range(1000, 1010);
  905. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  906. snd_soc_component_update_bits(component,
  907. WCD937X_ANA_RX_SUPPLIES,
  908. 0x02, 0x02);
  909. if (wcd937x->update_wcd_event)
  910. wcd937x->update_wcd_event(wcd937x->handle,
  911. SLV_BOLERO_EVT_RX_MUTE,
  912. (WCD_RX3 << 0x10));
  913. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  914. break;
  915. case SND_SOC_DAPM_PRE_PMD:
  916. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  917. if (wcd937x->update_wcd_event)
  918. wcd937x->update_wcd_event(wcd937x->handle,
  919. SLV_BOLERO_EVT_RX_MUTE,
  920. (WCD_RX3 << 0x10 | 0x1));
  921. break;
  922. case SND_SOC_DAPM_POST_PMD:
  923. /* Add delay as per hw requirement */
  924. usleep_range(2000, 2010);
  925. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  926. WCD_CLSH_EVENT_POST_PA,
  927. WCD_CLSH_STATE_AUX,
  928. hph_mode);
  929. snd_soc_component_update_bits(component,
  930. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  931. break;
  932. };
  933. return ret;
  934. }
  935. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  936. struct snd_kcontrol *kcontrol,
  937. int event)
  938. {
  939. struct snd_soc_component *component =
  940. snd_soc_dapm_to_component(w->dapm);
  941. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  942. int hph_mode = wcd937x->hph_mode;
  943. int ret = 0;
  944. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  945. w->name, event);
  946. switch (event) {
  947. case SND_SOC_DAPM_PRE_PMU:
  948. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  949. wcd937x->rx_swr_dev->dev_num,
  950. true);
  951. /*
  952. * Enable watchdog interrupt for HPHL or AUX
  953. * depending on mux value
  954. */
  955. wcd937x->ear_rx_path =
  956. snd_soc_component_read(
  957. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  958. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  959. snd_soc_component_update_bits(component,
  960. WCD937X_DIGITAL_PDM_WD_CTL2,
  961. 0x05, 0x05);
  962. else
  963. snd_soc_component_update_bits(component,
  964. WCD937X_DIGITAL_PDM_WD_CTL0,
  965. 0x17, 0x13);
  966. if (!wcd937x->comp1_enable)
  967. snd_soc_component_update_bits(component,
  968. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  969. break;
  970. case SND_SOC_DAPM_POST_PMU:
  971. usleep_range(6000, 6010);
  972. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  973. snd_soc_component_update_bits(component,
  974. WCD937X_ANA_RX_SUPPLIES,
  975. 0x02, 0x02);
  976. if (wcd937x->update_wcd_event)
  977. wcd937x->update_wcd_event(wcd937x->handle,
  978. SLV_BOLERO_EVT_RX_MUTE,
  979. (WCD_RX1 << 0x10));
  980. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  981. wcd_enable_irq(&wcd937x->irq_info,
  982. WCD937X_IRQ_AUX_PDM_WD_INT);
  983. else
  984. wcd_enable_irq(&wcd937x->irq_info,
  985. WCD937X_IRQ_HPHL_PDM_WD_INT);
  986. break;
  987. case SND_SOC_DAPM_PRE_PMD:
  988. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  989. wcd_disable_irq(&wcd937x->irq_info,
  990. WCD937X_IRQ_AUX_PDM_WD_INT);
  991. else
  992. wcd_disable_irq(&wcd937x->irq_info,
  993. WCD937X_IRQ_HPHL_PDM_WD_INT);
  994. if (wcd937x->update_wcd_event)
  995. wcd937x->update_wcd_event(wcd937x->handle,
  996. SLV_BOLERO_EVT_RX_MUTE,
  997. (WCD_RX1 << 0x10 | 0x1));
  998. break;
  999. case SND_SOC_DAPM_POST_PMD:
  1000. if (!wcd937x->comp1_enable)
  1001. snd_soc_component_update_bits(component,
  1002. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1003. usleep_range(7000, 7010);
  1004. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  1005. WCD_CLSH_EVENT_POST_PA,
  1006. WCD_CLSH_STATE_EAR,
  1007. hph_mode);
  1008. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1009. 0x04, 0x04);
  1010. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1011. snd_soc_component_update_bits(component,
  1012. WCD937X_DIGITAL_PDM_WD_CTL2,
  1013. 0x05, 0x00);
  1014. else
  1015. snd_soc_component_update_bits(component,
  1016. WCD937X_DIGITAL_PDM_WD_CTL0,
  1017. 0x17, 0x00);
  1018. break;
  1019. };
  1020. return ret;
  1021. }
  1022. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1023. struct snd_kcontrol *kcontrol,
  1024. int event)
  1025. {
  1026. struct snd_soc_component *component =
  1027. snd_soc_dapm_to_component(w->dapm);
  1028. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1029. int mode = wcd937x->hph_mode;
  1030. int ret = 0;
  1031. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1032. w->name, event);
  1033. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1034. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1035. wcd937x_rx_connect_port(component, CLSH,
  1036. SND_SOC_DAPM_EVENT_ON(event));
  1037. }
  1038. if (SND_SOC_DAPM_EVENT_OFF(event))
  1039. ret = swr_slvdev_datapath_control(
  1040. wcd937x->rx_swr_dev,
  1041. wcd937x->rx_swr_dev->dev_num,
  1042. false);
  1043. return ret;
  1044. }
  1045. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1046. struct snd_kcontrol *kcontrol,
  1047. int event)
  1048. {
  1049. struct snd_soc_component *component =
  1050. snd_soc_dapm_to_component(w->dapm);
  1051. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1052. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1053. w->name, event);
  1054. switch (event) {
  1055. case SND_SOC_DAPM_PRE_PMU:
  1056. wcd937x_rx_connect_port(component, HPH_L, true);
  1057. if (wcd937x->comp1_enable)
  1058. wcd937x_rx_connect_port(component, COMP_L, true);
  1059. break;
  1060. case SND_SOC_DAPM_POST_PMD:
  1061. wcd937x_rx_connect_port(component, HPH_L, false);
  1062. if (wcd937x->comp1_enable)
  1063. wcd937x_rx_connect_port(component, COMP_L, false);
  1064. wcd937x_rx_clk_disable(component);
  1065. snd_soc_component_update_bits(component,
  1066. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1067. 0x01, 0x00);
  1068. break;
  1069. };
  1070. return 0;
  1071. }
  1072. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1073. struct snd_kcontrol *kcontrol, int event)
  1074. {
  1075. struct snd_soc_component *component =
  1076. snd_soc_dapm_to_component(w->dapm);
  1077. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1078. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1079. w->name, event);
  1080. switch (event) {
  1081. case SND_SOC_DAPM_PRE_PMU:
  1082. wcd937x_rx_connect_port(component, HPH_R, true);
  1083. if (wcd937x->comp2_enable)
  1084. wcd937x_rx_connect_port(component, COMP_R, true);
  1085. break;
  1086. case SND_SOC_DAPM_POST_PMD:
  1087. wcd937x_rx_connect_port(component, HPH_R, false);
  1088. if (wcd937x->comp2_enable)
  1089. wcd937x_rx_connect_port(component, COMP_R, false);
  1090. wcd937x_rx_clk_disable(component);
  1091. snd_soc_component_update_bits(component,
  1092. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1093. 0x02, 0x00);
  1094. break;
  1095. };
  1096. return 0;
  1097. }
  1098. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1099. struct snd_kcontrol *kcontrol,
  1100. int event)
  1101. {
  1102. struct snd_soc_component *component =
  1103. snd_soc_dapm_to_component(w->dapm);
  1104. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1105. w->name, event);
  1106. switch (event) {
  1107. case SND_SOC_DAPM_PRE_PMU:
  1108. wcd937x_rx_connect_port(component, LO, true);
  1109. break;
  1110. case SND_SOC_DAPM_POST_PMD:
  1111. wcd937x_rx_connect_port(component, LO, false);
  1112. usleep_range(6000, 6010);
  1113. wcd937x_rx_clk_disable(component);
  1114. snd_soc_component_update_bits(component,
  1115. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1116. break;
  1117. }
  1118. return 0;
  1119. }
  1120. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1121. struct snd_kcontrol *kcontrol,
  1122. int event)
  1123. {
  1124. struct snd_soc_component *component =
  1125. snd_soc_dapm_to_component(w->dapm);
  1126. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1127. u16 dmic_clk_reg;
  1128. s32 *dmic_clk_cnt;
  1129. unsigned int dmic;
  1130. char *wname;
  1131. int ret = 0;
  1132. wname = strpbrk(w->name, "012345");
  1133. if (!wname) {
  1134. dev_err(component->dev, "%s: widget not found\n", __func__);
  1135. return -EINVAL;
  1136. }
  1137. ret = kstrtouint(wname, 10, &dmic);
  1138. if (ret < 0) {
  1139. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1140. __func__);
  1141. return -EINVAL;
  1142. }
  1143. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1144. w->name, event);
  1145. switch (dmic) {
  1146. case 0:
  1147. case 1:
  1148. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1149. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1150. break;
  1151. case 2:
  1152. case 3:
  1153. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1154. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1155. break;
  1156. case 4:
  1157. case 5:
  1158. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1159. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1160. break;
  1161. default:
  1162. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1163. __func__);
  1164. return -EINVAL;
  1165. };
  1166. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1167. __func__, event, dmic, *dmic_clk_cnt);
  1168. switch (event) {
  1169. case SND_SOC_DAPM_PRE_PMU:
  1170. snd_soc_component_update_bits(component,
  1171. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1172. snd_soc_component_update_bits(component,
  1173. dmic_clk_reg, 0x07, 0x02);
  1174. snd_soc_component_update_bits(component,
  1175. dmic_clk_reg, 0x08, 0x08);
  1176. snd_soc_component_update_bits(component,
  1177. dmic_clk_reg, 0x70, 0x20);
  1178. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1179. wcd937x->tx_swr_dev->dev_num,
  1180. true);
  1181. break;
  1182. case SND_SOC_DAPM_POST_PMD:
  1183. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1184. break;
  1185. };
  1186. return 0;
  1187. }
  1188. /*
  1189. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1190. * @micb_mv: micbias in mv
  1191. *
  1192. * return register value converted
  1193. */
  1194. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1195. {
  1196. /* min micbias voltage is 1V and maximum is 2.85V */
  1197. if (micb_mv < 1000 || micb_mv > 2850) {
  1198. pr_err("%s: unsupported micbias voltage\n", __func__);
  1199. return -EINVAL;
  1200. }
  1201. return (micb_mv - 1000) / 50;
  1202. }
  1203. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1204. /*
  1205. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1206. * @component: handle to snd_soc_component *
  1207. * @req_volt: micbias voltage to be set
  1208. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1209. *
  1210. * return 0 if adjustment is success or error code in case of failure
  1211. */
  1212. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1213. int req_volt, int micb_num)
  1214. {
  1215. struct wcd937x_priv *wcd937x =
  1216. snd_soc_component_get_drvdata(component);
  1217. int cur_vout_ctl, req_vout_ctl;
  1218. int micb_reg, micb_val, micb_en;
  1219. int ret = 0;
  1220. switch (micb_num) {
  1221. case MIC_BIAS_1:
  1222. micb_reg = WCD937X_ANA_MICB1;
  1223. break;
  1224. case MIC_BIAS_2:
  1225. micb_reg = WCD937X_ANA_MICB2;
  1226. break;
  1227. case MIC_BIAS_3:
  1228. micb_reg = WCD937X_ANA_MICB3;
  1229. break;
  1230. default:
  1231. return -EINVAL;
  1232. }
  1233. mutex_lock(&wcd937x->micb_lock);
  1234. /*
  1235. * If requested micbias voltage is same as current micbias
  1236. * voltage, then just return. Otherwise, adjust voltage as
  1237. * per requested value. If micbias is already enabled, then
  1238. * to avoid slow micbias ramp-up or down enable pull-up
  1239. * momentarily, change the micbias value and then re-enable
  1240. * micbias.
  1241. */
  1242. micb_val = snd_soc_component_read(component, micb_reg);
  1243. micb_en = (micb_val & 0xC0) >> 6;
  1244. cur_vout_ctl = micb_val & 0x3F;
  1245. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1246. if (req_vout_ctl < 0) {
  1247. ret = -EINVAL;
  1248. goto exit;
  1249. }
  1250. if (cur_vout_ctl == req_vout_ctl) {
  1251. ret = 0;
  1252. goto exit;
  1253. }
  1254. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1255. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1256. req_volt, micb_en);
  1257. if (micb_en == 0x1)
  1258. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1259. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1260. if (micb_en == 0x1) {
  1261. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1262. /*
  1263. * Add 2ms delay as per HW requirement after enabling
  1264. * micbias
  1265. */
  1266. usleep_range(2000, 2100);
  1267. }
  1268. exit:
  1269. mutex_unlock(&wcd937x->micb_lock);
  1270. return ret;
  1271. }
  1272. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1273. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1274. struct snd_kcontrol *kcontrol,
  1275. int event)
  1276. {
  1277. struct snd_soc_component *component =
  1278. snd_soc_dapm_to_component(w->dapm);
  1279. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1280. int ret = 0;
  1281. switch (event) {
  1282. case SND_SOC_DAPM_PRE_PMU:
  1283. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1284. /* Enable BCS for Headset mic */
  1285. if (w->shift == 1 && !(snd_soc_component_read(component,
  1286. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1287. wcd937x_tx_connect_port(component, MBHC, true);
  1288. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1289. }
  1290. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1291. } else {
  1292. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1293. }
  1294. break;
  1295. case SND_SOC_DAPM_POST_PMD:
  1296. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1297. wcd937x->tx_swr_dev->dev_num,
  1298. false);
  1299. break;
  1300. };
  1301. return ret;
  1302. }
  1303. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1304. struct snd_kcontrol *kcontrol,
  1305. int event){
  1306. struct snd_soc_component *component =
  1307. snd_soc_dapm_to_component(w->dapm);
  1308. struct wcd937x_priv *wcd937x =
  1309. snd_soc_component_get_drvdata(component);
  1310. int ret = 0;
  1311. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1312. w->name, event);
  1313. switch (event) {
  1314. case SND_SOC_DAPM_PRE_PMU:
  1315. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1316. wcd937x->ana_clk_count++;
  1317. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1318. snd_soc_component_update_bits(component,
  1319. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1320. snd_soc_component_update_bits(component,
  1321. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1322. snd_soc_component_update_bits(component,
  1323. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1324. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1325. wcd937x->tx_swr_dev->dev_num,
  1326. true);
  1327. break;
  1328. case SND_SOC_DAPM_POST_PMD:
  1329. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1330. if (w->shift == 1 &&
  1331. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1332. wcd937x_tx_connect_port(component, MBHC, false);
  1333. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1334. }
  1335. snd_soc_component_update_bits(component,
  1336. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1337. break;
  1338. };
  1339. return ret;
  1340. }
  1341. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1342. struct snd_kcontrol *kcontrol, int event)
  1343. {
  1344. struct snd_soc_component *component =
  1345. snd_soc_dapm_to_component(w->dapm);
  1346. struct wcd937x_priv *wcd937x =
  1347. snd_soc_component_get_drvdata(component);
  1348. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1349. w->name, event);
  1350. switch (event) {
  1351. case SND_SOC_DAPM_PRE_PMU:
  1352. snd_soc_component_update_bits(component,
  1353. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1354. snd_soc_component_update_bits(component,
  1355. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1356. snd_soc_component_update_bits(component,
  1357. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1358. snd_soc_component_update_bits(component,
  1359. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1360. snd_soc_component_update_bits(component,
  1361. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1362. snd_soc_component_update_bits(component,
  1363. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1364. snd_soc_component_update_bits(component,
  1365. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1366. snd_soc_component_update_bits(component,
  1367. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1368. snd_soc_component_update_bits(component,
  1369. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1370. break;
  1371. case SND_SOC_DAPM_POST_PMD:
  1372. snd_soc_component_update_bits(component,
  1373. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1374. snd_soc_component_update_bits(component,
  1375. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1376. snd_soc_component_update_bits(component,
  1377. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1378. snd_soc_component_update_bits(component,
  1379. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1380. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1381. wcd937x->ana_clk_count--;
  1382. if (wcd937x->ana_clk_count <= 0) {
  1383. snd_soc_component_update_bits(component,
  1384. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1385. wcd937x->ana_clk_count = 0;
  1386. }
  1387. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1388. snd_soc_component_update_bits(component,
  1389. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1390. break;
  1391. };
  1392. return 0;
  1393. }
  1394. int wcd937x_micbias_control(struct snd_soc_component *component,
  1395. int micb_num, int req, bool is_dapm)
  1396. {
  1397. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1398. int micb_index = micb_num - 1;
  1399. u16 micb_reg;
  1400. int pre_off_event = 0, post_off_event = 0;
  1401. int post_on_event = 0, post_dapm_off = 0;
  1402. int post_dapm_on = 0;
  1403. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1404. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1405. __func__, micb_index);
  1406. return -EINVAL;
  1407. }
  1408. switch (micb_num) {
  1409. case MIC_BIAS_1:
  1410. micb_reg = WCD937X_ANA_MICB1;
  1411. break;
  1412. case MIC_BIAS_2:
  1413. micb_reg = WCD937X_ANA_MICB2;
  1414. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1415. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1416. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1417. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1418. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1419. break;
  1420. case MIC_BIAS_3:
  1421. micb_reg = WCD937X_ANA_MICB3;
  1422. break;
  1423. default:
  1424. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1425. __func__, micb_num);
  1426. return -EINVAL;
  1427. };
  1428. mutex_lock(&wcd937x->micb_lock);
  1429. switch (req) {
  1430. case MICB_PULLUP_ENABLE:
  1431. wcd937x->pullup_ref[micb_index]++;
  1432. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1433. (wcd937x->micb_ref[micb_index] == 0))
  1434. snd_soc_component_update_bits(component, micb_reg,
  1435. 0xC0, 0x80);
  1436. break;
  1437. case MICB_PULLUP_DISABLE:
  1438. if (wcd937x->pullup_ref[micb_index] > 0)
  1439. wcd937x->pullup_ref[micb_index]--;
  1440. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1441. (wcd937x->micb_ref[micb_index] == 0))
  1442. snd_soc_component_update_bits(component, micb_reg,
  1443. 0xC0, 0x00);
  1444. break;
  1445. case MICB_ENABLE:
  1446. wcd937x->micb_ref[micb_index]++;
  1447. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1448. wcd937x->ana_clk_count++;
  1449. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1450. if (wcd937x->micb_ref[micb_index] == 1) {
  1451. snd_soc_component_update_bits(component,
  1452. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1453. snd_soc_component_update_bits(component,
  1454. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1455. snd_soc_component_update_bits(component,
  1456. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1457. snd_soc_component_update_bits(component,
  1458. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1459. snd_soc_component_update_bits(component,
  1460. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1461. snd_soc_component_update_bits(component,
  1462. micb_reg, 0xC0, 0x40);
  1463. if (post_on_event)
  1464. blocking_notifier_call_chain(
  1465. &wcd937x->mbhc->notifier, post_on_event,
  1466. &wcd937x->mbhc->wcd_mbhc);
  1467. }
  1468. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1469. blocking_notifier_call_chain(
  1470. &wcd937x->mbhc->notifier, post_dapm_on,
  1471. &wcd937x->mbhc->wcd_mbhc);
  1472. break;
  1473. case MICB_DISABLE:
  1474. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1475. wcd937x->ana_clk_count--;
  1476. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1477. if (wcd937x->micb_ref[micb_index] > 0)
  1478. wcd937x->micb_ref[micb_index]--;
  1479. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1480. (wcd937x->pullup_ref[micb_index] > 0))
  1481. snd_soc_component_update_bits(component, micb_reg,
  1482. 0xC0, 0x80);
  1483. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1484. (wcd937x->pullup_ref[micb_index] == 0)) {
  1485. if (pre_off_event && wcd937x->mbhc)
  1486. blocking_notifier_call_chain(
  1487. &wcd937x->mbhc->notifier, pre_off_event,
  1488. &wcd937x->mbhc->wcd_mbhc);
  1489. snd_soc_component_update_bits(component, micb_reg,
  1490. 0xC0, 0x00);
  1491. if (post_off_event && wcd937x->mbhc)
  1492. blocking_notifier_call_chain(
  1493. &wcd937x->mbhc->notifier,
  1494. post_off_event,
  1495. &wcd937x->mbhc->wcd_mbhc);
  1496. }
  1497. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1498. if (wcd937x->ana_clk_count <= 0) {
  1499. snd_soc_component_update_bits(component,
  1500. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1501. 0x10, 0x00);
  1502. wcd937x->ana_clk_count = 0;
  1503. }
  1504. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1505. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1506. blocking_notifier_call_chain(
  1507. &wcd937x->mbhc->notifier, post_dapm_off,
  1508. &wcd937x->mbhc->wcd_mbhc);
  1509. break;
  1510. };
  1511. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1512. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1513. wcd937x->pullup_ref[micb_index]);
  1514. mutex_unlock(&wcd937x->micb_lock);
  1515. return 0;
  1516. }
  1517. EXPORT_SYMBOL(wcd937x_micbias_control);
  1518. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1519. bool bcs_disable)
  1520. {
  1521. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1522. if (wcd937x->update_wcd_event) {
  1523. if (bcs_disable)
  1524. wcd937x->update_wcd_event(wcd937x->handle,
  1525. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1526. else
  1527. wcd937x->update_wcd_event(wcd937x->handle,
  1528. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1529. }
  1530. }
  1531. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1532. {
  1533. int ret = 0;
  1534. uint8_t devnum = 0;
  1535. int num_retry = NUM_ATTEMPTS;
  1536. do {
  1537. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1538. if (ret) {
  1539. dev_err(&swr_dev->dev,
  1540. "%s get devnum %d for dev addr %lx failed\n",
  1541. __func__, devnum, swr_dev->addr);
  1542. /* retry after 1ms */
  1543. usleep_range(1000, 1010);
  1544. }
  1545. } while (ret && --num_retry);
  1546. swr_dev->dev_num = devnum;
  1547. return 0;
  1548. }
  1549. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1550. struct wcd_mbhc_config *mbhc_cfg)
  1551. {
  1552. if (mbhc_cfg->enable_usbc_analog) {
  1553. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1554. & 0x20))
  1555. return true;
  1556. }
  1557. return false;
  1558. }
  1559. static int wcd937x_event_notify(struct notifier_block *block,
  1560. unsigned long val,
  1561. void *data)
  1562. {
  1563. u16 event = (val & 0xffff);
  1564. u16 amic = (val >> 0x10);
  1565. u16 mask = 0x40, reg = 0x0;
  1566. int ret = 0;
  1567. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1568. struct snd_soc_component *component = wcd937x->component;
  1569. struct wcd_mbhc *mbhc;
  1570. switch (event) {
  1571. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1572. if (amic == 0x1 || amic == 0x2)
  1573. reg = WCD937X_ANA_TX_CH2;
  1574. else if (amic == 0x3)
  1575. reg = WCD937X_ANA_TX_CH3_HPF;
  1576. else
  1577. return 0;
  1578. if (amic == 0x2)
  1579. mask = 0x20;
  1580. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1581. break;
  1582. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1583. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1584. 0xC0, 0x00);
  1585. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1586. 0x80, 0x00);
  1587. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1588. 0x80, 0x00);
  1589. break;
  1590. case BOLERO_SLV_EVT_SSR_DOWN:
  1591. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1592. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1593. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1594. mbhc->mbhc_cfg);
  1595. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1596. wcd937x_reset_low(wcd937x->dev);
  1597. break;
  1598. case BOLERO_SLV_EVT_SSR_UP:
  1599. wcd937x_reset(wcd937x->dev);
  1600. /* allow reset to take effect */
  1601. usleep_range(10000, 10010);
  1602. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1603. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1604. wcd937x_init_reg(component);
  1605. regcache_mark_dirty(wcd937x->regmap);
  1606. regcache_sync(wcd937x->regmap);
  1607. /* Initialize MBHC module */
  1608. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1609. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1610. if (ret) {
  1611. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1612. __func__);
  1613. } else {
  1614. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1615. if (wcd937x->usbc_hs_status)
  1616. mdelay(500);
  1617. }
  1618. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1619. break;
  1620. default:
  1621. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1622. event);
  1623. break;
  1624. }
  1625. return 0;
  1626. }
  1627. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1628. int event)
  1629. {
  1630. struct snd_soc_component *component =
  1631. snd_soc_dapm_to_component(w->dapm);
  1632. int micb_num;
  1633. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1634. __func__, w->name, event);
  1635. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1636. micb_num = MIC_BIAS_1;
  1637. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1638. micb_num = MIC_BIAS_2;
  1639. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1640. micb_num = MIC_BIAS_3;
  1641. else
  1642. return -EINVAL;
  1643. switch (event) {
  1644. case SND_SOC_DAPM_PRE_PMU:
  1645. wcd937x_micbias_control(component, micb_num,
  1646. MICB_ENABLE, true);
  1647. break;
  1648. case SND_SOC_DAPM_POST_PMU:
  1649. usleep_range(1000, 1100);
  1650. break;
  1651. case SND_SOC_DAPM_POST_PMD:
  1652. wcd937x_micbias_control(component, micb_num,
  1653. MICB_DISABLE, true);
  1654. break;
  1655. };
  1656. return 0;
  1657. }
  1658. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1659. struct snd_kcontrol *kcontrol,
  1660. int event)
  1661. {
  1662. return __wcd937x_codec_enable_micbias(w, event);
  1663. }
  1664. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1665. int event)
  1666. {
  1667. struct snd_soc_component *component =
  1668. snd_soc_dapm_to_component(w->dapm);
  1669. int micb_num;
  1670. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1671. __func__, w->name, event);
  1672. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1673. micb_num = MIC_BIAS_1;
  1674. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1675. micb_num = MIC_BIAS_2;
  1676. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1677. micb_num = MIC_BIAS_3;
  1678. else
  1679. return -EINVAL;
  1680. switch (event) {
  1681. case SND_SOC_DAPM_PRE_PMU:
  1682. wcd937x_micbias_control(component, micb_num,
  1683. MICB_PULLUP_ENABLE, true);
  1684. break;
  1685. case SND_SOC_DAPM_POST_PMU:
  1686. /* 1 msec delay as per HW requirement */
  1687. usleep_range(1000, 1100);
  1688. break;
  1689. case SND_SOC_DAPM_POST_PMD:
  1690. wcd937x_micbias_control(component, micb_num,
  1691. MICB_PULLUP_DISABLE, true);
  1692. break;
  1693. };
  1694. return 0;
  1695. }
  1696. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1697. struct snd_kcontrol *kcontrol,
  1698. int event)
  1699. {
  1700. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1701. }
  1702. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1703. struct snd_ctl_elem_value *ucontrol)
  1704. {
  1705. struct snd_soc_component *component =
  1706. snd_soc_kcontrol_component(kcontrol);
  1707. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1708. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1709. return 0;
  1710. }
  1711. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1712. struct snd_ctl_elem_value *ucontrol)
  1713. {
  1714. struct snd_soc_component *component =
  1715. snd_soc_kcontrol_component(kcontrol);
  1716. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1717. u32 mode_val;
  1718. mode_val = ucontrol->value.enumerated.item[0];
  1719. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1720. if (mode_val == 0) {
  1721. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1722. __func__);
  1723. mode_val = 3; /* enum will be updated later */
  1724. }
  1725. wcd937x->hph_mode = mode_val;
  1726. return 0;
  1727. }
  1728. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1729. struct snd_ctl_elem_value *ucontrol)
  1730. {
  1731. struct snd_soc_component *component =
  1732. snd_soc_kcontrol_component(kcontrol);
  1733. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1734. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1735. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1736. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1737. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1738. return 0;
  1739. }
  1740. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1741. struct snd_ctl_elem_value *ucontrol)
  1742. {
  1743. struct snd_soc_component *component =
  1744. snd_soc_kcontrol_component(kcontrol);
  1745. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1746. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1747. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1748. __func__, pwr_level);
  1749. if (strnstr(kcontrol->id.name, "CH1",
  1750. sizeof(kcontrol->id.name))) {
  1751. snd_soc_component_update_bits(component,
  1752. WCD937X_ANA_TX_CH1, 0x60,
  1753. pwr_level << 0x5);
  1754. wcd937x->tx_ch_pwr[0] = pwr_level;
  1755. } else if (strnstr(kcontrol->id.name, "CH3",
  1756. sizeof(kcontrol->id.name))) {
  1757. snd_soc_component_update_bits(component,
  1758. WCD937X_ANA_TX_CH3, 0x60,
  1759. pwr_level << 0x5);
  1760. wcd937x->tx_ch_pwr[1] = pwr_level;
  1761. }
  1762. return 0;
  1763. }
  1764. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_value *ucontrol)
  1766. {
  1767. u8 ear_pa_gain = 0;
  1768. struct snd_soc_component *component =
  1769. snd_soc_kcontrol_component(kcontrol);
  1770. ear_pa_gain = snd_soc_component_read(component,
  1771. WCD937X_ANA_EAR_COMPANDER_CTL);
  1772. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1773. ucontrol->value.integer.value[0] = ear_pa_gain;
  1774. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1775. ear_pa_gain);
  1776. return 0;
  1777. }
  1778. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1779. struct snd_ctl_elem_value *ucontrol)
  1780. {
  1781. u8 ear_pa_gain = 0;
  1782. struct snd_soc_component *component =
  1783. snd_soc_kcontrol_component(kcontrol);
  1784. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1785. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1786. __func__, ucontrol->value.integer.value[0]);
  1787. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1788. if (!wcd937x->comp1_enable) {
  1789. snd_soc_component_update_bits(component,
  1790. WCD937X_ANA_EAR_COMPANDER_CTL,
  1791. 0x7C, ear_pa_gain);
  1792. }
  1793. return 0;
  1794. }
  1795. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1796. struct snd_ctl_elem_value *ucontrol)
  1797. {
  1798. struct snd_soc_component *component =
  1799. snd_soc_kcontrol_component(kcontrol);
  1800. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1801. bool hphr;
  1802. struct soc_multi_mixer_control *mc;
  1803. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1804. hphr = mc->shift;
  1805. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1806. wcd937x->comp1_enable;
  1807. return 0;
  1808. }
  1809. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1810. struct snd_ctl_elem_value *ucontrol)
  1811. {
  1812. struct snd_soc_component *component =
  1813. snd_soc_kcontrol_component(kcontrol);
  1814. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1815. int value = ucontrol->value.integer.value[0];
  1816. bool hphr;
  1817. struct soc_multi_mixer_control *mc;
  1818. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1819. hphr = mc->shift;
  1820. if (hphr)
  1821. wcd937x->comp2_enable = value;
  1822. else
  1823. wcd937x->comp1_enable = value;
  1824. return 0;
  1825. }
  1826. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1827. struct snd_kcontrol *kcontrol,
  1828. int event)
  1829. {
  1830. struct snd_soc_component *component =
  1831. snd_soc_dapm_to_component(w->dapm);
  1832. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1833. struct wcd937x_pdata *pdata = NULL;
  1834. int ret = 0;
  1835. pdata = dev_get_platdata(wcd937x->dev);
  1836. if (!pdata) {
  1837. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1838. return -EINVAL;
  1839. }
  1840. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1841. w->name, event);
  1842. switch (event) {
  1843. case SND_SOC_DAPM_PRE_PMU:
  1844. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1845. dev_dbg(component->dev,
  1846. "%s: buck already in enabled state\n",
  1847. __func__);
  1848. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1849. return 0;
  1850. }
  1851. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1852. wcd937x->supplies,
  1853. pdata->regulator,
  1854. pdata->num_supplies,
  1855. "cdc-vdd-buck");
  1856. if (ret == -EINVAL) {
  1857. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1858. __func__);
  1859. return ret;
  1860. }
  1861. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1862. /*
  1863. * 200us sleep is required after LDO15 is enabled as per
  1864. * HW requirement
  1865. */
  1866. usleep_range(200, 250);
  1867. break;
  1868. case SND_SOC_DAPM_POST_PMD:
  1869. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1870. break;
  1871. }
  1872. return 0;
  1873. }
  1874. static const char * const rx_hph_mode_mux_text[] = {
  1875. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1876. "CLS_H_ULP", "CLS_AB_HIFI",
  1877. };
  1878. const char * const tx_master_ch_text[] = {
  1879. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1880. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1881. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1882. "SWRM_PCM_IN",
  1883. };
  1884. const struct soc_enum tx_master_ch_enum =
  1885. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1886. tx_master_ch_text);
  1887. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1888. {
  1889. u8 ch_type = 0;
  1890. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1891. ch_type = ADC1;
  1892. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1893. ch_type = ADC2;
  1894. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1895. ch_type = ADC3;
  1896. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1897. ch_type = DMIC0;
  1898. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1899. ch_type = DMIC1;
  1900. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1901. ch_type = MBHC;
  1902. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1903. ch_type = DMIC2;
  1904. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1905. ch_type = DMIC3;
  1906. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1907. ch_type = DMIC4;
  1908. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1909. ch_type = DMIC5;
  1910. else
  1911. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1912. if (ch_type)
  1913. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1914. else
  1915. *ch_idx = -EINVAL;
  1916. }
  1917. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. struct snd_soc_component *component =
  1921. snd_soc_kcontrol_component(kcontrol);
  1922. struct wcd937x_priv *wcd937x = NULL;
  1923. int slave_ch_idx = -EINVAL;
  1924. if (component == NULL)
  1925. return -EINVAL;
  1926. wcd937x = snd_soc_component_get_drvdata(component);
  1927. if (wcd937x == NULL)
  1928. return -EINVAL;
  1929. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1930. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1931. return -EINVAL;
  1932. ucontrol->value.integer.value[0] =
  1933. wcd937x_slave_get_master_ch_val(
  1934. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1935. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1936. __func__, ucontrol->value.integer.value[0]);
  1937. return 0;
  1938. }
  1939. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1940. struct snd_ctl_elem_value *ucontrol)
  1941. {
  1942. struct snd_soc_component *component =
  1943. snd_soc_kcontrol_component(kcontrol);
  1944. struct wcd937x_priv *wcd937x;
  1945. int slave_ch_idx = -EINVAL, idx = 0;
  1946. if (component == NULL)
  1947. return -EINVAL;
  1948. wcd937x = snd_soc_component_get_drvdata(component);
  1949. if (wcd937x == NULL)
  1950. return -EINVAL;
  1951. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1952. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1953. return -EINVAL;
  1954. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1955. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1956. __func__, ucontrol->value.enumerated.item[0]);
  1957. idx = ucontrol->value.enumerated.item[0];
  1958. if (idx < 0 || idx >= ARRAY_SIZE(wcd937x_swr_master_ch_map))
  1959. return -EINVAL;
  1960. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1961. wcd937x_slave_get_master_ch(idx);
  1962. return 0;
  1963. }
  1964. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1965. "L0", "L1", "L2", "L3",
  1966. };
  1967. static const char * const wcd937x_ear_pa_gain_text[] = {
  1968. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1969. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1970. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1971. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1972. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1973. };
  1974. static const struct soc_enum rx_hph_mode_mux_enum =
  1975. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1976. rx_hph_mode_mux_text);
  1977. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1978. wcd937x_ear_pa_gain_text);
  1979. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1980. wcd937x_tx_ch_pwr_level_text);
  1981. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1982. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1983. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1984. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1985. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1986. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1987. wcd937x_get_compander, wcd937x_set_compander),
  1988. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1989. wcd937x_get_compander, wcd937x_set_compander),
  1990. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1991. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1992. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1993. analog_gain),
  1994. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1995. analog_gain),
  1996. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1997. analog_gain),
  1998. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1999. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2000. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2001. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2002. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2003. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2004. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2005. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2006. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2007. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2008. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2009. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2010. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2011. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2012. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2013. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2014. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2015. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2016. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2017. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2018. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  2019. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2020. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2021. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2022. };
  2023. static const struct snd_kcontrol_new adc1_switch[] = {
  2024. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2025. };
  2026. static const struct snd_kcontrol_new adc2_switch[] = {
  2027. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2028. };
  2029. static const struct snd_kcontrol_new adc3_switch[] = {
  2030. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2031. };
  2032. static const struct snd_kcontrol_new dmic1_switch[] = {
  2033. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2034. };
  2035. static const struct snd_kcontrol_new dmic2_switch[] = {
  2036. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2037. };
  2038. static const struct snd_kcontrol_new dmic3_switch[] = {
  2039. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2040. };
  2041. static const struct snd_kcontrol_new dmic4_switch[] = {
  2042. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2043. };
  2044. static const struct snd_kcontrol_new dmic5_switch[] = {
  2045. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2046. };
  2047. static const struct snd_kcontrol_new dmic6_switch[] = {
  2048. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2049. };
  2050. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2051. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2052. };
  2053. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2054. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2055. };
  2056. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2057. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2058. };
  2059. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2060. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2061. };
  2062. static const char * const adc2_mux_text[] = {
  2063. "INP2", "INP3"
  2064. };
  2065. static const char * const rdac3_mux_text[] = {
  2066. "RX1", "RX3"
  2067. };
  2068. static const struct soc_enum adc2_enum =
  2069. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2070. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2071. static const struct soc_enum rdac3_enum =
  2072. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2073. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2074. static const struct snd_kcontrol_new tx_adc2_mux =
  2075. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2076. static const struct snd_kcontrol_new rx_rdac3_mux =
  2077. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2078. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2079. /*input widgets*/
  2080. SND_SOC_DAPM_INPUT("AMIC1"),
  2081. SND_SOC_DAPM_INPUT("AMIC2"),
  2082. SND_SOC_DAPM_INPUT("AMIC3"),
  2083. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2084. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2085. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2086. /*
  2087. * These dummy widgets are null connected to WCD937x dapm input and
  2088. * output widgets which are not actual path endpoints. This ensures
  2089. * dapm doesnt set these dapm input and output widgets as endpoints.
  2090. */
  2091. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2092. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2093. /*tx widgets*/
  2094. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2095. wcd937x_codec_enable_adc,
  2096. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2097. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2098. wcd937x_codec_enable_adc,
  2099. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2100. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2101. NULL, 0, wcd937x_enable_req,
  2102. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2103. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2104. NULL, 0, wcd937x_enable_req,
  2105. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2106. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2107. &tx_adc2_mux),
  2108. /*tx mixers*/
  2109. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2110. adc1_switch, ARRAY_SIZE(adc1_switch),
  2111. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2112. SND_SOC_DAPM_POST_PMD),
  2113. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2114. adc2_switch, ARRAY_SIZE(adc2_switch),
  2115. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2116. SND_SOC_DAPM_POST_PMD),
  2117. /* micbias widgets*/
  2118. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2119. wcd937x_codec_enable_micbias,
  2120. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2121. SND_SOC_DAPM_POST_PMD),
  2122. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2123. wcd937x_codec_enable_micbias,
  2124. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2125. SND_SOC_DAPM_POST_PMD),
  2126. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2127. wcd937x_codec_enable_micbias,
  2128. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2129. SND_SOC_DAPM_POST_PMD),
  2130. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2131. wcd937x_codec_enable_vdd_buck,
  2132. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2133. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2134. wcd937x_enable_clsh,
  2135. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2136. /*rx widgets*/
  2137. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2138. wcd937x_codec_enable_ear_pa,
  2139. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2140. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2141. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2142. wcd937x_codec_enable_aux_pa,
  2143. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2144. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2145. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2146. wcd937x_codec_enable_hphl_pa,
  2147. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2148. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2149. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2150. wcd937x_codec_enable_hphr_pa,
  2151. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2152. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2153. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2154. wcd937x_codec_hphl_dac_event,
  2155. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2156. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2157. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2158. wcd937x_codec_hphr_dac_event,
  2159. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2160. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2161. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2162. wcd937x_codec_ear_dac_event,
  2163. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2164. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2165. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2166. wcd937x_codec_aux_dac_event,
  2167. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2168. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2169. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2170. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2171. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2172. SND_SOC_DAPM_POST_PMD),
  2173. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2174. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2175. SND_SOC_DAPM_POST_PMD),
  2176. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2177. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2178. SND_SOC_DAPM_POST_PMD),
  2179. /* rx mixer widgets*/
  2180. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2181. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2182. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2183. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2184. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2185. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2186. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2187. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2188. /*output widgets tx*/
  2189. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2190. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2191. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2192. /*output widgets rx*/
  2193. SND_SOC_DAPM_OUTPUT("EAR"),
  2194. SND_SOC_DAPM_OUTPUT("AUX"),
  2195. SND_SOC_DAPM_OUTPUT("HPHL"),
  2196. SND_SOC_DAPM_OUTPUT("HPHR"),
  2197. /* micbias pull up widgets*/
  2198. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2199. wcd937x_codec_enable_micbias_pullup,
  2200. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2201. SND_SOC_DAPM_POST_PMD),
  2202. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2203. wcd937x_codec_enable_micbias_pullup,
  2204. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2205. SND_SOC_DAPM_POST_PMD),
  2206. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2207. wcd937x_codec_enable_micbias_pullup,
  2208. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2209. SND_SOC_DAPM_POST_PMD),
  2210. };
  2211. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2212. /*input widgets*/
  2213. SND_SOC_DAPM_INPUT("AMIC4"),
  2214. /*tx widgets*/
  2215. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2216. wcd937x_codec_enable_adc,
  2217. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2218. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2219. NULL, 0, wcd937x_enable_req,
  2220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2221. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2222. wcd937x_codec_enable_dmic,
  2223. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2224. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2225. wcd937x_codec_enable_dmic,
  2226. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2227. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2228. wcd937x_codec_enable_dmic,
  2229. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2230. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2231. wcd937x_codec_enable_dmic,
  2232. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2233. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2234. wcd937x_codec_enable_dmic,
  2235. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2236. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2237. wcd937x_codec_enable_dmic,
  2238. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2239. /*tx mixer widgets*/
  2240. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2241. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2242. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2243. SND_SOC_DAPM_POST_PMD),
  2244. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2245. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2246. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2247. SND_SOC_DAPM_POST_PMD),
  2248. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2249. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2250. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2251. SND_SOC_DAPM_POST_PMD),
  2252. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2253. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2254. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2255. SND_SOC_DAPM_POST_PMD),
  2256. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2257. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2258. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2259. SND_SOC_DAPM_POST_PMD),
  2260. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2261. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2262. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2263. SND_SOC_DAPM_POST_PMD),
  2264. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2265. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2266. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2267. /*output widgets*/
  2268. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2269. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2270. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2271. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2272. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2273. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2274. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2275. };
  2276. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2277. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2278. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2279. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2280. {"ADC1 REQ", NULL, "ADC1"},
  2281. {"ADC1", NULL, "AMIC1"},
  2282. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2283. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2284. {"ADC2 REQ", NULL, "ADC2"},
  2285. {"ADC2", NULL, "ADC2 MUX"},
  2286. {"ADC2 MUX", "INP3", "AMIC3"},
  2287. {"ADC2 MUX", "INP2", "AMIC2"},
  2288. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2289. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2290. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2291. {"RX1", NULL, "IN1_HPHL"},
  2292. {"RDAC1", NULL, "RX1"},
  2293. {"HPHL_RDAC", "Switch", "RDAC1"},
  2294. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2295. {"HPHL", NULL, "HPHL PGA"},
  2296. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2297. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2298. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2299. {"RX2", NULL, "IN2_HPHR"},
  2300. {"RDAC2", NULL, "RX2"},
  2301. {"HPHR_RDAC", "Switch", "RDAC2"},
  2302. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2303. {"HPHR", NULL, "HPHR PGA"},
  2304. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2305. {"IN3_AUX", NULL, "VDD_BUCK"},
  2306. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2307. {"RX3", NULL, "IN3_AUX"},
  2308. {"RDAC4", NULL, "RX3"},
  2309. {"AUX_RDAC", "Switch", "RDAC4"},
  2310. {"AUX PGA", NULL, "AUX_RDAC"},
  2311. {"AUX", NULL, "AUX PGA"},
  2312. {"RDAC3_MUX", "RX3", "RX3"},
  2313. {"RDAC3_MUX", "RX1", "RX1"},
  2314. {"RDAC3", NULL, "RDAC3_MUX"},
  2315. {"EAR_RDAC", "Switch", "RDAC3"},
  2316. {"EAR PGA", NULL, "EAR_RDAC"},
  2317. {"EAR", NULL, "EAR PGA"},
  2318. };
  2319. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2320. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2321. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2322. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2323. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2324. {"ADC3 REQ", NULL, "ADC3"},
  2325. {"ADC3", NULL, "AMIC4"},
  2326. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2327. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2328. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2329. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2330. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2331. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2332. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2333. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2334. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2335. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2336. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2337. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2338. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2339. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2340. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2341. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2342. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2343. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2344. };
  2345. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2346. void *file_private_data,
  2347. struct file *file,
  2348. char __user *buf, size_t count,
  2349. loff_t pos)
  2350. {
  2351. struct wcd937x_priv *priv;
  2352. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2353. int len = 0;
  2354. priv = (struct wcd937x_priv *) entry->private_data;
  2355. if (!priv) {
  2356. pr_err("%s: wcd937x priv is null\n", __func__);
  2357. return -EINVAL;
  2358. }
  2359. switch (priv->version) {
  2360. case WCD937X_VERSION_1_0:
  2361. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2362. break;
  2363. default:
  2364. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2365. }
  2366. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2367. }
  2368. static struct snd_info_entry_ops wcd937x_info_ops = {
  2369. .read = wcd937x_version_read,
  2370. };
  2371. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2372. void *file_private_data,
  2373. struct file *file,
  2374. char __user *buf, size_t count,
  2375. loff_t pos)
  2376. {
  2377. struct wcd937x_priv *priv;
  2378. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2379. int len = 0;
  2380. priv = (struct wcd937x_priv *) entry->private_data;
  2381. if (!priv) {
  2382. pr_err("%s: wcd937x priv is null\n", __func__);
  2383. return -EINVAL;
  2384. }
  2385. switch (priv->variant) {
  2386. case WCD9370_VARIANT:
  2387. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2388. break;
  2389. case WCD9375_VARIANT:
  2390. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2391. break;
  2392. default:
  2393. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2394. }
  2395. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2396. }
  2397. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2398. .read = wcd937x_variant_read,
  2399. };
  2400. /*
  2401. * wcd937x_info_create_codec_entry - creates wcd937x module
  2402. * @codec_root: The parent directory
  2403. * @component: component instance
  2404. *
  2405. * Creates wcd937x module, variant and version entry under the given
  2406. * parent directory.
  2407. *
  2408. * Return: 0 on success or negative error code on failure.
  2409. */
  2410. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2411. struct snd_soc_component *component)
  2412. {
  2413. struct snd_info_entry *version_entry;
  2414. struct snd_info_entry *variant_entry;
  2415. struct wcd937x_priv *priv;
  2416. struct snd_soc_card *card;
  2417. if (!codec_root || !component)
  2418. return -EINVAL;
  2419. priv = snd_soc_component_get_drvdata(component);
  2420. if (priv->entry) {
  2421. dev_dbg(priv->dev,
  2422. "%s:wcd937x module already created\n", __func__);
  2423. return 0;
  2424. }
  2425. card = component->card;
  2426. priv->entry = snd_info_create_module_entry(codec_root->module,
  2427. "wcd937x", codec_root);
  2428. if (!priv->entry) {
  2429. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2430. __func__);
  2431. return -ENOMEM;
  2432. }
  2433. priv->entry->mode = S_IFDIR | 0555;
  2434. if (snd_info_register(priv->entry) < 0) {
  2435. snd_info_free_entry(priv->entry);
  2436. return -ENOMEM;
  2437. }
  2438. version_entry = snd_info_create_card_entry(card->snd_card,
  2439. "version",
  2440. priv->entry);
  2441. if (!version_entry) {
  2442. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2443. __func__);
  2444. snd_info_free_entry(priv->entry);
  2445. return -ENOMEM;
  2446. }
  2447. version_entry->private_data = priv;
  2448. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2449. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2450. version_entry->c.ops = &wcd937x_info_ops;
  2451. if (snd_info_register(version_entry) < 0) {
  2452. snd_info_free_entry(version_entry);
  2453. snd_info_free_entry(priv->entry);
  2454. return -ENOMEM;
  2455. }
  2456. priv->version_entry = version_entry;
  2457. variant_entry = snd_info_create_card_entry(card->snd_card,
  2458. "variant",
  2459. priv->entry);
  2460. if (!variant_entry) {
  2461. dev_dbg(component->dev,
  2462. "%s: failed to create wcd937x variant entry\n",
  2463. __func__);
  2464. snd_info_free_entry(version_entry);
  2465. snd_info_free_entry(priv->entry);
  2466. return -ENOMEM;
  2467. }
  2468. variant_entry->private_data = priv;
  2469. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2470. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2471. variant_entry->c.ops = &wcd937x_variant_ops;
  2472. if (snd_info_register(variant_entry) < 0) {
  2473. snd_info_free_entry(variant_entry);
  2474. snd_info_free_entry(version_entry);
  2475. snd_info_free_entry(priv->entry);
  2476. return -ENOMEM;
  2477. }
  2478. priv->variant_entry = variant_entry;
  2479. return 0;
  2480. }
  2481. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2482. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2483. struct wcd937x_pdata *pdata)
  2484. {
  2485. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2486. int rc = 0;
  2487. if (!pdata) {
  2488. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2489. return -ENODEV;
  2490. }
  2491. /* set micbias voltage */
  2492. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2493. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2494. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2495. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2496. rc = -EINVAL;
  2497. goto done;
  2498. }
  2499. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2500. vout_ctl_1);
  2501. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2502. vout_ctl_2);
  2503. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2504. vout_ctl_3);
  2505. done:
  2506. return rc;
  2507. }
  2508. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2509. {
  2510. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2511. struct snd_soc_dapm_context *dapm =
  2512. snd_soc_component_get_dapm(component);
  2513. int variant;
  2514. int ret = -EINVAL;
  2515. dev_info(component->dev, "%s()\n", __func__);
  2516. wcd937x = snd_soc_component_get_drvdata(component);
  2517. if (!wcd937x)
  2518. return -EINVAL;
  2519. wcd937x->component = component;
  2520. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2521. devm_regmap_qti_debugfs_register(&wcd937x->tx_swr_dev->dev, wcd937x->regmap);
  2522. variant = (snd_soc_component_read(
  2523. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2524. wcd937x->variant = variant;
  2525. wcd937x->fw_data = devm_kzalloc(component->dev,
  2526. sizeof(*(wcd937x->fw_data)),
  2527. GFP_KERNEL);
  2528. if (!wcd937x->fw_data) {
  2529. dev_err(component->dev, "Failed to allocate fw_data\n");
  2530. ret = -ENOMEM;
  2531. goto err;
  2532. }
  2533. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2534. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2535. WCD9XXX_CODEC_HWDEP_NODE, component);
  2536. if (ret < 0) {
  2537. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2538. goto err_hwdep;
  2539. }
  2540. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2541. if (ret) {
  2542. pr_err("%s: mbhc initialization failed\n", __func__);
  2543. goto err_hwdep;
  2544. }
  2545. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2546. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2547. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2548. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2549. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2550. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2551. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2552. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2553. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2554. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2555. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2556. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2557. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2558. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2559. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2560. snd_soc_dapm_sync(dapm);
  2561. wcd_cls_h_init(&wcd937x->clsh_info);
  2562. wcd937x_init_reg(component);
  2563. if (wcd937x->variant == WCD9375_VARIANT) {
  2564. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2565. ARRAY_SIZE(wcd9375_dapm_widgets));
  2566. if (ret < 0) {
  2567. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2568. __func__);
  2569. goto err_hwdep;
  2570. }
  2571. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2572. ARRAY_SIZE(wcd9375_audio_map));
  2573. if (ret < 0) {
  2574. dev_err(component->dev, "%s: Failed to add routes\n",
  2575. __func__);
  2576. goto err_hwdep;
  2577. }
  2578. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2579. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2580. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2581. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2582. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2583. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2584. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2585. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2586. snd_soc_dapm_sync(dapm);
  2587. }
  2588. wcd937x->version = WCD937X_VERSION_1_0;
  2589. /* Register event notifier */
  2590. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2591. if (wcd937x->register_notifier) {
  2592. ret = wcd937x->register_notifier(wcd937x->handle,
  2593. &wcd937x->nblock,
  2594. true);
  2595. if (ret) {
  2596. dev_err(component->dev,
  2597. "%s: Failed to register notifier %d\n",
  2598. __func__, ret);
  2599. return ret;
  2600. }
  2601. }
  2602. return ret;
  2603. err_hwdep:
  2604. wcd937x->fw_data = NULL;
  2605. err:
  2606. return ret;
  2607. }
  2608. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2609. {
  2610. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2611. if (!wcd937x)
  2612. return;
  2613. if (wcd937x->register_notifier)
  2614. wcd937x->register_notifier(wcd937x->handle,
  2615. &wcd937x->nblock,
  2616. false);
  2617. return;
  2618. }
  2619. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2620. .name = WCD937X_DRV_NAME,
  2621. .probe = wcd937x_soc_codec_probe,
  2622. .remove = wcd937x_soc_codec_remove,
  2623. .controls = wcd937x_snd_controls,
  2624. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2625. .dapm_widgets = wcd937x_dapm_widgets,
  2626. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2627. .dapm_routes = wcd937x_audio_map,
  2628. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2629. };
  2630. #ifdef CONFIG_PM_SLEEP
  2631. static int wcd937x_suspend(struct device *dev)
  2632. {
  2633. struct wcd937x_priv *wcd937x = NULL;
  2634. int ret = 0;
  2635. struct wcd937x_pdata *pdata = NULL;
  2636. if (!dev)
  2637. return -ENODEV;
  2638. wcd937x = dev_get_drvdata(dev);
  2639. if (!wcd937x)
  2640. return -EINVAL;
  2641. pdata = dev_get_platdata(wcd937x->dev);
  2642. if (!pdata) {
  2643. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2644. return -EINVAL;
  2645. }
  2646. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2647. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2648. wcd937x->supplies,
  2649. pdata->regulator,
  2650. pdata->num_supplies,
  2651. "cdc-vdd-buck");
  2652. if (ret == -EINVAL) {
  2653. dev_err(dev, "%s: vdd buck is not disabled\n",
  2654. __func__);
  2655. return 0;
  2656. }
  2657. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2658. }
  2659. return 0;
  2660. }
  2661. static int wcd937x_resume(struct device *dev)
  2662. {
  2663. return 0;
  2664. }
  2665. #endif
  2666. static int wcd937x_reset(struct device *dev)
  2667. {
  2668. struct wcd937x_priv *wcd937x = NULL;
  2669. int rc = 0;
  2670. int value = 0;
  2671. if (!dev)
  2672. return -ENODEV;
  2673. wcd937x = dev_get_drvdata(dev);
  2674. if (!wcd937x)
  2675. return -EINVAL;
  2676. if (!wcd937x->rst_np) {
  2677. dev_err(dev, "%s: reset gpio device node not specified\n",
  2678. __func__);
  2679. return -EINVAL;
  2680. }
  2681. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2682. if (value > 0)
  2683. return 0;
  2684. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2685. if (rc) {
  2686. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2687. __func__);
  2688. return rc;
  2689. }
  2690. /* 20ms sleep required after pulling the reset gpio to LOW */
  2691. usleep_range(20, 30);
  2692. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2693. if (rc) {
  2694. dev_err(dev, "%s: wcd active state request fail!\n",
  2695. __func__);
  2696. return rc;
  2697. }
  2698. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2699. usleep_range(20, 30);
  2700. return rc;
  2701. }
  2702. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2703. u32 *val)
  2704. {
  2705. int rc = 0;
  2706. rc = of_property_read_u32(dev->of_node, name, val);
  2707. if (rc)
  2708. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2709. __func__, name, dev->of_node->full_name);
  2710. return rc;
  2711. }
  2712. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2713. struct wcd937x_micbias_setting *mb)
  2714. {
  2715. u32 prop_val = 0;
  2716. int rc = 0;
  2717. /* MB1 */
  2718. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2719. NULL)) {
  2720. rc = wcd937x_read_of_property_u32(dev,
  2721. "qcom,cdc-micbias1-mv",
  2722. &prop_val);
  2723. if (!rc)
  2724. mb->micb1_mv = prop_val;
  2725. } else {
  2726. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2727. __func__);
  2728. }
  2729. /* MB2 */
  2730. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2731. NULL)) {
  2732. rc = wcd937x_read_of_property_u32(dev,
  2733. "qcom,cdc-micbias2-mv",
  2734. &prop_val);
  2735. if (!rc)
  2736. mb->micb2_mv = prop_val;
  2737. } else {
  2738. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2739. __func__);
  2740. }
  2741. /* MB3 */
  2742. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2743. NULL)) {
  2744. rc = wcd937x_read_of_property_u32(dev,
  2745. "qcom,cdc-micbias3-mv",
  2746. &prop_val);
  2747. if (!rc)
  2748. mb->micb3_mv = prop_val;
  2749. } else {
  2750. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2751. __func__);
  2752. }
  2753. }
  2754. static int wcd937x_reset_low(struct device *dev)
  2755. {
  2756. struct wcd937x_priv *wcd937x = NULL;
  2757. int rc = 0;
  2758. if (!dev)
  2759. return -ENODEV;
  2760. wcd937x = dev_get_drvdata(dev);
  2761. if (!wcd937x)
  2762. return -EINVAL;
  2763. if (!wcd937x->rst_np) {
  2764. dev_err(dev, "%s: reset gpio device node not specified\n",
  2765. __func__);
  2766. return -EINVAL;
  2767. }
  2768. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2769. if (rc) {
  2770. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2771. __func__);
  2772. return rc;
  2773. }
  2774. /* 20ms sleep required after pulling the reset gpio to LOW */
  2775. usleep_range(20, 30);
  2776. return rc;
  2777. }
  2778. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2779. {
  2780. struct wcd937x_pdata *pdata = NULL;
  2781. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2782. GFP_KERNEL);
  2783. if (!pdata)
  2784. return NULL;
  2785. pdata->rst_np = of_parse_phandle(dev->of_node,
  2786. "qcom,wcd-rst-gpio-node", 0);
  2787. if (!pdata->rst_np) {
  2788. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2789. __func__, "qcom,wcd-rst-gpio-node",
  2790. dev->of_node->full_name);
  2791. return NULL;
  2792. }
  2793. /* Parse power supplies */
  2794. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2795. &pdata->num_supplies);
  2796. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2797. dev_err(dev, "%s: no power supplies defined for codec\n",
  2798. __func__);
  2799. return NULL;
  2800. }
  2801. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2802. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2803. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2804. return pdata;
  2805. }
  2806. static int wcd937x_wakeup(void *handle, bool enable)
  2807. {
  2808. struct wcd937x_priv *priv;
  2809. if (!handle) {
  2810. pr_err("%s: NULL handle\n", __func__);
  2811. return -EINVAL;
  2812. }
  2813. priv = (struct wcd937x_priv *)handle;
  2814. if (!priv->tx_swr_dev) {
  2815. pr_err("%s: tx swr dev is NULL\n", __func__);
  2816. return -EINVAL;
  2817. }
  2818. if (enable)
  2819. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2820. else
  2821. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2822. }
  2823. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2824. {
  2825. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2826. __func__, irq);
  2827. return IRQ_HANDLED;
  2828. }
  2829. static int wcd937x_bind(struct device *dev)
  2830. {
  2831. int ret = 0, i = 0;
  2832. struct wcd937x_priv *wcd937x = NULL;
  2833. struct wcd937x_pdata *pdata = NULL;
  2834. struct wcd_ctrl_platform_data *plat_data = NULL;
  2835. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2836. if (!wcd937x)
  2837. return -ENOMEM;
  2838. dev_set_drvdata(dev, wcd937x);
  2839. pdata = wcd937x_populate_dt_data(dev);
  2840. if (!pdata) {
  2841. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2842. return -EINVAL;
  2843. }
  2844. wcd937x->dev = dev;
  2845. wcd937x->dev->platform_data = pdata;
  2846. wcd937x->rst_np = pdata->rst_np;
  2847. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2848. pdata->regulator, pdata->num_supplies);
  2849. if (!wcd937x->supplies) {
  2850. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2851. __func__);
  2852. goto err_bind_all;
  2853. }
  2854. plat_data = dev_get_platdata(dev->parent);
  2855. if (!plat_data) {
  2856. dev_err(dev, "%s: platform data from parent is NULL\n",
  2857. __func__);
  2858. ret = -EINVAL;
  2859. goto err_bind_all;
  2860. }
  2861. wcd937x->handle = (void *)plat_data->handle;
  2862. if (!wcd937x->handle) {
  2863. dev_err(dev, "%s: handle is NULL\n", __func__);
  2864. ret = -EINVAL;
  2865. goto err_bind_all;
  2866. }
  2867. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2868. if (!wcd937x->update_wcd_event) {
  2869. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2870. __func__);
  2871. ret = -EINVAL;
  2872. goto err_bind_all;
  2873. }
  2874. wcd937x->register_notifier = plat_data->register_notifier;
  2875. if (!wcd937x->register_notifier) {
  2876. dev_err(dev, "%s: register_notifier api is null!\n",
  2877. __func__);
  2878. ret = -EINVAL;
  2879. goto err_bind_all;
  2880. }
  2881. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2882. pdata->regulator,
  2883. pdata->num_supplies);
  2884. if (ret) {
  2885. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2886. __func__);
  2887. goto err_bind_all;
  2888. }
  2889. wcd937x_reset(dev);
  2890. /*
  2891. * Add 5msec delay to provide sufficient time for
  2892. * soundwire auto enumeration of slave devices as
  2893. * as per HW requirement.
  2894. */
  2895. usleep_range(5000, 5010);
  2896. wcd937x->wakeup = wcd937x_wakeup;
  2897. ret = component_bind_all(dev, wcd937x);
  2898. if (ret) {
  2899. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2900. __func__, ret);
  2901. goto err_bind_all;
  2902. }
  2903. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2904. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2905. if (ret) {
  2906. dev_err(dev, "Failed to read port mapping\n");
  2907. goto err;
  2908. }
  2909. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2910. CODEC_TX);
  2911. if (ret) {
  2912. dev_err(dev, "Failed to read port params\n");
  2913. goto err;
  2914. }
  2915. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2916. if (!wcd937x->rx_swr_dev) {
  2917. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2918. __func__);
  2919. ret = -ENODEV;
  2920. goto err;
  2921. }
  2922. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2923. if (!wcd937x->tx_swr_dev) {
  2924. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2925. __func__);
  2926. ret = -ENODEV;
  2927. goto err;
  2928. }
  2929. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  2930. wcd937x->swr_tx_port_params);
  2931. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2932. &wcd937x_regmap_config);
  2933. if (!wcd937x->regmap) {
  2934. dev_err(dev, "%s: Regmap init failed\n",
  2935. __func__);
  2936. goto err;
  2937. }
  2938. /* Set all interupts as edge triggered */
  2939. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2940. regmap_write(wcd937x->regmap,
  2941. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2942. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2943. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2944. wcd937x->irq_info.codec_name = "WCD937X";
  2945. wcd937x->irq_info.regmap = wcd937x->regmap;
  2946. wcd937x->irq_info.dev = dev;
  2947. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2948. if (ret) {
  2949. dev_err(dev, "%s: IRQ init failed: %d\n",
  2950. __func__, ret);
  2951. goto err;
  2952. }
  2953. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2954. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2955. if (ret < 0) {
  2956. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2957. goto err_irq;
  2958. }
  2959. /* default L1 power setting */
  2960. wcd937x->tx_ch_pwr[0] = 1;
  2961. wcd937x->tx_ch_pwr[1] = 1;
  2962. mutex_init(&wcd937x->micb_lock);
  2963. mutex_init(&wcd937x->ana_tx_clk_lock);
  2964. /* Request for watchdog interrupt */
  2965. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2966. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2967. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2968. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2969. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2970. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2971. /* Disable watchdog interrupt for HPH and AUX */
  2972. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2973. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2974. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2975. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2976. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2977. if (ret) {
  2978. dev_err(dev, "%s: Codec registration failed\n",
  2979. __func__);
  2980. goto err_irq;
  2981. }
  2982. return ret;
  2983. err_irq:
  2984. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2985. err:
  2986. component_unbind_all(dev, wcd937x);
  2987. err_bind_all:
  2988. dev_set_drvdata(dev, NULL);
  2989. kfree(pdata);
  2990. kfree(wcd937x);
  2991. return ret;
  2992. }
  2993. static void wcd937x_unbind(struct device *dev)
  2994. {
  2995. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2996. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2997. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2998. snd_soc_unregister_component(dev);
  2999. component_unbind_all(dev, wcd937x);
  3000. mutex_destroy(&wcd937x->micb_lock);
  3001. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  3002. dev_set_drvdata(dev, NULL);
  3003. kfree(pdata);
  3004. kfree(wcd937x);
  3005. }
  3006. static const struct of_device_id wcd937x_dt_match[] = {
  3007. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  3008. {}
  3009. };
  3010. static const struct component_master_ops wcd937x_comp_ops = {
  3011. .bind = wcd937x_bind,
  3012. .unbind = wcd937x_unbind,
  3013. };
  3014. static int wcd937x_compare_of(struct device *dev, void *data)
  3015. {
  3016. return dev->of_node == data;
  3017. }
  3018. static void wcd937x_release_of(struct device *dev, void *data)
  3019. {
  3020. of_node_put(data);
  3021. }
  3022. static int wcd937x_add_slave_components(struct device *dev,
  3023. struct component_match **matchptr)
  3024. {
  3025. struct device_node *np, *rx_node, *tx_node;
  3026. np = dev->of_node;
  3027. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3028. if (!rx_node) {
  3029. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3030. return -ENODEV;
  3031. }
  3032. of_node_get(rx_node);
  3033. component_match_add_release(dev, matchptr,
  3034. wcd937x_release_of,
  3035. wcd937x_compare_of,
  3036. rx_node);
  3037. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3038. if (!tx_node) {
  3039. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3040. return -ENODEV;
  3041. }
  3042. of_node_get(tx_node);
  3043. component_match_add_release(dev, matchptr,
  3044. wcd937x_release_of,
  3045. wcd937x_compare_of,
  3046. tx_node);
  3047. return 0;
  3048. }
  3049. static int wcd937x_probe(struct platform_device *pdev)
  3050. {
  3051. struct component_match *match = NULL;
  3052. int ret;
  3053. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3054. if (ret)
  3055. return ret;
  3056. return component_master_add_with_match(&pdev->dev,
  3057. &wcd937x_comp_ops, match);
  3058. }
  3059. static int wcd937x_remove(struct platform_device *pdev)
  3060. {
  3061. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3062. dev_set_drvdata(&pdev->dev, NULL);
  3063. return 0;
  3064. }
  3065. #ifdef CONFIG_PM_SLEEP
  3066. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3067. SET_SYSTEM_SLEEP_PM_OPS(
  3068. wcd937x_suspend,
  3069. wcd937x_resume
  3070. )
  3071. };
  3072. #endif
  3073. static struct platform_driver wcd937x_codec_driver = {
  3074. .probe = wcd937x_probe,
  3075. .remove = wcd937x_remove,
  3076. .driver = {
  3077. .name = "wcd937x_codec",
  3078. .owner = THIS_MODULE,
  3079. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3080. #ifdef CONFIG_PM_SLEEP
  3081. .pm = &wcd937x_dev_pm_ops,
  3082. #endif
  3083. .suppress_bind_attrs = true,
  3084. },
  3085. };
  3086. module_platform_driver(wcd937x_codec_driver);
  3087. MODULE_DESCRIPTION("WCD937X Codec driver");
  3088. MODULE_LICENSE("GPL v2");