wcd938x.c 97 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #include "wcd938x.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. enum {
  38. CODEC_TX = 0,
  39. CODEC_RX,
  40. };
  41. enum {
  42. WCD_ADC1 = 0,
  43. WCD_ADC2,
  44. WCD_ADC3,
  45. WCD_ADC4,
  46. ALLOW_BUCK_DISABLE,
  47. HPH_COMP_DELAY,
  48. HPH_PA_DELAY,
  49. AMIC2_BCS_ENABLE,
  50. };
  51. enum {
  52. ADC_MODE_INVALID = 0,
  53. ADC_MODE_HIFI,
  54. ADC_MODE_LO_HIF,
  55. ADC_MODE_NORMAL,
  56. ADC_MODE_LP,
  57. ADC_MODE_ULP1,
  58. ADC_MODE_ULP2,
  59. };
  60. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  61. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  62. static int wcd938x_handle_post_irq(void *data);
  63. static int wcd938x_reset(struct device *dev);
  64. static int wcd938x_reset_low(struct device *dev);
  65. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  66. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  86. };
  87. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  88. .name = "wcd938x",
  89. .irqs = wcd938x_irqs,
  90. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  91. .num_regs = 3,
  92. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  93. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  94. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  95. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  96. .use_ack = 1,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd938x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static int wcd938x_handle_post_irq(void *data)
  102. {
  103. struct wcd938x_priv *wcd938x = data;
  104. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  105. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  108. wcd938x->tx_swr_dev->slave_irq_pending =
  109. ((sts1 || sts2 || sts3) ? true : false);
  110. return IRQ_HANDLED;
  111. }
  112. static int wcd938x_init_reg(struct snd_soc_component *component)
  113. {
  114. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  116. /* 1 msec delay as per HW requirement */
  117. usleep_range(1000, 1010);
  118. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  119. /* 1 msec delay as per HW requirement */
  120. usleep_range(1000, 1010);
  121. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  122. 0x10, 0x00);
  123. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  124. 0xF0, 0x80);
  125. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  127. /* 10 msec delay as per HW requirement */
  128. usleep_range(10000, 10010);
  129. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  130. snd_soc_component_update_bits(component,
  131. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  132. 0xF0, 0x00);
  133. snd_soc_component_update_bits(component,
  134. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  135. 0x1F, 0x15);
  136. snd_soc_component_update_bits(component,
  137. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  138. 0x1F, 0x15);
  139. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  140. 0xC0, 0x80);
  141. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  142. 0x02, 0x02);
  143. snd_soc_component_update_bits(component,
  144. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  145. 0xFF, 0x14);
  146. snd_soc_component_update_bits(component,
  147. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  148. 0x1F, 0x08);
  149. snd_soc_component_update_bits(component,
  150. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  151. snd_soc_component_update_bits(component,
  152. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  153. snd_soc_component_update_bits(component,
  154. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  155. snd_soc_component_update_bits(component,
  156. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  157. snd_soc_component_update_bits(component,
  158. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  159. snd_soc_component_update_bits(component,
  160. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  161. snd_soc_component_update_bits(component,
  162. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  163. snd_soc_component_update_bits(component,
  164. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  165. snd_soc_component_update_bits(component,
  166. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  167. return 0;
  168. }
  169. static int wcd938x_set_port_params(struct snd_soc_component *component,
  170. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  171. u8 *ch_mask, u32 *ch_rate,
  172. u8 *port_type, u8 path)
  173. {
  174. int i, j;
  175. u8 num_ports = 0;
  176. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  177. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  178. switch (path) {
  179. case CODEC_RX:
  180. map = &wcd938x->rx_port_mapping;
  181. num_ports = wcd938x->num_rx_ports;
  182. break;
  183. case CODEC_TX:
  184. map = &wcd938x->tx_port_mapping;
  185. num_ports = wcd938x->num_tx_ports;
  186. break;
  187. default:
  188. dev_err(component->dev, "%s Invalid path selected %u\n",
  189. __func__, path);
  190. return -EINVAL;
  191. }
  192. for (i = 0; i <= num_ports; i++) {
  193. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  194. if ((*map)[i][j].slave_port_type == slv_prt_type)
  195. goto found;
  196. }
  197. }
  198. found:
  199. if (i > num_ports || j == MAX_CH_PER_PORT) {
  200. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  201. __func__, slv_prt_type);
  202. return -EINVAL;
  203. }
  204. *port_id = i;
  205. *num_ch = (*map)[i][j].num_ch;
  206. *ch_mask = (*map)[i][j].ch_mask;
  207. *ch_rate = (*map)[i][j].ch_rate;
  208. *port_type = (*map)[i][j].master_port_type;
  209. return 0;
  210. }
  211. static int wcd938x_parse_port_mapping(struct device *dev,
  212. char *prop, u8 path)
  213. {
  214. u32 *dt_array, map_size, map_length;
  215. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  216. u32 slave_port_type, master_port_type;
  217. u32 i, ch_iter = 0;
  218. int ret = 0;
  219. u8 *num_ports = NULL;
  220. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  221. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  222. switch (path) {
  223. case CODEC_RX:
  224. map = &wcd938x->rx_port_mapping;
  225. num_ports = &wcd938x->num_rx_ports;
  226. break;
  227. case CODEC_TX:
  228. map = &wcd938x->tx_port_mapping;
  229. num_ports = &wcd938x->num_tx_ports;
  230. break;
  231. default:
  232. dev_err(dev, "%s Invalid path selected %u\n",
  233. __func__, path);
  234. return -EINVAL;
  235. }
  236. if (!of_find_property(dev->of_node, prop,
  237. &map_size)) {
  238. dev_err(dev, "missing port mapping prop %s\n", prop);
  239. ret = -EINVAL;
  240. goto err_port_map;
  241. }
  242. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  243. dt_array = kzalloc(map_size, GFP_KERNEL);
  244. if (!dt_array) {
  245. ret = -ENOMEM;
  246. goto err_alloc;
  247. }
  248. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  249. NUM_SWRS_DT_PARAMS * map_length);
  250. if (ret) {
  251. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  252. __func__, prop);
  253. goto err_pdata_fail;
  254. }
  255. for (i = 0; i < map_length; i++) {
  256. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  257. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  258. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  259. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  260. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  261. if (port_num != old_port_num)
  262. ch_iter = 0;
  263. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  264. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  265. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  266. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  267. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  268. old_port_num = port_num;
  269. }
  270. *num_ports = port_num;
  271. kfree(dt_array);
  272. return 0;
  273. err_pdata_fail:
  274. kfree(dt_array);
  275. err_alloc:
  276. err_port_map:
  277. return ret;
  278. }
  279. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  280. u8 slv_port_type, u8 enable)
  281. {
  282. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  283. u8 port_id, num_ch, ch_mask, port_type;
  284. u32 ch_rate;
  285. u8 num_port = 1;
  286. int ret = 0;
  287. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  288. &num_ch, &ch_mask, &ch_rate,
  289. &port_type, CODEC_TX);
  290. if (ret)
  291. return ret;
  292. if (enable)
  293. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  294. num_port, &ch_mask, &ch_rate,
  295. &num_ch, &port_type);
  296. else
  297. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  298. num_port, &ch_mask, &port_type);
  299. return ret;
  300. }
  301. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  302. u8 slv_port_type, u8 enable)
  303. {
  304. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  305. u8 port_id, num_ch, ch_mask, port_type;
  306. u32 ch_rate;
  307. u8 num_port = 1;
  308. int ret = 0;
  309. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  310. &num_ch, &ch_mask, &ch_rate,
  311. &port_type, CODEC_RX);
  312. if (ret)
  313. return ret;
  314. if (enable)
  315. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  316. num_port, &ch_mask, &ch_rate,
  317. &num_ch, &port_type);
  318. else
  319. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  320. num_port, &ch_mask, &port_type);
  321. return ret;
  322. }
  323. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  324. {
  325. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  326. if (wcd938x->rx_clk_cnt == 0) {
  327. snd_soc_component_update_bits(component,
  328. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  329. snd_soc_component_update_bits(component,
  330. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  331. snd_soc_component_update_bits(component,
  332. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  333. snd_soc_component_update_bits(component,
  334. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  335. snd_soc_component_update_bits(component,
  336. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  337. snd_soc_component_update_bits(component,
  338. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  339. snd_soc_component_update_bits(component,
  340. WCD938X_AUX_AUXPA, 0x10, 0x10);
  341. }
  342. wcd938x->rx_clk_cnt++;
  343. return 0;
  344. }
  345. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  346. {
  347. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  348. wcd938x->rx_clk_cnt--;
  349. if (wcd938x->rx_clk_cnt == 0) {
  350. snd_soc_component_update_bits(component,
  351. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  352. snd_soc_component_update_bits(component,
  353. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  354. snd_soc_component_update_bits(component,
  355. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  356. snd_soc_component_update_bits(component,
  357. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  358. snd_soc_component_update_bits(component,
  359. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  360. }
  361. return 0;
  362. }
  363. /*
  364. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  365. * @component: handle to snd_soc_component *
  366. *
  367. * return wcd938x_mbhc handle or error code in case of failure
  368. */
  369. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  370. {
  371. struct wcd938x_priv *wcd938x;
  372. if (!component) {
  373. pr_err("%s: Invalid params, NULL component\n", __func__);
  374. return NULL;
  375. }
  376. wcd938x = snd_soc_component_get_drvdata(component);
  377. if (!wcd938x) {
  378. pr_err("%s: wcd938x is NULL\n", __func__);
  379. return NULL;
  380. }
  381. return wcd938x->mbhc;
  382. }
  383. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  384. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  385. struct snd_kcontrol *kcontrol,
  386. int event)
  387. {
  388. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  389. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  390. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  391. w->name, event);
  392. switch (event) {
  393. case SND_SOC_DAPM_PRE_PMU:
  394. wcd938x_rx_clk_enable(component);
  395. snd_soc_component_update_bits(component,
  396. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  397. snd_soc_component_update_bits(component,
  398. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  399. snd_soc_component_update_bits(component,
  400. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  401. break;
  402. case SND_SOC_DAPM_POST_PMU:
  403. snd_soc_component_update_bits(component,
  404. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  405. if (wcd938x->comp1_enable) {
  406. snd_soc_component_update_bits(component,
  407. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  408. /* 5msec compander delay as per HW requirement */
  409. if (!wcd938x->comp2_enable ||
  410. (snd_soc_component_read32(component,
  411. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  412. usleep_range(5000, 5010);
  413. snd_soc_component_update_bits(component,
  414. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  415. } else {
  416. snd_soc_component_update_bits(component,
  417. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  418. 0x02, 0x00);
  419. snd_soc_component_update_bits(component,
  420. WCD938X_HPH_L_EN, 0x20, 0x20);
  421. }
  422. break;
  423. case SND_SOC_DAPM_POST_PMD:
  424. snd_soc_component_update_bits(component,
  425. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  426. 0x0F, 0x01);
  427. break;
  428. }
  429. return 0;
  430. }
  431. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  432. struct snd_kcontrol *kcontrol,
  433. int event)
  434. {
  435. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  436. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  437. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  438. w->name, event);
  439. switch (event) {
  440. case SND_SOC_DAPM_PRE_PMU:
  441. wcd938x_rx_clk_enable(component);
  442. snd_soc_component_update_bits(component,
  443. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  444. snd_soc_component_update_bits(component,
  445. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  446. snd_soc_component_update_bits(component,
  447. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  448. break;
  449. case SND_SOC_DAPM_POST_PMU:
  450. snd_soc_component_update_bits(component,
  451. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  452. if (wcd938x->comp2_enable) {
  453. snd_soc_component_update_bits(component,
  454. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  455. /* 5msec compander delay as per HW requirement */
  456. if (!wcd938x->comp1_enable ||
  457. (snd_soc_component_read32(component,
  458. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  459. usleep_range(5000, 5010);
  460. snd_soc_component_update_bits(component,
  461. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  462. } else {
  463. snd_soc_component_update_bits(component,
  464. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  465. 0x01, 0x00);
  466. snd_soc_component_update_bits(component,
  467. WCD938X_HPH_R_EN, 0x20, 0x20);
  468. }
  469. break;
  470. case SND_SOC_DAPM_POST_PMD:
  471. snd_soc_component_update_bits(component,
  472. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  473. 0x0F, 0x01);
  474. break;
  475. }
  476. return 0;
  477. }
  478. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  479. struct snd_kcontrol *kcontrol,
  480. int event)
  481. {
  482. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  483. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  484. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  485. w->name, event);
  486. switch (event) {
  487. case SND_SOC_DAPM_PRE_PMU:
  488. wcd938x_rx_clk_enable(component);
  489. snd_soc_component_update_bits(component,
  490. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  491. snd_soc_component_update_bits(component,
  492. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  493. snd_soc_component_update_bits(component,
  494. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  495. /* 5 msec delay as per HW requirement */
  496. usleep_range(5000, 5010);
  497. if (wcd938x->flyback_cur_det_disable == 0)
  498. snd_soc_component_update_bits(component,
  499. WCD938X_FLYBACK_EN,
  500. 0x04, 0x00);
  501. wcd938x->flyback_cur_det_disable++;
  502. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  503. WCD_CLSH_EVENT_PRE_DAC,
  504. WCD_CLSH_STATE_EAR,
  505. wcd938x->hph_mode);
  506. break;
  507. case SND_SOC_DAPM_POST_PMD:
  508. break;
  509. };
  510. return 0;
  511. }
  512. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  513. struct snd_kcontrol *kcontrol,
  514. int event)
  515. {
  516. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  517. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  518. int ret = 0;
  519. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  520. w->name, event);
  521. switch (event) {
  522. case SND_SOC_DAPM_PRE_PMU:
  523. wcd938x_rx_clk_enable(component);
  524. snd_soc_component_update_bits(component,
  525. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  526. snd_soc_component_update_bits(component,
  527. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  528. snd_soc_component_update_bits(component,
  529. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  530. if (wcd938x->flyback_cur_det_disable == 0)
  531. snd_soc_component_update_bits(component,
  532. WCD938X_FLYBACK_EN,
  533. 0x04, 0x00);
  534. wcd938x->flyback_cur_det_disable++;
  535. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  536. WCD_CLSH_EVENT_PRE_DAC,
  537. WCD_CLSH_STATE_AUX,
  538. wcd938x->hph_mode);
  539. break;
  540. case SND_SOC_DAPM_POST_PMD:
  541. snd_soc_component_update_bits(component,
  542. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  543. break;
  544. };
  545. return ret;
  546. }
  547. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  548. struct snd_kcontrol *kcontrol,
  549. int event)
  550. {
  551. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  552. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  553. int ret = 0;
  554. int hph_mode = wcd938x->hph_mode;
  555. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  556. w->name, event);
  557. switch (event) {
  558. case SND_SOC_DAPM_PRE_PMU:
  559. if (wcd938x->ldoh)
  560. snd_soc_component_update_bits(component,
  561. WCD938X_LDOH_MODE,
  562. 0x80, 0x80);
  563. if (wcd938x->update_wcd_event)
  564. wcd938x->update_wcd_event(wcd938x->handle,
  565. WCD_BOLERO_EVT_RX_MUTE,
  566. (WCD_RX2 << 0x10 | 0x1));
  567. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  568. wcd938x->rx_swr_dev->dev_num,
  569. true);
  570. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  571. WCD_CLSH_EVENT_PRE_DAC,
  572. WCD_CLSH_STATE_HPHR,
  573. hph_mode);
  574. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  575. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  576. 0x10, 0x10);
  577. wcd_clsh_set_hph_mode(component, hph_mode);
  578. /* 100 usec delay as per HW requirement */
  579. usleep_range(100, 110);
  580. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  581. snd_soc_component_update_bits(component,
  582. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  583. break;
  584. case SND_SOC_DAPM_POST_PMU:
  585. /*
  586. * 7ms sleep is required if compander is enabled as per
  587. * HW requirement. If compander is disabled, then
  588. * 20ms delay is required.
  589. */
  590. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  591. if (!wcd938x->comp2_enable)
  592. usleep_range(20000, 20100);
  593. else
  594. usleep_range(7000, 7100);
  595. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  596. }
  597. snd_soc_component_update_bits(component,
  598. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  599. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  600. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  601. snd_soc_component_update_bits(component,
  602. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  603. if (wcd938x->update_wcd_event)
  604. wcd938x->update_wcd_event(wcd938x->handle,
  605. WCD_BOLERO_EVT_RX_MUTE,
  606. (WCD_RX2 << 0x10));
  607. wcd_enable_irq(&wcd938x->irq_info,
  608. WCD938X_IRQ_HPHR_PDM_WD_INT);
  609. break;
  610. case SND_SOC_DAPM_PRE_PMD:
  611. if (wcd938x->update_wcd_event)
  612. wcd938x->update_wcd_event(wcd938x->handle,
  613. WCD_BOLERO_EVT_RX_MUTE,
  614. (WCD_RX2 << 0x10 | 0x1));
  615. wcd_disable_irq(&wcd938x->irq_info,
  616. WCD938X_IRQ_HPHR_PDM_WD_INT);
  617. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  618. wcd938x->update_wcd_event(wcd938x->handle,
  619. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  620. (WCD_RX2 << 0x10));
  621. /*
  622. * 7ms sleep is required if compander is enabled as per
  623. * HW requirement. If compander is disabled, then
  624. * 20ms delay is required.
  625. */
  626. if (!wcd938x->comp2_enable)
  627. usleep_range(20000, 20100);
  628. else
  629. usleep_range(7000, 7100);
  630. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  631. 0x40, 0x00);
  632. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  633. WCD_EVENT_PRE_HPHR_PA_OFF,
  634. &wcd938x->mbhc->wcd_mbhc);
  635. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  636. break;
  637. case SND_SOC_DAPM_POST_PMD:
  638. /*
  639. * 7ms sleep is required if compander is enabled as per
  640. * HW requirement. If compander is disabled, then
  641. * 20ms delay is required.
  642. */
  643. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  644. if (!wcd938x->comp2_enable)
  645. usleep_range(20000, 20100);
  646. else
  647. usleep_range(7000, 7100);
  648. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  649. }
  650. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  651. WCD_EVENT_POST_HPHR_PA_OFF,
  652. &wcd938x->mbhc->wcd_mbhc);
  653. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  654. 0x10, 0x00);
  655. snd_soc_component_update_bits(component,
  656. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  657. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  658. WCD_CLSH_EVENT_POST_PA,
  659. WCD_CLSH_STATE_HPHR,
  660. hph_mode);
  661. if (wcd938x->ldoh)
  662. snd_soc_component_update_bits(component,
  663. WCD938X_LDOH_MODE,
  664. 0x80, 0x00);
  665. break;
  666. };
  667. return ret;
  668. }
  669. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  670. struct snd_kcontrol *kcontrol,
  671. int event)
  672. {
  673. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  674. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  675. int ret = 0;
  676. int hph_mode = wcd938x->hph_mode;
  677. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  678. w->name, event);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. if (wcd938x->ldoh)
  682. snd_soc_component_update_bits(component,
  683. WCD938X_LDOH_MODE,
  684. 0x80, 0x80);
  685. if (wcd938x->update_wcd_event)
  686. wcd938x->update_wcd_event(wcd938x->handle,
  687. WCD_BOLERO_EVT_RX_MUTE,
  688. (WCD_RX1 << 0x10 | 0x01));
  689. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  690. wcd938x->rx_swr_dev->dev_num,
  691. true);
  692. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  693. WCD_CLSH_EVENT_PRE_DAC,
  694. WCD_CLSH_STATE_HPHL,
  695. hph_mode);
  696. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  697. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  698. 0x20, 0x20);
  699. wcd_clsh_set_hph_mode(component, hph_mode);
  700. /* 100 usec delay as per HW requirement */
  701. usleep_range(100, 110);
  702. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  703. snd_soc_component_update_bits(component,
  704. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  705. break;
  706. case SND_SOC_DAPM_POST_PMU:
  707. /*
  708. * 7ms sleep is required if compander is enabled as per
  709. * HW requirement. If compander is disabled, then
  710. * 20ms delay is required.
  711. */
  712. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  713. if (!wcd938x->comp1_enable)
  714. usleep_range(20000, 20100);
  715. else
  716. usleep_range(7000, 7100);
  717. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  718. }
  719. snd_soc_component_update_bits(component,
  720. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  721. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  722. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  723. snd_soc_component_update_bits(component,
  724. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  725. if (wcd938x->update_wcd_event)
  726. wcd938x->update_wcd_event(wcd938x->handle,
  727. WCD_BOLERO_EVT_RX_MUTE,
  728. (WCD_RX1 << 0x10));
  729. wcd_enable_irq(&wcd938x->irq_info,
  730. WCD938X_IRQ_HPHL_PDM_WD_INT);
  731. break;
  732. case SND_SOC_DAPM_PRE_PMD:
  733. if (wcd938x->update_wcd_event)
  734. wcd938x->update_wcd_event(wcd938x->handle,
  735. WCD_BOLERO_EVT_RX_MUTE,
  736. (WCD_RX1 << 0x10 | 0x1));
  737. wcd_disable_irq(&wcd938x->irq_info,
  738. WCD938X_IRQ_HPHL_PDM_WD_INT);
  739. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  742. (WCD_RX1 << 0x10));
  743. /*
  744. * 7ms sleep is required if compander is enabled as per
  745. * HW requirement. If compander is disabled, then
  746. * 20ms delay is required.
  747. */
  748. if (!wcd938x->comp1_enable)
  749. usleep_range(20000, 20100);
  750. else
  751. usleep_range(7000, 7100);
  752. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  753. 0x80, 0x00);
  754. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  755. WCD_EVENT_PRE_HPHL_PA_OFF,
  756. &wcd938x->mbhc->wcd_mbhc);
  757. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  758. break;
  759. case SND_SOC_DAPM_POST_PMD:
  760. /*
  761. * 7ms sleep is required if compander is enabled as per
  762. * HW requirement. If compander is disabled, then
  763. * 20ms delay is required.
  764. */
  765. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  766. if (!wcd938x->comp1_enable)
  767. usleep_range(21000, 21100);
  768. else
  769. usleep_range(7000, 7100);
  770. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  771. }
  772. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  773. WCD_EVENT_POST_HPHL_PA_OFF,
  774. &wcd938x->mbhc->wcd_mbhc);
  775. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  776. 0x20, 0x00);
  777. snd_soc_component_update_bits(component,
  778. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  779. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  780. WCD_CLSH_EVENT_POST_PA,
  781. WCD_CLSH_STATE_HPHL,
  782. hph_mode);
  783. if (wcd938x->ldoh)
  784. snd_soc_component_update_bits(component,
  785. WCD938X_LDOH_MODE,
  786. 0x80, 0x00);
  787. break;
  788. };
  789. return ret;
  790. }
  791. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  792. struct snd_kcontrol *kcontrol,
  793. int event)
  794. {
  795. struct snd_soc_component *component =
  796. snd_soc_dapm_to_component(w->dapm);
  797. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  798. int hph_mode = wcd938x->hph_mode;
  799. int ret = 0;
  800. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  801. w->name, event);
  802. switch (event) {
  803. case SND_SOC_DAPM_PRE_PMU:
  804. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  805. wcd938x->rx_swr_dev->dev_num,
  806. true);
  807. snd_soc_component_update_bits(component,
  808. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  809. break;
  810. case SND_SOC_DAPM_POST_PMU:
  811. /* 1 msec delay as per HW requirement */
  812. usleep_range(1000, 1010);
  813. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  814. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  815. snd_soc_component_update_bits(component,
  816. WCD938X_ANA_RX_SUPPLIES,
  817. 0x02, 0x02);
  818. if (wcd938x->update_wcd_event)
  819. wcd938x->update_wcd_event(wcd938x->handle,
  820. WCD_BOLERO_EVT_RX_MUTE,
  821. (WCD_RX3 << 0x10));
  822. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  823. break;
  824. case SND_SOC_DAPM_PRE_PMD:
  825. wcd_disable_irq(&wcd938x->irq_info,
  826. WCD938X_IRQ_AUX_PDM_WD_INT);
  827. if (wcd938x->update_wcd_event)
  828. wcd938x->update_wcd_event(wcd938x->handle,
  829. WCD_BOLERO_EVT_RX_MUTE,
  830. (WCD_RX3 << 0x10 | 0x1));
  831. break;
  832. case SND_SOC_DAPM_POST_PMD:
  833. /* 1 msec delay as per HW requirement */
  834. usleep_range(1000, 1010);
  835. snd_soc_component_update_bits(component,
  836. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  837. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  838. WCD_CLSH_EVENT_POST_PA,
  839. WCD_CLSH_STATE_AUX,
  840. hph_mode);
  841. wcd938x->flyback_cur_det_disable--;
  842. if (wcd938x->flyback_cur_det_disable == 0)
  843. snd_soc_component_update_bits(component,
  844. WCD938X_FLYBACK_EN,
  845. 0x04, 0x04);
  846. break;
  847. };
  848. return ret;
  849. }
  850. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  851. struct snd_kcontrol *kcontrol,
  852. int event)
  853. {
  854. struct snd_soc_component *component =
  855. snd_soc_dapm_to_component(w->dapm);
  856. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  857. int hph_mode = wcd938x->hph_mode;
  858. int ret = 0;
  859. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  860. w->name, event);
  861. switch (event) {
  862. case SND_SOC_DAPM_PRE_PMU:
  863. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  864. wcd938x->rx_swr_dev->dev_num,
  865. true);
  866. /*
  867. * Enable watchdog interrupt for HPHL or AUX
  868. * depending on mux value
  869. */
  870. wcd938x->ear_rx_path =
  871. snd_soc_component_read32(
  872. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  873. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  874. snd_soc_component_update_bits(component,
  875. WCD938X_DIGITAL_PDM_WD_CTL2,
  876. 0x05, 0x05);
  877. else
  878. snd_soc_component_update_bits(component,
  879. WCD938X_DIGITAL_PDM_WD_CTL0,
  880. 0x17, 0x13);
  881. break;
  882. case SND_SOC_DAPM_POST_PMU:
  883. /* 6 msec delay as per HW requirement */
  884. usleep_range(6000, 6010);
  885. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  886. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  887. snd_soc_component_update_bits(component,
  888. WCD938X_ANA_RX_SUPPLIES,
  889. 0x02, 0x02);
  890. if (wcd938x->update_wcd_event)
  891. wcd938x->update_wcd_event(wcd938x->handle,
  892. WCD_BOLERO_EVT_RX_MUTE,
  893. (WCD_RX1 << 0x10));
  894. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  895. wcd_enable_irq(&wcd938x->irq_info,
  896. WCD938X_IRQ_AUX_PDM_WD_INT);
  897. else
  898. wcd_enable_irq(&wcd938x->irq_info,
  899. WCD938X_IRQ_HPHL_PDM_WD_INT);
  900. break;
  901. case SND_SOC_DAPM_PRE_PMD:
  902. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  903. wcd_disable_irq(&wcd938x->irq_info,
  904. WCD938X_IRQ_AUX_PDM_WD_INT);
  905. else
  906. wcd_disable_irq(&wcd938x->irq_info,
  907. WCD938X_IRQ_HPHL_PDM_WD_INT);
  908. if (wcd938x->update_wcd_event)
  909. wcd938x->update_wcd_event(wcd938x->handle,
  910. WCD_BOLERO_EVT_RX_MUTE,
  911. (WCD_RX1 << 0x10 | 0x1));
  912. break;
  913. case SND_SOC_DAPM_POST_PMD:
  914. /* 7 msec delay as per HW requirement */
  915. usleep_range(7000, 7010);
  916. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  917. snd_soc_component_update_bits(component,
  918. WCD938X_DIGITAL_PDM_WD_CTL2,
  919. 0x05, 0x00);
  920. else
  921. snd_soc_component_update_bits(component,
  922. WCD938X_DIGITAL_PDM_WD_CTL0,
  923. 0x17, 0x00);
  924. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  925. WCD_CLSH_EVENT_POST_PA,
  926. WCD_CLSH_STATE_EAR,
  927. hph_mode);
  928. wcd938x->flyback_cur_det_disable--;
  929. if (wcd938x->flyback_cur_det_disable == 0)
  930. snd_soc_component_update_bits(component,
  931. WCD938X_FLYBACK_EN,
  932. 0x04, 0x04);
  933. break;
  934. };
  935. return ret;
  936. }
  937. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  938. struct snd_kcontrol *kcontrol,
  939. int event)
  940. {
  941. struct snd_soc_component *component =
  942. snd_soc_dapm_to_component(w->dapm);
  943. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  944. int mode = wcd938x->hph_mode;
  945. int ret = 0;
  946. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  947. w->name, event);
  948. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  949. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  950. wcd938x_rx_connect_port(component, CLSH,
  951. SND_SOC_DAPM_EVENT_ON(event));
  952. }
  953. if (SND_SOC_DAPM_EVENT_OFF(event))
  954. ret = swr_slvdev_datapath_control(
  955. wcd938x->rx_swr_dev,
  956. wcd938x->rx_swr_dev->dev_num,
  957. false);
  958. return ret;
  959. }
  960. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  961. struct snd_kcontrol *kcontrol,
  962. int event)
  963. {
  964. struct snd_soc_component *component =
  965. snd_soc_dapm_to_component(w->dapm);
  966. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  967. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  968. w->name, event);
  969. switch (event) {
  970. case SND_SOC_DAPM_PRE_PMU:
  971. wcd938x_rx_connect_port(component, HPH_L, true);
  972. if (wcd938x->comp1_enable)
  973. wcd938x_rx_connect_port(component, COMP_L, true);
  974. break;
  975. case SND_SOC_DAPM_POST_PMD:
  976. wcd938x_rx_connect_port(component, HPH_L, false);
  977. if (wcd938x->comp1_enable)
  978. wcd938x_rx_connect_port(component, COMP_L, false);
  979. wcd938x_rx_clk_disable(component);
  980. snd_soc_component_update_bits(component,
  981. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  982. 0x01, 0x00);
  983. break;
  984. };
  985. return 0;
  986. }
  987. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  988. struct snd_kcontrol *kcontrol, int event)
  989. {
  990. struct snd_soc_component *component =
  991. snd_soc_dapm_to_component(w->dapm);
  992. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  993. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  994. w->name, event);
  995. switch (event) {
  996. case SND_SOC_DAPM_PRE_PMU:
  997. wcd938x_rx_connect_port(component, HPH_R, true);
  998. if (wcd938x->comp2_enable)
  999. wcd938x_rx_connect_port(component, COMP_R, true);
  1000. break;
  1001. case SND_SOC_DAPM_POST_PMD:
  1002. wcd938x_rx_connect_port(component, HPH_R, false);
  1003. if (wcd938x->comp2_enable)
  1004. wcd938x_rx_connect_port(component, COMP_R, false);
  1005. wcd938x_rx_clk_disable(component);
  1006. snd_soc_component_update_bits(component,
  1007. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1008. 0x02, 0x00);
  1009. break;
  1010. };
  1011. return 0;
  1012. }
  1013. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1014. struct snd_kcontrol *kcontrol,
  1015. int event)
  1016. {
  1017. struct snd_soc_component *component =
  1018. snd_soc_dapm_to_component(w->dapm);
  1019. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1020. w->name, event);
  1021. switch (event) {
  1022. case SND_SOC_DAPM_PRE_PMU:
  1023. wcd938x_rx_connect_port(component, LO, true);
  1024. break;
  1025. case SND_SOC_DAPM_POST_PMD:
  1026. wcd938x_rx_connect_port(component, LO, false);
  1027. /* 6 msec delay as per HW requirement */
  1028. usleep_range(6000, 6010);
  1029. wcd938x_rx_clk_disable(component);
  1030. snd_soc_component_update_bits(component,
  1031. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1032. break;
  1033. }
  1034. return 0;
  1035. }
  1036. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1037. struct snd_kcontrol *kcontrol,
  1038. int event)
  1039. {
  1040. struct snd_soc_component *component =
  1041. snd_soc_dapm_to_component(w->dapm);
  1042. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1043. u16 dmic_clk_reg, dmic_clk_en_reg;
  1044. s32 *dmic_clk_cnt;
  1045. u8 dmic_ctl_shift = 0;
  1046. u8 dmic_clk_shift = 0;
  1047. u8 dmic_clk_mask = 0;
  1048. u16 dmic2_left_en = 0;
  1049. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1050. w->name, event);
  1051. switch (w->shift) {
  1052. case 0:
  1053. case 1:
  1054. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1055. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1056. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1057. dmic_clk_mask = 0x0F;
  1058. dmic_clk_shift = 0x00;
  1059. dmic_ctl_shift = 0x00;
  1060. break;
  1061. case 2:
  1062. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1063. case 3:
  1064. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1065. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1066. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1067. dmic_clk_mask = 0xF0;
  1068. dmic_clk_shift = 0x04;
  1069. dmic_ctl_shift = 0x01;
  1070. break;
  1071. case 4:
  1072. case 5:
  1073. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1074. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1075. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1076. dmic_clk_mask = 0x0F;
  1077. dmic_clk_shift = 0x00;
  1078. dmic_ctl_shift = 0x02;
  1079. break;
  1080. case 6:
  1081. case 7:
  1082. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1083. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1084. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1085. dmic_clk_mask = 0xF0;
  1086. dmic_clk_shift = 0x04;
  1087. dmic_ctl_shift = 0x03;
  1088. break;
  1089. default:
  1090. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1091. __func__);
  1092. return -EINVAL;
  1093. };
  1094. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1095. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1096. switch (event) {
  1097. case SND_SOC_DAPM_PRE_PMU:
  1098. snd_soc_component_update_bits(component,
  1099. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1100. (0x01 << dmic_ctl_shift), 0x00);
  1101. /* 250us sleep as per HW requirement */
  1102. usleep_range(250, 260);
  1103. if (dmic2_left_en)
  1104. snd_soc_component_update_bits(component,
  1105. dmic2_left_en, 0x80, 0x80);
  1106. /* Setting DMIC clock rate to 2.4MHz */
  1107. snd_soc_component_update_bits(component,
  1108. dmic_clk_reg, dmic_clk_mask,
  1109. (0x03 << dmic_clk_shift));
  1110. snd_soc_component_update_bits(component,
  1111. dmic_clk_en_reg, 0x08, 0x08);
  1112. /* enable clock scaling */
  1113. snd_soc_component_update_bits(component,
  1114. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1115. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1116. break;
  1117. case SND_SOC_DAPM_POST_PMD:
  1118. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1119. snd_soc_component_update_bits(component,
  1120. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1121. (0x01 << dmic_ctl_shift),
  1122. (0x01 << dmic_ctl_shift));
  1123. if (dmic2_left_en)
  1124. snd_soc_component_update_bits(component,
  1125. dmic2_left_en, 0x80, 0x00);
  1126. snd_soc_component_update_bits(component,
  1127. dmic_clk_en_reg, 0x08, 0x00);
  1128. break;
  1129. };
  1130. return 0;
  1131. }
  1132. /*
  1133. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1134. * @micb_mv: micbias in mv
  1135. *
  1136. * return register value converted
  1137. */
  1138. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1139. {
  1140. /* min micbias voltage is 1V and maximum is 2.85V */
  1141. if (micb_mv < 1000 || micb_mv > 2850) {
  1142. pr_err("%s: unsupported micbias voltage\n", __func__);
  1143. return -EINVAL;
  1144. }
  1145. return (micb_mv - 1000) / 50;
  1146. }
  1147. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1148. /*
  1149. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1150. * @component: handle to snd_soc_component *
  1151. * @req_volt: micbias voltage to be set
  1152. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1153. *
  1154. * return 0 if adjustment is success or error code in case of failure
  1155. */
  1156. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1157. int req_volt, int micb_num)
  1158. {
  1159. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1160. int cur_vout_ctl, req_vout_ctl;
  1161. int micb_reg, micb_val, micb_en;
  1162. int ret = 0;
  1163. switch (micb_num) {
  1164. case MIC_BIAS_1:
  1165. micb_reg = WCD938X_ANA_MICB1;
  1166. break;
  1167. case MIC_BIAS_2:
  1168. micb_reg = WCD938X_ANA_MICB2;
  1169. break;
  1170. case MIC_BIAS_3:
  1171. micb_reg = WCD938X_ANA_MICB3;
  1172. break;
  1173. case MIC_BIAS_4:
  1174. micb_reg = WCD938X_ANA_MICB4;
  1175. break;
  1176. default:
  1177. return -EINVAL;
  1178. }
  1179. mutex_lock(&wcd938x->micb_lock);
  1180. /*
  1181. * If requested micbias voltage is same as current micbias
  1182. * voltage, then just return. Otherwise, adjust voltage as
  1183. * per requested value. If micbias is already enabled, then
  1184. * to avoid slow micbias ramp-up or down enable pull-up
  1185. * momentarily, change the micbias value and then re-enable
  1186. * micbias.
  1187. */
  1188. micb_val = snd_soc_component_read32(component, micb_reg);
  1189. micb_en = (micb_val & 0xC0) >> 6;
  1190. cur_vout_ctl = micb_val & 0x3F;
  1191. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1192. if (req_vout_ctl < 0) {
  1193. ret = -EINVAL;
  1194. goto exit;
  1195. }
  1196. if (cur_vout_ctl == req_vout_ctl) {
  1197. ret = 0;
  1198. goto exit;
  1199. }
  1200. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1201. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1202. req_volt, micb_en);
  1203. if (micb_en == 0x1)
  1204. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1205. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1206. if (micb_en == 0x1) {
  1207. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1208. /*
  1209. * Add 2ms delay as per HW requirement after enabling
  1210. * micbias
  1211. */
  1212. usleep_range(2000, 2100);
  1213. }
  1214. exit:
  1215. mutex_unlock(&wcd938x->micb_lock);
  1216. return ret;
  1217. }
  1218. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1219. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1220. struct snd_kcontrol *kcontrol,
  1221. int event)
  1222. {
  1223. struct snd_soc_component *component =
  1224. snd_soc_dapm_to_component(w->dapm);
  1225. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1226. int ret = 0;
  1227. switch (event) {
  1228. case SND_SOC_DAPM_PRE_PMU:
  1229. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1230. wcd938x->tx_swr_dev->dev_num,
  1231. true);
  1232. break;
  1233. case SND_SOC_DAPM_POST_PMD:
  1234. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1235. wcd938x->tx_swr_dev->dev_num,
  1236. false);
  1237. break;
  1238. };
  1239. return ret;
  1240. }
  1241. static int wcd938x_get_adc_mode(int val)
  1242. {
  1243. int ret = 0;
  1244. switch (val) {
  1245. case ADC_MODE_INVALID:
  1246. ret = ADC_MODE_VAL_NORMAL;
  1247. break;
  1248. case ADC_MODE_HIFI:
  1249. ret = ADC_MODE_VAL_HIFI;
  1250. break;
  1251. case ADC_MODE_LO_HIF:
  1252. ret = ADC_MODE_VAL_LO_HIF;
  1253. break;
  1254. case ADC_MODE_NORMAL:
  1255. ret = ADC_MODE_VAL_NORMAL;
  1256. break;
  1257. case ADC_MODE_LP:
  1258. ret = ADC_MODE_VAL_LP;
  1259. break;
  1260. case ADC_MODE_ULP1:
  1261. ret = ADC_MODE_VAL_ULP1;
  1262. break;
  1263. case ADC_MODE_ULP2:
  1264. ret = ADC_MODE_VAL_ULP2;
  1265. break;
  1266. default:
  1267. ret = -EINVAL;
  1268. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1269. break;
  1270. }
  1271. return ret;
  1272. }
  1273. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1274. struct snd_kcontrol *kcontrol,
  1275. int event){
  1276. struct snd_soc_component *component =
  1277. snd_soc_dapm_to_component(w->dapm);
  1278. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1279. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1280. w->name, event);
  1281. switch (event) {
  1282. case SND_SOC_DAPM_PRE_PMU:
  1283. snd_soc_component_update_bits(component,
  1284. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1285. snd_soc_component_update_bits(component,
  1286. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1287. set_bit(w->shift, &wcd938x->status_mask);
  1288. /* Enable BCS for Headset mic */
  1289. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1290. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1291. wcd938x_tx_connect_port(component, MBHC, true);
  1292. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1293. }
  1294. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1295. break;
  1296. case SND_SOC_DAPM_POST_PMD:
  1297. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1298. if (w->shift == 1 &&
  1299. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1300. wcd938x_tx_connect_port(component, MBHC, false);
  1301. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1302. }
  1303. snd_soc_component_update_bits(component,
  1304. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1305. clear_bit(w->shift, &wcd938x->status_mask);
  1306. break;
  1307. };
  1308. return 0;
  1309. }
  1310. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1311. int channel, int mode)
  1312. {
  1313. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1314. int ret = 0;
  1315. switch (channel) {
  1316. case 0:
  1317. reg = WCD938X_ANA_TX_CH2;
  1318. mask = 0x40;
  1319. break;
  1320. case 1:
  1321. reg = WCD938X_ANA_TX_CH2;
  1322. mask = 0x20;
  1323. break;
  1324. case 2:
  1325. reg = WCD938X_ANA_TX_CH4;
  1326. mask = 0x40;
  1327. break;
  1328. case 3:
  1329. reg = WCD938X_ANA_TX_CH4;
  1330. mask = 0x20;
  1331. break;
  1332. default:
  1333. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1334. ret = -EINVAL;
  1335. break;
  1336. }
  1337. if (!mode)
  1338. val = 0x00;
  1339. else
  1340. val = mask;
  1341. if (!ret)
  1342. snd_soc_component_update_bits(component, reg, mask, val);
  1343. return ret;
  1344. }
  1345. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1346. struct snd_kcontrol *kcontrol, int event)
  1347. {
  1348. struct snd_soc_component *component =
  1349. snd_soc_dapm_to_component(w->dapm);
  1350. int mode;
  1351. int ret = 0;
  1352. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1353. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1354. w->name, event);
  1355. switch (event) {
  1356. case SND_SOC_DAPM_PRE_PMU:
  1357. snd_soc_component_update_bits(component,
  1358. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1359. snd_soc_component_update_bits(component,
  1360. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1361. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1362. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1363. if (mode < 0) {
  1364. dev_info(component->dev,
  1365. "%s: invalid mode, setting to normal mode\n",
  1366. __func__);
  1367. mode = ADC_MODE_VAL_NORMAL;
  1368. }
  1369. switch (w->shift) {
  1370. case 0:
  1371. snd_soc_component_update_bits(component,
  1372. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1373. mode);
  1374. snd_soc_component_update_bits(component,
  1375. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1376. break;
  1377. case 1:
  1378. snd_soc_component_update_bits(component,
  1379. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1380. mode << 4);
  1381. snd_soc_component_update_bits(component,
  1382. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1383. break;
  1384. case 2:
  1385. snd_soc_component_update_bits(component,
  1386. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1387. mode);
  1388. snd_soc_component_update_bits(component,
  1389. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1390. break;
  1391. case 3:
  1392. snd_soc_component_update_bits(component,
  1393. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1394. mode << 4);
  1395. snd_soc_component_update_bits(component,
  1396. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1397. break;
  1398. default:
  1399. break;
  1400. }
  1401. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1402. break;
  1403. case SND_SOC_DAPM_POST_PMD:
  1404. switch (w->shift) {
  1405. case 0:
  1406. snd_soc_component_update_bits(component,
  1407. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1408. break;
  1409. case 1:
  1410. snd_soc_component_update_bits(component,
  1411. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1412. break;
  1413. case 2:
  1414. snd_soc_component_update_bits(component,
  1415. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1416. break;
  1417. case 3:
  1418. snd_soc_component_update_bits(component,
  1419. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1420. break;
  1421. default:
  1422. break;
  1423. }
  1424. snd_soc_component_update_bits(component,
  1425. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1426. break;
  1427. };
  1428. return ret;
  1429. }
  1430. int wcd938x_micbias_control(struct snd_soc_component *component,
  1431. int micb_num, int req, bool is_dapm)
  1432. {
  1433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1434. int micb_index = micb_num - 1;
  1435. u16 micb_reg;
  1436. int pre_off_event = 0, post_off_event = 0;
  1437. int post_on_event = 0, post_dapm_off = 0;
  1438. int post_dapm_on = 0;
  1439. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1440. dev_err(component->dev,
  1441. "%s: Invalid micbias index, micb_ind:%d\n",
  1442. __func__, micb_index);
  1443. return -EINVAL;
  1444. }
  1445. if (NULL == wcd938x) {
  1446. dev_err(component->dev,
  1447. "%s: wcd938x private data is NULL\n", __func__);
  1448. return -EINVAL;
  1449. }
  1450. switch (micb_num) {
  1451. case MIC_BIAS_1:
  1452. micb_reg = WCD938X_ANA_MICB1;
  1453. break;
  1454. case MIC_BIAS_2:
  1455. micb_reg = WCD938X_ANA_MICB2;
  1456. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1457. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1458. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1459. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1460. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1461. break;
  1462. case MIC_BIAS_3:
  1463. micb_reg = WCD938X_ANA_MICB3;
  1464. break;
  1465. case MIC_BIAS_4:
  1466. micb_reg = WCD938X_ANA_MICB4;
  1467. break;
  1468. default:
  1469. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1470. __func__, micb_num);
  1471. return -EINVAL;
  1472. };
  1473. mutex_lock(&wcd938x->micb_lock);
  1474. switch (req) {
  1475. case MICB_PULLUP_ENABLE:
  1476. wcd938x->pullup_ref[micb_index]++;
  1477. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1478. (wcd938x->micb_ref[micb_index] == 0))
  1479. snd_soc_component_update_bits(component, micb_reg,
  1480. 0xC0, 0x80);
  1481. break;
  1482. case MICB_PULLUP_DISABLE:
  1483. if (wcd938x->pullup_ref[micb_index] > 0)
  1484. wcd938x->pullup_ref[micb_index]--;
  1485. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1486. (wcd938x->micb_ref[micb_index] == 0))
  1487. snd_soc_component_update_bits(component, micb_reg,
  1488. 0xC0, 0x00);
  1489. break;
  1490. case MICB_ENABLE:
  1491. wcd938x->micb_ref[micb_index]++;
  1492. if (wcd938x->micb_ref[micb_index] == 1) {
  1493. snd_soc_component_update_bits(component,
  1494. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1495. snd_soc_component_update_bits(component,
  1496. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1497. snd_soc_component_update_bits(component,
  1498. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1499. snd_soc_component_update_bits(component,
  1500. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1501. snd_soc_component_update_bits(component,
  1502. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1503. snd_soc_component_update_bits(component,
  1504. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1505. snd_soc_component_update_bits(component,
  1506. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1507. snd_soc_component_update_bits(component,
  1508. micb_reg, 0xC0, 0x40);
  1509. if (post_on_event)
  1510. blocking_notifier_call_chain(
  1511. &wcd938x->mbhc->notifier,
  1512. post_on_event,
  1513. &wcd938x->mbhc->wcd_mbhc);
  1514. }
  1515. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1516. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1517. post_dapm_on,
  1518. &wcd938x->mbhc->wcd_mbhc);
  1519. break;
  1520. case MICB_DISABLE:
  1521. if (wcd938x->micb_ref[micb_index] > 0)
  1522. wcd938x->micb_ref[micb_index]--;
  1523. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1524. (wcd938x->pullup_ref[micb_index] > 0))
  1525. snd_soc_component_update_bits(component, micb_reg,
  1526. 0xC0, 0x80);
  1527. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1528. (wcd938x->pullup_ref[micb_index] == 0)) {
  1529. if (pre_off_event && wcd938x->mbhc)
  1530. blocking_notifier_call_chain(
  1531. &wcd938x->mbhc->notifier,
  1532. pre_off_event,
  1533. &wcd938x->mbhc->wcd_mbhc);
  1534. snd_soc_component_update_bits(component, micb_reg,
  1535. 0xC0, 0x00);
  1536. if (post_off_event && wcd938x->mbhc)
  1537. blocking_notifier_call_chain(
  1538. &wcd938x->mbhc->notifier,
  1539. post_off_event,
  1540. &wcd938x->mbhc->wcd_mbhc);
  1541. }
  1542. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1543. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1544. post_dapm_off,
  1545. &wcd938x->mbhc->wcd_mbhc);
  1546. break;
  1547. };
  1548. dev_dbg(component->dev,
  1549. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1550. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1551. wcd938x->pullup_ref[micb_index]);
  1552. mutex_unlock(&wcd938x->micb_lock);
  1553. return 0;
  1554. }
  1555. EXPORT_SYMBOL(wcd938x_micbias_control);
  1556. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1557. {
  1558. int ret = 0;
  1559. uint8_t devnum = 0;
  1560. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1561. if (ret) {
  1562. dev_err(&swr_dev->dev,
  1563. "%s get devnum %d for dev addr %lx failed\n",
  1564. __func__, devnum, swr_dev->addr);
  1565. swr_remove_device(swr_dev);
  1566. return ret;
  1567. }
  1568. swr_dev->dev_num = devnum;
  1569. return 0;
  1570. }
  1571. static int wcd938x_event_notify(struct notifier_block *block,
  1572. unsigned long val,
  1573. void *data)
  1574. {
  1575. u16 event = (val & 0xffff);
  1576. int ret = 0;
  1577. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1578. struct snd_soc_component *component = wcd938x->component;
  1579. struct wcd_mbhc *mbhc;
  1580. switch (event) {
  1581. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1582. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1583. snd_soc_component_update_bits(component,
  1584. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1585. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1586. }
  1587. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1588. snd_soc_component_update_bits(component,
  1589. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1590. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1591. }
  1592. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1593. snd_soc_component_update_bits(component,
  1594. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1595. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1596. }
  1597. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1598. snd_soc_component_update_bits(component,
  1599. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1600. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1601. }
  1602. break;
  1603. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1604. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1605. 0xC0, 0x00);
  1606. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1607. 0x80, 0x00);
  1608. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1609. 0x80, 0x00);
  1610. break;
  1611. case BOLERO_WCD_EVT_SSR_DOWN:
  1612. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1613. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1614. wcd938x_reset_low(wcd938x->dev);
  1615. break;
  1616. case BOLERO_WCD_EVT_SSR_UP:
  1617. wcd938x_reset(wcd938x->dev);
  1618. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1619. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1620. wcd938x_init_reg(component);
  1621. regcache_mark_dirty(wcd938x->regmap);
  1622. regcache_sync(wcd938x->regmap);
  1623. /* Initialize MBHC module */
  1624. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1625. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1626. if (ret) {
  1627. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1628. __func__);
  1629. } else {
  1630. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1631. }
  1632. break;
  1633. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1634. snd_soc_component_update_bits(component,
  1635. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1636. ((val >> 0x10) << 0x01));
  1637. break;
  1638. default:
  1639. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1640. break;
  1641. }
  1642. return 0;
  1643. }
  1644. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1645. int event)
  1646. {
  1647. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1648. int micb_num;
  1649. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1650. __func__, w->name, event);
  1651. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1652. micb_num = MIC_BIAS_1;
  1653. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1654. micb_num = MIC_BIAS_2;
  1655. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1656. micb_num = MIC_BIAS_3;
  1657. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1658. micb_num = MIC_BIAS_4;
  1659. else
  1660. return -EINVAL;
  1661. switch (event) {
  1662. case SND_SOC_DAPM_PRE_PMU:
  1663. wcd938x_micbias_control(component, micb_num,
  1664. MICB_ENABLE, true);
  1665. break;
  1666. case SND_SOC_DAPM_POST_PMU:
  1667. /* 1 msec delay as per HW requirement */
  1668. usleep_range(1000, 1100);
  1669. break;
  1670. case SND_SOC_DAPM_POST_PMD:
  1671. wcd938x_micbias_control(component, micb_num,
  1672. MICB_DISABLE, true);
  1673. break;
  1674. };
  1675. return 0;
  1676. }
  1677. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1678. struct snd_kcontrol *kcontrol,
  1679. int event)
  1680. {
  1681. return __wcd938x_codec_enable_micbias(w, event);
  1682. }
  1683. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1684. int event)
  1685. {
  1686. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1687. int micb_num;
  1688. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1689. __func__, w->name, event);
  1690. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1691. micb_num = MIC_BIAS_1;
  1692. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1693. micb_num = MIC_BIAS_2;
  1694. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1695. micb_num = MIC_BIAS_3;
  1696. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1697. micb_num = MIC_BIAS_4;
  1698. else
  1699. return -EINVAL;
  1700. switch (event) {
  1701. case SND_SOC_DAPM_PRE_PMU:
  1702. wcd938x_micbias_control(component, micb_num,
  1703. MICB_PULLUP_ENABLE, true);
  1704. break;
  1705. case SND_SOC_DAPM_POST_PMU:
  1706. /* 1 msec delay as per HW requirement */
  1707. usleep_range(1000, 1100);
  1708. break;
  1709. case SND_SOC_DAPM_POST_PMD:
  1710. wcd938x_micbias_control(component, micb_num,
  1711. MICB_PULLUP_DISABLE, true);
  1712. break;
  1713. };
  1714. return 0;
  1715. }
  1716. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1717. struct snd_kcontrol *kcontrol,
  1718. int event)
  1719. {
  1720. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1721. }
  1722. static inline int wcd938x_tx_path_get(const char *wname,
  1723. unsigned int *path_num)
  1724. {
  1725. int ret = 0;
  1726. char *widget_name = NULL;
  1727. char *w_name = NULL;
  1728. char *path_num_char = NULL;
  1729. char *path_name = NULL;
  1730. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1731. if (!widget_name)
  1732. return -EINVAL;
  1733. w_name = widget_name;
  1734. path_name = strsep(&widget_name, " ");
  1735. if (!path_name) {
  1736. pr_err("%s: Invalid widget name = %s\n",
  1737. __func__, widget_name);
  1738. ret = -EINVAL;
  1739. goto err;
  1740. }
  1741. path_num_char = strpbrk(path_name, "0123");
  1742. if (!path_num_char) {
  1743. pr_err("%s: tx path index not found\n",
  1744. __func__);
  1745. ret = -EINVAL;
  1746. goto err;
  1747. }
  1748. ret = kstrtouint(path_num_char, 10, path_num);
  1749. if (ret < 0)
  1750. pr_err("%s: Invalid tx path = %s\n",
  1751. __func__, w_name);
  1752. err:
  1753. kfree(w_name);
  1754. return ret;
  1755. }
  1756. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. struct snd_soc_component *component =
  1760. snd_soc_kcontrol_component(kcontrol);
  1761. struct wcd938x_priv *wcd938x = NULL;
  1762. int ret = 0;
  1763. unsigned int path = 0;
  1764. if (!component)
  1765. return -EINVAL;
  1766. wcd938x = snd_soc_component_get_drvdata(component);
  1767. if (!wcd938x)
  1768. return -EINVAL;
  1769. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1770. if (ret < 0)
  1771. return ret;
  1772. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1773. return 0;
  1774. }
  1775. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1776. struct snd_ctl_elem_value *ucontrol)
  1777. {
  1778. struct snd_soc_component *component =
  1779. snd_soc_kcontrol_component(kcontrol);
  1780. struct wcd938x_priv *wcd938x = NULL;
  1781. u32 mode_val;
  1782. unsigned int path = 0;
  1783. int ret = 0;
  1784. if (!component)
  1785. return -EINVAL;
  1786. wcd938x = snd_soc_component_get_drvdata(component);
  1787. if (!wcd938x)
  1788. return -EINVAL;
  1789. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1790. if (ret)
  1791. return ret;
  1792. mode_val = ucontrol->value.enumerated.item[0];
  1793. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1794. wcd938x->tx_mode[path] = mode_val;
  1795. return 0;
  1796. }
  1797. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1798. struct snd_ctl_elem_value *ucontrol)
  1799. {
  1800. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1801. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1802. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1803. return 0;
  1804. }
  1805. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1806. struct snd_ctl_elem_value *ucontrol)
  1807. {
  1808. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1809. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1810. u32 mode_val;
  1811. mode_val = ucontrol->value.enumerated.item[0];
  1812. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1813. if (wcd938x->variant == WCD9380) {
  1814. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  1815. dev_info(component->dev,
  1816. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  1817. __func__);
  1818. mode_val = CLS_H_ULP;
  1819. }
  1820. }
  1821. if (mode_val == CLS_H_NORMAL) {
  1822. dev_info(component->dev,
  1823. "%s:Invalid HPH Mode, default to class_AB\n",
  1824. __func__);
  1825. mode_val = CLS_H_ULP;
  1826. }
  1827. wcd938x->hph_mode = mode_val;
  1828. return 0;
  1829. }
  1830. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1831. struct snd_ctl_elem_value *ucontrol)
  1832. {
  1833. struct snd_soc_component *component =
  1834. snd_soc_kcontrol_component(kcontrol);
  1835. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1836. bool hphr;
  1837. struct soc_multi_mixer_control *mc;
  1838. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1839. hphr = mc->shift;
  1840. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1841. wcd938x->comp1_enable;
  1842. return 0;
  1843. }
  1844. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1845. struct snd_ctl_elem_value *ucontrol)
  1846. {
  1847. struct snd_soc_component *component =
  1848. snd_soc_kcontrol_component(kcontrol);
  1849. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1850. int value = ucontrol->value.integer.value[0];
  1851. bool hphr;
  1852. struct soc_multi_mixer_control *mc;
  1853. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1854. hphr = mc->shift;
  1855. if (hphr)
  1856. wcd938x->comp2_enable = value;
  1857. else
  1858. wcd938x->comp1_enable = value;
  1859. return 0;
  1860. }
  1861. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  1862. struct snd_ctl_elem_value *ucontrol)
  1863. {
  1864. struct snd_soc_component *component =
  1865. snd_soc_kcontrol_component(kcontrol);
  1866. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1867. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  1868. return 0;
  1869. }
  1870. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  1871. struct snd_ctl_elem_value *ucontrol)
  1872. {
  1873. struct snd_soc_component *component =
  1874. snd_soc_kcontrol_component(kcontrol);
  1875. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1876. wcd938x->ldoh = ucontrol->value.integer.value[0];
  1877. return 0;
  1878. }
  1879. static const char * const tx_mode_mux_text_wcd9380[] = {
  1880. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1881. };
  1882. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1883. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1884. tx_mode_mux_text_wcd9380);
  1885. static const char * const tx_mode_mux_text[] = {
  1886. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1887. "ADC_ULP1", "ADC_ULP2",
  1888. };
  1889. static const struct soc_enum tx_mode_mux_enum =
  1890. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1891. tx_mode_mux_text);
  1892. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  1893. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  1894. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  1895. "CLS_AB_LOHIFI",
  1896. };
  1897. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  1898. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  1899. rx_hph_mode_mux_text_wcd9380);
  1900. static const char * const rx_hph_mode_mux_text[] = {
  1901. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1902. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  1903. };
  1904. static const struct soc_enum rx_hph_mode_mux_enum =
  1905. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1906. rx_hph_mode_mux_text);
  1907. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1908. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  1909. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1910. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1911. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1912. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1913. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1914. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1915. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1916. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1917. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1918. };
  1919. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1920. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1921. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1922. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1923. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1924. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1925. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1926. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1927. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1928. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1929. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1930. };
  1931. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1932. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1933. wcd938x_get_compander, wcd938x_set_compander),
  1934. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1935. wcd938x_get_compander, wcd938x_set_compander),
  1936. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  1937. wcd938x_ldoh_get, wcd938x_ldoh_put),
  1938. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1939. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1940. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1941. analog_gain),
  1942. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1943. analog_gain),
  1944. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1945. analog_gain),
  1946. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1947. analog_gain),
  1948. };
  1949. static const struct snd_kcontrol_new adc1_switch[] = {
  1950. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1951. };
  1952. static const struct snd_kcontrol_new adc2_switch[] = {
  1953. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1954. };
  1955. static const struct snd_kcontrol_new adc3_switch[] = {
  1956. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1957. };
  1958. static const struct snd_kcontrol_new adc4_switch[] = {
  1959. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1960. };
  1961. static const struct snd_kcontrol_new dmic1_switch[] = {
  1962. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1963. };
  1964. static const struct snd_kcontrol_new dmic2_switch[] = {
  1965. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1966. };
  1967. static const struct snd_kcontrol_new dmic3_switch[] = {
  1968. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1969. };
  1970. static const struct snd_kcontrol_new dmic4_switch[] = {
  1971. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1972. };
  1973. static const struct snd_kcontrol_new dmic5_switch[] = {
  1974. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1975. };
  1976. static const struct snd_kcontrol_new dmic6_switch[] = {
  1977. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1978. };
  1979. static const struct snd_kcontrol_new dmic7_switch[] = {
  1980. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1981. };
  1982. static const struct snd_kcontrol_new dmic8_switch[] = {
  1983. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1984. };
  1985. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1986. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1987. };
  1988. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1989. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1990. };
  1991. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1992. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1993. };
  1994. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1995. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1996. };
  1997. static const char * const adc2_mux_text[] = {
  1998. "INP2", "INP3"
  1999. };
  2000. static const struct soc_enum adc2_enum =
  2001. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2002. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2003. static const struct snd_kcontrol_new tx_adc2_mux =
  2004. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2005. static const char * const adc3_mux_text[] = {
  2006. "INP4", "INP6"
  2007. };
  2008. static const struct soc_enum adc3_enum =
  2009. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2010. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2011. static const struct snd_kcontrol_new tx_adc3_mux =
  2012. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2013. static const char * const adc4_mux_text[] = {
  2014. "INP5", "INP7"
  2015. };
  2016. static const struct soc_enum adc4_enum =
  2017. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2018. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2019. static const struct snd_kcontrol_new tx_adc4_mux =
  2020. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2021. static const char * const rdac3_mux_text[] = {
  2022. "RX1", "RX3"
  2023. };
  2024. static const char * const hdr12_mux_text[] = {
  2025. "NO_HDR12", "HDR12"
  2026. };
  2027. static const struct soc_enum hdr12_enum =
  2028. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2029. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2030. static const struct snd_kcontrol_new tx_hdr12_mux =
  2031. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2032. static const char * const hdr34_mux_text[] = {
  2033. "NO_HDR34", "HDR34"
  2034. };
  2035. static const struct soc_enum hdr34_enum =
  2036. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2037. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2038. static const struct snd_kcontrol_new tx_hdr34_mux =
  2039. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2040. static const struct soc_enum rdac3_enum =
  2041. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2042. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2043. static const struct snd_kcontrol_new rx_rdac3_mux =
  2044. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2045. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2046. /*input widgets*/
  2047. SND_SOC_DAPM_INPUT("AMIC1"),
  2048. SND_SOC_DAPM_INPUT("AMIC2"),
  2049. SND_SOC_DAPM_INPUT("AMIC3"),
  2050. SND_SOC_DAPM_INPUT("AMIC4"),
  2051. SND_SOC_DAPM_INPUT("AMIC5"),
  2052. SND_SOC_DAPM_INPUT("AMIC6"),
  2053. SND_SOC_DAPM_INPUT("AMIC7"),
  2054. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2055. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2056. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2057. /*tx widgets*/
  2058. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2059. wcd938x_codec_enable_adc,
  2060. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2061. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2062. wcd938x_codec_enable_adc,
  2063. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2064. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2065. wcd938x_codec_enable_adc,
  2066. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2067. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2068. wcd938x_codec_enable_adc,
  2069. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2070. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2071. wcd938x_codec_enable_dmic,
  2072. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2073. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2074. wcd938x_codec_enable_dmic,
  2075. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2076. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2077. wcd938x_codec_enable_dmic,
  2078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2079. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2080. wcd938x_codec_enable_dmic,
  2081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2082. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2083. wcd938x_codec_enable_dmic,
  2084. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2085. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2086. wcd938x_codec_enable_dmic,
  2087. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2088. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2089. wcd938x_codec_enable_dmic,
  2090. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2091. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2092. wcd938x_codec_enable_dmic,
  2093. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2094. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2095. NULL, 0, wcd938x_enable_req,
  2096. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2097. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2098. NULL, 0, wcd938x_enable_req,
  2099. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2100. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2101. NULL, 0, wcd938x_enable_req,
  2102. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2103. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2104. NULL, 0, wcd938x_enable_req,
  2105. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2106. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2107. &tx_adc2_mux),
  2108. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2109. &tx_adc3_mux),
  2110. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2111. &tx_adc4_mux),
  2112. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2113. &tx_hdr12_mux),
  2114. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2115. &tx_hdr34_mux),
  2116. /*tx mixers*/
  2117. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2118. adc1_switch, ARRAY_SIZE(adc1_switch),
  2119. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2120. SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2122. adc2_switch, ARRAY_SIZE(adc2_switch),
  2123. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2124. SND_SOC_DAPM_POST_PMD),
  2125. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2126. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2127. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2128. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2129. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2130. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2131. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2132. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2133. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2134. SND_SOC_DAPM_POST_PMD),
  2135. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2136. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2137. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2138. SND_SOC_DAPM_POST_PMD),
  2139. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2140. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2141. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2142. SND_SOC_DAPM_POST_PMD),
  2143. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2144. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2145. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2146. SND_SOC_DAPM_POST_PMD),
  2147. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2148. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2149. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2150. SND_SOC_DAPM_POST_PMD),
  2151. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2152. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2153. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2154. SND_SOC_DAPM_POST_PMD),
  2155. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2156. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2157. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2158. SND_SOC_DAPM_POST_PMD),
  2159. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2160. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2161. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2162. SND_SOC_DAPM_POST_PMD),
  2163. /* micbias widgets*/
  2164. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2165. wcd938x_codec_enable_micbias,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2167. SND_SOC_DAPM_POST_PMD),
  2168. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2169. wcd938x_codec_enable_micbias,
  2170. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2171. SND_SOC_DAPM_POST_PMD),
  2172. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2173. wcd938x_codec_enable_micbias,
  2174. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2175. SND_SOC_DAPM_POST_PMD),
  2176. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2177. wcd938x_codec_enable_micbias,
  2178. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2179. SND_SOC_DAPM_POST_PMD),
  2180. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2181. wcd938x_enable_clsh,
  2182. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2183. /*rx widgets*/
  2184. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2185. wcd938x_codec_enable_ear_pa,
  2186. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2187. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2188. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2189. wcd938x_codec_enable_aux_pa,
  2190. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2191. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2192. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2193. wcd938x_codec_enable_hphl_pa,
  2194. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2195. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2196. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2197. wcd938x_codec_enable_hphr_pa,
  2198. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2199. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2200. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2201. wcd938x_codec_hphl_dac_event,
  2202. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2203. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2204. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2205. wcd938x_codec_hphr_dac_event,
  2206. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2207. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2208. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2209. wcd938x_codec_ear_dac_event,
  2210. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2211. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2212. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2213. wcd938x_codec_aux_dac_event,
  2214. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2215. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2216. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2217. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2218. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2219. SND_SOC_DAPM_POST_PMD),
  2220. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2221. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2222. SND_SOC_DAPM_POST_PMD),
  2223. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2224. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2225. SND_SOC_DAPM_POST_PMD),
  2226. /* rx mixer widgets*/
  2227. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2228. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2229. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2230. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2231. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2232. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2233. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2234. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2235. /*output widgets tx*/
  2236. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2237. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2238. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2239. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2240. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2241. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2242. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2243. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2244. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2245. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2246. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2247. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2248. /*output widgets rx*/
  2249. SND_SOC_DAPM_OUTPUT("EAR"),
  2250. SND_SOC_DAPM_OUTPUT("AUX"),
  2251. SND_SOC_DAPM_OUTPUT("HPHL"),
  2252. SND_SOC_DAPM_OUTPUT("HPHR"),
  2253. /* micbias pull up widgets*/
  2254. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2255. wcd938x_codec_enable_micbias_pullup,
  2256. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2257. SND_SOC_DAPM_POST_PMD),
  2258. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2259. wcd938x_codec_enable_micbias_pullup,
  2260. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2261. SND_SOC_DAPM_POST_PMD),
  2262. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2263. wcd938x_codec_enable_micbias_pullup,
  2264. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2265. SND_SOC_DAPM_POST_PMD),
  2266. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2267. wcd938x_codec_enable_micbias_pullup,
  2268. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2269. SND_SOC_DAPM_POST_PMD),
  2270. };
  2271. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2272. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2273. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2274. {"ADC1 REQ", NULL, "ADC1"},
  2275. {"ADC1", NULL, "AMIC1"},
  2276. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2277. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2278. {"ADC2 REQ", NULL, "ADC2"},
  2279. {"ADC2", NULL, "HDR12 MUX"},
  2280. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2281. {"HDR12 MUX", "HDR12", "AMIC1"},
  2282. {"ADC2 MUX", "INP3", "AMIC3"},
  2283. {"ADC2 MUX", "INP2", "AMIC2"},
  2284. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2285. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2286. {"ADC3 REQ", NULL, "ADC3"},
  2287. {"ADC3", NULL, "HDR34 MUX"},
  2288. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2289. {"HDR34 MUX", "HDR34", "AMIC5"},
  2290. {"ADC3 MUX", "INP4", "AMIC4"},
  2291. {"ADC3 MUX", "INP6", "AMIC6"},
  2292. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2293. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2294. {"ADC4 REQ", NULL, "ADC4"},
  2295. {"ADC4", NULL, "ADC4 MUX"},
  2296. {"ADC4 MUX", "INP5", "AMIC5"},
  2297. {"ADC4 MUX", "INP7", "AMIC7"},
  2298. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2299. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2300. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2301. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2302. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2303. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2304. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2305. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2306. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2307. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2308. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2309. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2310. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2311. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2312. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2313. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2314. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2315. {"RX1", NULL, "IN1_HPHL"},
  2316. {"RDAC1", NULL, "RX1"},
  2317. {"HPHL_RDAC", "Switch", "RDAC1"},
  2318. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2319. {"HPHL", NULL, "HPHL PGA"},
  2320. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2321. {"RX2", NULL, "IN2_HPHR"},
  2322. {"RDAC2", NULL, "RX2"},
  2323. {"HPHR_RDAC", "Switch", "RDAC2"},
  2324. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2325. {"HPHR", NULL, "HPHR PGA"},
  2326. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2327. {"RX3", NULL, "IN3_AUX"},
  2328. {"RDAC4", NULL, "RX3"},
  2329. {"AUX_RDAC", "Switch", "RDAC4"},
  2330. {"AUX PGA", NULL, "AUX_RDAC"},
  2331. {"AUX", NULL, "AUX PGA"},
  2332. {"RDAC3_MUX", "RX3", "RX3"},
  2333. {"RDAC3_MUX", "RX1", "RX1"},
  2334. {"RDAC3", NULL, "RDAC3_MUX"},
  2335. {"EAR_RDAC", "Switch", "RDAC3"},
  2336. {"EAR PGA", NULL, "EAR_RDAC"},
  2337. {"EAR", NULL, "EAR PGA"},
  2338. };
  2339. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2340. void *file_private_data,
  2341. struct file *file,
  2342. char __user *buf, size_t count,
  2343. loff_t pos)
  2344. {
  2345. struct wcd938x_priv *priv;
  2346. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2347. int len = 0;
  2348. priv = (struct wcd938x_priv *) entry->private_data;
  2349. if (!priv) {
  2350. pr_err("%s: wcd938x priv is null\n", __func__);
  2351. return -EINVAL;
  2352. }
  2353. switch (priv->version) {
  2354. case WCD938X_VERSION_1_0:
  2355. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2356. break;
  2357. default:
  2358. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2359. }
  2360. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2361. }
  2362. static struct snd_info_entry_ops wcd938x_info_ops = {
  2363. .read = wcd938x_version_read,
  2364. };
  2365. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2366. void *file_private_data,
  2367. struct file *file,
  2368. char __user *buf, size_t count,
  2369. loff_t pos)
  2370. {
  2371. struct wcd938x_priv *priv;
  2372. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2373. int len = 0;
  2374. priv = (struct wcd938x_priv *) entry->private_data;
  2375. if (!priv) {
  2376. pr_err("%s: wcd938x priv is null\n", __func__);
  2377. return -EINVAL;
  2378. }
  2379. switch (priv->variant) {
  2380. case WCD9380:
  2381. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2382. break;
  2383. case WCD9385:
  2384. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2385. break;
  2386. default:
  2387. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2388. }
  2389. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2390. }
  2391. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2392. .read = wcd938x_variant_read,
  2393. };
  2394. /*
  2395. * wcd938x_get_codec_variant
  2396. * @component: component instance
  2397. *
  2398. * Return: codec variant or -EINVAL in error.
  2399. */
  2400. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2401. {
  2402. struct wcd938x_priv *priv = NULL;
  2403. if (!component)
  2404. return -EINVAL;
  2405. priv = snd_soc_component_get_drvdata(component);
  2406. if (!priv) {
  2407. dev_err(component->dev,
  2408. "%s:wcd938x not probed\n", __func__);
  2409. return 0;
  2410. }
  2411. return priv->variant;
  2412. }
  2413. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2414. /*
  2415. * wcd938x_info_create_codec_entry - creates wcd938x module
  2416. * @codec_root: The parent directory
  2417. * @component: component instance
  2418. *
  2419. * Creates wcd938x module, variant and version entry under the given
  2420. * parent directory.
  2421. *
  2422. * Return: 0 on success or negative error code on failure.
  2423. */
  2424. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2425. struct snd_soc_component *component)
  2426. {
  2427. struct snd_info_entry *version_entry;
  2428. struct snd_info_entry *variant_entry;
  2429. struct wcd938x_priv *priv;
  2430. struct snd_soc_card *card;
  2431. if (!codec_root || !component)
  2432. return -EINVAL;
  2433. priv = snd_soc_component_get_drvdata(component);
  2434. if (priv->entry) {
  2435. dev_dbg(priv->dev,
  2436. "%s:wcd938x module already created\n", __func__);
  2437. return 0;
  2438. }
  2439. card = component->card;
  2440. priv->entry = snd_info_create_subdir(codec_root->module,
  2441. "wcd938x", codec_root);
  2442. if (!priv->entry) {
  2443. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2444. __func__);
  2445. return -ENOMEM;
  2446. }
  2447. version_entry = snd_info_create_card_entry(card->snd_card,
  2448. "version",
  2449. priv->entry);
  2450. if (!version_entry) {
  2451. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2452. __func__);
  2453. return -ENOMEM;
  2454. }
  2455. version_entry->private_data = priv;
  2456. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2457. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2458. version_entry->c.ops = &wcd938x_info_ops;
  2459. if (snd_info_register(version_entry) < 0) {
  2460. snd_info_free_entry(version_entry);
  2461. return -ENOMEM;
  2462. }
  2463. priv->version_entry = version_entry;
  2464. variant_entry = snd_info_create_card_entry(card->snd_card,
  2465. "variant",
  2466. priv->entry);
  2467. if (!variant_entry) {
  2468. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2469. __func__);
  2470. return -ENOMEM;
  2471. }
  2472. variant_entry->private_data = priv;
  2473. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2474. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2475. variant_entry->c.ops = &wcd938x_variant_ops;
  2476. if (snd_info_register(variant_entry) < 0) {
  2477. snd_info_free_entry(variant_entry);
  2478. return -ENOMEM;
  2479. }
  2480. priv->variant_entry = variant_entry;
  2481. return 0;
  2482. }
  2483. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2484. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2485. {
  2486. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2487. struct snd_soc_dapm_context *dapm =
  2488. snd_soc_component_get_dapm(component);
  2489. int variant;
  2490. int ret = -EINVAL;
  2491. dev_info(component->dev, "%s()\n", __func__);
  2492. wcd938x = snd_soc_component_get_drvdata(component);
  2493. if (!wcd938x)
  2494. return -EINVAL;
  2495. wcd938x->component = component;
  2496. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2497. variant = (snd_soc_component_read32(component,
  2498. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2499. wcd938x->variant = variant;
  2500. wcd938x->fw_data = devm_kzalloc(component->dev,
  2501. sizeof(*(wcd938x->fw_data)),
  2502. GFP_KERNEL);
  2503. if (!wcd938x->fw_data) {
  2504. dev_err(component->dev, "Failed to allocate fw_data\n");
  2505. ret = -ENOMEM;
  2506. goto err;
  2507. }
  2508. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2509. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2510. WCD9XXX_CODEC_HWDEP_NODE, component);
  2511. if (ret < 0) {
  2512. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2513. goto err_hwdep;
  2514. }
  2515. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2516. if (ret) {
  2517. pr_err("%s: mbhc initialization failed\n", __func__);
  2518. goto err_hwdep;
  2519. }
  2520. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2521. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2522. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2523. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2524. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2525. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2526. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2527. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2528. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2529. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2530. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2531. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2532. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2533. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2534. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2535. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2536. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2537. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2538. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2539. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2540. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2541. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2542. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2543. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2544. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2545. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2546. snd_soc_dapm_sync(dapm);
  2547. wcd_cls_h_init(&wcd938x->clsh_info);
  2548. wcd938x_init_reg(component);
  2549. if (wcd938x->variant == WCD9380) {
  2550. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2551. ARRAY_SIZE(wcd9380_snd_controls));
  2552. if (ret < 0) {
  2553. dev_err(component->dev,
  2554. "%s: Failed to add snd ctrls for variant: %d\n",
  2555. __func__, wcd938x->variant);
  2556. goto err_hwdep;
  2557. }
  2558. }
  2559. if (wcd938x->variant == WCD9385) {
  2560. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2561. ARRAY_SIZE(wcd9385_snd_controls));
  2562. if (ret < 0) {
  2563. dev_err(component->dev,
  2564. "%s: Failed to add snd ctrls for variant: %d\n",
  2565. __func__, wcd938x->variant);
  2566. goto err_hwdep;
  2567. }
  2568. }
  2569. wcd938x->version = WCD938X_VERSION_1_0;
  2570. /* Register event notifier */
  2571. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2572. if (wcd938x->register_notifier) {
  2573. ret = wcd938x->register_notifier(wcd938x->handle,
  2574. &wcd938x->nblock,
  2575. true);
  2576. if (ret) {
  2577. dev_err(component->dev,
  2578. "%s: Failed to register notifier %d\n",
  2579. __func__, ret);
  2580. return ret;
  2581. }
  2582. }
  2583. return ret;
  2584. err_hwdep:
  2585. wcd938x->fw_data = NULL;
  2586. err:
  2587. return ret;
  2588. }
  2589. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2590. {
  2591. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2592. if (!wcd938x) {
  2593. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2594. __func__);
  2595. return;
  2596. }
  2597. if (wcd938x->register_notifier)
  2598. wcd938x->register_notifier(wcd938x->handle,
  2599. &wcd938x->nblock,
  2600. false);
  2601. }
  2602. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2603. .name = WCD938X_DRV_NAME,
  2604. .probe = wcd938x_soc_codec_probe,
  2605. .remove = wcd938x_soc_codec_remove,
  2606. .controls = wcd938x_snd_controls,
  2607. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2608. .dapm_widgets = wcd938x_dapm_widgets,
  2609. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2610. .dapm_routes = wcd938x_audio_map,
  2611. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2612. };
  2613. static int wcd938x_reset(struct device *dev)
  2614. {
  2615. struct wcd938x_priv *wcd938x = NULL;
  2616. int rc = 0;
  2617. int value = 0;
  2618. if (!dev)
  2619. return -ENODEV;
  2620. wcd938x = dev_get_drvdata(dev);
  2621. if (!wcd938x)
  2622. return -EINVAL;
  2623. if (!wcd938x->rst_np) {
  2624. dev_err(dev, "%s: reset gpio device node not specified\n",
  2625. __func__);
  2626. return -EINVAL;
  2627. }
  2628. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2629. if (value > 0)
  2630. return 0;
  2631. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2632. if (rc) {
  2633. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2634. __func__);
  2635. return rc;
  2636. }
  2637. /* 20us sleep required after pulling the reset gpio to LOW */
  2638. usleep_range(20, 30);
  2639. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2640. if (rc) {
  2641. dev_err(dev, "%s: wcd active state request fail!\n",
  2642. __func__);
  2643. return rc;
  2644. }
  2645. /* 20us sleep required after pulling the reset gpio to HIGH */
  2646. usleep_range(20, 30);
  2647. return rc;
  2648. }
  2649. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2650. u32 *val)
  2651. {
  2652. int rc = 0;
  2653. rc = of_property_read_u32(dev->of_node, name, val);
  2654. if (rc)
  2655. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2656. __func__, name, dev->of_node->full_name);
  2657. return rc;
  2658. }
  2659. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2660. struct wcd938x_micbias_setting *mb)
  2661. {
  2662. u32 prop_val = 0;
  2663. int rc = 0;
  2664. /* MB1 */
  2665. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2666. NULL)) {
  2667. rc = wcd938x_read_of_property_u32(dev,
  2668. "qcom,cdc-micbias1-mv",
  2669. &prop_val);
  2670. if (!rc)
  2671. mb->micb1_mv = prop_val;
  2672. } else {
  2673. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2674. __func__);
  2675. }
  2676. /* MB2 */
  2677. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2678. NULL)) {
  2679. rc = wcd938x_read_of_property_u32(dev,
  2680. "qcom,cdc-micbias2-mv",
  2681. &prop_val);
  2682. if (!rc)
  2683. mb->micb2_mv = prop_val;
  2684. } else {
  2685. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2686. __func__);
  2687. }
  2688. /* MB3 */
  2689. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2690. NULL)) {
  2691. rc = wcd938x_read_of_property_u32(dev,
  2692. "qcom,cdc-micbias3-mv",
  2693. &prop_val);
  2694. if (!rc)
  2695. mb->micb3_mv = prop_val;
  2696. } else {
  2697. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2698. __func__);
  2699. }
  2700. }
  2701. static int wcd938x_reset_low(struct device *dev)
  2702. {
  2703. struct wcd938x_priv *wcd938x = NULL;
  2704. int rc = 0;
  2705. if (!dev)
  2706. return -ENODEV;
  2707. wcd938x = dev_get_drvdata(dev);
  2708. if (!wcd938x)
  2709. return -EINVAL;
  2710. if (!wcd938x->rst_np) {
  2711. dev_err(dev, "%s: reset gpio device node not specified\n",
  2712. __func__);
  2713. return -EINVAL;
  2714. }
  2715. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2716. if (rc) {
  2717. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2718. __func__);
  2719. return rc;
  2720. }
  2721. /* 20us sleep required after pulling the reset gpio to LOW */
  2722. usleep_range(20, 30);
  2723. return rc;
  2724. }
  2725. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2726. {
  2727. struct wcd938x_pdata *pdata = NULL;
  2728. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2729. GFP_KERNEL);
  2730. if (!pdata)
  2731. return NULL;
  2732. pdata->rst_np = of_parse_phandle(dev->of_node,
  2733. "qcom,wcd-rst-gpio-node", 0);
  2734. if (!pdata->rst_np) {
  2735. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2736. __func__, "qcom,wcd-rst-gpio-node",
  2737. dev->of_node->full_name);
  2738. return NULL;
  2739. }
  2740. /* Parse power supplies */
  2741. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2742. &pdata->num_supplies);
  2743. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2744. dev_err(dev, "%s: no power supplies defined for codec\n",
  2745. __func__);
  2746. return NULL;
  2747. }
  2748. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2749. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2750. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2751. return pdata;
  2752. }
  2753. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2754. {
  2755. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2756. __func__, irq);
  2757. return IRQ_HANDLED;
  2758. }
  2759. static int wcd938x_bind(struct device *dev)
  2760. {
  2761. int ret = 0, i = 0;
  2762. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2763. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2764. /*
  2765. * Add 5msec delay to provide sufficient time for
  2766. * soundwire auto enumeration of slave devices as
  2767. * as per HW requirement.
  2768. */
  2769. usleep_range(5000, 5010);
  2770. ret = component_bind_all(dev, wcd938x);
  2771. if (ret) {
  2772. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2773. __func__, ret);
  2774. return ret;
  2775. }
  2776. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2777. if (!wcd938x->rx_swr_dev) {
  2778. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2779. __func__);
  2780. ret = -ENODEV;
  2781. goto err;
  2782. }
  2783. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2784. if (!wcd938x->tx_swr_dev) {
  2785. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2786. __func__);
  2787. ret = -ENODEV;
  2788. goto err;
  2789. }
  2790. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2791. &wcd938x_regmap_config);
  2792. if (!wcd938x->regmap) {
  2793. dev_err(dev, "%s: Regmap init failed\n",
  2794. __func__);
  2795. goto err;
  2796. }
  2797. /* Set all interupts as edge triggered */
  2798. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2799. regmap_write(wcd938x->regmap,
  2800. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2801. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2802. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2803. wcd938x->irq_info.codec_name = "WCD938X";
  2804. wcd938x->irq_info.regmap = wcd938x->regmap;
  2805. wcd938x->irq_info.dev = dev;
  2806. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2807. if (ret) {
  2808. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2809. __func__, ret);
  2810. goto err;
  2811. }
  2812. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2813. /* Request for watchdog interrupt */
  2814. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2815. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2816. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2817. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2818. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2819. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2820. /* Disable watchdog interrupt for HPH and AUX */
  2821. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2822. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2823. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2824. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2825. NULL, 0);
  2826. if (ret) {
  2827. dev_err(dev, "%s: Codec registration failed\n",
  2828. __func__);
  2829. goto err_irq;
  2830. }
  2831. return ret;
  2832. err_irq:
  2833. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2834. err:
  2835. component_unbind_all(dev, wcd938x);
  2836. return ret;
  2837. }
  2838. static void wcd938x_unbind(struct device *dev)
  2839. {
  2840. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2841. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  2842. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  2843. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  2844. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2845. snd_soc_unregister_component(dev);
  2846. component_unbind_all(dev, wcd938x);
  2847. }
  2848. static const struct of_device_id wcd938x_dt_match[] = {
  2849. { .compatible = "qcom,wcd938x-codec" },
  2850. {}
  2851. };
  2852. static const struct component_master_ops wcd938x_comp_ops = {
  2853. .bind = wcd938x_bind,
  2854. .unbind = wcd938x_unbind,
  2855. };
  2856. static int wcd938x_compare_of(struct device *dev, void *data)
  2857. {
  2858. return dev->of_node == data;
  2859. }
  2860. static void wcd938x_release_of(struct device *dev, void *data)
  2861. {
  2862. of_node_put(data);
  2863. }
  2864. static int wcd938x_add_slave_components(struct device *dev,
  2865. struct component_match **matchptr)
  2866. {
  2867. struct device_node *np, *rx_node, *tx_node;
  2868. np = dev->of_node;
  2869. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2870. if (!rx_node) {
  2871. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2872. return -ENODEV;
  2873. }
  2874. of_node_get(rx_node);
  2875. component_match_add_release(dev, matchptr,
  2876. wcd938x_release_of,
  2877. wcd938x_compare_of,
  2878. rx_node);
  2879. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2880. if (!tx_node) {
  2881. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2882. return -ENODEV;
  2883. }
  2884. of_node_get(tx_node);
  2885. component_match_add_release(dev, matchptr,
  2886. wcd938x_release_of,
  2887. wcd938x_compare_of,
  2888. tx_node);
  2889. return 0;
  2890. }
  2891. static int wcd938x_wakeup(void *handle, bool enable)
  2892. {
  2893. struct wcd938x_priv *priv;
  2894. if (!handle) {
  2895. pr_err("%s: NULL handle\n", __func__);
  2896. return -EINVAL;
  2897. }
  2898. priv = (struct wcd938x_priv *)handle;
  2899. if (!priv->tx_swr_dev) {
  2900. pr_err("%s: tx swr dev is NULL\n", __func__);
  2901. return -EINVAL;
  2902. }
  2903. if (enable)
  2904. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2905. else
  2906. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2907. }
  2908. static int wcd938x_probe(struct platform_device *pdev)
  2909. {
  2910. struct component_match *match = NULL;
  2911. struct wcd938x_priv *wcd938x = NULL;
  2912. struct wcd938x_pdata *pdata = NULL;
  2913. struct wcd_ctrl_platform_data *plat_data = NULL;
  2914. struct device *dev = &pdev->dev;
  2915. int ret;
  2916. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2917. GFP_KERNEL);
  2918. if (!wcd938x)
  2919. return -ENOMEM;
  2920. dev_set_drvdata(dev, wcd938x);
  2921. wcd938x->dev = dev;
  2922. pdata = wcd938x_populate_dt_data(dev);
  2923. if (!pdata) {
  2924. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2925. return -EINVAL;
  2926. }
  2927. dev->platform_data = pdata;
  2928. wcd938x->rst_np = pdata->rst_np;
  2929. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2930. pdata->regulator, pdata->num_supplies);
  2931. if (!wcd938x->supplies) {
  2932. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2933. __func__);
  2934. return ret;
  2935. }
  2936. plat_data = dev_get_platdata(dev->parent);
  2937. if (!plat_data) {
  2938. dev_err(dev, "%s: platform data from parent is NULL\n",
  2939. __func__);
  2940. return -EINVAL;
  2941. }
  2942. wcd938x->handle = (void *)plat_data->handle;
  2943. if (!wcd938x->handle) {
  2944. dev_err(dev, "%s: handle is NULL\n", __func__);
  2945. return -EINVAL;
  2946. }
  2947. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2948. if (!wcd938x->update_wcd_event) {
  2949. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2950. __func__);
  2951. return -EINVAL;
  2952. }
  2953. wcd938x->register_notifier = plat_data->register_notifier;
  2954. if (!wcd938x->register_notifier) {
  2955. dev_err(dev, "%s: register_notifier api is null!\n",
  2956. __func__);
  2957. return -EINVAL;
  2958. }
  2959. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2960. pdata->regulator,
  2961. pdata->num_supplies);
  2962. if (ret) {
  2963. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2964. __func__);
  2965. return ret;
  2966. }
  2967. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2968. CODEC_RX);
  2969. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2970. CODEC_TX);
  2971. if (ret) {
  2972. dev_err(dev, "Failed to read port mapping\n");
  2973. goto err;
  2974. }
  2975. mutex_init(&wcd938x->micb_lock);
  2976. ret = wcd938x_add_slave_components(dev, &match);
  2977. if (ret)
  2978. goto err_lock_init;
  2979. wcd938x_reset(dev);
  2980. wcd938x->wakeup = wcd938x_wakeup;
  2981. return component_master_add_with_match(dev,
  2982. &wcd938x_comp_ops, match);
  2983. err_lock_init:
  2984. mutex_destroy(&wcd938x->micb_lock);
  2985. err:
  2986. return ret;
  2987. }
  2988. static int wcd938x_remove(struct platform_device *pdev)
  2989. {
  2990. struct wcd938x_priv *wcd938x = NULL;
  2991. wcd938x = platform_get_drvdata(pdev);
  2992. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2993. mutex_destroy(&wcd938x->micb_lock);
  2994. dev_set_drvdata(&pdev->dev, NULL);
  2995. return 0;
  2996. }
  2997. #ifdef CONFIG_PM_SLEEP
  2998. static int wcd938x_suspend(struct device *dev)
  2999. {
  3000. return 0;
  3001. }
  3002. static int wcd938x_resume(struct device *dev)
  3003. {
  3004. return 0;
  3005. }
  3006. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3007. SET_SYSTEM_SLEEP_PM_OPS(
  3008. wcd938x_suspend,
  3009. wcd938x_resume
  3010. )
  3011. };
  3012. #endif
  3013. static struct platform_driver wcd938x_codec_driver = {
  3014. .probe = wcd938x_probe,
  3015. .remove = wcd938x_remove,
  3016. .driver = {
  3017. .name = "wcd938x_codec",
  3018. .owner = THIS_MODULE,
  3019. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3020. #ifdef CONFIG_PM_SLEEP
  3021. .pm = &wcd938x_dev_pm_ops,
  3022. #endif
  3023. .suppress_bind_attrs = true,
  3024. },
  3025. };
  3026. module_platform_driver(wcd938x_codec_driver);
  3027. MODULE_DESCRIPTION("WCD938X Codec driver");
  3028. MODULE_LICENSE("GPL v2");